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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 97.92 95.93 93.38 100.00 98.52 99.00 96.11


Total test records in report: 990
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T810 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1258577288 Jul 07 06:58:10 PM PDT 24 Jul 07 06:58:19 PM PDT 24 4309678084 ps
T811 /workspace/coverage/default/38.lc_ctrl_state_post_trans.544095210 Jul 07 06:58:04 PM PDT 24 Jul 07 06:58:12 PM PDT 24 281408123 ps
T812 /workspace/coverage/default/37.lc_ctrl_alert_test.1425723088 Jul 07 06:58:05 PM PDT 24 Jul 07 06:58:07 PM PDT 24 14691750 ps
T813 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.140860920 Jul 07 06:56:11 PM PDT 24 Jul 07 06:56:17 PM PDT 24 603230925 ps
T814 /workspace/coverage/default/19.lc_ctrl_jtag_errors.3435726959 Jul 07 06:56:29 PM PDT 24 Jul 07 06:57:23 PM PDT 24 15205712567 ps
T181 /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1302529252 Jul 07 06:52:41 PM PDT 24 Jul 07 06:54:48 PM PDT 24 6643617180 ps
T815 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4008840285 Jul 07 06:54:44 PM PDT 24 Jul 07 06:54:51 PM PDT 24 878582511 ps
T816 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1009011238 Jul 07 06:55:50 PM PDT 24 Jul 07 06:56:32 PM PDT 24 1847983050 ps
T817 /workspace/coverage/default/46.lc_ctrl_security_escalation.3704872064 Jul 07 06:58:46 PM PDT 24 Jul 07 06:58:58 PM PDT 24 1783998781 ps
T818 /workspace/coverage/default/19.lc_ctrl_prog_failure.1274018074 Jul 07 06:56:27 PM PDT 24 Jul 07 06:56:30 PM PDT 24 215316885 ps
T819 /workspace/coverage/default/26.lc_ctrl_state_failure.3052215158 Jul 07 06:57:07 PM PDT 24 Jul 07 06:57:39 PM PDT 24 266326252 ps
T820 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1182359334 Jul 07 06:55:06 PM PDT 24 Jul 07 06:55:13 PM PDT 24 448861958 ps
T821 /workspace/coverage/default/19.lc_ctrl_jtag_access.871582622 Jul 07 06:56:29 PM PDT 24 Jul 07 06:56:33 PM PDT 24 189902676 ps
T822 /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2959159517 Jul 07 06:58:19 PM PDT 24 Jul 07 06:58:33 PM PDT 24 705950147 ps
T823 /workspace/coverage/default/38.lc_ctrl_jtag_access.2159258079 Jul 07 06:58:09 PM PDT 24 Jul 07 06:58:15 PM PDT 24 694011761 ps
T824 /workspace/coverage/default/6.lc_ctrl_security_escalation.1999014134 Jul 07 06:54:25 PM PDT 24 Jul 07 06:54:34 PM PDT 24 167467231 ps
T825 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3562051766 Jul 07 06:56:34 PM PDT 24 Jul 07 06:56:54 PM PDT 24 1905845773 ps
T826 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1522582234 Jul 07 06:53:18 PM PDT 24 Jul 07 06:54:31 PM PDT 24 2055476488 ps
T827 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2567659627 Jul 07 06:55:43 PM PDT 24 Jul 07 06:55:49 PM PDT 24 1008337626 ps
T828 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1057107128 Jul 07 06:53:21 PM PDT 24 Jul 07 06:53:28 PM PDT 24 268856479 ps
T829 /workspace/coverage/default/8.lc_ctrl_state_post_trans.3399824065 Jul 07 06:54:55 PM PDT 24 Jul 07 06:55:02 PM PDT 24 81922026 ps
T830 /workspace/coverage/default/16.lc_ctrl_state_post_trans.948076771 Jul 07 06:56:05 PM PDT 24 Jul 07 06:56:13 PM PDT 24 142873060 ps
T831 /workspace/coverage/default/15.lc_ctrl_security_escalation.1698487188 Jul 07 06:55:58 PM PDT 24 Jul 07 06:56:10 PM PDT 24 349858678 ps
T832 /workspace/coverage/default/27.lc_ctrl_sec_mubi.3524909286 Jul 07 06:57:17 PM PDT 24 Jul 07 06:57:29 PM PDT 24 974299751 ps
T833 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1184395407 Jul 07 06:56:59 PM PDT 24 Jul 07 06:57:07 PM PDT 24 2604024624 ps
T834 /workspace/coverage/default/16.lc_ctrl_jtag_access.3721686142 Jul 07 06:56:07 PM PDT 24 Jul 07 06:56:27 PM PDT 24 803532961 ps
T835 /workspace/coverage/default/32.lc_ctrl_jtag_access.768505776 Jul 07 06:57:39 PM PDT 24 Jul 07 06:57:44 PM PDT 24 196202869 ps
T836 /workspace/coverage/default/28.lc_ctrl_errors.4058945156 Jul 07 06:57:20 PM PDT 24 Jul 07 06:57:36 PM PDT 24 433115362 ps
T837 /workspace/coverage/default/25.lc_ctrl_sec_mubi.1555172498 Jul 07 06:57:02 PM PDT 24 Jul 07 06:57:20 PM PDT 24 5729664841 ps
T838 /workspace/coverage/default/21.lc_ctrl_sec_mubi.1243294768 Jul 07 06:56:45 PM PDT 24 Jul 07 06:56:59 PM PDT 24 2150452066 ps
T839 /workspace/coverage/default/33.lc_ctrl_errors.2628270484 Jul 07 06:57:44 PM PDT 24 Jul 07 06:57:53 PM PDT 24 629417945 ps
T840 /workspace/coverage/default/23.lc_ctrl_security_escalation.1731075931 Jul 07 06:56:56 PM PDT 24 Jul 07 06:57:06 PM PDT 24 203753948 ps
T841 /workspace/coverage/default/45.lc_ctrl_state_post_trans.1485314681 Jul 07 06:58:37 PM PDT 24 Jul 07 06:58:45 PM PDT 24 80197061 ps
T842 /workspace/coverage/default/7.lc_ctrl_state_post_trans.3211619158 Jul 07 06:54:41 PM PDT 24 Jul 07 06:54:48 PM PDT 24 220523009 ps
T843 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3019145221 Jul 07 06:55:53 PM PDT 24 Jul 07 06:56:00 PM PDT 24 1370593055 ps
T844 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.4257704741 Jul 07 06:55:52 PM PDT 24 Jul 07 06:55:53 PM PDT 24 12368703 ps
T845 /workspace/coverage/default/22.lc_ctrl_security_escalation.3011265571 Jul 07 06:56:53 PM PDT 24 Jul 07 06:57:03 PM PDT 24 809198843 ps
T846 /workspace/coverage/default/5.lc_ctrl_state_failure.3865401879 Jul 07 06:54:08 PM PDT 24 Jul 07 06:54:34 PM PDT 24 589406617 ps
T847 /workspace/coverage/default/30.lc_ctrl_errors.1165781156 Jul 07 06:57:32 PM PDT 24 Jul 07 06:57:47 PM PDT 24 302301593 ps
T848 /workspace/coverage/default/34.lc_ctrl_prog_failure.4016935219 Jul 07 06:57:48 PM PDT 24 Jul 07 06:57:52 PM PDT 24 227222685 ps
T849 /workspace/coverage/default/4.lc_ctrl_state_failure.2060193870 Jul 07 06:53:51 PM PDT 24 Jul 07 06:54:17 PM PDT 24 851294829 ps
T850 /workspace/coverage/default/36.lc_ctrl_errors.2225675847 Jul 07 06:58:00 PM PDT 24 Jul 07 06:58:15 PM PDT 24 355964341 ps
T851 /workspace/coverage/default/10.lc_ctrl_stress_all.1239435815 Jul 07 06:55:18 PM PDT 24 Jul 07 06:59:22 PM PDT 24 13986117491 ps
T852 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.506883095 Jul 07 06:54:09 PM PDT 24 Jul 07 06:54:10 PM PDT 24 33955731 ps
T853 /workspace/coverage/default/48.lc_ctrl_security_escalation.3782447806 Jul 07 06:58:57 PM PDT 24 Jul 07 06:59:09 PM PDT 24 676141920 ps
T854 /workspace/coverage/default/29.lc_ctrl_security_escalation.2892028369 Jul 07 06:57:33 PM PDT 24 Jul 07 06:57:48 PM PDT 24 1779254470 ps
T855 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3111071518 Jul 07 06:54:18 PM PDT 24 Jul 07 06:54:35 PM PDT 24 2453348374 ps
T856 /workspace/coverage/default/43.lc_ctrl_jtag_access.2135434743 Jul 07 06:58:31 PM PDT 24 Jul 07 06:58:33 PM PDT 24 77961474 ps
T857 /workspace/coverage/default/24.lc_ctrl_jtag_access.291343844 Jul 07 06:57:00 PM PDT 24 Jul 07 06:57:01 PM PDT 24 61788648 ps
T858 /workspace/coverage/default/13.lc_ctrl_state_post_trans.1819558822 Jul 07 06:55:40 PM PDT 24 Jul 07 06:55:47 PM PDT 24 290267498 ps
T859 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3736014823 Jul 07 06:58:23 PM PDT 24 Jul 07 06:58:24 PM PDT 24 13358879 ps
T43 /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3375551451 Jul 07 06:58:20 PM PDT 24 Jul 07 07:04:00 PM PDT 24 14083809530 ps
T860 /workspace/coverage/default/25.lc_ctrl_state_failure.2371780014 Jul 07 06:57:02 PM PDT 24 Jul 07 06:57:28 PM PDT 24 221468228 ps
T861 /workspace/coverage/default/10.lc_ctrl_alert_test.5554178 Jul 07 06:55:19 PM PDT 24 Jul 07 06:55:20 PM PDT 24 83822670 ps
T862 /workspace/coverage/default/41.lc_ctrl_jtag_access.841300868 Jul 07 06:58:22 PM PDT 24 Jul 07 06:58:25 PM PDT 24 380204534 ps
T124 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4136949600 Jul 07 06:35:38 PM PDT 24 Jul 07 06:35:40 PM PDT 24 130013831 ps
T117 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2456013917 Jul 07 06:35:12 PM PDT 24 Jul 07 06:35:16 PM PDT 24 151456176 ps
T125 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.220890579 Jul 07 06:34:49 PM PDT 24 Jul 07 06:34:51 PM PDT 24 274110673 ps
T165 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1723307489 Jul 07 06:34:57 PM PDT 24 Jul 07 06:34:59 PM PDT 24 116189400 ps
T149 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3641198269 Jul 07 06:35:10 PM PDT 24 Jul 07 06:35:15 PM PDT 24 484357879 ps
T211 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2473571346 Jul 07 06:35:09 PM PDT 24 Jul 07 06:35:11 PM PDT 24 160054568 ps
T150 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.810707197 Jul 07 06:34:43 PM PDT 24 Jul 07 06:34:47 PM PDT 24 525533872 ps
T212 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2998863734 Jul 07 06:35:02 PM PDT 24 Jul 07 06:35:03 PM PDT 24 16948409 ps
T118 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2237631526 Jul 07 06:35:20 PM PDT 24 Jul 07 06:35:24 PM PDT 24 1423631780 ps
T863 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2086579954 Jul 07 06:34:54 PM PDT 24 Jul 07 06:34:55 PM PDT 24 26382192 ps
T213 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.523781007 Jul 07 06:35:22 PM PDT 24 Jul 07 06:35:23 PM PDT 24 11701560 ps
T119 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2566587510 Jul 07 06:35:32 PM PDT 24 Jul 07 06:35:33 PM PDT 24 48720875 ps
T166 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3719329999 Jul 07 06:35:14 PM PDT 24 Jul 07 06:35:16 PM PDT 24 43424362 ps
T121 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4145054473 Jul 07 06:35:03 PM PDT 24 Jul 07 06:35:05 PM PDT 24 169059418 ps
T167 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1399484019 Jul 07 06:35:18 PM PDT 24 Jul 07 06:35:20 PM PDT 24 30206214 ps
T147 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1364328023 Jul 07 06:35:19 PM PDT 24 Jul 07 06:35:26 PM PDT 24 2535788437 ps
T864 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2962096044 Jul 07 06:35:16 PM PDT 24 Jul 07 06:35:18 PM PDT 24 39300327 ps
T120 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2599636652 Jul 07 06:35:03 PM PDT 24 Jul 07 06:35:06 PM PDT 24 206960668 ps
T214 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3779274165 Jul 07 06:35:23 PM PDT 24 Jul 07 06:35:24 PM PDT 24 12529071 ps
T168 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4131786499 Jul 07 06:35:21 PM PDT 24 Jul 07 06:35:23 PM PDT 24 49523425 ps
T215 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.250269797 Jul 07 06:35:07 PM PDT 24 Jul 07 06:35:08 PM PDT 24 21137193 ps
T865 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2783207569 Jul 07 06:34:57 PM PDT 24 Jul 07 06:35:00 PM PDT 24 257429587 ps
T866 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2595790601 Jul 07 06:34:42 PM PDT 24 Jul 07 06:34:54 PM PDT 24 489749136 ps
T867 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.225473768 Jul 07 06:34:55 PM PDT 24 Jul 07 06:35:08 PM PDT 24 1996949072 ps
T868 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3809010119 Jul 07 06:35:27 PM PDT 24 Jul 07 06:35:28 PM PDT 24 21205628 ps
T198 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1132714494 Jul 07 06:35:14 PM PDT 24 Jul 07 06:35:15 PM PDT 24 21821071 ps
T869 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3304224401 Jul 07 06:35:02 PM PDT 24 Jul 07 06:35:04 PM PDT 24 44962473 ps
T169 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1120581445 Jul 07 06:34:45 PM PDT 24 Jul 07 06:34:46 PM PDT 24 55178545 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3319191771 Jul 07 06:34:47 PM PDT 24 Jul 07 06:34:49 PM PDT 24 84707608 ps
T123 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2461452199 Jul 07 06:35:34 PM PDT 24 Jul 07 06:35:36 PM PDT 24 142214671 ps
T871 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.396553130 Jul 07 06:35:31 PM PDT 24 Jul 07 06:35:32 PM PDT 24 83245119 ps
T138 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1088587995 Jul 07 06:35:01 PM PDT 24 Jul 07 06:35:03 PM PDT 24 28860804 ps
T129 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3195600128 Jul 07 06:35:27 PM PDT 24 Jul 07 06:35:28 PM PDT 24 127248040 ps
T136 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2173643982 Jul 07 06:35:28 PM PDT 24 Jul 07 06:35:31 PM PDT 24 75028892 ps
T148 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.957394493 Jul 07 06:35:06 PM PDT 24 Jul 07 06:35:09 PM PDT 24 151681496 ps
T872 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1810792745 Jul 07 06:35:05 PM PDT 24 Jul 07 06:35:07 PM PDT 24 44441460 ps
T139 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.241821661 Jul 07 06:35:21 PM PDT 24 Jul 07 06:35:24 PM PDT 24 67835069 ps
T873 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1900778406 Jul 07 06:35:29 PM PDT 24 Jul 07 06:35:31 PM PDT 24 50961787 ps
T874 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1770902826 Jul 07 06:35:26 PM PDT 24 Jul 07 06:35:28 PM PDT 24 44704274 ps
T122 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.616661360 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:36 PM PDT 24 417935555 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2402007339 Jul 07 06:34:47 PM PDT 24 Jul 07 06:34:48 PM PDT 24 34619828 ps
T876 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.271365759 Jul 07 06:35:00 PM PDT 24 Jul 07 06:35:01 PM PDT 24 15095327 ps
T877 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.298354652 Jul 07 06:35:19 PM PDT 24 Jul 07 06:35:20 PM PDT 24 50381665 ps
T199 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4154701979 Jul 07 06:35:35 PM PDT 24 Jul 07 06:35:37 PM PDT 24 87918207 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2673844362 Jul 07 06:35:10 PM PDT 24 Jul 07 06:35:11 PM PDT 24 226738261 ps
T879 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1328399843 Jul 07 06:35:15 PM PDT 24 Jul 07 06:35:34 PM PDT 24 3057020882 ps
T132 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.372458571 Jul 07 06:35:32 PM PDT 24 Jul 07 06:35:36 PM PDT 24 92744452 ps
T142 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1096811279 Jul 07 06:35:19 PM PDT 24 Jul 07 06:35:23 PM PDT 24 283486245 ps
T880 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2442749223 Jul 07 06:35:30 PM PDT 24 Jul 07 06:35:32 PM PDT 24 24923421 ps
T134 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.322998595 Jul 07 06:35:25 PM PDT 24 Jul 07 06:35:27 PM PDT 24 302116267 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.430075192 Jul 07 06:34:56 PM PDT 24 Jul 07 06:34:58 PM PDT 24 51541114 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3007530468 Jul 07 06:34:49 PM PDT 24 Jul 07 06:34:50 PM PDT 24 98952878 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.31793060 Jul 07 06:35:15 PM PDT 24 Jul 07 06:35:20 PM PDT 24 353963953 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1606957667 Jul 07 06:34:49 PM PDT 24 Jul 07 06:34:51 PM PDT 24 40854002 ps
T130 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3902722131 Jul 07 06:35:14 PM PDT 24 Jul 07 06:35:15 PM PDT 24 49920953 ps
T200 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3705977993 Jul 07 06:34:56 PM PDT 24 Jul 07 06:34:57 PM PDT 24 90757050 ps
T133 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1364863325 Jul 07 06:35:22 PM PDT 24 Jul 07 06:35:26 PM PDT 24 35273850 ps
T885 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1656071478 Jul 07 06:35:03 PM PDT 24 Jul 07 06:35:05 PM PDT 24 76003386 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1059211635 Jul 07 06:35:02 PM PDT 24 Jul 07 06:35:04 PM PDT 24 267476409 ps
T887 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2969912209 Jul 07 06:35:08 PM PDT 24 Jul 07 06:35:14 PM PDT 24 428689265 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1226434213 Jul 07 06:34:42 PM PDT 24 Jul 07 06:34:44 PM PDT 24 145323648 ps
T889 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4073692511 Jul 07 06:35:36 PM PDT 24 Jul 07 06:35:37 PM PDT 24 53118412 ps
T890 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2359859108 Jul 07 06:35:29 PM PDT 24 Jul 07 06:35:34 PM PDT 24 1372981897 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3913153300 Jul 07 06:35:16 PM PDT 24 Jul 07 06:35:20 PM PDT 24 688372117 ps
T126 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3634811123 Jul 07 06:35:29 PM PDT 24 Jul 07 06:35:33 PM PDT 24 118415595 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2903271887 Jul 07 06:34:59 PM PDT 24 Jul 07 06:35:01 PM PDT 24 48124422 ps
T893 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1515391440 Jul 07 06:35:32 PM PDT 24 Jul 07 06:35:34 PM PDT 24 24758029 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.730952723 Jul 07 06:34:54 PM PDT 24 Jul 07 06:34:55 PM PDT 24 38490810 ps
T895 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1157902649 Jul 07 06:35:07 PM PDT 24 Jul 07 06:35:08 PM PDT 24 48882006 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1216882427 Jul 07 06:34:50 PM PDT 24 Jul 07 06:34:52 PM PDT 24 258064981 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1654462744 Jul 07 06:34:54 PM PDT 24 Jul 07 06:35:01 PM PDT 24 879398713 ps
T898 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2370033014 Jul 07 06:35:03 PM PDT 24 Jul 07 06:35:18 PM PDT 24 1274438163 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3402121449 Jul 07 06:34:53 PM PDT 24 Jul 07 06:34:56 PM PDT 24 341140122 ps
T900 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4023782074 Jul 07 06:35:28 PM PDT 24 Jul 07 06:35:29 PM PDT 24 29744966 ps
T901 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2438800567 Jul 07 06:35:30 PM PDT 24 Jul 07 06:35:32 PM PDT 24 99879986 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4053385243 Jul 07 06:35:06 PM PDT 24 Jul 07 06:35:09 PM PDT 24 181180910 ps
T903 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.106966789 Jul 07 06:35:17 PM PDT 24 Jul 07 06:35:18 PM PDT 24 50602820 ps
T135 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4156977193 Jul 07 06:35:00 PM PDT 24 Jul 07 06:35:04 PM PDT 24 426410536 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2954019250 Jul 07 06:34:57 PM PDT 24 Jul 07 06:35:03 PM PDT 24 2348790851 ps
T905 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.774862734 Jul 07 06:35:22 PM PDT 24 Jul 07 06:35:25 PM PDT 24 86662846 ps
T906 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.248675125 Jul 07 06:35:15 PM PDT 24 Jul 07 06:35:18 PM PDT 24 241434768 ps
T140 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1795758165 Jul 07 06:35:06 PM PDT 24 Jul 07 06:35:10 PM PDT 24 2208326547 ps
T907 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3038731840 Jul 07 06:35:12 PM PDT 24 Jul 07 06:35:14 PM PDT 24 29714890 ps
T908 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3676502767 Jul 07 06:35:21 PM PDT 24 Jul 07 06:35:22 PM PDT 24 53490187 ps
T909 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.571952593 Jul 07 06:35:06 PM PDT 24 Jul 07 06:35:17 PM PDT 24 865606727 ps
T201 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4001602511 Jul 07 06:35:02 PM PDT 24 Jul 07 06:35:04 PM PDT 24 22372985 ps
T910 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1315310032 Jul 07 06:35:26 PM PDT 24 Jul 07 06:35:28 PM PDT 24 39312516 ps
T911 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1486214207 Jul 07 06:35:36 PM PDT 24 Jul 07 06:35:38 PM PDT 24 23095287 ps
T202 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3567623411 Jul 07 06:35:02 PM PDT 24 Jul 07 06:35:05 PM PDT 24 366441273 ps
T912 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3804557200 Jul 07 06:35:26 PM PDT 24 Jul 07 06:35:28 PM PDT 24 17879201 ps
T913 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2998979509 Jul 07 06:35:13 PM PDT 24 Jul 07 06:35:15 PM PDT 24 53376430 ps
T143 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2087628448 Jul 07 06:34:53 PM PDT 24 Jul 07 06:34:56 PM PDT 24 70377313 ps
T914 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.544874446 Jul 07 06:35:04 PM PDT 24 Jul 07 06:35:07 PM PDT 24 742480945 ps
T915 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1124343504 Jul 07 06:35:08 PM PDT 24 Jul 07 06:35:18 PM PDT 24 803951735 ps
T203 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2552918359 Jul 07 06:35:36 PM PDT 24 Jul 07 06:35:37 PM PDT 24 13873394 ps
T916 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3576792946 Jul 07 06:35:09 PM PDT 24 Jul 07 06:35:10 PM PDT 24 71841732 ps
T917 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4072483039 Jul 07 06:35:31 PM PDT 24 Jul 07 06:35:33 PM PDT 24 22976837 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2086753181 Jul 07 06:35:05 PM PDT 24 Jul 07 06:35:10 PM PDT 24 785542409 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2784987980 Jul 07 06:34:58 PM PDT 24 Jul 07 06:34:59 PM PDT 24 157684755 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3621491137 Jul 07 06:34:59 PM PDT 24 Jul 07 06:35:03 PM PDT 24 871590394 ps
T921 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.95784985 Jul 07 06:35:03 PM PDT 24 Jul 07 06:35:05 PM PDT 24 47403315 ps
T922 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2253179211 Jul 07 06:35:08 PM PDT 24 Jul 07 06:35:10 PM PDT 24 122668160 ps
T923 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.341030868 Jul 07 06:34:57 PM PDT 24 Jul 07 06:35:03 PM PDT 24 493655033 ps
T204 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2231946313 Jul 07 06:35:10 PM PDT 24 Jul 07 06:35:12 PM PDT 24 104741521 ps
T141 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1227745684 Jul 07 06:34:45 PM PDT 24 Jul 07 06:34:48 PM PDT 24 81093893 ps
T127 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1918337550 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:36 PM PDT 24 304848304 ps
T924 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.332354768 Jul 07 06:34:59 PM PDT 24 Jul 07 06:35:01 PM PDT 24 73976705 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.355252259 Jul 07 06:34:44 PM PDT 24 Jul 07 06:34:48 PM PDT 24 95672441 ps
T926 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3112959254 Jul 07 06:35:17 PM PDT 24 Jul 07 06:35:19 PM PDT 24 188283833 ps
T927 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2031600946 Jul 07 06:34:53 PM PDT 24 Jul 07 06:34:54 PM PDT 24 37169632 ps
T928 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1518382404 Jul 07 06:35:22 PM PDT 24 Jul 07 06:35:23 PM PDT 24 92559918 ps
T929 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.939344797 Jul 07 06:35:16 PM PDT 24 Jul 07 06:35:19 PM PDT 24 43140897 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.540953334 Jul 07 06:34:52 PM PDT 24 Jul 07 06:34:54 PM PDT 24 66921632 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2166285431 Jul 07 06:35:01 PM PDT 24 Jul 07 06:35:03 PM PDT 24 1279275039 ps
T932 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.230945817 Jul 07 06:35:02 PM PDT 24 Jul 07 06:35:04 PM PDT 24 89300519 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1414167629 Jul 07 06:35:21 PM PDT 24 Jul 07 06:35:23 PM PDT 24 56390773 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1505281333 Jul 07 06:34:42 PM PDT 24 Jul 07 06:34:46 PM PDT 24 415910448 ps
T935 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2689896817 Jul 07 06:35:29 PM PDT 24 Jul 07 06:35:33 PM PDT 24 191708340 ps
T936 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1531041532 Jul 07 06:34:59 PM PDT 24 Jul 07 06:35:01 PM PDT 24 73275937 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1626094553 Jul 07 06:35:07 PM PDT 24 Jul 07 06:35:08 PM PDT 24 29696976 ps
T938 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1297895250 Jul 07 06:35:35 PM PDT 24 Jul 07 06:35:39 PM PDT 24 277743902 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2671622614 Jul 07 06:35:19 PM PDT 24 Jul 07 06:35:25 PM PDT 24 516426148 ps
T940 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1535350841 Jul 07 06:35:32 PM PDT 24 Jul 07 06:35:33 PM PDT 24 52177471 ps
T941 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2495318165 Jul 07 06:35:22 PM PDT 24 Jul 07 06:35:24 PM PDT 24 87141909 ps
T942 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1438374982 Jul 07 06:35:13 PM PDT 24 Jul 07 06:35:25 PM PDT 24 489196295 ps
T943 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3362753098 Jul 07 06:34:57 PM PDT 24 Jul 07 06:34:58 PM PDT 24 30224880 ps
T146 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3557867989 Jul 07 06:35:23 PM PDT 24 Jul 07 06:35:25 PM PDT 24 74515610 ps
T205 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2938658996 Jul 07 06:35:01 PM PDT 24 Jul 07 06:35:02 PM PDT 24 21967900 ps
T944 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.954012957 Jul 07 06:35:20 PM PDT 24 Jul 07 06:35:22 PM PDT 24 175115619 ps
T945 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1459133218 Jul 07 06:35:20 PM PDT 24 Jul 07 06:35:31 PM PDT 24 351194201 ps
T946 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.484453948 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:34 PM PDT 24 24680066 ps
T128 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1805879976 Jul 07 06:35:30 PM PDT 24 Jul 07 06:35:33 PM PDT 24 104728220 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1624518881 Jul 07 06:34:46 PM PDT 24 Jul 07 06:34:48 PM PDT 24 61642558 ps
T144 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2104404056 Jul 07 06:35:25 PM PDT 24 Jul 07 06:35:29 PM PDT 24 383323222 ps
T948 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1546141701 Jul 07 06:35:22 PM PDT 24 Jul 07 06:35:24 PM PDT 24 205390321 ps
T949 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.76991806 Jul 07 06:35:18 PM PDT 24 Jul 07 06:35:19 PM PDT 24 104020334 ps
T950 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3365831665 Jul 07 06:35:21 PM PDT 24 Jul 07 06:35:24 PM PDT 24 98806522 ps
T951 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4147630261 Jul 07 06:35:27 PM PDT 24 Jul 07 06:35:28 PM PDT 24 223533039 ps
T952 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3036885296 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:35 PM PDT 24 351328967 ps
T953 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3544072742 Jul 07 06:34:43 PM PDT 24 Jul 07 06:34:44 PM PDT 24 102252347 ps
T954 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1352514093 Jul 07 06:35:36 PM PDT 24 Jul 07 06:35:39 PM PDT 24 70788796 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2002910034 Jul 07 06:35:02 PM PDT 24 Jul 07 06:35:04 PM PDT 24 518378802 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1559552358 Jul 07 06:34:48 PM PDT 24 Jul 07 06:34:50 PM PDT 24 30527649 ps
T957 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1147003010 Jul 07 06:35:06 PM PDT 24 Jul 07 06:35:32 PM PDT 24 4673216145 ps
T958 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3106796861 Jul 07 06:35:00 PM PDT 24 Jul 07 06:35:01 PM PDT 24 16648545 ps
T959 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3859624618 Jul 07 06:34:55 PM PDT 24 Jul 07 06:34:58 PM PDT 24 693376029 ps
T960 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.569460406 Jul 07 06:35:24 PM PDT 24 Jul 07 06:35:27 PM PDT 24 41751075 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1128745976 Jul 07 06:35:19 PM PDT 24 Jul 07 06:35:20 PM PDT 24 52958094 ps
T145 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3808283732 Jul 07 06:35:29 PM PDT 24 Jul 07 06:35:31 PM PDT 24 114408781 ps
T962 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2914029637 Jul 07 06:34:56 PM PDT 24 Jul 07 06:34:58 PM PDT 24 244505006 ps
T963 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.513502813 Jul 07 06:35:30 PM PDT 24 Jul 07 06:35:33 PM PDT 24 52019801 ps
T206 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2513829876 Jul 07 06:35:01 PM PDT 24 Jul 07 06:35:03 PM PDT 24 16288081 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.860629431 Jul 07 06:35:14 PM PDT 24 Jul 07 06:35:15 PM PDT 24 17492252 ps
T965 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.659670362 Jul 07 06:35:22 PM PDT 24 Jul 07 06:35:23 PM PDT 24 27661440 ps
T966 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3335620518 Jul 07 06:34:51 PM PDT 24 Jul 07 06:34:54 PM PDT 24 202878456 ps
T207 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1608337392 Jul 07 06:34:53 PM PDT 24 Jul 07 06:34:54 PM PDT 24 40611328 ps
T967 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1036934812 Jul 07 06:34:54 PM PDT 24 Jul 07 06:34:55 PM PDT 24 331786855 ps
T968 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.926111246 Jul 07 06:35:13 PM PDT 24 Jul 07 06:35:15 PM PDT 24 661096525 ps
T137 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.899823722 Jul 07 06:35:18 PM PDT 24 Jul 07 06:35:20 PM PDT 24 92066294 ps
T969 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2492072897 Jul 07 06:35:24 PM PDT 24 Jul 07 06:35:25 PM PDT 24 63404212 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1198299231 Jul 07 06:34:50 PM PDT 24 Jul 07 06:34:52 PM PDT 24 65324064 ps
T971 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1441442021 Jul 07 06:34:55 PM PDT 24 Jul 07 06:34:57 PM PDT 24 65315031 ps
T972 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2424814826 Jul 07 06:34:49 PM PDT 24 Jul 07 06:34:58 PM PDT 24 3202963950 ps
T208 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2786728454 Jul 07 06:34:46 PM PDT 24 Jul 07 06:34:47 PM PDT 24 41494371 ps
T973 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1938779858 Jul 07 06:34:59 PM PDT 24 Jul 07 06:35:01 PM PDT 24 45923488 ps
T974 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2457986438 Jul 07 06:35:20 PM PDT 24 Jul 07 06:35:22 PM PDT 24 57829400 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3886329619 Jul 07 06:34:50 PM PDT 24 Jul 07 06:34:53 PM PDT 24 203497342 ps
T976 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1525487059 Jul 07 06:34:58 PM PDT 24 Jul 07 06:35:01 PM PDT 24 555701838 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2382803813 Jul 07 06:35:02 PM PDT 24 Jul 07 06:35:06 PM PDT 24 164175705 ps
T209 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2910134380 Jul 07 06:35:07 PM PDT 24 Jul 07 06:35:08 PM PDT 24 19727177 ps
T978 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2520150516 Jul 07 06:35:30 PM PDT 24 Jul 07 06:35:31 PM PDT 24 35255334 ps
T979 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1068165377 Jul 07 06:35:26 PM PDT 24 Jul 07 06:35:27 PM PDT 24 16230818 ps
T980 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1048909769 Jul 07 06:35:00 PM PDT 24 Jul 07 06:35:35 PM PDT 24 4420917276 ps
T210 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.698845811 Jul 07 06:35:23 PM PDT 24 Jul 07 06:35:24 PM PDT 24 71823596 ps
T981 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1276828484 Jul 07 06:35:28 PM PDT 24 Jul 07 06:35:29 PM PDT 24 37990667 ps
T982 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.574819011 Jul 07 06:35:03 PM PDT 24 Jul 07 06:35:06 PM PDT 24 72661745 ps
T983 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2915178505 Jul 07 06:34:59 PM PDT 24 Jul 07 06:35:02 PM PDT 24 417592894 ps
T984 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2542217216 Jul 07 06:34:57 PM PDT 24 Jul 07 06:34:59 PM PDT 24 34990875 ps
T131 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1108995871 Jul 07 06:35:32 PM PDT 24 Jul 07 06:35:36 PM PDT 24 105669995 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3940673817 Jul 07 06:34:56 PM PDT 24 Jul 07 06:34:59 PM PDT 24 1108447102 ps
T986 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3511911979 Jul 07 06:35:31 PM PDT 24 Jul 07 06:35:33 PM PDT 24 68033444 ps
T987 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3802742035 Jul 07 06:35:00 PM PDT 24 Jul 07 06:35:02 PM PDT 24 380056748 ps
T988 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2903662470 Jul 07 06:34:53 PM PDT 24 Jul 07 06:34:55 PM PDT 24 87507447 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3450227618 Jul 07 06:35:21 PM PDT 24 Jul 07 06:35:24 PM PDT 24 65431477 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1469250157 Jul 07 06:35:10 PM PDT 24 Jul 07 06:35:15 PM PDT 24 148811793 ps

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.669171544
Short name T3
Test name
Test status
Simulation time 322934100 ps
CPU time 10.63 seconds
Started Jul 07 06:56:01 PM PDT 24
Finished Jul 07 06:56:11 PM PDT 24
Peak memory 226004 kb
Host smart-060e0468-0595-4a59-a9cd-112ce175b293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669171544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.669171544
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.492229371
Short name T29
Test name
Test status
Simulation time 17851618546 ps
CPU time 682.49 seconds
Started Jul 07 06:55:03 PM PDT 24
Finished Jul 07 07:06:25 PM PDT 24
Peak memory 422148 kb
Host smart-985bdcee-12a1-4d71-96b8-e1506a79c9d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=492229371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.492229371
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3851136188
Short name T24
Test name
Test status
Simulation time 4326752157 ps
CPU time 11.46 seconds
Started Jul 07 06:53:36 PM PDT 24
Finished Jul 07 06:53:47 PM PDT 24
Peak memory 226092 kb
Host smart-da17a9a2-1e23-4ecd-99fe-ce0b57451387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851136188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3851136188
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4242133932
Short name T16
Test name
Test status
Simulation time 6630925812 ps
CPU time 148.1 seconds
Started Jul 07 06:57:43 PM PDT 24
Finished Jul 07 07:00:11 PM PDT 24
Peak memory 276916 kb
Host smart-fddf86fe-e9f4-4f28-b6bc-f01269fc3b48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242133932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4242133932
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1404229476
Short name T48
Test name
Test status
Simulation time 2082415015 ps
CPU time 11.13 seconds
Started Jul 07 06:57:59 PM PDT 24
Finished Jul 07 06:58:10 PM PDT 24
Peak memory 226040 kb
Host smart-c13e2b76-7352-4d72-8bb8-70e3624df116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404229476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1404229476
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2237631526
Short name T118
Test name
Test status
Simulation time 1423631780 ps
CPU time 3.7 seconds
Started Jul 07 06:35:20 PM PDT 24
Finished Jul 07 06:35:24 PM PDT 24
Peak memory 218648 kb
Host smart-d5a6a16f-fa79-4363-891d-8d08a45d599b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223763
1526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2237631526
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3585220844
Short name T54
Test name
Test status
Simulation time 2163424170 ps
CPU time 11.93 seconds
Started Jul 07 06:58:09 PM PDT 24
Finished Jul 07 06:58:22 PM PDT 24
Peak memory 226084 kb
Host smart-28eaffd0-3262-4ab2-b8f6-cb3e2046fca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585220844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3585220844
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2662289419
Short name T49
Test name
Test status
Simulation time 273661917 ps
CPU time 26.87 seconds
Started Jul 07 06:52:43 PM PDT 24
Finished Jul 07 06:53:10 PM PDT 24
Peak memory 268904 kb
Host smart-affda52b-bfe3-4a89-b107-a0ce7a21287d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662289419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2662289419
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.4233429037
Short name T38
Test name
Test status
Simulation time 89258596512 ps
CPU time 1723.76 seconds
Started Jul 07 06:57:43 PM PDT 24
Finished Jul 07 07:26:27 PM PDT 24
Peak memory 529704 kb
Host smart-76a9600d-0511-40b9-8594-9615a75db011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4233429037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.4233429037
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2456013917
Short name T117
Test name
Test status
Simulation time 151456176 ps
CPU time 3.51 seconds
Started Jul 07 06:35:12 PM PDT 24
Finished Jul 07 06:35:16 PM PDT 24
Peak memory 217556 kb
Host smart-36e38f66-47d3-4cc5-a89e-836576a2a04e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456013917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2456013917
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.6863557
Short name T81
Test name
Test status
Simulation time 67957674 ps
CPU time 0.89 seconds
Started Jul 07 06:58:25 PM PDT 24
Finished Jul 07 06:58:27 PM PDT 24
Peak memory 208972 kb
Host smart-86819c8c-e28b-46df-b921-06c4e6b4da25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6863557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.6863557
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1685866098
Short name T4
Test name
Test status
Simulation time 1924705818 ps
CPU time 4.24 seconds
Started Jul 07 06:57:36 PM PDT 24
Finished Jul 07 06:57:40 PM PDT 24
Peak memory 217668 kb
Host smart-ab6f3441-f3b8-4a1a-b9d0-e3da3807c65f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685866098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1685866098
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4154701979
Short name T199
Test name
Test status
Simulation time 87918207 ps
CPU time 0.84 seconds
Started Jul 07 06:35:35 PM PDT 24
Finished Jul 07 06:35:37 PM PDT 24
Peak memory 209196 kb
Host smart-ec456ac8-e372-4680-91e4-538b42e2b826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154701979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4154701979
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2599636652
Short name T120
Test name
Test status
Simulation time 206960668 ps
CPU time 3.36 seconds
Started Jul 07 06:35:03 PM PDT 24
Finished Jul 07 06:35:06 PM PDT 24
Peak memory 218576 kb
Host smart-edf7f8dc-5a3c-4e5f-93b9-45afece4c4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599636652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2599636652
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3133201894
Short name T37
Test name
Test status
Simulation time 1772090562 ps
CPU time 10.35 seconds
Started Jul 07 06:58:23 PM PDT 24
Finished Jul 07 06:58:33 PM PDT 24
Peak memory 218596 kb
Host smart-c426c7e3-54fe-4d91-b7c9-085e379c36f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133201894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3133201894
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2768928059
Short name T27
Test name
Test status
Simulation time 17033664316 ps
CPU time 109.81 seconds
Started Jul 07 06:56:42 PM PDT 24
Finished Jul 07 06:58:32 PM PDT 24
Peak memory 283860 kb
Host smart-51aceed6-ed59-4311-ab16-b051656942fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768928059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2768928059
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4156977193
Short name T135
Test name
Test status
Simulation time 426410536 ps
CPU time 3.96 seconds
Started Jul 07 06:35:00 PM PDT 24
Finished Jul 07 06:35:04 PM PDT 24
Peak memory 217604 kb
Host smart-27f0d83b-7422-4111-a654-f59f881cb8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156977193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.4156977193
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.899823722
Short name T137
Test name
Test status
Simulation time 92066294 ps
CPU time 1.92 seconds
Started Jul 07 06:35:18 PM PDT 24
Finished Jul 07 06:35:20 PM PDT 24
Peak memory 221436 kb
Host smart-6c6f409f-1e0c-451e-87f6-6ec377baae30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899823722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.899823722
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.4200090974
Short name T221
Test name
Test status
Simulation time 475316429 ps
CPU time 13.8 seconds
Started Jul 07 06:54:50 PM PDT 24
Finished Jul 07 06:55:04 PM PDT 24
Peak memory 226052 kb
Host smart-10def983-3551-44d2-8526-be532cb9433b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200090974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.4200090974
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1986291144
Short name T114
Test name
Test status
Simulation time 763148861 ps
CPU time 24.02 seconds
Started Jul 07 06:55:49 PM PDT 24
Finished Jul 07 06:56:13 PM PDT 24
Peak memory 250976 kb
Host smart-6b5d5a83-2781-43f5-bec9-76aa5a0583bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986291144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1986291144
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.322998595
Short name T134
Test name
Test status
Simulation time 302116267 ps
CPU time 1.73 seconds
Started Jul 07 06:35:25 PM PDT 24
Finished Jul 07 06:35:27 PM PDT 24
Peak memory 212980 kb
Host smart-579106e0-b164-4c15-bd64-fb2b5588680b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322998595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.322998595
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2104404056
Short name T144
Test name
Test status
Simulation time 383323222 ps
CPU time 3.95 seconds
Started Jul 07 06:35:25 PM PDT 24
Finished Jul 07 06:35:29 PM PDT 24
Peak memory 217536 kb
Host smart-6277957f-dd16-4e00-a8e3-b153b391fa62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104404056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2104404056
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4145054473
Short name T121
Test name
Test status
Simulation time 169059418 ps
CPU time 1.92 seconds
Started Jul 07 06:35:03 PM PDT 24
Finished Jul 07 06:35:05 PM PDT 24
Peak memory 221092 kb
Host smart-6ec10c71-ff45-456f-b385-ff60c6aee6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145054473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4145054473
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3515059589
Short name T23
Test name
Test status
Simulation time 38548135 ps
CPU time 0.87 seconds
Started Jul 07 06:55:57 PM PDT 24
Finished Jul 07 06:55:58 PM PDT 24
Peak memory 211924 kb
Host smart-2897a2fb-d0a5-4739-9143-7a7658c5a0cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515059589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3515059589
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.220890579
Short name T125
Test name
Test status
Simulation time 274110673 ps
CPU time 1.37 seconds
Started Jul 07 06:34:49 PM PDT 24
Finished Jul 07 06:34:51 PM PDT 24
Peak memory 217556 kb
Host smart-a9875d61-88a5-4e22-b4a9-3320f1d6cde7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220890579 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.220890579
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2976373457
Short name T75
Test name
Test status
Simulation time 45560847486 ps
CPU time 929.25 seconds
Started Jul 07 06:56:34 PM PDT 24
Finished Jul 07 07:12:03 PM PDT 24
Peak memory 528760 kb
Host smart-bbb67dcf-e91c-4732-8a7f-b25c205fd216
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2976373457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2976373457
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2137914289
Short name T94
Test name
Test status
Simulation time 38409208736 ps
CPU time 186.38 seconds
Started Jul 07 06:54:03 PM PDT 24
Finished Jul 07 06:57:10 PM PDT 24
Peak memory 275892 kb
Host smart-264bf27b-d539-48dd-9106-6d5084c58b5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2137914289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2137914289
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1227745684
Short name T141
Test name
Test status
Simulation time 81093893 ps
CPU time 2.25 seconds
Started Jul 07 06:34:45 PM PDT 24
Finished Jul 07 06:34:48 PM PDT 24
Peak memory 221964 kb
Host smart-9e6ec1b1-72fd-4e5f-9ccc-196e4d97ff69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227745684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1227745684
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.616661360
Short name T122
Test name
Test status
Simulation time 417935555 ps
CPU time 2.87 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 222328 kb
Host smart-850a575f-ae9d-4244-b2df-978ea8527b6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616661360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.616661360
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3302622886
Short name T216
Test name
Test status
Simulation time 83185875 ps
CPU time 0.88 seconds
Started Jul 07 06:52:20 PM PDT 24
Finished Jul 07 06:52:21 PM PDT 24
Peak memory 208800 kb
Host smart-a45722e8-b978-4a6f-a88f-04ce05776fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302622886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3302622886
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.506867168
Short name T343
Test name
Test status
Simulation time 3155025800 ps
CPU time 8.76 seconds
Started Jul 07 06:55:27 PM PDT 24
Finished Jul 07 06:55:36 PM PDT 24
Peak memory 226076 kb
Host smart-c7529b2d-c63e-4239-bf31-5bc95d202a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506867168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.506867168
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.431359728
Short name T218
Test name
Test status
Simulation time 11748173 ps
CPU time 0.98 seconds
Started Jul 07 06:53:52 PM PDT 24
Finished Jul 07 06:53:54 PM PDT 24
Peak memory 208972 kb
Host smart-c0efcb67-8c06-4597-be4b-1829ffd81cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431359728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.431359728
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2375233842
Short name T69
Test name
Test status
Simulation time 74657655 ps
CPU time 0.89 seconds
Started Jul 07 06:55:00 PM PDT 24
Finished Jul 07 06:55:01 PM PDT 24
Peak memory 208856 kb
Host smart-0ab32c31-0ad6-4326-ab4f-25acab1a6dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375233842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2375233842
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3808283732
Short name T145
Test name
Test status
Simulation time 114408781 ps
CPU time 1.92 seconds
Started Jul 07 06:35:29 PM PDT 24
Finished Jul 07 06:35:31 PM PDT 24
Peak memory 221688 kb
Host smart-0c2122e8-3771-4f60-a557-e86c01b7a3e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808283732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3808283732
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3634811123
Short name T126
Test name
Test status
Simulation time 118415595 ps
CPU time 4.11 seconds
Started Jul 07 06:35:29 PM PDT 24
Finished Jul 07 06:35:33 PM PDT 24
Peak memory 217532 kb
Host smart-ee8f0ca6-d1d0-4be0-a2c1-dc892ba3062a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634811123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3634811123
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1918337550
Short name T127
Test name
Test status
Simulation time 304848304 ps
CPU time 2.77 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 222300 kb
Host smart-21ad8ba3-83f9-4569-9fa2-336725ac02b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918337550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1918337550
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1108995871
Short name T131
Test name
Test status
Simulation time 105669995 ps
CPU time 3.07 seconds
Started Jul 07 06:35:32 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 222280 kb
Host smart-16439986-0215-4d61-8f52-4c630eace281
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108995871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1108995871
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3375551451
Short name T43
Test name
Test status
Simulation time 14083809530 ps
CPU time 340.21 seconds
Started Jul 07 06:58:20 PM PDT 24
Finished Jul 07 07:04:00 PM PDT 24
Peak memory 373012 kb
Host smart-e96323ce-15f0-4241-84fd-40b60b87463f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3375551451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3375551451
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3112368554
Short name T11
Test name
Test status
Simulation time 781631331 ps
CPU time 7.22 seconds
Started Jul 07 06:53:51 PM PDT 24
Finished Jul 07 06:53:59 PM PDT 24
Peak memory 217712 kb
Host smart-c3ab008a-87a6-4052-a3cc-daf0cbae835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112368554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3112368554
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2908178521
Short name T1
Test name
Test status
Simulation time 1353014430 ps
CPU time 8.33 seconds
Started Jul 07 06:52:46 PM PDT 24
Finished Jul 07 06:52:55 PM PDT 24
Peak memory 251004 kb
Host smart-ca981f9e-bc81-408b-a25e-44cb39b1b8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908178521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2908178521
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1606957667
Short name T884
Test name
Test status
Simulation time 40854002 ps
CPU time 1.86 seconds
Started Jul 07 06:34:49 PM PDT 24
Finished Jul 07 06:34:51 PM PDT 24
Peak memory 209344 kb
Host smart-7ef0f8ec-f12b-4e88-b4ed-021e7d74c2ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606957667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1606957667
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1559552358
Short name T956
Test name
Test status
Simulation time 30527649 ps
CPU time 1.59 seconds
Started Jul 07 06:34:48 PM PDT 24
Finished Jul 07 06:34:50 PM PDT 24
Peak memory 217472 kb
Host smart-af0d35a9-0c75-4a5f-863e-bf153782cddd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559552358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1559552358
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2786728454
Short name T208
Test name
Test status
Simulation time 41494371 ps
CPU time 1.02 seconds
Started Jul 07 06:34:46 PM PDT 24
Finished Jul 07 06:34:47 PM PDT 24
Peak memory 210444 kb
Host smart-b7db80b1-193b-474e-a854-c448ee5d761e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786728454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2786728454
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3007530468
Short name T882
Test name
Test status
Simulation time 98952878 ps
CPU time 1.32 seconds
Started Jul 07 06:34:49 PM PDT 24
Finished Jul 07 06:34:50 PM PDT 24
Peak memory 217736 kb
Host smart-b7e5796c-7703-4b22-9c06-c5f7c24cc47c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007530468 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3007530468
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2402007339
Short name T875
Test name
Test status
Simulation time 34619828 ps
CPU time 0.83 seconds
Started Jul 07 06:34:47 PM PDT 24
Finished Jul 07 06:34:48 PM PDT 24
Peak memory 209336 kb
Host smart-f8082c2d-6bf1-4957-8599-f1ab280bc178
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402007339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2402007339
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1624518881
Short name T947
Test name
Test status
Simulation time 61642558 ps
CPU time 1.38 seconds
Started Jul 07 06:34:46 PM PDT 24
Finished Jul 07 06:34:48 PM PDT 24
Peak memory 209172 kb
Host smart-facf6acc-9987-48af-91c8-3461baebe01a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624518881 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1624518881
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.810707197
Short name T150
Test name
Test status
Simulation time 525533872 ps
CPU time 3.76 seconds
Started Jul 07 06:34:43 PM PDT 24
Finished Jul 07 06:34:47 PM PDT 24
Peak memory 209028 kb
Host smart-07259c60-5bca-463e-925c-5fa7269f4b8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810707197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.810707197
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2595790601
Short name T866
Test name
Test status
Simulation time 489749136 ps
CPU time 11.64 seconds
Started Jul 07 06:34:42 PM PDT 24
Finished Jul 07 06:34:54 PM PDT 24
Peak memory 209240 kb
Host smart-69055cb3-b0d4-4ece-bd69-d033e287ae03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595790601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2595790601
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3544072742
Short name T953
Test name
Test status
Simulation time 102252347 ps
CPU time 1.54 seconds
Started Jul 07 06:34:43 PM PDT 24
Finished Jul 07 06:34:44 PM PDT 24
Peak memory 210740 kb
Host smart-377a01a4-2b1a-4d58-8b84-650597c48055
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544072742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3544072742
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1505281333
Short name T934
Test name
Test status
Simulation time 415910448 ps
CPU time 3.3 seconds
Started Jul 07 06:34:42 PM PDT 24
Finished Jul 07 06:34:46 PM PDT 24
Peak memory 218624 kb
Host smart-b1b877e0-1562-47f7-b8f9-b724d1e10dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150528
1333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1505281333
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1226434213
Short name T888
Test name
Test status
Simulation time 145323648 ps
CPU time 1.18 seconds
Started Jul 07 06:34:42 PM PDT 24
Finished Jul 07 06:34:44 PM PDT 24
Peak memory 209276 kb
Host smart-3cf1040c-df83-4cd3-94cd-215c8cd2ae08
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226434213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1226434213
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1120581445
Short name T169
Test name
Test status
Simulation time 55178545 ps
CPU time 1.14 seconds
Started Jul 07 06:34:45 PM PDT 24
Finished Jul 07 06:34:46 PM PDT 24
Peak memory 209336 kb
Host smart-9fb11a2b-0748-48b1-af1e-1bd918211254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120581445 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1120581445
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3319191771
Short name T870
Test name
Test status
Simulation time 84707608 ps
CPU time 1.82 seconds
Started Jul 07 06:34:47 PM PDT 24
Finished Jul 07 06:34:49 PM PDT 24
Peak memory 211432 kb
Host smart-3d2aad18-5944-47f0-a53e-ef7129b71cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319191771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3319191771
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.355252259
Short name T925
Test name
Test status
Simulation time 95672441 ps
CPU time 4.2 seconds
Started Jul 07 06:34:44 PM PDT 24
Finished Jul 07 06:34:48 PM PDT 24
Peak memory 217476 kb
Host smart-61683929-22c8-4541-acf4-2efb617fe7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355252259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.355252259
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1059211635
Short name T886
Test name
Test status
Simulation time 267476409 ps
CPU time 1.31 seconds
Started Jul 07 06:35:02 PM PDT 24
Finished Jul 07 06:35:04 PM PDT 24
Peak memory 209312 kb
Host smart-6a09ee29-c16c-4854-9328-67fe45e7247d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059211635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1059211635
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1036934812
Short name T967
Test name
Test status
Simulation time 331786855 ps
CPU time 1.26 seconds
Started Jul 07 06:34:54 PM PDT 24
Finished Jul 07 06:34:55 PM PDT 24
Peak memory 208920 kb
Host smart-4df1a47d-8939-4b3f-bd7c-8bf87edc1db9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036934812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1036934812
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1608337392
Short name T207
Test name
Test status
Simulation time 40611328 ps
CPU time 0.88 seconds
Started Jul 07 06:34:53 PM PDT 24
Finished Jul 07 06:34:54 PM PDT 24
Peak memory 209620 kb
Host smart-b350b343-a733-47fe-8d5c-a19e7a9e916d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608337392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1608337392
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2542217216
Short name T984
Test name
Test status
Simulation time 34990875 ps
CPU time 0.99 seconds
Started Jul 07 06:34:57 PM PDT 24
Finished Jul 07 06:34:59 PM PDT 24
Peak memory 217640 kb
Host smart-d2f2c48e-b3b0-41bf-b114-c19e8d929fe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542217216 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2542217216
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.730952723
Short name T894
Test name
Test status
Simulation time 38490810 ps
CPU time 0.83 seconds
Started Jul 07 06:34:54 PM PDT 24
Finished Jul 07 06:34:55 PM PDT 24
Peak memory 209224 kb
Host smart-3e3e4f90-9c28-40d0-b1c0-c1fcb41c0bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730952723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.730952723
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1441442021
Short name T971
Test name
Test status
Simulation time 65315031 ps
CPU time 2.22 seconds
Started Jul 07 06:34:55 PM PDT 24
Finished Jul 07 06:34:57 PM PDT 24
Peak memory 209176 kb
Host smart-7b45c6ff-79d5-4af7-9714-58d6cf4cee4a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441442021 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1441442021
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1654462744
Short name T897
Test name
Test status
Simulation time 879398713 ps
CPU time 6.29 seconds
Started Jul 07 06:34:54 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 209000 kb
Host smart-69ea0120-979a-4405-b6d5-f44a43f861c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654462744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1654462744
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2424814826
Short name T972
Test name
Test status
Simulation time 3202963950 ps
CPU time 8.3 seconds
Started Jul 07 06:34:49 PM PDT 24
Finished Jul 07 06:34:58 PM PDT 24
Peak memory 209468 kb
Host smart-5ff9eb50-b6d7-40d6-96a9-b72edef342c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424814826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2424814826
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1216882427
Short name T896
Test name
Test status
Simulation time 258064981 ps
CPU time 1.36 seconds
Started Jul 07 06:34:50 PM PDT 24
Finished Jul 07 06:34:52 PM PDT 24
Peak memory 210700 kb
Host smart-e42aeb83-3985-4c0a-a2a0-3033884f2eca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216882427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1216882427
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3886329619
Short name T975
Test name
Test status
Simulation time 203497342 ps
CPU time 2.24 seconds
Started Jul 07 06:34:50 PM PDT 24
Finished Jul 07 06:34:53 PM PDT 24
Peak memory 217764 kb
Host smart-226a7aed-2550-40d0-8a46-4fcdc7e51d66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388632
9619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3886329619
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1198299231
Short name T970
Test name
Test status
Simulation time 65324064 ps
CPU time 1.46 seconds
Started Jul 07 06:34:50 PM PDT 24
Finished Jul 07 06:34:52 PM PDT 24
Peak memory 209272 kb
Host smart-c76ed026-2289-4ee6-a49c-6a7e6e30cc53
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198299231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1198299231
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1723307489
Short name T165
Test name
Test status
Simulation time 116189400 ps
CPU time 1.44 seconds
Started Jul 07 06:34:57 PM PDT 24
Finished Jul 07 06:34:59 PM PDT 24
Peak memory 211348 kb
Host smart-bf0b8b5e-47bb-46d6-aaa4-65b11fb7c792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723307489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1723307489
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3335620518
Short name T966
Test name
Test status
Simulation time 202878456 ps
CPU time 2.89 seconds
Started Jul 07 06:34:51 PM PDT 24
Finished Jul 07 06:34:54 PM PDT 24
Peak memory 217456 kb
Host smart-04dcb728-6693-4d7b-9a3d-9f46d4625843
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335620518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3335620518
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2087628448
Short name T143
Test name
Test status
Simulation time 70377313 ps
CPU time 2.85 seconds
Started Jul 07 06:34:53 PM PDT 24
Finished Jul 07 06:34:56 PM PDT 24
Peak memory 217520 kb
Host smart-98fcfc8d-c4c4-4fd7-a5ab-bf7222c82004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087628448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2087628448
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1546141701
Short name T948
Test name
Test status
Simulation time 205390321 ps
CPU time 1.19 seconds
Started Jul 07 06:35:22 PM PDT 24
Finished Jul 07 06:35:24 PM PDT 24
Peak memory 217616 kb
Host smart-0a422baa-8f96-4f76-a57b-1657b35c4752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546141701 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1546141701
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3779274165
Short name T214
Test name
Test status
Simulation time 12529071 ps
CPU time 0.89 seconds
Started Jul 07 06:35:23 PM PDT 24
Finished Jul 07 06:35:24 PM PDT 24
Peak memory 208972 kb
Host smart-e11d5312-3e94-48b5-aa87-93bb04500815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779274165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3779274165
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.659670362
Short name T965
Test name
Test status
Simulation time 27661440 ps
CPU time 1.14 seconds
Started Jul 07 06:35:22 PM PDT 24
Finished Jul 07 06:35:23 PM PDT 24
Peak memory 209400 kb
Host smart-9715e04b-a68b-45b4-bdf8-144c2f943b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659670362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.659670362
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1315310032
Short name T910
Test name
Test status
Simulation time 39312516 ps
CPU time 2.22 seconds
Started Jul 07 06:35:26 PM PDT 24
Finished Jul 07 06:35:28 PM PDT 24
Peak memory 217556 kb
Host smart-17b0e628-d625-4e78-96cc-757c4068d9db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315310032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1315310032
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2492072897
Short name T969
Test name
Test status
Simulation time 63404212 ps
CPU time 1.03 seconds
Started Jul 07 06:35:24 PM PDT 24
Finished Jul 07 06:35:25 PM PDT 24
Peak memory 217664 kb
Host smart-e00fd7b3-f55b-493a-b329-afa966f080b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492072897 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2492072897
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.523781007
Short name T213
Test name
Test status
Simulation time 11701560 ps
CPU time 0.86 seconds
Started Jul 07 06:35:22 PM PDT 24
Finished Jul 07 06:35:23 PM PDT 24
Peak memory 209292 kb
Host smart-7cf651c0-4e3e-4ab1-a6c4-35f8d609ef85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523781007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.523781007
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4131786499
Short name T168
Test name
Test status
Simulation time 49523425 ps
CPU time 1.4 seconds
Started Jul 07 06:35:21 PM PDT 24
Finished Jul 07 06:35:23 PM PDT 24
Peak memory 209428 kb
Host smart-5082cfab-3a83-4d71-a3ed-69023402f575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131786499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.4131786499
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3365831665
Short name T950
Test name
Test status
Simulation time 98806522 ps
CPU time 2.57 seconds
Started Jul 07 06:35:21 PM PDT 24
Finished Jul 07 06:35:24 PM PDT 24
Peak memory 217500 kb
Host smart-7531474b-39eb-46dc-9ab0-f9042512a00a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365831665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3365831665
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.774862734
Short name T905
Test name
Test status
Simulation time 86662846 ps
CPU time 2.15 seconds
Started Jul 07 06:35:22 PM PDT 24
Finished Jul 07 06:35:25 PM PDT 24
Peak memory 212772 kb
Host smart-0da46826-5912-4f66-bf2f-eee4fa683773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774862734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.774862734
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3195600128
Short name T129
Test name
Test status
Simulation time 127248040 ps
CPU time 1.23 seconds
Started Jul 07 06:35:27 PM PDT 24
Finished Jul 07 06:35:28 PM PDT 24
Peak memory 217728 kb
Host smart-bf8aaf33-c2da-41c1-9ba8-33b7210a03f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195600128 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3195600128
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1276828484
Short name T981
Test name
Test status
Simulation time 37990667 ps
CPU time 0.95 seconds
Started Jul 07 06:35:28 PM PDT 24
Finished Jul 07 06:35:29 PM PDT 24
Peak memory 209344 kb
Host smart-3ac1a9e9-da8e-4274-a998-db63769e5aee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276828484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1276828484
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4147630261
Short name T951
Test name
Test status
Simulation time 223533039 ps
CPU time 1.03 seconds
Started Jul 07 06:35:27 PM PDT 24
Finished Jul 07 06:35:28 PM PDT 24
Peak memory 209464 kb
Host smart-14c92fcf-5da0-4aac-a0c6-3393908887a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147630261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4147630261
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.569460406
Short name T960
Test name
Test status
Simulation time 41751075 ps
CPU time 3.02 seconds
Started Jul 07 06:35:24 PM PDT 24
Finished Jul 07 06:35:27 PM PDT 24
Peak memory 217512 kb
Host smart-6e465315-8888-4d96-b0b6-2ec9c3e99364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569460406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.569460406
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1068165377
Short name T979
Test name
Test status
Simulation time 16230818 ps
CPU time 1.02 seconds
Started Jul 07 06:35:26 PM PDT 24
Finished Jul 07 06:35:27 PM PDT 24
Peak memory 217604 kb
Host smart-0098239c-331e-4df4-a56d-c8dfa4d2a552
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068165377 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1068165377
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3809010119
Short name T868
Test name
Test status
Simulation time 21205628 ps
CPU time 0.84 seconds
Started Jul 07 06:35:27 PM PDT 24
Finished Jul 07 06:35:28 PM PDT 24
Peak memory 209292 kb
Host smart-081d89fd-da1d-4cbf-9cca-a58558536364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809010119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3809010119
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3804557200
Short name T912
Test name
Test status
Simulation time 17879201 ps
CPU time 1.22 seconds
Started Jul 07 06:35:26 PM PDT 24
Finished Jul 07 06:35:28 PM PDT 24
Peak memory 209384 kb
Host smart-54d0b701-b686-4264-86e8-1391fe85f8a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804557200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3804557200
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.513502813
Short name T963
Test name
Test status
Simulation time 52019801 ps
CPU time 2.48 seconds
Started Jul 07 06:35:30 PM PDT 24
Finished Jul 07 06:35:33 PM PDT 24
Peak memory 217480 kb
Host smart-bb9bc3f2-c298-45a6-9c6b-9acce4aefb2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513502813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.513502813
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2442749223
Short name T880
Test name
Test status
Simulation time 24923421 ps
CPU time 1.35 seconds
Started Jul 07 06:35:30 PM PDT 24
Finished Jul 07 06:35:32 PM PDT 24
Peak memory 217716 kb
Host smart-5a2ffe84-4e73-42a6-b2af-bdf6c24786c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442749223 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2442749223
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4073692511
Short name T889
Test name
Test status
Simulation time 53118412 ps
CPU time 0.77 seconds
Started Jul 07 06:35:36 PM PDT 24
Finished Jul 07 06:35:37 PM PDT 24
Peak memory 209188 kb
Host smart-c6559c05-6968-4d8b-9c1c-1efe1eeb743e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073692511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4073692511
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.396553130
Short name T871
Test name
Test status
Simulation time 83245119 ps
CPU time 1.07 seconds
Started Jul 07 06:35:31 PM PDT 24
Finished Jul 07 06:35:32 PM PDT 24
Peak memory 209360 kb
Host smart-03e9f152-3fdf-45a8-949e-b3d4ff162c84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396553130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.396553130
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2173643982
Short name T136
Test name
Test status
Simulation time 75028892 ps
CPU time 2.21 seconds
Started Jul 07 06:35:28 PM PDT 24
Finished Jul 07 06:35:31 PM PDT 24
Peak memory 217484 kb
Host smart-5ab546d0-e1d0-4265-8aad-d7bb291136ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173643982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2173643982
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4072483039
Short name T917
Test name
Test status
Simulation time 22976837 ps
CPU time 1.39 seconds
Started Jul 07 06:35:31 PM PDT 24
Finished Jul 07 06:35:33 PM PDT 24
Peak memory 220548 kb
Host smart-c55b1a24-1fec-47a0-bdf2-38bce414086f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072483039 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.4072483039
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2552918359
Short name T203
Test name
Test status
Simulation time 13873394 ps
CPU time 0.86 seconds
Started Jul 07 06:35:36 PM PDT 24
Finished Jul 07 06:35:37 PM PDT 24
Peak memory 209360 kb
Host smart-a6f1ba52-aef2-411a-80a2-1982fdcc7932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552918359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2552918359
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1900778406
Short name T873
Test name
Test status
Simulation time 50961787 ps
CPU time 2 seconds
Started Jul 07 06:35:29 PM PDT 24
Finished Jul 07 06:35:31 PM PDT 24
Peak memory 217536 kb
Host smart-7c025947-db44-4b3c-ba32-0b894949186c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900778406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1900778406
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2689896817
Short name T935
Test name
Test status
Simulation time 191708340 ps
CPU time 4.04 seconds
Started Jul 07 06:35:29 PM PDT 24
Finished Jul 07 06:35:33 PM PDT 24
Peak memory 217484 kb
Host smart-64a1e7f6-a8e9-46ec-ad7d-dfd4e19c0d29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689896817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2689896817
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4023782074
Short name T900
Test name
Test status
Simulation time 29744966 ps
CPU time 1.29 seconds
Started Jul 07 06:35:28 PM PDT 24
Finished Jul 07 06:35:29 PM PDT 24
Peak memory 217744 kb
Host smart-ad1f7599-0fc3-41fe-8381-047d0de3764a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023782074 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4023782074
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2520150516
Short name T978
Test name
Test status
Simulation time 35255334 ps
CPU time 0.94 seconds
Started Jul 07 06:35:30 PM PDT 24
Finished Jul 07 06:35:31 PM PDT 24
Peak memory 209004 kb
Host smart-92a07fcc-87cb-40d6-b6a0-5ee0f8e1ea32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520150516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2520150516
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1486214207
Short name T911
Test name
Test status
Simulation time 23095287 ps
CPU time 1.5 seconds
Started Jul 07 06:35:36 PM PDT 24
Finished Jul 07 06:35:38 PM PDT 24
Peak memory 217584 kb
Host smart-a2055891-b2db-4555-a672-4f18a806d67b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486214207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1486214207
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1297895250
Short name T938
Test name
Test status
Simulation time 277743902 ps
CPU time 3.23 seconds
Started Jul 07 06:35:35 PM PDT 24
Finished Jul 07 06:35:39 PM PDT 24
Peak memory 217564 kb
Host smart-2e9c8631-7504-4579-91ad-6c8faba623ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297895250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1297895250
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1805879976
Short name T128
Test name
Test status
Simulation time 104728220 ps
CPU time 2.32 seconds
Started Jul 07 06:35:30 PM PDT 24
Finished Jul 07 06:35:33 PM PDT 24
Peak memory 221776 kb
Host smart-08af88a2-4285-4f62-abe4-8ae69afab2d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805879976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1805879976
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2438800567
Short name T901
Test name
Test status
Simulation time 99879986 ps
CPU time 1.37 seconds
Started Jul 07 06:35:30 PM PDT 24
Finished Jul 07 06:35:32 PM PDT 24
Peak memory 218712 kb
Host smart-f4b84c08-4065-44a9-abbf-2e8c6dd3aa5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438800567 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2438800567
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1515391440
Short name T893
Test name
Test status
Simulation time 24758029 ps
CPU time 1.27 seconds
Started Jul 07 06:35:32 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 209336 kb
Host smart-929e030a-cf70-40b1-8f72-49e3cc095343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515391440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1515391440
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2359859108
Short name T890
Test name
Test status
Simulation time 1372981897 ps
CPU time 4.63 seconds
Started Jul 07 06:35:29 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 217472 kb
Host smart-22b3f18b-bf6f-41df-bc93-08f17bf2ce7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359859108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2359859108
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3036885296
Short name T952
Test name
Test status
Simulation time 351328967 ps
CPU time 1.71 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:35 PM PDT 24
Peak memory 222196 kb
Host smart-6e56e898-41b6-4d5a-b928-5209ce7b92fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036885296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3036885296
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2566587510
Short name T119
Test name
Test status
Simulation time 48720875 ps
CPU time 1.58 seconds
Started Jul 07 06:35:32 PM PDT 24
Finished Jul 07 06:35:33 PM PDT 24
Peak memory 223636 kb
Host smart-521ced52-7233-477b-914a-ecab41e128f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566587510 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2566587510
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.484453948
Short name T946
Test name
Test status
Simulation time 24680066 ps
CPU time 0.9 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 209348 kb
Host smart-fc3d8dc8-5702-435f-bdd3-2e378d31dca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484453948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.484453948
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3511911979
Short name T986
Test name
Test status
Simulation time 68033444 ps
CPU time 1.77 seconds
Started Jul 07 06:35:31 PM PDT 24
Finished Jul 07 06:35:33 PM PDT 24
Peak memory 209340 kb
Host smart-ecaa2268-b272-4cc2-a6f3-537b189c9893
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511911979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3511911979
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.372458571
Short name T132
Test name
Test status
Simulation time 92744452 ps
CPU time 3.18 seconds
Started Jul 07 06:35:32 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 218504 kb
Host smart-7ed6a9b1-14b4-44cf-9252-caab24f58ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372458571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.372458571
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2461452199
Short name T123
Test name
Test status
Simulation time 142214671 ps
CPU time 1.58 seconds
Started Jul 07 06:35:34 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 217668 kb
Host smart-4afd57b1-c18e-435a-baf2-8a2511bb98f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461452199 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2461452199
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1535350841
Short name T940
Test name
Test status
Simulation time 52177471 ps
CPU time 0.89 seconds
Started Jul 07 06:35:32 PM PDT 24
Finished Jul 07 06:35:33 PM PDT 24
Peak memory 209332 kb
Host smart-2aaafe4d-ff1f-4522-a4c4-a6605b8ee01c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535350841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1535350841
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4136949600
Short name T124
Test name
Test status
Simulation time 130013831 ps
CPU time 1.58 seconds
Started Jul 07 06:35:38 PM PDT 24
Finished Jul 07 06:35:40 PM PDT 24
Peak memory 217552 kb
Host smart-44e915b1-3b06-4ebd-9890-59f04d71b9a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136949600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.4136949600
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1352514093
Short name T954
Test name
Test status
Simulation time 70788796 ps
CPU time 2.35 seconds
Started Jul 07 06:35:36 PM PDT 24
Finished Jul 07 06:35:39 PM PDT 24
Peak memory 217680 kb
Host smart-1c5f432a-449f-4ff9-8067-dccca349ce45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352514093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1352514093
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3705977993
Short name T200
Test name
Test status
Simulation time 90757050 ps
CPU time 1.24 seconds
Started Jul 07 06:34:56 PM PDT 24
Finished Jul 07 06:34:57 PM PDT 24
Peak memory 209348 kb
Host smart-a02abc50-a924-4077-858c-34011028d769
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705977993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3705977993
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2783207569
Short name T865
Test name
Test status
Simulation time 257429587 ps
CPU time 2.6 seconds
Started Jul 07 06:34:57 PM PDT 24
Finished Jul 07 06:35:00 PM PDT 24
Peak memory 209152 kb
Host smart-714e851a-f480-40bd-856e-764ef01f369f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783207569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2783207569
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3362753098
Short name T943
Test name
Test status
Simulation time 30224880 ps
CPU time 0.87 seconds
Started Jul 07 06:34:57 PM PDT 24
Finished Jul 07 06:34:58 PM PDT 24
Peak memory 209912 kb
Host smart-f0e15f7b-a3e6-4d91-8446-b9a7d4a45dca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362753098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3362753098
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2784987980
Short name T919
Test name
Test status
Simulation time 157684755 ps
CPU time 1.53 seconds
Started Jul 07 06:34:58 PM PDT 24
Finished Jul 07 06:34:59 PM PDT 24
Peak memory 217616 kb
Host smart-fb3d3a2f-3399-4875-aed1-607ecd1731f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784987980 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2784987980
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2086579954
Short name T863
Test name
Test status
Simulation time 26382192 ps
CPU time 0.91 seconds
Started Jul 07 06:34:54 PM PDT 24
Finished Jul 07 06:34:55 PM PDT 24
Peak memory 208796 kb
Host smart-e36d93f9-b237-41fe-8d59-74fb56ba94f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086579954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2086579954
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.540953334
Short name T930
Test name
Test status
Simulation time 66921632 ps
CPU time 1.71 seconds
Started Jul 07 06:34:52 PM PDT 24
Finished Jul 07 06:34:54 PM PDT 24
Peak memory 209180 kb
Host smart-7026e620-6492-4a5a-b469-a9839dc9912b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540953334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.540953334
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2370033014
Short name T898
Test name
Test status
Simulation time 1274438163 ps
CPU time 14.47 seconds
Started Jul 07 06:35:03 PM PDT 24
Finished Jul 07 06:35:18 PM PDT 24
Peak memory 209048 kb
Host smart-9802bc63-e824-4f58-8b1c-962859f9b84f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370033014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2370033014
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.225473768
Short name T867
Test name
Test status
Simulation time 1996949072 ps
CPU time 12.35 seconds
Started Jul 07 06:34:55 PM PDT 24
Finished Jul 07 06:35:08 PM PDT 24
Peak memory 209256 kb
Host smart-3235c3eb-a87a-4bdd-a8fd-21fbad08b6a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225473768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.225473768
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2903662470
Short name T988
Test name
Test status
Simulation time 87507447 ps
CPU time 1.52 seconds
Started Jul 07 06:34:53 PM PDT 24
Finished Jul 07 06:34:55 PM PDT 24
Peak memory 210720 kb
Host smart-363ecd3d-7850-4e4e-92a3-591b53765963
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903662470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2903662470
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3859624618
Short name T959
Test name
Test status
Simulation time 693376029 ps
CPU time 3.27 seconds
Started Jul 07 06:34:55 PM PDT 24
Finished Jul 07 06:34:58 PM PDT 24
Peak memory 218828 kb
Host smart-186500ea-b0c4-4adb-b1d8-d00eb22066d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385962
4618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3859624618
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1525487059
Short name T976
Test name
Test status
Simulation time 555701838 ps
CPU time 3.67 seconds
Started Jul 07 06:34:58 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 209252 kb
Host smart-6aed05ce-2b08-4d73-8115-3034adff8eae
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525487059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1525487059
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2031600946
Short name T927
Test name
Test status
Simulation time 37169632 ps
CPU time 1 seconds
Started Jul 07 06:34:53 PM PDT 24
Finished Jul 07 06:34:54 PM PDT 24
Peak memory 209360 kb
Host smart-67e65d80-c749-4f8c-84a2-f1dd8aa3df49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031600946 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2031600946
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.332354768
Short name T924
Test name
Test status
Simulation time 73976705 ps
CPU time 1.8 seconds
Started Jul 07 06:34:59 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 209304 kb
Host smart-7d4768d8-9d84-43bc-9e71-8f3d5ea6ff14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332354768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.332354768
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3402121449
Short name T899
Test name
Test status
Simulation time 341140122 ps
CPU time 2.03 seconds
Started Jul 07 06:34:53 PM PDT 24
Finished Jul 07 06:34:56 PM PDT 24
Peak memory 221388 kb
Host smart-887d40bd-7ab3-41b8-80b2-31313e8f7a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402121449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3402121449
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.271365759
Short name T876
Test name
Test status
Simulation time 15095327 ps
CPU time 1.01 seconds
Started Jul 07 06:35:00 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 209400 kb
Host smart-86b3b989-dd92-42c1-b1ff-711bf1ad99a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271365759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.271365759
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3802742035
Short name T987
Test name
Test status
Simulation time 380056748 ps
CPU time 2.3 seconds
Started Jul 07 06:35:00 PM PDT 24
Finished Jul 07 06:35:02 PM PDT 24
Peak memory 209280 kb
Host smart-cbd272ed-7654-4196-aaee-4519ea55f2fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802742035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3802742035
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2938658996
Short name T205
Test name
Test status
Simulation time 21967900 ps
CPU time 1.06 seconds
Started Jul 07 06:35:01 PM PDT 24
Finished Jul 07 06:35:02 PM PDT 24
Peak memory 209900 kb
Host smart-55bdcd78-e6a9-4762-a449-d77f89d97fa9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938658996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2938658996
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1088587995
Short name T138
Test name
Test status
Simulation time 28860804 ps
CPU time 2.35 seconds
Started Jul 07 06:35:01 PM PDT 24
Finished Jul 07 06:35:03 PM PDT 24
Peak memory 218728 kb
Host smart-f8ea6d5f-5be9-4b11-9964-745a69473083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088587995 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1088587995
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4001602511
Short name T201
Test name
Test status
Simulation time 22372985 ps
CPU time 1.1 seconds
Started Jul 07 06:35:02 PM PDT 24
Finished Jul 07 06:35:04 PM PDT 24
Peak memory 209352 kb
Host smart-d3ef7a43-a984-45a9-8019-b28eb981af0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001602511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4001602511
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2903271887
Short name T892
Test name
Test status
Simulation time 48124422 ps
CPU time 1.2 seconds
Started Jul 07 06:34:59 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 208668 kb
Host smart-0a746434-cf69-4610-82fa-5baa63506f9b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903271887 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2903271887
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2954019250
Short name T904
Test name
Test status
Simulation time 2348790851 ps
CPU time 5.65 seconds
Started Jul 07 06:34:57 PM PDT 24
Finished Jul 07 06:35:03 PM PDT 24
Peak memory 209164 kb
Host smart-3170007b-c565-4ccc-8453-22b41d720fd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954019250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2954019250
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.341030868
Short name T923
Test name
Test status
Simulation time 493655033 ps
CPU time 5.85 seconds
Started Jul 07 06:34:57 PM PDT 24
Finished Jul 07 06:35:03 PM PDT 24
Peak memory 209196 kb
Host smart-46cdd3ed-0aa8-4a63-ae65-d3491cb7c63d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341030868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.341030868
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3940673817
Short name T985
Test name
Test status
Simulation time 1108447102 ps
CPU time 2.76 seconds
Started Jul 07 06:34:56 PM PDT 24
Finished Jul 07 06:34:59 PM PDT 24
Peak memory 210876 kb
Host smart-c1f673ee-92ba-4f22-80c4-b8b5b08088b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940673817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3940673817
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.430075192
Short name T881
Test name
Test status
Simulation time 51541114 ps
CPU time 1.46 seconds
Started Jul 07 06:34:56 PM PDT 24
Finished Jul 07 06:34:58 PM PDT 24
Peak memory 218756 kb
Host smart-9f221137-70a7-441f-9b73-fb2354736592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430075
192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.430075192
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2914029637
Short name T962
Test name
Test status
Simulation time 244505006 ps
CPU time 2.21 seconds
Started Jul 07 06:34:56 PM PDT 24
Finished Jul 07 06:34:58 PM PDT 24
Peak memory 209276 kb
Host smart-6da07b67-3a15-47b9-958d-e1e390fc90d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914029637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2914029637
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1938779858
Short name T973
Test name
Test status
Simulation time 45923488 ps
CPU time 1.13 seconds
Started Jul 07 06:34:59 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 209372 kb
Host smart-1d75307b-9cd4-4cc2-971f-d033c5ef2afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938779858 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1938779858
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.230945817
Short name T932
Test name
Test status
Simulation time 89300519 ps
CPU time 1.44 seconds
Started Jul 07 06:35:02 PM PDT 24
Finished Jul 07 06:35:04 PM PDT 24
Peak memory 217544 kb
Host smart-3bc11a3b-4907-4e9d-8722-d77dd0635fe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230945817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.230945817
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3621491137
Short name T920
Test name
Test status
Simulation time 871590394 ps
CPU time 3.26 seconds
Started Jul 07 06:34:59 PM PDT 24
Finished Jul 07 06:35:03 PM PDT 24
Peak memory 217500 kb
Host smart-c2911b42-07b9-49b7-a57f-d7b16a419fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621491137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3621491137
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2910134380
Short name T209
Test name
Test status
Simulation time 19727177 ps
CPU time 1.23 seconds
Started Jul 07 06:35:07 PM PDT 24
Finished Jul 07 06:35:08 PM PDT 24
Peak memory 209324 kb
Host smart-2d17072a-d522-4377-9236-4dbfe0603a88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910134380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2910134380
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3567623411
Short name T202
Test name
Test status
Simulation time 366441273 ps
CPU time 2.14 seconds
Started Jul 07 06:35:02 PM PDT 24
Finished Jul 07 06:35:05 PM PDT 24
Peak memory 209304 kb
Host smart-3cb4b7c7-144d-41f9-aeee-5fef0d1d3c98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567623411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3567623411
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2513829876
Short name T206
Test name
Test status
Simulation time 16288081 ps
CPU time 0.9 seconds
Started Jul 07 06:35:01 PM PDT 24
Finished Jul 07 06:35:03 PM PDT 24
Peak memory 209776 kb
Host smart-a7dec575-f67e-46c0-9fed-08de1ab9915d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513829876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2513829876
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.95784985
Short name T921
Test name
Test status
Simulation time 47403315 ps
CPU time 1.74 seconds
Started Jul 07 06:35:03 PM PDT 24
Finished Jul 07 06:35:05 PM PDT 24
Peak memory 217600 kb
Host smart-dee5f802-8b9e-4ef7-be06-6fcd70ec0a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95784985 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.95784985
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3106796861
Short name T958
Test name
Test status
Simulation time 16648545 ps
CPU time 1.01 seconds
Started Jul 07 06:35:00 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 209336 kb
Host smart-597e2bc6-3caa-41b4-b69a-0abbbb82f659
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106796861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3106796861
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.574819011
Short name T982
Test name
Test status
Simulation time 72661745 ps
CPU time 2.28 seconds
Started Jul 07 06:35:03 PM PDT 24
Finished Jul 07 06:35:06 PM PDT 24
Peak memory 208740 kb
Host smart-906972a8-d02c-4086-a9ad-e7e1d3417054
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574819011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.574819011
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2915178505
Short name T983
Test name
Test status
Simulation time 417592894 ps
CPU time 3.08 seconds
Started Jul 07 06:34:59 PM PDT 24
Finished Jul 07 06:35:02 PM PDT 24
Peak memory 208968 kb
Host smart-b5e46ba6-2475-49e4-a47f-6fe53275feaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915178505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2915178505
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1048909769
Short name T980
Test name
Test status
Simulation time 4420917276 ps
CPU time 34.4 seconds
Started Jul 07 06:35:00 PM PDT 24
Finished Jul 07 06:35:35 PM PDT 24
Peak memory 209364 kb
Host smart-80034242-c870-45b8-a65e-fd844c3e53a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048909769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1048909769
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2002910034
Short name T955
Test name
Test status
Simulation time 518378802 ps
CPU time 2.08 seconds
Started Jul 07 06:35:02 PM PDT 24
Finished Jul 07 06:35:04 PM PDT 24
Peak memory 211008 kb
Host smart-ec319090-ea0d-4e98-9880-dbfdae5c9e03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002910034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2002910034
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1531041532
Short name T936
Test name
Test status
Simulation time 73275937 ps
CPU time 1.69 seconds
Started Jul 07 06:34:59 PM PDT 24
Finished Jul 07 06:35:01 PM PDT 24
Peak memory 217624 kb
Host smart-35951c5b-7071-40ec-aa92-87d245c0d394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153104
1532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1531041532
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2382803813
Short name T977
Test name
Test status
Simulation time 164175705 ps
CPU time 4.17 seconds
Started Jul 07 06:35:02 PM PDT 24
Finished Jul 07 06:35:06 PM PDT 24
Peak memory 209276 kb
Host smart-57fd1d60-f103-464f-aed9-2c22f6838893
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382803813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2382803813
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2998863734
Short name T212
Test name
Test status
Simulation time 16948409 ps
CPU time 1.06 seconds
Started Jul 07 06:35:02 PM PDT 24
Finished Jul 07 06:35:03 PM PDT 24
Peak memory 209388 kb
Host smart-a0bf5017-374d-498e-b98d-cc54135d2c96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998863734 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2998863734
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1810792745
Short name T872
Test name
Test status
Simulation time 44441460 ps
CPU time 1.95 seconds
Started Jul 07 06:35:05 PM PDT 24
Finished Jul 07 06:35:07 PM PDT 24
Peak memory 209348 kb
Host smart-eab53649-3fb2-404b-9ec4-0abfe38e6cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810792745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1810792745
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2166285431
Short name T931
Test name
Test status
Simulation time 1279275039 ps
CPU time 2.15 seconds
Started Jul 07 06:35:01 PM PDT 24
Finished Jul 07 06:35:03 PM PDT 24
Peak memory 217940 kb
Host smart-80521277-67c1-4d56-a8e8-7419845d6997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166285431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2166285431
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2253179211
Short name T922
Test name
Test status
Simulation time 122668160 ps
CPU time 1.53 seconds
Started Jul 07 06:35:08 PM PDT 24
Finished Jul 07 06:35:10 PM PDT 24
Peak memory 219336 kb
Host smart-50bf9359-bbee-4993-b585-4a1885ce8c77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253179211 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2253179211
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1157902649
Short name T895
Test name
Test status
Simulation time 48882006 ps
CPU time 0.83 seconds
Started Jul 07 06:35:07 PM PDT 24
Finished Jul 07 06:35:08 PM PDT 24
Peak memory 209284 kb
Host smart-d53e9775-7ae2-4ece-8eb3-44ded889af35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157902649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1157902649
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.544874446
Short name T914
Test name
Test status
Simulation time 742480945 ps
CPU time 2.18 seconds
Started Jul 07 06:35:04 PM PDT 24
Finished Jul 07 06:35:07 PM PDT 24
Peak memory 209160 kb
Host smart-792e5a14-f5a2-40a4-ad85-bb965c1f34c8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544874446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.544874446
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.571952593
Short name T909
Test name
Test status
Simulation time 865606727 ps
CPU time 10.97 seconds
Started Jul 07 06:35:06 PM PDT 24
Finished Jul 07 06:35:17 PM PDT 24
Peak memory 217152 kb
Host smart-e5d4599b-77c3-48fd-b2b9-43ed87043219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571952593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.571952593
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1147003010
Short name T957
Test name
Test status
Simulation time 4673216145 ps
CPU time 25.74 seconds
Started Jul 07 06:35:06 PM PDT 24
Finished Jul 07 06:35:32 PM PDT 24
Peak memory 209356 kb
Host smart-55ced0b8-97e7-482f-81cb-671186a09946
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147003010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1147003010
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2086753181
Short name T918
Test name
Test status
Simulation time 785542409 ps
CPU time 4.95 seconds
Started Jul 07 06:35:05 PM PDT 24
Finished Jul 07 06:35:10 PM PDT 24
Peak memory 210780 kb
Host smart-d38f64dd-ea3d-4db7-a040-a9bbab82f304
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086753181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2086753181
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.957394493
Short name T148
Test name
Test status
Simulation time 151681496 ps
CPU time 2.8 seconds
Started Jul 07 06:35:06 PM PDT 24
Finished Jul 07 06:35:09 PM PDT 24
Peak memory 217628 kb
Host smart-c70fcc99-ac55-4cce-837d-4de908ced185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957394
493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.957394493
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3304224401
Short name T869
Test name
Test status
Simulation time 44962473 ps
CPU time 1.81 seconds
Started Jul 07 06:35:02 PM PDT 24
Finished Jul 07 06:35:04 PM PDT 24
Peak memory 209288 kb
Host smart-42ebe740-1b23-4662-8155-c6decae922a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304224401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3304224401
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.250269797
Short name T215
Test name
Test status
Simulation time 21137193 ps
CPU time 1.31 seconds
Started Jul 07 06:35:07 PM PDT 24
Finished Jul 07 06:35:08 PM PDT 24
Peak memory 211496 kb
Host smart-2d0d18eb-8b37-409d-a59c-79a34a7177d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250269797 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.250269797
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2473571346
Short name T211
Test name
Test status
Simulation time 160054568 ps
CPU time 0.96 seconds
Started Jul 07 06:35:09 PM PDT 24
Finished Jul 07 06:35:11 PM PDT 24
Peak memory 209368 kb
Host smart-19dc41a8-188f-4178-ada3-dc9006a928a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473571346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2473571346
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1656071478
Short name T885
Test name
Test status
Simulation time 76003386 ps
CPU time 1.97 seconds
Started Jul 07 06:35:03 PM PDT 24
Finished Jul 07 06:35:05 PM PDT 24
Peak memory 217476 kb
Host smart-a09aec72-cd09-453c-b629-3e2ef53283bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656071478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1656071478
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1795758165
Short name T140
Test name
Test status
Simulation time 2208326547 ps
CPU time 3.02 seconds
Started Jul 07 06:35:06 PM PDT 24
Finished Jul 07 06:35:10 PM PDT 24
Peak memory 222248 kb
Host smart-dee6f965-2442-4e9a-a8da-ec85a6b81db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795758165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1795758165
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3719329999
Short name T166
Test name
Test status
Simulation time 43424362 ps
CPU time 1.22 seconds
Started Jul 07 06:35:14 PM PDT 24
Finished Jul 07 06:35:16 PM PDT 24
Peak memory 218628 kb
Host smart-742fcea7-3849-4a58-9c13-c09f24309452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719329999 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3719329999
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2231946313
Short name T204
Test name
Test status
Simulation time 104741521 ps
CPU time 0.98 seconds
Started Jul 07 06:35:10 PM PDT 24
Finished Jul 07 06:35:12 PM PDT 24
Peak memory 209592 kb
Host smart-aa74438d-2da0-45f3-a674-972c06f1fede
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231946313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2231946313
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3576792946
Short name T916
Test name
Test status
Simulation time 71841732 ps
CPU time 1.19 seconds
Started Jul 07 06:35:09 PM PDT 24
Finished Jul 07 06:35:10 PM PDT 24
Peak memory 209304 kb
Host smart-e9a4e34e-4259-4fd4-9c19-c4057e8e15cf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576792946 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3576792946
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1124343504
Short name T915
Test name
Test status
Simulation time 803951735 ps
CPU time 10.05 seconds
Started Jul 07 06:35:08 PM PDT 24
Finished Jul 07 06:35:18 PM PDT 24
Peak memory 209276 kb
Host smart-5f81eebc-2129-44e3-9ad5-7548fc689318
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124343504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1124343504
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2969912209
Short name T887
Test name
Test status
Simulation time 428689265 ps
CPU time 5.72 seconds
Started Jul 07 06:35:08 PM PDT 24
Finished Jul 07 06:35:14 PM PDT 24
Peak memory 209096 kb
Host smart-30ecfe10-0f02-47d8-bd87-ecc7747bcf16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969912209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2969912209
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4053385243
Short name T902
Test name
Test status
Simulation time 181180910 ps
CPU time 1.97 seconds
Started Jul 07 06:35:06 PM PDT 24
Finished Jul 07 06:35:09 PM PDT 24
Peak memory 217424 kb
Host smart-ab3f8d2e-c4d5-43f7-808f-9711aaa76c28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053385243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4053385243
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1469250157
Short name T990
Test name
Test status
Simulation time 148811793 ps
CPU time 4.51 seconds
Started Jul 07 06:35:10 PM PDT 24
Finished Jul 07 06:35:15 PM PDT 24
Peak memory 221828 kb
Host smart-dd51b33d-d2eb-41d3-a7c1-a0dacf349fdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146925
0157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1469250157
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2673844362
Short name T878
Test name
Test status
Simulation time 226738261 ps
CPU time 1.45 seconds
Started Jul 07 06:35:10 PM PDT 24
Finished Jul 07 06:35:11 PM PDT 24
Peak memory 209208 kb
Host smart-9365e092-24d5-446a-ba70-b0fb5ecc9964
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673844362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2673844362
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1626094553
Short name T937
Test name
Test status
Simulation time 29696976 ps
CPU time 0.98 seconds
Started Jul 07 06:35:07 PM PDT 24
Finished Jul 07 06:35:08 PM PDT 24
Peak memory 209384 kb
Host smart-76c1c2a2-ecc8-475c-9516-e08022ac8c18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626094553 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1626094553
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.860629431
Short name T964
Test name
Test status
Simulation time 17492252 ps
CPU time 1.04 seconds
Started Jul 07 06:35:14 PM PDT 24
Finished Jul 07 06:35:15 PM PDT 24
Peak memory 209352 kb
Host smart-36e07529-b8fc-453f-aefb-353d14682ea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860629431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.860629431
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3038731840
Short name T907
Test name
Test status
Simulation time 29714890 ps
CPU time 2.23 seconds
Started Jul 07 06:35:12 PM PDT 24
Finished Jul 07 06:35:14 PM PDT 24
Peak memory 218636 kb
Host smart-25fa3bfc-1c8f-42a2-be6c-a431e1791be7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038731840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3038731840
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3902722131
Short name T130
Test name
Test status
Simulation time 49920953 ps
CPU time 1.1 seconds
Started Jul 07 06:35:14 PM PDT 24
Finished Jul 07 06:35:15 PM PDT 24
Peak memory 219584 kb
Host smart-ec4f5568-6526-4f63-b7fb-b660f3ba3e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902722131 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3902722131
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1132714494
Short name T198
Test name
Test status
Simulation time 21821071 ps
CPU time 0.85 seconds
Started Jul 07 06:35:14 PM PDT 24
Finished Jul 07 06:35:15 PM PDT 24
Peak memory 208588 kb
Host smart-5af8cace-4871-4fb4-8526-dc7e43703916
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132714494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1132714494
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2962096044
Short name T864
Test name
Test status
Simulation time 39300327 ps
CPU time 1.48 seconds
Started Jul 07 06:35:16 PM PDT 24
Finished Jul 07 06:35:18 PM PDT 24
Peak memory 209116 kb
Host smart-c3ab969e-1114-4f43-874a-22b038b35978
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962096044 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2962096044
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3641198269
Short name T149
Test name
Test status
Simulation time 484357879 ps
CPU time 4.37 seconds
Started Jul 07 06:35:10 PM PDT 24
Finished Jul 07 06:35:15 PM PDT 24
Peak memory 216964 kb
Host smart-7413b616-b177-4949-8f24-0b111117d95c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641198269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3641198269
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1438374982
Short name T942
Test name
Test status
Simulation time 489196295 ps
CPU time 12.19 seconds
Started Jul 07 06:35:13 PM PDT 24
Finished Jul 07 06:35:25 PM PDT 24
Peak memory 209220 kb
Host smart-a1ba97da-4bad-46a5-a8d5-6fb7c84d2395
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438374982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1438374982
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.926111246
Short name T968
Test name
Test status
Simulation time 661096525 ps
CPU time 2.19 seconds
Started Jul 07 06:35:13 PM PDT 24
Finished Jul 07 06:35:15 PM PDT 24
Peak memory 210932 kb
Host smart-d0a9f7b1-b417-4f1b-9375-20a078dd49ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926111246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.926111246
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2671622614
Short name T939
Test name
Test status
Simulation time 516426148 ps
CPU time 5.95 seconds
Started Jul 07 06:35:19 PM PDT 24
Finished Jul 07 06:35:25 PM PDT 24
Peak memory 223788 kb
Host smart-36a62d92-67b8-445a-aeae-44e0c533f347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267162
2614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2671622614
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2998979509
Short name T913
Test name
Test status
Simulation time 53376430 ps
CPU time 1.97 seconds
Started Jul 07 06:35:13 PM PDT 24
Finished Jul 07 06:35:15 PM PDT 24
Peak memory 209208 kb
Host smart-b04afe98-2aa8-4f22-b62b-dc1ffcae5274
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998979509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2998979509
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1128745976
Short name T961
Test name
Test status
Simulation time 52958094 ps
CPU time 0.99 seconds
Started Jul 07 06:35:19 PM PDT 24
Finished Jul 07 06:35:20 PM PDT 24
Peak memory 209340 kb
Host smart-73b5e7a2-6aa6-4d92-bfa6-4204d22ca5bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128745976 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1128745976
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1399484019
Short name T167
Test name
Test status
Simulation time 30206214 ps
CPU time 1.59 seconds
Started Jul 07 06:35:18 PM PDT 24
Finished Jul 07 06:35:20 PM PDT 24
Peak memory 209336 kb
Host smart-7372ee25-ced9-45c1-8e5f-c344de9f560c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399484019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1399484019
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.939344797
Short name T929
Test name
Test status
Simulation time 43140897 ps
CPU time 2.75 seconds
Started Jul 07 06:35:16 PM PDT 24
Finished Jul 07 06:35:19 PM PDT 24
Peak memory 219800 kb
Host smart-3646fa0a-a869-4736-b0f1-64fedcd62839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939344797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.939344797
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2495318165
Short name T941
Test name
Test status
Simulation time 87141909 ps
CPU time 1.2 seconds
Started Jul 07 06:35:22 PM PDT 24
Finished Jul 07 06:35:24 PM PDT 24
Peak memory 217824 kb
Host smart-cf6ee847-ee19-41c3-b1be-7e8ad8186f7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495318165 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2495318165
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.298354652
Short name T877
Test name
Test status
Simulation time 50381665 ps
CPU time 0.84 seconds
Started Jul 07 06:35:19 PM PDT 24
Finished Jul 07 06:35:20 PM PDT 24
Peak memory 209292 kb
Host smart-9a63c745-8dec-4b5d-adf4-a7c3d32d040b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298354652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.298354652
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.954012957
Short name T944
Test name
Test status
Simulation time 175115619 ps
CPU time 1.28 seconds
Started Jul 07 06:35:20 PM PDT 24
Finished Jul 07 06:35:22 PM PDT 24
Peak memory 209160 kb
Host smart-41c7fd5e-7c46-4e5f-8705-32662e374cc4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954012957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.954012957
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1328399843
Short name T879
Test name
Test status
Simulation time 3057020882 ps
CPU time 18.12 seconds
Started Jul 07 06:35:15 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 217556 kb
Host smart-7978fcdd-e6f5-451f-992e-e7741a219a7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328399843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1328399843
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.31793060
Short name T883
Test name
Test status
Simulation time 353963953 ps
CPU time 4.59 seconds
Started Jul 07 06:35:15 PM PDT 24
Finished Jul 07 06:35:20 PM PDT 24
Peak memory 209064 kb
Host smart-dd62ecff-5adc-4fe4-94bc-477415103172
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31793060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.31793060
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3112959254
Short name T926
Test name
Test status
Simulation time 188283833 ps
CPU time 2.56 seconds
Started Jul 07 06:35:17 PM PDT 24
Finished Jul 07 06:35:19 PM PDT 24
Peak memory 211108 kb
Host smart-90201d10-e515-47c8-9cb6-979e40f008e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112959254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3112959254
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3913153300
Short name T891
Test name
Test status
Simulation time 688372117 ps
CPU time 3.25 seconds
Started Jul 07 06:35:16 PM PDT 24
Finished Jul 07 06:35:20 PM PDT 24
Peak memory 218608 kb
Host smart-5e8e818a-19fc-4700-aeed-cfb88425b7d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391315
3300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3913153300
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.248675125
Short name T906
Test name
Test status
Simulation time 241434768 ps
CPU time 2.23 seconds
Started Jul 07 06:35:15 PM PDT 24
Finished Jul 07 06:35:18 PM PDT 24
Peak memory 209272 kb
Host smart-9cd007cc-5ce3-47fd-aec0-6de3e295a451
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248675125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.248675125
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.106966789
Short name T903
Test name
Test status
Simulation time 50602820 ps
CPU time 0.96 seconds
Started Jul 07 06:35:17 PM PDT 24
Finished Jul 07 06:35:18 PM PDT 24
Peak memory 209664 kb
Host smart-95439689-a0ce-4b6b-8f51-df9e972bbe36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106966789 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.106966789
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.76991806
Short name T949
Test name
Test status
Simulation time 104020334 ps
CPU time 1.13 seconds
Started Jul 07 06:35:18 PM PDT 24
Finished Jul 07 06:35:19 PM PDT 24
Peak memory 209376 kb
Host smart-6c778dff-fd7f-4efc-980e-c144f38427c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76991806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_s
ame_csr_outstanding.76991806
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1364863325
Short name T133
Test name
Test status
Simulation time 35273850 ps
CPU time 2.68 seconds
Started Jul 07 06:35:22 PM PDT 24
Finished Jul 07 06:35:26 PM PDT 24
Peak memory 217480 kb
Host smart-d2430541-008e-4804-9ae8-3e380906924a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364863325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1364863325
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1096811279
Short name T142
Test name
Test status
Simulation time 283486245 ps
CPU time 3.48 seconds
Started Jul 07 06:35:19 PM PDT 24
Finished Jul 07 06:35:23 PM PDT 24
Peak memory 217560 kb
Host smart-af49ef4b-a501-4189-8ce1-42be87855745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096811279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1096811279
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1414167629
Short name T933
Test name
Test status
Simulation time 56390773 ps
CPU time 1.14 seconds
Started Jul 07 06:35:21 PM PDT 24
Finished Jul 07 06:35:23 PM PDT 24
Peak memory 218600 kb
Host smart-226ff345-0f35-4e1e-803a-d0e914cb858f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414167629 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1414167629
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.698845811
Short name T210
Test name
Test status
Simulation time 71823596 ps
CPU time 1.08 seconds
Started Jul 07 06:35:23 PM PDT 24
Finished Jul 07 06:35:24 PM PDT 24
Peak memory 209056 kb
Host smart-6b7a5508-b1a4-4e35-bcbe-633c3725de7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698845811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.698845811
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1770902826
Short name T874
Test name
Test status
Simulation time 44704274 ps
CPU time 1.74 seconds
Started Jul 07 06:35:26 PM PDT 24
Finished Jul 07 06:35:28 PM PDT 24
Peak memory 209204 kb
Host smart-645e9cd0-80a5-4a40-bdf6-dca84aa2019e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770902826 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1770902826
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1364328023
Short name T147
Test name
Test status
Simulation time 2535788437 ps
CPU time 6.57 seconds
Started Jul 07 06:35:19 PM PDT 24
Finished Jul 07 06:35:26 PM PDT 24
Peak memory 209416 kb
Host smart-e0175c61-d047-4b33-bd73-9c067a93a72e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364328023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1364328023
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1459133218
Short name T945
Test name
Test status
Simulation time 351194201 ps
CPU time 9.75 seconds
Started Jul 07 06:35:20 PM PDT 24
Finished Jul 07 06:35:31 PM PDT 24
Peak memory 209052 kb
Host smart-5238e487-7f7f-49f2-9f3e-755c27197343
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459133218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1459133218
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3450227618
Short name T989
Test name
Test status
Simulation time 65431477 ps
CPU time 2.34 seconds
Started Jul 07 06:35:21 PM PDT 24
Finished Jul 07 06:35:24 PM PDT 24
Peak memory 217484 kb
Host smart-256e3ee4-adca-421f-8bb0-80410912cbb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450227618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3450227618
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2457986438
Short name T974
Test name
Test status
Simulation time 57829400 ps
CPU time 1.43 seconds
Started Jul 07 06:35:20 PM PDT 24
Finished Jul 07 06:35:22 PM PDT 24
Peak memory 209288 kb
Host smart-32ababd5-79d1-4f76-a31d-241c2fb47d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457986438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2457986438
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3676502767
Short name T908
Test name
Test status
Simulation time 53490187 ps
CPU time 1.17 seconds
Started Jul 07 06:35:21 PM PDT 24
Finished Jul 07 06:35:22 PM PDT 24
Peak memory 209360 kb
Host smart-78684355-727c-4e81-9697-c6405c2e0f33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676502767 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3676502767
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1518382404
Short name T928
Test name
Test status
Simulation time 92559918 ps
CPU time 1.46 seconds
Started Jul 07 06:35:22 PM PDT 24
Finished Jul 07 06:35:23 PM PDT 24
Peak memory 209340 kb
Host smart-6a154448-db6d-4ffa-bc41-6b594944fd4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518382404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1518382404
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.241821661
Short name T139
Test name
Test status
Simulation time 67835069 ps
CPU time 3.09 seconds
Started Jul 07 06:35:21 PM PDT 24
Finished Jul 07 06:35:24 PM PDT 24
Peak memory 217472 kb
Host smart-680e642b-7919-4047-8463-43b6cd56433a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241821661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.241821661
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3557867989
Short name T146
Test name
Test status
Simulation time 74515610 ps
CPU time 2.21 seconds
Started Jul 07 06:35:23 PM PDT 24
Finished Jul 07 06:35:25 PM PDT 24
Peak memory 221828 kb
Host smart-a24721cd-580d-408a-af91-baceaa2616bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557867989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3557867989
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1427842516
Short name T494
Test name
Test status
Simulation time 154253264 ps
CPU time 0.86 seconds
Started Jul 07 06:52:42 PM PDT 24
Finished Jul 07 06:52:43 PM PDT 24
Peak memory 208804 kb
Host smart-65394ce6-7888-4a94-9a78-1085657deb6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427842516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1427842516
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2902194142
Short name T786
Test name
Test status
Simulation time 267097678 ps
CPU time 11.19 seconds
Started Jul 07 06:52:20 PM PDT 24
Finished Jul 07 06:52:32 PM PDT 24
Peak memory 218272 kb
Host smart-d136ef09-5fde-4d57-a3a7-54ec51fd22d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902194142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2902194142
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.4160336736
Short name T784
Test name
Test status
Simulation time 316936990 ps
CPU time 9.17 seconds
Started Jul 07 06:52:33 PM PDT 24
Finished Jul 07 06:52:42 PM PDT 24
Peak memory 217264 kb
Host smart-207831f1-8302-4bdf-baa1-d1692bdda728
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160336736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.4160336736
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2492888122
Short name T797
Test name
Test status
Simulation time 2768120593 ps
CPU time 40.01 seconds
Started Jul 07 06:52:32 PM PDT 24
Finished Jul 07 06:53:12 PM PDT 24
Peak memory 219044 kb
Host smart-b410bf84-8c26-412e-94be-61f90a8efb9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492888122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2492888122
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2672391260
Short name T391
Test name
Test status
Simulation time 952376924 ps
CPU time 7.03 seconds
Started Jul 07 06:52:31 PM PDT 24
Finished Jul 07 06:52:38 PM PDT 24
Peak memory 217564 kb
Host smart-53c88de9-f038-4c6a-af4d-1fef7a5167e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672391260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
672391260
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2064993294
Short name T519
Test name
Test status
Simulation time 1452717423 ps
CPU time 11.71 seconds
Started Jul 07 06:52:27 PM PDT 24
Finished Jul 07 06:52:39 PM PDT 24
Peak memory 218252 kb
Host smart-c587441c-499e-49af-b491-3fdc2e4a2d54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064993294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2064993294
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3597847441
Short name T387
Test name
Test status
Simulation time 4251742115 ps
CPU time 29.16 seconds
Started Jul 07 06:52:33 PM PDT 24
Finished Jul 07 06:53:02 PM PDT 24
Peak memory 217640 kb
Host smart-0106b244-5317-4e41-927c-3f64b7e1d9fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597847441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3597847441
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3494098256
Short name T736
Test name
Test status
Simulation time 493425725 ps
CPU time 3.92 seconds
Started Jul 07 06:52:26 PM PDT 24
Finished Jul 07 06:52:30 PM PDT 24
Peak memory 217716 kb
Host smart-773d0c93-28d0-4d51-8287-3d02bab66606
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494098256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3494098256
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4205834587
Short name T737
Test name
Test status
Simulation time 1312798264 ps
CPU time 44.51 seconds
Started Jul 07 06:52:23 PM PDT 24
Finished Jul 07 06:53:08 PM PDT 24
Peak memory 268968 kb
Host smart-3514520c-672b-4f4b-a358-eea6714b12c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205834587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4205834587
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2348163549
Short name T283
Test name
Test status
Simulation time 402950920 ps
CPU time 9.15 seconds
Started Jul 07 06:52:26 PM PDT 24
Finished Jul 07 06:52:35 PM PDT 24
Peak memory 223984 kb
Host smart-78dbeeb0-57dd-4902-bf7f-071824032f87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348163549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2348163549
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3362722944
Short name T299
Test name
Test status
Simulation time 208991177 ps
CPU time 2.85 seconds
Started Jul 07 06:52:15 PM PDT 24
Finished Jul 07 06:52:18 PM PDT 24
Peak memory 222528 kb
Host smart-5eebe9b3-cbe1-4775-9c19-e52968035c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362722944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3362722944
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.4127228045
Short name T483
Test name
Test status
Simulation time 321049487 ps
CPU time 13.27 seconds
Started Jul 07 06:52:17 PM PDT 24
Finished Jul 07 06:52:31 PM PDT 24
Peak memory 214236 kb
Host smart-ad892ff0-c69b-44ff-88d0-c1a0cd15376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127228045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.4127228045
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.136040993
Short name T272
Test name
Test status
Simulation time 463262840 ps
CPU time 19.05 seconds
Started Jul 07 06:52:34 PM PDT 24
Finished Jul 07 06:52:54 PM PDT 24
Peak memory 218828 kb
Host smart-861c9155-cf05-4d8e-a99a-800a47e68676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136040993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.136040993
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3092983621
Short name T481
Test name
Test status
Simulation time 956894881 ps
CPU time 12.44 seconds
Started Jul 07 06:52:36 PM PDT 24
Finished Jul 07 06:52:48 PM PDT 24
Peak memory 225904 kb
Host smart-b243a2e1-72db-482e-8a6c-b21ec9ef6b51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092983621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3092983621
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1437948194
Short name T258
Test name
Test status
Simulation time 1056980615 ps
CPU time 8.54 seconds
Started Jul 07 06:52:35 PM PDT 24
Finished Jul 07 06:52:43 PM PDT 24
Peak memory 226032 kb
Host smart-7a9256b5-8929-4262-ae17-9f20602e07ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437948194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
437948194
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.967755381
Short name T582
Test name
Test status
Simulation time 1605192973 ps
CPU time 7.35 seconds
Started Jul 07 06:52:19 PM PDT 24
Finished Jul 07 06:52:26 PM PDT 24
Peak memory 218316 kb
Host smart-e74fc24c-5355-4a7a-a6ae-8d0885a065b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967755381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.967755381
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1422873183
Short name T418
Test name
Test status
Simulation time 108716437 ps
CPU time 3.51 seconds
Started Jul 07 06:52:10 PM PDT 24
Finished Jul 07 06:52:14 PM PDT 24
Peak memory 214960 kb
Host smart-2a9fa9fa-9782-4dac-92be-bfddb01348ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422873183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1422873183
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.615570341
Short name T801
Test name
Test status
Simulation time 396336967 ps
CPU time 31.45 seconds
Started Jul 07 06:52:15 PM PDT 24
Finished Jul 07 06:52:46 PM PDT 24
Peak memory 251052 kb
Host smart-57c2bef9-86ba-461c-a172-2d5f5a902baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615570341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.615570341
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2991186121
Short name T267
Test name
Test status
Simulation time 78246875 ps
CPU time 6.53 seconds
Started Jul 07 06:52:19 PM PDT 24
Finished Jul 07 06:52:26 PM PDT 24
Peak memory 247320 kb
Host smart-31cc7a8c-705a-4723-85aa-6fc3358c7931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991186121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2991186121
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2006998064
Short name T39
Test name
Test status
Simulation time 17724094309 ps
CPU time 95.53 seconds
Started Jul 07 06:52:38 PM PDT 24
Finished Jul 07 06:54:14 PM PDT 24
Peak memory 226108 kb
Host smart-7a1f9d0d-964a-4856-858a-4f322133fedf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006998064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2006998064
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1302529252
Short name T181
Test name
Test status
Simulation time 6643617180 ps
CPU time 127.07 seconds
Started Jul 07 06:52:41 PM PDT 24
Finished Jul 07 06:54:48 PM PDT 24
Peak memory 226228 kb
Host smart-4b548b72-cd0e-4272-a47e-ad7e30d903d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1302529252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.1302529252
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3541607081
Short name T667
Test name
Test status
Simulation time 126356691 ps
CPU time 0.94 seconds
Started Jul 07 06:52:11 PM PDT 24
Finished Jul 07 06:52:12 PM PDT 24
Peak memory 211844 kb
Host smart-40d31cc3-dcd1-4458-85e6-9d453ed6a3f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541607081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3541607081
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.253476772
Short name T502
Test name
Test status
Simulation time 103515695 ps
CPU time 1.38 seconds
Started Jul 07 06:53:02 PM PDT 24
Finished Jul 07 06:53:03 PM PDT 24
Peak memory 209148 kb
Host smart-a8a8427c-34eb-4340-9589-cf96514cd896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253476772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.253476772
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2652635240
Short name T633
Test name
Test status
Simulation time 63142900 ps
CPU time 0.82 seconds
Started Jul 07 06:52:55 PM PDT 24
Finished Jul 07 06:52:56 PM PDT 24
Peak memory 208916 kb
Host smart-14b7c446-3099-4692-a5c6-42bb316a12c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652635240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2652635240
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.445733162
Short name T549
Test name
Test status
Simulation time 3148455541 ps
CPU time 14.53 seconds
Started Jul 07 06:52:48 PM PDT 24
Finished Jul 07 06:53:03 PM PDT 24
Peak memory 226168 kb
Host smart-5311ade1-664b-47de-b6c4-28fd7ed854fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445733162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.445733162
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1109961869
Short name T455
Test name
Test status
Simulation time 842934784 ps
CPU time 19.26 seconds
Started Jul 07 06:52:53 PM PDT 24
Finished Jul 07 06:53:13 PM PDT 24
Peak memory 217208 kb
Host smart-afc4e19f-5ade-4b98-bdfd-d2e782d46afe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109961869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1109961869
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3439229263
Short name T806
Test name
Test status
Simulation time 2681222605 ps
CPU time 23.24 seconds
Started Jul 07 06:52:53 PM PDT 24
Finished Jul 07 06:53:16 PM PDT 24
Peak memory 219176 kb
Host smart-38ba4aba-c00b-4078-b20c-70d811623dba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439229263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3439229263
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2207221370
Short name T195
Test name
Test status
Simulation time 483523966 ps
CPU time 11.96 seconds
Started Jul 07 06:52:56 PM PDT 24
Finished Jul 07 06:53:08 PM PDT 24
Peak memory 217768 kb
Host smart-e81662ef-3167-41fc-8ffd-54bc71d4af3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207221370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
207221370
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.4102058352
Short name T235
Test name
Test status
Simulation time 264463640 ps
CPU time 2.48 seconds
Started Jul 07 06:52:56 PM PDT 24
Finished Jul 07 06:52:58 PM PDT 24
Peak memory 218196 kb
Host smart-735c9232-482e-4854-8503-3415408e7bf0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102058352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.4102058352
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.73267776
Short name T726
Test name
Test status
Simulation time 1088932417 ps
CPU time 32.23 seconds
Started Jul 07 06:52:56 PM PDT 24
Finished Jul 07 06:53:28 PM PDT 24
Peak memory 217984 kb
Host smart-b13cc3f1-c8dd-4601-9154-25ce7fe63fe2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73267776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jt
ag_regwen_during_op.73267776
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3269767911
Short name T239
Test name
Test status
Simulation time 333331313 ps
CPU time 1.8 seconds
Started Jul 07 06:52:53 PM PDT 24
Finished Jul 07 06:52:55 PM PDT 24
Peak memory 217652 kb
Host smart-06da87c0-d064-42bd-9ffe-8dfaf17d655b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269767911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3269767911
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.312529585
Short name T276
Test name
Test status
Simulation time 8354573341 ps
CPU time 76.32 seconds
Started Jul 07 06:52:53 PM PDT 24
Finished Jul 07 06:54:09 PM PDT 24
Peak memory 276804 kb
Host smart-cf9a5186-a48a-4cd1-9d60-da32c843b9c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312529585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.312529585
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.674877035
Short name T676
Test name
Test status
Simulation time 1693961114 ps
CPU time 11.85 seconds
Started Jul 07 06:52:52 PM PDT 24
Finished Jul 07 06:53:04 PM PDT 24
Peak memory 251060 kb
Host smart-daf391b4-64cc-457a-94e9-b63d5a0cddf2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674877035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.674877035
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4095459570
Short name T176
Test name
Test status
Simulation time 72604056 ps
CPU time 4.13 seconds
Started Jul 07 06:52:46 PM PDT 24
Finished Jul 07 06:52:50 PM PDT 24
Peak memory 218224 kb
Host smart-21a4893f-3e40-427c-85a8-889382c95882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095459570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4095459570
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2717483271
Short name T196
Test name
Test status
Simulation time 2909505472 ps
CPU time 7.49 seconds
Started Jul 07 06:52:50 PM PDT 24
Finished Jul 07 06:52:57 PM PDT 24
Peak memory 217764 kb
Host smart-be702eee-7769-4b34-b660-5504f7c341ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717483271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2717483271
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.471576411
Short name T51
Test name
Test status
Simulation time 487162905 ps
CPU time 23.07 seconds
Started Jul 07 06:53:04 PM PDT 24
Finished Jul 07 06:53:28 PM PDT 24
Peak memory 281772 kb
Host smart-30918c5b-5344-4ceb-9c0e-4b404f858ca3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471576411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.471576411
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1796432280
Short name T553
Test name
Test status
Simulation time 349505924 ps
CPU time 16.44 seconds
Started Jul 07 06:52:55 PM PDT 24
Finished Jul 07 06:53:12 PM PDT 24
Peak memory 218456 kb
Host smart-e225120d-4dcc-4b72-95bd-b608f707a6ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796432280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1796432280
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1182278888
Short name T244
Test name
Test status
Simulation time 3092071861 ps
CPU time 12.63 seconds
Started Jul 07 06:52:58 PM PDT 24
Finished Jul 07 06:53:11 PM PDT 24
Peak memory 226064 kb
Host smart-dd93d9d0-aa70-474b-87fd-fe52721df3fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182278888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1182278888
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3283793702
Short name T634
Test name
Test status
Simulation time 1773813519 ps
CPU time 9.29 seconds
Started Jul 07 06:52:57 PM PDT 24
Finished Jul 07 06:53:07 PM PDT 24
Peak memory 218252 kb
Host smart-8911a077-688c-451a-98c4-5b53141f924b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283793702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
283793702
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2954706902
Short name T277
Test name
Test status
Simulation time 1413820855 ps
CPU time 7.49 seconds
Started Jul 07 06:52:50 PM PDT 24
Finished Jul 07 06:52:58 PM PDT 24
Peak memory 225052 kb
Host smart-324c098e-765e-4703-9b4b-1b9872337a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954706902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2954706902
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3843835465
Short name T66
Test name
Test status
Simulation time 44548917 ps
CPU time 2.13 seconds
Started Jul 07 06:52:42 PM PDT 24
Finished Jul 07 06:52:44 PM PDT 24
Peak memory 214524 kb
Host smart-a978448f-13be-42da-9eb7-3452a75a011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843835465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3843835465
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.4046524554
Short name T638
Test name
Test status
Simulation time 304501184 ps
CPU time 25.39 seconds
Started Jul 07 06:52:46 PM PDT 24
Finished Jul 07 06:53:12 PM PDT 24
Peak memory 250924 kb
Host smart-48ccc54c-1d4e-42d8-974e-f9a65cc53725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046524554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.4046524554
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4011836577
Short name T798
Test name
Test status
Simulation time 1762616469 ps
CPU time 39.21 seconds
Started Jul 07 06:52:59 PM PDT 24
Finished Jul 07 06:53:38 PM PDT 24
Peak memory 218408 kb
Host smart-c9fb4d3c-7df2-43b8-9dc2-2db8ee16362f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011836577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4011836577
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2965976661
Short name T13
Test name
Test status
Simulation time 12935657 ps
CPU time 0.99 seconds
Started Jul 07 06:52:44 PM PDT 24
Finished Jul 07 06:52:45 PM PDT 24
Peak memory 208580 kb
Host smart-95555d6e-e5c3-412a-be09-e41efb38fcb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965976661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2965976661
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.5554178
Short name T861
Test name
Test status
Simulation time 83822670 ps
CPU time 0.94 seconds
Started Jul 07 06:55:19 PM PDT 24
Finished Jul 07 06:55:20 PM PDT 24
Peak memory 209304 kb
Host smart-07b16cb4-6895-4724-ac7b-4ccc7add034c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5554178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.5554178
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3444223972
Short name T724
Test name
Test status
Simulation time 1267448746 ps
CPU time 8.32 seconds
Started Jul 07 06:55:13 PM PDT 24
Finished Jul 07 06:55:21 PM PDT 24
Peak memory 226028 kb
Host smart-13ecef12-30d2-416c-9c46-d611399eb014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444223972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3444223972
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3635173851
Short name T610
Test name
Test status
Simulation time 148712781 ps
CPU time 4.24 seconds
Started Jul 07 06:55:19 PM PDT 24
Finished Jul 07 06:55:24 PM PDT 24
Peak memory 217124 kb
Host smart-a2542ea2-17cf-4e0a-8848-732f0296a5c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635173851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3635173851
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3800539104
Short name T110
Test name
Test status
Simulation time 48290959942 ps
CPU time 98.42 seconds
Started Jul 07 06:55:17 PM PDT 24
Finished Jul 07 06:56:56 PM PDT 24
Peak memory 220128 kb
Host smart-cf4295b4-17b9-438a-8da9-b6c9ff295b25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800539104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3800539104
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.549867403
Short name T357
Test name
Test status
Simulation time 1078328372 ps
CPU time 5.28 seconds
Started Jul 07 06:55:18 PM PDT 24
Finished Jul 07 06:55:24 PM PDT 24
Peak memory 223104 kb
Host smart-9a88c4b3-53b6-440a-b584-e10d6c7cf207
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549867403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.549867403
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1284019796
Short name T732
Test name
Test status
Simulation time 445029035 ps
CPU time 10.68 seconds
Started Jul 07 06:55:18 PM PDT 24
Finished Jul 07 06:55:29 PM PDT 24
Peak memory 217728 kb
Host smart-88307883-3cd6-4f8a-acff-a19fc4761e9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284019796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1284019796
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1500595917
Short name T459
Test name
Test status
Simulation time 13080138438 ps
CPU time 68.12 seconds
Started Jul 07 06:55:13 PM PDT 24
Finished Jul 07 06:56:21 PM PDT 24
Peak memory 283820 kb
Host smart-eaa8cee0-e65b-4834-b6bb-da111e4f175c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500595917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1500595917
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1144531452
Short name T703
Test name
Test status
Simulation time 1289348720 ps
CPU time 23.85 seconds
Started Jul 07 06:55:19 PM PDT 24
Finished Jul 07 06:55:43 PM PDT 24
Peak memory 250972 kb
Host smart-6c131133-17b5-4b78-bde7-0d688d6bb367
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144531452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1144531452
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.54924943
Short name T408
Test name
Test status
Simulation time 780409642 ps
CPU time 2.8 seconds
Started Jul 07 06:55:18 PM PDT 24
Finished Jul 07 06:55:21 PM PDT 24
Peak memory 218232 kb
Host smart-7752dcea-7679-4428-a418-61b64c1a90f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54924943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.54924943
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2295074738
Short name T470
Test name
Test status
Simulation time 405345264 ps
CPU time 16.1 seconds
Started Jul 07 06:55:17 PM PDT 24
Finished Jul 07 06:55:33 PM PDT 24
Peak memory 226040 kb
Host smart-67aa65eb-6df3-4003-8ede-148381a83a51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295074738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2295074738
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2011493328
Short name T251
Test name
Test status
Simulation time 409623570 ps
CPU time 14.53 seconds
Started Jul 07 06:55:18 PM PDT 24
Finished Jul 07 06:55:33 PM PDT 24
Peak memory 226044 kb
Host smart-586d718e-1763-4df8-af9c-896a11325341
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011493328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2011493328
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3957897538
Short name T326
Test name
Test status
Simulation time 1321889735 ps
CPU time 9.32 seconds
Started Jul 07 06:55:16 PM PDT 24
Finished Jul 07 06:55:26 PM PDT 24
Peak memory 226032 kb
Host smart-d667c4f2-49b7-4276-8127-466e9e90c27d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957897538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3957897538
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.541562996
Short name T421
Test name
Test status
Simulation time 425829991 ps
CPU time 9.3 seconds
Started Jul 07 06:55:14 PM PDT 24
Finished Jul 07 06:55:23 PM PDT 24
Peak memory 224852 kb
Host smart-f6fb219e-6346-4e7e-aa43-b45222bf4b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541562996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.541562996
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1950065468
Short name T620
Test name
Test status
Simulation time 38524090 ps
CPU time 2.43 seconds
Started Jul 07 06:55:11 PM PDT 24
Finished Jul 07 06:55:14 PM PDT 24
Peak memory 214312 kb
Host smart-9ea20062-d2e8-4618-b360-59a37f033b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950065468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1950065468
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3975767769
Short name T99
Test name
Test status
Simulation time 261457027 ps
CPU time 31.71 seconds
Started Jul 07 06:55:13 PM PDT 24
Finished Jul 07 06:55:45 PM PDT 24
Peak memory 251020 kb
Host smart-b7398b5d-58be-4ce2-98d3-bc13307561f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975767769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3975767769
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2576236215
Short name T90
Test name
Test status
Simulation time 1588403303 ps
CPU time 6.68 seconds
Started Jul 07 06:55:15 PM PDT 24
Finished Jul 07 06:55:21 PM PDT 24
Peak memory 250928 kb
Host smart-b89c69e0-c75a-4504-9abd-41a0eb6ec64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576236215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2576236215
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1239435815
Short name T851
Test name
Test status
Simulation time 13986117491 ps
CPU time 243.85 seconds
Started Jul 07 06:55:18 PM PDT 24
Finished Jul 07 06:59:22 PM PDT 24
Peak memory 272076 kb
Host smart-a6df9888-9202-45ec-b5cb-f3390dee91ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239435815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1239435815
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1442553933
Short name T232
Test name
Test status
Simulation time 29215835 ps
CPU time 0.91 seconds
Started Jul 07 06:55:09 PM PDT 24
Finished Jul 07 06:55:10 PM PDT 24
Peak memory 211924 kb
Host smart-67e86141-71e2-4e3d-a4fb-f2654ab8453d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442553933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1442553933
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1899834827
Short name T375
Test name
Test status
Simulation time 21541136 ps
CPU time 1.25 seconds
Started Jul 07 06:55:30 PM PDT 24
Finished Jul 07 06:55:31 PM PDT 24
Peak memory 209016 kb
Host smart-bec80884-8416-42c2-b86d-8b5178bd3467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899834827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1899834827
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2049087711
Short name T712
Test name
Test status
Simulation time 1444389142 ps
CPU time 27.68 seconds
Started Jul 07 06:55:24 PM PDT 24
Finished Jul 07 06:55:52 PM PDT 24
Peak memory 226044 kb
Host smart-f2906e53-4661-4768-892e-519d3b62604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049087711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2049087711
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.746352076
Short name T8
Test name
Test status
Simulation time 2380464830 ps
CPU time 4.82 seconds
Started Jul 07 06:55:24 PM PDT 24
Finished Jul 07 06:55:29 PM PDT 24
Peak memory 217500 kb
Host smart-e913d9c4-7cea-4679-a05f-9077b46ec72e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746352076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.746352076
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2436534489
Short name T399
Test name
Test status
Simulation time 16832233399 ps
CPU time 48.59 seconds
Started Jul 07 06:55:24 PM PDT 24
Finished Jul 07 06:56:13 PM PDT 24
Peak memory 218936 kb
Host smart-7a3d2af3-209e-410a-9cfc-99b1d1cc0aaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436534489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2436534489
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.168088816
Short name T700
Test name
Test status
Simulation time 338960391 ps
CPU time 6.27 seconds
Started Jul 07 06:55:25 PM PDT 24
Finished Jul 07 06:55:31 PM PDT 24
Peak memory 223024 kb
Host smart-1e3e0939-e3e7-4642-92ff-a030399d9726
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168088816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.168088816
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2614755398
Short name T649
Test name
Test status
Simulation time 341709265 ps
CPU time 2.78 seconds
Started Jul 07 06:55:27 PM PDT 24
Finished Jul 07 06:55:30 PM PDT 24
Peak memory 217712 kb
Host smart-b2c34284-8341-4fe2-a9e6-2763c10d3f00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614755398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2614755398
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2650284598
Short name T592
Test name
Test status
Simulation time 8947042194 ps
CPU time 41.02 seconds
Started Jul 07 06:55:25 PM PDT 24
Finished Jul 07 06:56:07 PM PDT 24
Peak memory 267500 kb
Host smart-8cd52daa-c860-45c1-b112-3ebe5a94ddbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650284598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2650284598
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4194124822
Short name T319
Test name
Test status
Simulation time 277338580 ps
CPU time 13.36 seconds
Started Jul 07 06:55:25 PM PDT 24
Finished Jul 07 06:55:39 PM PDT 24
Peak memory 250984 kb
Host smart-57440842-7a95-465f-b2af-6897655c9b95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194124822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4194124822
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.787938158
Short name T350
Test name
Test status
Simulation time 123570820 ps
CPU time 3.14 seconds
Started Jul 07 06:55:21 PM PDT 24
Finished Jul 07 06:55:24 PM PDT 24
Peak memory 218192 kb
Host smart-6a2a8331-b017-46fe-bbb6-786608ee5f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787938158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.787938158
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.4226072243
Short name T183
Test name
Test status
Simulation time 735097927 ps
CPU time 8.85 seconds
Started Jul 07 06:55:28 PM PDT 24
Finished Jul 07 06:55:37 PM PDT 24
Peak memory 226048 kb
Host smart-d95977c4-4f73-49f2-bc4e-09e424665d05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226072243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.4226072243
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2272756009
Short name T774
Test name
Test status
Simulation time 472917250 ps
CPU time 6.8 seconds
Started Jul 07 06:55:29 PM PDT 24
Finished Jul 07 06:55:36 PM PDT 24
Peak memory 226084 kb
Host smart-3d805c48-28ba-499c-b14e-28ce02707437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272756009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2272756009
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3038966798
Short name T21
Test name
Test status
Simulation time 349163809 ps
CPU time 4.81 seconds
Started Jul 07 06:55:20 PM PDT 24
Finished Jul 07 06:55:26 PM PDT 24
Peak memory 217660 kb
Host smart-a31c3d8d-88d0-48bd-92d0-de882b3c4afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038966798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3038966798
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1144337656
Short name T484
Test name
Test status
Simulation time 207398411 ps
CPU time 22.39 seconds
Started Jul 07 06:55:22 PM PDT 24
Finished Jul 07 06:55:44 PM PDT 24
Peak memory 250988 kb
Host smart-f5dab810-b042-41c9-a5b6-1074e15122b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144337656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1144337656
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3066459766
Short name T274
Test name
Test status
Simulation time 434389263 ps
CPU time 7.28 seconds
Started Jul 07 06:55:20 PM PDT 24
Finished Jul 07 06:55:28 PM PDT 24
Peak memory 250816 kb
Host smart-f2b0e932-b04a-4843-b5a6-b73bcbbe4091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066459766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3066459766
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3919623824
Short name T352
Test name
Test status
Simulation time 1720350417 ps
CPU time 56.22 seconds
Started Jul 07 06:55:27 PM PDT 24
Finished Jul 07 06:56:24 PM PDT 24
Peak memory 250920 kb
Host smart-72c8887e-b003-4d15-b3b5-3e24f0c12c43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919623824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3919623824
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3952235928
Short name T184
Test name
Test status
Simulation time 14294114 ps
CPU time 1.1 seconds
Started Jul 07 06:55:21 PM PDT 24
Finished Jul 07 06:55:22 PM PDT 24
Peak memory 211996 kb
Host smart-d569c45d-f42c-4e4a-993c-05134f6ce6c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952235928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3952235928
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3534127071
Short name T237
Test name
Test status
Simulation time 27055322 ps
CPU time 1.33 seconds
Started Jul 07 06:55:35 PM PDT 24
Finished Jul 07 06:55:37 PM PDT 24
Peak memory 209060 kb
Host smart-8bb50451-f9c8-4904-8ca0-c4e2e3d55328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534127071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3534127071
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2556001584
Short name T747
Test name
Test status
Simulation time 691534375 ps
CPU time 18.18 seconds
Started Jul 07 06:55:34 PM PDT 24
Finished Jul 07 06:55:53 PM PDT 24
Peak memory 218184 kb
Host smart-b9eab701-6dca-430c-ba64-bcb1bafa575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556001584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2556001584
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3794811038
Short name T310
Test name
Test status
Simulation time 3802734114 ps
CPU time 13.61 seconds
Started Jul 07 06:55:34 PM PDT 24
Finished Jul 07 06:55:48 PM PDT 24
Peak memory 217748 kb
Host smart-644d20f9-acb6-4e35-9ec6-d829d3e1b43a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794811038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3794811038
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3531650170
Short name T390
Test name
Test status
Simulation time 2476140038 ps
CPU time 69.18 seconds
Started Jul 07 06:55:35 PM PDT 24
Finished Jul 07 06:56:44 PM PDT 24
Peak memory 219288 kb
Host smart-90a32b4c-f476-4513-b849-a5f69b1d17d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531650170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3531650170
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.60498606
Short name T716
Test name
Test status
Simulation time 2619073721 ps
CPU time 5.81 seconds
Started Jul 07 06:55:31 PM PDT 24
Finished Jul 07 06:55:37 PM PDT 24
Peak memory 218284 kb
Host smart-db9926e6-f7b2-4364-a31c-eae71966c182
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60498606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_
prog_failure.60498606
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2554837425
Short name T642
Test name
Test status
Simulation time 142176385 ps
CPU time 4.62 seconds
Started Jul 07 06:55:33 PM PDT 24
Finished Jul 07 06:55:38 PM PDT 24
Peak memory 217768 kb
Host smart-20f2432d-469f-41e4-b8b3-4c5e69901b56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554837425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2554837425
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3029382422
Short name T710
Test name
Test status
Simulation time 8460283848 ps
CPU time 81.15 seconds
Started Jul 07 06:55:33 PM PDT 24
Finished Jul 07 06:56:55 PM PDT 24
Peak memory 278272 kb
Host smart-c2aa2e0c-c829-4271-806a-7aedb1286bb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029382422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3029382422
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1785209236
Short name T556
Test name
Test status
Simulation time 677658855 ps
CPU time 15.3 seconds
Started Jul 07 06:55:31 PM PDT 24
Finished Jul 07 06:55:47 PM PDT 24
Peak memory 246648 kb
Host smart-223d4fe9-06a0-4279-bcf5-03dd572661d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785209236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1785209236
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2671016971
Short name T230
Test name
Test status
Simulation time 127885756 ps
CPU time 2.74 seconds
Started Jul 07 06:55:32 PM PDT 24
Finished Jul 07 06:55:35 PM PDT 24
Peak memory 218344 kb
Host smart-20606940-a65b-4dd7-9dfb-f33f93a46f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671016971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2671016971
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1638327378
Short name T495
Test name
Test status
Simulation time 759078059 ps
CPU time 33.69 seconds
Started Jul 07 06:55:35 PM PDT 24
Finished Jul 07 06:56:09 PM PDT 24
Peak memory 218900 kb
Host smart-9c7e08bf-907a-4d3a-b9c8-a0ba2de223b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638327378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1638327378
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3093089743
Short name T782
Test name
Test status
Simulation time 2228468634 ps
CPU time 12.11 seconds
Started Jul 07 06:55:36 PM PDT 24
Finished Jul 07 06:55:49 PM PDT 24
Peak memory 226104 kb
Host smart-62e65b0d-18cd-4de3-8f29-a645c48d9acc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093089743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3093089743
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2348979302
Short name T805
Test name
Test status
Simulation time 1463486389 ps
CPU time 8.03 seconds
Started Jul 07 06:55:35 PM PDT 24
Finished Jul 07 06:55:43 PM PDT 24
Peak memory 218204 kb
Host smart-3773f672-9f06-448c-a7c6-1cb39e41d34c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348979302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2348979302
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.947200013
Short name T670
Test name
Test status
Simulation time 2069697498 ps
CPU time 12.9 seconds
Started Jul 07 06:55:31 PM PDT 24
Finished Jul 07 06:55:44 PM PDT 24
Peak memory 218272 kb
Host smart-78661715-1f52-4a84-b02f-161263192261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947200013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.947200013
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1291479478
Short name T78
Test name
Test status
Simulation time 102708506 ps
CPU time 2.27 seconds
Started Jul 07 06:55:30 PM PDT 24
Finished Jul 07 06:55:33 PM PDT 24
Peak memory 214532 kb
Host smart-e12ff7e3-5ac8-4716-b282-957f2c097dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291479478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1291479478
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3840085064
Short name T85
Test name
Test status
Simulation time 2045777467 ps
CPU time 22.66 seconds
Started Jul 07 06:55:28 PM PDT 24
Finished Jul 07 06:55:51 PM PDT 24
Peak memory 250980 kb
Host smart-9e767657-f44a-477e-9b99-32350998ac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840085064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3840085064
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.869917444
Short name T416
Test name
Test status
Simulation time 123843794 ps
CPU time 9.09 seconds
Started Jul 07 06:55:31 PM PDT 24
Finished Jul 07 06:55:41 PM PDT 24
Peak memory 250924 kb
Host smart-eaa8df98-b03b-455b-ac49-b9a474619a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869917444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.869917444
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3884316865
Short name T301
Test name
Test status
Simulation time 2745661663 ps
CPU time 69.21 seconds
Started Jul 07 06:55:35 PM PDT 24
Finished Jul 07 06:56:44 PM PDT 24
Peak memory 283804 kb
Host smart-f5748af0-9b38-4289-8cfa-a64354ad9e89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884316865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3884316865
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3929837538
Short name T180
Test name
Test status
Simulation time 21749188799 ps
CPU time 249.56 seconds
Started Jul 07 06:55:37 PM PDT 24
Finished Jul 07 06:59:47 PM PDT 24
Peak memory 280596 kb
Host smart-9611c901-bbd7-4f53-8940-489bf081c479
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3929837538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3929837538
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.19758111
Short name T242
Test name
Test status
Simulation time 13791239 ps
CPU time 1.11 seconds
Started Jul 07 06:55:31 PM PDT 24
Finished Jul 07 06:55:32 PM PDT 24
Peak memory 211928 kb
Host smart-2655edb0-834d-441c-8c1d-724d1f4feed4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19758111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_volatile_unlock_smoke.19758111
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1231992524
Short name T790
Test name
Test status
Simulation time 47163856 ps
CPU time 1.06 seconds
Started Jul 07 06:55:49 PM PDT 24
Finished Jul 07 06:55:50 PM PDT 24
Peak memory 208968 kb
Host smart-3f4d0eb3-6d3f-4264-a61a-3e94862024fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231992524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1231992524
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1599439560
Short name T533
Test name
Test status
Simulation time 752785338 ps
CPU time 10.71 seconds
Started Jul 07 06:55:39 PM PDT 24
Finished Jul 07 06:55:50 PM PDT 24
Peak memory 218204 kb
Host smart-3fba1743-5788-44b2-bb52-de915d2e0981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599439560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1599439560
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3686723516
Short name T647
Test name
Test status
Simulation time 1146847107 ps
CPU time 7.15 seconds
Started Jul 07 06:55:50 PM PDT 24
Finished Jul 07 06:55:57 PM PDT 24
Peak memory 217712 kb
Host smart-edb23489-a024-4d93-ab26-55d72405f104
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686723516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3686723516
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3765061468
Short name T471
Test name
Test status
Simulation time 3502578446 ps
CPU time 34.12 seconds
Started Jul 07 06:55:43 PM PDT 24
Finished Jul 07 06:56:17 PM PDT 24
Peak memory 219080 kb
Host smart-a431be6c-23fc-4d1c-ba4c-a56c827c961e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765061468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3765061468
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1809970511
Short name T615
Test name
Test status
Simulation time 211110265 ps
CPU time 2.88 seconds
Started Jul 07 06:55:44 PM PDT 24
Finished Jul 07 06:55:47 PM PDT 24
Peak memory 218248 kb
Host smart-920513b5-0070-4bc8-8a75-666d03198e2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809970511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1809970511
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.204272212
Short name T682
Test name
Test status
Simulation time 162811606 ps
CPU time 2.58 seconds
Started Jul 07 06:55:42 PM PDT 24
Finished Jul 07 06:55:45 PM PDT 24
Peak memory 217724 kb
Host smart-86dc5f7b-83ed-49f0-b7c3-908ed66245e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204272212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
204272212
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.321899956
Short name T367
Test name
Test status
Simulation time 27570665777 ps
CPU time 58.24 seconds
Started Jul 07 06:55:43 PM PDT 24
Finished Jul 07 06:56:42 PM PDT 24
Peak memory 268636 kb
Host smart-827b6e8a-cad0-442c-b5ed-94d8b7823512
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321899956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.321899956
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2567659627
Short name T827
Test name
Test status
Simulation time 1008337626 ps
CPU time 5.82 seconds
Started Jul 07 06:55:43 PM PDT 24
Finished Jul 07 06:55:49 PM PDT 24
Peak memory 222824 kb
Host smart-4e33e2dc-7b1d-4c60-bbfe-97f667cb6cab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567659627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2567659627
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3233579929
Short name T236
Test name
Test status
Simulation time 54357224 ps
CPU time 3.23 seconds
Started Jul 07 06:55:42 PM PDT 24
Finished Jul 07 06:55:45 PM PDT 24
Peak memory 222184 kb
Host smart-aebe0209-0005-4327-8d68-64b8e36bb65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233579929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3233579929
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.105440002
Short name T631
Test name
Test status
Simulation time 578181539 ps
CPU time 13.28 seconds
Started Jul 07 06:55:46 PM PDT 24
Finished Jul 07 06:55:59 PM PDT 24
Peak memory 225904 kb
Host smart-eb806f14-75e5-4707-821b-b9a986ef2efc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105440002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.105440002
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1347426326
Short name T735
Test name
Test status
Simulation time 1008896171 ps
CPU time 7.22 seconds
Started Jul 07 06:55:46 PM PDT 24
Finished Jul 07 06:55:53 PM PDT 24
Peak memory 226000 kb
Host smart-dd6d8574-0027-4ef0-9830-b960bb1ad72a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347426326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1347426326
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1472464635
Short name T177
Test name
Test status
Simulation time 1777028842 ps
CPU time 9.77 seconds
Started Jul 07 06:55:39 PM PDT 24
Finished Jul 07 06:55:49 PM PDT 24
Peak memory 226044 kb
Host smart-b6d2cf7e-640b-4698-9f57-5e0ea8b98a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472464635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1472464635
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1347942241
Short name T472
Test name
Test status
Simulation time 81280150 ps
CPU time 4.34 seconds
Started Jul 07 06:55:41 PM PDT 24
Finished Jul 07 06:55:46 PM PDT 24
Peak memory 217720 kb
Host smart-b4f4c716-4646-4de7-93a8-9873a40504dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347942241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1347942241
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1182637059
Short name T547
Test name
Test status
Simulation time 686140749 ps
CPU time 15.71 seconds
Started Jul 07 06:55:37 PM PDT 24
Finished Jul 07 06:55:53 PM PDT 24
Peak memory 250980 kb
Host smart-94b1469d-c2d0-4719-b9c1-1eb7024191d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182637059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1182637059
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1819558822
Short name T858
Test name
Test status
Simulation time 290267498 ps
CPU time 6.41 seconds
Started Jul 07 06:55:40 PM PDT 24
Finished Jul 07 06:55:47 PM PDT 24
Peak memory 247120 kb
Host smart-50c5b7e6-d2cd-40af-973a-8a521822d057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819558822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1819558822
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.4100463637
Short name T758
Test name
Test status
Simulation time 2052361070 ps
CPU time 43.81 seconds
Started Jul 07 06:55:47 PM PDT 24
Finished Jul 07 06:56:31 PM PDT 24
Peak memory 226720 kb
Host smart-5bfd8c2e-d322-458a-92a2-d980f2bdee31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100463637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.4100463637
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3328418642
Short name T485
Test name
Test status
Simulation time 22932769 ps
CPU time 1.02 seconds
Started Jul 07 06:55:40 PM PDT 24
Finished Jul 07 06:55:42 PM PDT 24
Peak memory 211932 kb
Host smart-f6bf7c61-7fad-41d5-841b-917255d0bf3c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328418642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3328418642
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2601526436
Short name T501
Test name
Test status
Simulation time 21785906 ps
CPU time 0.99 seconds
Started Jul 07 06:55:56 PM PDT 24
Finished Jul 07 06:55:57 PM PDT 24
Peak memory 209244 kb
Host smart-e75d6a3c-e0fb-4879-a8c4-4b2ad7b5491f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601526436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2601526436
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2451014302
Short name T794
Test name
Test status
Simulation time 280523525 ps
CPU time 12.86 seconds
Started Jul 07 06:55:52 PM PDT 24
Finished Jul 07 06:56:06 PM PDT 24
Peak memory 218228 kb
Host smart-8f312a99-3298-4308-8c89-620843084d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451014302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2451014302
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3581909372
Short name T681
Test name
Test status
Simulation time 753224633 ps
CPU time 2.22 seconds
Started Jul 07 06:55:54 PM PDT 24
Finished Jul 07 06:55:57 PM PDT 24
Peak memory 217084 kb
Host smart-8a5b17e1-262c-4a96-a857-251635150190
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581909372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3581909372
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.222749388
Short name T659
Test name
Test status
Simulation time 14635314751 ps
CPU time 97.82 seconds
Started Jul 07 06:55:53 PM PDT 24
Finished Jul 07 06:57:31 PM PDT 24
Peak memory 226100 kb
Host smart-070c9d27-6ce1-45cf-a05a-29ac05dd571f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222749388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.222749388
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3019145221
Short name T843
Test name
Test status
Simulation time 1370593055 ps
CPU time 7.06 seconds
Started Jul 07 06:55:53 PM PDT 24
Finished Jul 07 06:56:00 PM PDT 24
Peak memory 218244 kb
Host smart-c7d90489-841b-4daa-993c-85ac7b75d009
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019145221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3019145221
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1853549841
Short name T428
Test name
Test status
Simulation time 4201660992 ps
CPU time 11.31 seconds
Started Jul 07 06:55:50 PM PDT 24
Finished Jul 07 06:56:02 PM PDT 24
Peak memory 217896 kb
Host smart-c70b39cc-5514-42a7-89cd-5a1f64c2f7b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853549841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1853549841
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1009011238
Short name T816
Test name
Test status
Simulation time 1847983050 ps
CPU time 41.97 seconds
Started Jul 07 06:55:50 PM PDT 24
Finished Jul 07 06:56:32 PM PDT 24
Peak memory 275620 kb
Host smart-2d417eae-78b8-47cb-8ee5-2c05d348f656
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009011238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1009011238
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.688820267
Short name T591
Test name
Test status
Simulation time 1506717185 ps
CPU time 13.76 seconds
Started Jul 07 06:55:50 PM PDT 24
Finished Jul 07 06:56:04 PM PDT 24
Peak memory 250944 kb
Host smart-14060beb-db20-457c-a3c7-6a633df452a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688820267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.688820267
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3310471818
Short name T243
Test name
Test status
Simulation time 56631073 ps
CPU time 1.42 seconds
Started Jul 07 06:55:51 PM PDT 24
Finished Jul 07 06:55:53 PM PDT 24
Peak memory 221764 kb
Host smart-437d1405-d223-4d1a-af56-0f6a46a5fecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310471818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3310471818
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.529982305
Short name T551
Test name
Test status
Simulation time 380632052 ps
CPU time 11.61 seconds
Started Jul 07 06:55:55 PM PDT 24
Finished Jul 07 06:56:06 PM PDT 24
Peak memory 218984 kb
Host smart-05c6f982-4c27-492b-afa3-f901243f8173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529982305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.529982305
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2585676617
Short name T98
Test name
Test status
Simulation time 2309213326 ps
CPU time 21.92 seconds
Started Jul 07 06:55:54 PM PDT 24
Finished Jul 07 06:56:16 PM PDT 24
Peak memory 226068 kb
Host smart-b3ba4481-3331-4628-83cf-b7089918cfc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585676617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2585676617
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.928896638
Short name T709
Test name
Test status
Simulation time 1631694904 ps
CPU time 10.44 seconds
Started Jul 07 06:55:59 PM PDT 24
Finished Jul 07 06:56:10 PM PDT 24
Peak memory 226308 kb
Host smart-d34a6c0d-1d07-46f1-9e08-1b2f748c7d74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928896638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.928896638
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3828116069
Short name T427
Test name
Test status
Simulation time 1265924786 ps
CPU time 7.49 seconds
Started Jul 07 06:55:50 PM PDT 24
Finished Jul 07 06:55:58 PM PDT 24
Peak memory 218356 kb
Host smart-25dee77f-6a48-4bbe-ad7e-41b45358ca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828116069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3828116069
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.68369766
Short name T671
Test name
Test status
Simulation time 29476945 ps
CPU time 1.79 seconds
Started Jul 07 06:55:46 PM PDT 24
Finished Jul 07 06:55:48 PM PDT 24
Peak memory 214012 kb
Host smart-8e7854dc-ce7c-4780-b568-a871af37b4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68369766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.68369766
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3719670330
Short name T315
Test name
Test status
Simulation time 168216072 ps
CPU time 7.8 seconds
Started Jul 07 06:55:52 PM PDT 24
Finished Jul 07 06:56:01 PM PDT 24
Peak memory 250420 kb
Host smart-095fc267-2b21-48c1-831f-6102aedcad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719670330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3719670330
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.615604347
Short name T771
Test name
Test status
Simulation time 10890321560 ps
CPU time 255.72 seconds
Started Jul 07 06:55:54 PM PDT 24
Finished Jul 07 07:00:10 PM PDT 24
Peak memory 276496 kb
Host smart-e581d4b9-b3e8-49fa-9c6f-01976056009f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615604347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.615604347
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1693000802
Short name T151
Test name
Test status
Simulation time 6121366983 ps
CPU time 197.93 seconds
Started Jul 07 06:55:52 PM PDT 24
Finished Jul 07 06:59:11 PM PDT 24
Peak memory 284004 kb
Host smart-328b50d8-074e-4fa0-baae-8d3f098a609c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1693000802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1693000802
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.4257704741
Short name T844
Test name
Test status
Simulation time 12368703 ps
CPU time 0.9 seconds
Started Jul 07 06:55:52 PM PDT 24
Finished Jul 07 06:55:53 PM PDT 24
Peak memory 211932 kb
Host smart-bde97ef5-77e8-43f1-b663-4674fb8707b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257704741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.4257704741
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3875184346
Short name T337
Test name
Test status
Simulation time 65587706 ps
CPU time 1.18 seconds
Started Jul 07 06:56:01 PM PDT 24
Finished Jul 07 06:56:02 PM PDT 24
Peak memory 209056 kb
Host smart-d8a88814-5b70-427b-a8b4-43e83504956e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875184346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3875184346
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2457360991
Short name T415
Test name
Test status
Simulation time 175617125 ps
CPU time 8.3 seconds
Started Jul 07 06:55:57 PM PDT 24
Finished Jul 07 06:56:05 PM PDT 24
Peak memory 218240 kb
Host smart-bfe29d6c-3e43-4abe-af57-41e218599524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457360991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2457360991
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1127222356
Short name T795
Test name
Test status
Simulation time 557527021 ps
CPU time 5.26 seconds
Started Jul 07 06:55:59 PM PDT 24
Finished Jul 07 06:56:05 PM PDT 24
Peak memory 217416 kb
Host smart-14915b08-7aed-43d9-9043-2e4cc8ec313f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127222356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1127222356
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4235330352
Short name T640
Test name
Test status
Simulation time 65673591924 ps
CPU time 65.07 seconds
Started Jul 07 06:55:57 PM PDT 24
Finished Jul 07 06:57:02 PM PDT 24
Peak memory 218992 kb
Host smart-7934a5ca-a04f-4e5c-9a13-0f577d435b5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235330352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4235330352
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.548510820
Short name T224
Test name
Test status
Simulation time 414726308 ps
CPU time 12.8 seconds
Started Jul 07 06:56:01 PM PDT 24
Finished Jul 07 06:56:14 PM PDT 24
Peak memory 218240 kb
Host smart-b4732d0d-9cad-423c-9ae1-b4bd5a18e6f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548510820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.548510820
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1495901389
Short name T68
Test name
Test status
Simulation time 57003880 ps
CPU time 2.39 seconds
Started Jul 07 06:55:59 PM PDT 24
Finished Jul 07 06:56:01 PM PDT 24
Peak memory 217792 kb
Host smart-8eb89f0d-4297-447c-bb6a-99a80ecad3c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495901389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1495901389
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.4007310298
Short name T527
Test name
Test status
Simulation time 1989398579 ps
CPU time 50.57 seconds
Started Jul 07 06:55:59 PM PDT 24
Finished Jul 07 06:56:50 PM PDT 24
Peak memory 277352 kb
Host smart-ab7164cf-fd70-4cd0-9292-1b795e6bc7fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007310298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.4007310298
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.515562579
Short name T100
Test name
Test status
Simulation time 1799648381 ps
CPU time 13.04 seconds
Started Jul 07 06:56:00 PM PDT 24
Finished Jul 07 06:56:14 PM PDT 24
Peak memory 246356 kb
Host smart-a228259f-b2a6-4b7b-afba-00ce2609d3e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515562579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.515562579
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1608342772
Short name T402
Test name
Test status
Simulation time 119709342 ps
CPU time 2.8 seconds
Started Jul 07 06:56:01 PM PDT 24
Finished Jul 07 06:56:04 PM PDT 24
Peak memory 222220 kb
Host smart-40fc112a-0bb4-4730-9f48-8d8142ea94e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608342772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1608342772
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2781600952
Short name T701
Test name
Test status
Simulation time 664961658 ps
CPU time 8.62 seconds
Started Jul 07 06:56:02 PM PDT 24
Finished Jul 07 06:56:10 PM PDT 24
Peak memory 226048 kb
Host smart-52e8f308-2e6b-44ef-ad4d-f46f0ea74f07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781600952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2781600952
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4087860714
Short name T526
Test name
Test status
Simulation time 645801555 ps
CPU time 15.33 seconds
Started Jul 07 06:56:01 PM PDT 24
Finished Jul 07 06:56:17 PM PDT 24
Peak memory 225980 kb
Host smart-e369059c-952c-45c9-b01d-3dc2e5475f97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087860714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4087860714
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1698487188
Short name T831
Test name
Test status
Simulation time 349858678 ps
CPU time 12.03 seconds
Started Jul 07 06:55:58 PM PDT 24
Finished Jul 07 06:56:10 PM PDT 24
Peak memory 226300 kb
Host smart-5fe78de0-92cf-4988-bf91-4beee52d3592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698487188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1698487188
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.897771450
Short name T412
Test name
Test status
Simulation time 50002635 ps
CPU time 2.48 seconds
Started Jul 07 06:55:56 PM PDT 24
Finished Jul 07 06:55:58 PM PDT 24
Peak memory 223980 kb
Host smart-be20f2ac-6ae3-4198-b897-7e8cace9bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897771450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.897771450
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2950066973
Short name T545
Test name
Test status
Simulation time 542773442 ps
CPU time 31.53 seconds
Started Jul 07 06:55:58 PM PDT 24
Finished Jul 07 06:56:30 PM PDT 24
Peak memory 251004 kb
Host smart-0dc7cb6b-1fb2-4403-807d-a19d33cf3cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950066973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2950066973
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2190221527
Short name T275
Test name
Test status
Simulation time 79318165 ps
CPU time 7.8 seconds
Started Jul 07 06:55:59 PM PDT 24
Finished Jul 07 06:56:07 PM PDT 24
Peak memory 251236 kb
Host smart-53c40b9d-a41e-4a25-8aa9-6c1cbe8644ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190221527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2190221527
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2598331282
Short name T40
Test name
Test status
Simulation time 1827508352 ps
CPU time 63.5 seconds
Started Jul 07 06:56:04 PM PDT 24
Finished Jul 07 06:57:08 PM PDT 24
Peak memory 267360 kb
Host smart-b2a672ca-0999-459c-ae4c-218e399e5521
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598331282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2598331282
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.81172601
Short name T679
Test name
Test status
Simulation time 41716754467 ps
CPU time 1356.94 seconds
Started Jul 07 06:56:01 PM PDT 24
Finished Jul 07 07:18:38 PM PDT 24
Peak memory 349460 kb
Host smart-c392287b-6fdc-4207-b1ee-09acd6dcaa1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=81172601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.81172601
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1001331733
Short name T629
Test name
Test status
Simulation time 132731890 ps
CPU time 1.36 seconds
Started Jul 07 06:56:08 PM PDT 24
Finished Jul 07 06:56:10 PM PDT 24
Peak memory 209092 kb
Host smart-dfb4d40e-fd28-4381-bf41-5dc6c751182f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001331733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1001331733
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4128728542
Short name T555
Test name
Test status
Simulation time 469478546 ps
CPU time 11.95 seconds
Started Jul 07 06:56:08 PM PDT 24
Finished Jul 07 06:56:20 PM PDT 24
Peak memory 218220 kb
Host smart-e2efcedf-bf6c-496e-8fb0-84124aace977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128728542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4128728542
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3721686142
Short name T834
Test name
Test status
Simulation time 803532961 ps
CPU time 19.66 seconds
Started Jul 07 06:56:07 PM PDT 24
Finished Jul 07 06:56:27 PM PDT 24
Peak memory 217432 kb
Host smart-5b07cd97-2a59-45b0-b7d2-fa77d7867c4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721686142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3721686142
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2021097215
Short name T584
Test name
Test status
Simulation time 21048546191 ps
CPU time 41.58 seconds
Started Jul 07 06:56:09 PM PDT 24
Finished Jul 07 06:56:50 PM PDT 24
Peak memory 218816 kb
Host smart-90f98959-1409-40a2-b6fe-094330c874be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021097215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2021097215
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1293888915
Short name T554
Test name
Test status
Simulation time 1348332609 ps
CPU time 8.79 seconds
Started Jul 07 06:56:06 PM PDT 24
Finished Jul 07 06:56:15 PM PDT 24
Peak memory 218248 kb
Host smart-d8693b00-8635-4a7c-9972-65e5c62e7ac5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293888915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1293888915
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2137730391
Short name T311
Test name
Test status
Simulation time 786904924 ps
CPU time 3.33 seconds
Started Jul 07 06:56:03 PM PDT 24
Finished Jul 07 06:56:07 PM PDT 24
Peak memory 217700 kb
Host smart-895346eb-7c69-4a65-a525-bd249fcbe2e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137730391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2137730391
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3125940315
Short name T268
Test name
Test status
Simulation time 16649847004 ps
CPU time 81.33 seconds
Started Jul 07 06:56:06 PM PDT 24
Finished Jul 07 06:57:27 PM PDT 24
Peak memory 275864 kb
Host smart-0f41683f-8bf0-4c0f-99dd-915f1f3f8cec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125940315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3125940315
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.4159175146
Short name T641
Test name
Test status
Simulation time 733369005 ps
CPU time 17.15 seconds
Started Jul 07 06:56:06 PM PDT 24
Finished Jul 07 06:56:24 PM PDT 24
Peak memory 250968 kb
Host smart-e85f8918-f0ce-4392-9bfb-93e45fe9840f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159175146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.4159175146
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2178902723
Short name T525
Test name
Test status
Simulation time 73834660 ps
CPU time 3.23 seconds
Started Jul 07 06:56:04 PM PDT 24
Finished Jul 07 06:56:07 PM PDT 24
Peak memory 218228 kb
Host smart-4fce417b-fe83-4890-aa4b-435528f5732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178902723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2178902723
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1554360592
Short name T453
Test name
Test status
Simulation time 374269151 ps
CPU time 18.08 seconds
Started Jul 07 06:56:06 PM PDT 24
Finished Jul 07 06:56:25 PM PDT 24
Peak memory 226052 kb
Host smart-053cf18b-803a-4194-b8ae-132c4d317739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554360592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1554360592
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2114557414
Short name T748
Test name
Test status
Simulation time 1168273704 ps
CPU time 13.08 seconds
Started Jul 07 06:56:07 PM PDT 24
Finished Jul 07 06:56:20 PM PDT 24
Peak memory 226064 kb
Host smart-d9d997b4-6a52-40e2-8502-2b7f3e6d65d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114557414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2114557414
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.229785850
Short name T536
Test name
Test status
Simulation time 820686960 ps
CPU time 6.09 seconds
Started Jul 07 06:56:09 PM PDT 24
Finished Jul 07 06:56:15 PM PDT 24
Peak memory 218232 kb
Host smart-bca95c11-73ee-4802-8492-601f4d7628da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229785850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.229785850
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.341782513
Short name T734
Test name
Test status
Simulation time 207746444 ps
CPU time 9.89 seconds
Started Jul 07 06:56:04 PM PDT 24
Finished Jul 07 06:56:15 PM PDT 24
Peak memory 225908 kb
Host smart-8cc245ea-c576-48e8-bca9-c634ef0c0a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341782513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.341782513
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3425953598
Short name T229
Test name
Test status
Simulation time 419541037 ps
CPU time 3.21 seconds
Started Jul 07 06:56:01 PM PDT 24
Finished Jul 07 06:56:04 PM PDT 24
Peak memory 217672 kb
Host smart-f9376440-88ae-49ec-9bb3-628558d3c2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425953598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3425953598
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3896941612
Short name T652
Test name
Test status
Simulation time 550962180 ps
CPU time 18.5 seconds
Started Jul 07 06:56:04 PM PDT 24
Finished Jul 07 06:56:23 PM PDT 24
Peak memory 246016 kb
Host smart-91479ccc-29d9-44a3-b430-861585b00230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896941612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3896941612
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.948076771
Short name T830
Test name
Test status
Simulation time 142873060 ps
CPU time 7.58 seconds
Started Jul 07 06:56:05 PM PDT 24
Finished Jul 07 06:56:13 PM PDT 24
Peak memory 250984 kb
Host smart-70fbb70e-f543-4898-816c-7e5d30281b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948076771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.948076771
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2601728668
Short name T447
Test name
Test status
Simulation time 28278629356 ps
CPU time 212.11 seconds
Started Jul 07 06:56:08 PM PDT 24
Finished Jul 07 06:59:40 PM PDT 24
Peak memory 298164 kb
Host smart-320da9d2-e51e-4d0e-9ac5-c3b104e46b5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601728668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2601728668
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1857268988
Short name T581
Test name
Test status
Simulation time 24559588517 ps
CPU time 819.45 seconds
Started Jul 07 06:56:07 PM PDT 24
Finished Jul 07 07:09:47 PM PDT 24
Peak memory 364760 kb
Host smart-6442f2f5-0ba8-43ba-8684-4f202bccbbdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1857268988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1857268988
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3608064837
Short name T241
Test name
Test status
Simulation time 12039745 ps
CPU time 0.86 seconds
Started Jul 07 06:56:02 PM PDT 24
Finished Jul 07 06:56:04 PM PDT 24
Peak memory 208120 kb
Host smart-c988aa66-7306-4d15-aab4-e6a8db96dbb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608064837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3608064837
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.595442401
Short name T612
Test name
Test status
Simulation time 22754077 ps
CPU time 0.85 seconds
Started Jul 07 06:56:20 PM PDT 24
Finished Jul 07 06:56:22 PM PDT 24
Peak memory 208696 kb
Host smart-7b19e060-dee2-479e-8523-7777fe86ca87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595442401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.595442401
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.4047848887
Short name T560
Test name
Test status
Simulation time 335706276 ps
CPU time 11.54 seconds
Started Jul 07 06:56:13 PM PDT 24
Finished Jul 07 06:56:25 PM PDT 24
Peak memory 218228 kb
Host smart-576c5fef-df6a-4aad-9a7a-26566212b3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047848887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4047848887
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1774658599
Short name T650
Test name
Test status
Simulation time 320402702 ps
CPU time 2.02 seconds
Started Jul 07 06:56:15 PM PDT 24
Finished Jul 07 06:56:17 PM PDT 24
Peak memory 217196 kb
Host smart-094a8767-c789-4dae-b829-db0446146b2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774658599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1774658599
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3245355553
Short name T473
Test name
Test status
Simulation time 1652730141 ps
CPU time 28.02 seconds
Started Jul 07 06:56:10 PM PDT 24
Finished Jul 07 06:56:38 PM PDT 24
Peak memory 219000 kb
Host smart-50d5ad90-aa42-41f7-bdd7-b22d77b83ce7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245355553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3245355553
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4072147495
Short name T516
Test name
Test status
Simulation time 898193432 ps
CPU time 2.78 seconds
Started Jul 07 06:56:13 PM PDT 24
Finished Jul 07 06:56:16 PM PDT 24
Peak memory 221608 kb
Host smart-9b5910f7-f14f-438e-a44d-1965cfc71297
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072147495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4072147495
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.140860920
Short name T813
Test name
Test status
Simulation time 603230925 ps
CPU time 5.13 seconds
Started Jul 07 06:56:11 PM PDT 24
Finished Jul 07 06:56:17 PM PDT 24
Peak memory 217736 kb
Host smart-a795621e-f801-4ac8-b336-412ca2371b12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140860920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
140860920
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.177878421
Short name T512
Test name
Test status
Simulation time 8620315179 ps
CPU time 72.78 seconds
Started Jul 07 06:56:14 PM PDT 24
Finished Jul 07 06:57:27 PM PDT 24
Peak memory 267484 kb
Host smart-5dd7e3f1-eb5f-42cd-a195-74751e9fba17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177878421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.177878421
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1638223017
Short name T250
Test name
Test status
Simulation time 334878887 ps
CPU time 11.67 seconds
Started Jul 07 06:56:11 PM PDT 24
Finished Jul 07 06:56:22 PM PDT 24
Peak memory 250944 kb
Host smart-51101a04-1ef2-44e8-80d7-cff1ecbf2bc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638223017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1638223017
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4037691903
Short name T182
Test name
Test status
Simulation time 58501987 ps
CPU time 1.57 seconds
Started Jul 07 06:56:13 PM PDT 24
Finished Jul 07 06:56:15 PM PDT 24
Peak memory 218224 kb
Host smart-cb6af38e-00ba-4b09-891b-30f2d46d5054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037691903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4037691903
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3690705859
Short name T445
Test name
Test status
Simulation time 772596922 ps
CPU time 13.32 seconds
Started Jul 07 06:56:15 PM PDT 24
Finished Jul 07 06:56:28 PM PDT 24
Peak memory 226000 kb
Host smart-56f1bab6-d7cd-488c-b10c-9630cde83e6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690705859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3690705859
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1035088954
Short name T373
Test name
Test status
Simulation time 1038377724 ps
CPU time 10.66 seconds
Started Jul 07 06:56:14 PM PDT 24
Finished Jul 07 06:56:25 PM PDT 24
Peak memory 226048 kb
Host smart-72e1a5d0-3e22-4911-a4f1-2b60073ceb6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035088954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1035088954
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2915198010
Short name T574
Test name
Test status
Simulation time 199077344 ps
CPU time 7.7 seconds
Started Jul 07 06:56:16 PM PDT 24
Finished Jul 07 06:56:24 PM PDT 24
Peak memory 218248 kb
Host smart-6320196b-a65c-48d3-923e-e3333a668c0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915198010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2915198010
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3245109164
Short name T605
Test name
Test status
Simulation time 384025996 ps
CPU time 14.4 seconds
Started Jul 07 06:56:13 PM PDT 24
Finished Jul 07 06:56:28 PM PDT 24
Peak memory 218312 kb
Host smart-ec9f0642-fc97-41c1-836c-72ad5ddb0fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245109164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3245109164
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2965108656
Short name T106
Test name
Test status
Simulation time 51638944 ps
CPU time 1.33 seconds
Started Jul 07 06:56:09 PM PDT 24
Finished Jul 07 06:56:11 PM PDT 24
Peak memory 217840 kb
Host smart-213787c3-9f6b-47f5-9652-be2d0d56d042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965108656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2965108656
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1219249890
Short name T762
Test name
Test status
Simulation time 608883564 ps
CPU time 33.19 seconds
Started Jul 07 06:56:07 PM PDT 24
Finished Jul 07 06:56:40 PM PDT 24
Peak memory 250964 kb
Host smart-2fcf504a-e7d2-44a1-9e36-6dc8e67055c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219249890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1219249890
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.755486730
Short name T79
Test name
Test status
Simulation time 190252855 ps
CPU time 3.78 seconds
Started Jul 07 06:56:08 PM PDT 24
Finished Jul 07 06:56:12 PM PDT 24
Peak memory 226452 kb
Host smart-ff80c863-3252-4dc2-b19e-07bea52a7383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755486730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.755486730
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2293289732
Short name T599
Test name
Test status
Simulation time 7300220224 ps
CPU time 116.13 seconds
Started Jul 07 06:56:16 PM PDT 24
Finished Jul 07 06:58:13 PM PDT 24
Peak memory 251032 kb
Host smart-7ab898e1-baea-4f71-91ab-5500d714f44f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293289732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2293289732
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3854404192
Short name T775
Test name
Test status
Simulation time 10910284 ps
CPU time 0.77 seconds
Started Jul 07 06:56:09 PM PDT 24
Finished Jul 07 06:56:10 PM PDT 24
Peak memory 208136 kb
Host smart-2a723741-3513-4055-a080-78cca600de6b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854404192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3854404192
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3931523399
Short name T474
Test name
Test status
Simulation time 21205849 ps
CPU time 1.17 seconds
Started Jul 07 06:56:26 PM PDT 24
Finished Jul 07 06:56:28 PM PDT 24
Peak memory 209044 kb
Host smart-5abb7d3f-de49-4e77-b5bc-2dbea9681f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931523399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3931523399
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2451517083
Short name T684
Test name
Test status
Simulation time 383006725 ps
CPU time 13.07 seconds
Started Jul 07 06:56:21 PM PDT 24
Finished Jul 07 06:56:34 PM PDT 24
Peak memory 218220 kb
Host smart-2d574573-ec91-467d-a171-bca607e24255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451517083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2451517083
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2982507500
Short name T544
Test name
Test status
Simulation time 128813447 ps
CPU time 2.06 seconds
Started Jul 07 06:56:21 PM PDT 24
Finished Jul 07 06:56:24 PM PDT 24
Peak memory 217072 kb
Host smart-0187d2c2-9cc5-454b-acfe-1b6df3f73ba4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982507500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2982507500
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3652793860
Short name T489
Test name
Test status
Simulation time 9437466455 ps
CPU time 35.86 seconds
Started Jul 07 06:56:24 PM PDT 24
Finished Jul 07 06:57:00 PM PDT 24
Peak memory 226104 kb
Host smart-55216988-9642-4ef9-904d-1223de6e6410
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652793860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3652793860
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2414468174
Short name T247
Test name
Test status
Simulation time 1418465055 ps
CPU time 6.77 seconds
Started Jul 07 06:56:27 PM PDT 24
Finished Jul 07 06:56:34 PM PDT 24
Peak memory 223548 kb
Host smart-8b793f99-9c35-4a6b-ac19-70a5d934b15a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414468174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2414468174
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2240126889
Short name T520
Test name
Test status
Simulation time 177987374 ps
CPU time 1.89 seconds
Started Jul 07 06:56:20 PM PDT 24
Finished Jul 07 06:56:22 PM PDT 24
Peak memory 217672 kb
Host smart-392535bf-5525-4b50-b9ca-78a70100009e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240126889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2240126889
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3502041230
Short name T457
Test name
Test status
Simulation time 1990360585 ps
CPU time 61.59 seconds
Started Jul 07 06:56:21 PM PDT 24
Finished Jul 07 06:57:23 PM PDT 24
Peak memory 250980 kb
Host smart-0bbadfb7-78ef-4ab4-975c-4e1b3ddc6e82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502041230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3502041230
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1861000150
Short name T692
Test name
Test status
Simulation time 1937394255 ps
CPU time 9.98 seconds
Started Jul 07 06:56:21 PM PDT 24
Finished Jul 07 06:56:31 PM PDT 24
Peak memory 247532 kb
Host smart-a888e480-ff4c-47ef-9fee-d1c55dd137fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861000150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1861000150
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2825065425
Short name T722
Test name
Test status
Simulation time 100322469 ps
CPU time 2.44 seconds
Started Jul 07 06:56:22 PM PDT 24
Finished Jul 07 06:56:25 PM PDT 24
Peak memory 218272 kb
Host smart-a1dff5d0-8576-42c5-a5ac-dfec887a867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825065425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2825065425
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.947829187
Short name T776
Test name
Test status
Simulation time 826806428 ps
CPU time 15.7 seconds
Started Jul 07 06:56:23 PM PDT 24
Finished Jul 07 06:56:39 PM PDT 24
Peak memory 226012 kb
Host smart-0afb85d1-cf44-42ad-a2ba-16bf51f62371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947829187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.947829187
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3042246371
Short name T648
Test name
Test status
Simulation time 356213723 ps
CPU time 10.29 seconds
Started Jul 07 06:56:23 PM PDT 24
Finished Jul 07 06:56:33 PM PDT 24
Peak memory 218192 kb
Host smart-f8b1c6f7-fc2f-4a6c-bd07-706052f47520
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042246371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3042246371
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2191844980
Short name T571
Test name
Test status
Simulation time 271782542 ps
CPU time 10.77 seconds
Started Jul 07 06:56:22 PM PDT 24
Finished Jul 07 06:56:33 PM PDT 24
Peak memory 226084 kb
Host smart-9a345ff8-310b-4f49-9bf1-439b3c583c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191844980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2191844980
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1298705564
Short name T669
Test name
Test status
Simulation time 108749235 ps
CPU time 1.79 seconds
Started Jul 07 06:56:21 PM PDT 24
Finished Jul 07 06:56:23 PM PDT 24
Peak memory 213920 kb
Host smart-0b1ccb24-c42e-4132-9852-28af6bbc4759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298705564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1298705564
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2693289984
Short name T324
Test name
Test status
Simulation time 1661857051 ps
CPU time 27.7 seconds
Started Jul 07 06:56:20 PM PDT 24
Finished Jul 07 06:56:48 PM PDT 24
Peak memory 251016 kb
Host smart-da6e7f4a-d81a-4fe0-8c2d-0f4f13355060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693289984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2693289984
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3661227460
Short name T488
Test name
Test status
Simulation time 245961963 ps
CPU time 6.99 seconds
Started Jul 07 06:56:20 PM PDT 24
Finished Jul 07 06:56:28 PM PDT 24
Peak memory 250960 kb
Host smart-a32e587b-3c1b-4c3d-a8a5-504fb928c9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661227460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3661227460
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3110653061
Short name T803
Test name
Test status
Simulation time 1754824266 ps
CPU time 37.64 seconds
Started Jul 07 06:56:22 PM PDT 24
Finished Jul 07 06:56:59 PM PDT 24
Peak memory 225988 kb
Host smart-132dfb2b-16f5-4647-8297-aaed30255cf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110653061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3110653061
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1298521153
Short name T597
Test name
Test status
Simulation time 14756431 ps
CPU time 1.11 seconds
Started Jul 07 06:56:21 PM PDT 24
Finished Jul 07 06:56:22 PM PDT 24
Peak memory 211880 kb
Host smart-4088dce0-0dc3-4515-bf63-8c88ba073844
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298521153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1298521153
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2579375092
Short name T194
Test name
Test status
Simulation time 56679157 ps
CPU time 0.94 seconds
Started Jul 07 06:56:36 PM PDT 24
Finished Jul 07 06:56:37 PM PDT 24
Peak memory 208992 kb
Host smart-3e95fd87-dadd-480b-aaee-555b6b3abe6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579375092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2579375092
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1030343506
Short name T478
Test name
Test status
Simulation time 417423150 ps
CPU time 10.78 seconds
Started Jul 07 06:56:27 PM PDT 24
Finished Jul 07 06:56:38 PM PDT 24
Peak memory 218204 kb
Host smart-f601dc88-8aee-422c-8c92-bb1fa7dcea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030343506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1030343506
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.871582622
Short name T821
Test name
Test status
Simulation time 189902676 ps
CPU time 3.96 seconds
Started Jul 07 06:56:29 PM PDT 24
Finished Jul 07 06:56:33 PM PDT 24
Peak memory 217184 kb
Host smart-a849c3f1-15c2-48ac-9edd-0bb35ac452e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871582622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.871582622
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3435726959
Short name T814
Test name
Test status
Simulation time 15205712567 ps
CPU time 54.45 seconds
Started Jul 07 06:56:29 PM PDT 24
Finished Jul 07 06:57:23 PM PDT 24
Peak memory 226100 kb
Host smart-9c691a50-b87e-4998-920a-73a88109340f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435726959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3435726959
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1221790946
Short name T314
Test name
Test status
Simulation time 565114559 ps
CPU time 16.4 seconds
Started Jul 07 06:56:29 PM PDT 24
Finished Jul 07 06:56:46 PM PDT 24
Peak memory 218192 kb
Host smart-3c717528-a3aa-4adb-9570-ac7eb11da9b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221790946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1221790946
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3378924371
Short name T282
Test name
Test status
Simulation time 715790770 ps
CPU time 5.76 seconds
Started Jul 07 06:56:29 PM PDT 24
Finished Jul 07 06:56:35 PM PDT 24
Peak memory 217840 kb
Host smart-f1106c1d-21b2-4c2f-af49-5edd83c0256f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378924371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3378924371
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.512071003
Short name T596
Test name
Test status
Simulation time 991803441 ps
CPU time 42.24 seconds
Started Jul 07 06:56:30 PM PDT 24
Finished Jul 07 06:57:13 PM PDT 24
Peak memory 248948 kb
Host smart-18e828e2-dd28-42c1-9c42-b057d87991ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512071003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.512071003
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.116862146
Short name T271
Test name
Test status
Simulation time 6335374062 ps
CPU time 20.39 seconds
Started Jul 07 06:56:29 PM PDT 24
Finished Jul 07 06:56:49 PM PDT 24
Peak memory 251296 kb
Host smart-aad0175f-15a1-42c7-b318-2336136e1c68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116862146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.116862146
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1274018074
Short name T818
Test name
Test status
Simulation time 215316885 ps
CPU time 2.63 seconds
Started Jul 07 06:56:27 PM PDT 24
Finished Jul 07 06:56:30 PM PDT 24
Peak memory 218232 kb
Host smart-970cabee-83b4-489d-a725-c208ea29da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274018074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1274018074
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3562051766
Short name T825
Test name
Test status
Simulation time 1905845773 ps
CPU time 20.05 seconds
Started Jul 07 06:56:34 PM PDT 24
Finished Jul 07 06:56:54 PM PDT 24
Peak memory 226028 kb
Host smart-2d1dbe1a-9fa4-44c8-a011-e743114569ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562051766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3562051766
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.199067445
Short name T487
Test name
Test status
Simulation time 370168630 ps
CPU time 9.39 seconds
Started Jul 07 06:56:36 PM PDT 24
Finished Jul 07 06:56:45 PM PDT 24
Peak memory 218224 kb
Host smart-1dc50d95-fd8e-44a3-8090-080e48eeaa41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199067445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.199067445
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2089574
Short name T288
Test name
Test status
Simulation time 273045425 ps
CPU time 7.21 seconds
Started Jul 07 06:56:26 PM PDT 24
Finished Jul 07 06:56:34 PM PDT 24
Peak memory 218256 kb
Host smart-24d73cf5-b71e-4f2b-b17d-b903eee763bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2089574
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.530052434
Short name T769
Test name
Test status
Simulation time 50297864 ps
CPU time 2.84 seconds
Started Jul 07 06:56:27 PM PDT 24
Finished Jul 07 06:56:30 PM PDT 24
Peak memory 214244 kb
Host smart-228cad9b-5b7e-4585-ab8f-8efc977d8f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530052434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.530052434
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.4057992526
Short name T601
Test name
Test status
Simulation time 176591135 ps
CPU time 19.3 seconds
Started Jul 07 06:56:28 PM PDT 24
Finished Jul 07 06:56:48 PM PDT 24
Peak memory 250936 kb
Host smart-43e7432c-721f-4c1c-8659-72397c4c60cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057992526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.4057992526
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2471592883
Short name T222
Test name
Test status
Simulation time 57805553 ps
CPU time 3.56 seconds
Started Jul 07 06:56:28 PM PDT 24
Finished Jul 07 06:56:32 PM PDT 24
Peak memory 222640 kb
Host smart-37b73c18-59f1-43fb-b59b-9ed031cf51dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471592883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2471592883
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3732129376
Short name T706
Test name
Test status
Simulation time 3034860558 ps
CPU time 46.65 seconds
Started Jul 07 06:56:35 PM PDT 24
Finished Jul 07 06:57:21 PM PDT 24
Peak memory 217968 kb
Host smart-53777323-d9ee-4f00-a2d9-b103b0032c1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732129376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3732129376
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3225929933
Short name T464
Test name
Test status
Simulation time 16128576 ps
CPU time 1.03 seconds
Started Jul 07 06:56:28 PM PDT 24
Finished Jul 07 06:56:29 PM PDT 24
Peak memory 217720 kb
Host smart-ff041844-f186-4c44-ac6b-cc1803550efb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225929933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3225929933
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3545325569
Short name T82
Test name
Test status
Simulation time 37806705 ps
CPU time 0.86 seconds
Started Jul 07 06:53:28 PM PDT 24
Finished Jul 07 06:53:29 PM PDT 24
Peak memory 208772 kb
Host smart-0ba878f1-e7d7-4bdc-b674-51c247b2a633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545325569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3545325569
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1051976072
Short name T432
Test name
Test status
Simulation time 40595325 ps
CPU time 0.81 seconds
Started Jul 07 06:53:12 PM PDT 24
Finished Jul 07 06:53:13 PM PDT 24
Peak memory 208972 kb
Host smart-3f48de2e-11e9-4d30-9a18-6e979025a7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051976072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1051976072
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2115982349
Short name T429
Test name
Test status
Simulation time 1284396551 ps
CPU time 11.96 seconds
Started Jul 07 06:53:10 PM PDT 24
Finished Jul 07 06:53:22 PM PDT 24
Peak memory 218196 kb
Host smart-ed0844f9-7bbf-44f1-81a8-b3d46f324af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115982349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2115982349
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3036356028
Short name T452
Test name
Test status
Simulation time 272144743 ps
CPU time 2.06 seconds
Started Jul 07 06:53:19 PM PDT 24
Finished Jul 07 06:53:21 PM PDT 24
Peak memory 217132 kb
Host smart-a1790d53-4d25-41bb-97d5-301c5c929565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036356028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3036356028
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3515862455
Short name T630
Test name
Test status
Simulation time 1284191628 ps
CPU time 38.5 seconds
Started Jul 07 06:53:16 PM PDT 24
Finished Jul 07 06:53:55 PM PDT 24
Peak memory 218272 kb
Host smart-d8bd7ad2-d8d9-474a-8007-775c6faea6ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515862455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3515862455
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1819896585
Short name T63
Test name
Test status
Simulation time 2632522852 ps
CPU time 24.42 seconds
Started Jul 07 06:53:17 PM PDT 24
Finished Jul 07 06:53:42 PM PDT 24
Peak memory 217844 kb
Host smart-240a84a9-daf8-4339-8ba6-ec019ee05443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819896585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
819896585
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3514700292
Short name T807
Test name
Test status
Simulation time 496792253 ps
CPU time 15.15 seconds
Started Jul 07 06:53:17 PM PDT 24
Finished Jul 07 06:53:32 PM PDT 24
Peak memory 218188 kb
Host smart-3b938b4f-6234-4b0c-aae7-9081f555aaa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514700292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3514700292
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2480265383
Short name T793
Test name
Test status
Simulation time 4860935269 ps
CPU time 18.21 seconds
Started Jul 07 06:53:18 PM PDT 24
Finished Jul 07 06:53:36 PM PDT 24
Peak memory 217776 kb
Host smart-6d2b4477-8723-4a97-8669-337f7972514e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480265383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2480265383
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1505184498
Short name T67
Test name
Test status
Simulation time 959709526 ps
CPU time 3.84 seconds
Started Jul 07 06:53:13 PM PDT 24
Finished Jul 07 06:53:17 PM PDT 24
Peak memory 217696 kb
Host smart-f1e59086-153a-4b4e-9119-461919b22c38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505184498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1505184498
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1522582234
Short name T826
Test name
Test status
Simulation time 2055476488 ps
CPU time 72.89 seconds
Started Jul 07 06:53:18 PM PDT 24
Finished Jul 07 06:54:31 PM PDT 24
Peak memory 276112 kb
Host smart-5f707d98-364a-40ce-adff-f8eea44fc360
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522582234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1522582234
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1768703986
Short name T511
Test name
Test status
Simulation time 1791389992 ps
CPU time 14.2 seconds
Started Jul 07 06:53:17 PM PDT 24
Finished Jul 07 06:53:32 PM PDT 24
Peak memory 250980 kb
Host smart-4e052574-3d8a-4714-a1b5-ed7d24befb50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768703986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1768703986
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.4116469910
Short name T281
Test name
Test status
Simulation time 65387283 ps
CPU time 3.59 seconds
Started Jul 07 06:53:06 PM PDT 24
Finished Jul 07 06:53:10 PM PDT 24
Peak memory 222460 kb
Host smart-2f8a76a4-85de-41a8-becc-e2e812e55183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116469910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.4116469910
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2212135745
Short name T653
Test name
Test status
Simulation time 360044181 ps
CPU time 9.08 seconds
Started Jul 07 06:53:11 PM PDT 24
Finished Jul 07 06:53:20 PM PDT 24
Peak memory 217672 kb
Host smart-68829f07-bae9-43b2-a1ab-8482de9d7a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212135745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2212135745
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.377254089
Short name T80
Test name
Test status
Simulation time 141510271 ps
CPU time 23.3 seconds
Started Jul 07 06:53:28 PM PDT 24
Finished Jul 07 06:53:52 PM PDT 24
Peak memory 282636 kb
Host smart-5950dc09-67ee-4655-853e-c5252839b1f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377254089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.377254089
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2463778353
Short name T475
Test name
Test status
Simulation time 387877907 ps
CPU time 7.98 seconds
Started Jul 07 06:53:21 PM PDT 24
Finished Jul 07 06:53:30 PM PDT 24
Peak memory 218244 kb
Host smart-4d56e576-bcd0-49ab-8bf2-14616d9ea9c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463778353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2463778353
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1296746917
Short name T158
Test name
Test status
Simulation time 524711552 ps
CPU time 10.59 seconds
Started Jul 07 06:53:24 PM PDT 24
Finished Jul 07 06:53:35 PM PDT 24
Peak memory 226000 kb
Host smart-cc375f2f-87af-4e9d-8efd-255ed8afb8b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296746917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1296746917
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1057107128
Short name T828
Test name
Test status
Simulation time 268856479 ps
CPU time 7.06 seconds
Started Jul 07 06:53:21 PM PDT 24
Finished Jul 07 06:53:28 PM PDT 24
Peak memory 218148 kb
Host smart-d6c282bb-71c3-4e75-adc8-e48420ddcfe3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057107128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
057107128
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.949806358
Short name T220
Test name
Test status
Simulation time 1210176030 ps
CPU time 10.49 seconds
Started Jul 07 06:53:10 PM PDT 24
Finished Jul 07 06:53:20 PM PDT 24
Peak memory 225600 kb
Host smart-daadbe66-05d6-4015-ae4b-ad97302b0206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949806358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.949806358
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.311918041
Short name T77
Test name
Test status
Simulation time 791839036 ps
CPU time 5.44 seconds
Started Jul 07 06:53:05 PM PDT 24
Finished Jul 07 06:53:11 PM PDT 24
Peak memory 217712 kb
Host smart-fe63b5d1-2aaf-4da5-9814-96358759f597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311918041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.311918041
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1280038667
Short name T562
Test name
Test status
Simulation time 250244586 ps
CPU time 32.08 seconds
Started Jul 07 06:53:06 PM PDT 24
Finished Jul 07 06:53:38 PM PDT 24
Peak memory 250984 kb
Host smart-bcb8ad4f-5cc8-4d9c-b6a4-487a59210347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280038667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1280038667
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1323992502
Short name T753
Test name
Test status
Simulation time 156825593 ps
CPU time 3.55 seconds
Started Jul 07 06:53:07 PM PDT 24
Finished Jul 07 06:53:11 PM PDT 24
Peak memory 224304 kb
Host smart-bb664f7d-99da-461b-b66b-66ac97c74989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323992502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1323992502
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1579422903
Short name T174
Test name
Test status
Simulation time 20013631983 ps
CPU time 285.23 seconds
Started Jul 07 06:53:24 PM PDT 24
Finished Jul 07 06:58:10 PM PDT 24
Peak memory 283740 kb
Host smart-1b73e50a-b514-43c3-a3c0-87d453452619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579422903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1579422903
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.219027319
Short name T320
Test name
Test status
Simulation time 42716625 ps
CPU time 0.89 seconds
Started Jul 07 06:53:06 PM PDT 24
Finished Jul 07 06:53:07 PM PDT 24
Peak memory 211884 kb
Host smart-3f3e65e9-263b-4a2b-818e-ee8ff3cdc2a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219027319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.219027319
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2050189966
Short name T388
Test name
Test status
Simulation time 13003122 ps
CPU time 0.83 seconds
Started Jul 07 06:56:44 PM PDT 24
Finished Jul 07 06:56:45 PM PDT 24
Peak memory 209028 kb
Host smart-fe1c7ab4-6d48-4550-88b9-2edaecae2fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050189966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2050189966
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3910115256
Short name T598
Test name
Test status
Simulation time 1205896887 ps
CPU time 12.99 seconds
Started Jul 07 06:56:37 PM PDT 24
Finished Jul 07 06:56:51 PM PDT 24
Peak memory 218292 kb
Host smart-34d55fa8-3926-40d0-8e4c-782439c1e475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910115256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3910115256
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3897756329
Short name T438
Test name
Test status
Simulation time 1877758666 ps
CPU time 4.06 seconds
Started Jul 07 06:56:38 PM PDT 24
Finished Jul 07 06:56:42 PM PDT 24
Peak memory 217192 kb
Host smart-16ee721d-9af9-479d-97cc-eda54a734d4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897756329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3897756329
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.4096590520
Short name T663
Test name
Test status
Simulation time 1088935236 ps
CPU time 3.85 seconds
Started Jul 07 06:56:37 PM PDT 24
Finished Jul 07 06:56:41 PM PDT 24
Peak memory 222560 kb
Host smart-c02cc418-5b42-412a-b91a-7621ef3d9f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096590520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.4096590520
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3761764999
Short name T400
Test name
Test status
Simulation time 1173360132 ps
CPU time 12.63 seconds
Started Jul 07 06:56:38 PM PDT 24
Finished Jul 07 06:56:50 PM PDT 24
Peak memory 226000 kb
Host smart-85180873-e135-42a8-98ec-e38f2a28e2d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761764999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3761764999
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3283626816
Short name T651
Test name
Test status
Simulation time 1589789558 ps
CPU time 11.28 seconds
Started Jul 07 06:56:36 PM PDT 24
Finished Jul 07 06:56:48 PM PDT 24
Peak memory 226032 kb
Host smart-a79c324b-85a8-4f56-abde-30227846d825
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283626816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3283626816
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2204435941
Short name T466
Test name
Test status
Simulation time 1280557819 ps
CPU time 12.25 seconds
Started Jul 07 06:56:36 PM PDT 24
Finished Jul 07 06:56:48 PM PDT 24
Peak memory 218252 kb
Host smart-21761dd9-3857-4075-bfd4-2e9b586eaaea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204435941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2204435941
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2234895470
Short name T576
Test name
Test status
Simulation time 182982178 ps
CPU time 6.07 seconds
Started Jul 07 06:56:38 PM PDT 24
Finished Jul 07 06:56:44 PM PDT 24
Peak memory 218164 kb
Host smart-378fc45f-4d48-4939-9500-da5a2d6273ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234895470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2234895470
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1235874323
Short name T70
Test name
Test status
Simulation time 68746398 ps
CPU time 1.95 seconds
Started Jul 07 06:56:34 PM PDT 24
Finished Jul 07 06:56:36 PM PDT 24
Peak memory 217732 kb
Host smart-b37c8eaa-1c04-494e-a2b2-6e0793d752a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235874323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1235874323
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.14228568
Short name T546
Test name
Test status
Simulation time 383357168 ps
CPU time 27.59 seconds
Started Jul 07 06:56:41 PM PDT 24
Finished Jul 07 06:57:09 PM PDT 24
Peak memory 251224 kb
Host smart-8d6a990b-49c2-45b5-83ac-19551e4fc94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14228568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.14228568
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2849916125
Short name T160
Test name
Test status
Simulation time 109571022 ps
CPU time 6.44 seconds
Started Jul 07 06:56:37 PM PDT 24
Finished Jul 07 06:56:44 PM PDT 24
Peak memory 247188 kb
Host smart-27fe41e9-965a-4b1d-abfd-740bb74ca880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849916125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2849916125
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1738267293
Short name T155
Test name
Test status
Simulation time 23775220028 ps
CPU time 408.46 seconds
Started Jul 07 06:56:42 PM PDT 24
Finished Jul 07 07:03:31 PM PDT 24
Peak memory 298448 kb
Host smart-a28029f4-1b99-44f1-8764-871a1e7014d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1738267293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1738267293
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.430531382
Short name T719
Test name
Test status
Simulation time 10825067 ps
CPU time 0.85 seconds
Started Jul 07 06:56:36 PM PDT 24
Finished Jul 07 06:56:37 PM PDT 24
Peak memory 211988 kb
Host smart-02cc5543-001d-4de1-b64a-79c9b74b488a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430531382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.430531382
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.4221239565
Short name T624
Test name
Test status
Simulation time 62017242 ps
CPU time 0.89 seconds
Started Jul 07 06:56:47 PM PDT 24
Finished Jul 07 06:56:48 PM PDT 24
Peak memory 208992 kb
Host smart-522c3275-a02f-4e87-a87e-cf25ec07e77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221239565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.4221239565
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2941728222
Short name T88
Test name
Test status
Simulation time 521661757 ps
CPU time 11.35 seconds
Started Jul 07 06:56:45 PM PDT 24
Finished Jul 07 06:56:56 PM PDT 24
Peak memory 218228 kb
Host smart-f48bcc0f-b747-4312-9da0-ad92b1d94da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941728222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2941728222
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2592846326
Short name T444
Test name
Test status
Simulation time 106600365 ps
CPU time 2.14 seconds
Started Jul 07 06:56:47 PM PDT 24
Finished Jul 07 06:56:49 PM PDT 24
Peak memory 217424 kb
Host smart-2d6a8c4d-a9a9-4998-a15e-2d9d57f59e5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592846326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2592846326
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2765670878
Short name T374
Test name
Test status
Simulation time 76149794 ps
CPU time 2.79 seconds
Started Jul 07 06:56:45 PM PDT 24
Finished Jul 07 06:56:48 PM PDT 24
Peak memory 218272 kb
Host smart-433a7c0d-e477-4c86-a948-5f2ab31c74f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765670878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2765670878
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1243294768
Short name T838
Test name
Test status
Simulation time 2150452066 ps
CPU time 14.17 seconds
Started Jul 07 06:56:45 PM PDT 24
Finished Jul 07 06:56:59 PM PDT 24
Peak memory 218264 kb
Host smart-d51759d8-8c32-457e-8ce1-9b7dfe701c1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243294768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1243294768
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3193685925
Short name T756
Test name
Test status
Simulation time 1121500533 ps
CPU time 8.32 seconds
Started Jul 07 06:56:44 PM PDT 24
Finished Jul 07 06:56:53 PM PDT 24
Peak memory 225968 kb
Host smart-2103322e-db56-49f2-8907-0e99b96a17ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193685925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3193685925
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1203959873
Short name T458
Test name
Test status
Simulation time 1427883327 ps
CPU time 13.35 seconds
Started Jul 07 06:56:44 PM PDT 24
Finished Jul 07 06:56:58 PM PDT 24
Peak memory 218252 kb
Host smart-471fe102-13ad-4206-aeb5-e171858c1400
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203959873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1203959873
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.874724875
Short name T594
Test name
Test status
Simulation time 409519634 ps
CPU time 11.18 seconds
Started Jul 07 06:56:46 PM PDT 24
Finished Jul 07 06:56:57 PM PDT 24
Peak memory 218292 kb
Host smart-f1eb23a5-772e-4b09-956d-85c649a1a361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874724875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.874724875
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4287857310
Short name T358
Test name
Test status
Simulation time 135587938 ps
CPU time 2.94 seconds
Started Jul 07 06:56:40 PM PDT 24
Finished Jul 07 06:56:44 PM PDT 24
Peak memory 214864 kb
Host smart-3854b829-34a8-4403-8675-7f3eb908df84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287857310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4287857310
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.89877429
Short name T567
Test name
Test status
Simulation time 708363799 ps
CPU time 21.95 seconds
Started Jul 07 06:56:40 PM PDT 24
Finished Jul 07 06:57:02 PM PDT 24
Peak memory 250920 kb
Host smart-727a163e-6acb-4f72-9585-2f8f161dddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89877429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.89877429
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3669219285
Short name T193
Test name
Test status
Simulation time 425649025 ps
CPU time 5.12 seconds
Started Jul 07 06:56:45 PM PDT 24
Finished Jul 07 06:56:50 PM PDT 24
Peak memory 226412 kb
Host smart-12546584-0211-4bed-98ac-7158fbaa04e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669219285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3669219285
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3396826416
Short name T395
Test name
Test status
Simulation time 15955558773 ps
CPU time 201 seconds
Started Jul 07 06:56:44 PM PDT 24
Finished Jul 07 07:00:05 PM PDT 24
Peak memory 276528 kb
Host smart-e72d7b7d-4ac6-4d5a-a36f-505f7ef69417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396826416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3396826416
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3607644741
Short name T510
Test name
Test status
Simulation time 44481088 ps
CPU time 0.97 seconds
Started Jul 07 06:56:41 PM PDT 24
Finished Jul 07 06:56:42 PM PDT 24
Peak memory 211996 kb
Host smart-e3349ee4-602e-4d45-b00f-9f06b216cd58
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607644741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3607644741
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.159406765
Short name T476
Test name
Test status
Simulation time 84474100 ps
CPU time 1.1 seconds
Started Jul 07 06:56:55 PM PDT 24
Finished Jul 07 06:56:57 PM PDT 24
Peak memory 209108 kb
Host smart-01c4e604-6b28-4718-93e0-eea97113005d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159406765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.159406765
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.4067721550
Short name T765
Test name
Test status
Simulation time 1107732728 ps
CPU time 15.03 seconds
Started Jul 07 06:56:50 PM PDT 24
Finished Jul 07 06:57:05 PM PDT 24
Peak memory 218228 kb
Host smart-91c3d13a-e564-47e7-a7df-b242197aadb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067721550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.4067721550
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3404374183
Short name T704
Test name
Test status
Simulation time 847917603 ps
CPU time 3.11 seconds
Started Jul 07 06:56:50 PM PDT 24
Finished Jul 07 06:56:54 PM PDT 24
Peak memory 217176 kb
Host smart-e41c76df-548e-4b2c-a70b-a4ffbd269821
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404374183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3404374183
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3088365513
Short name T577
Test name
Test status
Simulation time 42631117 ps
CPU time 2.63 seconds
Started Jul 07 06:56:52 PM PDT 24
Finished Jul 07 06:56:55 PM PDT 24
Peak memory 222272 kb
Host smart-ea4b83cc-4e8f-4571-8926-6f8d6e4f7f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088365513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3088365513
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1033426040
Short name T590
Test name
Test status
Simulation time 243923668 ps
CPU time 12.71 seconds
Started Jul 07 06:56:48 PM PDT 24
Finished Jul 07 06:57:01 PM PDT 24
Peak memory 218928 kb
Host smart-4be4a661-5944-42fe-b4cc-6a11585ccc47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033426040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1033426040
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.807010347
Short name T604
Test name
Test status
Simulation time 303322584 ps
CPU time 12.58 seconds
Started Jul 07 06:56:48 PM PDT 24
Finished Jul 07 06:57:01 PM PDT 24
Peak memory 226048 kb
Host smart-ef509c70-1404-44eb-8466-b393ee9f59f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807010347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.807010347
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3988474705
Short name T450
Test name
Test status
Simulation time 655963347 ps
CPU time 9.18 seconds
Started Jul 07 06:56:54 PM PDT 24
Finished Jul 07 06:57:03 PM PDT 24
Peak memory 218220 kb
Host smart-4cf933ef-c47b-4b84-b31f-24c0ba517c45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988474705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3988474705
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3011265571
Short name T845
Test name
Test status
Simulation time 809198843 ps
CPU time 9.32 seconds
Started Jul 07 06:56:53 PM PDT 24
Finished Jul 07 06:57:03 PM PDT 24
Peak memory 226068 kb
Host smart-38db5a55-6899-427f-8251-52ea8ca33b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011265571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3011265571
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4253236953
Short name T172
Test name
Test status
Simulation time 255698611 ps
CPU time 2.89 seconds
Started Jul 07 06:56:53 PM PDT 24
Finished Jul 07 06:56:56 PM PDT 24
Peak memory 214932 kb
Host smart-946eccaa-9a71-4507-96ec-a6459498e5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253236953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4253236953
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1140409355
Short name T635
Test name
Test status
Simulation time 479603057 ps
CPU time 24.88 seconds
Started Jul 07 06:56:53 PM PDT 24
Finished Jul 07 06:57:18 PM PDT 24
Peak memory 251040 kb
Host smart-e0149869-7652-4633-8258-23adb1912878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140409355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1140409355
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3798653581
Short name T579
Test name
Test status
Simulation time 433855528 ps
CPU time 6.7 seconds
Started Jul 07 06:56:48 PM PDT 24
Finished Jul 07 06:56:55 PM PDT 24
Peak memory 250364 kb
Host smart-b0e32cf1-b487-439b-b878-17e696b0ebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798653581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3798653581
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3746792696
Short name T92
Test name
Test status
Simulation time 1639294368 ps
CPU time 64.32 seconds
Started Jul 07 06:56:52 PM PDT 24
Finished Jul 07 06:57:57 PM PDT 24
Peak memory 268544 kb
Host smart-c8a9f789-1e8b-4196-b805-67f91af0136f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746792696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3746792696
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3407394000
Short name T191
Test name
Test status
Simulation time 18703681 ps
CPU time 0.95 seconds
Started Jul 07 06:56:56 PM PDT 24
Finished Jul 07 06:56:57 PM PDT 24
Peak memory 211904 kb
Host smart-72e40252-0bb9-4209-b9e2-30332306f046
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407394000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3407394000
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1393613550
Short name T660
Test name
Test status
Simulation time 13734085 ps
CPU time 0.87 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:56:59 PM PDT 24
Peak memory 209012 kb
Host smart-17286582-079f-4ec7-b7dd-4743c422cd5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393613550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1393613550
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2074094381
Short name T717
Test name
Test status
Simulation time 682861450 ps
CPU time 10.32 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:57:08 PM PDT 24
Peak memory 226032 kb
Host smart-d35af1ef-995e-47f2-91f7-d618dca146e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074094381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2074094381
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2652702852
Short name T36
Test name
Test status
Simulation time 679376877 ps
CPU time 5.67 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:57:04 PM PDT 24
Peak memory 217304 kb
Host smart-41523394-7381-46f6-8ab5-25a5cbb968a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652702852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2652702852
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.752385249
Short name T785
Test name
Test status
Simulation time 146287222 ps
CPU time 2.14 seconds
Started Jul 07 06:57:00 PM PDT 24
Finished Jul 07 06:57:02 PM PDT 24
Peak memory 218232 kb
Host smart-dd197cfd-d336-4d04-a030-49ac5e736887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752385249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.752385249
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3173497849
Short name T433
Test name
Test status
Simulation time 1195424160 ps
CPU time 16.07 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:57:14 PM PDT 24
Peak memory 226024 kb
Host smart-83477544-5aae-46c7-b69d-95e34f8a2788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173497849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3173497849
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2598582052
Short name T529
Test name
Test status
Simulation time 4347360478 ps
CPU time 12.69 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:57:11 PM PDT 24
Peak memory 226364 kb
Host smart-6432cb65-17c0-4572-a26b-26472eb8c425
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598582052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2598582052
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1184395407
Short name T833
Test name
Test status
Simulation time 2604024624 ps
CPU time 7.25 seconds
Started Jul 07 06:56:59 PM PDT 24
Finished Jul 07 06:57:07 PM PDT 24
Peak memory 218300 kb
Host smart-f96ddddb-69ef-46d9-8784-b655f447401b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184395407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1184395407
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1731075931
Short name T840
Test name
Test status
Simulation time 203753948 ps
CPU time 9.07 seconds
Started Jul 07 06:56:56 PM PDT 24
Finished Jul 07 06:57:06 PM PDT 24
Peak memory 218288 kb
Host smart-aa02625d-d715-4ec7-aaf1-7f1edcb7aa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731075931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1731075931
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.21642180
Short name T407
Test name
Test status
Simulation time 91651848 ps
CPU time 2.68 seconds
Started Jul 07 06:56:54 PM PDT 24
Finished Jul 07 06:56:57 PM PDT 24
Peak memory 214268 kb
Host smart-a04f311c-d43e-4581-86c9-1e59e3fdfb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21642180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.21642180
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1773679625
Short name T192
Test name
Test status
Simulation time 394906198 ps
CPU time 25.02 seconds
Started Jul 07 06:56:53 PM PDT 24
Finished Jul 07 06:57:18 PM PDT 24
Peak memory 250984 kb
Host smart-d412245b-3d85-422f-8515-93c31cdc90b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773679625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1773679625
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3323172473
Short name T740
Test name
Test status
Simulation time 82074656 ps
CPU time 8.28 seconds
Started Jul 07 06:56:53 PM PDT 24
Finished Jul 07 06:57:01 PM PDT 24
Peak memory 250976 kb
Host smart-0c64fd50-cd3d-4b30-8c82-e48dc0f00ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323172473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3323172473
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3930524375
Short name T115
Test name
Test status
Simulation time 9279318782 ps
CPU time 107.33 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:58:45 PM PDT 24
Peak memory 275852 kb
Host smart-7af62a6a-bfe4-419d-8437-6700141ea48a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930524375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3930524375
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3996585263
Short name T152
Test name
Test status
Simulation time 108703980315 ps
CPU time 535.77 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 07:05:54 PM PDT 24
Peak memory 282932 kb
Host smart-8070a603-adad-459a-9121-5ecb1a8b441f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3996585263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3996585263
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2429094817
Short name T675
Test name
Test status
Simulation time 12537513 ps
CPU time 0.92 seconds
Started Jul 07 06:56:53 PM PDT 24
Finished Jul 07 06:56:54 PM PDT 24
Peak memory 211892 kb
Host smart-fd696105-79d9-4f1c-9084-c09298b6b210
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429094817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2429094817
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.6182329
Short name T632
Test name
Test status
Simulation time 52840746 ps
CPU time 1.05 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:57:00 PM PDT 24
Peak memory 209076 kb
Host smart-c0830d9c-d602-449d-8da2-854c832d0f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6182329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.6182329
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2940280174
Short name T490
Test name
Test status
Simulation time 896216186 ps
CPU time 11.53 seconds
Started Jul 07 06:56:57 PM PDT 24
Finished Jul 07 06:57:08 PM PDT 24
Peak memory 226032 kb
Host smart-d92c937a-afd7-4555-952e-a298f9477bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940280174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2940280174
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.291343844
Short name T857
Test name
Test status
Simulation time 61788648 ps
CPU time 1.21 seconds
Started Jul 07 06:57:00 PM PDT 24
Finished Jul 07 06:57:01 PM PDT 24
Peak memory 217048 kb
Host smart-8868ea5a-f337-432a-8923-b3f03d514610
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291343844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.291343844
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2906345335
Short name T246
Test name
Test status
Simulation time 264964248 ps
CPU time 3.17 seconds
Started Jul 07 06:57:00 PM PDT 24
Finished Jul 07 06:57:03 PM PDT 24
Peak memory 218216 kb
Host smart-c5c45b5a-7639-47ee-9c41-71259eecbfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906345335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2906345335
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2670590041
Short name T644
Test name
Test status
Simulation time 1130921815 ps
CPU time 12.78 seconds
Started Jul 07 06:56:59 PM PDT 24
Finished Jul 07 06:57:12 PM PDT 24
Peak memory 218560 kb
Host smart-d008763d-26b4-4f4b-99fc-67bb9805c25d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670590041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2670590041
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1591270790
Short name T662
Test name
Test status
Simulation time 158720159 ps
CPU time 7.98 seconds
Started Jul 07 06:57:01 PM PDT 24
Finished Jul 07 06:57:09 PM PDT 24
Peak memory 226036 kb
Host smart-d3924a9f-b560-4ffd-9b08-d968e621b991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591270790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1591270790
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.154408442
Short name T573
Test name
Test status
Simulation time 3325530159 ps
CPU time 10.57 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:57:09 PM PDT 24
Peak memory 226096 kb
Host smart-dce39c2d-e92c-4f26-b1a4-f3d20803075f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154408442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.154408442
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1760223286
Short name T278
Test name
Test status
Simulation time 811427280 ps
CPU time 6.88 seconds
Started Jul 07 06:57:00 PM PDT 24
Finished Jul 07 06:57:07 PM PDT 24
Peak memory 224844 kb
Host smart-59026349-3979-4106-bad1-7600de70430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760223286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1760223286
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1127844894
Short name T74
Test name
Test status
Simulation time 44941561 ps
CPU time 2.79 seconds
Started Jul 07 06:56:57 PM PDT 24
Finished Jul 07 06:57:00 PM PDT 24
Peak memory 217844 kb
Host smart-fec6116b-510c-4617-a101-04e371b9d9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127844894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1127844894
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.165264496
Short name T446
Test name
Test status
Simulation time 289709744 ps
CPU time 36.04 seconds
Started Jul 07 06:56:59 PM PDT 24
Finished Jul 07 06:57:36 PM PDT 24
Peak memory 251000 kb
Host smart-3566ff85-f1ac-47ee-94ab-59b7c173dc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165264496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.165264496
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1633995860
Short name T674
Test name
Test status
Simulation time 220845531 ps
CPU time 7.11 seconds
Started Jul 07 06:56:57 PM PDT 24
Finished Jul 07 06:57:04 PM PDT 24
Peak memory 246668 kb
Host smart-9c786cbe-b7e7-479b-b81b-fbd3b1c39808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633995860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1633995860
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.292863089
Short name T521
Test name
Test status
Simulation time 5117122786 ps
CPU time 55.35 seconds
Started Jul 07 06:57:01 PM PDT 24
Finished Jul 07 06:57:56 PM PDT 24
Peak memory 250920 kb
Host smart-e74e7041-5fa0-4211-979f-5573276c707a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292863089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.292863089
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3374544192
Short name T467
Test name
Test status
Simulation time 19502408 ps
CPU time 1.04 seconds
Started Jul 07 06:56:57 PM PDT 24
Finished Jul 07 06:56:58 PM PDT 24
Peak memory 211648 kb
Host smart-e3b20bfa-e7f0-4c32-998d-c35c11d0b2f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374544192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3374544192
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.852025928
Short name T93
Test name
Test status
Simulation time 14464397 ps
CPU time 0.89 seconds
Started Jul 07 06:57:06 PM PDT 24
Finished Jul 07 06:57:07 PM PDT 24
Peak memory 209004 kb
Host smart-ca6694e7-d06b-44ac-98c1-b3dca173678c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852025928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.852025928
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3403936542
Short name T522
Test name
Test status
Simulation time 535665987 ps
CPU time 9.77 seconds
Started Jul 07 06:57:07 PM PDT 24
Finished Jul 07 06:57:17 PM PDT 24
Peak memory 218156 kb
Host smart-fe6f86a0-8756-4325-a4f3-270f47200899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403936542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3403936542
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.4153001112
Short name T331
Test name
Test status
Simulation time 1859388404 ps
CPU time 5.95 seconds
Started Jul 07 06:57:06 PM PDT 24
Finished Jul 07 06:57:12 PM PDT 24
Peak memory 217276 kb
Host smart-937f2d6e-cabf-49c7-a986-1ff7ebcbcedd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153001112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.4153001112
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1041050435
Short name T405
Test name
Test status
Simulation time 83831889 ps
CPU time 3.92 seconds
Started Jul 07 06:57:05 PM PDT 24
Finished Jul 07 06:57:09 PM PDT 24
Peak memory 222584 kb
Host smart-b88ac26f-857b-47da-acdb-51227f7602a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041050435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1041050435
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1555172498
Short name T837
Test name
Test status
Simulation time 5729664841 ps
CPU time 17.67 seconds
Started Jul 07 06:57:02 PM PDT 24
Finished Jul 07 06:57:20 PM PDT 24
Peak memory 226112 kb
Host smart-b258446e-06ea-4d94-b892-cfae37487df3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555172498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1555172498
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.209815329
Short name T248
Test name
Test status
Simulation time 9659590936 ps
CPU time 22.31 seconds
Started Jul 07 06:57:04 PM PDT 24
Finished Jul 07 06:57:27 PM PDT 24
Peak memory 226112 kb
Host smart-1e6a93bb-f642-4108-be31-0f25feec74b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209815329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.209815329
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2355725316
Short name T518
Test name
Test status
Simulation time 233789270 ps
CPU time 6.54 seconds
Started Jul 07 06:57:03 PM PDT 24
Finished Jul 07 06:57:10 PM PDT 24
Peak memory 218228 kb
Host smart-3f2575fc-f3bc-4480-b6c0-1604616c269b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355725316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2355725316
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2027994200
Short name T690
Test name
Test status
Simulation time 1911502663 ps
CPU time 10.55 seconds
Started Jul 07 06:57:03 PM PDT 24
Finished Jul 07 06:57:14 PM PDT 24
Peak memory 226056 kb
Host smart-b998253e-fe2c-4668-a0e8-dd740e468716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027994200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2027994200
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1903143914
Short name T384
Test name
Test status
Simulation time 57445583 ps
CPU time 2.49 seconds
Started Jul 07 06:56:58 PM PDT 24
Finished Jul 07 06:57:01 PM PDT 24
Peak memory 217728 kb
Host smart-e41ab2b3-9b89-49c8-8dac-683c1bf9e171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903143914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1903143914
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2371780014
Short name T860
Test name
Test status
Simulation time 221468228 ps
CPU time 25.89 seconds
Started Jul 07 06:57:02 PM PDT 24
Finished Jul 07 06:57:28 PM PDT 24
Peak memory 247728 kb
Host smart-99e956f3-af5e-4397-af77-57bf2563492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371780014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2371780014
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.810806063
Short name T602
Test name
Test status
Simulation time 48566133 ps
CPU time 6.88 seconds
Started Jul 07 06:57:03 PM PDT 24
Finished Jul 07 06:57:10 PM PDT 24
Peak memory 250568 kb
Host smart-bae62d0e-80e7-49c7-96c4-fabce055eb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810806063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.810806063
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.4163468795
Short name T95
Test name
Test status
Simulation time 13775051743 ps
CPU time 226.73 seconds
Started Jul 07 06:57:03 PM PDT 24
Finished Jul 07 07:00:51 PM PDT 24
Peak memory 258448 kb
Host smart-bd0cf035-924e-429c-a628-baf3abe9d499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163468795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.4163468795
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.156225156
Short name T764
Test name
Test status
Simulation time 18310609 ps
CPU time 0.89 seconds
Started Jul 07 06:57:01 PM PDT 24
Finished Jul 07 06:57:02 PM PDT 24
Peak memory 211884 kb
Host smart-03c11017-4c4c-4e18-b3ec-eb503c536372
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156225156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.156225156
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2214271919
Short name T372
Test name
Test status
Simulation time 22429510 ps
CPU time 0.89 seconds
Started Jul 07 06:57:13 PM PDT 24
Finished Jul 07 06:57:14 PM PDT 24
Peak memory 208964 kb
Host smart-19053a52-900e-4243-aeca-3a700bc1b1b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214271919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2214271919
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1255340542
Short name T355
Test name
Test status
Simulation time 289195808 ps
CPU time 14.79 seconds
Started Jul 07 06:57:08 PM PDT 24
Finished Jul 07 06:57:24 PM PDT 24
Peak memory 226044 kb
Host smart-e403a7f6-19e8-46f9-8b93-60cb3447d392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255340542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1255340542
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.770577709
Short name T292
Test name
Test status
Simulation time 5470966910 ps
CPU time 7.32 seconds
Started Jul 07 06:57:10 PM PDT 24
Finished Jul 07 06:57:17 PM PDT 24
Peak memory 217648 kb
Host smart-6291ff0d-5fbb-4ad7-8a4f-191ba29bb2cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770577709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.770577709
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2351110285
Short name T303
Test name
Test status
Simulation time 84641080 ps
CPU time 1.55 seconds
Started Jul 07 06:57:06 PM PDT 24
Finished Jul 07 06:57:08 PM PDT 24
Peak memory 218148 kb
Host smart-ed14726f-0f93-4c7b-9ded-8cdbb4ee3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351110285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2351110285
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3427858981
Short name T339
Test name
Test status
Simulation time 1357595933 ps
CPU time 11.92 seconds
Started Jul 07 06:57:11 PM PDT 24
Finished Jul 07 06:57:23 PM PDT 24
Peak memory 225988 kb
Host smart-c3773d0f-3fd8-49c3-b21a-35e2d626e0e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427858981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3427858981
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2901119142
Short name T266
Test name
Test status
Simulation time 441664251 ps
CPU time 10.5 seconds
Started Jul 07 06:57:12 PM PDT 24
Finished Jul 07 06:57:23 PM PDT 24
Peak memory 218248 kb
Host smart-90ffccf5-df56-4062-a795-45f5c138520d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901119142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2901119142
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.4205651491
Short name T107
Test name
Test status
Simulation time 356468768 ps
CPU time 14.75 seconds
Started Jul 07 06:57:11 PM PDT 24
Finished Jul 07 06:57:26 PM PDT 24
Peak memory 226068 kb
Host smart-0a4e3897-bc66-4ea7-8b6f-b6fd087255ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205651491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4205651491
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3986805276
Short name T56
Test name
Test status
Simulation time 145008360 ps
CPU time 3.06 seconds
Started Jul 07 06:57:08 PM PDT 24
Finished Jul 07 06:57:11 PM PDT 24
Peak memory 214816 kb
Host smart-a0bfec7a-4d68-4277-a9ce-64fdbd5c3dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986805276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3986805276
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3052215158
Short name T819
Test name
Test status
Simulation time 266326252 ps
CPU time 31.39 seconds
Started Jul 07 06:57:07 PM PDT 24
Finished Jul 07 06:57:39 PM PDT 24
Peak memory 250976 kb
Host smart-b4dd590c-c602-4005-925d-a5b6959a3802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052215158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3052215158
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.593555363
Short name T15
Test name
Test status
Simulation time 288047267 ps
CPU time 5.5 seconds
Started Jul 07 06:57:06 PM PDT 24
Finished Jul 07 06:57:12 PM PDT 24
Peak memory 226392 kb
Host smart-a2e9398f-5c33-47da-9d55-7c969828c2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593555363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.593555363
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1321677913
Short name T197
Test name
Test status
Simulation time 1069391061 ps
CPU time 56.56 seconds
Started Jul 07 06:57:15 PM PDT 24
Finished Jul 07 06:58:12 PM PDT 24
Peak memory 226140 kb
Host smart-b3c8a96c-a6f3-47b7-9fbf-62c12e1aae1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321677913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1321677913
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2619511494
Short name T686
Test name
Test status
Simulation time 21682110 ps
CPU time 1.04 seconds
Started Jul 07 06:57:09 PM PDT 24
Finished Jul 07 06:57:10 PM PDT 24
Peak memory 211868 kb
Host smart-c3909aef-3573-47a4-96cf-3b322a799ab8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619511494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2619511494
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.282054902
Short name T557
Test name
Test status
Simulation time 53659856 ps
CPU time 1.34 seconds
Started Jul 07 06:57:18 PM PDT 24
Finished Jul 07 06:57:20 PM PDT 24
Peak memory 208892 kb
Host smart-c3c971ca-3b07-4337-9a15-2549ddc95c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282054902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.282054902
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3764899872
Short name T618
Test name
Test status
Simulation time 274699084 ps
CPU time 12.24 seconds
Started Jul 07 06:57:19 PM PDT 24
Finished Jul 07 06:57:31 PM PDT 24
Peak memory 218216 kb
Host smart-7d352fea-6049-478b-b41b-fed1cabb948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764899872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3764899872
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1058662473
Short name T87
Test name
Test status
Simulation time 1152143308 ps
CPU time 3.38 seconds
Started Jul 07 06:57:17 PM PDT 24
Finished Jul 07 06:57:20 PM PDT 24
Peak memory 217192 kb
Host smart-c80facb1-1eca-4004-90fa-86ab5242d56a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058662473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1058662473
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3736904106
Short name T417
Test name
Test status
Simulation time 257914921 ps
CPU time 5.52 seconds
Started Jul 07 06:57:17 PM PDT 24
Finished Jul 07 06:57:23 PM PDT 24
Peak memory 218220 kb
Host smart-40b27174-1921-451e-a48c-c5e7a3117a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736904106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3736904106
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3524909286
Short name T832
Test name
Test status
Simulation time 974299751 ps
CPU time 11.56 seconds
Started Jul 07 06:57:17 PM PDT 24
Finished Jul 07 06:57:29 PM PDT 24
Peak memory 226040 kb
Host smart-86914dd9-35f6-45da-b28d-a428646a1e3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524909286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3524909286
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3427161760
Short name T680
Test name
Test status
Simulation time 1121782558 ps
CPU time 11.45 seconds
Started Jul 07 06:57:16 PM PDT 24
Finished Jul 07 06:57:27 PM PDT 24
Peak memory 226300 kb
Host smart-8a9d9519-b5ff-4100-bfc9-e2e2149f9d35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427161760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3427161760
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3065074306
Short name T285
Test name
Test status
Simulation time 365992285 ps
CPU time 12.37 seconds
Started Jul 07 06:57:17 PM PDT 24
Finished Jul 07 06:57:30 PM PDT 24
Peak memory 218244 kb
Host smart-4c6696d4-726d-47ad-9dbf-8299637808c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065074306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3065074306
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.235281654
Short name T414
Test name
Test status
Simulation time 471946258 ps
CPU time 11.58 seconds
Started Jul 07 06:57:13 PM PDT 24
Finished Jul 07 06:57:25 PM PDT 24
Peak memory 218436 kb
Host smart-2f92519c-3a0a-4518-8dda-1d9bbfa9c052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235281654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.235281654
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1922778477
Short name T228
Test name
Test status
Simulation time 592575463 ps
CPU time 1.5 seconds
Started Jul 07 06:57:12 PM PDT 24
Finished Jul 07 06:57:14 PM PDT 24
Peak memory 217724 kb
Host smart-f98b18d3-7668-4515-b158-37fe7f71f207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922778477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1922778477
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1585999402
Short name T566
Test name
Test status
Simulation time 244891433 ps
CPU time 23.75 seconds
Started Jul 07 06:57:12 PM PDT 24
Finished Jul 07 06:57:36 PM PDT 24
Peak memory 250944 kb
Host smart-bbb440db-8b80-4a5f-95df-9df619e520a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585999402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1585999402
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1934334879
Short name T658
Test name
Test status
Simulation time 108714521 ps
CPU time 8.73 seconds
Started Jul 07 06:57:16 PM PDT 24
Finished Jul 07 06:57:25 PM PDT 24
Peak memory 250548 kb
Host smart-7bacb42a-6aa9-4b1b-8dc7-d540653dc195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934334879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1934334879
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2547940530
Short name T792
Test name
Test status
Simulation time 3383149355 ps
CPU time 39.96 seconds
Started Jul 07 06:57:17 PM PDT 24
Finished Jul 07 06:57:57 PM PDT 24
Peak memory 272752 kb
Host smart-b12501d8-3ae8-4ece-9304-d352475a136a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547940530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2547940530
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1177755218
Short name T449
Test name
Test status
Simulation time 76780617 ps
CPU time 0.99 seconds
Started Jul 07 06:57:13 PM PDT 24
Finished Jul 07 06:57:14 PM PDT 24
Peak memory 211992 kb
Host smart-7516b51c-c75d-4ee7-a973-3672f400b895
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177755218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1177755218
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1643262200
Short name T809
Test name
Test status
Simulation time 19471697 ps
CPU time 0.98 seconds
Started Jul 07 06:57:26 PM PDT 24
Finished Jul 07 06:57:27 PM PDT 24
Peak memory 208964 kb
Host smart-f4140b61-699a-4d75-a68d-0aa5a86c79e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643262200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1643262200
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4058945156
Short name T836
Test name
Test status
Simulation time 433115362 ps
CPU time 15.32 seconds
Started Jul 07 06:57:20 PM PDT 24
Finished Jul 07 06:57:36 PM PDT 24
Peak memory 218148 kb
Host smart-dc62f18c-5bff-4669-b5e5-cd6951411a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058945156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4058945156
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2975230313
Short name T645
Test name
Test status
Simulation time 865116107 ps
CPU time 2.54 seconds
Started Jul 07 06:57:22 PM PDT 24
Finished Jul 07 06:57:25 PM PDT 24
Peak memory 217708 kb
Host smart-e3999890-5ac7-458e-a172-cc75bd8dc330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975230313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2975230313
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3104662136
Short name T290
Test name
Test status
Simulation time 356790394 ps
CPU time 3.82 seconds
Started Jul 07 06:57:21 PM PDT 24
Finished Jul 07 06:57:25 PM PDT 24
Peak memory 218184 kb
Host smart-bee37538-4b0b-4be4-a2b1-e88ce8e22128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104662136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3104662136
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1235355625
Short name T304
Test name
Test status
Simulation time 370278924 ps
CPU time 11.22 seconds
Started Jul 07 06:57:26 PM PDT 24
Finished Jul 07 06:57:37 PM PDT 24
Peak memory 226028 kb
Host smart-a3979011-b185-4767-9ba5-ee9d935772c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235355625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1235355625
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3015460510
Short name T330
Test name
Test status
Simulation time 532541510 ps
CPU time 8.87 seconds
Started Jul 07 06:57:26 PM PDT 24
Finished Jul 07 06:57:35 PM PDT 24
Peak memory 226028 kb
Host smart-d62d0ca1-0ac2-44b1-b2ed-d07a3b09f065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015460510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3015460510
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3709111556
Short name T655
Test name
Test status
Simulation time 279669748 ps
CPU time 10.29 seconds
Started Jul 07 06:57:20 PM PDT 24
Finished Jul 07 06:57:30 PM PDT 24
Peak memory 225232 kb
Host smart-6909adc3-e3d5-41d2-8bba-889e33d8f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709111556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3709111556
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.54377255
Short name T420
Test name
Test status
Simulation time 67723325 ps
CPU time 1.91 seconds
Started Jul 07 06:57:17 PM PDT 24
Finished Jul 07 06:57:19 PM PDT 24
Peak memory 217732 kb
Host smart-e0157913-1abd-410c-9f17-05fc74baa4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54377255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.54377255
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3487494744
Short name T535
Test name
Test status
Simulation time 505934235 ps
CPU time 29.2 seconds
Started Jul 07 06:57:24 PM PDT 24
Finished Jul 07 06:57:54 PM PDT 24
Peak memory 246048 kb
Host smart-3fe34d0d-e06d-4194-bd90-4be7a679ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487494744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3487494744
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3416294518
Short name T468
Test name
Test status
Simulation time 467065058 ps
CPU time 6.7 seconds
Started Jul 07 06:57:20 PM PDT 24
Finished Jul 07 06:57:27 PM PDT 24
Peak memory 246672 kb
Host smart-b65d2a03-5b36-45e3-81da-d0af1c314ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416294518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3416294518
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2311195672
Short name T532
Test name
Test status
Simulation time 7980455410 ps
CPU time 285.29 seconds
Started Jul 07 06:57:27 PM PDT 24
Finished Jul 07 07:02:12 PM PDT 24
Peak memory 268960 kb
Host smart-b64a6a28-c35f-4347-8cbf-45be6a7ec2e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311195672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2311195672
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1406071738
Short name T730
Test name
Test status
Simulation time 34182449 ps
CPU time 0.87 seconds
Started Jul 07 06:57:16 PM PDT 24
Finished Jul 07 06:57:17 PM PDT 24
Peak memory 211836 kb
Host smart-26c23844-ff57-46bf-aced-e240e0f530b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406071738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1406071738
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.496889805
Short name T568
Test name
Test status
Simulation time 59730144 ps
CPU time 0.88 seconds
Started Jul 07 06:57:28 PM PDT 24
Finished Jul 07 06:57:30 PM PDT 24
Peak memory 208996 kb
Host smart-7a802292-8fe8-40f3-9c4a-fb2ba952c5ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496889805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.496889805
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2923538505
Short name T178
Test name
Test status
Simulation time 319456105 ps
CPU time 10.56 seconds
Started Jul 07 06:57:28 PM PDT 24
Finished Jul 07 06:57:39 PM PDT 24
Peak memory 218420 kb
Host smart-37ed622b-43cb-4186-ad07-1c4fc342c1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923538505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2923538505
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3745385638
Short name T688
Test name
Test status
Simulation time 1816042192 ps
CPU time 12.81 seconds
Started Jul 07 06:57:30 PM PDT 24
Finished Jul 07 06:57:43 PM PDT 24
Peak memory 217460 kb
Host smart-439b9e6a-5769-42e1-87e8-9b29efe7b47e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745385638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3745385638
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3277545706
Short name T189
Test name
Test status
Simulation time 32849373 ps
CPU time 1.96 seconds
Started Jul 07 06:57:24 PM PDT 24
Finished Jul 07 06:57:26 PM PDT 24
Peak memory 218256 kb
Host smart-e8d9f2d7-630c-48fa-aa2c-c00fcd648fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277545706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3277545706
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3403915006
Short name T112
Test name
Test status
Simulation time 345308861 ps
CPU time 13.59 seconds
Started Jul 07 06:57:29 PM PDT 24
Finished Jul 07 06:57:43 PM PDT 24
Peak memory 219520 kb
Host smart-c188e5e9-0403-4c7e-a4fd-0c4f742d38b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403915006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3403915006
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3365376517
Short name T363
Test name
Test status
Simulation time 1340245097 ps
CPU time 7.57 seconds
Started Jul 07 06:57:29 PM PDT 24
Finished Jul 07 06:57:37 PM PDT 24
Peak memory 226044 kb
Host smart-627b4f0e-a736-4c5d-a393-8338db9ccee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365376517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3365376517
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2022616129
Short name T673
Test name
Test status
Simulation time 707696312 ps
CPU time 11.57 seconds
Started Jul 07 06:57:29 PM PDT 24
Finished Jul 07 06:57:41 PM PDT 24
Peak memory 218236 kb
Host smart-7b8bcb0d-1728-4b20-99cd-3e765f307b7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022616129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2022616129
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2892028369
Short name T854
Test name
Test status
Simulation time 1779254470 ps
CPU time 14.09 seconds
Started Jul 07 06:57:33 PM PDT 24
Finished Jul 07 06:57:48 PM PDT 24
Peak memory 226032 kb
Host smart-5346d268-aedf-4d1c-98d4-23f9ec57b2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892028369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2892028369
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4278298644
Short name T257
Test name
Test status
Simulation time 138882782 ps
CPU time 3.67 seconds
Started Jul 07 06:57:26 PM PDT 24
Finished Jul 07 06:57:30 PM PDT 24
Peak memory 217708 kb
Host smart-a1bc4904-1d81-4f53-ae78-6083928c6b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278298644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.4278298644
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.102727690
Short name T570
Test name
Test status
Simulation time 347887661 ps
CPU time 33.62 seconds
Started Jul 07 06:57:24 PM PDT 24
Finished Jul 07 06:57:58 PM PDT 24
Peak memory 250980 kb
Host smart-64b07f70-869b-4a6a-9e1d-aa06987a905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102727690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.102727690
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.157398770
Short name T302
Test name
Test status
Simulation time 231273000 ps
CPU time 6.57 seconds
Started Jul 07 06:57:24 PM PDT 24
Finished Jul 07 06:57:30 PM PDT 24
Peak memory 250300 kb
Host smart-46fb2388-c6ac-4207-acb0-6c6d77c479a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157398770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.157398770
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4176576536
Short name T252
Test name
Test status
Simulation time 5826785568 ps
CPU time 190.62 seconds
Started Jul 07 06:57:30 PM PDT 24
Finished Jul 07 07:00:41 PM PDT 24
Peak memory 269132 kb
Host smart-2455cc97-6b4f-4e4d-8112-32b0fabf64d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176576536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4176576536
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.297342325
Short name T608
Test name
Test status
Simulation time 13255796 ps
CPU time 1.02 seconds
Started Jul 07 06:57:23 PM PDT 24
Finished Jul 07 06:57:24 PM PDT 24
Peak memory 211880 kb
Host smart-7f24719c-eaf8-44b5-9d20-dbfb649418ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297342325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.297342325
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2298475864
Short name T284
Test name
Test status
Simulation time 64065171 ps
CPU time 0.85 seconds
Started Jul 07 06:53:51 PM PDT 24
Finished Jul 07 06:53:53 PM PDT 24
Peak memory 208772 kb
Host smart-0351200a-b42e-4ac6-8c04-0ea9b625f8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298475864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2298475864
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3975065483
Short name T423
Test name
Test status
Simulation time 10976747 ps
CPU time 0.95 seconds
Started Jul 07 06:53:35 PM PDT 24
Finished Jul 07 06:53:36 PM PDT 24
Peak memory 209028 kb
Host smart-69bfe338-4e0e-44cc-818d-104d7ac64e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975065483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3975065483
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3974079621
Short name T463
Test name
Test status
Simulation time 1760971815 ps
CPU time 14.19 seconds
Started Jul 07 06:53:31 PM PDT 24
Finished Jul 07 06:53:45 PM PDT 24
Peak memory 218100 kb
Host smart-e6c8254a-8f54-4b88-aa0a-ffc2aef0cdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974079621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3974079621
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2399748833
Short name T425
Test name
Test status
Simulation time 11521253432 ps
CPU time 17 seconds
Started Jul 07 06:53:42 PM PDT 24
Finished Jul 07 06:53:59 PM PDT 24
Peak memory 217764 kb
Host smart-26d28f59-d0ab-4be9-b164-86e99a02807c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399748833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2399748833
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2679978509
Short name T537
Test name
Test status
Simulation time 2701994503 ps
CPU time 42.47 seconds
Started Jul 07 06:53:42 PM PDT 24
Finished Jul 07 06:54:25 PM PDT 24
Peak memory 218932 kb
Host smart-11367a53-befb-4f58-a323-840477721ed8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679978509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2679978509
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.929926730
Short name T534
Test name
Test status
Simulation time 370852880 ps
CPU time 8.98 seconds
Started Jul 07 06:53:41 PM PDT 24
Finished Jul 07 06:53:50 PM PDT 24
Peak memory 217540 kb
Host smart-46f4ac33-315b-49bc-9025-79be58583a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929926730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.929926730
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2745547769
Short name T728
Test name
Test status
Simulation time 577521228 ps
CPU time 9.65 seconds
Started Jul 07 06:53:38 PM PDT 24
Finished Jul 07 06:53:48 PM PDT 24
Peak memory 218092 kb
Host smart-893fb63c-0097-4a6a-99e2-c992b8a8586e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745547769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2745547769
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2952667387
Short name T376
Test name
Test status
Simulation time 2239422776 ps
CPU time 21.14 seconds
Started Jul 07 06:53:41 PM PDT 24
Finished Jul 07 06:54:03 PM PDT 24
Peak memory 217712 kb
Host smart-6ae2e9a8-4c21-4c3f-bbad-6211e361fde2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952667387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2952667387
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1036466391
Short name T398
Test name
Test status
Simulation time 877167754 ps
CPU time 7.5 seconds
Started Jul 07 06:53:34 PM PDT 24
Finished Jul 07 06:53:41 PM PDT 24
Peak memory 217724 kb
Host smart-1d04612e-10bf-49b0-9896-ec6cb1330887
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036466391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1036466391
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2330736922
Short name T542
Test name
Test status
Simulation time 3129503090 ps
CPU time 63.18 seconds
Started Jul 07 06:53:36 PM PDT 24
Finished Jul 07 06:54:39 PM PDT 24
Peak memory 267296 kb
Host smart-48a76cd5-3a0d-4adc-b7a1-da016446449d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330736922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2330736922
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2784509115
Short name T109
Test name
Test status
Simulation time 513242685 ps
CPU time 13.26 seconds
Started Jul 07 06:53:42 PM PDT 24
Finished Jul 07 06:53:55 PM PDT 24
Peak memory 250964 kb
Host smart-596d1951-842c-4b9c-a096-2d80759b9314
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784509115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2784509115
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3223291117
Short name T382
Test name
Test status
Simulation time 92588508 ps
CPU time 1.71 seconds
Started Jul 07 06:53:31 PM PDT 24
Finished Jul 07 06:53:33 PM PDT 24
Peak memory 218236 kb
Host smart-d5bd04ca-4e61-4a0f-8b4e-90c253676e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223291117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3223291117
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.308873143
Short name T603
Test name
Test status
Simulation time 332040028 ps
CPU time 9.48 seconds
Started Jul 07 06:53:37 PM PDT 24
Finished Jul 07 06:53:47 PM PDT 24
Peak memory 214784 kb
Host smart-642de5ad-7c56-402c-97b0-507486f170a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308873143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.308873143
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3331866124
Short name T104
Test name
Test status
Simulation time 1016346678 ps
CPU time 34.13 seconds
Started Jul 07 06:53:52 PM PDT 24
Finished Jul 07 06:54:26 PM PDT 24
Peak memory 269916 kb
Host smart-40d5ea8b-7738-424f-b97f-94a59df7e2d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331866124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3331866124
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.715861884
Short name T804
Test name
Test status
Simulation time 7191185291 ps
CPU time 15.14 seconds
Started Jul 07 06:53:41 PM PDT 24
Finished Jul 07 06:53:57 PM PDT 24
Peak memory 226092 kb
Host smart-d778b1e1-f9eb-45e2-aa9f-1896bfbde6ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715861884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.715861884
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.938281609
Short name T498
Test name
Test status
Simulation time 1141507454 ps
CPU time 13.32 seconds
Started Jul 07 06:53:43 PM PDT 24
Finished Jul 07 06:53:57 PM PDT 24
Peak memory 226044 kb
Host smart-873b1efc-7295-4973-b7a7-5dfa9ca2ec9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938281609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.938281609
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1934495446
Short name T96
Test name
Test status
Simulation time 226029748 ps
CPU time 8.51 seconds
Started Jul 07 06:53:43 PM PDT 24
Finished Jul 07 06:53:51 PM PDT 24
Peak memory 218188 kb
Host smart-3a0def21-325a-4f73-8f92-64d549e54f0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934495446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
934495446
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2475907262
Short name T744
Test name
Test status
Simulation time 18008201 ps
CPU time 1.1 seconds
Started Jul 07 06:53:29 PM PDT 24
Finished Jul 07 06:53:31 PM PDT 24
Peak memory 217980 kb
Host smart-10b33e17-0329-472b-bb4a-d128998b3165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475907262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2475907262
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.909069578
Short name T504
Test name
Test status
Simulation time 656924184 ps
CPU time 33.18 seconds
Started Jul 07 06:53:29 PM PDT 24
Finished Jul 07 06:54:03 PM PDT 24
Peak memory 250984 kb
Host smart-ea1f7cf0-39c7-43f5-b9da-5d758e9b3852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909069578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.909069578
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3944072709
Short name T188
Test name
Test status
Simulation time 267433863 ps
CPU time 6.92 seconds
Started Jul 07 06:53:31 PM PDT 24
Finished Jul 07 06:53:38 PM PDT 24
Peak memory 250524 kb
Host smart-f5f9d41c-4176-4c87-81a0-c4ddd75944ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944072709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3944072709
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1455594564
Short name T153
Test name
Test status
Simulation time 6123585829 ps
CPU time 76.66 seconds
Started Jul 07 06:53:45 PM PDT 24
Finished Jul 07 06:55:02 PM PDT 24
Peak memory 270748 kb
Host smart-a7f1cd4d-d0c2-4cd2-bd8e-3c8212e48050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1455594564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.1455594564
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1795443329
Short name T361
Test name
Test status
Simulation time 34114288 ps
CPU time 0.86 seconds
Started Jul 07 06:53:29 PM PDT 24
Finished Jul 07 06:53:31 PM PDT 24
Peak memory 211884 kb
Host smart-f2517200-54fe-4a7a-992e-11f2c8c617a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795443329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1795443329
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.4206171558
Short name T607
Test name
Test status
Simulation time 113160948 ps
CPU time 0.88 seconds
Started Jul 07 06:57:32 PM PDT 24
Finished Jul 07 06:57:33 PM PDT 24
Peak memory 208868 kb
Host smart-62286ec7-4d34-40ce-8bff-777e351e90df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206171558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.4206171558
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1165781156
Short name T847
Test name
Test status
Simulation time 302301593 ps
CPU time 15.02 seconds
Started Jul 07 06:57:32 PM PDT 24
Finished Jul 07 06:57:47 PM PDT 24
Peak memory 218180 kb
Host smart-d6f0fab6-156d-465d-9659-85e63a32c47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165781156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1165781156
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2598313059
Short name T691
Test name
Test status
Simulation time 333169963 ps
CPU time 1.9 seconds
Started Jul 07 06:57:33 PM PDT 24
Finished Jul 07 06:57:36 PM PDT 24
Peak memory 217156 kb
Host smart-e04292f6-cb17-4ef2-8cef-1e935de17df4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598313059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2598313059
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.923194718
Short name T2
Test name
Test status
Simulation time 22206840 ps
CPU time 1.84 seconds
Started Jul 07 06:57:34 PM PDT 24
Finished Jul 07 06:57:36 PM PDT 24
Peak memory 218228 kb
Host smart-ab380e20-8efe-4e52-bd3b-ee7b41af5a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923194718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.923194718
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1467275188
Short name T431
Test name
Test status
Simulation time 695618723 ps
CPU time 17.2 seconds
Started Jul 07 06:57:31 PM PDT 24
Finished Jul 07 06:57:48 PM PDT 24
Peak memory 225964 kb
Host smart-0f7d6eae-3316-41ff-a8eb-601c0261f4e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467275188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1467275188
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.825664889
Short name T20
Test name
Test status
Simulation time 2176236930 ps
CPU time 13.75 seconds
Started Jul 07 06:57:35 PM PDT 24
Finished Jul 07 06:57:49 PM PDT 24
Peak memory 226056 kb
Host smart-d34f6415-a167-4401-9445-2b3e75a32c29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825664889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.825664889
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.4061231006
Short name T738
Test name
Test status
Simulation time 296857643 ps
CPU time 11.86 seconds
Started Jul 07 06:57:36 PM PDT 24
Finished Jul 07 06:57:48 PM PDT 24
Peak memory 218228 kb
Host smart-521bbc20-ca1d-449c-9c7c-f4fd23083e61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061231006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
4061231006
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.553108530
Short name T383
Test name
Test status
Simulation time 237208889 ps
CPU time 6.28 seconds
Started Jul 07 06:57:32 PM PDT 24
Finished Jul 07 06:57:39 PM PDT 24
Peak memory 218372 kb
Host smart-66ce7182-38e6-4817-b1e6-248500880093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553108530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.553108530
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2023454225
Short name T492
Test name
Test status
Simulation time 320971499 ps
CPU time 1.96 seconds
Started Jul 07 06:57:30 PM PDT 24
Finished Jul 07 06:57:32 PM PDT 24
Peak memory 217748 kb
Host smart-bda48906-177c-4c0e-96e8-d461da51b641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023454225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2023454225
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3505334953
Short name T503
Test name
Test status
Simulation time 617138960 ps
CPU time 30.41 seconds
Started Jul 07 06:57:33 PM PDT 24
Finished Jul 07 06:58:04 PM PDT 24
Peak memory 250968 kb
Host smart-7897eb19-f630-4189-ad14-5fc951d76099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505334953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3505334953
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.4246275635
Short name T280
Test name
Test status
Simulation time 99444254 ps
CPU time 6.24 seconds
Started Jul 07 06:57:33 PM PDT 24
Finished Jul 07 06:57:39 PM PDT 24
Peak memory 248512 kb
Host smart-41e8ab52-a4f6-42c2-ac71-9da583c33fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246275635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.4246275635
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3670203598
Short name T108
Test name
Test status
Simulation time 11409676061 ps
CPU time 83.86 seconds
Started Jul 07 06:57:34 PM PDT 24
Finished Jul 07 06:58:58 PM PDT 24
Peak memory 251008 kb
Host smart-6a9976a5-bd26-4527-8cbe-ac15ef6032b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670203598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3670203598
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.371916278
Short name T637
Test name
Test status
Simulation time 195435542068 ps
CPU time 681.56 seconds
Started Jul 07 06:57:33 PM PDT 24
Finished Jul 07 07:08:56 PM PDT 24
Peak memory 496868 kb
Host smart-9aaec413-9098-45f3-9d6a-cdd8950a014a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=371916278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.371916278
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.212150791
Short name T219
Test name
Test status
Simulation time 15379849 ps
CPU time 0.88 seconds
Started Jul 07 06:57:34 PM PDT 24
Finished Jul 07 06:57:35 PM PDT 24
Peak memory 211972 kb
Host smart-524c1a33-b4e3-4ac7-8b98-d785ec200834
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212150791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.212150791
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2987671246
Short name T240
Test name
Test status
Simulation time 15722461 ps
CPU time 0.9 seconds
Started Jul 07 06:57:36 PM PDT 24
Finished Jul 07 06:57:37 PM PDT 24
Peak memory 209244 kb
Host smart-f35a875e-190a-4b47-a7ac-bb7f9fd708b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987671246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2987671246
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.808891462
Short name T294
Test name
Test status
Simulation time 2305573535 ps
CPU time 19.98 seconds
Started Jul 07 06:57:31 PM PDT 24
Finished Jul 07 06:57:51 PM PDT 24
Peak memory 218296 kb
Host smart-08e92958-a358-4644-84d8-cabe8ea50514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808891462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.808891462
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.702097804
Short name T580
Test name
Test status
Simulation time 51783398 ps
CPU time 2.98 seconds
Started Jul 07 06:57:31 PM PDT 24
Finished Jul 07 06:57:34 PM PDT 24
Peak memory 218228 kb
Host smart-d93f325f-3a50-4b0c-9694-fac1e80bfcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702097804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.702097804
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1303465862
Short name T587
Test name
Test status
Simulation time 573597822 ps
CPU time 12.33 seconds
Started Jul 07 06:57:40 PM PDT 24
Finished Jul 07 06:57:52 PM PDT 24
Peak memory 226032 kb
Host smart-622650ad-f79a-4344-bbc4-a8c7d7d232d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303465862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1303465862
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1143810936
Short name T434
Test name
Test status
Simulation time 1252670519 ps
CPU time 9.58 seconds
Started Jul 07 06:57:34 PM PDT 24
Finished Jul 07 06:57:44 PM PDT 24
Peak memory 225976 kb
Host smart-006040f2-f94f-40aa-85a5-aaddd3e43c64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143810936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1143810936
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2543474449
Short name T479
Test name
Test status
Simulation time 821683315 ps
CPU time 9.04 seconds
Started Jul 07 06:57:36 PM PDT 24
Finished Jul 07 06:57:46 PM PDT 24
Peak memory 226040 kb
Host smart-17f133c5-90eb-4d5d-8f73-64c3d408ca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543474449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2543474449
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4183439623
Short name T316
Test name
Test status
Simulation time 39418083 ps
CPU time 3.04 seconds
Started Jul 07 06:57:32 PM PDT 24
Finished Jul 07 06:57:35 PM PDT 24
Peak memory 214368 kb
Host smart-27cb08b4-e181-4da5-a49a-ccbe173ae403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183439623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4183439623
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1813470926
Short name T678
Test name
Test status
Simulation time 1283672071 ps
CPU time 36.69 seconds
Started Jul 07 06:57:32 PM PDT 24
Finished Jul 07 06:58:09 PM PDT 24
Peak memory 250988 kb
Host smart-e6857a4e-7e84-4d3b-8fb7-0ec8019586a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813470926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1813470926
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2949307705
Short name T731
Test name
Test status
Simulation time 76780966 ps
CPU time 3.28 seconds
Started Jul 07 06:57:33 PM PDT 24
Finished Jul 07 06:57:36 PM PDT 24
Peak memory 226392 kb
Host smart-47e88823-8f91-45c8-ab9c-d81d0c81ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949307705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2949307705
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1607247152
Short name T515
Test name
Test status
Simulation time 3485655609 ps
CPU time 62.84 seconds
Started Jul 07 06:57:38 PM PDT 24
Finished Jul 07 06:58:41 PM PDT 24
Peak memory 226136 kb
Host smart-37d30659-9f5c-4be6-9d53-36a955107130
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607247152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1607247152
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.115941758
Short name T469
Test name
Test status
Simulation time 21402511307 ps
CPU time 230.85 seconds
Started Jul 07 06:57:37 PM PDT 24
Finished Jul 07 07:01:28 PM PDT 24
Peak memory 277984 kb
Host smart-e4d2ba8a-a5c4-4a42-bcc5-d0711459f46a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=115941758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.115941758
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.210439927
Short name T802
Test name
Test status
Simulation time 15574522 ps
CPU time 0.94 seconds
Started Jul 07 06:57:32 PM PDT 24
Finished Jul 07 06:57:33 PM PDT 24
Peak memory 212940 kb
Host smart-a1a63d79-fb69-433f-a1b9-49eba6e36402
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210439927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.210439927
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3922421366
Short name T766
Test name
Test status
Simulation time 26338446 ps
CPU time 0.91 seconds
Started Jul 07 06:57:39 PM PDT 24
Finished Jul 07 06:57:40 PM PDT 24
Peak memory 209012 kb
Host smart-04cfe15d-3ba1-4169-b32c-743375a3de21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922421366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3922421366
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1992130670
Short name T531
Test name
Test status
Simulation time 1096028225 ps
CPU time 15.5 seconds
Started Jul 07 06:57:35 PM PDT 24
Finished Jul 07 06:57:51 PM PDT 24
Peak memory 226036 kb
Host smart-f6afccee-e609-4724-8a10-6423fb286077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992130670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1992130670
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.768505776
Short name T835
Test name
Test status
Simulation time 196202869 ps
CPU time 4.68 seconds
Started Jul 07 06:57:39 PM PDT 24
Finished Jul 07 06:57:44 PM PDT 24
Peak memory 217136 kb
Host smart-abbaf0ad-0266-4938-ab83-a2632487c937
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768505776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.768505776
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3953021684
Short name T426
Test name
Test status
Simulation time 218987355 ps
CPU time 2.64 seconds
Started Jul 07 06:57:36 PM PDT 24
Finished Jul 07 06:57:39 PM PDT 24
Peak memory 218240 kb
Host smart-c0d3f913-b9c9-417e-acfc-78a8775c7b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953021684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3953021684
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.644351842
Short name T461
Test name
Test status
Simulation time 1471185923 ps
CPU time 17.11 seconds
Started Jul 07 06:57:43 PM PDT 24
Finished Jul 07 06:58:00 PM PDT 24
Peak memory 219224 kb
Host smart-96120d85-1f62-4006-a30b-883e35d13169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644351842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.644351842
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.122030031
Short name T585
Test name
Test status
Simulation time 229795394 ps
CPU time 7.48 seconds
Started Jul 07 06:57:42 PM PDT 24
Finished Jul 07 06:57:50 PM PDT 24
Peak memory 226296 kb
Host smart-e1446739-f02c-46c3-8ba0-b7dcfec6425f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122030031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.122030031
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4230515033
Short name T741
Test name
Test status
Simulation time 2791662159 ps
CPU time 9.95 seconds
Started Jul 07 06:57:40 PM PDT 24
Finished Jul 07 06:57:51 PM PDT 24
Peak memory 218324 kb
Host smart-8ad99c1f-e3ef-4c05-a984-0f796323cfaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230515033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4230515033
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2603134233
Short name T46
Test name
Test status
Simulation time 296961340 ps
CPU time 8.22 seconds
Started Jul 07 06:57:40 PM PDT 24
Finished Jul 07 06:57:48 PM PDT 24
Peak memory 224724 kb
Host smart-f1d79a64-1083-482b-88ec-54c9497a568d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603134233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2603134233
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4046848250
Short name T261
Test name
Test status
Simulation time 63338458 ps
CPU time 1.34 seconds
Started Jul 07 06:57:35 PM PDT 24
Finished Jul 07 06:57:37 PM PDT 24
Peak memory 217732 kb
Host smart-b6e1d586-1194-4f17-8cb6-f1f736e968f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046848250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4046848250
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1596236536
Short name T430
Test name
Test status
Simulation time 199696343 ps
CPU time 20.07 seconds
Started Jul 07 06:57:35 PM PDT 24
Finished Jul 07 06:57:56 PM PDT 24
Peak memory 250940 kb
Host smart-15696e9e-b3ed-4d44-8f96-8979f0143d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596236536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1596236536
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.293398100
Short name T559
Test name
Test status
Simulation time 290705627 ps
CPU time 7.51 seconds
Started Jul 07 06:57:36 PM PDT 24
Finished Jul 07 06:57:44 PM PDT 24
Peak memory 246752 kb
Host smart-29a2d714-2466-4d39-975c-f131e02911b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293398100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.293398100
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3245620309
Short name T561
Test name
Test status
Simulation time 8007429719 ps
CPU time 186.05 seconds
Started Jul 07 06:57:40 PM PDT 24
Finished Jul 07 07:00:46 PM PDT 24
Peak memory 267444 kb
Host smart-77d4987f-217c-4c80-b216-be95da354259
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245620309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3245620309
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.3165772383
Short name T163
Test name
Test status
Simulation time 80574194627 ps
CPU time 333.21 seconds
Started Jul 07 06:57:42 PM PDT 24
Finished Jul 07 07:03:15 PM PDT 24
Peak memory 284020 kb
Host smart-9817ea7e-2c45-44c7-b6bb-764a1f224151
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3165772383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.3165772383
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3914376568
Short name T454
Test name
Test status
Simulation time 13506413 ps
CPU time 1.06 seconds
Started Jul 07 06:57:36 PM PDT 24
Finished Jul 07 06:57:37 PM PDT 24
Peak memory 211812 kb
Host smart-fe239d09-b5ac-4a1d-b544-b1cf4dcbace0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914376568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3914376568
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1256079164
Short name T808
Test name
Test status
Simulation time 25859615 ps
CPU time 1.08 seconds
Started Jul 07 06:57:46 PM PDT 24
Finished Jul 07 06:57:48 PM PDT 24
Peak memory 208960 kb
Host smart-f7ad4fe3-d856-4882-aabe-8d4025c18649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256079164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1256079164
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2628270484
Short name T839
Test name
Test status
Simulation time 629417945 ps
CPU time 9.11 seconds
Started Jul 07 06:57:44 PM PDT 24
Finished Jul 07 06:57:53 PM PDT 24
Peak memory 218220 kb
Host smart-edf9923a-a912-47c0-9699-5e7922b6db3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628270484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2628270484
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1435227776
Short name T35
Test name
Test status
Simulation time 2220358648 ps
CPU time 14.45 seconds
Started Jul 07 06:57:42 PM PDT 24
Finished Jul 07 06:57:57 PM PDT 24
Peak memory 217556 kb
Host smart-e080544c-43b6-402a-9899-825150fa6cf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435227776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1435227776
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3530318828
Short name T739
Test name
Test status
Simulation time 98000310 ps
CPU time 4.37 seconds
Started Jul 07 06:57:44 PM PDT 24
Finished Jul 07 06:57:48 PM PDT 24
Peak memory 218216 kb
Host smart-db566783-931a-4b61-b821-c4b15eca027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530318828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3530318828
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2522997410
Short name T365
Test name
Test status
Simulation time 379507150 ps
CPU time 16.8 seconds
Started Jul 07 06:57:45 PM PDT 24
Finished Jul 07 06:58:02 PM PDT 24
Peak memory 226040 kb
Host smart-b7a7ea94-263e-4d6e-af46-ebdfa0ce132d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522997410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2522997410
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2691340496
Short name T287
Test name
Test status
Simulation time 708396755 ps
CPU time 10.11 seconds
Started Jul 07 06:57:44 PM PDT 24
Finished Jul 07 06:57:54 PM PDT 24
Peak memory 226076 kb
Host smart-1b368a96-96a5-48a3-81a6-f3aa8d1f595e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691340496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2691340496
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.178445217
Short name T460
Test name
Test status
Simulation time 397072754 ps
CPU time 13.5 seconds
Started Jul 07 06:57:45 PM PDT 24
Finished Jul 07 06:57:59 PM PDT 24
Peak memory 218248 kb
Host smart-d3e35acf-d217-4651-bbd5-d8c5fd8ad3a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178445217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.178445217
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3908494481
Short name T628
Test name
Test status
Simulation time 1499216108 ps
CPU time 8.91 seconds
Started Jul 07 06:57:44 PM PDT 24
Finished Jul 07 06:57:53 PM PDT 24
Peak memory 218344 kb
Host smart-1880ea03-273b-4c18-ad53-6a87c941bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908494481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3908494481
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.912297046
Short name T371
Test name
Test status
Simulation time 736384310 ps
CPU time 4.09 seconds
Started Jul 07 06:57:40 PM PDT 24
Finished Jul 07 06:57:45 PM PDT 24
Peak memory 217716 kb
Host smart-7c0f7d0a-df42-440f-af12-045cabaf5764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912297046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.912297046
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2654020004
Short name T273
Test name
Test status
Simulation time 507345736 ps
CPU time 32.98 seconds
Started Jul 07 06:57:41 PM PDT 24
Finished Jul 07 06:58:15 PM PDT 24
Peak memory 250976 kb
Host smart-44344a2e-8354-4ffc-a0f9-f725e95173f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654020004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2654020004
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.480807419
Short name T354
Test name
Test status
Simulation time 52324481 ps
CPU time 2.92 seconds
Started Jul 07 06:57:43 PM PDT 24
Finished Jul 07 06:57:46 PM PDT 24
Peak memory 226668 kb
Host smart-f8ad0f00-2638-4a0c-8251-5b548d5007ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480807419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.480807419
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2253884238
Short name T366
Test name
Test status
Simulation time 81549534 ps
CPU time 0.91 seconds
Started Jul 07 06:57:42 PM PDT 24
Finished Jul 07 06:57:43 PM PDT 24
Peak memory 212972 kb
Host smart-940e31c7-4236-43d5-b75c-af07d50fdd33
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253884238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2253884238
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3665359060
Short name T190
Test name
Test status
Simulation time 12813083 ps
CPU time 1 seconds
Started Jul 07 06:57:50 PM PDT 24
Finished Jul 07 06:57:51 PM PDT 24
Peak memory 208996 kb
Host smart-bded93de-6e96-4079-9383-e840ec07f0ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665359060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3665359060
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1644234260
Short name T778
Test name
Test status
Simulation time 560024876 ps
CPU time 13 seconds
Started Jul 07 06:57:47 PM PDT 24
Finished Jul 07 06:58:00 PM PDT 24
Peak memory 218220 kb
Host smart-b5fcd588-adf9-46d0-8372-a1bf01b14bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644234260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1644234260
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3968056261
Short name T31
Test name
Test status
Simulation time 3475961395 ps
CPU time 16.85 seconds
Started Jul 07 06:57:45 PM PDT 24
Finished Jul 07 06:58:02 PM PDT 24
Peak memory 217784 kb
Host smart-ef51ea42-8bc1-4fe6-88a7-752cf24013ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968056261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3968056261
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.4016935219
Short name T848
Test name
Test status
Simulation time 227222685 ps
CPU time 2.99 seconds
Started Jul 07 06:57:48 PM PDT 24
Finished Jul 07 06:57:52 PM PDT 24
Peak memory 218216 kb
Host smart-c70640d8-dc51-484c-b919-fa32fa1c0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016935219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.4016935219
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.933474945
Short name T385
Test name
Test status
Simulation time 1303705609 ps
CPU time 14.61 seconds
Started Jul 07 06:57:47 PM PDT 24
Finished Jul 07 06:58:02 PM PDT 24
Peak memory 218220 kb
Host smart-33d2e7c5-6345-4b29-8486-d24605c0a1f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933474945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.933474945
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.556238531
Short name T351
Test name
Test status
Simulation time 381489950 ps
CPU time 12.57 seconds
Started Jul 07 06:57:52 PM PDT 24
Finished Jul 07 06:58:04 PM PDT 24
Peak memory 226044 kb
Host smart-a4040e5b-c326-46ae-95a4-6b82e3a6b8fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556238531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.556238531
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1147808790
Short name T256
Test name
Test status
Simulation time 1351967882 ps
CPU time 12.13 seconds
Started Jul 07 06:57:46 PM PDT 24
Finished Jul 07 06:57:58 PM PDT 24
Peak memory 218244 kb
Host smart-3828195a-b233-4266-ad61-1b9075ae4bc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147808790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1147808790
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3054793127
Short name T539
Test name
Test status
Simulation time 1380610927 ps
CPU time 11.24 seconds
Started Jul 07 06:57:46 PM PDT 24
Finished Jul 07 06:57:57 PM PDT 24
Peak memory 218288 kb
Host smart-14b8abca-66c4-4f29-b605-4737f3e4b292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054793127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3054793127
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2973353479
Short name T356
Test name
Test status
Simulation time 46897793 ps
CPU time 1 seconds
Started Jul 07 06:57:45 PM PDT 24
Finished Jul 07 06:57:46 PM PDT 24
Peak memory 212244 kb
Host smart-3bb946bf-8851-41db-b01f-fc49ca42ac3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973353479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2973353479
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1806732897
Short name T297
Test name
Test status
Simulation time 213785554 ps
CPU time 27.71 seconds
Started Jul 07 06:57:47 PM PDT 24
Finished Jul 07 06:58:15 PM PDT 24
Peak memory 247648 kb
Host smart-db6bdc81-de0b-4a24-9386-92260b437c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806732897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1806732897
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3321166259
Short name T265
Test name
Test status
Simulation time 48107899 ps
CPU time 6.06 seconds
Started Jul 07 06:57:49 PM PDT 24
Finished Jul 07 06:57:56 PM PDT 24
Peak memory 247184 kb
Host smart-664370bc-18d2-4c9f-bd00-c3aa17d0efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321166259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3321166259
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.200991
Short name T514
Test name
Test status
Simulation time 5518205253 ps
CPU time 202.63 seconds
Started Jul 07 06:57:52 PM PDT 24
Finished Jul 07 07:01:15 PM PDT 24
Peak memory 267440 kb
Host smart-a71b76ee-8043-4351-98b4-a3e3a1399b31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TES
T_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
lc_ctrl_stress_all.200991
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3329816245
Short name T619
Test name
Test status
Simulation time 2370775755 ps
CPU time 69.41 seconds
Started Jul 07 06:57:52 PM PDT 24
Finished Jul 07 06:59:01 PM PDT 24
Peak memory 284016 kb
Host smart-b3e3323d-fb67-48f4-8525-8691781e467b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3329816245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3329816245
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1358191113
Short name T389
Test name
Test status
Simulation time 17683778 ps
CPU time 0.94 seconds
Started Jul 07 06:57:46 PM PDT 24
Finished Jul 07 06:57:48 PM PDT 24
Peak memory 211860 kb
Host smart-08e052fd-2f39-4045-a3bc-688532378125
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358191113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1358191113
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.49642624
Short name T103
Test name
Test status
Simulation time 18833773 ps
CPU time 1.02 seconds
Started Jul 07 06:57:55 PM PDT 24
Finished Jul 07 06:57:57 PM PDT 24
Peak memory 209160 kb
Host smart-4fb97dc4-91e9-4775-9c4f-2eb620671809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49642624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.49642624
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2952649284
Short name T800
Test name
Test status
Simulation time 453344090 ps
CPU time 13.49 seconds
Started Jul 07 06:57:56 PM PDT 24
Finished Jul 07 06:58:09 PM PDT 24
Peak memory 226028 kb
Host smart-b8727476-ec25-41dd-841c-56fdc254e3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952649284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2952649284
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2390209117
Short name T7
Test name
Test status
Simulation time 120059501 ps
CPU time 3.64 seconds
Started Jul 07 06:57:55 PM PDT 24
Finished Jul 07 06:57:59 PM PDT 24
Peak memory 217112 kb
Host smart-3eb73fe8-2bb9-439b-9b3f-9c542108a792
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390209117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2390209117
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1376685935
Short name T231
Test name
Test status
Simulation time 37883097 ps
CPU time 1.76 seconds
Started Jul 07 06:57:52 PM PDT 24
Finished Jul 07 06:57:54 PM PDT 24
Peak memory 218484 kb
Host smart-9b49900e-e6ab-4c44-8e21-b5f84d0385e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376685935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1376685935
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.683159078
Short name T729
Test name
Test status
Simulation time 1700252529 ps
CPU time 11.86 seconds
Started Jul 07 06:57:55 PM PDT 24
Finished Jul 07 06:58:07 PM PDT 24
Peak memory 218304 kb
Host smart-bae87b20-7d16-4dae-a6d4-8a8b29b2fcb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683159078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.683159078
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2743581652
Short name T19
Test name
Test status
Simulation time 1358884697 ps
CPU time 11.81 seconds
Started Jul 07 06:57:55 PM PDT 24
Finished Jul 07 06:58:07 PM PDT 24
Peak memory 226036 kb
Host smart-e7dd48ce-4d89-4f63-906b-3d999694d074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743581652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2743581652
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4111674316
Short name T44
Test name
Test status
Simulation time 1092697967 ps
CPU time 6.42 seconds
Started Jul 07 06:57:54 PM PDT 24
Finished Jul 07 06:58:01 PM PDT 24
Peak memory 225972 kb
Host smart-36de871e-6e4f-461f-9236-b52cefff12a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111674316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4111674316
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.822933507
Short name T683
Test name
Test status
Simulation time 689916050 ps
CPU time 11.77 seconds
Started Jul 07 06:57:55 PM PDT 24
Finished Jul 07 06:58:07 PM PDT 24
Peak memory 218344 kb
Host smart-1652b9a2-0507-4806-a5ab-b1d99110fb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822933507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.822933507
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4245433243
Short name T264
Test name
Test status
Simulation time 58565275 ps
CPU time 2.53 seconds
Started Jul 07 06:57:53 PM PDT 24
Finished Jul 07 06:57:56 PM PDT 24
Peak memory 223836 kb
Host smart-13f7aa47-3020-4f10-838f-7f7ae3e24493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245433243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4245433243
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1419505853
Short name T270
Test name
Test status
Simulation time 2775851355 ps
CPU time 32.64 seconds
Started Jul 07 06:57:52 PM PDT 24
Finished Jul 07 06:58:25 PM PDT 24
Peak memory 251048 kb
Host smart-9ea5b022-e825-4b4d-a92b-ff70b02f0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419505853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1419505853
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3430457494
Short name T548
Test name
Test status
Simulation time 69256291 ps
CPU time 7.59 seconds
Started Jul 07 06:57:53 PM PDT 24
Finished Jul 07 06:58:00 PM PDT 24
Peak memory 250960 kb
Host smart-610b57b3-9bc2-453f-86ce-58025601694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430457494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3430457494
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2628368207
Short name T462
Test name
Test status
Simulation time 16549340946 ps
CPU time 165.56 seconds
Started Jul 07 06:57:54 PM PDT 24
Finished Jul 07 07:00:40 PM PDT 24
Peak memory 263580 kb
Host smart-7fe66766-ac51-4a93-ab0e-87e11301cbcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628368207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2628368207
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1651113152
Short name T742
Test name
Test status
Simulation time 69112810706 ps
CPU time 569.58 seconds
Started Jul 07 06:57:55 PM PDT 24
Finished Jul 07 07:07:25 PM PDT 24
Peak memory 281020 kb
Host smart-53592cba-4bd8-4ef4-94e5-8181c642516d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1651113152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1651113152
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1403746516
Short name T175
Test name
Test status
Simulation time 12519142 ps
CPU time 0.9 seconds
Started Jul 07 06:57:52 PM PDT 24
Finished Jul 07 06:57:53 PM PDT 24
Peak memory 211932 kb
Host smart-61f8e9ce-61e8-4c4a-b9fe-5f6f054d5fe7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403746516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1403746516
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.560980442
Short name T157
Test name
Test status
Simulation time 22808089 ps
CPU time 1.28 seconds
Started Jul 07 06:58:01 PM PDT 24
Finished Jul 07 06:58:03 PM PDT 24
Peak memory 208968 kb
Host smart-a922fab1-7cee-4b66-a8ee-fbcf49ef16ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560980442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.560980442
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2225675847
Short name T850
Test name
Test status
Simulation time 355964341 ps
CPU time 14.26 seconds
Started Jul 07 06:58:00 PM PDT 24
Finished Jul 07 06:58:15 PM PDT 24
Peak memory 226092 kb
Host smart-61f1a673-b1e1-4e2d-a5a7-aaff99cc1b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225675847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2225675847
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3293471572
Short name T34
Test name
Test status
Simulation time 1946898821 ps
CPU time 4.71 seconds
Started Jul 07 06:58:02 PM PDT 24
Finished Jul 07 06:58:07 PM PDT 24
Peak memory 217480 kb
Host smart-678b4e4d-e675-4b95-9201-1c52a3ebbe42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293471572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3293471572
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1577921855
Short name T505
Test name
Test status
Simulation time 73865595 ps
CPU time 1.66 seconds
Started Jul 07 06:57:59 PM PDT 24
Finished Jul 07 06:58:01 PM PDT 24
Peak memory 218224 kb
Host smart-8914e82e-20d3-458a-b4ca-450902c51a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577921855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1577921855
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.743841822
Short name T435
Test name
Test status
Simulation time 740307837 ps
CPU time 11.07 seconds
Started Jul 07 06:58:00 PM PDT 24
Finished Jul 07 06:58:11 PM PDT 24
Peak memory 226028 kb
Host smart-12f60082-9dec-47e6-8212-49499f0ec485
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743841822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.743841822
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.543960012
Short name T715
Test name
Test status
Simulation time 1514364767 ps
CPU time 21.75 seconds
Started Jul 07 06:57:58 PM PDT 24
Finished Jul 07 06:58:20 PM PDT 24
Peak memory 226044 kb
Host smart-e46f71d8-890a-4590-ae7d-4ed5ae70a020
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543960012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.543960012
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2124407625
Short name T403
Test name
Test status
Simulation time 221762233 ps
CPU time 7.9 seconds
Started Jul 07 06:57:58 PM PDT 24
Finished Jul 07 06:58:06 PM PDT 24
Peak memory 218168 kb
Host smart-96b7a5f8-f2d1-4e0c-8423-2e57692a9796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124407625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2124407625
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2018774718
Short name T569
Test name
Test status
Simulation time 60195373 ps
CPU time 3.25 seconds
Started Jul 07 06:57:57 PM PDT 24
Finished Jul 07 06:58:00 PM PDT 24
Peak memory 217736 kb
Host smart-57166ad7-228d-49d9-a507-b77c4560f9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018774718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2018774718
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1237566114
Short name T616
Test name
Test status
Simulation time 227898296 ps
CPU time 25.13 seconds
Started Jul 07 06:58:00 PM PDT 24
Finished Jul 07 06:58:25 PM PDT 24
Peak memory 250976 kb
Host smart-85fd61ae-d13b-47d8-91f3-2c6ab4d81a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237566114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1237566114
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.772787029
Short name T245
Test name
Test status
Simulation time 396101744 ps
CPU time 7.47 seconds
Started Jul 07 06:57:57 PM PDT 24
Finished Jul 07 06:58:05 PM PDT 24
Peak memory 250972 kb
Host smart-5b954d65-59b5-4c55-972d-ad185d920915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772787029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.772787029
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1624572893
Short name T755
Test name
Test status
Simulation time 1777063327 ps
CPU time 87.67 seconds
Started Jul 07 06:57:57 PM PDT 24
Finished Jul 07 06:59:24 PM PDT 24
Peak memory 250968 kb
Host smart-62837850-2b93-45ac-a3c2-ead304fe20bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624572893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1624572893
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1735669036
Short name T347
Test name
Test status
Simulation time 17809930 ps
CPU time 1.08 seconds
Started Jul 07 06:57:57 PM PDT 24
Finished Jul 07 06:57:58 PM PDT 24
Peak memory 217580 kb
Host smart-6b88dd3d-9e8a-484c-b02c-6eea75849100
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735669036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1735669036
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1425723088
Short name T812
Test name
Test status
Simulation time 14691750 ps
CPU time 0.88 seconds
Started Jul 07 06:58:05 PM PDT 24
Finished Jul 07 06:58:07 PM PDT 24
Peak memory 209060 kb
Host smart-ffe6aa59-6d10-4a0f-b9d1-76f4bfd676ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425723088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1425723088
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1799240249
Short name T179
Test name
Test status
Simulation time 745392189 ps
CPU time 10.47 seconds
Started Jul 07 06:58:04 PM PDT 24
Finished Jul 07 06:58:15 PM PDT 24
Peak memory 218180 kb
Host smart-5987ffa4-ce74-4246-ae0b-8c692335ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799240249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1799240249
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1927438769
Short name T699
Test name
Test status
Simulation time 2008875458 ps
CPU time 12.75 seconds
Started Jul 07 06:58:04 PM PDT 24
Finished Jul 07 06:58:17 PM PDT 24
Peak memory 217404 kb
Host smart-60e864b3-1680-4a6e-9bf5-8e52862b4dd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927438769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1927438769
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.861040384
Short name T392
Test name
Test status
Simulation time 137200989 ps
CPU time 2.61 seconds
Started Jul 07 06:58:03 PM PDT 24
Finished Jul 07 06:58:06 PM PDT 24
Peak memory 218224 kb
Host smart-d037c0ae-f1a1-417b-bd40-5892776f8f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861040384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.861040384
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3504133086
Short name T60
Test name
Test status
Simulation time 1173249448 ps
CPU time 14.79 seconds
Started Jul 07 06:57:59 PM PDT 24
Finished Jul 07 06:58:14 PM PDT 24
Peak memory 226036 kb
Host smart-5e35000c-1e7c-46f1-b5dc-c675a01a703b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504133086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3504133086
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.4031790069
Short name T113
Test name
Test status
Simulation time 1611780048 ps
CPU time 16.09 seconds
Started Jul 07 06:58:08 PM PDT 24
Finished Jul 07 06:58:24 PM PDT 24
Peak memory 226036 kb
Host smart-9b52693a-fec5-42f3-81bd-cd8d702b3fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031790069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.4031790069
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1165666457
Short name T636
Test name
Test status
Simulation time 1336853524 ps
CPU time 12.95 seconds
Started Jul 07 06:58:06 PM PDT 24
Finished Jul 07 06:58:20 PM PDT 24
Peak memory 218240 kb
Host smart-6f8608e6-bb06-4901-b992-d36e2a35ae14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165666457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1165666457
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3370953708
Short name T752
Test name
Test status
Simulation time 1142697081 ps
CPU time 8.89 seconds
Started Jul 07 06:58:02 PM PDT 24
Finished Jul 07 06:58:11 PM PDT 24
Peak memory 225384 kb
Host smart-2de190b3-b6cf-445b-b5d1-8772f3e605c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370953708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3370953708
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2102685086
Short name T378
Test name
Test status
Simulation time 96460980 ps
CPU time 2.38 seconds
Started Jul 07 06:58:04 PM PDT 24
Finished Jul 07 06:58:06 PM PDT 24
Peak memory 217720 kb
Host smart-62429da8-2e0c-45ef-825f-5e75424bd50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102685086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2102685086
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3125828333
Short name T513
Test name
Test status
Simulation time 284527940 ps
CPU time 26.66 seconds
Started Jul 07 06:58:02 PM PDT 24
Finished Jul 07 06:58:29 PM PDT 24
Peak memory 251024 kb
Host smart-0eebc363-f64f-44f1-8a1a-f05a1d6d378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125828333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3125828333
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2040158269
Short name T509
Test name
Test status
Simulation time 222950992 ps
CPU time 3.44 seconds
Started Jul 07 06:58:03 PM PDT 24
Finished Jul 07 06:58:07 PM PDT 24
Peak memory 222356 kb
Host smart-038b46dc-c0b9-488a-8bb6-1c9284aabbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040158269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2040158269
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1838450771
Short name T443
Test name
Test status
Simulation time 12731266908 ps
CPU time 146.43 seconds
Started Jul 07 06:58:07 PM PDT 24
Finished Jul 07 07:00:34 PM PDT 24
Peak memory 308664 kb
Host smart-9eabaf95-5221-44e2-8e58-0a6e8f9a10c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838450771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1838450771
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2235813107
Short name T57
Test name
Test status
Simulation time 3674061129 ps
CPU time 113.78 seconds
Started Jul 07 06:58:04 PM PDT 24
Finished Jul 07 06:59:59 PM PDT 24
Peak memory 277976 kb
Host smart-c8deadab-640d-4aa7-a2e3-cb47fb388118
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2235813107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2235813107
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.461058672
Short name T622
Test name
Test status
Simulation time 73394984 ps
CPU time 1.15 seconds
Started Jul 07 06:58:03 PM PDT 24
Finished Jul 07 06:58:04 PM PDT 24
Peak memory 212908 kb
Host smart-2ae5e26f-2536-44d6-98b8-d8e671802128
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461058672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.461058672
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3441098587
Short name T83
Test name
Test status
Simulation time 53765847 ps
CPU time 1.06 seconds
Started Jul 07 06:58:16 PM PDT 24
Finished Jul 07 06:58:18 PM PDT 24
Peak memory 208944 kb
Host smart-72645dae-f395-408b-b73e-5528c9a413b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441098587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3441098587
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3383735496
Short name T338
Test name
Test status
Simulation time 602381711 ps
CPU time 22.71 seconds
Started Jul 07 06:58:10 PM PDT 24
Finished Jul 07 06:58:33 PM PDT 24
Peak memory 218188 kb
Host smart-b561337d-d195-4447-93a0-63668873ca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383735496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3383735496
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2159258079
Short name T823
Test name
Test status
Simulation time 694011761 ps
CPU time 5.68 seconds
Started Jul 07 06:58:09 PM PDT 24
Finished Jul 07 06:58:15 PM PDT 24
Peak memory 217280 kb
Host smart-6641cda4-6bdc-44a1-ad12-94ff3ea0930b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159258079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2159258079
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1275285618
Short name T401
Test name
Test status
Simulation time 184142022 ps
CPU time 4.18 seconds
Started Jul 07 06:58:08 PM PDT 24
Finished Jul 07 06:58:12 PM PDT 24
Peak memory 222616 kb
Host smart-3922cdb6-c08d-4352-974e-dc176e2332d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275285618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1275285618
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1048158213
Short name T746
Test name
Test status
Simulation time 908134273 ps
CPU time 15.58 seconds
Started Jul 07 06:58:08 PM PDT 24
Finished Jul 07 06:58:24 PM PDT 24
Peak memory 226032 kb
Host smart-9cfe9cf3-b97f-4f14-aede-6726a258e29b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048158213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1048158213
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1258577288
Short name T810
Test name
Test status
Simulation time 4309678084 ps
CPU time 8.82 seconds
Started Jul 07 06:58:10 PM PDT 24
Finished Jul 07 06:58:19 PM PDT 24
Peak memory 226064 kb
Host smart-655bd6f1-d3f7-419f-a675-ce299472a892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258577288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1258577288
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2636878320
Short name T97
Test name
Test status
Simulation time 430312730 ps
CPU time 10.16 seconds
Started Jul 07 06:58:16 PM PDT 24
Finished Jul 07 06:58:27 PM PDT 24
Peak memory 226036 kb
Host smart-dafc318d-2521-46dd-9c7d-ab47e9c04908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636878320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2636878320
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1902403491
Short name T609
Test name
Test status
Simulation time 100580062 ps
CPU time 3.94 seconds
Started Jul 07 06:58:05 PM PDT 24
Finished Jul 07 06:58:10 PM PDT 24
Peak memory 217716 kb
Host smart-4aa43552-ff1c-4d23-9b95-2bd69f30085c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902403491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1902403491
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2655460815
Short name T540
Test name
Test status
Simulation time 200477527 ps
CPU time 27.17 seconds
Started Jul 07 06:58:06 PM PDT 24
Finished Jul 07 06:58:33 PM PDT 24
Peak memory 250968 kb
Host smart-8c256245-211a-460e-b738-910e1aaf5b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655460815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2655460815
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.544095210
Short name T811
Test name
Test status
Simulation time 281408123 ps
CPU time 7.57 seconds
Started Jul 07 06:58:04 PM PDT 24
Finished Jul 07 06:58:12 PM PDT 24
Peak memory 250392 kb
Host smart-33c69ca8-7131-4cb9-af50-7ffcd7e4922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544095210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.544095210
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.577088730
Short name T617
Test name
Test status
Simulation time 87678232916 ps
CPU time 196.69 seconds
Started Jul 07 06:58:09 PM PDT 24
Finished Jul 07 07:01:26 PM PDT 24
Peak memory 283520 kb
Host smart-ce1238a1-c522-415c-a3ee-77c7e4fe105c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577088730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.577088730
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.956293395
Short name T162
Test name
Test status
Simulation time 57899696373 ps
CPU time 1848.14 seconds
Started Jul 07 06:58:08 PM PDT 24
Finished Jul 07 07:28:57 PM PDT 24
Peak memory 742632 kb
Host smart-bba7f2c0-dcc8-4dc7-b889-47b01e8de3dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=956293395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.956293395
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1096318099
Short name T322
Test name
Test status
Simulation time 12196303 ps
CPU time 0.98 seconds
Started Jul 07 06:58:07 PM PDT 24
Finished Jul 07 06:58:08 PM PDT 24
Peak memory 211972 kb
Host smart-692f6e62-c54b-476a-9dfe-12d1da93b898
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096318099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1096318099
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2926370071
Short name T780
Test name
Test status
Simulation time 36389906 ps
CPU time 0.87 seconds
Started Jul 07 06:58:17 PM PDT 24
Finished Jul 07 06:58:18 PM PDT 24
Peak memory 208920 kb
Host smart-752c4b89-9030-4224-aaf1-ba345ebcc0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926370071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2926370071
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2995581141
Short name T791
Test name
Test status
Simulation time 9289993127 ps
CPU time 24.18 seconds
Started Jul 07 06:58:13 PM PDT 24
Finished Jul 07 06:58:38 PM PDT 24
Peak memory 218668 kb
Host smart-b2cbd42d-daca-4355-89b1-0919d73db857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995581141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2995581141
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3506461148
Short name T33
Test name
Test status
Simulation time 1493188316 ps
CPU time 2.8 seconds
Started Jul 07 06:58:13 PM PDT 24
Finished Jul 07 06:58:16 PM PDT 24
Peak memory 217288 kb
Host smart-771f8d9c-d927-4d84-8cb2-8222ff2f1f52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506461148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3506461148
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.866145878
Short name T307
Test name
Test status
Simulation time 156031647 ps
CPU time 2.49 seconds
Started Jul 07 06:58:17 PM PDT 24
Finished Jul 07 06:58:20 PM PDT 24
Peak memory 222192 kb
Host smart-4dc3a127-04fb-45c7-a095-fe6abf88a7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866145878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.866145878
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.514803183
Short name T41
Test name
Test status
Simulation time 1979152881 ps
CPU time 14.87 seconds
Started Jul 07 06:58:13 PM PDT 24
Finished Jul 07 06:58:28 PM PDT 24
Peak memory 226000 kb
Host smart-86cdae92-76da-46e0-817e-da7b603afbd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514803183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.514803183
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1988857913
Short name T761
Test name
Test status
Simulation time 1301474919 ps
CPU time 12.98 seconds
Started Jul 07 06:58:17 PM PDT 24
Finished Jul 07 06:58:30 PM PDT 24
Peak memory 226028 kb
Host smart-e7739b02-e3a7-42a0-a54c-f553f3ba49b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988857913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1988857913
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2430370088
Short name T695
Test name
Test status
Simulation time 2711414275 ps
CPU time 12.9 seconds
Started Jul 07 06:58:12 PM PDT 24
Finished Jul 07 06:58:25 PM PDT 24
Peak memory 218296 kb
Host smart-11b77a52-999a-40e7-9b90-939c7d5d8a71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430370088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2430370088
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4056956288
Short name T47
Test name
Test status
Simulation time 1746046959 ps
CPU time 12.36 seconds
Started Jul 07 06:58:15 PM PDT 24
Finished Jul 07 06:58:27 PM PDT 24
Peak memory 226036 kb
Host smart-3389af50-1631-40b4-a62f-beaed99f7917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056956288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4056956288
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1976536242
Short name T161
Test name
Test status
Simulation time 59011525 ps
CPU time 1.3 seconds
Started Jul 07 06:58:10 PM PDT 24
Finished Jul 07 06:58:11 PM PDT 24
Peak memory 213752 kb
Host smart-8b3f240e-7c18-4e1e-91ae-7317f14b4dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976536242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1976536242
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2409564304
Short name T456
Test name
Test status
Simulation time 294218489 ps
CPU time 26.89 seconds
Started Jul 07 06:58:09 PM PDT 24
Finished Jul 07 06:58:36 PM PDT 24
Peak memory 250984 kb
Host smart-7fbd992b-0ad9-4b97-8216-fd8805cb3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409564304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2409564304
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.4089522139
Short name T491
Test name
Test status
Simulation time 58029442 ps
CPU time 7.06 seconds
Started Jul 07 06:58:13 PM PDT 24
Finished Jul 07 06:58:21 PM PDT 24
Peak memory 246752 kb
Host smart-4a987508-7b44-4685-8499-10d602d77bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089522139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4089522139
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.511334747
Short name T657
Test name
Test status
Simulation time 65245107 ps
CPU time 0.96 seconds
Started Jul 07 06:58:09 PM PDT 24
Finished Jul 07 06:58:10 PM PDT 24
Peak memory 217720 kb
Host smart-75e77b8b-b2a3-4abe-969b-261fa34b3d79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511334747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.511334747
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.4029866859
Short name T396
Test name
Test status
Simulation time 20831004 ps
CPU time 1.22 seconds
Started Jul 07 06:54:08 PM PDT 24
Finished Jul 07 06:54:10 PM PDT 24
Peak memory 209012 kb
Host smart-72434894-51e1-4d70-8e93-65636aa02920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029866859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.4029866859
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2793519495
Short name T393
Test name
Test status
Simulation time 965339396 ps
CPU time 11.27 seconds
Started Jul 07 06:53:48 PM PDT 24
Finished Jul 07 06:54:00 PM PDT 24
Peak memory 218244 kb
Host smart-93593800-64a5-424f-9dd3-60a7a792e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793519495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2793519495
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3806047891
Short name T30
Test name
Test status
Simulation time 157588244 ps
CPU time 1.68 seconds
Started Jul 07 06:54:00 PM PDT 24
Finished Jul 07 06:54:02 PM PDT 24
Peak memory 217116 kb
Host smart-47fa6191-04ba-4e63-b3c6-6f5a90b6558d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806047891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3806047891
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1971163319
Short name T718
Test name
Test status
Simulation time 1179863310 ps
CPU time 36.94 seconds
Started Jul 07 06:54:00 PM PDT 24
Finished Jul 07 06:54:37 PM PDT 24
Peak memory 218108 kb
Host smart-0331f982-c737-448d-ad1c-542b8021877e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971163319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1971163319
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.862682201
Short name T448
Test name
Test status
Simulation time 299665313 ps
CPU time 8.28 seconds
Started Jul 07 06:54:03 PM PDT 24
Finished Jul 07 06:54:11 PM PDT 24
Peak memory 217600 kb
Host smart-e0441b8d-ab4f-4f9d-a582-77cb36cbd0a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862682201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.862682201
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2443143151
Short name T772
Test name
Test status
Simulation time 540313185 ps
CPU time 16.46 seconds
Started Jul 07 06:53:59 PM PDT 24
Finished Jul 07 06:54:15 PM PDT 24
Peak memory 218228 kb
Host smart-e428c4d0-bbde-4062-932a-2980bd081000
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443143151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2443143151
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2207161076
Short name T796
Test name
Test status
Simulation time 968787386 ps
CPU time 24.24 seconds
Started Jul 07 06:54:04 PM PDT 24
Finished Jul 07 06:54:29 PM PDT 24
Peak memory 217640 kb
Host smart-2ca5c15c-c249-4a42-a077-f4bc43c56325
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207161076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2207161076
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.200714998
Short name T777
Test name
Test status
Simulation time 939665062 ps
CPU time 3.29 seconds
Started Jul 07 06:53:53 PM PDT 24
Finished Jul 07 06:53:56 PM PDT 24
Peak memory 217676 kb
Host smart-d16636fa-3897-4fa4-b8f9-330135ff453a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200714998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.200714998
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.704354708
Short name T370
Test name
Test status
Simulation time 1455946188 ps
CPU time 43.93 seconds
Started Jul 07 06:53:53 PM PDT 24
Finished Jul 07 06:54:37 PM PDT 24
Peak memory 267360 kb
Host smart-f2bca549-9d81-493c-b5a3-baf7c2977fbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704354708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.704354708
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2830801860
Short name T656
Test name
Test status
Simulation time 892159526 ps
CPU time 13.09 seconds
Started Jul 07 06:53:55 PM PDT 24
Finished Jul 07 06:54:09 PM PDT 24
Peak memory 251268 kb
Host smart-7f381cba-245e-4773-aa2f-c6b849dccd70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830801860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2830801860
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.366111778
Short name T588
Test name
Test status
Simulation time 99326574 ps
CPU time 2.53 seconds
Started Jul 07 06:53:47 PM PDT 24
Finished Jul 07 06:53:50 PM PDT 24
Peak memory 218212 kb
Host smart-f6464d2e-24f3-41f4-b84f-776c87d0742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366111778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.366111778
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2784608747
Short name T348
Test name
Test status
Simulation time 307767516 ps
CPU time 12.53 seconds
Started Jul 07 06:53:55 PM PDT 24
Finished Jul 07 06:54:07 PM PDT 24
Peak memory 223112 kb
Host smart-e5ca0042-6c8c-4678-ac51-df00aedece1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784608747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2784608747
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.736069140
Short name T50
Test name
Test status
Simulation time 125928894 ps
CPU time 25.11 seconds
Started Jul 07 06:54:08 PM PDT 24
Finished Jul 07 06:54:33 PM PDT 24
Peak memory 269804 kb
Host smart-67f6836b-c6ac-41f4-88a0-3be77f77c6dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736069140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.736069140
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.120004967
Short name T409
Test name
Test status
Simulation time 217405016 ps
CPU time 12.12 seconds
Started Jul 07 06:54:04 PM PDT 24
Finished Jul 07 06:54:16 PM PDT 24
Peak memory 226024 kb
Host smart-3f563e4f-acc9-4eda-8a3c-861510a352ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120004967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.120004967
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.543088781
Short name T696
Test name
Test status
Simulation time 375238296 ps
CPU time 13.54 seconds
Started Jul 07 06:54:04 PM PDT 24
Finished Jul 07 06:54:18 PM PDT 24
Peak memory 225844 kb
Host smart-d3e6719e-0bd0-4617-b491-90e8f36acb38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543088781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.543088781
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2944459142
Short name T760
Test name
Test status
Simulation time 204664873 ps
CPU time 5.95 seconds
Started Jul 07 06:54:04 PM PDT 24
Finished Jul 07 06:54:10 PM PDT 24
Peak memory 225972 kb
Host smart-36e54c54-ab68-426b-aea7-201cfe52267e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944459142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
944459142
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.369365051
Short name T52
Test name
Test status
Simulation time 1261303737 ps
CPU time 9.24 seconds
Started Jul 07 06:53:52 PM PDT 24
Finished Jul 07 06:54:01 PM PDT 24
Peak memory 225364 kb
Host smart-aa71a61f-99ae-41d7-994c-4aeb627f3913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369365051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.369365051
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2060193870
Short name T849
Test name
Test status
Simulation time 851294829 ps
CPU time 25.57 seconds
Started Jul 07 06:53:51 PM PDT 24
Finished Jul 07 06:54:17 PM PDT 24
Peak memory 251092 kb
Host smart-8ad10ba1-3552-49d1-bf8f-57d4da54d467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060193870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2060193870
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2081275355
Short name T171
Test name
Test status
Simulation time 58621735 ps
CPU time 6.96 seconds
Started Jul 07 06:53:46 PM PDT 24
Finished Jul 07 06:53:53 PM PDT 24
Peak memory 246756 kb
Host smart-fc8a9d82-392b-4190-a589-bf6a8810348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081275355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2081275355
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1522579480
Short name T279
Test name
Test status
Simulation time 6893663691 ps
CPU time 80.4 seconds
Started Jul 07 06:54:02 PM PDT 24
Finished Jul 07 06:55:23 PM PDT 24
Peak memory 251036 kb
Host smart-e89fca1c-8666-4a40-803b-a9d189db13f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522579480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1522579480
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2113378155
Short name T779
Test name
Test status
Simulation time 16282025 ps
CPU time 0.95 seconds
Started Jul 07 06:53:46 PM PDT 24
Finished Jul 07 06:53:47 PM PDT 24
Peak memory 212880 kb
Host smart-0be4300a-5454-461d-8d3b-1a6be76c8164
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113378155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2113378155
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3053229070
Short name T530
Test name
Test status
Simulation time 15875132 ps
CPU time 1.06 seconds
Started Jul 07 06:58:19 PM PDT 24
Finished Jul 07 06:58:21 PM PDT 24
Peak memory 209248 kb
Host smart-b02fdfc8-4a69-4677-9cad-c8e389441cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053229070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3053229070
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1339710925
Short name T18
Test name
Test status
Simulation time 652541307 ps
CPU time 18.33 seconds
Started Jul 07 06:58:17 PM PDT 24
Finished Jul 07 06:58:35 PM PDT 24
Peak memory 218220 kb
Host smart-905aeb24-fefe-4537-9b88-121516621eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339710925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1339710925
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2619642949
Short name T5
Test name
Test status
Simulation time 352554928 ps
CPU time 4.81 seconds
Started Jul 07 06:58:21 PM PDT 24
Finished Jul 07 06:58:26 PM PDT 24
Peak memory 217100 kb
Host smart-1f2272a6-7a58-4879-9c30-632bb14ace00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619642949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2619642949
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1738592191
Short name T377
Test name
Test status
Simulation time 544111234 ps
CPU time 4.05 seconds
Started Jul 07 06:58:16 PM PDT 24
Finished Jul 07 06:58:21 PM PDT 24
Peak memory 218220 kb
Host smart-2aa40e76-6e91-40af-b060-55f45d4dac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738592191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1738592191
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.771713377
Short name T543
Test name
Test status
Simulation time 1150165365 ps
CPU time 17.15 seconds
Started Jul 07 06:58:22 PM PDT 24
Finished Jul 07 06:58:39 PM PDT 24
Peak memory 218228 kb
Host smart-0fed3957-e38f-489b-9382-8a762c873fd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771713377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.771713377
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.386345426
Short name T768
Test name
Test status
Simulation time 271846389 ps
CPU time 7.58 seconds
Started Jul 07 06:58:21 PM PDT 24
Finished Jul 07 06:58:29 PM PDT 24
Peak memory 226036 kb
Host smart-bdcbbc59-49f2-4de3-9dfc-5f6fcb7eb25c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386345426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.386345426
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2959159517
Short name T822
Test name
Test status
Simulation time 705950147 ps
CPU time 13.21 seconds
Started Jul 07 06:58:19 PM PDT 24
Finished Jul 07 06:58:33 PM PDT 24
Peak memory 226000 kb
Host smart-f7fa5ad8-a967-46fd-ad55-b7bfbc1e237a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959159517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2959159517
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.707263732
Short name T12
Test name
Test status
Simulation time 1248432865 ps
CPU time 14.34 seconds
Started Jul 07 06:58:18 PM PDT 24
Finished Jul 07 06:58:33 PM PDT 24
Peak memory 218288 kb
Host smart-90a795a6-2cca-4db2-bbff-a8de22e45c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707263732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.707263732
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3995963410
Short name T493
Test name
Test status
Simulation time 81880625 ps
CPU time 1.45 seconds
Started Jul 07 06:58:16 PM PDT 24
Finished Jul 07 06:58:18 PM PDT 24
Peak memory 217712 kb
Host smart-aad11da0-d1f6-4344-96e5-4178350b58cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995963410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3995963410
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3175096438
Short name T59
Test name
Test status
Simulation time 163252929 ps
CPU time 25.18 seconds
Started Jul 07 06:58:17 PM PDT 24
Finished Jul 07 06:58:42 PM PDT 24
Peak memory 251008 kb
Host smart-7a5b9fdf-730f-4d61-af0b-a74b6eb332ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175096438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3175096438
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1824781624
Short name T586
Test name
Test status
Simulation time 237941495 ps
CPU time 5.64 seconds
Started Jul 07 06:58:16 PM PDT 24
Finished Jul 07 06:58:21 PM PDT 24
Peak memory 246640 kb
Host smart-377a5fab-0307-408d-8249-758b3956c52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824781624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1824781624
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1624754722
Short name T253
Test name
Test status
Simulation time 38187282443 ps
CPU time 79.67 seconds
Started Jul 07 06:58:19 PM PDT 24
Finished Jul 07 06:59:39 PM PDT 24
Peak memory 272840 kb
Host smart-847711bc-6a79-454a-8746-8dcc7a61fc72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624754722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1624754722
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3155174567
Short name T386
Test name
Test status
Simulation time 32828834 ps
CPU time 0.94 seconds
Started Jul 07 06:58:15 PM PDT 24
Finished Jul 07 06:58:17 PM PDT 24
Peak memory 211936 kb
Host smart-e44bd1a3-d203-45a6-844e-a4436b520067
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155174567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3155174567
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.226648581
Short name T173
Test name
Test status
Simulation time 1054899909 ps
CPU time 14.01 seconds
Started Jul 07 06:58:26 PM PDT 24
Finished Jul 07 06:58:40 PM PDT 24
Peak memory 218484 kb
Host smart-aeb2863b-203f-4640-998f-0569ad861019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226648581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.226648581
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.841300868
Short name T862
Test name
Test status
Simulation time 380204534 ps
CPU time 3.27 seconds
Started Jul 07 06:58:22 PM PDT 24
Finished Jul 07 06:58:25 PM PDT 24
Peak memory 217200 kb
Host smart-72f730a5-8b78-42e6-a306-2d9c0e133ed5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841300868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.841300868
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.223479455
Short name T233
Test name
Test status
Simulation time 112913109 ps
CPU time 2.37 seconds
Started Jul 07 06:58:25 PM PDT 24
Finished Jul 07 06:58:27 PM PDT 24
Peak memory 218208 kb
Host smart-03903fab-70e5-47f2-868c-7da6e99c51e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223479455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.223479455
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2690037398
Short name T380
Test name
Test status
Simulation time 420261020 ps
CPU time 14.47 seconds
Started Jul 07 06:58:22 PM PDT 24
Finished Jul 07 06:58:37 PM PDT 24
Peak memory 226072 kb
Host smart-cf316d8a-958c-4a43-b34d-40e0e86276d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690037398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2690037398
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3502865980
Short name T291
Test name
Test status
Simulation time 867428035 ps
CPU time 15.27 seconds
Started Jul 07 06:58:25 PM PDT 24
Finished Jul 07 06:58:41 PM PDT 24
Peak memory 218256 kb
Host smart-aca30a44-91be-46f6-b95a-52a2e683c71f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502865980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3502865980
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.351400788
Short name T743
Test name
Test status
Simulation time 257066696 ps
CPU time 7.87 seconds
Started Jul 07 06:58:24 PM PDT 24
Finished Jul 07 06:58:32 PM PDT 24
Peak memory 226032 kb
Host smart-23fbcb39-4b94-47f8-ada2-fc9c5020d11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351400788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.351400788
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1315047321
Short name T76
Test name
Test status
Simulation time 89866812 ps
CPU time 3.15 seconds
Started Jul 07 06:58:19 PM PDT 24
Finished Jul 07 06:58:23 PM PDT 24
Peak memory 214680 kb
Host smart-a6180598-7384-40df-a3f8-1223290e1988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315047321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1315047321
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1305326189
Short name T523
Test name
Test status
Simulation time 149391648 ps
CPU time 21.87 seconds
Started Jul 07 06:58:18 PM PDT 24
Finished Jul 07 06:58:40 PM PDT 24
Peak memory 250920 kb
Host smart-8944dc88-342a-4c9a-9a69-d257235897f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305326189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1305326189
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2731759101
Short name T646
Test name
Test status
Simulation time 151572453 ps
CPU time 6.49 seconds
Started Jul 07 06:58:24 PM PDT 24
Finished Jul 07 06:58:31 PM PDT 24
Peak memory 250560 kb
Host smart-ca7f9d99-e113-4657-807f-6a1da1d54441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731759101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2731759101
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.929966630
Short name T323
Test name
Test status
Simulation time 4982702683 ps
CPU time 97 seconds
Started Jul 07 06:58:25 PM PDT 24
Finished Jul 07 07:00:03 PM PDT 24
Peak memory 251048 kb
Host smart-43c3953d-325c-42f8-870d-e71403e82fba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929966630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.929966630
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3736014823
Short name T859
Test name
Test status
Simulation time 13358879 ps
CPU time 0.9 seconds
Started Jul 07 06:58:23 PM PDT 24
Finished Jul 07 06:58:24 PM PDT 24
Peak memory 212012 kb
Host smart-a623d2c3-c23f-4ac6-82d7-9d3ed9a08563
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736014823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3736014823
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1379072459
Short name T440
Test name
Test status
Simulation time 34956791 ps
CPU time 1.17 seconds
Started Jul 07 06:58:30 PM PDT 24
Finished Jul 07 06:58:32 PM PDT 24
Peak memory 209088 kb
Host smart-4c26d0d7-c203-4fb6-8979-967d1bfa7827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379072459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1379072459
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3155678260
Short name T305
Test name
Test status
Simulation time 842379522 ps
CPU time 13.07 seconds
Started Jul 07 06:58:27 PM PDT 24
Finished Jul 07 06:58:40 PM PDT 24
Peak memory 218180 kb
Host smart-61c0af8e-acb4-4f06-b0a8-d816922e6bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155678260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3155678260
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1801863256
Short name T436
Test name
Test status
Simulation time 2547582515 ps
CPU time 3.55 seconds
Started Jul 07 06:58:25 PM PDT 24
Finished Jul 07 06:58:29 PM PDT 24
Peak memory 217560 kb
Host smart-a16645cc-d946-400a-8283-4850192f3e55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801863256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1801863256
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1051631139
Short name T707
Test name
Test status
Simulation time 99535420 ps
CPU time 2.87 seconds
Started Jul 07 06:58:30 PM PDT 24
Finished Jul 07 06:58:33 PM PDT 24
Peak memory 218480 kb
Host smart-6310d8d3-8387-4aa4-918d-42e7b942d188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051631139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1051631139
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1342117860
Short name T394
Test name
Test status
Simulation time 1192293571 ps
CPU time 15.63 seconds
Started Jul 07 06:58:28 PM PDT 24
Finished Jul 07 06:58:43 PM PDT 24
Peak memory 226040 kb
Host smart-c02afa22-3d45-4734-bd25-bc86e3dbf86f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342117860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1342117860
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3202227495
Short name T611
Test name
Test status
Simulation time 492020921 ps
CPU time 13.49 seconds
Started Jul 07 06:58:29 PM PDT 24
Finished Jul 07 06:58:43 PM PDT 24
Peak memory 226024 kb
Host smart-794abca8-ed51-49e6-9162-6656b3f77d77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202227495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3202227495
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1124096459
Short name T639
Test name
Test status
Simulation time 792274510 ps
CPU time 10.46 seconds
Started Jul 07 06:58:32 PM PDT 24
Finished Jul 07 06:58:43 PM PDT 24
Peak memory 218260 kb
Host smart-d3748c90-c31e-4cd0-83b5-e99a793b8e38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124096459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1124096459
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1527760998
Short name T687
Test name
Test status
Simulation time 540730767 ps
CPU time 11.14 seconds
Started Jul 07 06:58:28 PM PDT 24
Finished Jul 07 06:58:40 PM PDT 24
Peak memory 224632 kb
Host smart-a11fdc30-5edb-42b9-8fd8-490afa67888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527760998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1527760998
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3798997110
Short name T312
Test name
Test status
Simulation time 211551177 ps
CPU time 2.48 seconds
Started Jul 07 06:58:30 PM PDT 24
Finished Jul 07 06:58:33 PM PDT 24
Peak memory 214384 kb
Host smart-936e875d-18f6-42d1-9f23-449fc8a3719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798997110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3798997110
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1671528631
Short name T14
Test name
Test status
Simulation time 277606949 ps
CPU time 32.8 seconds
Started Jul 07 06:58:26 PM PDT 24
Finished Jul 07 06:58:59 PM PDT 24
Peak memory 250992 kb
Host smart-1892a6c8-a100-417a-b814-0b444119efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671528631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1671528631
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2178036980
Short name T336
Test name
Test status
Simulation time 164276270 ps
CPU time 4.32 seconds
Started Jul 07 06:58:26 PM PDT 24
Finished Jul 07 06:58:31 PM PDT 24
Peak memory 222720 kb
Host smart-55811b5a-e9f9-4b43-8b6c-c140b1c47e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178036980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2178036980
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2908472204
Short name T625
Test name
Test status
Simulation time 60883310484 ps
CPU time 949.12 seconds
Started Jul 07 06:58:31 PM PDT 24
Finished Jul 07 07:14:20 PM PDT 24
Peak memory 283808 kb
Host smart-825f636a-872d-48ee-a539-75bf0078c09a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908472204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2908472204
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2990760038
Short name T260
Test name
Test status
Simulation time 23272483 ps
CPU time 0.88 seconds
Started Jul 07 06:58:26 PM PDT 24
Finished Jul 07 06:58:27 PM PDT 24
Peak memory 211864 kb
Host smart-69a6056f-e6b0-4539-8038-c4bde8af9377
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990760038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2990760038
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1624796074
Short name T333
Test name
Test status
Simulation time 29229455 ps
CPU time 0.89 seconds
Started Jul 07 06:58:35 PM PDT 24
Finished Jul 07 06:58:37 PM PDT 24
Peak memory 208924 kb
Host smart-28e48e8b-72b2-44d6-b031-b23ef1639570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624796074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1624796074
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2665730851
Short name T552
Test name
Test status
Simulation time 2360684079 ps
CPU time 16.92 seconds
Started Jul 07 06:58:30 PM PDT 24
Finished Jul 07 06:58:47 PM PDT 24
Peak memory 218932 kb
Host smart-39c0bce9-2c9a-4457-9d2c-e92ea9c25934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665730851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2665730851
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2135434743
Short name T856
Test name
Test status
Simulation time 77961474 ps
CPU time 1.59 seconds
Started Jul 07 06:58:31 PM PDT 24
Finished Jul 07 06:58:33 PM PDT 24
Peak memory 217120 kb
Host smart-efe4db54-aace-47a8-8d4e-aeadfddb23c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135434743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2135434743
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3149725419
Short name T25
Test name
Test status
Simulation time 130804773 ps
CPU time 3.39 seconds
Started Jul 07 06:58:30 PM PDT 24
Finished Jul 07 06:58:34 PM PDT 24
Peak memory 218176 kb
Host smart-d2d8ef43-7a51-488d-aa1e-db8f74f5b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149725419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3149725419
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.403580820
Short name T564
Test name
Test status
Simulation time 497966491 ps
CPU time 12.91 seconds
Started Jul 07 06:58:34 PM PDT 24
Finished Jul 07 06:58:47 PM PDT 24
Peak memory 226072 kb
Host smart-eaa5294f-41bb-4cb9-817c-7558575cea95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403580820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.403580820
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.187601079
Short name T613
Test name
Test status
Simulation time 302849462 ps
CPU time 13.25 seconds
Started Jul 07 06:58:35 PM PDT 24
Finished Jul 07 06:58:48 PM PDT 24
Peak memory 226000 kb
Host smart-99272999-4f06-41c3-a8d0-cb78a27fe00c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187601079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.187601079
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.844664682
Short name T53
Test name
Test status
Simulation time 1917411640 ps
CPU time 14.62 seconds
Started Jul 07 06:58:35 PM PDT 24
Finished Jul 07 06:58:49 PM PDT 24
Peak memory 225912 kb
Host smart-02537265-ba68-487f-9c97-07edc0507820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844664682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.844664682
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1579842907
Short name T477
Test name
Test status
Simulation time 315177859 ps
CPU time 5.16 seconds
Started Jul 07 06:58:29 PM PDT 24
Finished Jul 07 06:58:34 PM PDT 24
Peak memory 217720 kb
Host smart-b05314ab-3993-4cea-bb3e-7e949a438da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579842907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1579842907
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2564919402
Short name T298
Test name
Test status
Simulation time 584937812 ps
CPU time 22.63 seconds
Started Jul 07 06:58:32 PM PDT 24
Finished Jul 07 06:58:55 PM PDT 24
Peak memory 250976 kb
Host smart-771c5d39-e529-4983-94ab-0118e2a8f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564919402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2564919402
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1635643451
Short name T300
Test name
Test status
Simulation time 90451954 ps
CPU time 3.04 seconds
Started Jul 07 06:58:30 PM PDT 24
Finished Jul 07 06:58:34 PM PDT 24
Peak memory 218224 kb
Host smart-857ddba8-c35c-4924-8ea6-fbb52aab7ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635643451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1635643451
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3891281276
Short name T595
Test name
Test status
Simulation time 5666063344 ps
CPU time 133.79 seconds
Started Jul 07 06:58:37 PM PDT 24
Finished Jul 07 07:00:51 PM PDT 24
Peak memory 283816 kb
Host smart-ac5f38f9-5a22-40dd-b718-b99e5b470351
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891281276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3891281276
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.836605996
Short name T353
Test name
Test status
Simulation time 24245511 ps
CPU time 1 seconds
Started Jul 07 06:58:35 PM PDT 24
Finished Jul 07 06:58:36 PM PDT 24
Peak memory 211964 kb
Host smart-d76917cf-5f36-469a-b681-6ad355d0e063
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836605996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.836605996
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2274795133
Short name T406
Test name
Test status
Simulation time 21499672 ps
CPU time 0.91 seconds
Started Jul 07 06:58:41 PM PDT 24
Finished Jul 07 06:58:42 PM PDT 24
Peak memory 209012 kb
Host smart-9de2bef7-9b8d-4510-87f3-b4cced12b2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274795133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2274795133
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.996829948
Short name T711
Test name
Test status
Simulation time 2473040744 ps
CPU time 11.69 seconds
Started Jul 07 06:58:36 PM PDT 24
Finished Jul 07 06:58:48 PM PDT 24
Peak memory 219016 kb
Host smart-3141ab03-c137-46e3-a0ac-ed349a93a44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996829948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.996829948
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.35059038
Short name T626
Test name
Test status
Simulation time 259323167 ps
CPU time 1.58 seconds
Started Jul 07 06:58:38 PM PDT 24
Finished Jul 07 06:58:40 PM PDT 24
Peak memory 217088 kb
Host smart-9840ead8-3e9e-4d64-85cb-d33168dec735
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35059038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.35059038
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3391093941
Short name T329
Test name
Test status
Simulation time 418273852 ps
CPU time 3.2 seconds
Started Jul 07 06:58:39 PM PDT 24
Finished Jul 07 06:58:42 PM PDT 24
Peak memory 218428 kb
Host smart-513a8daf-b618-4568-a121-728e63d774ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391093941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3391093941
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1602735476
Short name T661
Test name
Test status
Simulation time 216182232 ps
CPU time 8.75 seconds
Started Jul 07 06:58:36 PM PDT 24
Finished Jul 07 06:58:45 PM PDT 24
Peak memory 226032 kb
Host smart-4a4fdd6f-f407-428c-87c5-3e859627701a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602735476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1602735476
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3432740629
Short name T269
Test name
Test status
Simulation time 214243029 ps
CPU time 9.08 seconds
Started Jul 07 06:58:39 PM PDT 24
Finished Jul 07 06:58:49 PM PDT 24
Peak memory 226036 kb
Host smart-aaf4f32d-1a90-49a9-97d2-891b573ce6a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432740629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3432740629
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.962506999
Short name T360
Test name
Test status
Simulation time 2277233229 ps
CPU time 10.04 seconds
Started Jul 07 06:58:37 PM PDT 24
Finished Jul 07 06:58:47 PM PDT 24
Peak memory 218308 kb
Host smart-1aa317b1-5bbe-4dd5-8bef-4fbca3d66129
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962506999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.962506999
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.4161511473
Short name T249
Test name
Test status
Simulation time 213961193 ps
CPU time 7.54 seconds
Started Jul 07 06:58:35 PM PDT 24
Finished Jul 07 06:58:43 PM PDT 24
Peak memory 218288 kb
Host smart-1c582188-7064-4b73-bbeb-11a2583f6a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161511473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.4161511473
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3649178183
Short name T73
Test name
Test status
Simulation time 33642954 ps
CPU time 2.32 seconds
Started Jul 07 06:58:34 PM PDT 24
Finished Jul 07 06:58:36 PM PDT 24
Peak memory 214392 kb
Host smart-7964564a-585f-44f5-9f13-06b45c507f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649178183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3649178183
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.26490531
Short name T332
Test name
Test status
Simulation time 262052955 ps
CPU time 34.67 seconds
Started Jul 07 06:58:33 PM PDT 24
Finished Jul 07 06:59:08 PM PDT 24
Peak memory 251044 kb
Host smart-285a5158-555c-43b9-bb7f-eb7ca9dd2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26490531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.26490531
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3623146467
Short name T754
Test name
Test status
Simulation time 225137285 ps
CPU time 7.3 seconds
Started Jul 07 06:58:36 PM PDT 24
Finished Jul 07 06:58:44 PM PDT 24
Peak memory 250956 kb
Host smart-31d93a0f-b8a3-4a11-ab10-0b9319a7edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623146467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3623146467
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3102965845
Short name T578
Test name
Test status
Simulation time 2448007753 ps
CPU time 84.09 seconds
Started Jul 07 06:58:37 PM PDT 24
Finished Jul 07 07:00:01 PM PDT 24
Peak memory 250844 kb
Host smart-b5dfd109-3b6f-475b-8b3e-c9cbb1a84543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102965845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3102965845
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.4186177210
Short name T84
Test name
Test status
Simulation time 18230160178 ps
CPU time 301.07 seconds
Started Jul 07 06:58:40 PM PDT 24
Finished Jul 07 07:03:41 PM PDT 24
Peak memory 251192 kb
Host smart-e32e79b6-33c2-4716-8695-db2a2800f774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4186177210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.4186177210
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.133304385
Short name T750
Test name
Test status
Simulation time 21445481 ps
CPU time 0.96 seconds
Started Jul 07 06:58:36 PM PDT 24
Finished Jul 07 06:58:37 PM PDT 24
Peak memory 211832 kb
Host smart-7e582588-ce0e-4b68-8248-8fb400c3cae5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133304385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.133304385
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2918358928
Short name T541
Test name
Test status
Simulation time 78623161 ps
CPU time 1.19 seconds
Started Jul 07 06:58:42 PM PDT 24
Finished Jul 07 06:58:43 PM PDT 24
Peak memory 209240 kb
Host smart-aca60dfd-11d2-45ab-aeaf-ab14838e22a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918358928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2918358928
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.838090660
Short name T42
Test name
Test status
Simulation time 1278528325 ps
CPU time 10.98 seconds
Started Jul 07 06:58:42 PM PDT 24
Finished Jul 07 06:58:53 PM PDT 24
Peak memory 218228 kb
Host smart-f6d0206c-7d75-41da-a65a-f8094b916b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838090660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.838090660
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2844226675
Short name T26
Test name
Test status
Simulation time 155675180 ps
CPU time 2.72 seconds
Started Jul 07 06:58:42 PM PDT 24
Finished Jul 07 06:58:45 PM PDT 24
Peak memory 217084 kb
Host smart-97001be1-6807-4c47-8d8f-eb9259d220b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844226675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2844226675
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3278145245
Short name T713
Test name
Test status
Simulation time 79998873 ps
CPU time 3.28 seconds
Started Jul 07 06:58:41 PM PDT 24
Finished Jul 07 06:58:45 PM PDT 24
Peak memory 218224 kb
Host smart-1ee7eb85-3ff5-487d-a1bd-73b41a23d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278145245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3278145245
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2860439988
Short name T565
Test name
Test status
Simulation time 578177514 ps
CPU time 14.04 seconds
Started Jul 07 06:58:40 PM PDT 24
Finished Jul 07 06:58:55 PM PDT 24
Peak memory 226036 kb
Host smart-bb423bff-c185-4758-8201-8854d449aada
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860439988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2860439988
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2277674443
Short name T614
Test name
Test status
Simulation time 394315507 ps
CPU time 12.7 seconds
Started Jul 07 06:58:43 PM PDT 24
Finished Jul 07 06:58:56 PM PDT 24
Peak memory 218244 kb
Host smart-ac2cf73e-4999-4cce-90d1-02c0d0d23644
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277674443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2277674443
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1284582090
Short name T306
Test name
Test status
Simulation time 730576171 ps
CPU time 9.55 seconds
Started Jul 07 06:58:44 PM PDT 24
Finished Jul 07 06:58:54 PM PDT 24
Peak memory 218232 kb
Host smart-021953b1-824d-4d5f-81ae-a8e59658341b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284582090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1284582090
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3689127292
Short name T289
Test name
Test status
Simulation time 932521413 ps
CPU time 11.43 seconds
Started Jul 07 06:58:43 PM PDT 24
Finished Jul 07 06:58:55 PM PDT 24
Peak memory 226008 kb
Host smart-c6b0ddd4-6665-4780-ac13-f461f74247d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689127292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3689127292
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3069755838
Short name T677
Test name
Test status
Simulation time 132502921 ps
CPU time 2.74 seconds
Started Jul 07 06:58:39 PM PDT 24
Finished Jul 07 06:58:42 PM PDT 24
Peak memory 217980 kb
Host smart-c0e3dccc-3ddc-47b3-a0d8-a6ec0f9fba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069755838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3069755838
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1463427355
Short name T693
Test name
Test status
Simulation time 1243728984 ps
CPU time 30.51 seconds
Started Jul 07 06:58:40 PM PDT 24
Finished Jul 07 06:59:10 PM PDT 24
Peak memory 250948 kb
Host smart-52349fcf-f88d-41fc-94f8-0a3e84a306fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463427355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1463427355
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1485314681
Short name T841
Test name
Test status
Simulation time 80197061 ps
CPU time 7.58 seconds
Started Jul 07 06:58:37 PM PDT 24
Finished Jul 07 06:58:45 PM PDT 24
Peak memory 250964 kb
Host smart-a90d9eb4-2015-4303-9322-f359788ae61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485314681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1485314681
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2614705113
Short name T262
Test name
Test status
Simulation time 4241661249 ps
CPU time 89.05 seconds
Started Jul 07 06:58:41 PM PDT 24
Finished Jul 07 07:00:10 PM PDT 24
Peak memory 283752 kb
Host smart-ef82cf1c-84f5-4df7-ad4a-c5d6e266718a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614705113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2614705113
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.295483491
Short name T341
Test name
Test status
Simulation time 24064958 ps
CPU time 0.94 seconds
Started Jul 07 06:58:40 PM PDT 24
Finished Jul 07 06:58:41 PM PDT 24
Peak memory 213080 kb
Host smart-e6ac9661-e94d-45c0-bc10-404b731fd35e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295483491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.295483491
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3420784776
Short name T770
Test name
Test status
Simulation time 18620383 ps
CPU time 0.91 seconds
Started Jul 07 06:58:48 PM PDT 24
Finished Jul 07 06:58:49 PM PDT 24
Peak memory 209052 kb
Host smart-106636ae-678b-4f15-842f-2f418af5b859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420784776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3420784776
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2299826276
Short name T714
Test name
Test status
Simulation time 2106921468 ps
CPU time 14.47 seconds
Started Jul 07 06:58:44 PM PDT 24
Finished Jul 07 06:58:58 PM PDT 24
Peak memory 226052 kb
Host smart-d4edfbeb-5d6b-4190-a896-c2d6b24c5640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299826276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2299826276
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2448296891
Short name T32
Test name
Test status
Simulation time 3925955022 ps
CPU time 8.76 seconds
Started Jul 07 06:58:47 PM PDT 24
Finished Jul 07 06:58:56 PM PDT 24
Peak memory 217776 kb
Host smart-906b8a98-0feb-4a2d-a9c4-29672d2cfa42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448296891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2448296891
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.84766558
Short name T91
Test name
Test status
Simulation time 264173202 ps
CPU time 2.92 seconds
Started Jul 07 06:58:44 PM PDT 24
Finished Jul 07 06:58:47 PM PDT 24
Peak memory 218296 kb
Host smart-838945f0-a48c-4792-914b-5a7f37b1caf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84766558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.84766558
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.588160598
Short name T185
Test name
Test status
Simulation time 460660825 ps
CPU time 12.92 seconds
Started Jul 07 06:58:47 PM PDT 24
Finished Jul 07 06:59:00 PM PDT 24
Peak memory 226024 kb
Host smart-61212f5d-65ff-4248-bd4c-5b09b6f2b86b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588160598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.588160598
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1645584608
Short name T506
Test name
Test status
Simulation time 1934527371 ps
CPU time 14.43 seconds
Started Jul 07 06:58:46 PM PDT 24
Finished Jul 07 06:59:01 PM PDT 24
Peak memory 218236 kb
Host smart-4cd48626-0667-4717-a016-ac94e9c568b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645584608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1645584608
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3704872064
Short name T817
Test name
Test status
Simulation time 1783998781 ps
CPU time 12.08 seconds
Started Jul 07 06:58:46 PM PDT 24
Finished Jul 07 06:58:58 PM PDT 24
Peak memory 225024 kb
Host smart-68b3ad77-be6e-4d56-9368-854463bed7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704872064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3704872064
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.936452988
Short name T62
Test name
Test status
Simulation time 51045289 ps
CPU time 2.73 seconds
Started Jul 07 06:58:42 PM PDT 24
Finished Jul 07 06:58:45 PM PDT 24
Peak memory 217724 kb
Host smart-817ab98e-3f0e-4560-97ee-ede999eeb61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936452988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.936452988
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2422962259
Short name T575
Test name
Test status
Simulation time 195771086 ps
CPU time 22.79 seconds
Started Jul 07 06:58:45 PM PDT 24
Finished Jul 07 06:59:08 PM PDT 24
Peak memory 250932 kb
Host smart-2995c2da-b644-4fc6-968f-5cdc9ab57adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422962259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2422962259
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1318015498
Short name T781
Test name
Test status
Simulation time 168509188 ps
CPU time 3.13 seconds
Started Jul 07 06:58:46 PM PDT 24
Finished Jul 07 06:58:49 PM PDT 24
Peak memory 218220 kb
Host smart-143780ad-10e2-4b47-af6a-dfd8bd3b69e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318015498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1318015498
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1081391262
Short name T223
Test name
Test status
Simulation time 7108304535 ps
CPU time 241.48 seconds
Started Jul 07 06:58:49 PM PDT 24
Finished Jul 07 07:02:51 PM PDT 24
Peak memory 316540 kb
Host smart-b9f3d909-b361-48dd-a35b-13f49e503659
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081391262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1081391262
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1695299185
Short name T187
Test name
Test status
Simulation time 30224791 ps
CPU time 0.85 seconds
Started Jul 07 06:58:47 PM PDT 24
Finished Jul 07 06:58:48 PM PDT 24
Peak memory 212024 kb
Host smart-d5555878-4a12-4bb8-844e-75acfb1ccd80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695299185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1695299185
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3976858321
Short name T410
Test name
Test status
Simulation time 31143481 ps
CPU time 1.05 seconds
Started Jul 07 06:58:51 PM PDT 24
Finished Jul 07 06:58:53 PM PDT 24
Peak memory 208936 kb
Host smart-95a69bd7-4325-4ed6-85e9-eb93db338047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976858321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3976858321
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.549504249
Short name T419
Test name
Test status
Simulation time 332487849 ps
CPU time 14.63 seconds
Started Jul 07 06:58:50 PM PDT 24
Finished Jul 07 06:59:05 PM PDT 24
Peak memory 226068 kb
Host smart-2c9fb63d-90c8-4772-bd17-14ccd02bab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549504249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.549504249
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3927060458
Short name T643
Test name
Test status
Simulation time 104975530 ps
CPU time 1.97 seconds
Started Jul 07 06:58:51 PM PDT 24
Finished Jul 07 06:58:53 PM PDT 24
Peak memory 217080 kb
Host smart-79bb3deb-456d-4b8a-8a3b-3a536e1c670a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927060458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3927060458
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1671042902
Short name T381
Test name
Test status
Simulation time 64914294 ps
CPU time 2.87 seconds
Started Jul 07 06:58:50 PM PDT 24
Finished Jul 07 06:58:53 PM PDT 24
Peak memory 218496 kb
Host smart-08bad383-eab9-4f7c-ac8b-cec80e5cd97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671042902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1671042902
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2302401331
Short name T321
Test name
Test status
Simulation time 1699808921 ps
CPU time 17.61 seconds
Started Jul 07 06:58:52 PM PDT 24
Finished Jul 07 06:59:09 PM PDT 24
Peak memory 226032 kb
Host smart-7ddd86d2-a1ba-4169-91f9-a1e67d9aaf8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302401331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2302401331
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4268600741
Short name T623
Test name
Test status
Simulation time 253866008 ps
CPU time 10.71 seconds
Started Jul 07 06:58:52 PM PDT 24
Finished Jul 07 06:59:03 PM PDT 24
Peak memory 226020 kb
Host smart-18be3ecd-10f8-40cb-b478-495946b218ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268600741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.4268600741
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1691658377
Short name T413
Test name
Test status
Simulation time 366035092 ps
CPU time 13.86 seconds
Started Jul 07 06:58:53 PM PDT 24
Finished Jul 07 06:59:07 PM PDT 24
Peak memory 218252 kb
Host smart-bd25881a-44dc-489e-8a8a-884cf2026a8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691658377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1691658377
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2643428793
Short name T318
Test name
Test status
Simulation time 281178265 ps
CPU time 7.31 seconds
Started Jul 07 06:58:53 PM PDT 24
Finished Jul 07 06:59:01 PM PDT 24
Peak memory 225068 kb
Host smart-14514504-447e-4ea7-8693-d3cb8c5175e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643428793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2643428793
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2146362145
Short name T61
Test name
Test status
Simulation time 38673273 ps
CPU time 2.45 seconds
Started Jul 07 06:58:49 PM PDT 24
Finished Jul 07 06:58:52 PM PDT 24
Peak memory 217748 kb
Host smart-4d12d09c-3f65-4161-9924-3904d8bd8844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146362145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2146362145
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.132494828
Short name T723
Test name
Test status
Simulation time 248987432 ps
CPU time 25.42 seconds
Started Jul 07 06:58:50 PM PDT 24
Finished Jul 07 06:59:16 PM PDT 24
Peak memory 250972 kb
Host smart-5e1bac04-f920-4856-ae03-24e9d87bbb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132494828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.132494828
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1747210002
Short name T563
Test name
Test status
Simulation time 235995149 ps
CPU time 6.5 seconds
Started Jul 07 06:58:50 PM PDT 24
Finished Jul 07 06:58:56 PM PDT 24
Peak memory 246344 kb
Host smart-2f4600ad-e71f-486c-a6bb-d49567d4a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747210002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1747210002
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3649350166
Short name T116
Test name
Test status
Simulation time 21938524018 ps
CPU time 222.96 seconds
Started Jul 07 06:58:50 PM PDT 24
Finished Jul 07 07:02:34 PM PDT 24
Peak memory 271304 kb
Host smart-7aae18dc-6c52-4cca-bc6a-1fccca3b9908
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649350166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3649350166
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.320349181
Short name T349
Test name
Test status
Simulation time 34266341 ps
CPU time 0.88 seconds
Started Jul 07 06:58:51 PM PDT 24
Finished Jul 07 06:58:52 PM PDT 24
Peak memory 211880 kb
Host smart-7e5c9d93-d6e2-46fc-a95b-135f5056e823
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320349181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.320349181
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3253252139
Short name T727
Test name
Test status
Simulation time 13663627 ps
CPU time 1.1 seconds
Started Jul 07 06:59:01 PM PDT 24
Finished Jul 07 06:59:02 PM PDT 24
Peak memory 208956 kb
Host smart-b176929e-9284-468c-aca1-ff230a25e97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253252139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3253252139
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1461999668
Short name T259
Test name
Test status
Simulation time 660840827 ps
CPU time 9.68 seconds
Started Jul 07 06:58:57 PM PDT 24
Finished Jul 07 06:59:07 PM PDT 24
Peak memory 225996 kb
Host smart-d14759e1-9476-41fe-b0f4-26dc5b4a469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461999668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1461999668
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.750705314
Short name T486
Test name
Test status
Simulation time 574216592 ps
CPU time 5.19 seconds
Started Jul 07 06:58:58 PM PDT 24
Finished Jul 07 06:59:03 PM PDT 24
Peak memory 217732 kb
Host smart-f7987e09-075f-4cd3-ae26-2bf39df6b46a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750705314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.750705314
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1195505264
Short name T65
Test name
Test status
Simulation time 129205527 ps
CPU time 2.11 seconds
Started Jul 07 06:58:57 PM PDT 24
Finished Jul 07 06:59:00 PM PDT 24
Peak memory 218172 kb
Host smart-aaa888e9-d2b2-4403-a7f7-ced663a87c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195505264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1195505264
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2086572557
Short name T654
Test name
Test status
Simulation time 5269704762 ps
CPU time 13.85 seconds
Started Jul 07 06:59:01 PM PDT 24
Finished Jul 07 06:59:15 PM PDT 24
Peak memory 218944 kb
Host smart-804a629e-fa3f-429e-a345-c069acf087eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086572557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2086572557
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3024772140
Short name T697
Test name
Test status
Simulation time 865510305 ps
CPU time 11.47 seconds
Started Jul 07 06:59:01 PM PDT 24
Finished Jul 07 06:59:12 PM PDT 24
Peak memory 226028 kb
Host smart-c5b72281-ed07-4851-bd72-0f6ad8c39662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024772140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3024772140
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.39087818
Short name T788
Test name
Test status
Simulation time 1600140720 ps
CPU time 9.75 seconds
Started Jul 07 06:59:02 PM PDT 24
Finished Jul 07 06:59:12 PM PDT 24
Peak memory 218240 kb
Host smart-3a17fd00-4a66-4b5f-91e8-9805d4a51e93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39087818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.39087818
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3782447806
Short name T853
Test name
Test status
Simulation time 676141920 ps
CPU time 12.18 seconds
Started Jul 07 06:58:57 PM PDT 24
Finished Jul 07 06:59:09 PM PDT 24
Peak memory 226040 kb
Host smart-d06fbed9-e8ca-459c-87be-1f3c17a62df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782447806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3782447806
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1429077970
Short name T86
Test name
Test status
Simulation time 86866974 ps
CPU time 2.59 seconds
Started Jul 07 06:58:58 PM PDT 24
Finished Jul 07 06:59:01 PM PDT 24
Peak memory 214652 kb
Host smart-72d30426-cc1c-469a-8c7e-b046aa92e725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429077970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1429077970
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1092169468
Short name T708
Test name
Test status
Simulation time 1822426508 ps
CPU time 26.72 seconds
Started Jul 07 06:58:58 PM PDT 24
Finished Jul 07 06:59:25 PM PDT 24
Peak memory 250984 kb
Host smart-ce1f8488-4aa0-48c0-ac0d-9088d209a21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092169468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1092169468
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2901398248
Short name T787
Test name
Test status
Simulation time 70025158 ps
CPU time 3.53 seconds
Started Jul 07 06:58:55 PM PDT 24
Finished Jul 07 06:58:58 PM PDT 24
Peak memory 222160 kb
Host smart-20256112-936b-4e73-9baf-eef07596071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901398248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2901398248
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1167432367
Short name T368
Test name
Test status
Simulation time 19252831408 ps
CPU time 160.4 seconds
Started Jul 07 06:58:58 PM PDT 24
Finished Jul 07 07:01:38 PM PDT 24
Peak memory 229492 kb
Host smart-4ad21c0a-75bf-43c4-aa8b-86bcb16f3759
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167432367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1167432367
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.4102827547
Short name T154
Test name
Test status
Simulation time 187514734532 ps
CPU time 814.28 seconds
Started Jul 07 06:58:57 PM PDT 24
Finished Jul 07 07:12:32 PM PDT 24
Peak memory 448044 kb
Host smart-56c5328e-9728-49b1-a8cd-1a13750d5e2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4102827547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.4102827547
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.879524212
Short name T359
Test name
Test status
Simulation time 19036533 ps
CPU time 0.92 seconds
Started Jul 07 06:58:54 PM PDT 24
Finished Jul 07 06:58:55 PM PDT 24
Peak memory 211876 kb
Host smart-8a8e9124-e731-4a4a-bf69-5ee2fcb4a2ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879524212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.879524212
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1643888113
Short name T725
Test name
Test status
Simulation time 17411774 ps
CPU time 0.87 seconds
Started Jul 07 06:59:02 PM PDT 24
Finished Jul 07 06:59:03 PM PDT 24
Peak memory 208988 kb
Host smart-f1be2b0f-0faf-4c59-a701-fa5ffb620063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643888113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1643888113
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3364271457
Short name T733
Test name
Test status
Simulation time 607103589 ps
CPU time 11.03 seconds
Started Jul 07 06:59:01 PM PDT 24
Finished Jul 07 06:59:13 PM PDT 24
Peak memory 218280 kb
Host smart-e960e470-e448-49b2-ac1d-af227cf9a669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364271457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3364271457
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1514019490
Short name T583
Test name
Test status
Simulation time 535940541 ps
CPU time 3.3 seconds
Started Jul 07 06:59:02 PM PDT 24
Finished Jul 07 06:59:06 PM PDT 24
Peak memory 217220 kb
Host smart-c3b47424-48c0-4916-8ba8-cfd7e03e11cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514019490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1514019490
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2935197807
Short name T507
Test name
Test status
Simulation time 21737610 ps
CPU time 1.86 seconds
Started Jul 07 06:58:59 PM PDT 24
Finished Jul 07 06:59:01 PM PDT 24
Peak memory 218224 kb
Host smart-8864310c-4271-4b8f-a617-8931093bb2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935197807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2935197807
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2316020253
Short name T757
Test name
Test status
Simulation time 2046727144 ps
CPU time 10.61 seconds
Started Jul 07 06:59:02 PM PDT 24
Finished Jul 07 06:59:13 PM PDT 24
Peak memory 226036 kb
Host smart-83c1fbf9-ca01-461e-84df-7422adcdf175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316020253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2316020253
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2087249789
Short name T767
Test name
Test status
Simulation time 618399187 ps
CPU time 11.12 seconds
Started Jul 07 06:59:02 PM PDT 24
Finished Jul 07 06:59:14 PM PDT 24
Peak memory 226028 kb
Host smart-80439960-822b-47a5-9739-e26ba6010365
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087249789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2087249789
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1565524847
Short name T763
Test name
Test status
Simulation time 1506624832 ps
CPU time 9.12 seconds
Started Jul 07 06:59:03 PM PDT 24
Finished Jul 07 06:59:12 PM PDT 24
Peak memory 218324 kb
Host smart-d318de45-4bf9-498c-be0b-8625852290c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565524847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1565524847
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1942009128
Short name T72
Test name
Test status
Simulation time 84893013 ps
CPU time 1.95 seconds
Started Jul 07 06:58:59 PM PDT 24
Finished Jul 07 06:59:01 PM PDT 24
Peak memory 214428 kb
Host smart-ab9f807e-ee08-4c58-85cf-1e551a3c566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942009128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1942009128
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.810312450
Short name T442
Test name
Test status
Simulation time 319792253 ps
CPU time 31.56 seconds
Started Jul 07 06:58:57 PM PDT 24
Finished Jul 07 06:59:29 PM PDT 24
Peak memory 245136 kb
Host smart-65ef5a07-8907-4427-b888-60414489b696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810312450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.810312450
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3409283830
Short name T111
Test name
Test status
Simulation time 1508562118 ps
CPU time 4.41 seconds
Started Jul 07 06:58:58 PM PDT 24
Finished Jul 07 06:59:03 PM PDT 24
Peak memory 222840 kb
Host smart-dae2f107-2bb2-48fc-bf91-c007bf604651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409283830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3409283830
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2038630799
Short name T749
Test name
Test status
Simulation time 13121543136 ps
CPU time 137.47 seconds
Started Jul 07 06:59:06 PM PDT 24
Finished Jul 07 07:01:24 PM PDT 24
Peak memory 283808 kb
Host smart-d7d3831c-dcc1-4b10-93a9-7a9bd3a352d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038630799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2038630799
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2648758366
Short name T335
Test name
Test status
Simulation time 25338684 ps
CPU time 0.89 seconds
Started Jul 07 06:58:59 PM PDT 24
Finished Jul 07 06:59:00 PM PDT 24
Peak memory 211820 kb
Host smart-5ea90bc7-36db-4ef0-bae2-97a28769a6ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648758366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2648758366
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3971255517
Short name T689
Test name
Test status
Simulation time 27670370 ps
CPU time 0.93 seconds
Started Jul 07 06:54:20 PM PDT 24
Finished Jul 07 06:54:22 PM PDT 24
Peak memory 208992 kb
Host smart-5a20dda3-74e6-46e8-9a13-b645bef1bd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971255517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3971255517
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.506883095
Short name T852
Test name
Test status
Simulation time 33955731 ps
CPU time 0.79 seconds
Started Jul 07 06:54:09 PM PDT 24
Finished Jul 07 06:54:10 PM PDT 24
Peak memory 209016 kb
Host smart-be2fe9d0-91b3-46ee-a326-3eb6cd47a287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506883095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.506883095
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2978646832
Short name T550
Test name
Test status
Simulation time 2234391075 ps
CPU time 23.59 seconds
Started Jul 07 06:54:11 PM PDT 24
Finished Jul 07 06:54:35 PM PDT 24
Peak memory 218292 kb
Host smart-12dd8e82-43ad-416f-80df-d14ca80b9ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978646832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2978646832
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3020743743
Short name T621
Test name
Test status
Simulation time 460257806 ps
CPU time 10.78 seconds
Started Jul 07 06:54:13 PM PDT 24
Finished Jul 07 06:54:24 PM PDT 24
Peak memory 217372 kb
Host smart-c348670e-1ad8-4039-b6fe-2f38e11e12dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020743743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3020743743
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.510363709
Short name T28
Test name
Test status
Simulation time 12087616289 ps
CPU time 66.42 seconds
Started Jul 07 06:54:14 PM PDT 24
Finished Jul 07 06:55:21 PM PDT 24
Peak memory 219136 kb
Host smart-351361e9-f570-4ced-b756-529a48947195
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510363709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.510363709
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3643894658
Short name T6
Test name
Test status
Simulation time 824370860 ps
CPU time 2.47 seconds
Started Jul 07 06:54:16 PM PDT 24
Finished Jul 07 06:54:19 PM PDT 24
Peak memory 217756 kb
Host smart-3476daff-09a2-401f-8ef7-74b6670e6402
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643894658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
643894658
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.4133676252
Short name T234
Test name
Test status
Simulation time 3662565117 ps
CPU time 26.72 seconds
Started Jul 07 06:54:15 PM PDT 24
Finished Jul 07 06:54:41 PM PDT 24
Peak memory 218248 kb
Host smart-148783ac-2182-4792-bdbe-c7398ddba260
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133676252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.4133676252
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3111071518
Short name T855
Test name
Test status
Simulation time 2453348374 ps
CPU time 16.89 seconds
Started Jul 07 06:54:18 PM PDT 24
Finished Jul 07 06:54:35 PM PDT 24
Peak memory 217776 kb
Host smart-e5eddf93-8c7f-4354-8035-c16b984bb6f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111071518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3111071518
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3138179123
Short name T441
Test name
Test status
Simulation time 3723453183 ps
CPU time 11.49 seconds
Started Jul 07 06:54:09 PM PDT 24
Finished Jul 07 06:54:20 PM PDT 24
Peak memory 217736 kb
Host smart-4192da27-9d7c-4cea-8bd1-2ca99f63d256
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138179123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3138179123
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.487815332
Short name T499
Test name
Test status
Simulation time 8121719154 ps
CPU time 75.67 seconds
Started Jul 07 06:54:10 PM PDT 24
Finished Jul 07 06:55:26 PM PDT 24
Peak memory 276068 kb
Host smart-06277718-7c22-42fd-8b08-1e893999a0c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487815332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.487815332
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3462673628
Short name T226
Test name
Test status
Simulation time 1298995640 ps
CPU time 10.15 seconds
Started Jul 07 06:54:09 PM PDT 24
Finished Jul 07 06:54:20 PM PDT 24
Peak memory 226340 kb
Host smart-fbd08447-ee89-4153-b212-ed2048f98c3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462673628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3462673628
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2417565704
Short name T572
Test name
Test status
Simulation time 75212716 ps
CPU time 1.85 seconds
Started Jul 07 06:54:12 PM PDT 24
Finished Jul 07 06:54:14 PM PDT 24
Peak memory 222000 kb
Host smart-75cb882a-5f59-4225-b357-1b73f8473863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417565704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2417565704
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1496982679
Short name T101
Test name
Test status
Simulation time 382782363 ps
CPU time 22.39 seconds
Started Jul 07 06:54:09 PM PDT 24
Finished Jul 07 06:54:32 PM PDT 24
Peak memory 214876 kb
Host smart-ff731b23-5e39-4161-bfca-2ddfbd6dfe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496982679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1496982679
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1185954683
Short name T627
Test name
Test status
Simulation time 1095866682 ps
CPU time 14.12 seconds
Started Jul 07 06:54:23 PM PDT 24
Finished Jul 07 06:54:37 PM PDT 24
Peak memory 226160 kb
Host smart-69f1b39b-ad9b-407a-8d10-71bd1ae3b3c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185954683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1185954683
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1490027630
Short name T309
Test name
Test status
Simulation time 1483642429 ps
CPU time 13 seconds
Started Jul 07 06:54:21 PM PDT 24
Finished Jul 07 06:54:34 PM PDT 24
Peak memory 226028 kb
Host smart-1ceef21e-28e3-403c-b4c7-43e0600042b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490027630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1490027630
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1862952600
Short name T404
Test name
Test status
Simulation time 748746951 ps
CPU time 10.68 seconds
Started Jul 07 06:54:22 PM PDT 24
Finished Jul 07 06:54:33 PM PDT 24
Peak memory 226004 kb
Host smart-0a64da2b-1b6f-4ec9-96ab-e2fb1d7b6011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862952600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
862952600
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1806078310
Short name T664
Test name
Test status
Simulation time 1035411929 ps
CPU time 8.86 seconds
Started Jul 07 06:54:12 PM PDT 24
Finished Jul 07 06:54:21 PM PDT 24
Peak memory 225688 kb
Host smart-d2507c10-db2d-45d1-b389-f28b2c99a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806078310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1806078310
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1708745910
Short name T720
Test name
Test status
Simulation time 114812005 ps
CPU time 2.82 seconds
Started Jul 07 06:54:08 PM PDT 24
Finished Jul 07 06:54:11 PM PDT 24
Peak memory 214848 kb
Host smart-3c42684d-f844-42cf-9abe-87d042aca5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708745910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1708745910
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3865401879
Short name T846
Test name
Test status
Simulation time 589406617 ps
CPU time 25.56 seconds
Started Jul 07 06:54:08 PM PDT 24
Finished Jul 07 06:54:34 PM PDT 24
Peak memory 250976 kb
Host smart-5c33c524-b5fa-43e5-8f8a-370b73b283ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865401879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3865401879
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3793362059
Short name T668
Test name
Test status
Simulation time 254680710 ps
CPU time 6.61 seconds
Started Jul 07 06:54:06 PM PDT 24
Finished Jul 07 06:54:13 PM PDT 24
Peak memory 250716 kb
Host smart-cbf7c62f-47ad-4d79-9b25-8acf5cbbffa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793362059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3793362059
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2535604987
Short name T344
Test name
Test status
Simulation time 13048920779 ps
CPU time 214.11 seconds
Started Jul 07 06:54:20 PM PDT 24
Finished Jul 07 06:57:55 PM PDT 24
Peak memory 293392 kb
Host smart-6194e960-5faa-4aec-a32d-fd85494cb3ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535604987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2535604987
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2943691740
Short name T558
Test name
Test status
Simulation time 40650951 ps
CPU time 0.96 seconds
Started Jul 07 06:54:06 PM PDT 24
Finished Jul 07 06:54:08 PM PDT 24
Peak memory 211900 kb
Host smart-9aa4aa41-cc0a-420e-ad0a-3fe2ff19bcb6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943691740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2943691740
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.4102035746
Short name T308
Test name
Test status
Simulation time 43216997 ps
CPU time 1 seconds
Started Jul 07 06:54:36 PM PDT 24
Finished Jul 07 06:54:38 PM PDT 24
Peak memory 209040 kb
Host smart-adcc641a-0693-400e-b7b6-bfdb41236274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102035746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4102035746
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.394404679
Short name T217
Test name
Test status
Simulation time 11873109 ps
CPU time 0.83 seconds
Started Jul 07 06:54:31 PM PDT 24
Finished Jul 07 06:54:32 PM PDT 24
Peak memory 208712 kb
Host smart-fcb03a9c-9b59-474f-9966-9b12001ff73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394404679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.394404679
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1493752169
Short name T17
Test name
Test status
Simulation time 292350133 ps
CPU time 15.48 seconds
Started Jul 07 06:54:25 PM PDT 24
Finished Jul 07 06:54:42 PM PDT 24
Peak memory 218160 kb
Host smart-22ba602c-305d-41d9-92c4-aa86b2ce7ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493752169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1493752169
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3365031236
Short name T517
Test name
Test status
Simulation time 186684472 ps
CPU time 5.71 seconds
Started Jul 07 06:54:31 PM PDT 24
Finished Jul 07 06:54:37 PM PDT 24
Peak memory 217356 kb
Host smart-7bfe4e92-ead8-4a56-b534-84846a016b74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365031236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3365031236
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2839486936
Short name T327
Test name
Test status
Simulation time 3471468189 ps
CPU time 30.13 seconds
Started Jul 07 06:54:27 PM PDT 24
Finished Jul 07 06:54:58 PM PDT 24
Peak memory 218288 kb
Host smart-61fdc905-2c08-490f-9d69-6216d0fcc470
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839486936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2839486936
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2632946747
Short name T672
Test name
Test status
Simulation time 682873981 ps
CPU time 4.62 seconds
Started Jul 07 06:54:32 PM PDT 24
Finished Jul 07 06:54:37 PM PDT 24
Peak memory 217740 kb
Host smart-c72f52b4-e96b-4e90-8838-16325598084a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632946747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
632946747
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.413905126
Short name T293
Test name
Test status
Simulation time 595173702 ps
CPU time 15.94 seconds
Started Jul 07 06:54:30 PM PDT 24
Finished Jul 07 06:54:46 PM PDT 24
Peak memory 218196 kb
Host smart-f2f33228-ff34-4c1f-8fd6-7cc2de50f728
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413905126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.413905126
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4173641017
Short name T295
Test name
Test status
Simulation time 3671821981 ps
CPU time 12.77 seconds
Started Jul 07 06:54:32 PM PDT 24
Finished Jul 07 06:54:45 PM PDT 24
Peak memory 217724 kb
Host smart-a51570ca-d580-454c-98c3-7260a022f590
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173641017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.4173641017
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1558577916
Short name T286
Test name
Test status
Simulation time 119993958 ps
CPU time 2.8 seconds
Started Jul 07 06:54:28 PM PDT 24
Finished Jul 07 06:54:31 PM PDT 24
Peak memory 217712 kb
Host smart-5d1ae8a3-4e43-47ad-b413-86e6835b565b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558577916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1558577916
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2334500464
Short name T480
Test name
Test status
Simulation time 6974276256 ps
CPU time 72.42 seconds
Started Jul 07 06:54:26 PM PDT 24
Finished Jul 07 06:55:39 PM PDT 24
Peak memory 283908 kb
Host smart-8bfba9f4-fe33-4e29-bb98-948dd8eeca32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334500464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2334500464
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2856393188
Short name T508
Test name
Test status
Simulation time 2007995048 ps
CPU time 19.64 seconds
Started Jul 07 06:54:31 PM PDT 24
Finished Jul 07 06:54:51 PM PDT 24
Peak memory 250360 kb
Host smart-1f561f1f-edaf-4a56-846b-658e2475a41d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856393188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2856393188
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.942858695
Short name T451
Test name
Test status
Simulation time 297767309 ps
CPU time 3.01 seconds
Started Jul 07 06:54:23 PM PDT 24
Finished Jul 07 06:54:27 PM PDT 24
Peak memory 222708 kb
Host smart-dd690c72-cb25-41e5-8ff7-a0123e0c95ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942858695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.942858695
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1675911445
Short name T606
Test name
Test status
Simulation time 539186436 ps
CPU time 18.72 seconds
Started Jul 07 06:54:25 PM PDT 24
Finished Jul 07 06:54:45 PM PDT 24
Peak memory 214672 kb
Host smart-2643eb77-3532-4449-bdb4-4eee44f351b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675911445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1675911445
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1292550191
Short name T105
Test name
Test status
Simulation time 1222450294 ps
CPU time 9.63 seconds
Started Jul 07 06:54:31 PM PDT 24
Finished Jul 07 06:54:41 PM PDT 24
Peak memory 226032 kb
Host smart-7eddc8f4-2b54-4f80-bb8a-7eccad856d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292550191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1292550191
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.190614121
Short name T364
Test name
Test status
Simulation time 1455628451 ps
CPU time 10.79 seconds
Started Jul 07 06:54:32 PM PDT 24
Finished Jul 07 06:54:43 PM PDT 24
Peak memory 226028 kb
Host smart-0f01bbff-a6cd-4a5e-9e57-122db934ac83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190614121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.190614121
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2371772028
Short name T58
Test name
Test status
Simulation time 6159691190 ps
CPU time 13.26 seconds
Started Jul 07 06:54:31 PM PDT 24
Finished Jul 07 06:54:44 PM PDT 24
Peak memory 226128 kb
Host smart-44ff354a-e754-462e-83a9-63a75d0c8371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371772028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
371772028
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1999014134
Short name T824
Test name
Test status
Simulation time 167467231 ps
CPU time 7.99 seconds
Started Jul 07 06:54:25 PM PDT 24
Finished Jul 07 06:54:34 PM PDT 24
Peak memory 225980 kb
Host smart-839321f3-e546-4288-9285-8079cd71f563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999014134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1999014134
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2668517071
Short name T263
Test name
Test status
Simulation time 16703008 ps
CPU time 1.1 seconds
Started Jul 07 06:54:23 PM PDT 24
Finished Jul 07 06:54:24 PM PDT 24
Peak memory 217592 kb
Host smart-d38fad28-6cf2-4c1f-92ac-4f9de8aa6fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668517071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2668517071
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3127820430
Short name T665
Test name
Test status
Simulation time 314758806 ps
CPU time 30.09 seconds
Started Jul 07 06:54:25 PM PDT 24
Finished Jul 07 06:54:56 PM PDT 24
Peak memory 250980 kb
Host smart-e546e37a-50eb-4032-85d1-39723735d9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127820430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3127820430
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2726950089
Short name T439
Test name
Test status
Simulation time 127597414 ps
CPU time 6.89 seconds
Started Jul 07 06:54:24 PM PDT 24
Finished Jul 07 06:54:31 PM PDT 24
Peak memory 247120 kb
Host smart-83ff5b24-824f-400d-9f8c-99b0b0235caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726950089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2726950089
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2226762148
Short name T702
Test name
Test status
Simulation time 3353526522 ps
CPU time 99.6 seconds
Started Jul 07 06:54:36 PM PDT 24
Finished Jul 07 06:56:16 PM PDT 24
Peak memory 283772 kb
Host smart-fe6e474f-705e-40c5-9cbd-bea2e5fe361a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226762148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2226762148
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2703681447
Short name T164
Test name
Test status
Simulation time 10333272914 ps
CPU time 382.01 seconds
Started Jul 07 06:54:35 PM PDT 24
Finished Jul 07 07:00:57 PM PDT 24
Peak memory 316984 kb
Host smart-e28e25ce-bae2-4f10-a71a-ac257ecee614
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2703681447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2703681447
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1595041525
Short name T22
Test name
Test status
Simulation time 12365372 ps
CPU time 1.03 seconds
Started Jul 07 06:54:24 PM PDT 24
Finished Jul 07 06:54:25 PM PDT 24
Peak memory 211876 kb
Host smart-6085f3cf-be46-4cca-99f0-49dbc6c49d15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595041525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1595041525
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1954746069
Short name T422
Test name
Test status
Simulation time 97613786 ps
CPU time 0.88 seconds
Started Jul 07 06:54:50 PM PDT 24
Finished Jul 07 06:54:52 PM PDT 24
Peak memory 208812 kb
Host smart-e89eb828-e1b0-4c69-a5d7-3a365d1db7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954746069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1954746069
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3623848400
Short name T437
Test name
Test status
Simulation time 35317593 ps
CPU time 0.89 seconds
Started Jul 07 06:54:42 PM PDT 24
Finished Jul 07 06:54:43 PM PDT 24
Peak memory 208820 kb
Host smart-ad3fe7ff-2b01-4f16-bfed-a1a73d782943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623848400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3623848400
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.373147889
Short name T751
Test name
Test status
Simulation time 727673640 ps
CPU time 14.4 seconds
Started Jul 07 06:54:40 PM PDT 24
Finished Jul 07 06:54:55 PM PDT 24
Peak memory 225980 kb
Host smart-a7de7853-6464-4688-9c1f-1bb3febb7d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373147889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.373147889
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.872845181
Short name T9
Test name
Test status
Simulation time 126971535 ps
CPU time 1.48 seconds
Started Jul 07 06:54:46 PM PDT 24
Finished Jul 07 06:54:47 PM PDT 24
Peak memory 217060 kb
Host smart-36d56c6a-63e9-48ff-a147-60276a2b6896
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872845181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.872845181
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3901579184
Short name T789
Test name
Test status
Simulation time 3389119026 ps
CPU time 51.06 seconds
Started Jul 07 06:54:47 PM PDT 24
Finished Jul 07 06:55:38 PM PDT 24
Peak memory 218304 kb
Host smart-aa8113f6-ad80-425b-879f-ca0cc5005459
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901579184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3901579184
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1536720595
Short name T159
Test name
Test status
Simulation time 796785153 ps
CPU time 9.6 seconds
Started Jul 07 06:54:48 PM PDT 24
Finished Jul 07 06:54:58 PM PDT 24
Peak memory 217904 kb
Host smart-d84ab71c-1d4f-4f34-9782-c745df2d1839
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536720595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
536720595
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4008840285
Short name T815
Test name
Test status
Simulation time 878582511 ps
CPU time 6.97 seconds
Started Jul 07 06:54:44 PM PDT 24
Finished Jul 07 06:54:51 PM PDT 24
Peak memory 218236 kb
Host smart-d0012bb9-2f84-46f7-a492-30b001e06ba9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008840285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.4008840285
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3210857695
Short name T589
Test name
Test status
Simulation time 3809998383 ps
CPU time 28.29 seconds
Started Jul 07 06:54:48 PM PDT 24
Finished Jul 07 06:55:16 PM PDT 24
Peak memory 218048 kb
Host smart-f95fffb0-7a81-43b7-83c2-3da1040e3891
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210857695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3210857695
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2499988137
Short name T10
Test name
Test status
Simulation time 886875564 ps
CPU time 6.62 seconds
Started Jul 07 06:54:40 PM PDT 24
Finished Jul 07 06:54:47 PM PDT 24
Peak memory 217720 kb
Host smart-00f79731-7c20-41b7-a395-57015a736179
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499988137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2499988137
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3042779348
Short name T342
Test name
Test status
Simulation time 2334876706 ps
CPU time 56.66 seconds
Started Jul 07 06:54:41 PM PDT 24
Finished Jul 07 06:55:38 PM PDT 24
Peak memory 267944 kb
Host smart-f62513d3-0ebe-4b4b-ba3e-59c43ca48b15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042779348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3042779348
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2661238050
Short name T528
Test name
Test status
Simulation time 905273484 ps
CPU time 20.44 seconds
Started Jul 07 06:54:45 PM PDT 24
Finished Jul 07 06:55:05 PM PDT 24
Peak memory 250984 kb
Host smart-d72bc65a-d69b-491c-ab9c-5a1bff9e5732
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661238050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2661238050
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1935434177
Short name T496
Test name
Test status
Simulation time 92211004 ps
CPU time 4.09 seconds
Started Jul 07 06:54:42 PM PDT 24
Finished Jul 07 06:54:47 PM PDT 24
Peak memory 218220 kb
Host smart-ae1b647c-92f1-406b-9ab5-6192e1c1d75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935434177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1935434177
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3483350406
Short name T705
Test name
Test status
Simulation time 1597665951 ps
CPU time 7.18 seconds
Started Jul 07 06:54:42 PM PDT 24
Finished Jul 07 06:54:49 PM PDT 24
Peak memory 213964 kb
Host smart-648fafab-8d3a-494c-9265-f966f6e8c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483350406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3483350406
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2609916671
Short name T313
Test name
Test status
Simulation time 1925160666 ps
CPU time 11.22 seconds
Started Jul 07 06:54:44 PM PDT 24
Finished Jul 07 06:54:56 PM PDT 24
Peak memory 226036 kb
Host smart-fff8ec2d-e103-4b25-a09e-a9c6d8bf23ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609916671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
609916671
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.506708734
Short name T55
Test name
Test status
Simulation time 575347904 ps
CPU time 10.79 seconds
Started Jul 07 06:54:43 PM PDT 24
Finished Jul 07 06:54:54 PM PDT 24
Peak memory 226004 kb
Host smart-294948f0-3ccc-4fd9-b2d9-2bf34542d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506708734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.506708734
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2674827788
Short name T497
Test name
Test status
Simulation time 92289793 ps
CPU time 1.5 seconds
Started Jul 07 06:54:34 PM PDT 24
Finished Jul 07 06:54:35 PM PDT 24
Peak memory 217780 kb
Host smart-78dadb69-141a-41df-b449-bc605b55cf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674827788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2674827788
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2067930429
Short name T255
Test name
Test status
Simulation time 186241784 ps
CPU time 22.09 seconds
Started Jul 07 06:54:41 PM PDT 24
Finished Jul 07 06:55:04 PM PDT 24
Peak memory 250956 kb
Host smart-00e62ff8-5225-4723-ba40-129a55e16085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067930429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2067930429
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3211619158
Short name T842
Test name
Test status
Simulation time 220523009 ps
CPU time 6.98 seconds
Started Jul 07 06:54:41 PM PDT 24
Finished Jul 07 06:54:48 PM PDT 24
Peak memory 250520 kb
Host smart-e1772e1b-ffd1-4955-b64c-2b5c95dcf6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211619158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3211619158
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3672208977
Short name T698
Test name
Test status
Simulation time 1263351437 ps
CPU time 37.15 seconds
Started Jul 07 06:54:51 PM PDT 24
Finished Jul 07 06:55:28 PM PDT 24
Peak memory 248180 kb
Host smart-b2dc86de-fc32-4eda-a089-c11e0ae3bc72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672208977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3672208977
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2099432310
Short name T600
Test name
Test status
Simulation time 166070997 ps
CPU time 0.88 seconds
Started Jul 07 06:54:35 PM PDT 24
Finished Jul 07 06:54:36 PM PDT 24
Peak memory 211888 kb
Host smart-04cc32cf-5b11-47e5-bc0f-e9b4a30b3478
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099432310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2099432310
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3174129549
Short name T759
Test name
Test status
Simulation time 49119731 ps
CPU time 1.49 seconds
Started Jul 07 06:55:02 PM PDT 24
Finished Jul 07 06:55:04 PM PDT 24
Peak memory 208944 kb
Host smart-462919de-13a7-4cfc-a76f-c8578933316f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174129549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3174129549
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3788204135
Short name T666
Test name
Test status
Simulation time 308227436 ps
CPU time 11.43 seconds
Started Jul 07 06:54:54 PM PDT 24
Finished Jul 07 06:55:05 PM PDT 24
Peak memory 218248 kb
Host smart-5245b36a-4da2-4150-ac54-3e7e59bdb7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788204135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3788204135
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2884431096
Short name T345
Test name
Test status
Simulation time 421525305 ps
CPU time 3.57 seconds
Started Jul 07 06:54:58 PM PDT 24
Finished Jul 07 06:55:02 PM PDT 24
Peak memory 217184 kb
Host smart-5b11c5ac-4f2b-4648-bc76-cb92e5abced3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884431096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2884431096
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1516041022
Short name T593
Test name
Test status
Simulation time 19744341232 ps
CPU time 36.52 seconds
Started Jul 07 06:54:59 PM PDT 24
Finished Jul 07 06:55:36 PM PDT 24
Peak memory 218940 kb
Host smart-fafec2b4-aad9-4d5c-b10f-a7402fe00b1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516041022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1516041022
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1357928119
Short name T64
Test name
Test status
Simulation time 452869640 ps
CPU time 10.51 seconds
Started Jul 07 06:55:00 PM PDT 24
Finished Jul 07 06:55:10 PM PDT 24
Peak memory 217584 kb
Host smart-e1cd3438-4ab2-4e1d-9fb6-d2dffdec8083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357928119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
357928119
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2925714606
Short name T102
Test name
Test status
Simulation time 3590049586 ps
CPU time 5.2 seconds
Started Jul 07 06:54:59 PM PDT 24
Finished Jul 07 06:55:05 PM PDT 24
Peak memory 223484 kb
Host smart-fae9bcf2-cd0e-4483-bc4f-306759c24652
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925714606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2925714606
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.87827605
Short name T238
Test name
Test status
Simulation time 4273344087 ps
CPU time 30.64 seconds
Started Jul 07 06:55:05 PM PDT 24
Finished Jul 07 06:55:36 PM PDT 24
Peak memory 217776 kb
Host smart-3879f982-20ef-46f5-be97-412a1743b9cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87827605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt
ag_regwen_during_op.87827605
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.309833817
Short name T424
Test name
Test status
Simulation time 133260529 ps
CPU time 4.72 seconds
Started Jul 07 06:54:55 PM PDT 24
Finished Jul 07 06:55:00 PM PDT 24
Peak memory 217708 kb
Host smart-df48dcc3-0583-4f07-a948-4b811c5f9604
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309833817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.309833817
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.4136775523
Short name T340
Test name
Test status
Simulation time 5440691132 ps
CPU time 95.07 seconds
Started Jul 07 06:54:55 PM PDT 24
Finished Jul 07 06:56:31 PM PDT 24
Peak memory 275884 kb
Host smart-afe43e55-6928-42af-87af-7ed81fb9962f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136775523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.4136775523
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3479358653
Short name T369
Test name
Test status
Simulation time 1184637266 ps
CPU time 6.27 seconds
Started Jul 07 06:54:54 PM PDT 24
Finished Jul 07 06:55:00 PM PDT 24
Peak memory 220776 kb
Host smart-f2aecf99-6867-4eb5-bd84-21d25fd1493e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479358653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3479358653
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3567544798
Short name T296
Test name
Test status
Simulation time 290453354 ps
CPU time 1.97 seconds
Started Jul 07 06:54:52 PM PDT 24
Finished Jul 07 06:54:54 PM PDT 24
Peak memory 218200 kb
Host smart-fb2a3a97-c69e-4b52-a4c5-eddda15dd38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567544798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3567544798
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2570365725
Short name T745
Test name
Test status
Simulation time 536953582 ps
CPU time 17.82 seconds
Started Jul 07 06:54:55 PM PDT 24
Finished Jul 07 06:55:13 PM PDT 24
Peak memory 214688 kb
Host smart-a16e345d-a473-4448-9b27-54aa435ef674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570365725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2570365725
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3373590356
Short name T482
Test name
Test status
Simulation time 277300791 ps
CPU time 9.61 seconds
Started Jul 07 06:55:03 PM PDT 24
Finished Jul 07 06:55:12 PM PDT 24
Peak memory 225936 kb
Host smart-5528c498-f224-4bde-ae93-adc51d7fbf34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373590356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3373590356
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.401882674
Short name T328
Test name
Test status
Simulation time 1260747071 ps
CPU time 15.87 seconds
Started Jul 07 06:55:02 PM PDT 24
Finished Jul 07 06:55:18 PM PDT 24
Peak memory 226000 kb
Host smart-5151ec10-41a8-4e9c-bd4c-bbd4d9c323fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401882674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.401882674
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1569247418
Short name T346
Test name
Test status
Simulation time 519192752 ps
CPU time 9.5 seconds
Started Jul 07 06:55:03 PM PDT 24
Finished Jul 07 06:55:13 PM PDT 24
Peak memory 218196 kb
Host smart-7f4c9ad4-6c49-4e27-b359-5b401c216eb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569247418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
569247418
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1021908097
Short name T170
Test name
Test status
Simulation time 2479779286 ps
CPU time 11.26 seconds
Started Jul 07 06:54:53 PM PDT 24
Finished Jul 07 06:55:04 PM PDT 24
Peak memory 226120 kb
Host smart-fec4bd01-1bea-4220-bb77-2c27746f27ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021908097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1021908097
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2602218663
Short name T89
Test name
Test status
Simulation time 83858628 ps
CPU time 2.96 seconds
Started Jul 07 06:54:50 PM PDT 24
Finished Jul 07 06:54:53 PM PDT 24
Peak memory 214796 kb
Host smart-9256d422-4b66-4690-b1c0-5ebd089d2208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602218663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2602218663
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.130221290
Short name T799
Test name
Test status
Simulation time 234071586 ps
CPU time 23.95 seconds
Started Jul 07 06:54:50 PM PDT 24
Finished Jul 07 06:55:14 PM PDT 24
Peak memory 251116 kb
Host smart-e454799d-a0a7-4b91-8380-8e9183241e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130221290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.130221290
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3399824065
Short name T829
Test name
Test status
Simulation time 81922026 ps
CPU time 6.88 seconds
Started Jul 07 06:54:55 PM PDT 24
Finished Jul 07 06:55:02 PM PDT 24
Peak memory 244496 kb
Host smart-2c284c7d-2eb4-4b2e-8c4a-5c667accdb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399824065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3399824065
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2042388927
Short name T334
Test name
Test status
Simulation time 1492020723 ps
CPU time 43.04 seconds
Started Jul 07 06:55:03 PM PDT 24
Finished Jul 07 06:55:46 PM PDT 24
Peak memory 267360 kb
Host smart-39a41836-c6fa-4e4d-9c3c-3c070122db12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042388927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2042388927
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.159315899
Short name T773
Test name
Test status
Simulation time 43156256 ps
CPU time 1.02 seconds
Started Jul 07 06:54:51 PM PDT 24
Finished Jul 07 06:54:52 PM PDT 24
Peak memory 211936 kb
Host smart-c35a0171-fcd4-4a85-902e-5e21f3a64255
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159315899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.159315899
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1119547276
Short name T397
Test name
Test status
Simulation time 44969099 ps
CPU time 1 seconds
Started Jul 07 06:55:10 PM PDT 24
Finished Jul 07 06:55:11 PM PDT 24
Peak memory 208920 kb
Host smart-2f79ed35-cbd1-4ee4-91ce-f061b058b847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119547276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1119547276
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3654965246
Short name T317
Test name
Test status
Simulation time 18672031 ps
CPU time 0.82 seconds
Started Jul 07 06:55:17 PM PDT 24
Finished Jul 07 06:55:18 PM PDT 24
Peak memory 208796 kb
Host smart-862172ac-9cb3-4d8a-9efe-5c586fbd4be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654965246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3654965246
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1646574145
Short name T465
Test name
Test status
Simulation time 372911122 ps
CPU time 12.44 seconds
Started Jul 07 06:55:08 PM PDT 24
Finished Jul 07 06:55:21 PM PDT 24
Peak memory 218212 kb
Host smart-a75bf8ae-3a7d-410e-8315-8b3960d4d853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646574145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1646574145
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.506060186
Short name T538
Test name
Test status
Simulation time 171539730 ps
CPU time 5.06 seconds
Started Jul 07 06:55:10 PM PDT 24
Finished Jul 07 06:55:15 PM PDT 24
Peak memory 217180 kb
Host smart-d4a9a985-2661-42e0-950b-8482eb4aa3dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506060186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.506060186
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2513963090
Short name T325
Test name
Test status
Simulation time 3237008042 ps
CPU time 87.25 seconds
Started Jul 07 06:55:17 PM PDT 24
Finished Jul 07 06:56:44 PM PDT 24
Peak memory 226088 kb
Host smart-6397bc81-c541-4dab-af8d-6078facead65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513963090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2513963090
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3605414976
Short name T254
Test name
Test status
Simulation time 452305368 ps
CPU time 3.78 seconds
Started Jul 07 06:55:10 PM PDT 24
Finished Jul 07 06:55:14 PM PDT 24
Peak memory 218040 kb
Host smart-62893bab-ff4f-41d3-9cea-5546cfcf51d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605414976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
605414976
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2405355967
Short name T721
Test name
Test status
Simulation time 756108140 ps
CPU time 10.88 seconds
Started Jul 07 06:55:16 PM PDT 24
Finished Jul 07 06:55:28 PM PDT 24
Peak memory 218220 kb
Host smart-d764752c-2843-4cb5-906c-d15f42a88128
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405355967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2405355967
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3099340230
Short name T156
Test name
Test status
Simulation time 2808545999 ps
CPU time 20.76 seconds
Started Jul 07 06:55:09 PM PDT 24
Finished Jul 07 06:55:30 PM PDT 24
Peak memory 217764 kb
Host smart-9716a213-1d0b-4b79-a09a-b8e97b4d316c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099340230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3099340230
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1182359334
Short name T820
Test name
Test status
Simulation time 448861958 ps
CPU time 6.84 seconds
Started Jul 07 06:55:06 PM PDT 24
Finished Jul 07 06:55:13 PM PDT 24
Peak memory 217720 kb
Host smart-77f58dbd-a7e4-485c-a18f-0b590dd9dcc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182359334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1182359334
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3475270798
Short name T411
Test name
Test status
Simulation time 1776509332 ps
CPU time 48.63 seconds
Started Jul 07 06:55:08 PM PDT 24
Finished Jul 07 06:55:57 PM PDT 24
Peak memory 275540 kb
Host smart-23272464-fe47-4451-8fa7-13acf30e7ce7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475270798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3475270798
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1426527405
Short name T225
Test name
Test status
Simulation time 399400989 ps
CPU time 16.48 seconds
Started Jul 07 06:55:08 PM PDT 24
Finished Jul 07 06:55:25 PM PDT 24
Peak memory 246596 kb
Host smart-1a55194d-7628-469a-97db-d1b302439f8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426527405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1426527405
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3786711396
Short name T186
Test name
Test status
Simulation time 287375609 ps
CPU time 2.74 seconds
Started Jul 07 06:55:07 PM PDT 24
Finished Jul 07 06:55:09 PM PDT 24
Peak memory 218212 kb
Host smart-27ef0768-1722-49ed-9bd9-3fee7f5e9e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786711396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3786711396
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1688836326
Short name T71
Test name
Test status
Simulation time 676685201 ps
CPU time 5.12 seconds
Started Jul 07 06:55:06 PM PDT 24
Finished Jul 07 06:55:12 PM PDT 24
Peak memory 213888 kb
Host smart-a2bc96a2-261e-4669-b5b6-1938c60da905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688836326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1688836326
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1421320178
Short name T227
Test name
Test status
Simulation time 504234786 ps
CPU time 14.61 seconds
Started Jul 07 06:55:10 PM PDT 24
Finished Jul 07 06:55:25 PM PDT 24
Peak memory 226032 kb
Host smart-d1cc9114-3405-4035-b996-e299f85f1860
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421320178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1421320178
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.976924047
Short name T362
Test name
Test status
Simulation time 207171259 ps
CPU time 10.12 seconds
Started Jul 07 06:55:09 PM PDT 24
Finished Jul 07 06:55:19 PM PDT 24
Peak memory 226048 kb
Host smart-a307981e-f127-41c4-b48a-0bb474aeba24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976924047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.976924047
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1260675833
Short name T500
Test name
Test status
Simulation time 1935529771 ps
CPU time 8.4 seconds
Started Jul 07 06:55:17 PM PDT 24
Finished Jul 07 06:55:26 PM PDT 24
Peak memory 218240 kb
Host smart-3e499a03-1e00-437a-93e5-536aca75d739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260675833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
260675833
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4290358011
Short name T45
Test name
Test status
Simulation time 1657063037 ps
CPU time 10.04 seconds
Started Jul 07 06:55:07 PM PDT 24
Finished Jul 07 06:55:17 PM PDT 24
Peak memory 226008 kb
Host smart-9b059752-ca23-46ed-8678-2d6396ea0462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290358011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4290358011
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3487646983
Short name T379
Test name
Test status
Simulation time 181588894 ps
CPU time 2.88 seconds
Started Jul 07 06:55:02 PM PDT 24
Finished Jul 07 06:55:05 PM PDT 24
Peak memory 217692 kb
Host smart-fadaf523-3f5b-4f7a-a980-66fbb3322c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487646983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3487646983
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2773238787
Short name T685
Test name
Test status
Simulation time 4202271261 ps
CPU time 30.06 seconds
Started Jul 07 06:55:07 PM PDT 24
Finished Jul 07 06:55:37 PM PDT 24
Peak memory 251016 kb
Host smart-30c2dcfb-c89f-456a-a046-4bd97e6aa3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773238787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2773238787
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.384253686
Short name T783
Test name
Test status
Simulation time 322382960 ps
CPU time 6.43 seconds
Started Jul 07 06:55:17 PM PDT 24
Finished Jul 07 06:55:24 PM PDT 24
Peak memory 247132 kb
Host smart-927349c9-b199-44b7-8bd4-ead4aa5e9bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384253686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.384253686
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3934760098
Short name T694
Test name
Test status
Simulation time 2804829055 ps
CPU time 105.52 seconds
Started Jul 07 06:55:10 PM PDT 24
Finished Jul 07 06:56:56 PM PDT 24
Peak memory 279076 kb
Host smart-b2a6da25-fe5b-4082-963d-65b425be5dea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934760098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3934760098
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1366082560
Short name T524
Test name
Test status
Simulation time 31313635 ps
CPU time 0.93 seconds
Started Jul 07 06:55:05 PM PDT 24
Finished Jul 07 06:55:06 PM PDT 24
Peak memory 211880 kb
Host smart-c3a3cb50-ff33-45bf-80e4-ef71e0116896
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366082560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1366082560
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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