Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48735 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1701 |
1 |
|
|
T9 |
13 |
|
T11 |
5 |
|
T12 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49794 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
642 |
1 |
|
|
T62 |
10 |
|
T38 |
14 |
|
T63 |
23 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48630 |
1 |
|
|
T1 |
133 |
|
T2 |
11 |
|
T3 |
66 |
auto[1] |
1806 |
1 |
|
|
T1 |
4 |
|
T3 |
5 |
|
T9 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48704 |
1 |
|
|
T1 |
130 |
|
T2 |
11 |
|
T3 |
68 |
auto[1] |
1732 |
1 |
|
|
T1 |
7 |
|
T3 |
3 |
|
T9 |
3 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48665 |
1 |
|
|
T1 |
132 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1771 |
1 |
|
|
T1 |
5 |
|
T10 |
2 |
|
T12 |
19 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
45895 |
1 |
|
|
T1 |
109 |
|
T2 |
11 |
|
T3 |
48 |
no_err_inj |
4541 |
1 |
|
|
T1 |
28 |
|
T3 |
23 |
|
T9 |
33 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48726 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1710 |
1 |
|
|
T9 |
10 |
|
T11 |
9 |
|
T12 |
7 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49854 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
582 |
1 |
|
|
T62 |
10 |
|
T38 |
18 |
|
T63 |
12 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34787 |
1 |
|
|
T1 |
95 |
|
T3 |
58 |
|
T10 |
15 |
auto[1] |
15649 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48678 |
1 |
|
|
T1 |
131 |
|
T2 |
11 |
|
T3 |
70 |
auto[1] |
1758 |
1 |
|
|
T1 |
6 |
|
T3 |
1 |
|
T9 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48711 |
1 |
|
|
T1 |
134 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1725 |
1 |
|
|
T1 |
3 |
|
T10 |
3 |
|
T12 |
18 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48619 |
1 |
|
|
T1 |
126 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1817 |
1 |
|
|
T1 |
11 |
|
T10 |
1 |
|
T12 |
20 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48716 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1720 |
1 |
|
|
T9 |
12 |
|
T11 |
18 |
|
T12 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48284 |
1 |
|
|
T1 |
93 |
|
T3 |
38 |
|
T9 |
138 |
auto[1] |
2152 |
1 |
|
|
T1 |
44 |
|
T2 |
11 |
|
T3 |
33 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49822 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
614 |
1 |
|
|
T62 |
10 |
|
T38 |
20 |
|
T63 |
11 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49836 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
600 |
1 |
|
|
T62 |
13 |
|
T38 |
23 |
|
T63 |
22 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49819 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
617 |
1 |
|
|
T62 |
8 |
|
T38 |
19 |
|
T63 |
17 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47830 |
1 |
|
|
T1 |
114 |
|
T2 |
11 |
|
T3 |
33 |
auto[1] |
2606 |
1 |
|
|
T1 |
23 |
|
T3 |
38 |
|
T9 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46616 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
3820 |
1 |
|
|
T49 |
98 |
|
T50 |
80 |
|
T52 |
64 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48563 |
1 |
|
|
T1 |
126 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1873 |
1 |
|
|
T1 |
11 |
|
T12 |
27 |
|
T90 |
14 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48711 |
1 |
|
|
T1 |
131 |
|
T2 |
11 |
|
T3 |
68 |
auto[1] |
1725 |
1 |
|
|
T1 |
6 |
|
T3 |
3 |
|
T10 |
2 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48628 |
1 |
|
|
T1 |
125 |
|
T2 |
11 |
|
T3 |
68 |
auto[1] |
1808 |
1 |
|
|
T1 |
12 |
|
T3 |
3 |
|
T9 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48759 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1677 |
1 |
|
|
T9 |
19 |
|
T11 |
11 |
|
T12 |
6 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45105 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
5331 |
1 |
|
|
T9 |
12 |
|
T11 |
12 |
|
T12 |
14 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46781 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
3655 |
1 |
|
|
T13 |
72 |
|
T47 |
70 |
|
T48 |
68 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50436 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48749 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1687 |
1 |
|
|
T9 |
7 |
|
T11 |
4 |
|
T12 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48743 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1693 |
1 |
|
|
T9 |
10 |
|
T11 |
7 |
|
T12 |
10 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48757 |
1 |
|
|
T1 |
137 |
|
T2 |
11 |
|
T3 |
71 |
auto[1] |
1679 |
1 |
|
|
T9 |
16 |
|
T11 |
6 |
|
T12 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
44606 |
1 |
|
|
T1 |
98 |
|
T2 |
11 |
|
T3 |
33 |
auto[0] |
no_err_inj |
3224 |
1 |
|
|
T1 |
16 |
|
T9 |
26 |
|
T11 |
30 |
auto[1] |
err_inj |
1289 |
1 |
|
|
T1 |
11 |
|
T3 |
15 |
|
T9 |
6 |
auto[1] |
no_err_inj |
1317 |
1 |
|
|
T1 |
12 |
|
T3 |
23 |
|
T9 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46250 |
1 |
|
|
T1 |
108 |
|
T2 |
11 |
|
T3 |
33 |
auto[0] |
auto[1] |
1580 |
1 |
|
|
T1 |
6 |
|
T12 |
19 |
|
T90 |
10 |
auto[1] |
auto[0] |
2461 |
1 |
|
|
T1 |
23 |
|
T3 |
35 |
|
T9 |
13 |
auto[1] |
auto[1] |
145 |
1 |
|
|
T3 |
3 |
|
T10 |
2 |
|
T11 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46241 |
1 |
|
|
T1 |
111 |
|
T2 |
11 |
|
T3 |
33 |
auto[0] |
auto[1] |
1589 |
1 |
|
|
T1 |
3 |
|
T12 |
18 |
|
T90 |
10 |
auto[1] |
auto[0] |
2470 |
1 |
|
|
T1 |
23 |
|
T3 |
38 |
|
T9 |
13 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T10 |
3 |
|
T73 |
2 |
|
T16 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46184 |
1 |
|
|
T1 |
103 |
|
T2 |
11 |
|
T3 |
33 |
auto[0] |
auto[1] |
1646 |
1 |
|
|
T1 |
11 |
|
T12 |
33 |
|
T90 |
9 |
auto[1] |
auto[0] |
2444 |
1 |
|
|
T1 |
22 |
|
T3 |
35 |
|
T9 |
12 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T9 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46253 |
1 |
|
|
T1 |
109 |
|
T2 |
11 |
|
T3 |
33 |
auto[0] |
auto[1] |
1577 |
1 |
|
|
T1 |
5 |
|
T12 |
24 |
|
T90 |
10 |
auto[1] |
auto[0] |
2451 |
1 |
|
|
T1 |
21 |
|
T3 |
35 |
|
T9 |
10 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T1 |
2 |
|
T3 |
3 |
|
T9 |
3 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46189 |
1 |
|
|
T1 |
110 |
|
T2 |
11 |
|
T3 |
33 |
auto[0] |
auto[1] |
1641 |
1 |
|
|
T1 |
4 |
|
T12 |
19 |
|
T90 |
11 |
auto[1] |
auto[0] |
2476 |
1 |
|
|
T1 |
22 |
|
T3 |
38 |
|
T9 |
13 |
auto[1] |
auto[1] |
130 |
1 |
|
|
T1 |
1 |
|
T10 |
2 |
|
T16 |
3 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46167 |
1 |
|
|
T1 |
110 |
|
T2 |
11 |
|
T3 |
33 |
auto[0] |
auto[1] |
1663 |
1 |
|
|
T1 |
4 |
|
T12 |
18 |
|
T90 |
9 |
auto[1] |
auto[0] |
2463 |
1 |
|
|
T1 |
23 |
|
T3 |
33 |
|
T9 |
12 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T3 |
5 |
|
T9 |
1 |
|
T10 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33780 |
1 |
|
|
T1 |
95 |
|
T3 |
58 |
|
T10 |
15 |
auto[0] |
auto[1] |
1007 |
1 |
|
|
T12 |
9 |
|
T14 |
12 |
|
T72 |
5 |
auto[1] |
auto[0] |
14955 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
694 |
1 |
|
|
T9 |
13 |
|
T11 |
5 |
|
T35 |
5 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33765 |
1 |
|
|
T1 |
95 |
|
T3 |
58 |
|
T10 |
15 |
auto[0] |
auto[1] |
1022 |
1 |
|
|
T12 |
7 |
|
T14 |
11 |
|
T72 |
13 |
auto[1] |
auto[0] |
14961 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
688 |
1 |
|
|
T9 |
10 |
|
T11 |
9 |
|
T18 |
1 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33567 |
1 |
|
|
T1 |
70 |
|
T3 |
25 |
|
T10 |
15 |
auto[0] |
auto[1] |
1220 |
1 |
|
|
T1 |
25 |
|
T3 |
33 |
|
T12 |
17 |
auto[1] |
auto[0] |
14717 |
1 |
|
|
T1 |
23 |
|
T3 |
13 |
|
T9 |
138 |
auto[1] |
auto[1] |
932 |
1 |
|
|
T1 |
19 |
|
T2 |
11 |
|
T9 |
4 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33779 |
1 |
|
|
T1 |
95 |
|
T3 |
58 |
|
T10 |
15 |
auto[0] |
auto[1] |
1008 |
1 |
|
|
T12 |
12 |
|
T14 |
6 |
|
T72 |
9 |
auto[1] |
auto[0] |
14937 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
712 |
1 |
|
|
T9 |
12 |
|
T11 |
18 |
|
T18 |
4 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30174 |
1 |
|
|
T1 |
95 |
|
T3 |
58 |
|
T10 |
15 |
auto[0] |
auto[1] |
4613 |
1 |
|
|
T12 |
14 |
|
T14 |
14 |
|
T15 |
52 |
auto[1] |
auto[0] |
14931 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
718 |
1 |
|
|
T9 |
12 |
|
T11 |
12 |
|
T18 |
1 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33833 |
1 |
|
|
T1 |
89 |
|
T3 |
55 |
|
T10 |
13 |
auto[0] |
auto[1] |
954 |
1 |
|
|
T1 |
6 |
|
T3 |
3 |
|
T10 |
2 |
auto[1] |
auto[0] |
14878 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
771 |
1 |
|
|
T11 |
1 |
|
T12 |
19 |
|
T16 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33787 |
1 |
|
|
T1 |
87 |
|
T3 |
58 |
|
T10 |
15 |
auto[0] |
auto[1] |
1000 |
1 |
|
|
T1 |
8 |
|
T90 |
14 |
|
T16 |
8 |
auto[1] |
auto[0] |
14776 |
1 |
|
|
T1 |
39 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
873 |
1 |
|
|
T1 |
3 |
|
T12 |
27 |
|
T16 |
14 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33812 |
1 |
|
|
T1 |
92 |
|
T3 |
58 |
|
T10 |
12 |
auto[0] |
auto[1] |
975 |
1 |
|
|
T1 |
3 |
|
T10 |
3 |
|
T73 |
2 |
auto[1] |
auto[0] |
14899 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T12 |
18 |
|
T16 |
9 |
|
T18 |
2 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33812 |
1 |
|
|
T1 |
91 |
|
T3 |
57 |
|
T10 |
14 |
auto[0] |
auto[1] |
975 |
1 |
|
|
T1 |
4 |
|
T3 |
1 |
|
T10 |
1 |
auto[1] |
auto[0] |
14866 |
1 |
|
|
T1 |
40 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
783 |
1 |
|
|
T1 |
2 |
|
T9 |
1 |
|
T11 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33826 |
1 |
|
|
T1 |
90 |
|
T3 |
57 |
|
T10 |
15 |
auto[0] |
auto[1] |
961 |
1 |
|
|
T1 |
5 |
|
T3 |
1 |
|
T73 |
1 |
auto[1] |
auto[0] |
14878 |
1 |
|
|
T1 |
40 |
|
T2 |
11 |
|
T3 |
11 |
auto[1] |
auto[1] |
771 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T9 |
3 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33819 |
1 |
|
|
T1 |
91 |
|
T3 |
56 |
|
T10 |
13 |
auto[0] |
auto[1] |
968 |
1 |
|
|
T1 |
4 |
|
T3 |
2 |
|
T10 |
2 |
auto[1] |
auto[0] |
14811 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
10 |
auto[1] |
auto[1] |
838 |
1 |
|
|
T3 |
3 |
|
T9 |
1 |
|
T11 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33833 |
1 |
|
|
T1 |
95 |
|
T3 |
58 |
|
T10 |
15 |
auto[0] |
auto[1] |
954 |
1 |
|
|
T12 |
9 |
|
T14 |
12 |
|
T72 |
12 |
auto[1] |
auto[0] |
14924 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
725 |
1 |
|
|
T9 |
16 |
|
T11 |
6 |
|
T35 |
15 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33797 |
1 |
|
|
T1 |
95 |
|
T3 |
58 |
|
T10 |
15 |
auto[0] |
auto[1] |
990 |
1 |
|
|
T12 |
10 |
|
T14 |
12 |
|
T72 |
8 |
auto[1] |
auto[0] |
14946 |
1 |
|
|
T1 |
42 |
|
T2 |
11 |
|
T3 |
13 |
auto[1] |
auto[1] |
703 |
1 |
|
|
T9 |
10 |
|
T11 |
7 |
|
T18 |
1 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33269 |
1 |
|
|
T1 |
95 |
|
T3 |
33 |
|
T11 |
23 |
auto[0] |
auto[1] |
1518 |
1 |
|
|
T3 |
25 |
|
T10 |
15 |
|
T73 |
10 |
auto[1] |
auto[0] |
14561 |
1 |
|
|
T1 |
19 |
|
T2 |
11 |
|
T9 |
129 |
auto[1] |
auto[1] |
1088 |
1 |
|
|
T1 |
23 |
|
T3 |
13 |
|
T9 |
13 |