Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94200800

1

T1

171823

T2

36361

T3

63645

auto[1]

1339243

1

T1

4043

T2

784

T3

2275

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94197172

1

T1

171422

T2

36851

T3

63745

auto[1]

1342871

1

T1

4444

T2

294

T3

2175

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7012846	1			T1	16737		T2	1080		T3	6901
auto[IdleSt]	20369139	1			T1	43257		T2	21077		T3	17691
auto[ClkMuxSt]	33386	1			T1	72		T2	11		T3	56
auto[CntIncrSt]	33148	1			T1	72		T2	11		T3	56
auto[CntProgSt]	1711016	1			T1	144		T2	303		T3	112
auto[TransCheckSt]	25794	1			T1	28		T3	23		T9	107
auto[TokenHashSt]	34909680	1			T1	38697		T3	4098		T9	101131
auto[FlashRmaSt]	34272	1			T1	45		T3	89		T9	123
auto[TokenCheck0St]	11818	1			T1	28		T3	23		T9	53
auto[TokenCheck1St]	8816	1			T1	28		T3	23		T9	44
auto[TransProgSt]	444311	1			T1	56		T3	46		T9	9655
auto[PostTransSt]	11916661	1			T1	35360		T2	8226		T3	17978
auto[ScrapSt]	146147	1			T1	9		T9	6476		T11	1427
auto[EscalateSt]	6670340	1			T1	26476		T2	6437		T3	12142
auto[InvalidSt]	12210871	1			T1	14854		T3	6682		T9	13407

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1798	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12210871	1			T1	14854		T3	6682		T9	13407
EscalateSt	6670340	1			T1	26476		T2	6437		T3	12142
ScrapSt	146147	1			T1	9		T9	6476		T11	1427
PostTransSt	11916661	1			T1	35360		T2	8226		T3	17978
TransProgSt	444311	1			T1	56		T3	46		T9	9655
TokenCheck1St	8816	1			T1	28		T3	23		T9	44
TokenCheck0St	11818	1			T1	28		T3	23		T9	53
FlashRmaSt	34272	1			T1	45		T3	89		T9	123
TokenHashSt	34909680	1			T1	38697		T3	4098		T9	101131
TransCheckSt	25794	1			T1	28		T3	23		T9	107
CntProgSt	1711016	1			T1	144		T2	303		T3	112
CntIncrSt	33148	1			T1	72		T2	11		T3	56
ClkMuxSt	33386	1			T1	72		T2	11		T3	56
IdleSt	20369139	1			T1	43257		T2	21077		T3	17691
ResetSt	7012846	1			T1	16737		T2	1080		T3	6901
arcs[ResetSt=>IdleSt]	50687	1			T1	133		T2	12		T3	77
arcs[IdleSt=>ScrapSt]	263	1			T1	1		T9	2		T11	4
arcs[IdleSt=>ClkMuxSt]	33219	1			T1	72		T2	11		T3	56
arcs[ClkMuxSt=>CntIncrSt]	33148	1			T1	72		T2	11		T3	56
arcs[CntIncrSt=>PostTransSt]	1693	1			T9	10		T11	7		T12	10
arcs[CntIncrSt=>CntProgSt]	31386	1			T1	72		T2	11		T3	56
arcs[CntProgSt=>PostTransSt]	4451	1			T1	44		T2	11		T3	33
arcs[CntProgSt=>TransCheckSt]	25794	1			T1	28		T3	23		T9	107
arcs[TransCheckSt=>PostTransSt]	3455	1			T9	16		T11	6		T12	9
arcs[TransCheckSt=>TokenHashSt]	22226	1			T1	28		T3	23		T9	91
arcs[TokenHashSt=>PostTransSt]	9618	1			T9	38		T11	27		T12	27
arcs[TokenHashSt=>FlashRmaSt]	11916	1			T1	28		T3	23		T9	53
arcs[FlashRmaSt=>TokenCheck0St]	11818	1			T1	28		T3	23		T9	53
arcs[TokenCheck0St=>PostTransSt]	2979	1			T9	9		T11	7		T12	6
arcs[TokenCheck0St=>TokenCheck1St]	8816	1			T1	28		T3	23		T9	44
arcs[TokenCheck1St=>PostTransSt]	653	1			T9	1		T11	2		T12	1
arcs[TransProgSt=>PostTransSt]	7312	1			T1	28		T3	23		T9	43
arcs[IdleSt=>EscalateSt]	200	1			T50	7		T52	4		T53	3
arcs[ClkMuxSt=>EscalateSt]	71	1			T49	3		T50	1		T51	2
arcs[CntIncrSt=>EscalateSt]	69	1			T49	1		T52	4		T53	3
arcs[CntProgSt=>EscalateSt]	1141	1			T49	12		T50	29		T52	4
arcs[TransCheckSt=>EscalateSt]	113	1			T49	10		T52	7		T53	1
arcs[TokenHashSt=>EscalateSt]	692	1			T49	31		T50	6		T52	20
arcs[FlashRmaSt=>EscalateSt]	98	1			T49	3		T50	3		T52	1
arcs[TokenCheck0St=>EscalateSt]	23	1			T50	1		T51	1		T57	1
arcs[TokenCheck1St=>EscalateSt]	138	1			T49	5		T50	5		T53	3
arcs[TransProgSt=>EscalateSt]	713	1			T49	11		T50	22		T52	9
arcs[PostTransSt=>EscalateSt]	4710	1			T1	44		T2	11		T3	33
arcs[InvalidSt=>EscalateSt]	13003	1			T1	42		T3	12		T9	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7012647	1			T1	16737		T2	1080		T3	6901
auto[0]	auto[IdleSt]	20369013	1			T1	43257		T2	21077		T3	17691
auto[0]	auto[ClkMuxSt]	33342	1			T1	72		T2	11		T3	56
auto[0]	auto[CntIncrSt]	33098	1			T1	72		T2	11		T3	56
auto[0]	auto[CntProgSt]	1710249	1			T1	144		T2	303		T3	112
auto[0]	auto[TransCheckSt]	25713	1			T1	28		T3	23		T9	107
auto[0]	auto[TokenHashSt]	34909221	1			T1	38697		T3	4098		T9	101131
auto[0]	auto[FlashRmaSt]	34213	1			T1	45		T3	89		T9	123
auto[0]	auto[TokenCheck0St]	11800	1			T1	28		T3	23		T9	53
auto[0]	auto[TokenCheck1St]	8731	1			T1	28		T3	23		T9	44
auto[0]	auto[TransProgSt]	443840	1			T1	56		T3	46		T9	9655
auto[0]	auto[PostTransSt]	11914268	1			T1	35335		T2	8218		T3	17960
auto[0]	auto[ScrapSt]	146101	1			T1	9		T9	6476		T11	1427
auto[0]	auto[EscalateSt]	5342369	1			T1	22474		T2	5661		T3	9890
auto[0]	auto[InvalidSt]	12204397	1			T1	14838		T3	6677		T9	13402
auto[1]	auto[ResetSt]	199	1			T49	7		T50	4		T52	4
auto[1]	auto[IdleSt]	126	1			T50	2		T52	3		T53	2
auto[1]	auto[ClkMuxSt]	44	1			T49	2		T50	1		T51	1
auto[1]	auto[CntIncrSt]	50	1			T49	1		T52	2		T53	3
auto[1]	auto[CntProgSt]	767	1			T49	9		T50	21		T52	4
auto[1]	auto[TransCheckSt]	81	1			T49	7		T52	6		T53	1
auto[1]	auto[TokenHashSt]	459	1			T49	19		T50	4		T52	16
auto[1]	auto[FlashRmaSt]	59	1			T49	1		T50	1		T51	1
auto[1]	auto[TokenCheck0St]	18	1			T50	1		T51	1		T57	1
auto[1]	auto[TokenCheck1St]	85	1			T49	3		T50	4		T53	3
auto[1]	auto[TransProgSt]	471	1			T49	7		T50	16		T52	3
auto[1]	auto[PostTransSt]	2393	1			T1	25		T2	8		T3	18
auto[1]	auto[ScrapSt]	46	1			T49	1		T52	3		T51	1
auto[1]	auto[EscalateSt]	1327971	1			T1	4002		T2	776		T3	2252
auto[1]	auto[InvalidSt]	6474	1			T1	16		T3	5		T9	5

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7012669	1			T1	16737		T2	1080		T3	6901
auto[0]	auto[IdleSt]	20369008	1			T1	43257		T2	21077		T3	17691
auto[0]	auto[ClkMuxSt]	33340	1			T1	72		T2	11		T3	56
auto[0]	auto[CntIncrSt]	33104	1			T1	72		T2	11		T3	56
auto[0]	auto[CntProgSt]	1710242	1			T1	144		T2	303		T3	112
auto[0]	auto[TransCheckSt]	25729	1			T1	28		T3	23		T9	107
auto[0]	auto[TokenHashSt]	34909222	1			T1	38697		T3	4098		T9	101131
auto[0]	auto[FlashRmaSt]	34203	1			T1	45		T3	89		T9	123
auto[0]	auto[TokenCheck0St]	11802	1			T1	28		T3	23		T9	53
auto[0]	auto[TokenCheck1St]	8716	1			T1	28		T3	23		T9	44
auto[0]	auto[TransProgSt]	443845	1			T1	56		T3	46		T9	9655
auto[0]	auto[PostTransSt]	11914260	1			T1	35341		T2	8223		T3	17963
auto[0]	auto[ScrapSt]	146102	1			T1	9		T9	6476		T11	1427
auto[0]	auto[EscalateSt]	5338790	1			T1	22077		T2	6146		T3	9989
auto[0]	auto[InvalidSt]	12204342	1			T1	14828		T3	6675		T9	13407
auto[1]	auto[ResetSt]	177	1			T49	4		T50	3		T52	4
auto[1]	auto[IdleSt]	131	1			T50	6		T52	3		T53	2
auto[1]	auto[ClkMuxSt]	46	1			T49	1		T51	1		T103	2
auto[1]	auto[CntIncrSt]	44	1			T49	1		T52	3		T53	1
auto[1]	auto[CntProgSt]	774	1			T49	6		T50	21		T52	4
auto[1]	auto[TransCheckSt]	65	1			T49	6		T52	3		T51	1
auto[1]	auto[TokenHashSt]	458	1			T49	23		T50	4		T52	13
auto[1]	auto[FlashRmaSt]	69	1			T49	2		T50	3		T52	1
auto[1]	auto[TokenCheck0St]	16	1			T50	1		T51	1		T57	1
auto[1]	auto[TokenCheck1St]	100	1			T49	4		T50	5		T53	1
auto[1]	auto[TransProgSt]	466	1			T49	8		T50	10		T52	8
auto[1]	auto[PostTransSt]	2401	1			T1	19		T2	3		T3	15
auto[1]	auto[ScrapSt]	45	1			T49	1		T52	2		T51	1
auto[1]	auto[EscalateSt]	1331550	1			T1	4399		T2	291		T3	2153
auto[1]	auto[InvalidSt]	6529	1			T1	26		T3	7		T10	7