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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.92 96.12 93.38 100.00 98.52 98.51 96.29


Total test records in report: 992
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T810 /workspace/coverage/default/46.lc_ctrl_jtag_access.2891506977 Jul 09 05:27:27 PM PDT 24 Jul 09 05:27:37 PM PDT 24 1219758404 ps
T811 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1633951447 Jul 09 05:26:52 PM PDT 24 Jul 09 05:27:02 PM PDT 24 335428844 ps
T812 /workspace/coverage/default/44.lc_ctrl_state_post_trans.627074949 Jul 09 05:27:16 PM PDT 24 Jul 09 05:27:21 PM PDT 24 41707976 ps
T813 /workspace/coverage/default/25.lc_ctrl_jtag_access.254650028 Jul 09 05:26:36 PM PDT 24 Jul 09 05:26:42 PM PDT 24 776429493 ps
T814 /workspace/coverage/default/22.lc_ctrl_errors.1740246270 Jul 09 05:26:31 PM PDT 24 Jul 09 05:26:54 PM PDT 24 599509833 ps
T56 /workspace/coverage/default/2.lc_ctrl_sec_cm.1556386563 Jul 09 05:25:31 PM PDT 24 Jul 09 05:26:10 PM PDT 24 2731417605 ps
T815 /workspace/coverage/default/3.lc_ctrl_jtag_errors.3770182230 Jul 09 05:25:34 PM PDT 24 Jul 09 05:25:54 PM PDT 24 3876334612 ps
T816 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4276859481 Jul 09 05:27:03 PM PDT 24 Jul 09 05:27:29 PM PDT 24 1249732447 ps
T817 /workspace/coverage/default/1.lc_ctrl_errors.1491209380 Jul 09 05:25:31 PM PDT 24 Jul 09 05:25:38 PM PDT 24 1839638755 ps
T818 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1635621002 Jul 09 05:26:30 PM PDT 24 Jul 09 05:26:41 PM PDT 24 302776809 ps
T819 /workspace/coverage/default/12.lc_ctrl_state_failure.1820574626 Jul 09 05:26:10 PM PDT 24 Jul 09 05:26:46 PM PDT 24 5701811405 ps
T820 /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3927606703 Jul 09 05:26:15 PM PDT 24 Jul 09 05:26:19 PM PDT 24 19613423 ps
T821 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.72968381 Jul 09 05:27:02 PM PDT 24 Jul 09 05:27:21 PM PDT 24 1911098182 ps
T822 /workspace/coverage/default/15.lc_ctrl_state_post_trans.3372346888 Jul 09 05:26:17 PM PDT 24 Jul 09 05:26:22 PM PDT 24 50062450 ps
T823 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.795461328 Jul 09 05:26:12 PM PDT 24 Jul 09 05:26:19 PM PDT 24 969621547 ps
T824 /workspace/coverage/default/39.lc_ctrl_smoke.916074289 Jul 09 05:27:04 PM PDT 24 Jul 09 05:27:08 PM PDT 24 376289592 ps
T825 /workspace/coverage/default/26.lc_ctrl_stress_all.3308157028 Jul 09 05:26:39 PM PDT 24 Jul 09 05:28:44 PM PDT 24 48903275144 ps
T826 /workspace/coverage/default/36.lc_ctrl_jtag_access.1609057389 Jul 09 05:27:01 PM PDT 24 Jul 09 05:27:05 PM PDT 24 344889858 ps
T827 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4231079384 Jul 09 05:27:23 PM PDT 24 Jul 09 05:27:38 PM PDT 24 1015667292 ps
T828 /workspace/coverage/default/44.lc_ctrl_jtag_access.1755039079 Jul 09 05:27:21 PM PDT 24 Jul 09 05:27:24 PM PDT 24 91686170 ps
T829 /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1608879670 Jul 09 05:26:35 PM PDT 24 Jul 09 05:26:46 PM PDT 24 3928782757 ps
T830 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2703316388 Jul 09 05:25:55 PM PDT 24 Jul 09 05:25:58 PM PDT 24 52739490 ps
T831 /workspace/coverage/default/47.lc_ctrl_prog_failure.2398818796 Jul 09 05:27:22 PM PDT 24 Jul 09 05:27:27 PM PDT 24 124540824 ps
T832 /workspace/coverage/default/18.lc_ctrl_jtag_access.2999016130 Jul 09 05:26:23 PM PDT 24 Jul 09 05:26:46 PM PDT 24 930272399 ps
T833 /workspace/coverage/default/13.lc_ctrl_errors.1411581665 Jul 09 05:26:28 PM PDT 24 Jul 09 05:26:42 PM PDT 24 434391300 ps
T834 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3900913808 Jul 09 05:25:32 PM PDT 24 Jul 09 05:25:53 PM PDT 24 347991459 ps
T835 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2746097550 Jul 09 05:25:45 PM PDT 24 Jul 09 05:25:54 PM PDT 24 269810496 ps
T836 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.210771999 Jul 09 05:26:08 PM PDT 24 Jul 09 05:27:14 PM PDT 24 10359717492 ps
T837 /workspace/coverage/default/4.lc_ctrl_errors.1246996088 Jul 09 05:25:39 PM PDT 24 Jul 09 05:25:49 PM PDT 24 1521731453 ps
T838 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1075450491 Jul 09 05:26:13 PM PDT 24 Jul 09 05:26:17 PM PDT 24 1671101022 ps
T839 /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2166974158 Jul 09 05:27:25 PM PDT 24 Jul 09 05:27:34 PM PDT 24 535385381 ps
T840 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3365505919 Jul 09 05:25:41 PM PDT 24 Jul 09 05:25:56 PM PDT 24 565550723 ps
T841 /workspace/coverage/default/17.lc_ctrl_jtag_errors.2544485462 Jul 09 05:26:21 PM PDT 24 Jul 09 05:27:13 PM PDT 24 5713337363 ps
T842 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2818336700 Jul 09 05:26:13 PM PDT 24 Jul 09 05:26:15 PM PDT 24 37969230 ps
T843 /workspace/coverage/default/13.lc_ctrl_security_escalation.3880590235 Jul 09 05:26:13 PM PDT 24 Jul 09 05:26:28 PM PDT 24 358644580 ps
T844 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.251564062 Jul 09 05:25:28 PM PDT 24 Jul 09 05:26:23 PM PDT 24 2557679740 ps
T845 /workspace/coverage/default/47.lc_ctrl_jtag_access.3443328798 Jul 09 05:27:29 PM PDT 24 Jul 09 05:27:33 PM PDT 24 831979388 ps
T846 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3412457155 Jul 09 05:26:01 PM PDT 24 Jul 09 05:26:20 PM PDT 24 592770583 ps
T847 /workspace/coverage/default/42.lc_ctrl_errors.2182594157 Jul 09 05:27:12 PM PDT 24 Jul 09 05:27:23 PM PDT 24 875156572 ps
T848 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1726475769 Jul 09 05:26:17 PM PDT 24 Jul 09 05:26:22 PM PDT 24 530888733 ps
T849 /workspace/coverage/default/41.lc_ctrl_errors.3914539943 Jul 09 05:27:21 PM PDT 24 Jul 09 05:27:35 PM PDT 24 2292343240 ps
T850 /workspace/coverage/default/39.lc_ctrl_jtag_access.3852006123 Jul 09 05:27:06 PM PDT 24 Jul 09 05:27:15 PM PDT 24 2183640813 ps
T851 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.4013264764 Jul 09 05:25:42 PM PDT 24 Jul 09 05:25:53 PM PDT 24 263668052 ps
T852 /workspace/coverage/default/3.lc_ctrl_jtag_priority.3999986271 Jul 09 05:25:36 PM PDT 24 Jul 09 05:25:45 PM PDT 24 2061573454 ps
T853 /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2078521179 Jul 09 05:26:07 PM PDT 24 Jul 09 05:26:20 PM PDT 24 297581535 ps
T854 /workspace/coverage/default/7.lc_ctrl_security_escalation.2172834395 Jul 09 05:25:56 PM PDT 24 Jul 09 05:26:07 PM PDT 24 813727414 ps
T855 /workspace/coverage/default/38.lc_ctrl_security_escalation.1142965314 Jul 09 05:27:05 PM PDT 24 Jul 09 05:27:16 PM PDT 24 942085312 ps
T856 /workspace/coverage/default/27.lc_ctrl_jtag_access.1355665219 Jul 09 05:26:52 PM PDT 24 Jul 09 05:27:00 PM PDT 24 696944647 ps
T857 /workspace/coverage/default/16.lc_ctrl_jtag_errors.3327639470 Jul 09 05:26:17 PM PDT 24 Jul 09 05:26:54 PM PDT 24 3907219445 ps
T858 /workspace/coverage/default/23.lc_ctrl_alert_test.3138426973 Jul 09 05:26:45 PM PDT 24 Jul 09 05:26:48 PM PDT 24 118645681 ps
T859 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.4177763224 Jul 09 05:25:48 PM PDT 24 Jul 09 05:26:17 PM PDT 24 2212010558 ps
T860 /workspace/coverage/default/16.lc_ctrl_smoke.3061330992 Jul 09 05:26:16 PM PDT 24 Jul 09 05:26:20 PM PDT 24 48882795 ps
T861 /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1326190137 Jul 09 05:27:21 PM PDT 24 Jul 09 05:27:23 PM PDT 24 23507355 ps
T862 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.229709782 Jul 09 05:27:10 PM PDT 24 Jul 09 05:27:23 PM PDT 24 512506509 ps
T44 /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2802056095 Jul 09 05:26:12 PM PDT 24 Jul 09 05:36:05 PM PDT 24 16641471565 ps
T863 /workspace/coverage/default/41.lc_ctrl_stress_all.1815043351 Jul 09 05:27:14 PM PDT 24 Jul 09 05:28:42 PM PDT 24 5340313627 ps
T864 /workspace/coverage/default/9.lc_ctrl_alert_test.3454462577 Jul 09 05:25:53 PM PDT 24 Jul 09 05:25:56 PM PDT 24 87368036 ps
T138 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1770591409 Jul 09 06:59:18 PM PDT 24 Jul 09 06:59:24 PM PDT 24 134205244 ps
T105 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4262975990 Jul 09 06:59:30 PM PDT 24 Jul 09 06:59:33 PM PDT 24 56588345 ps
T118 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1322084290 Jul 09 06:59:22 PM PDT 24 Jul 09 06:59:26 PM PDT 24 18172923 ps
T111 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3409382052 Jul 09 06:59:27 PM PDT 24 Jul 09 06:59:29 PM PDT 24 35708090 ps
T119 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4023705887 Jul 09 06:59:08 PM PDT 24 Jul 09 06:59:12 PM PDT 24 24475557 ps
T112 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.676215009 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:09 PM PDT 24 75622990 ps
T865 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.200967353 Jul 09 06:59:11 PM PDT 24 Jul 09 06:59:15 PM PDT 24 48332227 ps
T113 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3169671472 Jul 09 06:59:05 PM PDT 24 Jul 09 06:59:10 PM PDT 24 495263332 ps
T106 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2713028637 Jul 09 06:59:34 PM PDT 24 Jul 09 06:59:38 PM PDT 24 202001000 ps
T866 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2965377054 Jul 09 06:59:24 PM PDT 24 Jul 09 06:59:26 PM PDT 24 106011909 ps
T867 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1335494666 Jul 09 06:59:00 PM PDT 24 Jul 09 06:59:02 PM PDT 24 57059949 ps
T150 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1537045746 Jul 09 06:59:21 PM PDT 24 Jul 09 06:59:25 PM PDT 24 26521244 ps
T868 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4047805666 Jul 09 06:59:34 PM PDT 24 Jul 09 06:59:37 PM PDT 24 21236895 ps
T139 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2114949772 Jul 09 06:59:12 PM PDT 24 Jul 09 06:59:28 PM PDT 24 771010071 ps
T140 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.878113675 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:59 PM PDT 24 12461049535 ps
T207 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3121807209 Jul 09 06:59:06 PM PDT 24 Jul 09 06:59:09 PM PDT 24 127223462 ps
T107 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3005426449 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:22 PM PDT 24 621276951 ps
T136 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.894676972 Jul 09 06:59:31 PM PDT 24 Jul 09 06:59:36 PM PDT 24 407473673 ps
T208 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.531499821 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:35 PM PDT 24 40600362 ps
T108 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.64467132 Jul 09 06:59:30 PM PDT 24 Jul 09 06:59:34 PM PDT 24 399117274 ps
T137 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3355875840 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:30 PM PDT 24 517191742 ps
T869 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3987819946 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:10 PM PDT 24 22156478 ps
T209 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3668865420 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:18 PM PDT 24 80050722 ps
T210 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4162277335 Jul 09 06:59:10 PM PDT 24 Jul 09 06:59:15 PM PDT 24 36605391 ps
T109 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4001481044 Jul 09 06:59:19 PM PDT 24 Jul 09 06:59:29 PM PDT 24 1243918163 ps
T870 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1946117547 Jul 09 06:59:09 PM PDT 24 Jul 09 06:59:13 PM PDT 24 73537235 ps
T110 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2905472566 Jul 09 06:59:36 PM PDT 24 Jul 09 06:59:39 PM PDT 24 52178162 ps
T134 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3568354912 Jul 09 06:59:08 PM PDT 24 Jul 09 06:59:13 PM PDT 24 505902299 ps
T151 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.945483001 Jul 09 06:59:37 PM PDT 24 Jul 09 06:59:41 PM PDT 24 53509699 ps
T871 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1408583396 Jul 09 06:59:12 PM PDT 24 Jul 09 06:59:15 PM PDT 24 57999687 ps
T114 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3752278450 Jul 09 06:59:18 PM PDT 24 Jul 09 06:59:26 PM PDT 24 219392678 ps
T152 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.771240130 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:35 PM PDT 24 43575252 ps
T115 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.622443390 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:19 PM PDT 24 303727557 ps
T872 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4179802096 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:11 PM PDT 24 613597387 ps
T122 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.6270727 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:38 PM PDT 24 188224810 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1828327947 Jul 09 06:59:04 PM PDT 24 Jul 09 06:59:15 PM PDT 24 3180274855 ps
T211 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2634581061 Jul 09 06:59:31 PM PDT 24 Jul 09 06:59:33 PM PDT 24 28173159 ps
T125 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1177284604 Jul 09 06:59:22 PM PDT 24 Jul 09 06:59:28 PM PDT 24 145440319 ps
T116 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1148356486 Jul 09 06:59:05 PM PDT 24 Jul 09 06:59:10 PM PDT 24 209185811 ps
T135 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3264483656 Jul 09 06:59:24 PM PDT 24 Jul 09 06:59:27 PM PDT 24 467799813 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3486948248 Jul 09 06:59:09 PM PDT 24 Jul 09 06:59:13 PM PDT 24 78403772 ps
T875 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.923905627 Jul 09 06:59:16 PM PDT 24 Jul 09 06:59:21 PM PDT 24 21883271 ps
T876 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1893010677 Jul 09 06:59:36 PM PDT 24 Jul 09 06:59:39 PM PDT 24 60222495 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1176705791 Jul 09 06:59:12 PM PDT 24 Jul 09 06:59:19 PM PDT 24 300198754 ps
T878 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2200995245 Jul 09 06:59:12 PM PDT 24 Jul 09 06:59:16 PM PDT 24 47659651 ps
T879 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1828878120 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:17 PM PDT 24 25533720 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4008263715 Jul 09 06:59:12 PM PDT 24 Jul 09 06:59:17 PM PDT 24 75557257 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1493000522 Jul 09 06:59:08 PM PDT 24 Jul 09 06:59:16 PM PDT 24 833373739 ps
T882 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2183967284 Jul 09 06:59:28 PM PDT 24 Jul 09 06:59:30 PM PDT 24 183381570 ps
T194 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.784441057 Jul 09 06:59:11 PM PDT 24 Jul 09 06:59:16 PM PDT 24 123658191 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1813922450 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:19 PM PDT 24 871151711 ps
T884 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.229848681 Jul 09 06:59:28 PM PDT 24 Jul 09 06:59:30 PM PDT 24 21721579 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.698801527 Jul 09 06:59:25 PM PDT 24 Jul 09 06:59:28 PM PDT 24 109959621 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2213941616 Jul 09 06:59:03 PM PDT 24 Jul 09 06:59:06 PM PDT 24 71716663 ps
T887 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1214282939 Jul 09 06:59:34 PM PDT 24 Jul 09 06:59:38 PM PDT 24 66004145 ps
T124 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.21122438 Jul 09 06:59:32 PM PDT 24 Jul 09 06:59:37 PM PDT 24 221925840 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.479933665 Jul 09 06:59:03 PM PDT 24 Jul 09 06:59:10 PM PDT 24 660516704 ps
T132 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2380424487 Jul 09 06:59:16 PM PDT 24 Jul 09 06:59:23 PM PDT 24 84353058 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1666162353 Jul 09 06:59:03 PM PDT 24 Jul 09 06:59:06 PM PDT 24 49290643 ps
T890 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.458499289 Jul 09 06:59:37 PM PDT 24 Jul 09 06:59:40 PM PDT 24 13759856 ps
T891 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.335255039 Jul 09 06:59:16 PM PDT 24 Jul 09 06:59:22 PM PDT 24 27967265 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4025643327 Jul 09 06:59:23 PM PDT 24 Jul 09 06:59:26 PM PDT 24 49136468 ps
T893 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2942628267 Jul 09 06:59:38 PM PDT 24 Jul 09 06:59:42 PM PDT 24 96347705 ps
T127 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3919385874 Jul 09 06:59:26 PM PDT 24 Jul 09 06:59:30 PM PDT 24 328818441 ps
T123 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.809918061 Jul 09 06:59:16 PM PDT 24 Jul 09 06:59:24 PM PDT 24 468289677 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.100340379 Jul 09 06:59:12 PM PDT 24 Jul 09 06:59:17 PM PDT 24 95148698 ps
T895 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3437151812 Jul 09 06:59:32 PM PDT 24 Jul 09 06:59:35 PM PDT 24 31725565 ps
T120 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2384454242 Jul 09 06:59:08 PM PDT 24 Jul 09 06:59:14 PM PDT 24 330158544 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.602970606 Jul 09 06:59:05 PM PDT 24 Jul 09 06:59:09 PM PDT 24 51615087 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2920714785 Jul 09 06:59:02 PM PDT 24 Jul 09 06:59:05 PM PDT 24 32296644 ps
T898 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2958942898 Jul 09 06:59:17 PM PDT 24 Jul 09 06:59:22 PM PDT 24 394632732 ps
T899 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3117960939 Jul 09 06:59:18 PM PDT 24 Jul 09 06:59:23 PM PDT 24 95215625 ps
T195 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2788301046 Jul 09 06:59:01 PM PDT 24 Jul 09 06:59:03 PM PDT 24 11760922 ps
T900 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3918539709 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:21 PM PDT 24 107757904 ps
T901 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.512228243 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:11 PM PDT 24 73933112 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1414084078 Jul 09 06:59:22 PM PDT 24 Jul 09 06:59:28 PM PDT 24 363016491 ps
T903 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3205106798 Jul 09 06:59:38 PM PDT 24 Jul 09 06:59:44 PM PDT 24 163571921 ps
T904 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3653985267 Jul 09 06:59:18 PM PDT 24 Jul 09 07:00:05 PM PDT 24 1928722306 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1818431609 Jul 09 06:59:08 PM PDT 24 Jul 09 06:59:24 PM PDT 24 559671138 ps
T196 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3685142498 Jul 09 06:59:08 PM PDT 24 Jul 09 06:59:11 PM PDT 24 15952519 ps
T121 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.152483105 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:39 PM PDT 24 200315685 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.61565073 Jul 09 06:59:06 PM PDT 24 Jul 09 06:59:08 PM PDT 24 21014125 ps
T907 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2506388674 Jul 09 06:59:05 PM PDT 24 Jul 09 06:59:09 PM PDT 24 957648696 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3838166845 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:12 PM PDT 24 730665534 ps
T909 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3153972236 Jul 09 06:59:37 PM PDT 24 Jul 09 06:59:42 PM PDT 24 60646752 ps
T133 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.650557464 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:12 PM PDT 24 117989966 ps
T910 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1722185194 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:19 PM PDT 24 32076844 ps
T911 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1187590091 Jul 09 06:59:06 PM PDT 24 Jul 09 06:59:10 PM PDT 24 118891295 ps
T912 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1269055218 Jul 09 06:59:35 PM PDT 24 Jul 09 06:59:38 PM PDT 24 72352957 ps
T913 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.512477963 Jul 09 06:59:29 PM PDT 24 Jul 09 06:59:31 PM PDT 24 128997241 ps
T126 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1909091382 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:38 PM PDT 24 128330672 ps
T914 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1096485223 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:19 PM PDT 24 21752647 ps
T915 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2107153950 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:23 PM PDT 24 442312000 ps
T916 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.118882336 Jul 09 06:59:36 PM PDT 24 Jul 09 06:59:40 PM PDT 24 47807129 ps
T917 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4191842473 Jul 09 06:59:09 PM PDT 24 Jul 09 06:59:13 PM PDT 24 45592683 ps
T128 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.739061116 Jul 09 06:59:06 PM PDT 24 Jul 09 06:59:10 PM PDT 24 205089949 ps
T918 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3681350776 Jul 09 06:59:19 PM PDT 24 Jul 09 06:59:24 PM PDT 24 57144962 ps
T919 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2044218434 Jul 09 06:59:35 PM PDT 24 Jul 09 06:59:38 PM PDT 24 74813506 ps
T129 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2137637477 Jul 09 06:59:28 PM PDT 24 Jul 09 06:59:35 PM PDT 24 721168282 ps
T197 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2338566561 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:35 PM PDT 24 13414475 ps
T920 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1377422135 Jul 09 06:59:35 PM PDT 24 Jul 09 06:59:40 PM PDT 24 2414462870 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2068971070 Jul 09 06:59:24 PM PDT 24 Jul 09 06:59:27 PM PDT 24 77380416 ps
T922 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.998361853 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:21 PM PDT 24 75856414 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3878530846 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:18 PM PDT 24 220746389 ps
T924 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3683891466 Jul 09 06:59:26 PM PDT 24 Jul 09 06:59:29 PM PDT 24 279489639 ps
T925 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3972817876 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:11 PM PDT 24 317251643 ps
T926 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3290545595 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:11 PM PDT 24 122244612 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2108624638 Jul 09 06:59:11 PM PDT 24 Jul 09 06:59:24 PM PDT 24 421089736 ps
T928 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1536598820 Jul 09 06:59:21 PM PDT 24 Jul 09 06:59:26 PM PDT 24 43194452 ps
T929 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.744491609 Jul 09 06:59:02 PM PDT 24 Jul 09 06:59:04 PM PDT 24 25789848 ps
T930 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1847280928 Jul 09 06:59:36 PM PDT 24 Jul 09 06:59:38 PM PDT 24 24400826 ps
T202 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.660890886 Jul 09 06:59:11 PM PDT 24 Jul 09 06:59:17 PM PDT 24 68985634 ps
T931 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4185516488 Jul 09 06:59:21 PM PDT 24 Jul 09 06:59:32 PM PDT 24 4472557868 ps
T198 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3633497779 Jul 09 06:59:02 PM PDT 24 Jul 09 06:59:04 PM PDT 24 14071678 ps
T932 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3551074197 Jul 09 06:59:31 PM PDT 24 Jul 09 06:59:34 PM PDT 24 123548586 ps
T933 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.236217588 Jul 09 06:59:34 PM PDT 24 Jul 09 06:59:38 PM PDT 24 74448974 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3712572681 Jul 09 06:59:08 PM PDT 24 Jul 09 06:59:13 PM PDT 24 38614686 ps
T935 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3557236184 Jul 09 06:59:02 PM PDT 24 Jul 09 06:59:04 PM PDT 24 51783879 ps
T131 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.84331642 Jul 09 06:59:23 PM PDT 24 Jul 09 06:59:28 PM PDT 24 214594176 ps
T936 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3993729171 Jul 09 06:59:34 PM PDT 24 Jul 09 06:59:38 PM PDT 24 100576085 ps
T937 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1080202131 Jul 09 06:59:27 PM PDT 24 Jul 09 06:59:29 PM PDT 24 76932679 ps
T938 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1544545545 Jul 09 06:59:03 PM PDT 24 Jul 09 06:59:07 PM PDT 24 184981313 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.229940081 Jul 09 06:59:21 PM PDT 24 Jul 09 06:59:25 PM PDT 24 86556784 ps
T940 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.49962139 Jul 09 06:59:11 PM PDT 24 Jul 09 06:59:15 PM PDT 24 14020120 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1705184210 Jul 09 06:59:00 PM PDT 24 Jul 09 06:59:03 PM PDT 24 89439557 ps
T942 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1557577842 Jul 09 06:59:28 PM PDT 24 Jul 09 06:59:30 PM PDT 24 199463476 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.898853163 Jul 09 06:59:11 PM PDT 24 Jul 09 06:59:16 PM PDT 24 398142711 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3510371366 Jul 09 06:59:06 PM PDT 24 Jul 09 06:59:09 PM PDT 24 99371992 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2338017860 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:20 PM PDT 24 74815261 ps
T199 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.927765616 Jul 09 06:59:35 PM PDT 24 Jul 09 06:59:38 PM PDT 24 22374472 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.744641854 Jul 09 06:59:31 PM PDT 24 Jul 09 06:59:33 PM PDT 24 44875131 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1539652291 Jul 09 06:59:31 PM PDT 24 Jul 09 06:59:34 PM PDT 24 38946943 ps
T948 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4177750331 Jul 09 06:59:22 PM PDT 24 Jul 09 06:59:26 PM PDT 24 156270084 ps
T949 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3778885404 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:13 PM PDT 24 141767783 ps
T950 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3735088447 Jul 09 06:59:35 PM PDT 24 Jul 09 06:59:38 PM PDT 24 193853151 ps
T951 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3826952730 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:19 PM PDT 24 37547469 ps
T952 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2253519972 Jul 09 06:59:16 PM PDT 24 Jul 09 06:59:58 PM PDT 24 1811179685 ps
T953 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1534400153 Jul 09 06:59:35 PM PDT 24 Jul 09 06:59:41 PM PDT 24 413935370 ps
T200 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3934479950 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:36 PM PDT 24 70958328 ps
T954 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1162090408 Jul 09 06:59:29 PM PDT 24 Jul 09 06:59:46 PM PDT 24 2721245760 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2001514463 Jul 09 06:59:03 PM PDT 24 Jul 09 06:59:06 PM PDT 24 11833523 ps
T956 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3113564165 Jul 09 06:59:38 PM PDT 24 Jul 09 06:59:41 PM PDT 24 21901021 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3431860023 Jul 09 06:59:21 PM PDT 24 Jul 09 06:59:28 PM PDT 24 280611198 ps
T958 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3190161495 Jul 09 06:59:31 PM PDT 24 Jul 09 06:59:37 PM PDT 24 124774848 ps
T959 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1693884202 Jul 09 06:59:11 PM PDT 24 Jul 09 06:59:15 PM PDT 24 34351840 ps
T960 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1127259063 Jul 09 06:59:02 PM PDT 24 Jul 09 06:59:07 PM PDT 24 1049208060 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.593069490 Jul 09 06:59:17 PM PDT 24 Jul 09 06:59:23 PM PDT 24 509556916 ps
T201 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3749253877 Jul 09 06:59:18 PM PDT 24 Jul 09 06:59:23 PM PDT 24 33134077 ps
T130 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1764673137 Jul 09 06:59:32 PM PDT 24 Jul 09 06:59:36 PM PDT 24 136246776 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2119491552 Jul 09 06:59:11 PM PDT 24 Jul 09 06:59:21 PM PDT 24 891231313 ps
T963 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3388967697 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:35 PM PDT 24 14408819 ps
T203 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2171842944 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:11 PM PDT 24 88145510 ps
T964 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3320745225 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:19 PM PDT 24 26425019 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3155255259 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:18 PM PDT 24 26163601 ps
T966 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2963595973 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:17 PM PDT 24 39437617 ps
T967 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4165760247 Jul 09 06:59:08 PM PDT 24 Jul 09 06:59:16 PM PDT 24 1430937090 ps
T968 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.40314071 Jul 09 06:59:38 PM PDT 24 Jul 09 06:59:42 PM PDT 24 45748151 ps
T969 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3398194647 Jul 09 06:59:18 PM PDT 24 Jul 09 06:59:26 PM PDT 24 701228877 ps
T970 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.268076845 Jul 09 06:59:34 PM PDT 24 Jul 09 06:59:37 PM PDT 24 113824142 ps
T204 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2716643400 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:11 PM PDT 24 72513625 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3170299805 Jul 09 06:59:07 PM PDT 24 Jul 09 06:59:10 PM PDT 24 58199056 ps
T972 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2125546368 Jul 09 06:59:32 PM PDT 24 Jul 09 06:59:35 PM PDT 24 76448682 ps
T973 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.857988031 Jul 09 06:59:34 PM PDT 24 Jul 09 06:59:38 PM PDT 24 38814249 ps
T974 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3635936681 Jul 09 06:59:12 PM PDT 24 Jul 09 06:59:17 PM PDT 24 691647819 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1249420756 Jul 09 06:59:15 PM PDT 24 Jul 09 06:59:22 PM PDT 24 132804779 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1410785037 Jul 09 06:59:03 PM PDT 24 Jul 09 06:59:05 PM PDT 24 23384590 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1060787744 Jul 09 06:59:14 PM PDT 24 Jul 09 06:59:20 PM PDT 24 22547037 ps
T205 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1505187934 Jul 09 06:59:22 PM PDT 24 Jul 09 06:59:25 PM PDT 24 16822208 ps
T978 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.838244015 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:27 PM PDT 24 5929759764 ps
T979 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3437133384 Jul 09 06:59:29 PM PDT 24 Jul 09 06:59:31 PM PDT 24 25797479 ps
T980 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3701522060 Jul 09 06:59:16 PM PDT 24 Jul 09 06:59:22 PM PDT 24 56354517 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2535804631 Jul 09 06:59:18 PM PDT 24 Jul 09 06:59:26 PM PDT 24 639542089 ps
T117 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.269103122 Jul 09 06:59:27 PM PDT 24 Jul 09 06:59:31 PM PDT 24 394967304 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3182165229 Jul 09 06:59:25 PM PDT 24 Jul 09 06:59:28 PM PDT 24 185013888 ps
T983 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2867947629 Jul 09 06:59:01 PM PDT 24 Jul 09 06:59:04 PM PDT 24 1069483074 ps
T984 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2630682800 Jul 09 06:59:27 PM PDT 24 Jul 09 06:59:28 PM PDT 24 17083848 ps
T985 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.434037860 Jul 09 06:59:36 PM PDT 24 Jul 09 06:59:40 PM PDT 24 57155282 ps
T986 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.453883316 Jul 09 06:59:38 PM PDT 24 Jul 09 06:59:42 PM PDT 24 26355106 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2166246687 Jul 09 06:59:18 PM PDT 24 Jul 09 06:59:23 PM PDT 24 51358324 ps
T988 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1161173263 Jul 09 06:59:13 PM PDT 24 Jul 09 06:59:17 PM PDT 24 23593346 ps
T989 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2597565167 Jul 09 06:59:12 PM PDT 24 Jul 09 06:59:18 PM PDT 24 152603326 ps
T990 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.883412439 Jul 09 06:59:22 PM PDT 24 Jul 09 06:59:34 PM PDT 24 2149272735 ps
T206 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3153921415 Jul 09 06:59:32 PM PDT 24 Jul 09 06:59:34 PM PDT 24 50698613 ps
T991 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.853980247 Jul 09 06:59:01 PM PDT 24 Jul 09 06:59:05 PM PDT 24 121036429 ps
T992 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1419244509 Jul 09 06:59:33 PM PDT 24 Jul 09 06:59:36 PM PDT 24 27141349 ps

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1466165990
Short name T11
Test name
Test status
Simulation time 16328163365 ps
CPU time 227.55 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 264596 kb
Host smart-d5aae5c8-8cc8-42a4-9baa-a390c0afbd83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466165990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1466165990
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2091778742
Short name T51
Test name
Test status
Simulation time 425802406 ps
CPU time 11 seconds
Started Jul 09 05:26:08 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 218328 kb
Host smart-8b769884-b2fc-4320-a7be-946e67f40a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091778742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2091778742
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3612222670
Short name T16
Test name
Test status
Simulation time 10684742443 ps
CPU time 231.68 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:30:10 PM PDT 24
Peak memory 283704 kb
Host smart-db02239b-c953-45cd-96d7-1e659924e72a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612222670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3612222670
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3913057765
Short name T62
Test name
Test status
Simulation time 416708708 ps
CPU time 9.42 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:25:56 PM PDT 24
Peak memory 218844 kb
Host smart-d88d40ab-bb2a-4792-ad1d-f34037594db6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913057765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3913057765
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4001481044
Short name T109
Test name
Test status
Simulation time 1243918163 ps
CPU time 6.39 seconds
Started Jul 09 06:59:19 PM PDT 24
Finished Jul 09 06:59:29 PM PDT 24
Peak memory 218720 kb
Host smart-8e71ea63-0e2b-4d49-849f-c6f2fce3caed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400148
1044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4001481044
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1666217978
Short name T54
Test name
Test status
Simulation time 209663456 ps
CPU time 26.66 seconds
Started Jul 09 05:25:27 PM PDT 24
Finished Jul 09 05:25:55 PM PDT 24
Peak memory 269832 kb
Host smart-adf1c598-b19f-4706-8e34-397e5664a61f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666217978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1666217978
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3283446439
Short name T13
Test name
Test status
Simulation time 1356785313 ps
CPU time 8.87 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:27:00 PM PDT 24
Peak memory 218172 kb
Host smart-eb81d938-ac4d-4fab-ad95-abeac5a9204b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283446439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3283446439
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1888041631
Short name T162
Test name
Test status
Simulation time 12126739710 ps
CPU time 248.6 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:29:56 PM PDT 24
Peak memory 275304 kb
Host smart-85aa8966-7e1b-467d-b779-880323694a33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1888041631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1888041631
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2238246035
Short name T12
Test name
Test status
Simulation time 9929564960 ps
CPU time 186.33 seconds
Started Jul 09 05:25:38 PM PDT 24
Finished Jul 09 05:28:45 PM PDT 24
Peak memory 299968 kb
Host smart-2c10cdb1-c5a2-40b4-a452-a2e97a91c5f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238246035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2238246035
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2713028637
Short name T106
Test name
Test status
Simulation time 202001000 ps
CPU time 1.96 seconds
Started Jul 09 06:59:34 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 222084 kb
Host smart-b291cdee-7dcd-46d1-971d-b2d9ab0ff2d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713028637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2713028637
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.63350872
Short name T49
Test name
Test status
Simulation time 382631251 ps
CPU time 10.9 seconds
Started Jul 09 05:27:10 PM PDT 24
Finished Jul 09 05:27:22 PM PDT 24
Peak memory 218216 kb
Host smart-8ff46e86-42e6-49d5-98aa-91a33e1f116f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63350872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.63350872
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3622211991
Short name T5
Test name
Test status
Simulation time 2502581518 ps
CPU time 4.43 seconds
Started Jul 09 05:25:54 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 217628 kb
Host smart-899f5f51-312e-4a56-9111-7bacfdc68c52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622211991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3622211991
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.927765616
Short name T199
Test name
Test status
Simulation time 22374472 ps
CPU time 0.85 seconds
Started Jul 09 06:59:35 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 209284 kb
Host smart-20a50769-828e-47ea-a494-2af4db9d3c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927765616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.927765616
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.429768237
Short name T60
Test name
Test status
Simulation time 33335299706 ps
CPU time 1276.37 seconds
Started Jul 09 05:27:10 PM PDT 24
Finished Jul 09 05:48:27 PM PDT 24
Peak memory 422040 kb
Host smart-64e1ccd8-a9ee-4937-a855-ba7ea5751ab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=429768237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.429768237
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3297730994
Short name T92
Test name
Test status
Simulation time 210742054 ps
CPU time 1.21 seconds
Started Jul 09 05:26:50 PM PDT 24
Finished Jul 09 05:26:53 PM PDT 24
Peak memory 208852 kb
Host smart-e2076dd7-3d68-4385-8e4a-ab3b97a6c742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297730994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3297730994
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.64467132
Short name T108
Test name
Test status
Simulation time 399117274 ps
CPU time 3.12 seconds
Started Jul 09 06:59:30 PM PDT 24
Finished Jul 09 06:59:34 PM PDT 24
Peak memory 222464 kb
Host smart-308d5991-a5a7-4333-99b9-fd2fb194a5ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64467132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_er
r.64467132
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1837363534
Short name T73
Test name
Test status
Simulation time 723501143 ps
CPU time 3.35 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 226148 kb
Host smart-a705ea7b-9572-479e-bd64-97d3aa061aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837363534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1837363534
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1148356486
Short name T116
Test name
Test status
Simulation time 209185811 ps
CPU time 4.09 seconds
Started Jul 09 06:59:05 PM PDT 24
Finished Jul 09 06:59:10 PM PDT 24
Peak memory 217560 kb
Host smart-7df0f7ae-2762-4297-9576-828a9cd8149a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148356486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1148356486
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3205106798
Short name T903
Test name
Test status
Simulation time 163571921 ps
CPU time 3.8 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:44 PM PDT 24
Peak memory 217500 kb
Host smart-c49aa323-4a1a-4b4c-8a67-386a8331d4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205106798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3205106798
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2924554521
Short name T390
Test name
Test status
Simulation time 8495849343 ps
CPU time 60.54 seconds
Started Jul 09 05:26:05 PM PDT 24
Finished Jul 09 05:27:06 PM PDT 24
Peak memory 218248 kb
Host smart-129a7156-2eeb-4fef-8a38-a9da8a90fd25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924554521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2924554521
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2380424487
Short name T132
Test name
Test status
Simulation time 84353058 ps
CPU time 2.92 seconds
Started Jul 09 06:59:16 PM PDT 24
Finished Jul 09 06:59:23 PM PDT 24
Peak memory 213316 kb
Host smart-7077efe4-48f0-4e4b-bf1f-ef6a4e5fa880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380424487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2380424487
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3354571201
Short name T103
Test name
Test status
Simulation time 378208425 ps
CPU time 14.26 seconds
Started Jul 09 05:25:29 PM PDT 24
Finished Jul 09 05:25:44 PM PDT 24
Peak memory 218300 kb
Host smart-15997706-74bb-472c-a0b6-7a96f417a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354571201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3354571201
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.765922659
Short name T43
Test name
Test status
Simulation time 626473909 ps
CPU time 15.03 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:26:02 PM PDT 24
Peak memory 218184 kb
Host smart-7b8505fc-3f31-47f3-8754-64bbf225bb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765922659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.765922659
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3037720128
Short name T59
Test name
Test status
Simulation time 5738075112 ps
CPU time 88.06 seconds
Started Jul 09 05:26:48 PM PDT 24
Finished Jul 09 05:28:17 PM PDT 24
Peak memory 276076 kb
Host smart-057c454a-a84b-40b4-8e6a-f8b5883a2851
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037720128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3037720128
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1496643211
Short name T10
Test name
Test status
Simulation time 66500331 ps
CPU time 8.18 seconds
Started Jul 09 05:25:57 PM PDT 24
Finished Jul 09 05:26:07 PM PDT 24
Peak memory 250892 kb
Host smart-2480219a-e708-4425-be35-9cf784437b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496643211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1496643211
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.771240130
Short name T152
Test name
Test status
Simulation time 43575252 ps
CPU time 1.31 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:35 PM PDT 24
Peak memory 217740 kb
Host smart-f71d435e-971b-4636-94a4-14eb40ed64a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771240130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.771240130
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.269103122
Short name T117
Test name
Test status
Simulation time 394967304 ps
CPU time 2.68 seconds
Started Jul 09 06:59:27 PM PDT 24
Finished Jul 09 06:59:31 PM PDT 24
Peak memory 221944 kb
Host smart-bcbfce83-c999-4904-89ce-17a3755521f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269103122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.269103122
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2137637477
Short name T129
Test name
Test status
Simulation time 721168282 ps
CPU time 5.51 seconds
Started Jul 09 06:59:28 PM PDT 24
Finished Jul 09 06:59:35 PM PDT 24
Peak memory 217552 kb
Host smart-ebf400b2-c7d8-4f6f-a3ef-55d379135d55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137637477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2137637477
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1909091382
Short name T126
Test name
Test status
Simulation time 128330672 ps
CPU time 3.83 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 217552 kb
Host smart-c2b925b1-d328-4350-b0e5-b2320da9d01d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909091382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1909091382
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.809918061
Short name T123
Test name
Test status
Simulation time 468289677 ps
CPU time 4.01 seconds
Started Jul 09 06:59:16 PM PDT 24
Finished Jul 09 06:59:24 PM PDT 24
Peak memory 217544 kb
Host smart-b8197281-2929-4ad2-a728-d2a903779ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809918061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.809918061
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3919385874
Short name T127
Test name
Test status
Simulation time 328818441 ps
CPU time 2.52 seconds
Started Jul 09 06:59:26 PM PDT 24
Finished Jul 09 06:59:30 PM PDT 24
Peak memory 217568 kb
Host smart-a485d34e-e16d-4bc6-838c-34c6147a83f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919385874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3919385874
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.4022834346
Short name T221
Test name
Test status
Simulation time 32484447 ps
CPU time 0.87 seconds
Started Jul 09 05:25:26 PM PDT 24
Finished Jul 09 05:25:28 PM PDT 24
Peak memory 208884 kb
Host smart-ca818944-01a0-4bea-925a-b681ee71bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022834346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4022834346
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2841144507
Short name T217
Test name
Test status
Simulation time 18099446 ps
CPU time 0.91 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:25:30 PM PDT 24
Peak memory 208896 kb
Host smart-49d4e4e2-ed2c-4d5b-aafd-2978b46f5301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841144507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2841144507
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1758598455
Short name T250
Test name
Test status
Simulation time 35981623 ps
CPU time 0.85 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:26:13 PM PDT 24
Peak memory 211852 kb
Host smart-6f28099a-cdb6-4087-8f7a-770dcc7a8b31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758598455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1758598455
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1246206991
Short name T78
Test name
Test status
Simulation time 13078063 ps
CPU time 0.88 seconds
Started Jul 09 05:25:49 PM PDT 24
Finished Jul 09 05:25:52 PM PDT 24
Peak memory 208784 kb
Host smart-196dab7d-8aed-48e7-b83e-24e818fe80ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246206991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1246206991
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2899470860
Short name T219
Test name
Test status
Simulation time 11578955 ps
CPU time 1 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:25:48 PM PDT 24
Peak memory 208820 kb
Host smart-a0525808-ef66-435e-99d6-062995219757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899470860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2899470860
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.479933665
Short name T888
Test name
Test status
Simulation time 660516704 ps
CPU time 6.44 seconds
Started Jul 09 06:59:03 PM PDT 24
Finished Jul 09 06:59:10 PM PDT 24
Peak memory 208960 kb
Host smart-6d267a5f-9a20-4d64-a7f8-c8491f8b74d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479933665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.479933665
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1764673137
Short name T130
Test name
Test status
Simulation time 136246776 ps
CPU time 2.6 seconds
Started Jul 09 06:59:32 PM PDT 24
Finished Jul 09 06:59:36 PM PDT 24
Peak memory 222288 kb
Host smart-30e0e3ad-2f72-49ba-b06a-e7571c672860
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764673137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1764673137
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.739061116
Short name T128
Test name
Test status
Simulation time 205089949 ps
CPU time 3.03 seconds
Started Jul 09 06:59:06 PM PDT 24
Finished Jul 09 06:59:10 PM PDT 24
Peak memory 222548 kb
Host smart-29198e51-2c16-40d9-8bb9-47057ebc4e77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739061116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.739061116
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3005426449
Short name T107
Test name
Test status
Simulation time 621276951 ps
CPU time 4.4 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:22 PM PDT 24
Peak memory 217596 kb
Host smart-57bd01f5-11a4-462d-a4b7-0b3cf6c1c30b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005426449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3005426449
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1386708716
Short name T45
Test name
Test status
Simulation time 53036970228 ps
CPU time 2061.12 seconds
Started Jul 09 05:27:14 PM PDT 24
Finished Jul 09 06:01:37 PM PDT 24
Peak memory 693448 kb
Host smart-6d989352-d88e-4118-a018-93775ff6305b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1386708716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1386708716
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2718964384
Short name T47
Test name
Test status
Simulation time 287876259 ps
CPU time 7.28 seconds
Started Jul 09 05:26:42 PM PDT 24
Finished Jul 09 05:26:50 PM PDT 24
Peak memory 218100 kb
Host smart-a1ae1087-fac7-4c02-a951-5cfefe55e4d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718964384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2718964384
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3097096160
Short name T233
Test name
Test status
Simulation time 1901512566 ps
CPU time 50.79 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:27:02 PM PDT 24
Peak memory 276064 kb
Host smart-5290e851-c971-41da-a3e0-1371ad9fe46c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097096160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3097096160
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1005096268
Short name T2
Test name
Test status
Simulation time 1485858360 ps
CPU time 6.24 seconds
Started Jul 09 05:26:00 PM PDT 24
Finished Jul 09 05:26:07 PM PDT 24
Peak memory 218192 kb
Host smart-1e77de9d-8218-4175-ad44-600421ef9c10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005096268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1005096268
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3633497779
Short name T198
Test name
Test status
Simulation time 14071678 ps
CPU time 1.13 seconds
Started Jul 09 06:59:02 PM PDT 24
Finished Jul 09 06:59:04 PM PDT 24
Peak memory 209408 kb
Host smart-bea67f8d-24b5-43c5-9bd1-2f86e33fcf43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633497779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3633497779
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3987819946
Short name T869
Test name
Test status
Simulation time 22156478 ps
CPU time 1.45 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:10 PM PDT 24
Peak memory 209300 kb
Host smart-37655be5-f275-4f9f-90fd-8e82eb61a8fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987819946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3987819946
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2788301046
Short name T195
Test name
Test status
Simulation time 11760922 ps
CPU time 0.85 seconds
Started Jul 09 06:59:01 PM PDT 24
Finished Jul 09 06:59:03 PM PDT 24
Peak memory 209220 kb
Host smart-2943d775-c2ae-4644-81f3-76f17ec9500a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788301046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2788301046
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2963595973
Short name T966
Test name
Test status
Simulation time 39437617 ps
CPU time 1.24 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:17 PM PDT 24
Peak memory 218480 kb
Host smart-4c83f7bb-b31d-4d58-a368-0cb30e01409e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963595973 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2963595973
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2001514463
Short name T955
Test name
Test status
Simulation time 11833523 ps
CPU time 0.91 seconds
Started Jul 09 06:59:03 PM PDT 24
Finished Jul 09 06:59:06 PM PDT 24
Peak memory 209256 kb
Host smart-25727b40-43cf-4cad-9b1f-a9024be155c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001514463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2001514463
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3878530846
Short name T923
Test name
Test status
Simulation time 220746389 ps
CPU time 1.83 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:18 PM PDT 24
Peak memory 209192 kb
Host smart-feea32e1-1831-4d8d-a7d3-b91a849c3729
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878530846 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3878530846
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1828327947
Short name T873
Test name
Test status
Simulation time 3180274855 ps
CPU time 9.15 seconds
Started Jul 09 06:59:04 PM PDT 24
Finished Jul 09 06:59:15 PM PDT 24
Peak memory 209308 kb
Host smart-d09ae0ca-8220-4b59-9baf-c7de92b82eba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828327947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1828327947
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2506388674
Short name T907
Test name
Test status
Simulation time 957648696 ps
CPU time 3.07 seconds
Started Jul 09 06:59:05 PM PDT 24
Finished Jul 09 06:59:09 PM PDT 24
Peak memory 210944 kb
Host smart-6d8171d8-2e78-458f-8a12-b735599de8f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506388674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2506388674
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1127259063
Short name T960
Test name
Test status
Simulation time 1049208060 ps
CPU time 3.63 seconds
Started Jul 09 06:59:02 PM PDT 24
Finished Jul 09 06:59:07 PM PDT 24
Peak memory 219200 kb
Host smart-e6dee725-38ca-4c8c-b0c2-1a8a4d120613
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112725
9063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1127259063
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.853980247
Short name T991
Test name
Test status
Simulation time 121036429 ps
CPU time 2.12 seconds
Started Jul 09 06:59:01 PM PDT 24
Finished Jul 09 06:59:05 PM PDT 24
Peak memory 209288 kb
Host smart-753cc071-b9d8-4354-b678-77175ee23790
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853980247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.853980247
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.744491609
Short name T929
Test name
Test status
Simulation time 25789848 ps
CPU time 1.05 seconds
Started Jul 09 06:59:02 PM PDT 24
Finished Jul 09 06:59:04 PM PDT 24
Peak memory 217484 kb
Host smart-94394126-3457-4971-b6fe-1ea6f3268a4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744491609 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.744491609
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2213941616
Short name T886
Test name
Test status
Simulation time 71716663 ps
CPU time 1.18 seconds
Started Jul 09 06:59:03 PM PDT 24
Finished Jul 09 06:59:06 PM PDT 24
Peak memory 209144 kb
Host smart-f3b370de-b2a0-478b-94b6-29408ec4ab46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213941616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2213941616
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2920714785
Short name T897
Test name
Test status
Simulation time 32296644 ps
CPU time 1.77 seconds
Started Jul 09 06:59:02 PM PDT 24
Finished Jul 09 06:59:05 PM PDT 24
Peak memory 217496 kb
Host smart-4b2ea03f-b67c-4778-b7bb-4bf9adcfd91a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920714785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2920714785
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.650557464
Short name T133
Test name
Test status
Simulation time 117989966 ps
CPU time 3.33 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:12 PM PDT 24
Peak memory 222568 kb
Host smart-cc621cd9-6091-4de9-b099-5ee4ff217f89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650557464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.650557464
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1335494666
Short name T867
Test name
Test status
Simulation time 57059949 ps
CPU time 0.99 seconds
Started Jul 09 06:59:00 PM PDT 24
Finished Jul 09 06:59:02 PM PDT 24
Peak memory 209224 kb
Host smart-d26d335e-244a-4a34-8437-59963bbd1a96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335494666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1335494666
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1666162353
Short name T889
Test name
Test status
Simulation time 49290643 ps
CPU time 1.79 seconds
Started Jul 09 06:59:03 PM PDT 24
Finished Jul 09 06:59:06 PM PDT 24
Peak memory 209288 kb
Host smart-52519677-fecb-4fb1-becd-59d0d01bcffe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666162353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1666162353
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1828878120
Short name T879
Test name
Test status
Simulation time 25533720 ps
CPU time 1.08 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:17 PM PDT 24
Peak memory 211288 kb
Host smart-7f213b0e-0e9e-42f7-8827-d3c83d9cf554
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828878120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1828878120
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1410785037
Short name T976
Test name
Test status
Simulation time 23384590 ps
CPU time 1.11 seconds
Started Jul 09 06:59:03 PM PDT 24
Finished Jul 09 06:59:05 PM PDT 24
Peak memory 218760 kb
Host smart-60eeb157-a63f-41ab-9324-f495edf2015f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410785037 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1410785037
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1161173263
Short name T988
Test name
Test status
Simulation time 23593346 ps
CPU time 0.83 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:17 PM PDT 24
Peak memory 209108 kb
Host smart-eebd5a76-f51a-4cdb-87d4-1eca19cb1d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161173263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1161173263
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1705184210
Short name T941
Test name
Test status
Simulation time 89439557 ps
CPU time 1.37 seconds
Started Jul 09 06:59:00 PM PDT 24
Finished Jul 09 06:59:03 PM PDT 24
Peak memory 209184 kb
Host smart-656e5379-374f-48c5-a858-c2a150e8d9e3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705184210 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1705184210
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3169671472
Short name T113
Test name
Test status
Simulation time 495263332 ps
CPU time 3.2 seconds
Started Jul 09 06:59:05 PM PDT 24
Finished Jul 09 06:59:10 PM PDT 24
Peak memory 209068 kb
Host smart-e4d62b96-5235-4440-8f2a-e1d5419fbecc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169671472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3169671472
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2114949772
Short name T139
Test name
Test status
Simulation time 771010071 ps
CPU time 12.32 seconds
Started Jul 09 06:59:12 PM PDT 24
Finished Jul 09 06:59:28 PM PDT 24
Peak memory 217144 kb
Host smart-0a4e64e4-5c8c-4235-9a99-8cc382fcb5f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114949772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2114949772
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1544545545
Short name T938
Test name
Test status
Simulation time 184981313 ps
CPU time 2.92 seconds
Started Jul 09 06:59:03 PM PDT 24
Finished Jul 09 06:59:07 PM PDT 24
Peak memory 217492 kb
Host smart-3001675b-a74b-4d2b-86bb-8cc9d3be5710
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544545545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1544545545
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.602970606
Short name T896
Test name
Test status
Simulation time 51615087 ps
CPU time 2.21 seconds
Started Jul 09 06:59:05 PM PDT 24
Finished Jul 09 06:59:09 PM PDT 24
Peak memory 217636 kb
Host smart-06602cc4-1a57-485e-9ef4-e254de7a8633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602970
606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.602970606
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2867947629
Short name T983
Test name
Test status
Simulation time 1069483074 ps
CPU time 2.53 seconds
Started Jul 09 06:59:01 PM PDT 24
Finished Jul 09 06:59:04 PM PDT 24
Peak memory 209280 kb
Host smart-9fe5542f-5fee-4503-ae51-ffaa0515eb1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867947629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2867947629
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.61565073
Short name T906
Test name
Test status
Simulation time 21014125 ps
CPU time 1.5 seconds
Started Jul 09 06:59:06 PM PDT 24
Finished Jul 09 06:59:08 PM PDT 24
Peak memory 217576 kb
Host smart-7c9def20-6ea3-4952-b2b0-d6ef078bf8c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61565073 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.61565073
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3557236184
Short name T935
Test name
Test status
Simulation time 51783879 ps
CPU time 1.39 seconds
Started Jul 09 06:59:02 PM PDT 24
Finished Jul 09 06:59:04 PM PDT 24
Peak memory 209384 kb
Host smart-fcc7fec6-0864-45c1-99db-7f7da6605e32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557236184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3557236184
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2597565167
Short name T989
Test name
Test status
Simulation time 152603326 ps
CPU time 2.37 seconds
Started Jul 09 06:59:12 PM PDT 24
Finished Jul 09 06:59:18 PM PDT 24
Peak memory 217488 kb
Host smart-0c55d919-7bbf-4044-83f0-66b43ea9f5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597565167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2597565167
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.229848681
Short name T884
Test name
Test status
Simulation time 21721579 ps
CPU time 1.74 seconds
Started Jul 09 06:59:28 PM PDT 24
Finished Jul 09 06:59:30 PM PDT 24
Peak memory 217736 kb
Host smart-01ba5db4-2aa0-4f59-a020-9725fd05b07d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229848681 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.229848681
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3437133384
Short name T979
Test name
Test status
Simulation time 25797479 ps
CPU time 0.89 seconds
Started Jul 09 06:59:29 PM PDT 24
Finished Jul 09 06:59:31 PM PDT 24
Peak memory 209360 kb
Host smart-3790bfbc-fd18-4524-b976-772492be1253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437133384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3437133384
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2630682800
Short name T984
Test name
Test status
Simulation time 17083848 ps
CPU time 1.01 seconds
Started Jul 09 06:59:27 PM PDT 24
Finished Jul 09 06:59:28 PM PDT 24
Peak memory 209324 kb
Host smart-1f68095e-ed59-4161-ab3b-ebf89befc5c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630682800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2630682800
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3683891466
Short name T924
Test name
Test status
Simulation time 279489639 ps
CPU time 2.1 seconds
Started Jul 09 06:59:26 PM PDT 24
Finished Jul 09 06:59:29 PM PDT 24
Peak memory 217516 kb
Host smart-87331cab-e846-4970-b0a6-e0b909e2f708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683891466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3683891466
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3437151812
Short name T895
Test name
Test status
Simulation time 31725565 ps
CPU time 1.86 seconds
Started Jul 09 06:59:32 PM PDT 24
Finished Jul 09 06:59:35 PM PDT 24
Peak memory 217612 kb
Host smart-8148e1ff-71b3-4c66-ae6c-0e392c8d2290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437151812 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3437151812
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3388967697
Short name T963
Test name
Test status
Simulation time 14408819 ps
CPU time 0.84 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:35 PM PDT 24
Peak memory 209356 kb
Host smart-b0530ace-e49d-475d-a71e-e37bbec60149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388967697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3388967697
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1269055218
Short name T912
Test name
Test status
Simulation time 72352957 ps
CPU time 1.03 seconds
Started Jul 09 06:59:35 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 209296 kb
Host smart-32e459d8-8307-43aa-a725-5a6dfb3c2807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269055218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1269055218
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4262975990
Short name T105
Test name
Test status
Simulation time 56588345 ps
CPU time 2.2 seconds
Started Jul 09 06:59:30 PM PDT 24
Finished Jul 09 06:59:33 PM PDT 24
Peak memory 217952 kb
Host smart-4a2b1f29-2f6f-4e61-86ac-3f91c9bc9b60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262975990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4262975990
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2905472566
Short name T110
Test name
Test status
Simulation time 52178162 ps
CPU time 2.13 seconds
Started Jul 09 06:59:36 PM PDT 24
Finished Jul 09 06:59:39 PM PDT 24
Peak memory 225736 kb
Host smart-2c5cb59a-44a6-4b64-9e09-61a4b2cc07f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905472566 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2905472566
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3934479950
Short name T200
Test name
Test status
Simulation time 70958328 ps
CPU time 0.93 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:36 PM PDT 24
Peak memory 209232 kb
Host smart-2921a166-0a9b-4725-8dd0-245b4a1b30fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934479950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3934479950
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.857988031
Short name T973
Test name
Test status
Simulation time 38814249 ps
CPU time 1.89 seconds
Started Jul 09 06:59:34 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 217468 kb
Host smart-674f8e8c-c13a-4c70-92a6-55fd71cedce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857988031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.857988031
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.434037860
Short name T985
Test name
Test status
Simulation time 57155282 ps
CPU time 2.34 seconds
Started Jul 09 06:59:36 PM PDT 24
Finished Jul 09 06:59:40 PM PDT 24
Peak memory 217500 kb
Host smart-488479fe-383e-42e9-a7a8-d3645f05ea9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434037860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.434037860
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3551074197
Short name T932
Test name
Test status
Simulation time 123548586 ps
CPU time 1.37 seconds
Started Jul 09 06:59:31 PM PDT 24
Finished Jul 09 06:59:34 PM PDT 24
Peak memory 218572 kb
Host smart-92b6d288-e892-486a-89be-9b59effee8ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551074197 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3551074197
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3190161495
Short name T958
Test name
Test status
Simulation time 124774848 ps
CPU time 4.95 seconds
Started Jul 09 06:59:31 PM PDT 24
Finished Jul 09 06:59:37 PM PDT 24
Peak memory 217496 kb
Host smart-d402aac4-c3d4-4a9f-9c45-8350f4f2d697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190161495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3190161495
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.6270727
Short name T122
Test name
Test status
Simulation time 188224810 ps
CPU time 2.78 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 217528 kb
Host smart-c5229aa2-6386-4da4-9797-7ad4af91630c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6270727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_er
r.6270727
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.118882336
Short name T916
Test name
Test status
Simulation time 47807129 ps
CPU time 1.53 seconds
Started Jul 09 06:59:36 PM PDT 24
Finished Jul 09 06:59:40 PM PDT 24
Peak memory 219496 kb
Host smart-03f984b4-6e7b-4948-903b-aa3c972cdda2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118882336 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.118882336
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2338566561
Short name T197
Test name
Test status
Simulation time 13414475 ps
CPU time 0.92 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:35 PM PDT 24
Peak memory 209236 kb
Host smart-1478f6df-bcba-4335-9786-8b00fb0503fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338566561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2338566561
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3993729171
Short name T936
Test name
Test status
Simulation time 100576085 ps
CPU time 1.44 seconds
Started Jul 09 06:59:34 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 217748 kb
Host smart-f9c02386-af28-4406-b691-6e051a2092ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993729171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3993729171
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1377422135
Short name T920
Test name
Test status
Simulation time 2414462870 ps
CPU time 3.09 seconds
Started Jul 09 06:59:35 PM PDT 24
Finished Jul 09 06:59:40 PM PDT 24
Peak memory 217620 kb
Host smart-1d9bb778-d56d-49bc-919e-a5fb75f69ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377422135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1377422135
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.152483105
Short name T121
Test name
Test status
Simulation time 200315685 ps
CPU time 4.19 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:39 PM PDT 24
Peak memory 217620 kb
Host smart-9c0ee39e-3418-4aef-a285-847cd04fe18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152483105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.152483105
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3735088447
Short name T950
Test name
Test status
Simulation time 193853151 ps
CPU time 1.7 seconds
Started Jul 09 06:59:35 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 217764 kb
Host smart-006a9279-d960-44a2-8dcf-fc1a43d5b4fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735088447 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3735088447
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1847280928
Short name T930
Test name
Test status
Simulation time 24400826 ps
CPU time 1.06 seconds
Started Jul 09 06:59:36 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 208980 kb
Host smart-928ab65b-d03f-4f70-87a7-d672245b9db7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847280928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1847280928
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.531499821
Short name T208
Test name
Test status
Simulation time 40600362 ps
CPU time 1.28 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:35 PM PDT 24
Peak memory 209276 kb
Host smart-c11d84e2-0fc1-470b-abda-a02d3a957470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531499821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.531499821
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1214282939
Short name T887
Test name
Test status
Simulation time 66004145 ps
CPU time 1.54 seconds
Started Jul 09 06:59:34 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 217412 kb
Host smart-62a224a8-cdc8-4153-b938-8176f1a0f11b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214282939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1214282939
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.21122438
Short name T124
Test name
Test status
Simulation time 221925840 ps
CPU time 3.08 seconds
Started Jul 09 06:59:32 PM PDT 24
Finished Jul 09 06:59:37 PM PDT 24
Peak memory 222260 kb
Host smart-5da4d7a0-d8a6-4b8c-8403-4e0dd417fbbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21122438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_e
rr.21122438
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1419244509
Short name T992
Test name
Test status
Simulation time 27141349 ps
CPU time 1.47 seconds
Started Jul 09 06:59:33 PM PDT 24
Finished Jul 09 06:59:36 PM PDT 24
Peak memory 217724 kb
Host smart-9f12a35c-a1db-4df5-9ace-5a3da6b095e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419244509 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1419244509
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3153921415
Short name T206
Test name
Test status
Simulation time 50698613 ps
CPU time 0.91 seconds
Started Jul 09 06:59:32 PM PDT 24
Finished Jul 09 06:59:34 PM PDT 24
Peak memory 209348 kb
Host smart-575b155a-22aa-4b48-b438-214160087904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153921415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3153921415
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2044218434
Short name T919
Test name
Test status
Simulation time 74813506 ps
CPU time 1.74 seconds
Started Jul 09 06:59:35 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 209300 kb
Host smart-5d3085e8-ae4f-4b7f-b91c-69b756539e27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044218434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2044218434
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2125546368
Short name T972
Test name
Test status
Simulation time 76448682 ps
CPU time 1.7 seconds
Started Jul 09 06:59:32 PM PDT 24
Finished Jul 09 06:59:35 PM PDT 24
Peak memory 218156 kb
Host smart-3d0e2053-906d-44dd-b861-1c9d1474d8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125546368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2125546368
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.236217588
Short name T933
Test name
Test status
Simulation time 74448974 ps
CPU time 2.24 seconds
Started Jul 09 06:59:34 PM PDT 24
Finished Jul 09 06:59:38 PM PDT 24
Peak memory 221792 kb
Host smart-b8254eb7-f25c-4b4d-beee-579418375b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236217588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.236217588
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.268076845
Short name T970
Test name
Test status
Simulation time 113824142 ps
CPU time 1.37 seconds
Started Jul 09 06:59:34 PM PDT 24
Finished Jul 09 06:59:37 PM PDT 24
Peak memory 219532 kb
Host smart-337d5e12-cfb6-42b9-b76d-886038557c42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268076845 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.268076845
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4047805666
Short name T868
Test name
Test status
Simulation time 21236895 ps
CPU time 1.05 seconds
Started Jul 09 06:59:34 PM PDT 24
Finished Jul 09 06:59:37 PM PDT 24
Peak memory 208996 kb
Host smart-e8fe33c9-59b6-4f90-a15f-789b5b7cc899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047805666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4047805666
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2634581061
Short name T211
Test name
Test status
Simulation time 28173159 ps
CPU time 1.44 seconds
Started Jul 09 06:59:31 PM PDT 24
Finished Jul 09 06:59:33 PM PDT 24
Peak memory 217544 kb
Host smart-e8bf5c9b-8041-4af8-93ae-d5de7e43d764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634581061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2634581061
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1893010677
Short name T876
Test name
Test status
Simulation time 60222495 ps
CPU time 2.09 seconds
Started Jul 09 06:59:36 PM PDT 24
Finished Jul 09 06:59:39 PM PDT 24
Peak memory 217488 kb
Host smart-1e45972c-e1cd-4629-915a-91ff8532813b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893010677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1893010677
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.453883316
Short name T986
Test name
Test status
Simulation time 26355106 ps
CPU time 2.03 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:42 PM PDT 24
Peak memory 223120 kb
Host smart-6c6bc08e-8a92-46fd-ab68-af0134728bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453883316 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.453883316
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3113564165
Short name T956
Test name
Test status
Simulation time 21901021 ps
CPU time 0.83 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:41 PM PDT 24
Peak memory 209168 kb
Host smart-47c834d6-9f13-4bff-ad10-1d62ee85834f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113564165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3113564165
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.40314071
Short name T968
Test name
Test status
Simulation time 45748151 ps
CPU time 2.11 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:42 PM PDT 24
Peak memory 217496 kb
Host smart-9bb1a32a-3677-4ec3-8f7b-4a794aaea4e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40314071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
same_csr_outstanding.40314071
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1534400153
Short name T953
Test name
Test status
Simulation time 413935370 ps
CPU time 4.3 seconds
Started Jul 09 06:59:35 PM PDT 24
Finished Jul 09 06:59:41 PM PDT 24
Peak memory 217556 kb
Host smart-05727daf-7363-4344-86fb-33b57efb92ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534400153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1534400153
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2942628267
Short name T893
Test name
Test status
Simulation time 96347705 ps
CPU time 1.58 seconds
Started Jul 09 06:59:38 PM PDT 24
Finished Jul 09 06:59:42 PM PDT 24
Peak memory 217744 kb
Host smart-cdc27d1d-c26c-4bfd-9f3c-6450ae27728a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942628267 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2942628267
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.458499289
Short name T890
Test name
Test status
Simulation time 13759856 ps
CPU time 0.97 seconds
Started Jul 09 06:59:37 PM PDT 24
Finished Jul 09 06:59:40 PM PDT 24
Peak memory 209312 kb
Host smart-8e5753fa-ebce-43a8-9940-6ddca032b240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458499289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.458499289
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.945483001
Short name T151
Test name
Test status
Simulation time 53509699 ps
CPU time 1.58 seconds
Started Jul 09 06:59:37 PM PDT 24
Finished Jul 09 06:59:41 PM PDT 24
Peak memory 209376 kb
Host smart-53065fc2-1820-4d18-9513-b466d63a9975
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945483001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.945483001
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3153972236
Short name T909
Test name
Test status
Simulation time 60646752 ps
CPU time 2.61 seconds
Started Jul 09 06:59:37 PM PDT 24
Finished Jul 09 06:59:42 PM PDT 24
Peak memory 217620 kb
Host smart-532b7b05-fe5c-4707-ac4d-c390a1e3ad43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153972236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3153972236
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2171842944
Short name T203
Test name
Test status
Simulation time 88145510 ps
CPU time 1.27 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:11 PM PDT 24
Peak memory 217656 kb
Host smart-f73cf802-78d5-4c9f-b817-4d0e15747b20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171842944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2171842944
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.512228243
Short name T901
Test name
Test status
Simulation time 73933112 ps
CPU time 1.28 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:11 PM PDT 24
Peak memory 217276 kb
Host smart-00077ae5-ae94-4ad0-b6f3-ea80495d85fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512228243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.512228243
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3486948248
Short name T874
Test name
Test status
Simulation time 78403772 ps
CPU time 1.05 seconds
Started Jul 09 06:59:09 PM PDT 24
Finished Jul 09 06:59:13 PM PDT 24
Peak memory 218128 kb
Host smart-255f6150-5207-4c42-bc56-6d81606bca7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486948248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3486948248
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3510371366
Short name T944
Test name
Test status
Simulation time 99371992 ps
CPU time 1.17 seconds
Started Jul 09 06:59:06 PM PDT 24
Finished Jul 09 06:59:09 PM PDT 24
Peak memory 218680 kb
Host smart-34f61916-84c5-4bde-8d6f-437710cb2414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510371366 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3510371366
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.676215009
Short name T112
Test name
Test status
Simulation time 75622990 ps
CPU time 0.79 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:09 PM PDT 24
Peak memory 209168 kb
Host smart-aa3c70ef-769c-4e75-b246-ff1711185c74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676215009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.676215009
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4179802096
Short name T872
Test name
Test status
Simulation time 613597387 ps
CPU time 1.78 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:11 PM PDT 24
Peak memory 209220 kb
Host smart-1843ebce-8575-4d85-a82b-b34ddf1cf981
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179802096 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4179802096
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4165760247
Short name T967
Test name
Test status
Simulation time 1430937090 ps
CPU time 4.62 seconds
Started Jul 09 06:59:08 PM PDT 24
Finished Jul 09 06:59:16 PM PDT 24
Peak memory 208952 kb
Host smart-c54e90ed-3468-4896-b175-e17a42851709
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165760247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4165760247
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.878113675
Short name T140
Test name
Test status
Simulation time 12461049535 ps
CPU time 50.13 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:59 PM PDT 24
Peak memory 209336 kb
Host smart-2fb0dcce-8143-44d3-a739-bf5312cb20d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878113675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.878113675
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.100340379
Short name T894
Test name
Test status
Simulation time 95148698 ps
CPU time 1.8 seconds
Started Jul 09 06:59:12 PM PDT 24
Finished Jul 09 06:59:17 PM PDT 24
Peak memory 210760 kb
Host smart-7eec496e-9eb7-4591-9a25-a034ce8243a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100340379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.100340379
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3568354912
Short name T134
Test name
Test status
Simulation time 505902299 ps
CPU time 2.06 seconds
Started Jul 09 06:59:08 PM PDT 24
Finished Jul 09 06:59:13 PM PDT 24
Peak memory 217636 kb
Host smart-05d0c181-5032-474e-8603-f213e49a7c01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356835
4912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3568354912
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3972817876
Short name T925
Test name
Test status
Simulation time 317251643 ps
CPU time 1.57 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:11 PM PDT 24
Peak memory 209216 kb
Host smart-b5064a50-19e8-4ee8-839c-830018fa3fe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972817876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3972817876
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4023705887
Short name T119
Test name
Test status
Simulation time 24475557 ps
CPU time 1.33 seconds
Started Jul 09 06:59:08 PM PDT 24
Finished Jul 09 06:59:12 PM PDT 24
Peak memory 211532 kb
Host smart-f838214c-8f01-4ce8-9047-175fe3ac8179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023705887 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4023705887
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3121807209
Short name T207
Test name
Test status
Simulation time 127223462 ps
CPU time 1.29 seconds
Started Jul 09 06:59:06 PM PDT 24
Finished Jul 09 06:59:09 PM PDT 24
Peak memory 209408 kb
Host smart-9365d31e-e227-47c5-912a-fd86978246c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121807209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3121807209
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3778885404
Short name T949
Test name
Test status
Simulation time 141767783 ps
CPU time 3.14 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:13 PM PDT 24
Peak memory 217544 kb
Host smart-3ef98471-5cce-458b-8ae1-07037ee72904
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778885404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3778885404
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.784441057
Short name T194
Test name
Test status
Simulation time 123658191 ps
CPU time 1.76 seconds
Started Jul 09 06:59:11 PM PDT 24
Finished Jul 09 06:59:16 PM PDT 24
Peak memory 209352 kb
Host smart-312ab705-18ba-4e82-90b8-ace4acb5a974
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784441057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.784441057
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3712572681
Short name T934
Test name
Test status
Simulation time 38614686 ps
CPU time 1.78 seconds
Started Jul 09 06:59:08 PM PDT 24
Finished Jul 09 06:59:13 PM PDT 24
Peak memory 209136 kb
Host smart-939d9db4-d9a6-4b75-86f0-3091b93e436f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712572681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3712572681
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2716643400
Short name T204
Test name
Test status
Simulation time 72513625 ps
CPU time 0.99 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:11 PM PDT 24
Peak memory 210452 kb
Host smart-61319d5c-1089-42aa-b342-f6b06d7d0edd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716643400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2716643400
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4008263715
Short name T880
Test name
Test status
Simulation time 75557257 ps
CPU time 1.25 seconds
Started Jul 09 06:59:12 PM PDT 24
Finished Jul 09 06:59:17 PM PDT 24
Peak memory 217692 kb
Host smart-5bf0332a-5561-46aa-947c-11045c5c5f6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008263715 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.4008263715
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3685142498
Short name T196
Test name
Test status
Simulation time 15952519 ps
CPU time 0.89 seconds
Started Jul 09 06:59:08 PM PDT 24
Finished Jul 09 06:59:11 PM PDT 24
Peak memory 209328 kb
Host smart-df308a93-1577-46b2-b04f-dc129838e724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685142498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3685142498
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1946117547
Short name T870
Test name
Test status
Simulation time 73537235 ps
CPU time 1.16 seconds
Started Jul 09 06:59:09 PM PDT 24
Finished Jul 09 06:59:13 PM PDT 24
Peak memory 208700 kb
Host smart-ae392e44-9af7-4a47-8d33-28cddcabc995
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946117547 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1946117547
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1493000522
Short name T881
Test name
Test status
Simulation time 833373739 ps
CPU time 5.7 seconds
Started Jul 09 06:59:08 PM PDT 24
Finished Jul 09 06:59:16 PM PDT 24
Peak memory 208624 kb
Host smart-50671ecb-3395-4482-9c23-b5b6632f3245
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493000522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1493000522
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1818431609
Short name T905
Test name
Test status
Simulation time 559671138 ps
CPU time 12.77 seconds
Started Jul 09 06:59:08 PM PDT 24
Finished Jul 09 06:59:24 PM PDT 24
Peak memory 209020 kb
Host smart-d003357e-f7d2-4979-85c3-7754d9ae0279
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818431609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1818431609
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1187590091
Short name T911
Test name
Test status
Simulation time 118891295 ps
CPU time 1.84 seconds
Started Jul 09 06:59:06 PM PDT 24
Finished Jul 09 06:59:10 PM PDT 24
Peak memory 217488 kb
Host smart-b660fb3c-420d-470e-a590-1a3ddfc5948c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187590091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1187590091
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3838166845
Short name T908
Test name
Test status
Simulation time 730665534 ps
CPU time 2.64 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:12 PM PDT 24
Peak memory 222152 kb
Host smart-6dd5cb76-f44e-450f-bb36-fffdd180c352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383816
6845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3838166845
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4191842473
Short name T917
Test name
Test status
Simulation time 45592683 ps
CPU time 1.19 seconds
Started Jul 09 06:59:09 PM PDT 24
Finished Jul 09 06:59:13 PM PDT 24
Peak memory 209144 kb
Host smart-6c11d19c-bee0-43e9-a1ce-1c8c9a3ef979
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191842473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4191842473
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3170299805
Short name T971
Test name
Test status
Simulation time 58199056 ps
CPU time 1.19 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:10 PM PDT 24
Peak memory 209356 kb
Host smart-7e40a3db-f99d-4fd1-bc81-c94dbc06d0eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170299805 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3170299805
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3668865420
Short name T209
Test name
Test status
Simulation time 80050722 ps
CPU time 1.27 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:18 PM PDT 24
Peak memory 209456 kb
Host smart-7f861af2-51da-46aa-9939-fdb6ae123398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668865420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3668865420
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3290545595
Short name T926
Test name
Test status
Simulation time 122244612 ps
CPU time 2 seconds
Started Jul 09 06:59:07 PM PDT 24
Finished Jul 09 06:59:11 PM PDT 24
Peak memory 217468 kb
Host smart-0bf8f668-6b4a-48df-8133-4aba8c78ead1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290545595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3290545595
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2384454242
Short name T120
Test name
Test status
Simulation time 330158544 ps
CPU time 3.55 seconds
Started Jul 09 06:59:08 PM PDT 24
Finished Jul 09 06:59:14 PM PDT 24
Peak memory 217556 kb
Host smart-2626e6ab-541e-4b22-9f11-07002197b2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384454242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2384454242
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1408583396
Short name T871
Test name
Test status
Simulation time 57999687 ps
CPU time 0.95 seconds
Started Jul 09 06:59:12 PM PDT 24
Finished Jul 09 06:59:15 PM PDT 24
Peak memory 209308 kb
Host smart-b0248bb6-0682-4462-9c40-a7d684435df8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408583396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1408583396
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.660890886
Short name T202
Test name
Test status
Simulation time 68985634 ps
CPU time 2.64 seconds
Started Jul 09 06:59:11 PM PDT 24
Finished Jul 09 06:59:17 PM PDT 24
Peak memory 209340 kb
Host smart-52e7c01f-cb66-4040-8426-0de9ca3bd86b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660890886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.660890886
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1693884202
Short name T959
Test name
Test status
Simulation time 34351840 ps
CPU time 1.12 seconds
Started Jul 09 06:59:11 PM PDT 24
Finished Jul 09 06:59:15 PM PDT 24
Peak memory 217552 kb
Host smart-9db97690-e526-4e94-8897-83d1d092359e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693884202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1693884202
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3155255259
Short name T965
Test name
Test status
Simulation time 26163601 ps
CPU time 1.84 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:18 PM PDT 24
Peak memory 217588 kb
Host smart-ed7380cc-8d80-48fc-96af-2d5b037b4858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155255259 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3155255259
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.200967353
Short name T865
Test name
Test status
Simulation time 48332227 ps
CPU time 0.81 seconds
Started Jul 09 06:59:11 PM PDT 24
Finished Jul 09 06:59:15 PM PDT 24
Peak memory 209264 kb
Host smart-d6dd5781-6d01-4875-87f0-05acbd9582cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200967353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.200967353
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3320745225
Short name T964
Test name
Test status
Simulation time 26425019 ps
CPU time 1.01 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:19 PM PDT 24
Peak memory 209192 kb
Host smart-c3d33b1c-e5cf-4d90-932b-11df7b943396
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320745225 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3320745225
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2119491552
Short name T962
Test name
Test status
Simulation time 891231313 ps
CPU time 6.51 seconds
Started Jul 09 06:59:11 PM PDT 24
Finished Jul 09 06:59:21 PM PDT 24
Peak memory 217140 kb
Host smart-47ab771c-5152-49ed-a6a4-02171389e737
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119491552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2119491552
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2108624638
Short name T927
Test name
Test status
Simulation time 421089736 ps
CPU time 10.56 seconds
Started Jul 09 06:59:11 PM PDT 24
Finished Jul 09 06:59:24 PM PDT 24
Peak memory 217088 kb
Host smart-6120f395-1e9a-4eff-8415-1962d912d1dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108624638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2108624638
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2338017860
Short name T945
Test name
Test status
Simulation time 74815261 ps
CPU time 1.49 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:20 PM PDT 24
Peak memory 217608 kb
Host smart-744da57a-1a2f-43ee-aa9e-b25f509e9fc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338017860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2338017860
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1176705791
Short name T877
Test name
Test status
Simulation time 300198754 ps
CPU time 3.44 seconds
Started Jul 09 06:59:12 PM PDT 24
Finished Jul 09 06:59:19 PM PDT 24
Peak memory 218708 kb
Host smart-cfab9ad3-cbb6-43f5-a04d-473a92f9facd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117670
5791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1176705791
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1813922450
Short name T883
Test name
Test status
Simulation time 871151711 ps
CPU time 1.91 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:19 PM PDT 24
Peak memory 209168 kb
Host smart-33c094e3-36d1-4391-972c-d45de1450946
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813922450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1813922450
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4162277335
Short name T210
Test name
Test status
Simulation time 36605391 ps
CPU time 1.39 seconds
Started Jul 09 06:59:10 PM PDT 24
Finished Jul 09 06:59:15 PM PDT 24
Peak memory 209336 kb
Host smart-b008a1da-c386-435c-9a18-e76310d4f133
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162277335 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4162277335
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1722185194
Short name T910
Test name
Test status
Simulation time 32076844 ps
CPU time 1.55 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:19 PM PDT 24
Peak memory 217524 kb
Host smart-efb8120e-f28c-4548-8b1d-cc2c183e241f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722185194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1722185194
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.622443390
Short name T115
Test name
Test status
Simulation time 303727557 ps
CPU time 3.12 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:19 PM PDT 24
Peak memory 217520 kb
Host smart-e8e0e481-95e6-4cb0-860a-d35c392a4591
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622443390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.622443390
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1060787744
Short name T977
Test name
Test status
Simulation time 22547037 ps
CPU time 1.39 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:20 PM PDT 24
Peak memory 219120 kb
Host smart-46538b34-884a-4ae2-a939-4de6ab3ae6e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060787744 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1060787744
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.49962139
Short name T940
Test name
Test status
Simulation time 14020120 ps
CPU time 1.01 seconds
Started Jul 09 06:59:11 PM PDT 24
Finished Jul 09 06:59:15 PM PDT 24
Peak memory 217696 kb
Host smart-b344c8f2-c905-4069-b925-5118ad4af63c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49962139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.49962139
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3635936681
Short name T974
Test name
Test status
Simulation time 691647819 ps
CPU time 1.22 seconds
Started Jul 09 06:59:12 PM PDT 24
Finished Jul 09 06:59:17 PM PDT 24
Peak memory 208676 kb
Host smart-a234304e-14e4-4954-9245-ecce4e1c396b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635936681 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3635936681
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3355875840
Short name T137
Test name
Test status
Simulation time 517191742 ps
CPU time 13.06 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:30 PM PDT 24
Peak memory 217136 kb
Host smart-c9e788c5-6e60-43da-ab6f-c5a6758e96bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355875840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3355875840
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2253519972
Short name T952
Test name
Test status
Simulation time 1811179685 ps
CPU time 37.65 seconds
Started Jul 09 06:59:16 PM PDT 24
Finished Jul 09 06:59:58 PM PDT 24
Peak memory 217160 kb
Host smart-d5169439-e683-4742-ac9d-6578c56b089e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253519972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2253519972
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3918539709
Short name T900
Test name
Test status
Simulation time 107757904 ps
CPU time 3.37 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:21 PM PDT 24
Peak memory 217480 kb
Host smart-8316fdd8-f959-4839-8d21-b0a8b33d3376
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918539709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3918539709
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.998361853
Short name T922
Test name
Test status
Simulation time 75856414 ps
CPU time 2.61 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:21 PM PDT 24
Peak memory 219120 kb
Host smart-63579e37-4b3f-44ac-bb7b-9686bf09fdd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998361
853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.998361853
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3826952730
Short name T951
Test name
Test status
Simulation time 37547469 ps
CPU time 1.59 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:19 PM PDT 24
Peak memory 217164 kb
Host smart-dd54d132-ebd3-4385-983d-5ec924cc9d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826952730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3826952730
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2200995245
Short name T878
Test name
Test status
Simulation time 47659651 ps
CPU time 0.98 seconds
Started Jul 09 06:59:12 PM PDT 24
Finished Jul 09 06:59:16 PM PDT 24
Peak memory 209084 kb
Host smart-99723dde-4081-438a-89b5-2980bf31cc46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200995245 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2200995245
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1096485223
Short name T914
Test name
Test status
Simulation time 21752647 ps
CPU time 1.19 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:19 PM PDT 24
Peak memory 211436 kb
Host smart-3ddcb5e9-2eff-4f5d-af3b-3de59bc318f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096485223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1096485223
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.898853163
Short name T943
Test name
Test status
Simulation time 398142711 ps
CPU time 1.51 seconds
Started Jul 09 06:59:11 PM PDT 24
Finished Jul 09 06:59:16 PM PDT 24
Peak memory 217560 kb
Host smart-f9d5397a-87f2-4c99-9860-2d469e7efd55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898853163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.898853163
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2166246687
Short name T987
Test name
Test status
Simulation time 51358324 ps
CPU time 1.21 seconds
Started Jul 09 06:59:18 PM PDT 24
Finished Jul 09 06:59:23 PM PDT 24
Peak memory 217528 kb
Host smart-6d8dc6ee-4b1e-4e3e-a723-d70203ffc99c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166246687 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2166246687
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3749253877
Short name T201
Test name
Test status
Simulation time 33134077 ps
CPU time 0.94 seconds
Started Jul 09 06:59:18 PM PDT 24
Finished Jul 09 06:59:23 PM PDT 24
Peak memory 209264 kb
Host smart-00d5c766-d8ad-43e6-8f41-91be0f10742b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749253877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3749253877
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3117960939
Short name T899
Test name
Test status
Simulation time 95215625 ps
CPU time 0.97 seconds
Started Jul 09 06:59:18 PM PDT 24
Finished Jul 09 06:59:23 PM PDT 24
Peak memory 208664 kb
Host smart-ff69842e-6809-4174-b474-be57b7c4fbd0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117960939 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3117960939
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2107153950
Short name T915
Test name
Test status
Simulation time 442312000 ps
CPU time 5.32 seconds
Started Jul 09 06:59:14 PM PDT 24
Finished Jul 09 06:59:23 PM PDT 24
Peak memory 209008 kb
Host smart-5a40271b-27ea-4f7b-997b-a1e3d5c1fca0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107153950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2107153950
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.838244015
Short name T978
Test name
Test status
Simulation time 5929759764 ps
CPU time 11.26 seconds
Started Jul 09 06:59:13 PM PDT 24
Finished Jul 09 06:59:27 PM PDT 24
Peak memory 209380 kb
Host smart-1edeff23-0447-44e2-b584-4f59b1d27177
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838244015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.838244015
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1249420756
Short name T975
Test name
Test status
Simulation time 132804779 ps
CPU time 1.83 seconds
Started Jul 09 06:59:15 PM PDT 24
Finished Jul 09 06:59:22 PM PDT 24
Peak memory 210668 kb
Host smart-1c4b70bd-885f-4fd7-b2c5-0d57dd65486a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249420756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1249420756
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3701522060
Short name T980
Test name
Test status
Simulation time 56354517 ps
CPU time 1.95 seconds
Started Jul 09 06:59:16 PM PDT 24
Finished Jul 09 06:59:22 PM PDT 24
Peak memory 209276 kb
Host smart-c416c56e-7cdb-489d-b597-144be09e2ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701522060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3701522060
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.229940081
Short name T939
Test name
Test status
Simulation time 86556784 ps
CPU time 1.08 seconds
Started Jul 09 06:59:21 PM PDT 24
Finished Jul 09 06:59:25 PM PDT 24
Peak memory 209472 kb
Host smart-8dff7ea8-96e6-4fc1-9a93-43eb0cf39d61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229940081 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.229940081
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.335255039
Short name T891
Test name
Test status
Simulation time 27967265 ps
CPU time 1.38 seconds
Started Jul 09 06:59:16 PM PDT 24
Finished Jul 09 06:59:22 PM PDT 24
Peak memory 209296 kb
Host smart-ce91134f-985d-4103-8781-a56f1cdf39ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335255039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.335255039
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3752278450
Short name T114
Test name
Test status
Simulation time 219392678 ps
CPU time 3.82 seconds
Started Jul 09 06:59:18 PM PDT 24
Finished Jul 09 06:59:26 PM PDT 24
Peak memory 217540 kb
Host smart-8cc8e6f4-0936-4ad7-855a-58b937548c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752278450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3752278450
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2068971070
Short name T921
Test name
Test status
Simulation time 77380416 ps
CPU time 1.18 seconds
Started Jul 09 06:59:24 PM PDT 24
Finished Jul 09 06:59:27 PM PDT 24
Peak memory 219704 kb
Host smart-8ea23997-8b37-40dc-8a1d-afd0d107be53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068971070 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2068971070
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1505187934
Short name T205
Test name
Test status
Simulation time 16822208 ps
CPU time 0.91 seconds
Started Jul 09 06:59:22 PM PDT 24
Finished Jul 09 06:59:25 PM PDT 24
Peak memory 209324 kb
Host smart-aadf0b26-b4c3-4033-a834-b642e64e0e31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505187934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1505187934
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1770591409
Short name T138
Test name
Test status
Simulation time 134205244 ps
CPU time 1.53 seconds
Started Jul 09 06:59:18 PM PDT 24
Finished Jul 09 06:59:24 PM PDT 24
Peak memory 209188 kb
Host smart-aff6bb2d-0b15-41ff-8e4b-861e6a86bb6c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770591409 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1770591409
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3398194647
Short name T969
Test name
Test status
Simulation time 701228877 ps
CPU time 4.05 seconds
Started Jul 09 06:59:18 PM PDT 24
Finished Jul 09 06:59:26 PM PDT 24
Peak memory 216992 kb
Host smart-659ad437-7471-40f6-86d9-90dd3b9811ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398194647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3398194647
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3653985267
Short name T904
Test name
Test status
Simulation time 1928722306 ps
CPU time 42.52 seconds
Started Jul 09 06:59:18 PM PDT 24
Finished Jul 09 07:00:05 PM PDT 24
Peak memory 217152 kb
Host smart-738ac02b-56ad-42eb-969a-999685407b20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653985267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3653985267
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3681350776
Short name T918
Test name
Test status
Simulation time 57144962 ps
CPU time 1.3 seconds
Started Jul 09 06:59:19 PM PDT 24
Finished Jul 09 06:59:24 PM PDT 24
Peak memory 210680 kb
Host smart-1871c9ef-fcc2-4748-a131-a80b1d0119a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681350776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3681350776
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.593069490
Short name T961
Test name
Test status
Simulation time 509556916 ps
CPU time 2.07 seconds
Started Jul 09 06:59:17 PM PDT 24
Finished Jul 09 06:59:23 PM PDT 24
Peak memory 217808 kb
Host smart-3cb4a388-de21-4800-a75a-7ab82e04baf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593069
490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.593069490
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2958942898
Short name T898
Test name
Test status
Simulation time 394632732 ps
CPU time 1.6 seconds
Started Jul 09 06:59:17 PM PDT 24
Finished Jul 09 06:59:22 PM PDT 24
Peak memory 209216 kb
Host smart-705d5dd6-5441-4ac3-acef-ddf775bf0bfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958942898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2958942898
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.923905627
Short name T875
Test name
Test status
Simulation time 21883271 ps
CPU time 1.29 seconds
Started Jul 09 06:59:16 PM PDT 24
Finished Jul 09 06:59:21 PM PDT 24
Peak memory 209356 kb
Host smart-8e982efd-36ad-4653-b835-a0856ccdbcf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923905627 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.923905627
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1537045746
Short name T150
Test name
Test status
Simulation time 26521244 ps
CPU time 1.31 seconds
Started Jul 09 06:59:21 PM PDT 24
Finished Jul 09 06:59:25 PM PDT 24
Peak memory 209352 kb
Host smart-dccf8594-34a0-469c-9909-eb6ff00c474a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537045746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1537045746
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2535804631
Short name T981
Test name
Test status
Simulation time 639542089 ps
CPU time 4.51 seconds
Started Jul 09 06:59:18 PM PDT 24
Finished Jul 09 06:59:26 PM PDT 24
Peak memory 217524 kb
Host smart-a0ab9865-0c49-4da4-a4a0-65419b1a71b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535804631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2535804631
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.84331642
Short name T131
Test name
Test status
Simulation time 214594176 ps
CPU time 2.53 seconds
Started Jul 09 06:59:23 PM PDT 24
Finished Jul 09 06:59:28 PM PDT 24
Peak memory 217488 kb
Host smart-6c0b76be-2688-47b0-be1a-86e929369e94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84331642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_er
r.84331642
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1322084290
Short name T118
Test name
Test status
Simulation time 18172923 ps
CPU time 1.26 seconds
Started Jul 09 06:59:22 PM PDT 24
Finished Jul 09 06:59:26 PM PDT 24
Peak memory 217612 kb
Host smart-453bbfd8-03ab-4e6d-a820-f90cd01f708a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322084290 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1322084290
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2965377054
Short name T866
Test name
Test status
Simulation time 106011909 ps
CPU time 0.79 seconds
Started Jul 09 06:59:24 PM PDT 24
Finished Jul 09 06:59:26 PM PDT 24
Peak memory 209240 kb
Host smart-896e8cc9-8421-4ce6-ba3a-b58546134f9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965377054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2965377054
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4177750331
Short name T948
Test name
Test status
Simulation time 156270084 ps
CPU time 1.54 seconds
Started Jul 09 06:59:22 PM PDT 24
Finished Jul 09 06:59:26 PM PDT 24
Peak memory 209204 kb
Host smart-7e47d1a0-0f30-4713-a0f2-2536ad7a32a0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177750331 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4177750331
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4185516488
Short name T931
Test name
Test status
Simulation time 4472557868 ps
CPU time 8.18 seconds
Started Jul 09 06:59:21 PM PDT 24
Finished Jul 09 06:59:32 PM PDT 24
Peak memory 217416 kb
Host smart-d0c0bdaa-a860-4136-8033-ffd9f5df7783
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185516488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4185516488
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.883412439
Short name T990
Test name
Test status
Simulation time 2149272735 ps
CPU time 9.3 seconds
Started Jul 09 06:59:22 PM PDT 24
Finished Jul 09 06:59:34 PM PDT 24
Peak memory 209276 kb
Host smart-843e6f3e-1a31-412e-99a8-762375f7c1c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883412439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.883412439
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1414084078
Short name T902
Test name
Test status
Simulation time 363016491 ps
CPU time 2.85 seconds
Started Jul 09 06:59:22 PM PDT 24
Finished Jul 09 06:59:28 PM PDT 24
Peak memory 210944 kb
Host smart-c09504cb-4a4f-4201-949e-3396044e3662
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414084078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1414084078
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3431860023
Short name T957
Test name
Test status
Simulation time 280611198 ps
CPU time 3.64 seconds
Started Jul 09 06:59:21 PM PDT 24
Finished Jul 09 06:59:28 PM PDT 24
Peak memory 217628 kb
Host smart-b67a9b3e-3ec1-4cb9-866a-2ec2cff1547f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343186
0023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3431860023
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.698801527
Short name T885
Test name
Test status
Simulation time 109959621 ps
CPU time 1.4 seconds
Started Jul 09 06:59:25 PM PDT 24
Finished Jul 09 06:59:28 PM PDT 24
Peak memory 209188 kb
Host smart-f9777e2d-5f63-4352-9861-a55e6fa0b0b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698801527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.698801527
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4025643327
Short name T892
Test name
Test status
Simulation time 49136468 ps
CPU time 1.1 seconds
Started Jul 09 06:59:23 PM PDT 24
Finished Jul 09 06:59:26 PM PDT 24
Peak memory 209412 kb
Host smart-8b4a9b92-3f55-4494-b297-a675cdfd21ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025643327 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4025643327
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1536598820
Short name T928
Test name
Test status
Simulation time 43194452 ps
CPU time 1.86 seconds
Started Jul 09 06:59:21 PM PDT 24
Finished Jul 09 06:59:26 PM PDT 24
Peak memory 217520 kb
Host smart-45190389-05d7-41ef-872b-7656480ef11a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536598820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1536598820
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1177284604
Short name T125
Test name
Test status
Simulation time 145440319 ps
CPU time 3.37 seconds
Started Jul 09 06:59:22 PM PDT 24
Finished Jul 09 06:59:28 PM PDT 24
Peak memory 217436 kb
Host smart-f6655dc1-3c71-4d4d-aecd-ff7e92582a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177284604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1177284604
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1080202131
Short name T937
Test name
Test status
Simulation time 76932679 ps
CPU time 1.08 seconds
Started Jul 09 06:59:27 PM PDT 24
Finished Jul 09 06:59:29 PM PDT 24
Peak memory 219380 kb
Host smart-675bd07b-bb6b-4205-9fc4-b71c8243cbc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080202131 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1080202131
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3409382052
Short name T111
Test name
Test status
Simulation time 35708090 ps
CPU time 0.9 seconds
Started Jul 09 06:59:27 PM PDT 24
Finished Jul 09 06:59:29 PM PDT 24
Peak memory 209224 kb
Host smart-3a661e3e-2137-4759-a269-7ae79e991bc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409382052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3409382052
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.744641854
Short name T946
Test name
Test status
Simulation time 44875131 ps
CPU time 1.15 seconds
Started Jul 09 06:59:31 PM PDT 24
Finished Jul 09 06:59:33 PM PDT 24
Peak memory 209164 kb
Host smart-e79482fe-c6f2-4fe3-be8c-483d58190446
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744641854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.744641854
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.894676972
Short name T136
Test name
Test status
Simulation time 407473673 ps
CPU time 3.5 seconds
Started Jul 09 06:59:31 PM PDT 24
Finished Jul 09 06:59:36 PM PDT 24
Peak memory 216976 kb
Host smart-77189acb-ac51-406e-bc46-e737f20a3793
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894676972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.894676972
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1162090408
Short name T954
Test name
Test status
Simulation time 2721245760 ps
CPU time 15.59 seconds
Started Jul 09 06:59:29 PM PDT 24
Finished Jul 09 06:59:46 PM PDT 24
Peak memory 209376 kb
Host smart-1cf80c81-617f-4402-b110-79fae2fb85ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162090408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1162090408
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3182165229
Short name T982
Test name
Test status
Simulation time 185013888 ps
CPU time 1.82 seconds
Started Jul 09 06:59:25 PM PDT 24
Finished Jul 09 06:59:28 PM PDT 24
Peak memory 209264 kb
Host smart-f4ab297c-7898-42a1-b2e1-f6c1ff45a71b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182165229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3182165229
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1557577842
Short name T942
Test name
Test status
Simulation time 199463476 ps
CPU time 1.33 seconds
Started Jul 09 06:59:28 PM PDT 24
Finished Jul 09 06:59:30 PM PDT 24
Peak memory 217672 kb
Host smart-05f3cecb-2e51-43b7-994e-222ccb97526d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155757
7842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1557577842
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3264483656
Short name T135
Test name
Test status
Simulation time 467799813 ps
CPU time 1.91 seconds
Started Jul 09 06:59:24 PM PDT 24
Finished Jul 09 06:59:27 PM PDT 24
Peak memory 209204 kb
Host smart-163387dc-8a56-41a1-818e-9d9f8257888c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264483656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3264483656
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2183967284
Short name T882
Test name
Test status
Simulation time 183381570 ps
CPU time 1.45 seconds
Started Jul 09 06:59:28 PM PDT 24
Finished Jul 09 06:59:30 PM PDT 24
Peak memory 209368 kb
Host smart-4455f528-c6aa-442e-b449-46ed9629826c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183967284 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2183967284
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.512477963
Short name T913
Test name
Test status
Simulation time 128997241 ps
CPU time 1.83 seconds
Started Jul 09 06:59:29 PM PDT 24
Finished Jul 09 06:59:31 PM PDT 24
Peak memory 209420 kb
Host smart-a5ffd240-15c8-41a9-b1d4-9d3b3dd651c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512477963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.512477963
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1539652291
Short name T947
Test name
Test status
Simulation time 38946943 ps
CPU time 1.71 seconds
Started Jul 09 06:59:31 PM PDT 24
Finished Jul 09 06:59:34 PM PDT 24
Peak memory 218468 kb
Host smart-2b43ac03-4f95-4e46-94ea-d9649d916eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539652291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1539652291
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3160656018
Short name T473
Test name
Test status
Simulation time 22749684 ps
CPU time 1.04 seconds
Started Jul 09 05:25:23 PM PDT 24
Finished Jul 09 05:25:25 PM PDT 24
Peak memory 208976 kb
Host smart-7ae486fb-d715-4ccf-b8b2-2dcf4b221852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160656018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3160656018
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2650979661
Short name T525
Test name
Test status
Simulation time 674679411 ps
CPU time 15.19 seconds
Started Jul 09 05:25:24 PM PDT 24
Finished Jul 09 05:25:40 PM PDT 24
Peak memory 225900 kb
Host smart-0e6a0b09-9957-44b1-bd2c-ea03ff2a4ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650979661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2650979661
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3303379405
Short name T556
Test name
Test status
Simulation time 952793686 ps
CPU time 12.35 seconds
Started Jul 09 05:25:23 PM PDT 24
Finished Jul 09 05:25:36 PM PDT 24
Peak memory 217248 kb
Host smart-5e2f4d9e-75b2-4665-b414-739c436958ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303379405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3303379405
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1047346617
Short name T228
Test name
Test status
Simulation time 4205393956 ps
CPU time 114.44 seconds
Started Jul 09 05:25:30 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 219220 kb
Host smart-7625980e-54ba-4aa6-bac4-7f138b8c77e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047346617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1047346617
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1326730527
Short name T791
Test name
Test status
Simulation time 5845867906 ps
CPU time 4.69 seconds
Started Jul 09 05:25:25 PM PDT 24
Finished Jul 09 05:25:30 PM PDT 24
Peak memory 217804 kb
Host smart-6cbb0888-851b-4490-97e1-fdbc7fff9d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326730527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
326730527
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3635347555
Short name T235
Test name
Test status
Simulation time 1441771748 ps
CPU time 5.85 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:25:35 PM PDT 24
Peak memory 218108 kb
Host smart-79e5603e-de66-4a18-8eb1-185f76ca9d9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635347555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3635347555
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3253296366
Short name T694
Test name
Test status
Simulation time 3193667276 ps
CPU time 12.32 seconds
Started Jul 09 05:25:26 PM PDT 24
Finished Jul 09 05:25:39 PM PDT 24
Peak memory 217848 kb
Host smart-e590dd9e-1b76-4870-b580-1fce9a5f377a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253296366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3253296366
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.549528764
Short name T601
Test name
Test status
Simulation time 343709052 ps
CPU time 4.24 seconds
Started Jul 09 05:25:26 PM PDT 24
Finished Jul 09 05:25:31 PM PDT 24
Peak memory 217672 kb
Host smart-b2fe1336-c862-4d35-910c-ab80eef2c687
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549528764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.549528764
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1760927599
Short name T463
Test name
Test status
Simulation time 9344027276 ps
CPU time 29.16 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:25:58 PM PDT 24
Peak memory 251824 kb
Host smart-dc2548ec-2c87-4eb6-baf3-64d3cc4f8bfa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760927599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1760927599
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1586840512
Short name T498
Test name
Test status
Simulation time 706437693 ps
CPU time 19.11 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:51 PM PDT 24
Peak memory 250940 kb
Host smart-3308056b-4247-4e86-b631-b79566d813bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586840512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1586840512
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.43372303
Short name T374
Test name
Test status
Simulation time 87419631 ps
CPU time 3.17 seconds
Started Jul 09 05:25:30 PM PDT 24
Finished Jul 09 05:25:34 PM PDT 24
Peak memory 218044 kb
Host smart-ee924c1f-2098-4c80-9d55-05a056573319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43372303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.43372303
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.586702868
Short name T672
Test name
Test status
Simulation time 647513805 ps
CPU time 11.53 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:25:40 PM PDT 24
Peak memory 217576 kb
Host smart-f26143d8-d971-426f-98d1-42456de67191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586702868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.586702868
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1983304677
Short name T55
Test name
Test status
Simulation time 876290755 ps
CPU time 24.55 seconds
Started Jul 09 05:25:27 PM PDT 24
Finished Jul 09 05:25:52 PM PDT 24
Peak memory 282120 kb
Host smart-12bcc553-fa2d-47e1-a528-828b26275549
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983304677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1983304677
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3664664681
Short name T63
Test name
Test status
Simulation time 353304625 ps
CPU time 12.25 seconds
Started Jul 09 05:25:23 PM PDT 24
Finished Jul 09 05:25:35 PM PDT 24
Peak memory 218380 kb
Host smart-ec5c16a6-886c-424f-929f-d95dda427cd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664664681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3664664681
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3215426589
Short name T799
Test name
Test status
Simulation time 368717036 ps
CPU time 6.83 seconds
Started Jul 09 05:25:27 PM PDT 24
Finished Jul 09 05:25:35 PM PDT 24
Peak memory 218096 kb
Host smart-0bee8467-31e1-45f1-84ae-132cba1f9796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215426589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3215426589
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2281196291
Short name T305
Test name
Test status
Simulation time 1118740342 ps
CPU time 7 seconds
Started Jul 09 05:25:31 PM PDT 24
Finished Jul 09 05:25:39 PM PDT 24
Peak memory 218444 kb
Host smart-e045a257-8540-411c-9b47-5b9772b16e7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281196291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
281196291
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.907972305
Short name T773
Test name
Test status
Simulation time 462208920 ps
CPU time 10.6 seconds
Started Jul 09 05:25:25 PM PDT 24
Finished Jul 09 05:25:36 PM PDT 24
Peak memory 218172 kb
Host smart-9cefeaf4-abed-4493-9bb9-25e771124248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907972305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.907972305
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3968355980
Short name T589
Test name
Test status
Simulation time 46830786 ps
CPU time 1.2 seconds
Started Jul 09 05:25:27 PM PDT 24
Finished Jul 09 05:25:29 PM PDT 24
Peak memory 217640 kb
Host smart-ced8076e-0433-4d51-a214-b9a5e0a98102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968355980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3968355980
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.4242395917
Short name T337
Test name
Test status
Simulation time 995563469 ps
CPU time 20.36 seconds
Started Jul 09 05:25:20 PM PDT 24
Finished Jul 09 05:25:41 PM PDT 24
Peak memory 250736 kb
Host smart-3d64c362-40e1-42b2-b0a5-f9da2a843765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242395917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.4242395917
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1116251234
Short name T642
Test name
Test status
Simulation time 202587489 ps
CPU time 9.9 seconds
Started Jul 09 05:25:21 PM PDT 24
Finished Jul 09 05:25:31 PM PDT 24
Peak memory 250936 kb
Host smart-610a0b29-a08d-4e86-bb13-4b7db488a31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116251234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1116251234
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3671247174
Short name T739
Test name
Test status
Simulation time 4367583203 ps
CPU time 84.97 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:26:54 PM PDT 24
Peak memory 253560 kb
Host smart-9419168c-2ca0-40b3-a1b3-f4f8a3a48965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671247174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3671247174
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3840432996
Short name T681
Test name
Test status
Simulation time 67314973 ps
CPU time 0.95 seconds
Started Jul 09 05:25:37 PM PDT 24
Finished Jul 09 05:25:39 PM PDT 24
Peak memory 212724 kb
Host smart-ed57e467-c46e-481f-b3f0-7b331efb849f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840432996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3840432996
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2642723754
Short name T719
Test name
Test status
Simulation time 42726829 ps
CPU time 1.26 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:25:49 PM PDT 24
Peak memory 208916 kb
Host smart-55156700-2a0e-469f-84fc-e92a7fd9c1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642723754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2642723754
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1491209380
Short name T817
Test name
Test status
Simulation time 1839638755 ps
CPU time 7.26 seconds
Started Jul 09 05:25:31 PM PDT 24
Finished Jul 09 05:25:38 PM PDT 24
Peak memory 225968 kb
Host smart-ac3de98c-8916-487a-b196-bf03c654d3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491209380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1491209380
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1333735379
Short name T7
Test name
Test status
Simulation time 5847918223 ps
CPU time 13.29 seconds
Started Jul 09 05:25:26 PM PDT 24
Finished Jul 09 05:25:40 PM PDT 24
Peak memory 217536 kb
Host smart-7ad31652-e38e-4501-8717-91d4b0f6e1e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333735379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1333735379
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.558076359
Short name T512
Test name
Test status
Simulation time 10507791520 ps
CPU time 37.03 seconds
Started Jul 09 05:25:29 PM PDT 24
Finished Jul 09 05:26:07 PM PDT 24
Peak memory 218444 kb
Host smart-dbd7fd36-ca28-42fc-9e1d-18b8fd56996b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558076359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.558076359
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2903122990
Short name T515
Test name
Test status
Simulation time 216748553 ps
CPU time 3.51 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:36 PM PDT 24
Peak memory 217724 kb
Host smart-f2f21047-53c2-40ec-9b5e-d0b5056ad247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903122990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
903122990
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2431171389
Short name T795
Test name
Test status
Simulation time 1762051477 ps
CPU time 11.77 seconds
Started Jul 09 05:25:27 PM PDT 24
Finished Jul 09 05:25:40 PM PDT 24
Peak memory 218160 kb
Host smart-4a61ffb4-28f1-41cf-8010-1fc7ae471824
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431171389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2431171389
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1902654042
Short name T568
Test name
Test status
Simulation time 2355465230 ps
CPU time 12.71 seconds
Started Jul 09 05:25:36 PM PDT 24
Finished Jul 09 05:25:49 PM PDT 24
Peak memory 217548 kb
Host smart-0e25696a-70ca-488d-86c1-b7d8db883368
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902654042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1902654042
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3566352438
Short name T592
Test name
Test status
Simulation time 90304637 ps
CPU time 2.18 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:35 PM PDT 24
Peak memory 217648 kb
Host smart-6efddcbc-d6bc-42d1-9740-4225f77ba271
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566352438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3566352438
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.251564062
Short name T844
Test name
Test status
Simulation time 2557679740 ps
CPU time 53.04 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:26:23 PM PDT 24
Peak memory 276632 kb
Host smart-6301b89c-0e35-46da-884e-54168af1d2f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251564062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.251564062
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1444677975
Short name T566
Test name
Test status
Simulation time 4082525923 ps
CPU time 17.93 seconds
Started Jul 09 05:25:39 PM PDT 24
Finished Jul 09 05:25:57 PM PDT 24
Peak memory 251280 kb
Host smart-2bb98f8b-a579-44e8-a700-194200fa0680
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444677975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1444677975
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1532106713
Short name T530
Test name
Test status
Simulation time 84059784 ps
CPU time 3.2 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:36 PM PDT 24
Peak memory 222452 kb
Host smart-e872a8fa-d392-43aa-b0aa-21f063ade52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532106713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1532106713
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3900913808
Short name T834
Test name
Test status
Simulation time 347991459 ps
CPU time 19.92 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:53 PM PDT 24
Peak memory 214832 kb
Host smart-43099ec1-0628-402d-b245-42566aa438f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900913808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3900913808
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2427678159
Short name T801
Test name
Test status
Simulation time 688536232 ps
CPU time 15.21 seconds
Started Jul 09 05:25:39 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 225940 kb
Host smart-bbfc0e5b-5c0f-4474-ae94-0d8d8de8bda9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427678159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2427678159
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1924277063
Short name T325
Test name
Test status
Simulation time 7630703988 ps
CPU time 10.87 seconds
Started Jul 09 05:25:27 PM PDT 24
Finished Jul 09 05:25:39 PM PDT 24
Peak memory 226020 kb
Host smart-2da09c3d-22c2-455d-b281-25f87a56ed41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924277063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1924277063
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.853397964
Short name T478
Test name
Test status
Simulation time 183443787 ps
CPU time 7.5 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:25:37 PM PDT 24
Peak memory 218184 kb
Host smart-4c555794-1464-4019-a6f0-8f0ef6eb9527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853397964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.853397964
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1667244378
Short name T545
Test name
Test status
Simulation time 161111507 ps
CPU time 2.9 seconds
Started Jul 09 05:25:26 PM PDT 24
Finished Jul 09 05:25:30 PM PDT 24
Peak memory 224124 kb
Host smart-4bb08ea2-f1cb-4c9e-a5a1-1545d554892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667244378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1667244378
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1203436978
Short name T671
Test name
Test status
Simulation time 1423166131 ps
CPU time 38.44 seconds
Started Jul 09 05:25:25 PM PDT 24
Finished Jul 09 05:26:03 PM PDT 24
Peak memory 250944 kb
Host smart-ca885916-a948-4535-87a7-ab77cc018382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203436978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1203436978
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1955488347
Short name T679
Test name
Test status
Simulation time 85187128 ps
CPU time 7.73 seconds
Started Jul 09 05:25:34 PM PDT 24
Finished Jul 09 05:25:42 PM PDT 24
Peak memory 250420 kb
Host smart-6fb3aabf-6aae-43fb-a34c-f80fc6fedd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955488347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1955488347
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3451353708
Short name T762
Test name
Test status
Simulation time 13840691 ps
CPU time 0.92 seconds
Started Jul 09 05:25:29 PM PDT 24
Finished Jul 09 05:25:31 PM PDT 24
Peak memory 212736 kb
Host smart-29bc61a4-ef9b-457d-adab-48143d726b10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451353708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3451353708
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2051807729
Short name T94
Test name
Test status
Simulation time 45502032 ps
CPU time 1.12 seconds
Started Jul 09 05:26:02 PM PDT 24
Finished Jul 09 05:26:04 PM PDT 24
Peak memory 209168 kb
Host smart-5c04a297-a137-45ab-952a-310c962a0e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051807729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2051807729
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.392922208
Short name T276
Test name
Test status
Simulation time 397446736 ps
CPU time 9.2 seconds
Started Jul 09 05:25:58 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 225968 kb
Host smart-7c8358b0-39b9-4920-9337-c6f8fff449a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392922208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.392922208
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1287326085
Short name T634
Test name
Test status
Simulation time 209655336 ps
CPU time 4.7 seconds
Started Jul 09 05:26:04 PM PDT 24
Finished Jul 09 05:26:09 PM PDT 24
Peak memory 217152 kb
Host smart-e6dd37b0-cc87-4167-9b3e-32d2420d6561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287326085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1287326085
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.572038256
Short name T692
Test name
Test status
Simulation time 246671185 ps
CPU time 1.55 seconds
Started Jul 09 05:26:02 PM PDT 24
Finished Jul 09 05:26:04 PM PDT 24
Peak memory 217612 kb
Host smart-04bef209-9710-4006-8df9-22a4337833f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572038256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
572038256
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1830128593
Short name T768
Test name
Test status
Simulation time 9624889788 ps
CPU time 81.57 seconds
Started Jul 09 05:25:58 PM PDT 24
Finished Jul 09 05:27:21 PM PDT 24
Peak memory 281236 kb
Host smart-e0c07bad-6db6-43f8-a736-5ab217df9bd6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830128593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1830128593
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.669603712
Short name T389
Test name
Test status
Simulation time 987296026 ps
CPU time 8.09 seconds
Started Jul 09 05:26:02 PM PDT 24
Finished Jul 09 05:26:11 PM PDT 24
Peak memory 222196 kb
Host smart-214606a8-5c91-46cb-85f1-38aface9a2ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669603712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.669603712
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.609300577
Short name T654
Test name
Test status
Simulation time 77157743 ps
CPU time 3.04 seconds
Started Jul 09 05:25:59 PM PDT 24
Finished Jul 09 05:26:04 PM PDT 24
Peak memory 218212 kb
Host smart-264fbf6f-6793-4474-9301-6d32375df32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609300577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.609300577
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.683074881
Short name T701
Test name
Test status
Simulation time 959297051 ps
CPU time 10.51 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:21 PM PDT 24
Peak memory 225896 kb
Host smart-b93bcb27-ce06-4bd9-9497-0ad4e68b3a57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683074881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.683074881
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3977326403
Short name T797
Test name
Test status
Simulation time 381567674 ps
CPU time 14.62 seconds
Started Jul 09 05:26:00 PM PDT 24
Finished Jul 09 05:26:16 PM PDT 24
Peak memory 225988 kb
Host smart-945d5cb9-751e-4755-8e55-3535520c353f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977326403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3977326403
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3509656953
Short name T504
Test name
Test status
Simulation time 509528899 ps
CPU time 7.44 seconds
Started Jul 09 05:26:05 PM PDT 24
Finished Jul 09 05:26:13 PM PDT 24
Peak memory 218008 kb
Host smart-92a2c72a-1524-4364-9322-4d03d45e2989
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509656953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3509656953
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3662395834
Short name T261
Test name
Test status
Simulation time 35613949 ps
CPU time 2.22 seconds
Started Jul 09 05:26:00 PM PDT 24
Finished Jul 09 05:26:04 PM PDT 24
Peak memory 217688 kb
Host smart-f49956a6-a008-4db3-98f9-c1e122b55387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662395834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3662395834
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1692186538
Short name T296
Test name
Test status
Simulation time 429783095 ps
CPU time 27.33 seconds
Started Jul 09 05:25:58 PM PDT 24
Finished Jul 09 05:26:27 PM PDT 24
Peak memory 250920 kb
Host smart-2fe239df-4c67-4f69-b5dc-5b3ae4e48650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692186538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1692186538
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1705491598
Short name T494
Test name
Test status
Simulation time 62370257 ps
CPU time 7.16 seconds
Started Jul 09 05:25:57 PM PDT 24
Finished Jul 09 05:26:05 PM PDT 24
Peak memory 242732 kb
Host smart-b14cd521-8391-4966-8844-ba51e07e84c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705491598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1705491598
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3350289343
Short name T750
Test name
Test status
Simulation time 9745319177 ps
CPU time 124.08 seconds
Started Jul 09 05:25:58 PM PDT 24
Finished Jul 09 05:28:03 PM PDT 24
Peak memory 422084 kb
Host smart-6a42c745-2fd0-4c42-9902-42329744f679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350289343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3350289343
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.279220148
Short name T141
Test name
Test status
Simulation time 319466761614 ps
CPU time 393.43 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:32:35 PM PDT 24
Peak memory 332988 kb
Host smart-ffb8d978-3e00-4e4a-811c-4a10b50f8287
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=279220148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.279220148
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1229331803
Short name T776
Test name
Test status
Simulation time 13786394 ps
CPU time 1.01 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:25:59 PM PDT 24
Peak memory 211644 kb
Host smart-8f19dfd6-ac70-4f07-a452-88db2d2de8d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229331803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1229331803
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.513409266
Short name T327
Test name
Test status
Simulation time 53796333 ps
CPU time 0.95 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:15 PM PDT 24
Peak memory 208912 kb
Host smart-d9247ebb-be16-4757-9f40-4a46d62264af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513409266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.513409266
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3361214351
Short name T637
Test name
Test status
Simulation time 398740289 ps
CPU time 15.64 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:26:17 PM PDT 24
Peak memory 218032 kb
Host smart-73c44095-cd72-4712-beb2-5ff0b2b6d80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361214351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3361214351
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2119805666
Short name T24
Test name
Test status
Simulation time 318033177 ps
CPU time 8.52 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 217300 kb
Host smart-5cb61a36-4ec9-4adb-86aa-7711bd9ce346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119805666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2119805666
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.56609968
Short name T784
Test name
Test status
Simulation time 2591931718 ps
CPU time 36.39 seconds
Started Jul 09 05:26:00 PM PDT 24
Finished Jul 09 05:26:38 PM PDT 24
Peak memory 225964 kb
Host smart-b60205af-7bc3-4577-98b1-dd33edcaffec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56609968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_err
ors.56609968
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1091073132
Short name T232
Test name
Test status
Simulation time 1244839652 ps
CPU time 6.95 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:26:19 PM PDT 24
Peak memory 218188 kb
Host smart-c1b5ed86-9d4c-4ef8-8362-55df615cb4b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091073132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1091073132
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3660169525
Short name T285
Test name
Test status
Simulation time 346700071 ps
CPU time 6.28 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 217924 kb
Host smart-1c0f737e-7459-412e-b264-91f7b627e60c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660169525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3660169525
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.210771999
Short name T836
Test name
Test status
Simulation time 10359717492 ps
CPU time 65.02 seconds
Started Jul 09 05:26:08 PM PDT 24
Finished Jul 09 05:27:14 PM PDT 24
Peak memory 278024 kb
Host smart-8f9b56b5-2c08-423b-bf37-b97c18b37869
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210771999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.210771999
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3441136601
Short name T416
Test name
Test status
Simulation time 636193217 ps
CPU time 15.75 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:26 PM PDT 24
Peak memory 250784 kb
Host smart-ad565248-a552-4103-83d9-f16200bac149
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441136601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3441136601
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.686106059
Short name T709
Test name
Test status
Simulation time 903171320 ps
CPU time 3.17 seconds
Started Jul 09 05:26:04 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 218192 kb
Host smart-f8dbcf97-d904-4926-8634-0fcc61b39697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686106059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.686106059
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3716433076
Short name T499
Test name
Test status
Simulation time 6073528601 ps
CPU time 22.48 seconds
Started Jul 09 05:26:09 PM PDT 24
Finished Jul 09 05:26:32 PM PDT 24
Peak memory 219640 kb
Host smart-7ed3faa8-c972-4dba-98ec-9ea6533b7aee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716433076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3716433076
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.524206347
Short name T595
Test name
Test status
Simulation time 3196525857 ps
CPU time 15.33 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:32 PM PDT 24
Peak memory 225872 kb
Host smart-5c9424f8-d8b5-4240-8d7f-1e54707872ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524206347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.524206347
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2061328155
Short name T245
Test name
Test status
Simulation time 1990454511 ps
CPU time 16.96 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:28 PM PDT 24
Peak memory 218108 kb
Host smart-bae5b41f-970b-49ea-8df3-9b5e7903a8a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061328155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2061328155
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2643461230
Short name T387
Test name
Test status
Simulation time 358848520 ps
CPU time 12.37 seconds
Started Jul 09 05:26:08 PM PDT 24
Finished Jul 09 05:26:21 PM PDT 24
Peak memory 218228 kb
Host smart-5e0271f1-cb92-4823-bdc4-5e695a2afa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643461230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2643461230
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.512670032
Short name T82
Test name
Test status
Simulation time 303412568 ps
CPU time 1.31 seconds
Started Jul 09 05:25:59 PM PDT 24
Finished Jul 09 05:26:02 PM PDT 24
Peak memory 217696 kb
Host smart-f38c41c6-f6e2-4888-a682-c965d275f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512670032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.512670032
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1565741388
Short name T490
Test name
Test status
Simulation time 194821646 ps
CPU time 27.54 seconds
Started Jul 09 05:26:03 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 250864 kb
Host smart-275f9b69-aaad-4ffe-8164-1716331f591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565741388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1565741388
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.105872098
Short name T583
Test name
Test status
Simulation time 345059669 ps
CPU time 8.16 seconds
Started Jul 09 05:26:04 PM PDT 24
Finished Jul 09 05:26:13 PM PDT 24
Peak memory 250988 kb
Host smart-b8d35617-9aed-4743-b1ba-d0285886131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105872098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.105872098
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3038589618
Short name T256
Test name
Test status
Simulation time 11717071939 ps
CPU time 44.26 seconds
Started Jul 09 05:26:20 PM PDT 24
Finished Jul 09 05:27:05 PM PDT 24
Peak memory 228216 kb
Host smart-85a02d15-deda-45fc-a2a7-ee0e676f9db2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038589618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3038589618
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1695018261
Short name T185
Test name
Test status
Simulation time 116705253 ps
CPU time 0.9 seconds
Started Jul 09 05:26:05 PM PDT 24
Finished Jul 09 05:26:07 PM PDT 24
Peak memory 211808 kb
Host smart-ee99bc4e-f256-4d46-a77c-86b9c6bea6db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695018261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1695018261
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1817587440
Short name T411
Test name
Test status
Simulation time 19080033 ps
CPU time 0.91 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:18 PM PDT 24
Peak memory 208916 kb
Host smart-44817894-1e2f-4427-8f1b-4365b2c9d54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817587440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1817587440
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2553034460
Short name T543
Test name
Test status
Simulation time 416896081 ps
CPU time 18.21 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 225896 kb
Host smart-e701d02f-c64d-465e-8ef9-d436cca08610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553034460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2553034460
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3299633722
Short name T529
Test name
Test status
Simulation time 1651980685 ps
CPU time 5.04 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:22 PM PDT 24
Peak memory 217164 kb
Host smart-e6408cdc-593b-4d4b-a3f5-ad38c251c584
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299633722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3299633722
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3195956053
Short name T474
Test name
Test status
Simulation time 2013829702 ps
CPU time 35.6 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:46 PM PDT 24
Peak memory 218292 kb
Host smart-776295cb-59fc-454a-bf15-5f6ca818b856
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195956053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3195956053
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.795461328
Short name T823
Test name
Test status
Simulation time 969621547 ps
CPU time 5.77 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:19 PM PDT 24
Peak memory 218176 kb
Host smart-8167dd97-599a-4ce4-93a6-8c82db38f24e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795461328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.795461328
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1921624232
Short name T165
Test name
Test status
Simulation time 2860225347 ps
CPU time 17.51 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:26:29 PM PDT 24
Peak memory 217692 kb
Host smart-11d60f05-5b72-4f3c-8a4d-4c491508b53a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921624232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1921624232
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1769123642
Short name T807
Test name
Test status
Simulation time 8440033538 ps
CPU time 78.67 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:27:31 PM PDT 24
Peak memory 251004 kb
Host smart-8b27f4a4-5f89-4d94-9cee-f7fa17642d5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769123642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1769123642
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1387774905
Short name T612
Test name
Test status
Simulation time 474454524 ps
CPU time 19.15 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 250820 kb
Host smart-5a5923b5-35e2-4755-a092-93885375b865
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387774905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1387774905
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1151264016
Short name T238
Test name
Test status
Simulation time 99655991 ps
CPU time 3.39 seconds
Started Jul 09 05:26:00 PM PDT 24
Finished Jul 09 05:26:04 PM PDT 24
Peak memory 218064 kb
Host smart-cbf6f2a0-b01c-4aaf-a283-6f5ec06b20f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151264016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1151264016
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1555444821
Short name T431
Test name
Test status
Simulation time 6336668949 ps
CPU time 11.81 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:26:23 PM PDT 24
Peak memory 226036 kb
Host smart-28e979d7-3e90-41ba-b413-5428fb6d934c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555444821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1555444821
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3084747235
Short name T454
Test name
Test status
Simulation time 211363526 ps
CPU time 7.71 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:23 PM PDT 24
Peak memory 225992 kb
Host smart-b17b5d8a-a258-413f-8cb1-e7e1f72db870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084747235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3084747235
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1273913911
Short name T32
Test name
Test status
Simulation time 220372171 ps
CPU time 8.66 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:22 PM PDT 24
Peak memory 218168 kb
Host smart-db83f8df-7bf2-43d2-ad78-fbccb98a3c95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273913911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1273913911
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2420299469
Short name T450
Test name
Test status
Simulation time 553295696 ps
CPU time 15.1 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:26 PM PDT 24
Peak memory 218128 kb
Host smart-6fd69e82-b486-4f28-8e7e-836cf14a68e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420299469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2420299469
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3618639232
Short name T339
Test name
Test status
Simulation time 158950462 ps
CPU time 2.69 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:13 PM PDT 24
Peak memory 217680 kb
Host smart-3fff7a91-f096-430f-a4b2-9b6ffd7021a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618639232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3618639232
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1820574626
Short name T819
Test name
Test status
Simulation time 5701811405 ps
CPU time 34.74 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:46 PM PDT 24
Peak memory 250952 kb
Host smart-dd245c53-966a-492f-be63-49c2785de7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820574626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1820574626
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.578234926
Short name T284
Test name
Test status
Simulation time 229061861 ps
CPU time 7.39 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:26:09 PM PDT 24
Peak memory 250172 kb
Host smart-1a1f85dd-650d-4b94-b333-034a6db94440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578234926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.578234926
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3460542099
Short name T312
Test name
Test status
Simulation time 2524118470 ps
CPU time 65.1 seconds
Started Jul 09 05:26:08 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 276384 kb
Host smart-9b622cb3-96d9-4383-8782-1dde179842f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460542099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3460542099
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2802056095
Short name T44
Test name
Test status
Simulation time 16641471565 ps
CPU time 592.74 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:36:05 PM PDT 24
Peak memory 422036 kb
Host smart-11664a28-464c-4c52-a7ea-e51b524af37a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2802056095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2802056095
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3691688681
Short name T783
Test name
Test status
Simulation time 62834145 ps
CPU time 1.2 seconds
Started Jul 09 05:26:04 PM PDT 24
Finished Jul 09 05:26:06 PM PDT 24
Peak memory 217680 kb
Host smart-5dd1db97-f3cc-428b-9b47-86702e5ea08e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691688681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3691688681
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3986626569
Short name T424
Test name
Test status
Simulation time 99765504 ps
CPU time 1.17 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:17 PM PDT 24
Peak memory 208912 kb
Host smart-0398ee57-2f0f-4469-a51d-78aa29a9a255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986626569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3986626569
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1411581665
Short name T833
Test name
Test status
Simulation time 434391300 ps
CPU time 11.98 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 218148 kb
Host smart-d4fe4ee3-c977-4343-a7df-0c2ad339d6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411581665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1411581665
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.45861126
Short name T407
Test name
Test status
Simulation time 351360646 ps
CPU time 2.08 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:19 PM PDT 24
Peak memory 216976 kb
Host smart-f495a428-336f-4900-aad4-5aef75bb1683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45861126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.45861126
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1112335458
Short name T170
Test name
Test status
Simulation time 3290892792 ps
CPU time 25.37 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:40 PM PDT 24
Peak memory 218784 kb
Host smart-e30ed5c5-68d3-4d5e-9a26-0698a277e30a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112335458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1112335458
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.539787722
Short name T567
Test name
Test status
Simulation time 118752089 ps
CPU time 3.12 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 218124 kb
Host smart-a9a88f7b-44b7-4626-8ef1-864facece374
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539787722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.539787722
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2265335275
Short name T408
Test name
Test status
Simulation time 252559298 ps
CPU time 3.77 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:18 PM PDT 24
Peak memory 217612 kb
Host smart-b1dcb758-dd5e-4ab1-bf85-c8842efa077c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265335275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2265335275
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1261248972
Short name T623
Test name
Test status
Simulation time 3582452055 ps
CPU time 21.99 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:35 PM PDT 24
Peak memory 250984 kb
Host smart-d714ae77-113b-4d5c-85ac-548e7a26383f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261248972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1261248972
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.19544679
Short name T455
Test name
Test status
Simulation time 65885102 ps
CPU time 3.52 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:16 PM PDT 24
Peak memory 218140 kb
Host smart-14a2e069-e8d0-416e-8a6f-9c4a062e5d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19544679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.19544679
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2080214759
Short name T646
Test name
Test status
Simulation time 311741590 ps
CPU time 13.97 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:25 PM PDT 24
Peak memory 226024 kb
Host smart-c8057245-ddc2-4662-90ad-f38c872cc201
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080214759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2080214759
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.429763570
Short name T231
Test name
Test status
Simulation time 1531671526 ps
CPU time 14.74 seconds
Started Jul 09 05:26:09 PM PDT 24
Finished Jul 09 05:26:24 PM PDT 24
Peak memory 225996 kb
Host smart-f4feb184-a9a3-4bfa-8cdf-ff929e76af9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429763570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.429763570
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2357181881
Short name T571
Test name
Test status
Simulation time 1830569248 ps
CPU time 6.75 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:26:19 PM PDT 24
Peak memory 225972 kb
Host smart-f6253390-d147-4c31-9461-85c3ca0c65f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357181881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2357181881
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3880590235
Short name T843
Test name
Test status
Simulation time 358644580 ps
CPU time 13.53 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:28 PM PDT 24
Peak memory 225972 kb
Host smart-03cae89f-b6ca-4d1e-86bc-e3fdcbe98875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880590235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3880590235
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2816055734
Short name T479
Test name
Test status
Simulation time 64145300 ps
CPU time 2.68 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:16 PM PDT 24
Peak memory 217656 kb
Host smart-80a213b1-4c61-444a-8b79-edbaff5b0d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816055734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2816055734
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2493328524
Short name T576
Test name
Test status
Simulation time 185103700 ps
CPU time 25.83 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 250952 kb
Host smart-b3af57c0-dc8e-4306-9c82-00e0cc7ddf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493328524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2493328524
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2863250962
Short name T503
Test name
Test status
Simulation time 80291934 ps
CPU time 8.91 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:23 PM PDT 24
Peak memory 250880 kb
Host smart-74df3bbd-8a85-4724-84be-63b16a9c7b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863250962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2863250962
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.228005289
Short name T143
Test name
Test status
Simulation time 55143251421 ps
CPU time 567.44 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:35:41 PM PDT 24
Peak memory 447692 kb
Host smart-b4420aa0-7165-460b-afdc-735de0f37240
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=228005289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.228005289
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1673334661
Short name T588
Test name
Test status
Simulation time 58674428 ps
CPU time 0.88 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:17 PM PDT 24
Peak memory 208608 kb
Host smart-bb1ed3b2-75b4-4c24-8412-51d806fe32e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673334661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1673334661
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.4226671838
Short name T381
Test name
Test status
Simulation time 1464388159 ps
CPU time 9.84 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:23 PM PDT 24
Peak memory 218084 kb
Host smart-1ab5025c-5056-4ebe-ad76-9c8e96430c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226671838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.4226671838
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.4223141616
Short name T8
Test name
Test status
Simulation time 87436234 ps
CPU time 1.86 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:15 PM PDT 24
Peak memory 216964 kb
Host smart-4e3b1c02-3e6f-455d-b7d6-ae8ce022f2dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223141616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4223141616
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2780961900
Short name T432
Test name
Test status
Simulation time 7628629630 ps
CPU time 45.16 seconds
Started Jul 09 05:26:11 PM PDT 24
Finished Jul 09 05:26:57 PM PDT 24
Peak memory 225996 kb
Host smart-e5d7970a-651b-4b6c-987e-b3a8bd38ea9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780961900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2780961900
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.4162222843
Short name T674
Test name
Test status
Simulation time 791418218 ps
CPU time 7.92 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:23 PM PDT 24
Peak memory 218084 kb
Host smart-0e4804d3-df59-4115-bae0-15fffdc14bad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162222843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.4162222843
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1075450491
Short name T838
Test name
Test status
Simulation time 1671101022 ps
CPU time 2.53 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:17 PM PDT 24
Peak memory 217612 kb
Host smart-e81a5328-f194-4974-95fa-84d05148d7a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075450491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1075450491
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3194096933
Short name T357
Test name
Test status
Simulation time 2433854906 ps
CPU time 58.9 seconds
Started Jul 09 05:26:18 PM PDT 24
Finished Jul 09 05:27:19 PM PDT 24
Peak memory 275584 kb
Host smart-0c2a4a7f-cd92-4fb4-99fa-fca85a3c26ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194096933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3194096933
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.978226193
Short name T716
Test name
Test status
Simulation time 7204226999 ps
CPU time 19.7 seconds
Started Jul 09 05:26:18 PM PDT 24
Finished Jul 09 05:26:39 PM PDT 24
Peak memory 250892 kb
Host smart-b81e95e1-05b6-4a15-ad35-b483dc835f4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978226193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.978226193
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.882195187
Short name T97
Test name
Test status
Simulation time 63332853 ps
CPU time 3.36 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 218176 kb
Host smart-b3c0bd69-8faf-452b-83b2-afcb130ab8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882195187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.882195187
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3704482151
Short name T611
Test name
Test status
Simulation time 345880566 ps
CPU time 14.96 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:32 PM PDT 24
Peak memory 218072 kb
Host smart-8748308a-3f96-457e-a8bb-dbe74f9daabf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704482151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3704482151
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1501397102
Short name T176
Test name
Test status
Simulation time 631790596 ps
CPU time 10.99 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:25 PM PDT 24
Peak memory 225948 kb
Host smart-e01b99d2-5fea-4456-a7c8-1e16bf8e1dfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501397102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1501397102
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3363435553
Short name T551
Test name
Test status
Simulation time 308727601 ps
CPU time 8.38 seconds
Started Jul 09 05:26:10 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 218184 kb
Host smart-cca8213c-c895-40e0-b566-cc3ef6dd7720
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363435553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3363435553
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1284706321
Short name T677
Test name
Test status
Simulation time 1379844966 ps
CPU time 10.11 seconds
Started Jul 09 05:26:18 PM PDT 24
Finished Jul 09 05:26:30 PM PDT 24
Peak memory 225896 kb
Host smart-f40f4897-6883-45bd-8bf4-30f3a1d723f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284706321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1284706321
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1661329456
Short name T711
Test name
Test status
Simulation time 79953885 ps
CPU time 1.99 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:16 PM PDT 24
Peak memory 214276 kb
Host smart-ac4c9e09-5104-4fc9-8f34-aaf9fe48207e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661329456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1661329456
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2943119399
Short name T732
Test name
Test status
Simulation time 155756698 ps
CPU time 22.05 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 250916 kb
Host smart-2512d5f7-d59a-45eb-a630-73b4295f3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943119399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2943119399
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2041778398
Short name T722
Test name
Test status
Simulation time 78941720 ps
CPU time 2.97 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:17 PM PDT 24
Peak memory 218132 kb
Host smart-cdea9fd3-0a13-4ea8-baa7-e80113e02b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041778398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2041778398
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1756293789
Short name T457
Test name
Test status
Simulation time 4262154116 ps
CPU time 94.1 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:27:49 PM PDT 24
Peak memory 274664 kb
Host smart-53a1bb1d-dd72-4f05-a5b9-a284514e0cda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756293789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1756293789
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2818336700
Short name T842
Test name
Test status
Simulation time 37969230 ps
CPU time 0.91 seconds
Started Jul 09 05:26:13 PM PDT 24
Finished Jul 09 05:26:15 PM PDT 24
Peak memory 212936 kb
Host smart-7e925be4-ecf0-45a2-b916-b182db99153f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818336700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2818336700
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.4247524843
Short name T417
Test name
Test status
Simulation time 16485164 ps
CPU time 1.11 seconds
Started Jul 09 05:26:16 PM PDT 24
Finished Jul 09 05:26:19 PM PDT 24
Peak memory 208956 kb
Host smart-4ac788a0-b481-45ed-b58f-502847b03de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247524843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4247524843
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3983113170
Short name T183
Test name
Test status
Simulation time 391789991 ps
CPU time 16.4 seconds
Started Jul 09 05:26:16 PM PDT 24
Finished Jul 09 05:26:34 PM PDT 24
Peak memory 218368 kb
Host smart-52e83870-1bc1-4cc8-90dd-70b49abe1c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983113170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3983113170
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.388579058
Short name T703
Test name
Test status
Simulation time 1125825171 ps
CPU time 14.57 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:32 PM PDT 24
Peak memory 217244 kb
Host smart-9ad8c3b9-0022-4b92-b956-185696905694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388579058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.388579058
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1232347834
Short name T288
Test name
Test status
Simulation time 2002344890 ps
CPU time 31.33 seconds
Started Jul 09 05:26:21 PM PDT 24
Finished Jul 09 05:26:54 PM PDT 24
Peak memory 225980 kb
Host smart-4e3fa917-e1b8-4f11-bcdb-413eea814191
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232347834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1232347834
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3567231242
Short name T433
Test name
Test status
Simulation time 309394136 ps
CPU time 4.43 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:18 PM PDT 24
Peak memory 221556 kb
Host smart-fa5fc5eb-5c9b-48f2-b72a-4e69124d2a37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567231242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3567231242
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2687975725
Short name T735
Test name
Test status
Simulation time 443119855 ps
CPU time 5.75 seconds
Started Jul 09 05:26:19 PM PDT 24
Finished Jul 09 05:26:26 PM PDT 24
Peak memory 217648 kb
Host smart-2cda2926-f4ae-4df3-b7b0-e58409f57cd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687975725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2687975725
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2580944935
Short name T766
Test name
Test status
Simulation time 5694118475 ps
CPU time 43.14 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:27:02 PM PDT 24
Peak memory 267632 kb
Host smart-db4bbdc3-023a-42f8-bca5-49f78504db8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580944935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2580944935
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2260205787
Short name T186
Test name
Test status
Simulation time 477914892 ps
CPU time 13.49 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:43 PM PDT 24
Peak memory 221832 kb
Host smart-656a5388-2cd3-4a16-bf37-b308b67ebd7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260205787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2260205787
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1399919197
Short name T651
Test name
Test status
Simulation time 104199505 ps
CPU time 3.19 seconds
Started Jul 09 05:26:18 PM PDT 24
Finished Jul 09 05:26:22 PM PDT 24
Peak memory 222268 kb
Host smart-61af5006-10b1-46b9-8c76-2c80af9c700e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399919197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1399919197
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.911457071
Short name T675
Test name
Test status
Simulation time 244549893 ps
CPU time 9.13 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:26 PM PDT 24
Peak memory 225948 kb
Host smart-180591d4-ceb4-4868-b473-e694f9a7c6f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911457071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.911457071
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.4120938549
Short name T31
Test name
Test status
Simulation time 588504550 ps
CPU time 15.43 seconds
Started Jul 09 05:26:18 PM PDT 24
Finished Jul 09 05:26:35 PM PDT 24
Peak memory 226000 kb
Host smart-43f00b84-3bfd-4c38-8c30-27af6bf03b52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120938549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.4120938549
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2916555591
Short name T460
Test name
Test status
Simulation time 295992150 ps
CPU time 7.21 seconds
Started Jul 09 05:26:21 PM PDT 24
Finished Jul 09 05:26:28 PM PDT 24
Peak memory 218148 kb
Host smart-832ddc40-90f5-4701-a56f-47e028eb0b05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916555591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2916555591
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1852832613
Short name T808
Test name
Test status
Simulation time 184000995 ps
CPU time 8.08 seconds
Started Jul 09 05:26:12 PM PDT 24
Finished Jul 09 05:26:21 PM PDT 24
Peak memory 224924 kb
Host smart-f60e9d0e-d34e-4d44-bc47-a0749d1572b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852832613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1852832613
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1685212684
Short name T467
Test name
Test status
Simulation time 550770582 ps
CPU time 2.6 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 217676 kb
Host smart-4cc492f3-fa94-447c-8b4d-2868a5ceb0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685212684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1685212684
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.226432340
Short name T399
Test name
Test status
Simulation time 303801250 ps
CPU time 33.07 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 250908 kb
Host smart-d8a9fb72-ca1e-441d-807c-a9849c6cc5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226432340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.226432340
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3372346888
Short name T822
Test name
Test status
Simulation time 50062450 ps
CPU time 2.96 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:22 PM PDT 24
Peak memory 222524 kb
Host smart-820f0d2b-fc59-489f-91d4-5bedb4eb712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372346888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3372346888
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3817985694
Short name T80
Test name
Test status
Simulation time 8209890958 ps
CPU time 91.9 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:27:49 PM PDT 24
Peak memory 219960 kb
Host smart-f1af75c2-2259-4516-9360-75f413bdf339
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817985694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3817985694
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1642133510
Short name T770
Test name
Test status
Simulation time 34239661 ps
CPU time 0.95 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:16 PM PDT 24
Peak memory 211952 kb
Host smart-c0c42888-6ee9-481e-aef8-24f0d03b7c08
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642133510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1642133510
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1184985505
Short name T658
Test name
Test status
Simulation time 25043287 ps
CPU time 1.38 seconds
Started Jul 09 05:26:22 PM PDT 24
Finished Jul 09 05:26:24 PM PDT 24
Peak memory 209008 kb
Host smart-e952ec24-493c-4979-8689-bf74d2acf340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184985505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1184985505
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1892636193
Short name T468
Test name
Test status
Simulation time 1348172251 ps
CPU time 12.87 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:32 PM PDT 24
Peak memory 218120 kb
Host smart-375c2cdd-134c-42cb-83b9-ba45763096c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892636193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1892636193
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1906207884
Short name T786
Test name
Test status
Simulation time 566004504 ps
CPU time 5.66 seconds
Started Jul 09 05:26:18 PM PDT 24
Finished Jul 09 05:26:25 PM PDT 24
Peak memory 217128 kb
Host smart-c6941364-3a11-466c-89f1-17a625cfbc8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906207884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1906207884
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3327639470
Short name T857
Test name
Test status
Simulation time 3907219445 ps
CPU time 35.74 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:54 PM PDT 24
Peak memory 226028 kb
Host smart-02f3ea82-0116-46f3-bc75-086be1cb8e74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327639470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3327639470
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4206492270
Short name T146
Test name
Test status
Simulation time 2025903888 ps
CPU time 13.49 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:33 PM PDT 24
Peak memory 218184 kb
Host smart-4e8d0bee-f12b-4eb2-ab92-579c7f53e79d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206492270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4206492270
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1726475769
Short name T848
Test name
Test status
Simulation time 530888733 ps
CPU time 2.98 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:22 PM PDT 24
Peak memory 217672 kb
Host smart-fb9d8637-c783-40f3-a071-51b3abfd60de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726475769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1726475769
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.4043507224
Short name T753
Test name
Test status
Simulation time 3323522169 ps
CPU time 28.74 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 250908 kb
Host smart-3eb8558d-6f5c-40c2-b4c7-82b6b4729f6b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043507224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.4043507224
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3237154464
Short name T777
Test name
Test status
Simulation time 424450014 ps
CPU time 11.35 seconds
Started Jul 09 05:26:16 PM PDT 24
Finished Jul 09 05:26:29 PM PDT 24
Peak memory 247664 kb
Host smart-60d77169-5f00-495f-812b-41a5902bf03a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237154464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3237154464
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1673505176
Short name T229
Test name
Test status
Simulation time 71911560 ps
CPU time 2.84 seconds
Started Jul 09 05:26:16 PM PDT 24
Finished Jul 09 05:26:21 PM PDT 24
Peak memory 218028 kb
Host smart-0f33ad20-cbc7-4bcc-a870-3ab8b328dc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673505176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1673505176
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3447813202
Short name T38
Test name
Test status
Simulation time 567726038 ps
CPU time 15.83 seconds
Started Jul 09 05:26:16 PM PDT 24
Finished Jul 09 05:26:34 PM PDT 24
Peak memory 219132 kb
Host smart-d8c91332-1760-4517-9a9b-03e4ba4c6572
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447813202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3447813202
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.307957495
Short name T425
Test name
Test status
Simulation time 594271311 ps
CPU time 14.12 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:33 PM PDT 24
Peak memory 225948 kb
Host smart-14f2c4e4-16d1-49fe-b0a1-28da8cf39c1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307957495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.307957495
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3319636178
Short name T367
Test name
Test status
Simulation time 2267125220 ps
CPU time 8.21 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:41 PM PDT 24
Peak memory 225852 kb
Host smart-066d8f61-505c-425f-ab92-8f5a11886c18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319636178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3319636178
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2879762291
Short name T419
Test name
Test status
Simulation time 166481455 ps
CPU time 7.43 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:24 PM PDT 24
Peak memory 225176 kb
Host smart-f823ef39-45c2-4ea4-aac6-604914ff1e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879762291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2879762291
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3061330992
Short name T860
Test name
Test status
Simulation time 48882795 ps
CPU time 2.39 seconds
Started Jul 09 05:26:16 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 214600 kb
Host smart-3302f262-1f55-454b-b6fe-5a1f2c57e544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061330992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3061330992
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.974896166
Short name T166
Test name
Test status
Simulation time 922029646 ps
CPU time 22.95 seconds
Started Jul 09 05:26:17 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 250872 kb
Host smart-7b41cd40-09d9-4915-8f05-e22f04e2b851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974896166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.974896166
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.696357185
Short name T251
Test name
Test status
Simulation time 302670666 ps
CPU time 8.13 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:25 PM PDT 24
Peak memory 247416 kb
Host smart-391fb66b-bbdc-4f52-9eb2-2157b00714d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696357185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.696357185
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1541459287
Short name T68
Test name
Test status
Simulation time 8685120434 ps
CPU time 77.13 seconds
Started Jul 09 05:26:21 PM PDT 24
Finished Jul 09 05:27:39 PM PDT 24
Peak memory 272388 kb
Host smart-08bcb6e8-c5e1-4e24-b69e-f75bb67137e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541459287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1541459287
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3571719753
Short name T480
Test name
Test status
Simulation time 44272425 ps
CPU time 0.92 seconds
Started Jul 09 05:26:16 PM PDT 24
Finished Jul 09 05:26:19 PM PDT 24
Peak memory 211700 kb
Host smart-131f648e-97a1-45f4-8a59-68c35bd81e45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571719753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3571719753
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1299189939
Short name T712
Test name
Test status
Simulation time 77655353 ps
CPU time 0.95 seconds
Started Jul 09 05:26:23 PM PDT 24
Finished Jul 09 05:26:24 PM PDT 24
Peak memory 208900 kb
Host smart-7d9102eb-979a-480f-b0f8-ce8d9eeafd95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299189939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1299189939
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.779883261
Short name T362
Test name
Test status
Simulation time 1152388735 ps
CPU time 12.6 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 218148 kb
Host smart-56023d8c-8de8-4087-9b87-17743d4a415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779883261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.779883261
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2570894509
Short name T475
Test name
Test status
Simulation time 464133061 ps
CPU time 8.83 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 216964 kb
Host smart-acb28289-fa6e-495c-8b17-28e434eaf81f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570894509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2570894509
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2544485462
Short name T841
Test name
Test status
Simulation time 5713337363 ps
CPU time 50.95 seconds
Started Jul 09 05:26:21 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 218908 kb
Host smart-b4eb7350-d6bb-4d85-81de-54a25929cb42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544485462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2544485462
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4023293139
Short name T585
Test name
Test status
Simulation time 607193077 ps
CPU time 6.29 seconds
Started Jul 09 05:26:18 PM PDT 24
Finished Jul 09 05:26:26 PM PDT 24
Peak memory 222896 kb
Host smart-dc4ee9eb-d061-4c1f-b729-1dbfdc32d3c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023293139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4023293139
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2844514315
Short name T87
Test name
Test status
Simulation time 5757640036 ps
CPU time 10.27 seconds
Started Jul 09 05:26:14 PM PDT 24
Finished Jul 09 05:26:27 PM PDT 24
Peak memory 217744 kb
Host smart-6aa41fa8-a6f8-40c1-89e9-23e74d3627e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844514315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2844514315
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2047694759
Short name T492
Test name
Test status
Simulation time 3241354098 ps
CPU time 67.17 seconds
Started Jul 09 05:26:21 PM PDT 24
Finished Jul 09 05:27:29 PM PDT 24
Peak memory 271008 kb
Host smart-b899334a-faf1-45b1-b0b3-000f38706c78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047694759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2047694759
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3385187553
Short name T237
Test name
Test status
Simulation time 2355896067 ps
CPU time 10.19 seconds
Started Jul 09 05:26:18 PM PDT 24
Finished Jul 09 05:26:30 PM PDT 24
Peak memory 218168 kb
Host smart-15bd281c-08ec-432b-9827-e3652b532235
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385187553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3385187553
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4090917031
Short name T721
Test name
Test status
Simulation time 130036705 ps
CPU time 2.06 seconds
Started Jul 09 05:26:22 PM PDT 24
Finished Jul 09 05:26:25 PM PDT 24
Peak memory 218228 kb
Host smart-2078e9da-e515-4203-9e9a-359fb4be4a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090917031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4090917031
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3904633420
Short name T443
Test name
Test status
Simulation time 247386880 ps
CPU time 9.64 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:37 PM PDT 24
Peak memory 226000 kb
Host smart-a1249556-e0bc-4382-9e11-95f35d12517e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904633420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3904633420
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1733911577
Short name T330
Test name
Test status
Simulation time 748130254 ps
CPU time 16.76 seconds
Started Jul 09 05:26:20 PM PDT 24
Finished Jul 09 05:26:37 PM PDT 24
Peak memory 226068 kb
Host smart-f37e3b96-ac6c-438b-a911-254eb612d9cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733911577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1733911577
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3642106346
Short name T306
Test name
Test status
Simulation time 1999892205 ps
CPU time 12.57 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:39 PM PDT 24
Peak memory 226000 kb
Host smart-c2984b31-3d12-47ca-8faf-eae718088122
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642106346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3642106346
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3789858842
Short name T580
Test name
Test status
Simulation time 986077021 ps
CPU time 10.84 seconds
Started Jul 09 05:26:19 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 225900 kb
Host smart-a008f744-c9c6-419e-83b4-17d4fcc083ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789858842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3789858842
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3932281167
Short name T552
Test name
Test status
Simulation time 47206457 ps
CPU time 2.65 seconds
Started Jul 09 05:26:25 PM PDT 24
Finished Jul 09 05:26:28 PM PDT 24
Peak memory 214600 kb
Host smart-fe41c2ba-7416-4b3b-92e8-18023812ee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932281167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3932281167
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2267704110
Short name T641
Test name
Test status
Simulation time 227246035 ps
CPU time 17.38 seconds
Started Jul 09 05:26:21 PM PDT 24
Finished Jul 09 05:26:39 PM PDT 24
Peak memory 250972 kb
Host smart-9af98d09-6605-4bc0-af8f-eba17a90ca7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267704110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2267704110
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2859829016
Short name T402
Test name
Test status
Simulation time 809940423 ps
CPU time 3.45 seconds
Started Jul 09 05:26:21 PM PDT 24
Finished Jul 09 05:26:26 PM PDT 24
Peak memory 222236 kb
Host smart-5a99c756-ed5f-47da-80e3-154ff64ecbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859829016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2859829016
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.723039357
Short name T376
Test name
Test status
Simulation time 83220290408 ps
CPU time 250.44 seconds
Started Jul 09 05:26:21 PM PDT 24
Finished Jul 09 05:30:32 PM PDT 24
Peak memory 250892 kb
Host smart-3cfd1928-e727-45a2-95a5-74f371327532
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723039357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.723039357
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3927606703
Short name T820
Test name
Test status
Simulation time 19613423 ps
CPU time 1.37 seconds
Started Jul 09 05:26:15 PM PDT 24
Finished Jul 09 05:26:19 PM PDT 24
Peak memory 217584 kb
Host smart-2efd7021-18d8-4d3f-845f-3576d0a78bcf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927606703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3927606703
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3726426451
Short name T93
Test name
Test status
Simulation time 27263974 ps
CPU time 1.12 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:34 PM PDT 24
Peak memory 208900 kb
Host smart-fd4b8c01-983e-42e1-8993-f9bf9c9909ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726426451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3726426451
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1115606053
Short name T248
Test name
Test status
Simulation time 1356223484 ps
CPU time 13.52 seconds
Started Jul 09 05:26:19 PM PDT 24
Finished Jul 09 05:26:33 PM PDT 24
Peak memory 218156 kb
Host smart-4a1a2cbe-9c0a-468a-ad08-d7f6a26b5a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115606053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1115606053
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2999016130
Short name T832
Test name
Test status
Simulation time 930272399 ps
CPU time 22.48 seconds
Started Jul 09 05:26:23 PM PDT 24
Finished Jul 09 05:26:46 PM PDT 24
Peak memory 217236 kb
Host smart-d12934bf-378a-4f31-960b-c3636c27d231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999016130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2999016130
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1643256711
Short name T313
Test name
Test status
Simulation time 27238950339 ps
CPU time 29.11 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:27:00 PM PDT 24
Peak memory 225952 kb
Host smart-44b18973-9f40-44f0-af7d-4a545858493e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643256711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1643256711
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.385537610
Short name T657
Test name
Test status
Simulation time 80346042 ps
CPU time 2.02 seconds
Started Jul 09 05:26:24 PM PDT 24
Finished Jul 09 05:26:26 PM PDT 24
Peak memory 218160 kb
Host smart-f00e510a-e877-41d8-acf8-30e6b3b78ad3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385537610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.385537610
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.114382110
Short name T291
Test name
Test status
Simulation time 1248397312 ps
CPU time 5.06 seconds
Started Jul 09 05:26:24 PM PDT 24
Finished Jul 09 05:26:29 PM PDT 24
Peak memory 217512 kb
Host smart-e908b93c-4793-4301-8e92-c69554ff7b2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114382110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
114382110
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.342194254
Short name T510
Test name
Test status
Simulation time 1782171025 ps
CPU time 47.04 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:27:20 PM PDT 24
Peak memory 267264 kb
Host smart-09625726-b1ed-4309-ab01-200e5cd799c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342194254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.342194254
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.11776222
Short name T599
Test name
Test status
Simulation time 3927709053 ps
CPU time 9.78 seconds
Started Jul 09 05:26:29 PM PDT 24
Finished Jul 09 05:26:45 PM PDT 24
Peak memory 250636 kb
Host smart-942b09eb-8ecc-4e63-b618-a1beed30d462
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_j
tag_state_post_trans.11776222
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1168380349
Short name T338
Test name
Test status
Simulation time 84735178 ps
CPU time 3.72 seconds
Started Jul 09 05:26:23 PM PDT 24
Finished Jul 09 05:26:27 PM PDT 24
Peak memory 222452 kb
Host smart-88c51631-ac17-43b5-b3c7-56ee4abb0e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168380349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1168380349
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1476273019
Short name T759
Test name
Test status
Simulation time 4565304385 ps
CPU time 12.15 seconds
Started Jul 09 05:26:34 PM PDT 24
Finished Jul 09 05:26:48 PM PDT 24
Peak memory 225768 kb
Host smart-f63dbff3-51fc-4324-b2ba-393ae2738d1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476273019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1476273019
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1635621002
Short name T818
Test name
Test status
Simulation time 302776809 ps
CPU time 8.31 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:41 PM PDT 24
Peak memory 225964 kb
Host smart-5278f510-1955-4d4c-abb3-b51cac44ceb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635621002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1635621002
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3409891249
Short name T346
Test name
Test status
Simulation time 923896532 ps
CPU time 9.95 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:37 PM PDT 24
Peak memory 225984 kb
Host smart-22f752df-caf8-4158-bfb9-e7173103521a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409891249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3409891249
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2971750834
Short name T50
Test name
Test status
Simulation time 845891247 ps
CPU time 9.83 seconds
Started Jul 09 05:26:23 PM PDT 24
Finished Jul 09 05:26:33 PM PDT 24
Peak memory 225976 kb
Host smart-4ecece86-5d45-49c4-aa8f-ae6c96b2c052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971750834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2971750834
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1095919326
Short name T733
Test name
Test status
Simulation time 81427699 ps
CPU time 2.13 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 214312 kb
Host smart-b334bf8d-b5f9-4194-99c8-2d84a28be3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095919326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1095919326
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3163705762
Short name T778
Test name
Test status
Simulation time 342572259 ps
CPU time 25.09 seconds
Started Jul 09 05:26:29 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 250948 kb
Host smart-3af006ba-80ab-46c3-9c98-2d7e05105209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163705762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3163705762
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3520553486
Short name T717
Test name
Test status
Simulation time 221415515 ps
CPU time 3.58 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 222180 kb
Host smart-58659f47-87ab-4ffb-a170-cb5a1d6b21fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520553486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3520553486
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2541043450
Short name T437
Test name
Test status
Simulation time 17610126166 ps
CPU time 80.68 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:27:51 PM PDT 24
Peak memory 250992 kb
Host smart-933e29d4-aad8-4242-99df-8b690895fb35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541043450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2541043450
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.457354537
Short name T318
Test name
Test status
Simulation time 100469480 ps
CPU time 0.96 seconds
Started Jul 09 05:26:24 PM PDT 24
Finished Jul 09 05:26:25 PM PDT 24
Peak memory 212904 kb
Host smart-fd49e86b-6832-45be-abb6-f54671cb937f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457354537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.457354537
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3336988439
Short name T77
Test name
Test status
Simulation time 49869982 ps
CPU time 1.04 seconds
Started Jul 09 05:26:27 PM PDT 24
Finished Jul 09 05:26:29 PM PDT 24
Peak memory 208912 kb
Host smart-4d0eb15b-c66f-4b1a-8083-7cb310d3b35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336988439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3336988439
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.91056674
Short name T319
Test name
Test status
Simulation time 1132023293 ps
CPU time 21.83 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:49 PM PDT 24
Peak memory 218136 kb
Host smart-3a9a8d6c-a917-4bf9-80e5-95d02c09440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91056674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.91056674
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.372466820
Short name T793
Test name
Test status
Simulation time 164806327 ps
CPU time 1.16 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 217156 kb
Host smart-da287888-cc8a-465c-825c-b31cd13213ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372466820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.372466820
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.229925348
Short name T758
Test name
Test status
Simulation time 6054024277 ps
CPU time 24.12 seconds
Started Jul 09 05:26:25 PM PDT 24
Finished Jul 09 05:26:50 PM PDT 24
Peak memory 226052 kb
Host smart-d966330d-367d-40be-804d-291891694958
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229925348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.229925348
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.415189054
Short name T686
Test name
Test status
Simulation time 447393292 ps
CPU time 13.63 seconds
Started Jul 09 05:26:27 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 218148 kb
Host smart-953c8307-0a06-45a9-844e-176a9385bd7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415189054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.415189054
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.4064686875
Short name T396
Test name
Test status
Simulation time 618231677 ps
CPU time 9.45 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 217644 kb
Host smart-0ea1a181-1621-4b1c-b935-63583838fcf0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064686875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.4064686875
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3087554802
Short name T253
Test name
Test status
Simulation time 2309924121 ps
CPU time 51.04 seconds
Started Jul 09 05:26:34 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 252096 kb
Host smart-2796338f-0fd1-460d-83f3-a0a6b9036402
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087554802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3087554802
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2567693589
Short name T302
Test name
Test status
Simulation time 432144525 ps
CPU time 13.54 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:43 PM PDT 24
Peak memory 250568 kb
Host smart-c5c8b872-46a6-4808-8d98-e4e937ae6ee5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567693589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2567693589
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2325928821
Short name T403
Test name
Test status
Simulation time 447956517 ps
CPU time 2.3 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:28 PM PDT 24
Peak memory 218084 kb
Host smart-ac970f8d-48de-405f-8cb7-5e5b1f51c260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325928821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2325928821
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.962305447
Short name T258
Test name
Test status
Simulation time 691010269 ps
CPU time 13.32 seconds
Started Jul 09 05:26:25 PM PDT 24
Finished Jul 09 05:26:39 PM PDT 24
Peak memory 225968 kb
Host smart-a702a6f0-f8fc-408b-93ff-21cf8d0d8c05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962305447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.962305447
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2499645294
Short name T670
Test name
Test status
Simulation time 2143512381 ps
CPU time 13.43 seconds
Started Jul 09 05:26:31 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 225900 kb
Host smart-b3f4681a-b2e3-46be-972f-cae506b1a1c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499645294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2499645294
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2672434086
Short name T259
Test name
Test status
Simulation time 369923535 ps
CPU time 13.66 seconds
Started Jul 09 05:26:25 PM PDT 24
Finished Jul 09 05:26:39 PM PDT 24
Peak memory 218112 kb
Host smart-92becb30-7415-4097-a27f-cf586734977f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672434086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2672434086
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.204282337
Short name T342
Test name
Test status
Simulation time 354551903 ps
CPU time 9.27 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 218328 kb
Host smart-977b647a-cf25-4c99-89d7-666b681d174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204282337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.204282337
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1213446956
Short name T689
Test name
Test status
Simulation time 183550794 ps
CPU time 2.97 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:30 PM PDT 24
Peak memory 214652 kb
Host smart-3db63036-83fc-4797-87b7-9433a5db1c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213446956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1213446956
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2115456678
Short name T771
Test name
Test status
Simulation time 1006934043 ps
CPU time 26.75 seconds
Started Jul 09 05:26:24 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 250896 kb
Host smart-6602a51f-b2d7-4373-8528-bc46af566665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115456678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2115456678
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3352234035
Short name T581
Test name
Test status
Simulation time 854871676 ps
CPU time 8.12 seconds
Started Jul 09 05:26:24 PM PDT 24
Finished Jul 09 05:26:33 PM PDT 24
Peak memory 250656 kb
Host smart-fc1647d5-8465-4ca7-9c94-db153091a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352234035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3352234035
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.223135066
Short name T517
Test name
Test status
Simulation time 22429260110 ps
CPU time 185.78 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:29:32 PM PDT 24
Peak memory 250888 kb
Host smart-1528fd3f-57cf-49ba-8c08-66b6d3ea8bd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223135066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.223135066
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.11874162
Short name T724
Test name
Test status
Simulation time 12699966 ps
CPU time 0.86 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:33 PM PDT 24
Peak memory 211808 kb
Host smart-0d0bec4b-a552-476e-8f41-44f13eb9034a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11874162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_volatile_unlock_smoke.11874162
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2343268624
Short name T289
Test name
Test status
Simulation time 57662490 ps
CPU time 1.07 seconds
Started Jul 09 05:25:41 PM PDT 24
Finished Jul 09 05:25:43 PM PDT 24
Peak memory 209000 kb
Host smart-21ffc441-b237-465f-a083-ab9e5b34cd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343268624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2343268624
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3534383975
Short name T216
Test name
Test status
Simulation time 30645740 ps
CPU time 0.86 seconds
Started Jul 09 05:25:35 PM PDT 24
Finished Jul 09 05:25:36 PM PDT 24
Peak memory 209164 kb
Host smart-8c66a481-101a-460a-93b5-9ef5a73aa873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534383975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3534383975
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.4155172796
Short name T668
Test name
Test status
Simulation time 1533644317 ps
CPU time 11.7 seconds
Started Jul 09 05:25:30 PM PDT 24
Finished Jul 09 05:25:42 PM PDT 24
Peak memory 225992 kb
Host smart-8bba9e28-c31d-4c93-8496-889180ad6dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155172796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.4155172796
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3042634896
Short name T21
Test name
Test status
Simulation time 460689168 ps
CPU time 12.23 seconds
Started Jul 09 05:25:34 PM PDT 24
Finished Jul 09 05:25:46 PM PDT 24
Peak memory 217408 kb
Host smart-9e9b9558-4358-4019-8ef0-780f10ee2f2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042634896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3042634896
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3010522254
Short name T626
Test name
Test status
Simulation time 3522019599 ps
CPU time 47.52 seconds
Started Jul 09 05:25:41 PM PDT 24
Finished Jul 09 05:26:29 PM PDT 24
Peak memory 219940 kb
Host smart-b3002060-7f05-4013-81fc-272493b8faf5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010522254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3010522254
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2196747929
Short name T265
Test name
Test status
Simulation time 489434218 ps
CPU time 5.18 seconds
Started Jul 09 05:25:30 PM PDT 24
Finished Jul 09 05:25:36 PM PDT 24
Peak memory 217616 kb
Host smart-9ba2363e-7fa8-41ee-a913-2308a52736c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196747929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
196747929
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1538615454
Short name T28
Test name
Test status
Simulation time 1859215417 ps
CPU time 4.21 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:37 PM PDT 24
Peak memory 218124 kb
Host smart-25bd0073-4d64-4972-af8b-95dad23e3548
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538615454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1538615454
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1834852588
Short name T356
Test name
Test status
Simulation time 3934846874 ps
CPU time 25.66 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:14 PM PDT 24
Peak memory 217584 kb
Host smart-7f9c1cd9-533c-4507-9595-2d605a9aa6e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834852588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1834852588
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.632072421
Short name T680
Test name
Test status
Simulation time 440533236 ps
CPU time 6.39 seconds
Started Jul 09 05:25:33 PM PDT 24
Finished Jul 09 05:25:40 PM PDT 24
Peak memory 217592 kb
Host smart-e72e68e2-6eb0-4266-b25a-bd9fab2b16ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632072421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.632072421
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2745003113
Short name T354
Test name
Test status
Simulation time 4259602183 ps
CPU time 72.19 seconds
Started Jul 09 05:25:53 PM PDT 24
Finished Jul 09 05:27:07 PM PDT 24
Peak memory 283708 kb
Host smart-cbbc5359-223e-4702-a52d-8930f91dd82b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745003113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2745003113
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.411916328
Short name T802
Test name
Test status
Simulation time 4643222409 ps
CPU time 18.89 seconds
Started Jul 09 05:25:35 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 250976 kb
Host smart-ebfe9681-3010-4653-a3b9-952377adc3e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411916328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.411916328
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1614677865
Short name T731
Test name
Test status
Simulation time 74665576 ps
CPU time 2.5 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:35 PM PDT 24
Peak memory 218172 kb
Host smart-7e5ca77e-65fe-4ffe-8a02-9c073614b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614677865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1614677865
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3900129717
Short name T81
Test name
Test status
Simulation time 2738024888 ps
CPU time 11.96 seconds
Started Jul 09 05:25:35 PM PDT 24
Finished Jul 09 05:25:48 PM PDT 24
Peak memory 217672 kb
Host smart-9826d9eb-e8f6-481f-8341-236bd8c6afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900129717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3900129717
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1556386563
Short name T56
Test name
Test status
Simulation time 2731417605 ps
CPU time 38.69 seconds
Started Jul 09 05:25:31 PM PDT 24
Finished Jul 09 05:26:10 PM PDT 24
Peak memory 282196 kb
Host smart-06038bca-26bc-4e60-9b91-844de0a4d540
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556386563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1556386563
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2005564676
Short name T366
Test name
Test status
Simulation time 2233525530 ps
CPU time 13.4 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:47 PM PDT 24
Peak memory 226060 kb
Host smart-40fa0356-47a1-46c8-b092-beadd2bb7909
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005564676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2005564676
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1435017729
Short name T382
Test name
Test status
Simulation time 286806811 ps
CPU time 11.7 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:25:44 PM PDT 24
Peak memory 218176 kb
Host smart-27f94e29-4ef2-4bc5-84d1-6be0a87fd75c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435017729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
435017729
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1483454822
Short name T614
Test name
Test status
Simulation time 714515179 ps
CPU time 7.29 seconds
Started Jul 09 05:25:50 PM PDT 24
Finished Jul 09 05:25:59 PM PDT 24
Peak memory 218096 kb
Host smart-097fe0b4-f3f4-4ca7-bab0-83e8f372bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483454822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1483454822
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1508255526
Short name T66
Test name
Test status
Simulation time 33757857 ps
CPU time 1.68 seconds
Started Jul 09 05:25:26 PM PDT 24
Finished Jul 09 05:25:29 PM PDT 24
Peak memory 217604 kb
Host smart-fe75efbf-563b-40fc-984a-3d5ae19647fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508255526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1508255526
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2675489090
Short name T395
Test name
Test status
Simulation time 287680571 ps
CPU time 33.74 seconds
Started Jul 09 05:25:31 PM PDT 24
Finished Jul 09 05:26:05 PM PDT 24
Peak memory 247212 kb
Host smart-3fcd123b-22ac-4247-893c-5de22c40c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675489090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2675489090
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.422455973
Short name T301
Test name
Test status
Simulation time 58741701 ps
CPU time 7.32 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:25:36 PM PDT 24
Peak memory 250888 kb
Host smart-173ad5a7-820f-45be-8158-5d80a14ae0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422455973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.422455973
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.4015813235
Short name T664
Test name
Test status
Simulation time 41716920231 ps
CPU time 146.81 seconds
Started Jul 09 05:25:32 PM PDT 24
Finished Jul 09 05:27:59 PM PDT 24
Peak memory 283708 kb
Host smart-f866df4d-c4fe-4efb-ad3e-af9afa36fe26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015813235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.4015813235
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.314666450
Short name T361
Test name
Test status
Simulation time 22292109 ps
CPU time 1.01 seconds
Started Jul 09 05:25:28 PM PDT 24
Finished Jul 09 05:25:30 PM PDT 24
Peak memory 212844 kb
Host smart-09e6d8ef-11c8-4e37-bdb4-8097baddb0c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314666450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.314666450
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1305344680
Short name T616
Test name
Test status
Simulation time 16884474 ps
CPU time 1.04 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 208840 kb
Host smart-730fd0f2-9eab-404b-a1da-12ddc9af424f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305344680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1305344680
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2557796402
Short name T488
Test name
Test status
Simulation time 1976224280 ps
CPU time 14.92 seconds
Started Jul 09 05:26:27 PM PDT 24
Finished Jul 09 05:26:43 PM PDT 24
Peak memory 218188 kb
Host smart-ee05786f-8809-4d8a-aedb-dd407ec8da8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557796402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2557796402
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2618808439
Short name T528
Test name
Test status
Simulation time 2072060388 ps
CPU time 4.84 seconds
Started Jul 09 05:26:31 PM PDT 24
Finished Jul 09 05:26:38 PM PDT 24
Peak memory 216900 kb
Host smart-72f18acc-45b7-4ca7-bd59-ef4ae283ba13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618808439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2618808439
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.833820594
Short name T298
Test name
Test status
Simulation time 26466231 ps
CPU time 1.84 seconds
Started Jul 09 05:26:26 PM PDT 24
Finished Jul 09 05:26:29 PM PDT 24
Peak memory 218140 kb
Host smart-305003c7-e28a-4188-8359-0f437e94e9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833820594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.833820594
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2602503852
Short name T349
Test name
Test status
Simulation time 270828895 ps
CPU time 12.26 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:45 PM PDT 24
Peak memory 225972 kb
Host smart-ff316ce3-bc12-4bf1-92e6-75e05b0d9afb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602503852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2602503852
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4164972931
Short name T307
Test name
Test status
Simulation time 457257299 ps
CPU time 7.37 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:26:43 PM PDT 24
Peak memory 218192 kb
Host smart-156448fc-a7e3-4671-a972-c723582b017a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164972931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
4164972931
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2483747410
Short name T375
Test name
Test status
Simulation time 2131682657 ps
CPU time 12.23 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:44 PM PDT 24
Peak memory 225968 kb
Host smart-7b056cd6-1557-4b0b-b19d-91f4198baeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483747410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2483747410
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.33040104
Short name T624
Test name
Test status
Simulation time 188520856 ps
CPU time 2.84 seconds
Started Jul 09 05:26:33 PM PDT 24
Finished Jul 09 05:26:38 PM PDT 24
Peak memory 214676 kb
Host smart-8d1b6746-57c0-43df-91b8-2eeb5004f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33040104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.33040104
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3770783658
Short name T549
Test name
Test status
Simulation time 187493213 ps
CPU time 17.08 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:49 PM PDT 24
Peak memory 250916 kb
Host smart-881491ea-c414-41c8-bd19-327a2ec9c4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770783658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3770783658
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1581794415
Short name T369
Test name
Test status
Simulation time 47872990 ps
CPU time 3.19 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:33 PM PDT 24
Peak memory 218056 kb
Host smart-1307475c-ce20-4d54-88ec-9367ebbadb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581794415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1581794415
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2910170693
Short name T537
Test name
Test status
Simulation time 29342854595 ps
CPU time 153.1 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:29:09 PM PDT 24
Peak memory 276700 kb
Host smart-5958f883-27b9-4e16-88a4-4cb682c5c6b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910170693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2910170693
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2857143782
Short name T596
Test name
Test status
Simulation time 15837453 ps
CPU time 0.94 seconds
Started Jul 09 05:26:29 PM PDT 24
Finished Jul 09 05:26:32 PM PDT 24
Peak memory 211892 kb
Host smart-696025b2-3ce7-459b-84d8-4150ae582fc3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857143782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2857143782
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.259642995
Short name T100
Test name
Test status
Simulation time 46901332 ps
CPU time 0.82 seconds
Started Jul 09 05:26:39 PM PDT 24
Finished Jul 09 05:26:41 PM PDT 24
Peak memory 208752 kb
Host smart-a5160e79-f81f-40ca-a2a7-ec3f2c945044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259642995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.259642995
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2741809639
Short name T569
Test name
Test status
Simulation time 1263303165 ps
CPU time 8.86 seconds
Started Jul 09 05:26:27 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 217152 kb
Host smart-49dd2880-fa32-452c-a0f4-0ca8e165b58f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741809639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2741809639
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.356699824
Short name T539
Test name
Test status
Simulation time 36894497 ps
CPU time 2.02 seconds
Started Jul 09 05:26:29 PM PDT 24
Finished Jul 09 05:26:34 PM PDT 24
Peak memory 218000 kb
Host smart-9c1b8921-439f-48e8-a183-393576ff31fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356699824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.356699824
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3607525409
Short name T441
Test name
Test status
Simulation time 905318076 ps
CPU time 11.6 seconds
Started Jul 09 05:26:32 PM PDT 24
Finished Jul 09 05:26:46 PM PDT 24
Peak memory 225892 kb
Host smart-caffc6a5-ab91-47b3-a1b8-a2148ab767f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607525409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3607525409
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1890897177
Short name T548
Test name
Test status
Simulation time 288710288 ps
CPU time 9.28 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:26:45 PM PDT 24
Peak memory 218196 kb
Host smart-8df19b2d-20da-4a50-98ce-d3028c580c1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890897177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1890897177
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.306803184
Short name T639
Test name
Test status
Simulation time 885594423 ps
CPU time 12.81 seconds
Started Jul 09 05:26:29 PM PDT 24
Finished Jul 09 05:26:44 PM PDT 24
Peak memory 218256 kb
Host smart-f9532b00-1452-4986-8b0c-ef944b1ab937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306803184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.306803184
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.877917161
Short name T348
Test name
Test status
Simulation time 113676978 ps
CPU time 2.36 seconds
Started Jul 09 05:26:28 PM PDT 24
Finished Jul 09 05:26:33 PM PDT 24
Peak memory 217544 kb
Host smart-3ec35e62-576c-4e71-89bd-f77033b60f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877917161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.877917161
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2031039470
Short name T101
Test name
Test status
Simulation time 256512949 ps
CPU time 29.5 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:27:02 PM PDT 24
Peak memory 250916 kb
Host smart-a05d966b-73df-4f53-a03a-2dcc9cf1dda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031039470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2031039470
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.4008757702
Short name T594
Test name
Test status
Simulation time 75013918 ps
CPU time 5.83 seconds
Started Jul 09 05:26:34 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 246324 kb
Host smart-a28f8fde-0688-489a-bcc0-f12f6711f24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008757702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.4008757702
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2243085253
Short name T1
Test name
Test status
Simulation time 7034679617 ps
CPU time 52.48 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 276364 kb
Host smart-4d7bb265-4e57-4edd-8c4b-1e69befa5c59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243085253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2243085253
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2802987995
Short name T617
Test name
Test status
Simulation time 25452034 ps
CPU time 0.85 seconds
Started Jul 09 05:26:29 PM PDT 24
Finished Jul 09 05:26:32 PM PDT 24
Peak memory 211804 kb
Host smart-f648c4e5-1ac8-4b33-82e0-be8f98a9121d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802987995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2802987995
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1972954790
Short name T412
Test name
Test status
Simulation time 18952231 ps
CPU time 0.86 seconds
Started Jul 09 05:26:32 PM PDT 24
Finished Jul 09 05:26:35 PM PDT 24
Peak memory 208816 kb
Host smart-34e346ce-310e-4069-9e29-3735ccb990fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972954790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1972954790
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1740246270
Short name T814
Test name
Test status
Simulation time 599509833 ps
CPU time 20.96 seconds
Started Jul 09 05:26:31 PM PDT 24
Finished Jul 09 05:26:54 PM PDT 24
Peak memory 218184 kb
Host smart-a9a6ffe6-35ed-4ec7-a21c-6f635e9f2206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740246270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1740246270
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.4204298769
Short name T501
Test name
Test status
Simulation time 620850117 ps
CPU time 4.22 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:26:41 PM PDT 24
Peak memory 217468 kb
Host smart-724e233f-f73b-41e8-a524-7fdebee477a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204298769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.4204298769
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.672867660
Short name T761
Test name
Test status
Simulation time 315527825 ps
CPU time 3.17 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:26:35 PM PDT 24
Peak memory 218052 kb
Host smart-740b0121-e7a3-4380-8d5d-c5ec6f65486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672867660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.672867660
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.320625596
Short name T39
Test name
Test status
Simulation time 1129881747 ps
CPU time 12.71 seconds
Started Jul 09 05:26:33 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 225840 kb
Host smart-a6b2d2a1-b77b-4b19-ae7a-5e7714b01352
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320625596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.320625596
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3016633647
Short name T619
Test name
Test status
Simulation time 2627298286 ps
CPU time 16.76 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:26:53 PM PDT 24
Peak memory 226056 kb
Host smart-c032153a-4d6e-40f3-9405-7f5bf4aeeb22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016633647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3016633647
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.4133582132
Short name T769
Test name
Test status
Simulation time 1016813411 ps
CPU time 7.82 seconds
Started Jul 09 05:26:43 PM PDT 24
Finished Jul 09 05:26:52 PM PDT 24
Peak memory 225948 kb
Host smart-b9a44a8a-28a5-4a48-b3ac-9438e9faa8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133582132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.4133582132
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1997140813
Short name T519
Test name
Test status
Simulation time 31504639 ps
CPU time 2.74 seconds
Started Jul 09 05:26:33 PM PDT 24
Finished Jul 09 05:26:38 PM PDT 24
Peak memory 214484 kb
Host smart-0b0ab901-a6c7-488a-92dc-3f4e3a62876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997140813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1997140813
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1485084592
Short name T532
Test name
Test status
Simulation time 763686619 ps
CPU time 29.62 seconds
Started Jul 09 05:26:36 PM PDT 24
Finished Jul 09 05:27:07 PM PDT 24
Peak memory 250948 kb
Host smart-e7e9c1b2-a761-4d55-ae6e-c355da0d1e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485084592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1485084592
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1259268190
Short name T420
Test name
Test status
Simulation time 506712018 ps
CPU time 7.66 seconds
Started Jul 09 05:26:31 PM PDT 24
Finished Jul 09 05:26:41 PM PDT 24
Peak memory 250940 kb
Host smart-b5133805-b571-46b4-92ff-904e64ae7eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259268190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1259268190
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2035257071
Short name T650
Test name
Test status
Simulation time 10099883093 ps
CPU time 95.31 seconds
Started Jul 09 05:26:33 PM PDT 24
Finished Jul 09 05:28:10 PM PDT 24
Peak memory 279648 kb
Host smart-3db5d1d8-a900-490f-85c6-f877f4425802
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035257071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2035257071
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3280013159
Short name T310
Test name
Test status
Simulation time 26056196 ps
CPU time 0.88 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:26:37 PM PDT 24
Peak memory 211692 kb
Host smart-8f75879a-f938-42bb-a182-bbb698e4c08a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280013159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3280013159
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3138426973
Short name T858
Test name
Test status
Simulation time 118645681 ps
CPU time 0.95 seconds
Started Jul 09 05:26:45 PM PDT 24
Finished Jul 09 05:26:48 PM PDT 24
Peak memory 208876 kb
Host smart-754ded57-7076-4f79-a996-ca11e59dc4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138426973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3138426973
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1447646717
Short name T660
Test name
Test status
Simulation time 1532927001 ps
CPU time 13.75 seconds
Started Jul 09 05:26:33 PM PDT 24
Finished Jul 09 05:26:48 PM PDT 24
Peak memory 218116 kb
Host smart-bbf2b4f5-3e91-48de-b1d5-a7a7e78e5277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447646717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1447646717
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3501712359
Short name T19
Test name
Test status
Simulation time 583401702 ps
CPU time 4.6 seconds
Started Jul 09 05:26:32 PM PDT 24
Finished Jul 09 05:26:39 PM PDT 24
Peak memory 216924 kb
Host smart-66f78979-7d4f-409d-a051-6ea1c5c78932
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501712359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3501712359
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.4160870839
Short name T645
Test name
Test status
Simulation time 92634115 ps
CPU time 1.78 seconds
Started Jul 09 05:26:36 PM PDT 24
Finished Jul 09 05:26:39 PM PDT 24
Peak memory 218164 kb
Host smart-625f9fc9-d60d-42b9-b2b6-e2747911e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160870839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.4160870839
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1164524330
Short name T622
Test name
Test status
Simulation time 323357381 ps
CPU time 12.24 seconds
Started Jul 09 05:26:37 PM PDT 24
Finished Jul 09 05:26:50 PM PDT 24
Peak memory 218752 kb
Host smart-52c2024d-9d38-4be6-898e-4756994f90b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164524330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1164524330
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1608879670
Short name T829
Test name
Test status
Simulation time 3928782757 ps
CPU time 10 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:26:46 PM PDT 24
Peak memory 225980 kb
Host smart-a2ea49cf-dcfc-4a13-999d-e1c4255a27b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608879670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1608879670
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3887074374
Short name T246
Test name
Test status
Simulation time 4839999994 ps
CPU time 16.24 seconds
Started Jul 09 05:26:36 PM PDT 24
Finished Jul 09 05:26:54 PM PDT 24
Peak memory 218276 kb
Host smart-38a14441-1433-438b-856d-134b8fb6cf4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887074374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3887074374
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1831008578
Short name T423
Test name
Test status
Simulation time 359470528 ps
CPU time 9.32 seconds
Started Jul 09 05:26:33 PM PDT 24
Finished Jul 09 05:26:44 PM PDT 24
Peak memory 218264 kb
Host smart-febd56c8-52b7-4c3b-9a23-8ac1564a4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831008578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1831008578
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3841989348
Short name T148
Test name
Test status
Simulation time 111783044 ps
CPU time 2.72 seconds
Started Jul 09 05:26:29 PM PDT 24
Finished Jul 09 05:26:34 PM PDT 24
Peak memory 217920 kb
Host smart-7cbe6c70-315f-46d3-954f-9ac886ec0bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841989348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3841989348
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3693610743
Short name T280
Test name
Test status
Simulation time 361005570 ps
CPU time 35.3 seconds
Started Jul 09 05:26:30 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 250828 kb
Host smart-cd18c853-a23f-46f4-a6db-60defcc1bf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693610743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3693610743
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.979182532
Short name T350
Test name
Test status
Simulation time 555030872 ps
CPU time 3.19 seconds
Started Jul 09 05:26:32 PM PDT 24
Finished Jul 09 05:26:37 PM PDT 24
Peak memory 222004 kb
Host smart-b194a427-778f-4315-be9c-2ffd63ba6bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979182532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.979182532
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3771768923
Short name T570
Test name
Test status
Simulation time 1680157065 ps
CPU time 59.35 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:27:36 PM PDT 24
Peak memory 227552 kb
Host smart-f6f8f8d2-6600-4c72-a663-cf8fe49a9cc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771768923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3771768923
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3245325942
Short name T268
Test name
Test status
Simulation time 44384280 ps
CPU time 1 seconds
Started Jul 09 05:26:31 PM PDT 24
Finished Jul 09 05:26:35 PM PDT 24
Peak memory 211816 kb
Host smart-a5435504-ab53-4f33-a95e-3d6dfef87b54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245325942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3245325942
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2642807731
Short name T275
Test name
Test status
Simulation time 12507885 ps
CPU time 0.85 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 208680 kb
Host smart-4e694ac6-386b-4fde-bcf4-f5df5e11eae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642807731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2642807731
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2226264581
Short name T184
Test name
Test status
Simulation time 944829063 ps
CPU time 8.51 seconds
Started Jul 09 05:26:45 PM PDT 24
Finished Jul 09 05:26:54 PM PDT 24
Peak memory 218184 kb
Host smart-90f9e050-f247-4efd-b86f-19e429569d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226264581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2226264581
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3570039812
Short name T459
Test name
Test status
Simulation time 445540576 ps
CPU time 12.29 seconds
Started Jul 09 05:26:37 PM PDT 24
Finished Jul 09 05:26:50 PM PDT 24
Peak memory 217372 kb
Host smart-72778359-bfe2-4af4-9336-43385461fe9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570039812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3570039812
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3058350846
Short name T427
Test name
Test status
Simulation time 79778504 ps
CPU time 3.09 seconds
Started Jul 09 05:26:36 PM PDT 24
Finished Jul 09 05:26:40 PM PDT 24
Peak memory 222304 kb
Host smart-0d948721-f476-4681-950b-9dfb68c1f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058350846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3058350846
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2132881605
Short name T598
Test name
Test status
Simulation time 1151161633 ps
CPU time 11.14 seconds
Started Jul 09 05:26:40 PM PDT 24
Finished Jul 09 05:26:52 PM PDT 24
Peak memory 225988 kb
Host smart-d02a71d7-1343-41fb-942b-46e62c3268a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132881605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2132881605
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1025286647
Short name T655
Test name
Test status
Simulation time 315845151 ps
CPU time 8.99 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:59 PM PDT 24
Peak memory 225872 kb
Host smart-d88d947d-7e46-4b54-878b-903e2a59c65c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025286647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1025286647
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2015656331
Short name T445
Test name
Test status
Simulation time 253758847 ps
CPU time 6.43 seconds
Started Jul 09 05:26:36 PM PDT 24
Finished Jul 09 05:26:43 PM PDT 24
Peak memory 218228 kb
Host smart-c763b09a-01df-4f9a-9f6e-f024bf4e266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015656331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2015656331
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.899987403
Short name T485
Test name
Test status
Simulation time 132551890 ps
CPU time 2.63 seconds
Started Jul 09 05:26:40 PM PDT 24
Finished Jul 09 05:26:44 PM PDT 24
Peak memory 214372 kb
Host smart-bd8fe4fd-c8f7-41cb-a428-db3cf0fb1ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899987403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.899987403
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1197657562
Short name T269
Test name
Test status
Simulation time 770316550 ps
CPU time 21.73 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:26:58 PM PDT 24
Peak memory 250796 kb
Host smart-665d9ccb-19d9-4395-8927-37c68a46cd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197657562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1197657562
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.174316956
Short name T507
Test name
Test status
Simulation time 68398997 ps
CPU time 6.09 seconds
Started Jul 09 05:26:39 PM PDT 24
Finished Jul 09 05:26:45 PM PDT 24
Peak memory 246820 kb
Host smart-2cdd355b-cfbe-4f4b-af67-cbc1544566a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174316956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.174316956
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1390179736
Short name T386
Test name
Test status
Simulation time 2994693477 ps
CPU time 68.35 seconds
Started Jul 09 05:26:45 PM PDT 24
Finished Jul 09 05:27:55 PM PDT 24
Peak memory 259192 kb
Host smart-72cfb707-b96e-4e5a-b9d7-be4e7ae7603b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390179736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1390179736
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.119685780
Short name T33
Test name
Test status
Simulation time 25317010587 ps
CPU time 148.08 seconds
Started Jul 09 05:26:36 PM PDT 24
Finished Jul 09 05:29:05 PM PDT 24
Peak memory 275804 kb
Host smart-edc0c60e-6d92-42fb-b7f7-82856823bbd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=119685780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.119685780
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.254197808
Short name T713
Test name
Test status
Simulation time 28567419 ps
CPU time 0.89 seconds
Started Jul 09 05:26:34 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 211796 kb
Host smart-4df46af2-2ff7-4ec7-8aa2-328772fa4d0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254197808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.254197808
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.90326489
Short name T74
Test name
Test status
Simulation time 15992734 ps
CPU time 1.1 seconds
Started Jul 09 05:26:38 PM PDT 24
Finished Jul 09 05:26:40 PM PDT 24
Peak memory 208940 kb
Host smart-9e4ead5d-02e2-4a62-9f8b-6a68cd8be457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90326489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.90326489
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1873973628
Short name T230
Test name
Test status
Simulation time 379277439 ps
CPU time 10.17 seconds
Started Jul 09 05:26:41 PM PDT 24
Finished Jul 09 05:26:52 PM PDT 24
Peak memory 218088 kb
Host smart-3c15c157-13f4-46dc-933a-5b42c203e971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873973628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1873973628
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.254650028
Short name T813
Test name
Test status
Simulation time 776429493 ps
CPU time 4.39 seconds
Started Jul 09 05:26:36 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 217220 kb
Host smart-f81d1c8b-0023-4bce-9d60-55b592c83fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254650028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.254650028
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.609439681
Short name T429
Test name
Test status
Simulation time 399830796 ps
CPU time 4.42 seconds
Started Jul 09 05:26:37 PM PDT 24
Finished Jul 09 05:26:42 PM PDT 24
Peak memory 218132 kb
Host smart-834d4cb4-3e9a-46cc-ab4a-530ac72714cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609439681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.609439681
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2860703695
Short name T536
Test name
Test status
Simulation time 1408029621 ps
CPU time 16.79 seconds
Started Jul 09 05:26:37 PM PDT 24
Finished Jul 09 05:26:55 PM PDT 24
Peak memory 225896 kb
Host smart-5c4a56f3-1543-48a9-997e-f91ca3c65408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860703695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2860703695
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.819861040
Short name T247
Test name
Test status
Simulation time 937629179 ps
CPU time 12.72 seconds
Started Jul 09 05:26:37 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 225896 kb
Host smart-5ca3fb38-7c62-4143-b040-a67a9955b1a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819861040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.819861040
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1113059930
Short name T516
Test name
Test status
Simulation time 1667837605 ps
CPU time 9.05 seconds
Started Jul 09 05:26:37 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 218144 kb
Host smart-81db9ef1-b545-460a-8f2b-3bb749167de3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113059930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1113059930
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2709078189
Short name T744
Test name
Test status
Simulation time 802815335 ps
CPU time 14.13 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 218196 kb
Host smart-39850b17-fc07-42b2-8a0f-a6caf00742ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709078189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2709078189
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.4036919951
Short name T726
Test name
Test status
Simulation time 17028424 ps
CPU time 1.13 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 213484 kb
Host smart-14a08f4f-9430-49af-9e63-97bd2bdbabcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036919951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.4036919951
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2623701427
Short name T718
Test name
Test status
Simulation time 2783232481 ps
CPU time 33.68 seconds
Started Jul 09 05:26:44 PM PDT 24
Finished Jul 09 05:27:19 PM PDT 24
Peak memory 250904 kb
Host smart-dee20491-0150-40af-9f97-5720e0707ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623701427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2623701427
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.389757622
Short name T741
Test name
Test status
Simulation time 115446483 ps
CPU time 8.97 seconds
Started Jul 09 05:26:47 PM PDT 24
Finished Jul 09 05:26:57 PM PDT 24
Peak memory 250924 kb
Host smart-df357e91-9baf-4e52-b16f-57ffe14c6308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389757622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.389757622
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.745316374
Short name T212
Test name
Test status
Simulation time 4015034437 ps
CPU time 75.85 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:28:09 PM PDT 24
Peak memory 244176 kb
Host smart-3cfa64ff-7dbe-4709-bf54-de05b790f423
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745316374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.745316374
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3652274636
Short name T34
Test name
Test status
Simulation time 14546229 ps
CPU time 1.12 seconds
Started Jul 09 05:26:35 PM PDT 24
Finished Jul 09 05:26:37 PM PDT 24
Peak memory 211880 kb
Host smart-7fb58e25-2a2a-4b2e-a0d4-cda0b250bca1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652274636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3652274636
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2375871502
Short name T76
Test name
Test status
Simulation time 74551635 ps
CPU time 1.02 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 208888 kb
Host smart-4857baf9-fd4f-4edf-aa68-b6ada92a49fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375871502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2375871502
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4216174055
Short name T321
Test name
Test status
Simulation time 612342786 ps
CPU time 18.17 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:27:11 PM PDT 24
Peak memory 218184 kb
Host smart-9136b50e-c3fa-4588-8ca8-2f9e702b00dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216174055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4216174055
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2562535484
Short name T20
Test name
Test status
Simulation time 255770130 ps
CPU time 7.58 seconds
Started Jul 09 05:26:53 PM PDT 24
Finished Jul 09 05:27:01 PM PDT 24
Peak memory 217132 kb
Host smart-3370d38a-932c-443e-8630-11fc52616565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562535484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2562535484
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3484486383
Short name T600
Test name
Test status
Simulation time 724962040 ps
CPU time 7 seconds
Started Jul 09 05:26:39 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 222272 kb
Host smart-9f56e3d0-7cf3-4559-87a7-6c4d780f5d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484486383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3484486383
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.931788533
Short name T591
Test name
Test status
Simulation time 662574143 ps
CPU time 10.29 seconds
Started Jul 09 05:26:46 PM PDT 24
Finished Jul 09 05:26:58 PM PDT 24
Peak memory 225992 kb
Host smart-73c43545-4186-4b91-a505-ed777c9b381d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931788533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.931788533
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.751468405
Short name T472
Test name
Test status
Simulation time 1970355399 ps
CPU time 12.8 seconds
Started Jul 09 05:26:47 PM PDT 24
Finished Jul 09 05:27:00 PM PDT 24
Peak memory 225864 kb
Host smart-82ab7c6a-e41c-41f9-b0b1-3b594ecc8294
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751468405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.751468405
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.397674935
Short name T360
Test name
Test status
Simulation time 340412244 ps
CPU time 11.8 seconds
Started Jul 09 05:26:48 PM PDT 24
Finished Jul 09 05:27:00 PM PDT 24
Peak memory 218076 kb
Host smart-fbeb9bb2-456e-4b48-a683-f806b6cc4231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397674935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.397674935
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3273722363
Short name T161
Test name
Test status
Simulation time 572630889 ps
CPU time 8.98 seconds
Started Jul 09 05:26:45 PM PDT 24
Finished Jul 09 05:26:55 PM PDT 24
Peak memory 218228 kb
Host smart-e62357b9-c52f-417a-a5d8-76a6a41c8228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273722363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3273722363
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.742688291
Short name T656
Test name
Test status
Simulation time 88778962 ps
CPU time 2.52 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:26:55 PM PDT 24
Peak memory 217620 kb
Host smart-f922d550-aaba-4091-aede-324d282f382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742688291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.742688291
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3505987669
Short name T740
Test name
Test status
Simulation time 225617445 ps
CPU time 27.08 seconds
Started Jul 09 05:26:40 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 250828 kb
Host smart-a7415f77-e511-4166-a08d-aa4768f99756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505987669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3505987669
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.893149868
Short name T628
Test name
Test status
Simulation time 382860044 ps
CPU time 7.42 seconds
Started Jul 09 05:26:44 PM PDT 24
Finished Jul 09 05:26:52 PM PDT 24
Peak memory 250932 kb
Host smart-38726dc0-6f73-4241-89d0-e84d33bad858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893149868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.893149868
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3308157028
Short name T825
Test name
Test status
Simulation time 48903275144 ps
CPU time 124.35 seconds
Started Jul 09 05:26:39 PM PDT 24
Finished Jul 09 05:28:44 PM PDT 24
Peak memory 283768 kb
Host smart-e9157c46-19df-4a7e-b80a-17b7418112bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308157028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3308157028
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.619748415
Short name T145
Test name
Test status
Simulation time 24962557473 ps
CPU time 774.7 seconds
Started Jul 09 05:26:42 PM PDT 24
Finished Jul 09 05:39:37 PM PDT 24
Peak memory 332892 kb
Host smart-966bcdac-7c9f-4b56-b474-e3dd36249e2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=619748415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.619748415
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2628335878
Short name T730
Test name
Test status
Simulation time 14179363 ps
CPU time 1.1 seconds
Started Jul 09 05:26:44 PM PDT 24
Finished Jul 09 05:26:46 PM PDT 24
Peak memory 211860 kb
Host smart-187af3a5-7659-4612-bc16-399efcdc11b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628335878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2628335878
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1261902412
Short name T42
Test name
Test status
Simulation time 939782541 ps
CPU time 12.43 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:27:06 PM PDT 24
Peak memory 218188 kb
Host smart-3763aaff-a2de-4e55-98b4-39f850ecb00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261902412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1261902412
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1355665219
Short name T856
Test name
Test status
Simulation time 696944647 ps
CPU time 6.71 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:27:00 PM PDT 24
Peak memory 217240 kb
Host smart-f41f3f61-3c14-4fd4-a31d-acc84cfcb569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355665219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1355665219
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.437573882
Short name T765
Test name
Test status
Simulation time 212583585 ps
CPU time 4.68 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:26:57 PM PDT 24
Peak memory 218072 kb
Host smart-6085b3b4-7791-4b5d-a77f-2ff7583642aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437573882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.437573882
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.4235821902
Short name T590
Test name
Test status
Simulation time 538170403 ps
CPU time 20.43 seconds
Started Jul 09 05:26:40 PM PDT 24
Finished Jul 09 05:27:01 PM PDT 24
Peak memory 225952 kb
Host smart-3d8d2bed-7922-4415-90d5-f700f133065e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235821902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.4235821902
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2141606457
Short name T344
Test name
Test status
Simulation time 309582025 ps
CPU time 11.45 seconds
Started Jul 09 05:26:46 PM PDT 24
Finished Jul 09 05:26:58 PM PDT 24
Peak memory 225892 kb
Host smart-da8a0c45-7d67-4632-b97e-3ce90f3e285c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141606457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2141606457
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1774567014
Short name T496
Test name
Test status
Simulation time 1008176542 ps
CPU time 9.4 seconds
Started Jul 09 05:26:41 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 218176 kb
Host smart-ec678d35-85b5-476b-84c4-504a7559bfa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774567014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1774567014
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.600534094
Short name T757
Test name
Test status
Simulation time 880177636 ps
CPU time 8.76 seconds
Started Jul 09 05:26:46 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 224760 kb
Host smart-70d31bc0-9945-4dfe-a5e9-7f0a366e6e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600534094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.600534094
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.554683328
Short name T86
Test name
Test status
Simulation time 438641661 ps
CPU time 3.3 seconds
Started Jul 09 05:26:42 PM PDT 24
Finished Jul 09 05:26:46 PM PDT 24
Peak memory 217648 kb
Host smart-7731b8b5-0bf0-4b08-b767-dfe4d55ab811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554683328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.554683328
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.790104864
Short name T243
Test name
Test status
Simulation time 357095974 ps
CPU time 20.34 seconds
Started Jul 09 05:26:40 PM PDT 24
Finished Jul 09 05:27:01 PM PDT 24
Peak memory 245136 kb
Host smart-7908b9eb-3832-4e99-9b2b-a63ee1756332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790104864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.790104864
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3929125295
Short name T156
Test name
Test status
Simulation time 327092156 ps
CPU time 7.13 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:27:01 PM PDT 24
Peak memory 251016 kb
Host smart-b6621c3c-5acf-4ce9-8f71-3e3b529d35a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929125295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3929125295
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3255960063
Short name T579
Test name
Test status
Simulation time 14556611909 ps
CPU time 160.4 seconds
Started Jul 09 05:26:40 PM PDT 24
Finished Jul 09 05:29:21 PM PDT 24
Peak memory 446832 kb
Host smart-91140d56-4ce3-474e-abff-ca1e174ea3c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255960063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3255960063
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3987373732
Short name T180
Test name
Test status
Simulation time 16868022 ps
CPU time 0.86 seconds
Started Jul 09 05:26:44 PM PDT 24
Finished Jul 09 05:26:46 PM PDT 24
Peak memory 211764 kb
Host smart-fb50c0c2-dd1e-4b75-8410-37fc462489b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987373732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3987373732
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3224371101
Short name T803
Test name
Test status
Simulation time 184139686 ps
CPU time 0.94 seconds
Started Jul 09 05:26:47 PM PDT 24
Finished Jul 09 05:26:49 PM PDT 24
Peak memory 208840 kb
Host smart-7ed97f07-f9bf-4ac2-b6d2-10b4f9b876c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224371101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3224371101
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3282127748
Short name T560
Test name
Test status
Simulation time 1437680000 ps
CPU time 13.01 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:27:03 PM PDT 24
Peak memory 225928 kb
Host smart-33e4411a-38bc-47a9-bcba-30f2d263f43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282127748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3282127748
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3928645712
Short name T521
Test name
Test status
Simulation time 2370203949 ps
CPU time 5.21 seconds
Started Jul 09 05:26:50 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 217636 kb
Host smart-de3c3461-0dfb-4dd8-bb91-07f82c799ada
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928645712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3928645712
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2422383886
Short name T706
Test name
Test status
Simulation time 31103272 ps
CPU time 1.93 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 218188 kb
Host smart-0e1d3f7f-a137-4d76-b1dd-79153436d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422383886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2422383886
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3421948444
Short name T621
Test name
Test status
Simulation time 814056701 ps
CPU time 19.19 seconds
Started Jul 09 05:26:50 PM PDT 24
Finished Jul 09 05:27:11 PM PDT 24
Peak memory 225928 kb
Host smart-869a0cbd-ddfc-48f8-90e6-dfdf8f9d396f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421948444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3421948444
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.901348318
Short name T15
Test name
Test status
Simulation time 371181027 ps
CPU time 10.36 seconds
Started Jul 09 05:26:45 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 225952 kb
Host smart-ca92d0ae-50ea-451d-8e9f-2e687e7c3225
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901348318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.901348318
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.134801671
Short name T755
Test name
Test status
Simulation time 1451849695 ps
CPU time 6.04 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 225960 kb
Host smart-cac9742f-d709-4558-8cb9-66d2ccd5c9e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134801671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.134801671
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1782565167
Short name T324
Test name
Test status
Simulation time 1053296118 ps
CPU time 10.2 seconds
Started Jul 09 05:26:44 PM PDT 24
Finished Jul 09 05:26:55 PM PDT 24
Peak memory 218036 kb
Host smart-0f1ebce6-de82-4031-bfd8-246fdf79774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782565167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1782565167
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3961233998
Short name T175
Test name
Test status
Simulation time 1243686263 ps
CPU time 10.41 seconds
Started Jul 09 05:26:41 PM PDT 24
Finished Jul 09 05:26:52 PM PDT 24
Peak memory 217604 kb
Host smart-3de9f155-dc04-4b18-84a1-53c888ba0160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961233998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3961233998
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3700451252
Short name T684
Test name
Test status
Simulation time 960201659 ps
CPU time 32.01 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:27:24 PM PDT 24
Peak memory 250528 kb
Host smart-425d1a90-faab-452c-b017-aba85549658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700451252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3700451252
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2817330856
Short name T608
Test name
Test status
Simulation time 67906451 ps
CPU time 5.84 seconds
Started Jul 09 05:26:43 PM PDT 24
Finished Jul 09 05:26:50 PM PDT 24
Peak memory 247092 kb
Host smart-6ac0bece-5f33-48f5-8879-d37c8e2b7080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817330856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2817330856
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.900704799
Short name T439
Test name
Test status
Simulation time 490513416 ps
CPU time 16.87 seconds
Started Jul 09 05:26:44 PM PDT 24
Finished Jul 09 05:27:02 PM PDT 24
Peak memory 225960 kb
Host smart-98225287-b38f-49ad-a60b-0c2b4866906f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900704799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.900704799
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2053277181
Short name T142
Test name
Test status
Simulation time 134076145931 ps
CPU time 1767.05 seconds
Started Jul 09 05:26:48 PM PDT 24
Finished Jul 09 05:56:16 PM PDT 24
Peak memory 905888 kb
Host smart-e96161db-b1bb-4df4-b884-050daf924b54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2053277181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2053277181
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.536342478
Short name T448
Test name
Test status
Simulation time 77972534 ps
CPU time 0.93 seconds
Started Jul 09 05:26:45 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 211792 kb
Host smart-8a569b82-5ba0-448e-a7f7-80dc23636511
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536342478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.536342478
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4265892010
Short name T315
Test name
Test status
Simulation time 26237862 ps
CPU time 1.31 seconds
Started Jul 09 05:26:50 PM PDT 24
Finished Jul 09 05:26:53 PM PDT 24
Peak memory 208916 kb
Host smart-7346dd20-2b83-40c7-b3a7-b6ec27b4fa52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265892010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4265892010
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1084915869
Short name T418
Test name
Test status
Simulation time 978647630 ps
CPU time 12.16 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:27:05 PM PDT 24
Peak memory 225736 kb
Host smart-54b9ff4b-8008-4916-af4e-954cf486c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084915869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1084915869
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2310900130
Short name T687
Test name
Test status
Simulation time 462119515 ps
CPU time 6.39 seconds
Started Jul 09 05:26:43 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 217232 kb
Host smart-90a6958d-222e-49a1-adcd-25691c9186f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310900130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2310900130
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1516590193
Short name T620
Test name
Test status
Simulation time 121502703 ps
CPU time 3.3 seconds
Started Jul 09 05:26:45 PM PDT 24
Finished Jul 09 05:26:49 PM PDT 24
Peak memory 218196 kb
Host smart-5ed35c48-91a0-4b4a-bb7d-a244f0f9f859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516590193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1516590193
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1496441072
Short name T409
Test name
Test status
Simulation time 682985314 ps
CPU time 11.37 seconds
Started Jul 09 05:26:50 PM PDT 24
Finished Jul 09 05:27:03 PM PDT 24
Peak memory 225940 kb
Host smart-53563713-996d-48f6-aed0-d413d231b0f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496441072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1496441072
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2745619650
Short name T157
Test name
Test status
Simulation time 1325221889 ps
CPU time 14.14 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 225956 kb
Host smart-5952b322-75b3-45de-8c92-5c9e49ed0e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745619650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2745619650
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1563093998
Short name T734
Test name
Test status
Simulation time 417107726 ps
CPU time 10.69 seconds
Started Jul 09 05:29:01 PM PDT 24
Finished Jul 09 05:29:13 PM PDT 24
Peak memory 218296 kb
Host smart-7dfee7b1-69e8-4107-b8cc-1d4515dd60e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563093998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1563093998
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1247335707
Short name T64
Test name
Test status
Simulation time 132190718 ps
CPU time 3.38 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 217548 kb
Host smart-8946489b-e265-49d8-aefb-8a8776938b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247335707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1247335707
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.103457472
Short name T435
Test name
Test status
Simulation time 187332049 ps
CPU time 20.07 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 250800 kb
Host smart-c56fe54e-831a-42fe-b86f-569a005d03f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103457472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.103457472
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4097708443
Short name T30
Test name
Test status
Simulation time 57182002360 ps
CPU time 186.02 seconds
Started Jul 09 05:26:50 PM PDT 24
Finished Jul 09 05:29:58 PM PDT 24
Peak memory 282784 kb
Host smart-7ed1e253-1942-4aa4-8cd8-fdeda1556588
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097708443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4097708443
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2782981939
Short name T323
Test name
Test status
Simulation time 126175598 ps
CPU time 0.82 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 211704 kb
Host smart-a9044d21-5f8e-4745-be2b-945daa0a0e8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782981939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2782981939
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.625369641
Short name T309
Test name
Test status
Simulation time 19496037 ps
CPU time 0.94 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:25:46 PM PDT 24
Peak memory 208840 kb
Host smart-c501433c-4797-4140-9c67-f878d4d239be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625369641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.625369641
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.448802028
Short name T565
Test name
Test status
Simulation time 21608216 ps
CPU time 0.93 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:25:48 PM PDT 24
Peak memory 208816 kb
Host smart-01be8d93-496b-4bb3-bd0f-0644cf14f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448802028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.448802028
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.899160920
Short name T187
Test name
Test status
Simulation time 668733934 ps
CPU time 19.28 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 218152 kb
Host smart-c8bcfec6-66ae-409c-a342-7e3bd94ca50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899160920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.899160920
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4087922526
Short name T46
Test name
Test status
Simulation time 518184417 ps
CPU time 2.4 seconds
Started Jul 09 05:25:44 PM PDT 24
Finished Jul 09 05:25:47 PM PDT 24
Peak memory 216868 kb
Host smart-b67ea9e2-3dd9-4e3b-b457-9c4aa4074aa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087922526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4087922526
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3770182230
Short name T815
Test name
Test status
Simulation time 3876334612 ps
CPU time 19.68 seconds
Started Jul 09 05:25:34 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 225948 kb
Host smart-4e5ac871-49a6-4def-8fb0-ae7fa3127ff8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770182230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3770182230
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3999986271
Short name T852
Test name
Test status
Simulation time 2061573454 ps
CPU time 7.7 seconds
Started Jul 09 05:25:36 PM PDT 24
Finished Jul 09 05:25:45 PM PDT 24
Peak memory 217696 kb
Host smart-a725b386-2497-4f32-ab48-bd433ac65698
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999986271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
999986271
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3160099323
Short name T98
Test name
Test status
Simulation time 1535024594 ps
CPU time 7.87 seconds
Started Jul 09 05:25:35 PM PDT 24
Finished Jul 09 05:25:43 PM PDT 24
Peak memory 223120 kb
Host smart-f373a1dd-b2fa-4722-a828-4f3ef3cd8556
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160099323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3160099323
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1950155265
Short name T286
Test name
Test status
Simulation time 5266720546 ps
CPU time 15.82 seconds
Started Jul 09 05:25:36 PM PDT 24
Finished Jul 09 05:25:52 PM PDT 24
Peak memory 217632 kb
Host smart-2ca839de-2fe6-4374-ae8d-ffca320695a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950155265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1950155265
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1274729604
Short name T153
Test name
Test status
Simulation time 340995914 ps
CPU time 3.1 seconds
Started Jul 09 05:25:37 PM PDT 24
Finished Jul 09 05:25:40 PM PDT 24
Peak memory 217656 kb
Host smart-6941c870-aeca-46c8-a8df-f5554fc4b071
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274729604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1274729604
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1660868931
Short name T173
Test name
Test status
Simulation time 2163463201 ps
CPU time 48.5 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:38 PM PDT 24
Peak memory 250896 kb
Host smart-dc92d336-9859-4822-a6d3-dd672ee119c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660868931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1660868931
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.694857595
Short name T663
Test name
Test status
Simulation time 2049947754 ps
CPU time 19.27 seconds
Started Jul 09 05:25:40 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 250472 kb
Host smart-d386e521-af40-4c2a-a2e4-abebd98bcb8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694857595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.694857595
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1095342584
Short name T798
Test name
Test status
Simulation time 169818549 ps
CPU time 2.14 seconds
Started Jul 09 05:25:43 PM PDT 24
Finished Jul 09 05:25:45 PM PDT 24
Peak memory 218188 kb
Host smart-caf77dfb-2aa9-4016-97ad-c4b141c60f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095342584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1095342584
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3376954577
Short name T531
Test name
Test status
Simulation time 736281956 ps
CPU time 21.33 seconds
Started Jul 09 05:25:36 PM PDT 24
Finished Jul 09 05:25:58 PM PDT 24
Peak memory 217676 kb
Host smart-1643a942-230b-409e-8893-157ebf7e4113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376954577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3376954577
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1147287044
Short name T91
Test name
Test status
Simulation time 661193772 ps
CPU time 37.72 seconds
Started Jul 09 05:25:51 PM PDT 24
Finished Jul 09 05:26:30 PM PDT 24
Peak memory 269988 kb
Host smart-122ff28f-52ac-407f-b7a3-4bd130a30290
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147287044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1147287044
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3878999099
Short name T171
Test name
Test status
Simulation time 371799406 ps
CPU time 13.67 seconds
Started Jul 09 05:25:36 PM PDT 24
Finished Jul 09 05:25:50 PM PDT 24
Peak memory 225976 kb
Host smart-8c065914-f4c6-42f8-8d25-c71573d540e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878999099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3878999099
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1647422971
Short name T320
Test name
Test status
Simulation time 7042607677 ps
CPU time 10.27 seconds
Started Jul 09 05:25:39 PM PDT 24
Finished Jul 09 05:25:50 PM PDT 24
Peak memory 218236 kb
Host smart-ba13a083-abbb-4dd9-b4ff-993da55b5d95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647422971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
647422971
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1835225346
Short name T57
Test name
Test status
Simulation time 231210122 ps
CPU time 10.31 seconds
Started Jul 09 05:25:51 PM PDT 24
Finished Jul 09 05:26:03 PM PDT 24
Peak memory 225976 kb
Host smart-ad7ef952-ee5e-45b9-9a9f-6869963c64df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835225346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1835225346
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2757118078
Short name T481
Test name
Test status
Simulation time 54197884 ps
CPU time 2.68 seconds
Started Jul 09 05:25:36 PM PDT 24
Finished Jul 09 05:25:39 PM PDT 24
Peak memory 214324 kb
Host smart-60b2cd5d-ddd2-4f82-9b11-bfd34a3de4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757118078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2757118078
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1540008545
Short name T484
Test name
Test status
Simulation time 288459343 ps
CPU time 31.74 seconds
Started Jul 09 05:25:38 PM PDT 24
Finished Jul 09 05:26:11 PM PDT 24
Peak memory 250916 kb
Host smart-7ad95810-c74d-439b-9fdc-08c65128e2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540008545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1540008545
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3575202065
Short name T502
Test name
Test status
Simulation time 1096217989 ps
CPU time 3.3 seconds
Started Jul 09 05:25:40 PM PDT 24
Finished Jul 09 05:25:44 PM PDT 24
Peak memory 226332 kb
Host smart-1f91b724-457e-4cee-87f8-50f5599eb961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575202065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3575202065
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1672709655
Short name T426
Test name
Test status
Simulation time 12557953785 ps
CPU time 64.42 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:26:52 PM PDT 24
Peak memory 250844 kb
Host smart-69bbae11-cc67-4969-84d7-c58d123f5764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672709655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1672709655
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1802280242
Short name T559
Test name
Test status
Simulation time 13974950 ps
CPU time 0.92 seconds
Started Jul 09 05:25:35 PM PDT 24
Finished Jul 09 05:25:37 PM PDT 24
Peak memory 208584 kb
Host smart-a4e28418-415c-48fa-b84e-5b56444ef393
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802280242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1802280242
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3456896212
Short name T747
Test name
Test status
Simulation time 228229359 ps
CPU time 0.9 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 208880 kb
Host smart-9c907258-809a-468c-99f5-c58a9aa5a4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456896212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3456896212
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3143628552
Short name T775
Test name
Test status
Simulation time 1190863927 ps
CPU time 12.9 seconds
Started Jul 09 05:26:53 PM PDT 24
Finished Jul 09 05:27:07 PM PDT 24
Peak memory 218156 kb
Host smart-951a1787-38d3-4fbf-8cc3-7d22d4f9fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143628552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3143628552
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2651171933
Short name T615
Test name
Test status
Simulation time 3232817281 ps
CPU time 8.82 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:59 PM PDT 24
Peak memory 217692 kb
Host smart-afd96ce7-b29c-4d00-9c1f-c9e045d7fe13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651171933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2651171933
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1800002760
Short name T225
Test name
Test status
Simulation time 130074821 ps
CPU time 2.26 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 221924 kb
Host smart-6c185e6a-333a-4b4e-b61e-9741bd6b2204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800002760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1800002760
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4258658485
Short name T514
Test name
Test status
Simulation time 349687669 ps
CPU time 14.18 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 218400 kb
Host smart-83646fba-c7a5-4e5f-be2d-0183a5a99e33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258658485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4258658485
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.380793401
Short name T631
Test name
Test status
Simulation time 379662479 ps
CPU time 13.6 seconds
Started Jul 09 05:26:53 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 225992 kb
Host smart-77599b05-eee2-4927-816c-a04299663e04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380793401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.380793401
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2541218590
Short name T278
Test name
Test status
Simulation time 2166553693 ps
CPU time 17.33 seconds
Started Jul 09 05:26:57 PM PDT 24
Finished Jul 09 05:27:15 PM PDT 24
Peak memory 218236 kb
Host smart-0392e428-e455-4f6e-b08a-f94a3ce519f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541218590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2541218590
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1491052815
Short name T763
Test name
Test status
Simulation time 442267362 ps
CPU time 7.39 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:27:01 PM PDT 24
Peak memory 224788 kb
Host smart-93c9cf26-a53c-48a8-b0ce-123c02a3fd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491052815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1491052815
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1737962090
Short name T690
Test name
Test status
Simulation time 277304904 ps
CPU time 10.66 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:27:03 PM PDT 24
Peak memory 217260 kb
Host smart-e2c168db-4a1a-4cee-ae67-cba5bc9e94a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737962090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1737962090
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2196028534
Short name T597
Test name
Test status
Simulation time 4201172023 ps
CPU time 31.16 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:27:24 PM PDT 24
Peak memory 250800 kb
Host smart-ed1966c6-6527-43bf-9eeb-6a50cbd654ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196028534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2196028534
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2936817007
Short name T249
Test name
Test status
Simulation time 148960733 ps
CPU time 8.55 seconds
Started Jul 09 05:26:50 PM PDT 24
Finished Jul 09 05:27:00 PM PDT 24
Peak memory 250936 kb
Host smart-fb30a763-7138-4e62-bec7-ea24514e4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936817007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2936817007
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3399701454
Short name T710
Test name
Test status
Simulation time 39823411 ps
CPU time 0.97 seconds
Started Jul 09 05:26:45 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 211900 kb
Host smart-9f11b32a-40c0-4747-84ea-9e2c3f1a143b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399701454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3399701454
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3241046312
Short name T392
Test name
Test status
Simulation time 75500028 ps
CPU time 1.2 seconds
Started Jul 09 05:26:53 PM PDT 24
Finished Jul 09 05:26:55 PM PDT 24
Peak memory 209032 kb
Host smart-5fb87e70-a773-4960-b720-08bc31f9a5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241046312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3241046312
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.283472539
Short name T794
Test name
Test status
Simulation time 236346029 ps
CPU time 11.24 seconds
Started Jul 09 05:26:50 PM PDT 24
Finished Jul 09 05:27:03 PM PDT 24
Peak memory 225960 kb
Host smart-995967e9-92b3-4e20-97aa-6a7c51a4cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283472539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.283472539
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3002052800
Short name T575
Test name
Test status
Simulation time 3277652955 ps
CPU time 13.78 seconds
Started Jul 09 05:26:53 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 217684 kb
Host smart-59557c89-753f-4e97-a611-ada64ae60273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002052800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3002052800
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.147016015
Short name T223
Test name
Test status
Simulation time 72017458 ps
CPU time 3.61 seconds
Started Jul 09 05:26:54 PM PDT 24
Finished Jul 09 05:26:58 PM PDT 24
Peak memory 222452 kb
Host smart-fb0115be-25dd-43a7-88ca-fd7fab2b37d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147016015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.147016015
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2525273115
Short name T355
Test name
Test status
Simulation time 1259315112 ps
CPU time 12.43 seconds
Started Jul 09 05:26:55 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 225896 kb
Host smart-386d8450-7d33-470f-a85a-9b60bd334fe3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525273115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2525273115
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1633951447
Short name T811
Test name
Test status
Simulation time 335428844 ps
CPU time 9.07 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:27:02 PM PDT 24
Peak memory 218160 kb
Host smart-12bf33f0-e859-4f30-a63e-0e23c54e6224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633951447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1633951447
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2303606911
Short name T691
Test name
Test status
Simulation time 1075287748 ps
CPU time 7.84 seconds
Started Jul 09 05:26:47 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 218088 kb
Host smart-a11cb88c-2232-47f7-a8e3-1254b4c2a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303606911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2303606911
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2460007999
Short name T705
Test name
Test status
Simulation time 116720756 ps
CPU time 3.74 seconds
Started Jul 09 05:26:49 PM PDT 24
Finished Jul 09 05:26:54 PM PDT 24
Peak memory 217672 kb
Host smart-be414c76-6c55-42fe-be19-d2218f0cb0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460007999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2460007999
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1541692720
Short name T772
Test name
Test status
Simulation time 281676838 ps
CPU time 26.24 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:27:19 PM PDT 24
Peak memory 250928 kb
Host smart-fcfd1843-5acb-48c0-a9bd-3f3846b174a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541692720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1541692720
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.4021392747
Short name T224
Test name
Test status
Simulation time 70250134 ps
CPU time 3.1 seconds
Started Jul 09 05:26:48 PM PDT 24
Finished Jul 09 05:26:51 PM PDT 24
Peak memory 223916 kb
Host smart-3e6f9cb3-6fa1-42a8-a76c-91c1aba84566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021392747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.4021392747
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2738582189
Short name T509
Test name
Test status
Simulation time 37290298748 ps
CPU time 339.4 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:32:32 PM PDT 24
Peak memory 251012 kb
Host smart-3e9a712b-7053-4411-9885-23782957cf19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738582189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2738582189
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2094367783
Short name T149
Test name
Test status
Simulation time 138858130051 ps
CPU time 1454.51 seconds
Started Jul 09 05:26:51 PM PDT 24
Finished Jul 09 05:51:08 PM PDT 24
Peak memory 611520 kb
Host smart-6b6097ea-c729-4c58-bed3-4d14234be4ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2094367783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2094367783
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.335084362
Short name T370
Test name
Test status
Simulation time 15293458 ps
CPU time 0.87 seconds
Started Jul 09 05:26:52 PM PDT 24
Finished Jul 09 05:26:55 PM PDT 24
Peak memory 211872 kb
Host smart-a41fbb15-5c52-42a9-8e98-9b655fa98dee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335084362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.335084362
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3557397549
Short name T430
Test name
Test status
Simulation time 23211605 ps
CPU time 1 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:05 PM PDT 24
Peak memory 208940 kb
Host smart-c424943a-58ca-48c0-bf70-671902b1e7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557397549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3557397549
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3466706085
Short name T447
Test name
Test status
Simulation time 311017677 ps
CPU time 15.17 seconds
Started Jul 09 05:26:57 PM PDT 24
Finished Jul 09 05:27:12 PM PDT 24
Peak memory 218092 kb
Host smart-5472271d-21d8-4a9d-84fd-aed3cdab06d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466706085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3466706085
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2655365908
Short name T606
Test name
Test status
Simulation time 1771325927 ps
CPU time 3.13 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:05 PM PDT 24
Peak memory 216984 kb
Host smart-6e5f9065-c80a-4ff6-baef-1ef6c0f4cfbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655365908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2655365908
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2525068119
Short name T584
Test name
Test status
Simulation time 229826560 ps
CPU time 3.31 seconds
Started Jul 09 05:26:57 PM PDT 24
Finished Jul 09 05:27:00 PM PDT 24
Peak memory 222328 kb
Host smart-4a7adc9d-9e28-4f2e-937f-f27e6033dacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525068119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2525068119
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3281743222
Short name T572
Test name
Test status
Simulation time 776113833 ps
CPU time 17.32 seconds
Started Jul 09 05:26:54 PM PDT 24
Finished Jul 09 05:27:12 PM PDT 24
Peak memory 225940 kb
Host smart-ced777df-05b6-4905-acef-0deb663b79cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281743222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3281743222
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4091497716
Short name T587
Test name
Test status
Simulation time 955280159 ps
CPU time 8.74 seconds
Started Jul 09 05:27:01 PM PDT 24
Finished Jul 09 05:27:12 PM PDT 24
Peak memory 225960 kb
Host smart-1f1f1c2a-b17e-4d2b-bba3-a4953f8b9af6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091497716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4091497716
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.72968381
Short name T821
Test name
Test status
Simulation time 1911098182 ps
CPU time 16.44 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:21 PM PDT 24
Peak memory 226000 kb
Host smart-e7c2b38d-6c19-4b3a-ba07-c9cf6d10b44c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72968381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.72968381
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4248451585
Short name T364
Test name
Test status
Simulation time 933834107 ps
CPU time 6.64 seconds
Started Jul 09 05:26:57 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 225128 kb
Host smart-f47fa2ca-cd4b-4598-afe9-f4b51e4bb2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248451585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4248451585
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.959273301
Short name T358
Test name
Test status
Simulation time 20751608 ps
CPU time 1.93 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:03 PM PDT 24
Peak memory 213916 kb
Host smart-b7f2ad8c-c358-44a3-8ffd-06cf2d1511fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959273301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.959273301
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3159139726
Short name T181
Test name
Test status
Simulation time 497585487 ps
CPU time 22.64 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 250884 kb
Host smart-7c6db7b8-1c08-4329-a000-51022032b2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159139726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3159139726
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3554341344
Short name T363
Test name
Test status
Simulation time 101689762 ps
CPU time 8.75 seconds
Started Jul 09 05:26:54 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 250876 kb
Host smart-2281e7ce-fcdd-4fc2-b404-3fc563595e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554341344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3554341344
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3333731922
Short name T239
Test name
Test status
Simulation time 7594749525 ps
CPU time 205.3 seconds
Started Jul 09 05:26:54 PM PDT 24
Finished Jul 09 05:30:20 PM PDT 24
Peak memory 482100 kb
Host smart-07f561ed-0115-43c8-81a0-50eca32ec69f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333731922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3333731922
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2731034790
Short name T144
Test name
Test status
Simulation time 6056952828 ps
CPU time 227.44 seconds
Started Jul 09 05:26:55 PM PDT 24
Finished Jul 09 05:30:43 PM PDT 24
Peak memory 283772 kb
Host smart-7c8bb6c2-52ec-4052-970d-3d5cf253ba90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2731034790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2731034790
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.196776662
Short name T636
Test name
Test status
Simulation time 23993700 ps
CPU time 1.01 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 211824 kb
Host smart-b533bfea-7d01-4426-9156-f62ff41665ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196776662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.196776662
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1115235799
Short name T292
Test name
Test status
Simulation time 13637552 ps
CPU time 0.84 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:06 PM PDT 24
Peak memory 208696 kb
Host smart-57feaccb-a4e5-417e-a864-294890e19b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115235799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1115235799
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3415310868
Short name T678
Test name
Test status
Simulation time 473860627 ps
CPU time 14.01 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 218184 kb
Host smart-f4a652f9-600b-4df7-8e82-f7fa40c8b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415310868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3415310868
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1118016055
Short name T428
Test name
Test status
Simulation time 153585091 ps
CPU time 4.21 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 216996 kb
Host smart-a9c0916e-f96d-47c7-ab05-1a74dcbb0695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118016055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1118016055
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3348394156
Short name T27
Test name
Test status
Simulation time 839057989 ps
CPU time 4.23 seconds
Started Jul 09 05:26:56 PM PDT 24
Finished Jul 09 05:27:01 PM PDT 24
Peak memory 218028 kb
Host smart-2c20edf5-16c2-4ef1-a744-4259b6da69a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348394156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3348394156
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3214100867
Short name T540
Test name
Test status
Simulation time 216918716 ps
CPU time 10.06 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:27:09 PM PDT 24
Peak memory 218296 kb
Host smart-221f2afb-191c-467a-a0fb-4a4d27729b58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214100867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3214100867
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1818454161
Short name T422
Test name
Test status
Simulation time 718677062 ps
CPU time 11.82 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:16 PM PDT 24
Peak memory 226000 kb
Host smart-d18cd6f1-e468-4073-8cbb-38ea95b2805d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818454161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1818454161
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.4206090147
Short name T48
Test name
Test status
Simulation time 550730772 ps
CPU time 10.29 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:14 PM PDT 24
Peak memory 218124 kb
Host smart-6b989794-caff-45b4-a253-065cb74ce750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206090147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
4206090147
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.890017133
Short name T695
Test name
Test status
Simulation time 382662958 ps
CPU time 10.75 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 225816 kb
Host smart-70a22583-3275-4717-9e36-b938434497b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890017133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.890017133
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4231016028
Short name T796
Test name
Test status
Simulation time 25599591 ps
CPU time 1.97 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:07 PM PDT 24
Peak memory 223184 kb
Host smart-195cc63d-6914-41b7-a80c-0c24b6d4d0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231016028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4231016028
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2704027777
Short name T610
Test name
Test status
Simulation time 1482322822 ps
CPU time 28.57 seconds
Started Jul 09 05:26:56 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 250892 kb
Host smart-71359bb9-4f36-4b8e-af15-ca184df21ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704027777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2704027777
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2833974633
Short name T563
Test name
Test status
Simulation time 377022850 ps
CPU time 6.76 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 250088 kb
Host smart-c4dbb342-74f0-4b03-8696-d7885d81d8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833974633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2833974633
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1964255672
Short name T9
Test name
Test status
Simulation time 15780809559 ps
CPU time 227.41 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:30:51 PM PDT 24
Peak memory 250988 kb
Host smart-d3266d29-be78-4716-8c54-2e7f67b32970
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964255672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1964255672
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2690449488
Short name T164
Test name
Test status
Simulation time 28022059079 ps
CPU time 374.77 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:33:16 PM PDT 24
Peak memory 274524 kb
Host smart-28e891c4-54fe-4f37-bd10-b719781f20fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2690449488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2690449488
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3942032245
Short name T444
Test name
Test status
Simulation time 33388374 ps
CPU time 0.86 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:03 PM PDT 24
Peak memory 211932 kb
Host smart-431cc2f8-c800-43ca-92ff-5637b8465c9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942032245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3942032245
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2600058891
Short name T373
Test name
Test status
Simulation time 21216947 ps
CPU time 0.97 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:07 PM PDT 24
Peak memory 208868 kb
Host smart-6bdb659b-c6da-4abc-a02b-acc15e4363a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600058891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2600058891
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3883778429
Short name T434
Test name
Test status
Simulation time 276675853 ps
CPU time 9.44 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:27:18 PM PDT 24
Peak memory 217980 kb
Host smart-ca25d11c-e20b-4862-adfd-22006014d503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883778429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3883778429
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3936218389
Short name T22
Test name
Test status
Simulation time 1432567612 ps
CPU time 10.08 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:12 PM PDT 24
Peak memory 217040 kb
Host smart-57bbebb5-c507-4daa-aa8e-9eadecfe754d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936218389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3936218389
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.263771376
Short name T335
Test name
Test status
Simulation time 22599252 ps
CPU time 1.6 seconds
Started Jul 09 05:27:08 PM PDT 24
Finished Jul 09 05:27:10 PM PDT 24
Peak memory 218064 kb
Host smart-061eb9ab-9326-417b-87b4-615ca4fcef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263771376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.263771376
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1237002707
Short name T720
Test name
Test status
Simulation time 451576111 ps
CPU time 14.39 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:20 PM PDT 24
Peak memory 226000 kb
Host smart-62cd0678-5dca-4335-b759-13d2531ccf9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237002707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1237002707
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1702677335
Short name T263
Test name
Test status
Simulation time 1884080851 ps
CPU time 13.73 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:16 PM PDT 24
Peak memory 225920 kb
Host smart-315dfcac-9d85-4a6d-b914-c9dfd73bcde7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702677335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1702677335
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2368347952
Short name T272
Test name
Test status
Simulation time 920716402 ps
CPU time 7.36 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:12 PM PDT 24
Peak memory 225636 kb
Host smart-a1fcf03c-aae7-49ff-8df5-b63f2d13de3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368347952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2368347952
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2219532437
Short name T410
Test name
Test status
Simulation time 259988696 ps
CPU time 7.79 seconds
Started Jul 09 05:26:55 PM PDT 24
Finished Jul 09 05:27:03 PM PDT 24
Peak memory 225964 kb
Host smart-46d7a789-e136-47d9-b005-8711a22dc66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219532437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2219532437
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.116563813
Short name T88
Test name
Test status
Simulation time 55535340 ps
CPU time 4.14 seconds
Started Jul 09 05:26:57 PM PDT 24
Finished Jul 09 05:27:01 PM PDT 24
Peak memory 217668 kb
Host smart-1d78eac8-09a2-4523-9dfc-0768f5b64b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116563813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.116563813
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2522334230
Short name T242
Test name
Test status
Simulation time 607852555 ps
CPU time 34.31 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:36 PM PDT 24
Peak memory 250820 kb
Host smart-f9710052-ad83-4247-bac9-2f5c2ba5828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522334230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2522334230
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1021494624
Short name T255
Test name
Test status
Simulation time 384163565 ps
CPU time 7.66 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:27:07 PM PDT 24
Peak memory 250380 kb
Host smart-bee48d0c-a101-4d57-9e0c-81bc41cf8b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021494624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1021494624
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3976497196
Short name T406
Test name
Test status
Simulation time 1571983223 ps
CPU time 55.67 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:57 PM PDT 24
Peak memory 250836 kb
Host smart-4370e2d8-ed6b-46ba-8937-770e5749e274
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976497196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3976497196
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3101043643
Short name T523
Test name
Test status
Simulation time 80605499853 ps
CPU time 353.69 seconds
Started Jul 09 05:26:58 PM PDT 24
Finished Jul 09 05:32:52 PM PDT 24
Peak memory 282248 kb
Host smart-bd439249-e12f-4500-9f8d-c1579b93e2a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3101043643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3101043643
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1335895172
Short name T154
Test name
Test status
Simulation time 55964272 ps
CPU time 1.08 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:27:09 PM PDT 24
Peak memory 217572 kb
Host smart-9be20171-e592-4a19-bd7c-4339239f800a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335895172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1335895172
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3556465104
Short name T635
Test name
Test status
Simulation time 339906008 ps
CPU time 1.12 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 208940 kb
Host smart-e8c85d2b-6e6f-44f6-8bad-28240fb4b55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556465104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3556465104
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3640757180
Short name T737
Test name
Test status
Simulation time 554416577 ps
CPU time 12.65 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:14 PM PDT 24
Peak memory 218176 kb
Host smart-c2de8ec5-9f65-44c7-95b2-41a8c8b77b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640757180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3640757180
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1105397369
Short name T497
Test name
Test status
Simulation time 3270346676 ps
CPU time 20.02 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 217612 kb
Host smart-3e2b9222-2f22-4690-bacb-e6595d66ef9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105397369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1105397369
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3337954169
Short name T368
Test name
Test status
Simulation time 18250265 ps
CPU time 1.76 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:27:02 PM PDT 24
Peak memory 217936 kb
Host smart-e07393c8-b7de-4423-b29e-15b1859ce1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337954169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3337954169
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3787767288
Short name T738
Test name
Test status
Simulation time 2634333988 ps
CPU time 17.31 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 225940 kb
Host smart-d138fd8a-1a58-4cdb-9939-73d2daa486f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787767288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3787767288
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3331993442
Short name T314
Test name
Test status
Simulation time 1277844568 ps
CPU time 12.12 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:16 PM PDT 24
Peak memory 226028 kb
Host smart-abefda29-5636-4c6e-99a7-8579308e6018
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331993442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3331993442
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.682801302
Short name T352
Test name
Test status
Simulation time 862333018 ps
CPU time 10.2 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:27:10 PM PDT 24
Peak memory 217964 kb
Host smart-d86c0541-6587-48db-9d26-444508a1ac36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682801302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.682801302
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3299623038
Short name T728
Test name
Test status
Simulation time 2294914100 ps
CPU time 12.56 seconds
Started Jul 09 05:26:57 PM PDT 24
Finished Jul 09 05:27:10 PM PDT 24
Peak memory 225308 kb
Host smart-43bbebb1-5c4f-463e-8f03-6feff431e5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299623038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3299623038
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1677512216
Short name T331
Test name
Test status
Simulation time 121718089 ps
CPU time 2.38 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 214604 kb
Host smart-cc1bd5a4-00f9-45b8-8684-9ca3744eecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677512216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1677512216
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3187333901
Short name T605
Test name
Test status
Simulation time 690129952 ps
CPU time 25.07 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:27:33 PM PDT 24
Peak memory 250780 kb
Host smart-91fa19ec-ad17-4102-83d4-ca6088f80324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187333901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3187333901
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3688315704
Short name T329
Test name
Test status
Simulation time 238543752 ps
CPU time 9.17 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:27:10 PM PDT 24
Peak memory 250976 kb
Host smart-3c566056-826a-4caa-ac46-48cfb1137d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688315704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3688315704
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3270538493
Short name T452
Test name
Test status
Simulation time 2939779441 ps
CPU time 125.33 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:29:06 PM PDT 24
Peak memory 279916 kb
Host smart-1d4fe965-852e-4a52-9fe7-c52b0dd20068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270538493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3270538493
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.132059375
Short name T702
Test name
Test status
Simulation time 69196566893 ps
CPU time 529.28 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:35:53 PM PDT 24
Peak memory 295980 kb
Host smart-4b2f8d79-9ff8-429f-8da6-2734b57b2853
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=132059375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.132059375
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.649197825
Short name T508
Test name
Test status
Simulation time 11918157 ps
CPU time 1.02 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:05 PM PDT 24
Peak memory 211896 kb
Host smart-3055e96d-3431-4cb3-bee6-d40f6762cfb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649197825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.649197825
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3864336513
Short name T172
Test name
Test status
Simulation time 45543911 ps
CPU time 1.25 seconds
Started Jul 09 05:27:01 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 208880 kb
Host smart-8ac1a193-772a-4d11-a6b4-c95e457620b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864336513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3864336513
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3573082588
Short name T267
Test name
Test status
Simulation time 366464605 ps
CPU time 14.68 seconds
Started Jul 09 05:27:01 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 225968 kb
Host smart-31780f4f-1a28-41cf-928a-19bd64a01859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573082588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3573082588
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1609057389
Short name T826
Test name
Test status
Simulation time 344889858 ps
CPU time 2.51 seconds
Started Jul 09 05:27:01 PM PDT 24
Finished Jul 09 05:27:05 PM PDT 24
Peak memory 217140 kb
Host smart-3e85ee7e-51bd-4256-bce4-4687d11fede8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609057389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1609057389
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3751594271
Short name T303
Test name
Test status
Simulation time 345988786 ps
CPU time 3.07 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:09 PM PDT 24
Peak memory 218156 kb
Host smart-0f2557cc-1c04-48ab-b7e4-137fd7a63981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751594271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3751594271
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3750774158
Short name T550
Test name
Test status
Simulation time 1012862363 ps
CPU time 8.88 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:15 PM PDT 24
Peak memory 218760 kb
Host smart-1d93844f-36bd-4109-b36a-dd4508d62794
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750774158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3750774158
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3895311017
Short name T487
Test name
Test status
Simulation time 677014727 ps
CPU time 13.13 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 225916 kb
Host smart-ecbd1af0-d8f7-4ff5-94d0-b18016e7adf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895311017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3895311017
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3879142443
Short name T388
Test name
Test status
Simulation time 925899036 ps
CPU time 10.03 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:27:10 PM PDT 24
Peak memory 218112 kb
Host smart-efe40ba4-1f05-4ad8-be40-6883b8678aa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879142443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3879142443
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.120969178
Short name T725
Test name
Test status
Simulation time 4280810107 ps
CPU time 9.74 seconds
Started Jul 09 05:27:01 PM PDT 24
Finished Jul 09 05:27:12 PM PDT 24
Peak memory 226040 kb
Host smart-6705b105-7e5d-41c1-aefe-4d8005130a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120969178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.120969178
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.875936976
Short name T618
Test name
Test status
Simulation time 54875096 ps
CPU time 3.46 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:05 PM PDT 24
Peak memory 217764 kb
Host smart-d352ad7d-ddf1-4381-9898-cb7b6a38e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875936976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.875936976
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.552934460
Short name T385
Test name
Test status
Simulation time 615211227 ps
CPU time 23.09 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:29 PM PDT 24
Peak memory 250780 kb
Host smart-835d26f8-079d-4f86-9f2c-7acc378a4a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552934460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.552934460
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1050444232
Short name T522
Test name
Test status
Simulation time 1183823888 ps
CPU time 7.75 seconds
Started Jul 09 05:27:05 PM PDT 24
Finished Jul 09 05:27:14 PM PDT 24
Peak memory 250892 kb
Host smart-89cea9a1-6f5f-49c8-adfb-a4c94927e32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050444232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1050444232
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1185208058
Short name T372
Test name
Test status
Simulation time 11302613910 ps
CPU time 129.13 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:29:14 PM PDT 24
Peak memory 283720 kb
Host smart-ca9e7344-9480-461e-b2d8-8022a5a45992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185208058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1185208058
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2579246439
Short name T604
Test name
Test status
Simulation time 28553858072 ps
CPU time 685.64 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:38:30 PM PDT 24
Peak memory 356612 kb
Host smart-2c1514f0-4dd0-4189-9a90-847514d7140b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2579246439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2579246439
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1104320531
Short name T535
Test name
Test status
Simulation time 85051612 ps
CPU time 0.83 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:07 PM PDT 24
Peak memory 211848 kb
Host smart-481c994c-dc4e-4596-9ebc-e6e6ad38a08d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104320531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1104320531
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.817948115
Short name T476
Test name
Test status
Simulation time 85885985 ps
CPU time 0.92 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:27:05 PM PDT 24
Peak memory 208812 kb
Host smart-a09781af-e22b-40b9-8c68-7b04c85f7235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817948115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.817948115
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3507460936
Short name T351
Test name
Test status
Simulation time 1046994943 ps
CPU time 9.22 seconds
Started Jul 09 05:27:08 PM PDT 24
Finished Jul 09 05:27:18 PM PDT 24
Peak memory 218172 kb
Host smart-9fdfa0e5-b437-4853-a091-b55d20663b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507460936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3507460936
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1179301201
Short name T602
Test name
Test status
Simulation time 1111675397 ps
CPU time 11.93 seconds
Started Jul 09 05:27:01 PM PDT 24
Finished Jul 09 05:27:15 PM PDT 24
Peak memory 217428 kb
Host smart-36d7ccdb-01f8-4c0c-8a9d-8eb61d3da587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179301201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1179301201
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3884540813
Short name T226
Test name
Test status
Simulation time 92936798 ps
CPU time 3.64 seconds
Started Jul 09 05:27:05 PM PDT 24
Finished Jul 09 05:27:10 PM PDT 24
Peak memory 222524 kb
Host smart-630cc13c-bcc7-4040-b62b-2f4b408b1661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884540813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3884540813
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3580010137
Short name T438
Test name
Test status
Simulation time 315293252 ps
CPU time 11.81 seconds
Started Jul 09 05:27:00 PM PDT 24
Finished Jul 09 05:27:14 PM PDT 24
Peak memory 225940 kb
Host smart-99921133-0e93-441c-8122-1f7e19d04be5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580010137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3580010137
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3615271751
Short name T99
Test name
Test status
Simulation time 783429701 ps
CPU time 14.64 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:21 PM PDT 24
Peak memory 225968 kb
Host smart-046eaafc-d8b1-4946-b4b3-98f8f1767d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615271751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3615271751
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.391128073
Short name T257
Test name
Test status
Simulation time 1090341745 ps
CPU time 10.03 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:15 PM PDT 24
Peak memory 218056 kb
Host smart-0a2ab259-0010-48e4-a4d5-7e1b40bb5fe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391128073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.391128073
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2494287552
Short name T643
Test name
Test status
Simulation time 209851281 ps
CPU time 9.68 seconds
Started Jul 09 05:27:01 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 226108 kb
Host smart-4090f803-fcfe-4174-80e7-10e582f0cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494287552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2494287552
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.4164802683
Short name T638
Test name
Test status
Simulation time 286392248 ps
CPU time 4.18 seconds
Started Jul 09 05:26:59 PM PDT 24
Finished Jul 09 05:27:04 PM PDT 24
Peak memory 217560 kb
Host smart-c5f8c6fb-eee7-46ba-b0b3-e83ea5566079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164802683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.4164802683
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.4041437061
Short name T751
Test name
Test status
Simulation time 298574674 ps
CPU time 31.34 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:37 PM PDT 24
Peak memory 250912 kb
Host smart-fedf22be-0be0-4d4d-9c8f-c2feeac26d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041437061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.4041437061
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1469852642
Short name T554
Test name
Test status
Simulation time 134956871 ps
CPU time 4.01 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:09 PM PDT 24
Peak memory 222336 kb
Host smart-f6d94d02-1a3a-4076-ad3e-6b06e56a05ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469852642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1469852642
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4147097769
Short name T682
Test name
Test status
Simulation time 8472331280 ps
CPU time 142.74 seconds
Started Jul 09 05:27:06 PM PDT 24
Finished Jul 09 05:29:30 PM PDT 24
Peak memory 268448 kb
Host smart-d2370b77-ee74-47d5-a788-1a38f2bc88bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147097769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4147097769
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2151172749
Short name T104
Test name
Test status
Simulation time 95048856373 ps
CPU time 305.91 seconds
Started Jul 09 05:27:06 PM PDT 24
Finished Jul 09 05:32:13 PM PDT 24
Peak memory 333072 kb
Host smart-417a053a-9a8e-481e-ab03-dd9dcc8f587a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2151172749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2151172749
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.137838533
Short name T421
Test name
Test status
Simulation time 52615668 ps
CPU time 0.98 seconds
Started Jul 09 05:28:40 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 211900 kb
Host smart-d3b42d98-04b7-4ddc-bc9c-762a55fc8dd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137838533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.137838533
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2295414621
Short name T524
Test name
Test status
Simulation time 58596085 ps
CPU time 0.97 seconds
Started Jul 09 05:27:01 PM PDT 24
Finished Jul 09 05:27:03 PM PDT 24
Peak memory 208896 kb
Host smart-15a31786-fc7c-4acd-b8e6-6f494f27afe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295414621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2295414621
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.399601170
Short name T347
Test name
Test status
Simulation time 1037792864 ps
CPU time 12.78 seconds
Started Jul 09 05:27:05 PM PDT 24
Finished Jul 09 05:27:19 PM PDT 24
Peak memory 226000 kb
Host smart-5f9667ef-c6c2-4246-a8f0-4a8f1c004d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399601170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.399601170
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2783801165
Short name T25
Test name
Test status
Simulation time 1564477007 ps
CPU time 6.42 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:12 PM PDT 24
Peak memory 217208 kb
Host smart-e44c34d4-0227-4473-a28d-82abc1bb1b6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783801165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2783801165
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2720419247
Short name T491
Test name
Test status
Simulation time 62651235 ps
CPU time 2.82 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 218208 kb
Host smart-f1146724-22e6-453f-b352-510acbe7f6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720419247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2720419247
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2412650504
Short name T527
Test name
Test status
Simulation time 285776165 ps
CPU time 11.61 seconds
Started Jul 09 05:27:05 PM PDT 24
Finished Jul 09 05:27:18 PM PDT 24
Peak memory 218012 kb
Host smart-0061abba-adcd-4f41-9582-a5d09d6d13a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412650504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2412650504
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4276859481
Short name T816
Test name
Test status
Simulation time 1249732447 ps
CPU time 23.77 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:29 PM PDT 24
Peak memory 225856 kb
Host smart-5cdc9356-9675-413d-9b89-78f4ffb6bdc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276859481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4276859481
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.4096669579
Short name T534
Test name
Test status
Simulation time 1848438345 ps
CPU time 8.63 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 218204 kb
Host smart-6f35ba8b-c932-473b-b080-2d8ea89961e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096669579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
4096669579
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1142965314
Short name T855
Test name
Test status
Simulation time 942085312 ps
CPU time 9.53 seconds
Started Jul 09 05:27:05 PM PDT 24
Finished Jul 09 05:27:16 PM PDT 24
Peak memory 218228 kb
Host smart-b7798fd3-7695-444e-b818-ca9348621e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142965314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1142965314
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4271963501
Short name T774
Test name
Test status
Simulation time 1257346000 ps
CPU time 10 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:16 PM PDT 24
Peak memory 217660 kb
Host smart-7516f722-b8fb-468c-865c-41dc17e77fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271963501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4271963501
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2936986034
Short name T555
Test name
Test status
Simulation time 1128390796 ps
CPU time 27.53 seconds
Started Jul 09 05:27:05 PM PDT 24
Finished Jul 09 05:27:34 PM PDT 24
Peak memory 250728 kb
Host smart-6c12146a-5286-4e5e-9dd6-93833a4ca3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936986034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2936986034
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3421871896
Short name T300
Test name
Test status
Simulation time 124450009 ps
CPU time 3.59 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:09 PM PDT 24
Peak memory 222352 kb
Host smart-6948dd59-d735-446d-a0c6-8a5abb7e4962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421871896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3421871896
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.444077083
Short name T788
Test name
Test status
Simulation time 9928714281 ps
CPU time 201.4 seconds
Started Jul 09 05:27:02 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 279252 kb
Host smart-69688813-16d4-46ea-801d-4d614d8994fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444077083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.444077083
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.774118133
Short name T489
Test name
Test status
Simulation time 95471170 ps
CPU time 0.87 seconds
Started Jul 09 05:27:03 PM PDT 24
Finished Jul 09 05:27:06 PM PDT 24
Peak memory 211856 kb
Host smart-0d9277e1-26c2-41ab-b3ad-59b557a4fdc3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774118133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.774118133
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.647619834
Short name T659
Test name
Test status
Simulation time 61666328 ps
CPU time 1.07 seconds
Started Jul 09 05:27:17 PM PDT 24
Finished Jul 09 05:27:20 PM PDT 24
Peak memory 209032 kb
Host smart-9bfcc4a3-f206-406a-a792-01beeed7e40b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647619834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.647619834
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3025479403
Short name T662
Test name
Test status
Simulation time 2218235036 ps
CPU time 16 seconds
Started Jul 09 05:27:08 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 218188 kb
Host smart-e97f201e-3bdc-4235-8ced-d34541b5645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025479403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3025479403
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3852006123
Short name T850
Test name
Test status
Simulation time 2183640813 ps
CPU time 7.97 seconds
Started Jul 09 05:27:06 PM PDT 24
Finished Jul 09 05:27:15 PM PDT 24
Peak memory 217076 kb
Host smart-db4edaf0-0b1c-4c84-86ce-d832423b327b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852006123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3852006123
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.139124181
Short name T415
Test name
Test status
Simulation time 200990069 ps
CPU time 2.57 seconds
Started Jul 09 05:27:15 PM PDT 24
Finished Jul 09 05:27:20 PM PDT 24
Peak memory 218268 kb
Host smart-aa128318-664c-45c7-8ba1-3bfe0241e910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139124181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.139124181
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2384488358
Short name T383
Test name
Test status
Simulation time 322443937 ps
CPU time 13.07 seconds
Started Jul 09 05:27:08 PM PDT 24
Finished Jul 09 05:27:22 PM PDT 24
Peak memory 225888 kb
Host smart-750a0ea8-6338-4ad7-889c-02949e774f23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384488358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2384488358
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.996904662
Short name T168
Test name
Test status
Simulation time 1314219265 ps
CPU time 15.06 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:32 PM PDT 24
Peak memory 225976 kb
Host smart-869c58a1-e01f-4da0-9722-189af20584a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996904662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.996904662
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.229709782
Short name T862
Test name
Test status
Simulation time 512506509 ps
CPU time 11.96 seconds
Started Jul 09 05:27:10 PM PDT 24
Finished Jul 09 05:27:23 PM PDT 24
Peak memory 218204 kb
Host smart-bb0e8090-b25e-4a50-8ab6-544b0999c14a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229709782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.229709782
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4157305306
Short name T789
Test name
Test status
Simulation time 435145608 ps
CPU time 15.7 seconds
Started Jul 09 05:27:08 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 218252 kb
Host smart-10c99b54-174a-43cb-9b83-767fcc19a013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157305306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4157305306
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.916074289
Short name T824
Test name
Test status
Simulation time 376289592 ps
CPU time 2.13 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:08 PM PDT 24
Peak memory 217580 kb
Host smart-7c790ab9-4646-4eda-939b-a65dcfecb5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916074289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.916074289
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.547511576
Short name T26
Test name
Test status
Simulation time 822802767 ps
CPU time 21.36 seconds
Started Jul 09 05:27:06 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 250936 kb
Host smart-eaa47722-4387-45af-96bb-e9b5d3591e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547511576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.547511576
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.482386333
Short name T745
Test name
Test status
Simulation time 232102228 ps
CPU time 3.04 seconds
Started Jul 09 05:27:06 PM PDT 24
Finished Jul 09 05:27:10 PM PDT 24
Peak memory 222704 kb
Host smart-de136210-e2ef-4faa-ad19-3ca297ba2573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482386333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.482386333
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1183230632
Short name T760
Test name
Test status
Simulation time 3092202101 ps
CPU time 77.73 seconds
Started Jul 09 05:27:09 PM PDT 24
Finished Jul 09 05:28:27 PM PDT 24
Peak memory 269616 kb
Host smart-bb9a31f9-6b10-44ae-9c61-763f21a109d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183230632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1183230632
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3771439277
Short name T169
Test name
Test status
Simulation time 35302249 ps
CPU time 0.88 seconds
Started Jul 09 05:27:05 PM PDT 24
Finished Jul 09 05:27:07 PM PDT 24
Peak memory 211916 kb
Host smart-b49f3b2b-a9ce-441a-9ab1-e0c1db908a91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771439277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3771439277
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1156826563
Short name T493
Test name
Test status
Simulation time 58807573 ps
CPU time 0.91 seconds
Started Jul 09 05:25:49 PM PDT 24
Finished Jul 09 05:25:52 PM PDT 24
Peak memory 208820 kb
Host smart-fcf8ba87-055f-47af-8057-887cf2ea1d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156826563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1156826563
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1246996088
Short name T837
Test name
Test status
Simulation time 1521731453 ps
CPU time 10.32 seconds
Started Jul 09 05:25:39 PM PDT 24
Finished Jul 09 05:25:49 PM PDT 24
Peak memory 218116 kb
Host smart-a0c3adc0-832b-4a95-8cf6-536843769de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246996088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1246996088
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.246691397
Short name T495
Test name
Test status
Simulation time 74372843 ps
CPU time 1.76 seconds
Started Jul 09 05:25:37 PM PDT 24
Finished Jul 09 05:25:40 PM PDT 24
Peak memory 217096 kb
Host smart-ed6d210e-96b0-4ca5-ba92-3919697a93b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246691397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.246691397
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4251268285
Short name T188
Test name
Test status
Simulation time 1968541388 ps
CPU time 61.85 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:26:52 PM PDT 24
Peak memory 218740 kb
Host smart-97c36cd7-cc40-44e1-a65f-a954a93b952d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251268285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4251268285
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.4231878731
Short name T213
Test name
Test status
Simulation time 821315769 ps
CPU time 2.96 seconds
Started Jul 09 05:25:49 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 217556 kb
Host smart-85fe1046-e4a5-47c8-8080-3aab0f4bd1e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231878731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.4
231878731
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3897614854
Short name T371
Test name
Test status
Simulation time 825623597 ps
CPU time 7.38 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:25:55 PM PDT 24
Peak memory 218084 kb
Host smart-e81e5f65-d51d-4b30-ba0c-d2a9d6ef8331
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897614854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3897614854
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.4177763224
Short name T859
Test name
Test status
Simulation time 2212010558 ps
CPU time 26.96 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:26:17 PM PDT 24
Peak memory 217704 kb
Host smart-0fe910e0-107f-497f-9a1d-1363b802dd49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177763224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.4177763224
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.487894703
Short name T69
Test name
Test status
Simulation time 1128744968 ps
CPU time 4.27 seconds
Started Jul 09 05:25:54 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 217544 kb
Host smart-767f1137-09cb-40f3-9b99-01e3ec4fe40c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487894703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.487894703
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1823146044
Short name T513
Test name
Test status
Simulation time 889728846 ps
CPU time 45.25 seconds
Started Jul 09 05:25:49 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 275528 kb
Host smart-239c8e5c-4624-4efe-b17a-58818404ffdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823146044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1823146044
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2098361558
Short name T281
Test name
Test status
Simulation time 954253460 ps
CPU time 13.95 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 250704 kb
Host smart-96b84757-309a-4949-9f62-feb5268ce9c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098361558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2098361558
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4029581229
Short name T698
Test name
Test status
Simulation time 19376353 ps
CPU time 1.47 seconds
Started Jul 09 05:28:03 PM PDT 24
Finished Jul 09 05:28:05 PM PDT 24
Peak memory 218296 kb
Host smart-5291951b-d1d5-4eda-9af4-9ab171036828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029581229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4029581229
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.465775713
Short name T193
Test name
Test status
Simulation time 415517452 ps
CPU time 21.98 seconds
Started Jul 09 05:25:53 PM PDT 24
Finished Jul 09 05:26:16 PM PDT 24
Peak memory 214736 kb
Host smart-827f7077-73d6-46ca-a128-fe380b8d879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465775713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.465775713
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2491184694
Short name T96
Test name
Test status
Simulation time 598252803 ps
CPU time 25.22 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:14 PM PDT 24
Peak memory 268788 kb
Host smart-fddddc20-c23c-4345-a940-bb4aa7d2e7cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491184694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2491184694
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2474235705
Short name T742
Test name
Test status
Simulation time 3999807345 ps
CPU time 20.26 seconds
Started Jul 09 05:25:52 PM PDT 24
Finished Jul 09 05:26:13 PM PDT 24
Peak memory 220168 kb
Host smart-0dc59049-98a1-4bb7-aff0-f81f1be52b90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474235705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2474235705
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3136487027
Short name T546
Test name
Test status
Simulation time 332749900 ps
CPU time 8.59 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:25:58 PM PDT 24
Peak memory 225844 kb
Host smart-faa7e027-d584-4021-bf59-68235a054a40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136487027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3136487027
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2345151309
Short name T446
Test name
Test status
Simulation time 660063721 ps
CPU time 5.38 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 218060 kb
Host smart-cfac4a8f-09af-418e-8119-53de27efc10e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345151309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
345151309
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3108869794
Short name T53
Test name
Test status
Simulation time 809423898 ps
CPU time 7.78 seconds
Started Jul 09 05:25:50 PM PDT 24
Finished Jul 09 05:25:59 PM PDT 24
Peak memory 218296 kb
Host smart-11ebc251-0245-4425-b451-0684d30f58f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108869794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3108869794
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.121172392
Short name T397
Test name
Test status
Simulation time 382228642 ps
CPU time 3.07 seconds
Started Jul 09 05:25:50 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 217704 kb
Host smart-2ac98329-4048-48a3-89d1-6a5eb4c67266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121172392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.121172392
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.468922502
Short name T673
Test name
Test status
Simulation time 183996250 ps
CPU time 23.85 seconds
Started Jul 09 05:25:39 PM PDT 24
Finished Jul 09 05:26:03 PM PDT 24
Peak memory 250948 kb
Host smart-ada0140f-ce20-4c16-a7c6-1befb04fa26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468922502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.468922502
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1091816975
Short name T483
Test name
Test status
Simulation time 287666348 ps
CPU time 10.32 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 251196 kb
Host smart-3f66dafe-5cc5-4023-8dfe-752baa5e51f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091816975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1091816975
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.763285845
Short name T533
Test name
Test status
Simulation time 13671639182 ps
CPU time 192.09 seconds
Started Jul 09 05:25:53 PM PDT 24
Finished Jul 09 05:29:07 PM PDT 24
Peak memory 280308 kb
Host smart-16e33059-c1c4-4b53-a582-4f9154018ec1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763285845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.763285845
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.783628082
Short name T241
Test name
Test status
Simulation time 43598544 ps
CPU time 0.7 seconds
Started Jul 09 05:25:52 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 206940 kb
Host smart-59295f2d-c6b4-4612-9614-d98cb64d2711
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783628082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.783628082
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1472059529
Short name T696
Test name
Test status
Simulation time 57841538 ps
CPU time 0.81 seconds
Started Jul 09 05:27:04 PM PDT 24
Finished Jul 09 05:27:06 PM PDT 24
Peak memory 208984 kb
Host smart-c23da68d-4749-4676-81d2-62be2173cd0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472059529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1472059529
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3341286403
Short name T340
Test name
Test status
Simulation time 653789551 ps
CPU time 11.06 seconds
Started Jul 09 05:27:10 PM PDT 24
Finished Jul 09 05:27:21 PM PDT 24
Peak memory 218268 kb
Host smart-048a6f40-75df-4f9f-98a9-62d932cf49b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341286403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3341286403
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2408539397
Short name T23
Test name
Test status
Simulation time 907583801 ps
CPU time 3.23 seconds
Started Jul 09 05:27:10 PM PDT 24
Finished Jul 09 05:27:14 PM PDT 24
Peak memory 217008 kb
Host smart-d78aac41-baf3-4fde-b5e7-5bed640e9169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408539397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2408539397
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3580592243
Short name T293
Test name
Test status
Simulation time 156401289 ps
CPU time 5.26 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 218080 kb
Host smart-93e2f8fb-db2f-485c-97c6-e94d3ada5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580592243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3580592243
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.268869549
Short name T625
Test name
Test status
Simulation time 582099704 ps
CPU time 16.01 seconds
Started Jul 09 05:27:07 PM PDT 24
Finished Jul 09 05:27:24 PM PDT 24
Peak memory 225884 kb
Host smart-7a604973-0f53-4284-9aa6-793765d9eb28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268869549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.268869549
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.304945406
Short name T647
Test name
Test status
Simulation time 1192237282 ps
CPU time 12.48 seconds
Started Jul 09 05:27:09 PM PDT 24
Finished Jul 09 05:27:23 PM PDT 24
Peak memory 225948 kb
Host smart-e0eeded4-7136-4681-961c-632c8ca900fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304945406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.304945406
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1211687215
Short name T746
Test name
Test status
Simulation time 352561605 ps
CPU time 12.81 seconds
Started Jul 09 05:27:06 PM PDT 24
Finished Jul 09 05:27:20 PM PDT 24
Peak memory 218168 kb
Host smart-de3dd538-2e80-410d-804f-f38c0123f356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211687215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1211687215
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1044936617
Short name T398
Test name
Test status
Simulation time 826651627 ps
CPU time 11.79 seconds
Started Jul 09 05:27:14 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 224820 kb
Host smart-e30c38df-1f91-4c44-ba3e-35e81c3a92d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044936617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1044936617
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1342769087
Short name T279
Test name
Test status
Simulation time 71442769 ps
CPU time 3.55 seconds
Started Jul 09 05:27:09 PM PDT 24
Finished Jul 09 05:27:13 PM PDT 24
Peak memory 217652 kb
Host smart-a99948e8-eef0-483d-ac60-04381b9123f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342769087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1342769087
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.880758879
Short name T304
Test name
Test status
Simulation time 339095792 ps
CPU time 32.18 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:50 PM PDT 24
Peak memory 250804 kb
Host smart-d247d342-4392-4900-9552-b963f0f589f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880758879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.880758879
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1871714001
Short name T29
Test name
Test status
Simulation time 45839651 ps
CPU time 6.37 seconds
Started Jul 09 05:27:10 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 246788 kb
Host smart-bc13265c-a59b-4c5b-b6c5-58042ca14cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871714001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1871714001
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.312504699
Short name T413
Test name
Test status
Simulation time 25280290 ps
CPU time 1.07 seconds
Started Jul 09 05:27:10 PM PDT 24
Finished Jul 09 05:27:12 PM PDT 24
Peak memory 212948 kb
Host smart-9e8d4205-e961-4387-a48f-d34d9f513a0c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312504699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.312504699
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3824886473
Short name T574
Test name
Test status
Simulation time 20009109 ps
CPU time 1.2 seconds
Started Jul 09 05:27:15 PM PDT 24
Finished Jul 09 05:27:18 PM PDT 24
Peak memory 208740 kb
Host smart-51992946-dfd6-4196-bb72-17a924e98feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824886473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3824886473
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3914539943
Short name T849
Test name
Test status
Simulation time 2292343240 ps
CPU time 12.17 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:35 PM PDT 24
Peak memory 225948 kb
Host smart-51b4c888-4a43-4946-8f73-2b2bc7628515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914539943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3914539943
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1796410174
Short name T743
Test name
Test status
Simulation time 686464656 ps
CPU time 4.91 seconds
Started Jul 09 05:27:11 PM PDT 24
Finished Jul 09 05:27:16 PM PDT 24
Peak memory 217236 kb
Host smart-b4eab957-05eb-4c04-bbb1-114e597d6af4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796410174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1796410174
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.748378221
Short name T317
Test name
Test status
Simulation time 1554272469 ps
CPU time 3.14 seconds
Started Jul 09 05:27:11 PM PDT 24
Finished Jul 09 05:27:15 PM PDT 24
Peak memory 218184 kb
Host smart-b04f0143-1889-4e53-b3a0-45e49c502d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748378221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.748378221
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3089404835
Short name T458
Test name
Test status
Simulation time 4598858930 ps
CPU time 14.67 seconds
Started Jul 09 05:27:18 PM PDT 24
Finished Jul 09 05:27:34 PM PDT 24
Peak memory 225968 kb
Host smart-400c98ea-2843-47fd-9b25-216214872fac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089404835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3089404835
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1210863407
Short name T297
Test name
Test status
Simulation time 804355644 ps
CPU time 9.37 seconds
Started Jul 09 05:27:13 PM PDT 24
Finished Jul 09 05:27:24 PM PDT 24
Peak memory 225940 kb
Host smart-fed76db7-3df7-491a-b349-e74266bb4947
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210863407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1210863407
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3550768488
Short name T704
Test name
Test status
Simulation time 1201106735 ps
CPU time 10.75 seconds
Started Jul 09 05:27:23 PM PDT 24
Finished Jul 09 05:27:34 PM PDT 24
Peak memory 218120 kb
Host smart-e275a17d-6efa-4607-839b-e14cd941fc48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550768488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3550768488
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.215500053
Short name T754
Test name
Test status
Simulation time 52464080 ps
CPU time 2.54 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:20 PM PDT 24
Peak memory 214376 kb
Host smart-73f08310-d717-4ea9-8519-d4395715f48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215500053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.215500053
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3356104232
Short name T333
Test name
Test status
Simulation time 253052097 ps
CPU time 24.33 seconds
Started Jul 09 05:27:08 PM PDT 24
Finished Jul 09 05:27:33 PM PDT 24
Peak memory 250892 kb
Host smart-482bba26-d7f8-4c55-9a85-e55d66e79c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356104232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3356104232
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3727443341
Short name T714
Test name
Test status
Simulation time 94147091 ps
CPU time 6.73 seconds
Started Jul 09 05:27:12 PM PDT 24
Finished Jul 09 05:27:19 PM PDT 24
Peak memory 250836 kb
Host smart-22bb75d1-4e60-42aa-ba66-fbc541689f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727443341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3727443341
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1815043351
Short name T863
Test name
Test status
Simulation time 5340313627 ps
CPU time 85.69 seconds
Started Jul 09 05:27:14 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 224588 kb
Host smart-919a0f7e-4ef1-4a7f-a712-11a82335d3ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815043351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1815043351
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3714133184
Short name T215
Test name
Test status
Simulation time 28742170 ps
CPU time 0.9 seconds
Started Jul 09 05:27:09 PM PDT 24
Finished Jul 09 05:27:11 PM PDT 24
Peak memory 211808 kb
Host smart-c05b372a-37e7-43c0-bc56-d3fb806f0b38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714133184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3714133184
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.760409927
Short name T316
Test name
Test status
Simulation time 63468357 ps
CPU time 0.93 seconds
Started Jul 09 05:27:13 PM PDT 24
Finished Jul 09 05:27:16 PM PDT 24
Peak memory 208792 kb
Host smart-b7efa01a-c184-4831-be29-2fd729e68d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760409927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.760409927
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2182594157
Short name T847
Test name
Test status
Simulation time 875156572 ps
CPU time 10.73 seconds
Started Jul 09 05:27:12 PM PDT 24
Finished Jul 09 05:27:23 PM PDT 24
Peak memory 225872 kb
Host smart-7df6bd81-cee4-4b78-ad6e-6e57dc8c2335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182594157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2182594157
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.198688789
Short name T699
Test name
Test status
Simulation time 34151270 ps
CPU time 1.3 seconds
Started Jul 09 05:27:12 PM PDT 24
Finished Jul 09 05:27:14 PM PDT 24
Peak memory 216928 kb
Host smart-7ef148a5-1ee0-4f93-b0ac-7b0c00ab16c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198688789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.198688789
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1193705951
Short name T781
Test name
Test status
Simulation time 250500424 ps
CPU time 2.8 seconds
Started Jul 09 05:27:12 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 222068 kb
Host smart-bae350f7-d961-4b8b-9d30-2205fd224343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193705951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1193705951
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.422661738
Short name T404
Test name
Test status
Simulation time 818975969 ps
CPU time 9.51 seconds
Started Jul 09 05:27:12 PM PDT 24
Finished Jul 09 05:27:24 PM PDT 24
Peak memory 225904 kb
Host smart-807469a8-7f6d-4381-a9cb-96de2574ee35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422661738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.422661738
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.750213438
Short name T465
Test name
Test status
Simulation time 1602436609 ps
CPU time 11.38 seconds
Started Jul 09 05:27:18 PM PDT 24
Finished Jul 09 05:27:31 PM PDT 24
Peak memory 225900 kb
Host smart-9e103b22-656c-439b-ae37-87449eae9f1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750213438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.750213438
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3024980681
Short name T334
Test name
Test status
Simulation time 645752866 ps
CPU time 9.56 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 226000 kb
Host smart-2eee1222-de52-43a7-9c6a-101b9dce488f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024980681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3024980681
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3900208287
Short name T52
Test name
Test status
Simulation time 758209629 ps
CPU time 7.96 seconds
Started Jul 09 05:27:11 PM PDT 24
Finished Jul 09 05:27:19 PM PDT 24
Peak memory 224696 kb
Host smart-8f593c10-a8d5-4708-814b-cc4d1f4f0c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900208287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3900208287
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1263971275
Short name T295
Test name
Test status
Simulation time 51034551 ps
CPU time 1.28 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:19 PM PDT 24
Peak memory 213752 kb
Host smart-4014de68-574c-4bc5-bb53-407de624d819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263971275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1263971275
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.135276900
Short name T511
Test name
Test status
Simulation time 580069482 ps
CPU time 19.94 seconds
Started Jul 09 05:27:11 PM PDT 24
Finished Jul 09 05:27:31 PM PDT 24
Peak memory 250976 kb
Host smart-f70c01ce-16eb-43c9-bf5b-d834b00e1084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135276900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.135276900
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3772903775
Short name T179
Test name
Test status
Simulation time 186048070 ps
CPU time 6.01 seconds
Started Jul 09 05:27:13 PM PDT 24
Finished Jul 09 05:27:21 PM PDT 24
Peak memory 250492 kb
Host smart-b2a8be4d-5fdb-4142-8ded-e874045c9324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772903775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3772903775
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.4062202062
Short name T3
Test name
Test status
Simulation time 693893899 ps
CPU time 23.94 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:42 PM PDT 24
Peak memory 250784 kb
Host smart-be6ffa82-b0de-4a14-a854-5433e22116af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062202062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.4062202062
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.4235044820
Short name T167
Test name
Test status
Simulation time 38255045008 ps
CPU time 1184.04 seconds
Started Jul 09 05:27:19 PM PDT 24
Finished Jul 09 05:47:05 PM PDT 24
Peak memory 325888 kb
Host smart-21ea1230-a370-4f65-a338-684a118f47dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4235044820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.4235044820
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.534801522
Short name T234
Test name
Test status
Simulation time 14445258 ps
CPU time 1.18 seconds
Started Jul 09 05:27:15 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 211764 kb
Host smart-94f5f538-7a08-47f4-924c-35c80cc5866c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534801522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.534801522
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.724271265
Short name T715
Test name
Test status
Simulation time 19501349 ps
CPU time 0.94 seconds
Started Jul 09 05:27:24 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 208904 kb
Host smart-039379b2-8248-4c42-acc8-86de47639335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724271265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.724271265
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1016860094
Short name T667
Test name
Test status
Simulation time 1035090964 ps
CPU time 11.3 seconds
Started Jul 09 05:27:12 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 218128 kb
Host smart-2c6d0d29-9238-4a7e-8a78-f48942d63492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016860094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1016860094
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1346746228
Short name T607
Test name
Test status
Simulation time 1071262203 ps
CPU time 4.12 seconds
Started Jul 09 05:27:17 PM PDT 24
Finished Jul 09 05:27:23 PM PDT 24
Peak memory 217060 kb
Host smart-dfdeed5f-e12c-47f3-9318-86e7c0477c8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346746228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1346746228
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3045748199
Short name T693
Test name
Test status
Simulation time 393849513 ps
CPU time 3.28 seconds
Started Jul 09 05:27:13 PM PDT 24
Finished Jul 09 05:27:18 PM PDT 24
Peak memory 222368 kb
Host smart-0ce4bda9-e701-4026-81bb-50561875ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045748199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3045748199
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3386449351
Short name T470
Test name
Test status
Simulation time 614599610 ps
CPU time 11.75 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:30 PM PDT 24
Peak memory 218748 kb
Host smart-6d781e82-387f-49fb-9aaa-bdbc786aa520
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386449351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3386449351
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1131006390
Short name T240
Test name
Test status
Simulation time 1365939774 ps
CPU time 11.42 seconds
Started Jul 09 05:27:17 PM PDT 24
Finished Jul 09 05:27:30 PM PDT 24
Peak memory 226020 kb
Host smart-3583d038-904b-4e48-b121-39e35471142f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131006390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1131006390
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.719784031
Short name T633
Test name
Test status
Simulation time 1321910204 ps
CPU time 9.77 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 218240 kb
Host smart-213b6277-7487-41cd-b4d6-dc99d4e48ad8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719784031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.719784031
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2244828953
Short name T456
Test name
Test status
Simulation time 381004171 ps
CPU time 16.29 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:34 PM PDT 24
Peak memory 225260 kb
Host smart-ac89be8a-6321-48c0-b432-73fd98209c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244828953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2244828953
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2235569911
Short name T440
Test name
Test status
Simulation time 82369988 ps
CPU time 3.11 seconds
Started Jul 09 05:27:15 PM PDT 24
Finished Jul 09 05:27:19 PM PDT 24
Peak memory 217652 kb
Host smart-39ddae6a-1bf0-4a56-a19d-f106745ba616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235569911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2235569911
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3888251306
Short name T190
Test name
Test status
Simulation time 2060181516 ps
CPU time 21.68 seconds
Started Jul 09 05:27:18 PM PDT 24
Finished Jul 09 05:27:42 PM PDT 24
Peak memory 251016 kb
Host smart-59fbd689-0260-47fe-abb2-e2a1575afba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888251306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3888251306
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2428737320
Short name T578
Test name
Test status
Simulation time 292286579 ps
CPU time 6.4 seconds
Started Jul 09 05:27:15 PM PDT 24
Finished Jul 09 05:27:23 PM PDT 24
Peak memory 246868 kb
Host smart-163c0fc9-aa37-4904-9e6b-d0b563d78c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428737320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2428737320
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1539114293
Short name T752
Test name
Test status
Simulation time 16311622279 ps
CPU time 70.67 seconds
Started Jul 09 05:27:19 PM PDT 24
Finished Jul 09 05:28:31 PM PDT 24
Peak memory 267256 kb
Host smart-c8e8012a-c020-4d6e-b2ea-52e4955091ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539114293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1539114293
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2988031193
Short name T18
Test name
Test status
Simulation time 2885260957 ps
CPU time 82.92 seconds
Started Jul 09 05:27:17 PM PDT 24
Finished Jul 09 05:28:42 PM PDT 24
Peak memory 277756 kb
Host smart-81fb3ba5-61a3-4436-864e-6938a95d70d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2988031193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2988031193
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1362825333
Short name T462
Test name
Test status
Simulation time 23963916 ps
CPU time 0.91 seconds
Started Jul 09 05:27:15 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 212656 kb
Host smart-c311ac7b-2d59-4c2e-8ff2-36cb13c546d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362825333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1362825333
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2002513597
Short name T266
Test name
Test status
Simulation time 96066090 ps
CPU time 0.91 seconds
Started Jul 09 05:27:14 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 209008 kb
Host smart-cae6d42b-5285-4f7d-b6ee-29af9348a8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002513597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2002513597
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.702984864
Short name T277
Test name
Test status
Simulation time 242536188 ps
CPU time 9.68 seconds
Started Jul 09 05:27:17 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 218128 kb
Host smart-98531971-9fd1-47b6-ab3e-c484dd66f3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702984864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.702984864
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1755039079
Short name T828
Test name
Test status
Simulation time 91686170 ps
CPU time 1.98 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:24 PM PDT 24
Peak memory 216892 kb
Host smart-3be7672c-e4c9-437c-89c3-bf2f907f5c40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755039079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1755039079
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3152309730
Short name T505
Test name
Test status
Simulation time 79391207 ps
CPU time 2.66 seconds
Started Jul 09 05:27:18 PM PDT 24
Finished Jul 09 05:27:22 PM PDT 24
Peak memory 222040 kb
Host smart-9d35481e-de87-4c00-a436-ac5d33469bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152309730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3152309730
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2964703059
Short name T380
Test name
Test status
Simulation time 542647423 ps
CPU time 9.15 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:31 PM PDT 24
Peak memory 226000 kb
Host smart-8812cc4f-5629-42e8-8cdd-5e435ddcd7d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964703059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2964703059
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.681822364
Short name T500
Test name
Test status
Simulation time 522875453 ps
CPU time 17.44 seconds
Started Jul 09 05:27:20 PM PDT 24
Finished Jul 09 05:27:39 PM PDT 24
Peak memory 218168 kb
Host smart-67af6e72-6c8d-4f27-84d6-bbdf64b1e4ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681822364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.681822364
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.975822962
Short name T666
Test name
Test status
Simulation time 388884166 ps
CPU time 7.97 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 224700 kb
Host smart-4d127e76-b796-40ae-981b-6e6de2cb9905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975822962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.975822962
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1644563496
Short name T627
Test name
Test status
Simulation time 127507793 ps
CPU time 2.51 seconds
Started Jul 09 05:27:19 PM PDT 24
Finished Jul 09 05:27:23 PM PDT 24
Peak memory 223396 kb
Host smart-4e5c579a-b2e0-449d-9938-2687c23bf1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644563496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1644563496
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3971952116
Short name T90
Test name
Test status
Simulation time 1268436012 ps
CPU time 34.65 seconds
Started Jul 09 05:27:20 PM PDT 24
Finished Jul 09 05:27:56 PM PDT 24
Peak memory 250928 kb
Host smart-a6791ea4-5329-4b1c-a40f-011e79a912bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971952116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3971952116
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.627074949
Short name T812
Test name
Test status
Simulation time 41707976 ps
CPU time 3.04 seconds
Started Jul 09 05:27:16 PM PDT 24
Finished Jul 09 05:27:21 PM PDT 24
Peak memory 222352 kb
Host smart-0333e008-d5fc-49e4-b186-2a14d9372096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627074949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.627074949
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3286130272
Short name T557
Test name
Test status
Simulation time 10374901692 ps
CPU time 72.56 seconds
Started Jul 09 05:27:17 PM PDT 24
Finished Jul 09 05:28:32 PM PDT 24
Peak memory 281544 kb
Host smart-737aaaa0-ea84-47a4-8fa0-9c7fee953e77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286130272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3286130272
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.270588289
Short name T562
Test name
Test status
Simulation time 12878551 ps
CPU time 1.05 seconds
Started Jul 09 05:27:14 PM PDT 24
Finished Jul 09 05:27:17 PM PDT 24
Peak memory 211904 kb
Host smart-9f2f517e-bb78-44d7-8c53-25a91affff15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270588289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.270588289
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.794226062
Short name T75
Test name
Test status
Simulation time 15972463 ps
CPU time 0.9 seconds
Started Jul 09 05:27:24 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 208904 kb
Host smart-cbf6589d-7409-4c77-9d3d-dcbb201e3ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794226062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.794226062
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.4227570391
Short name T14
Test name
Test status
Simulation time 466176128 ps
CPU time 12.37 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:35 PM PDT 24
Peak memory 218000 kb
Host smart-917698b6-6d79-4d5d-ac5a-cbf9ece3a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227570391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4227570391
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.194544782
Short name T648
Test name
Test status
Simulation time 259586574 ps
CPU time 4.45 seconds
Started Jul 09 05:27:17 PM PDT 24
Finished Jul 09 05:27:24 PM PDT 24
Peak memory 217216 kb
Host smart-01069856-4f38-4700-850a-14710e826823
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194544782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.194544782
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1195444129
Short name T486
Test name
Test status
Simulation time 160429008 ps
CPU time 2.9 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 222280 kb
Host smart-cacd26e2-f7ac-455d-847e-4293c22c32ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195444129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1195444129
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3173091987
Short name T593
Test name
Test status
Simulation time 321180366 ps
CPU time 11 seconds
Started Jul 09 05:27:20 PM PDT 24
Finished Jul 09 05:27:33 PM PDT 24
Peak memory 218160 kb
Host smart-75138ab0-33ae-4730-b861-b5c713cfed3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173091987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3173091987
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2521090616
Short name T414
Test name
Test status
Simulation time 412155358 ps
CPU time 11.88 seconds
Started Jul 09 05:27:26 PM PDT 24
Finished Jul 09 05:27:38 PM PDT 24
Peak memory 225996 kb
Host smart-1e7109d3-8010-4f08-8a7a-3fa8233ad3f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521090616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2521090616
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1425062228
Short name T326
Test name
Test status
Simulation time 764536078 ps
CPU time 23.32 seconds
Started Jul 09 05:27:26 PM PDT 24
Finished Jul 09 05:27:50 PM PDT 24
Peak memory 225892 kb
Host smart-d342ec0a-4b52-45eb-86d9-7c43fc7c3d0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425062228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1425062228
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1331035715
Short name T379
Test name
Test status
Simulation time 974590882 ps
CPU time 8.29 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:30 PM PDT 24
Peak memory 218368 kb
Host smart-4f4938d3-d39f-4e1a-b4ea-fa2ce1ccd315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331035715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1331035715
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1518766670
Short name T393
Test name
Test status
Simulation time 102331331 ps
CPU time 2.42 seconds
Started Jul 09 05:27:22 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 214352 kb
Host smart-321b84c5-4801-4ff4-a012-8378a677bafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518766670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1518766670
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3467467601
Short name T609
Test name
Test status
Simulation time 2615936849 ps
CPU time 24.98 seconds
Started Jul 09 05:27:23 PM PDT 24
Finished Jul 09 05:27:49 PM PDT 24
Peak memory 251000 kb
Host smart-a1d33c64-41d7-486e-a0db-1c40c1f1bfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467467601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3467467601
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3370994032
Short name T653
Test name
Test status
Simulation time 228714891 ps
CPU time 2.77 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:25 PM PDT 24
Peak memory 224084 kb
Host smart-b40dd1a4-54ed-4104-a889-6b3aac20a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370994032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3370994032
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2526091844
Short name T71
Test name
Test status
Simulation time 37365492987 ps
CPU time 298.45 seconds
Started Jul 09 05:27:22 PM PDT 24
Finished Jul 09 05:32:21 PM PDT 24
Peak memory 274012 kb
Host smart-51213353-51d0-4b44-8f00-b7a8528caf0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526091844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2526091844
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3102976605
Short name T700
Test name
Test status
Simulation time 45988849 ps
CPU time 0.96 seconds
Started Jul 09 05:27:19 PM PDT 24
Finished Jul 09 05:27:21 PM PDT 24
Peak memory 212808 kb
Host smart-e9acab59-2cd7-4905-90b4-adbe614ca762
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102976605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3102976605
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2585672198
Short name T336
Test name
Test status
Simulation time 23508305 ps
CPU time 0.85 seconds
Started Jul 09 05:27:28 PM PDT 24
Finished Jul 09 05:27:30 PM PDT 24
Peak memory 208128 kb
Host smart-c624b853-cb31-4cc5-8cfd-d6e3c1e82240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585672198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2585672198
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1583889108
Short name T37
Test name
Test status
Simulation time 497803191 ps
CPU time 11.64 seconds
Started Jul 09 05:27:20 PM PDT 24
Finished Jul 09 05:27:33 PM PDT 24
Peak memory 218032 kb
Host smart-c1135e09-42b0-479b-9f3c-4fbf6ac301f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583889108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1583889108
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2891506977
Short name T810
Test name
Test status
Simulation time 1219758404 ps
CPU time 8.66 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:37 PM PDT 24
Peak memory 217696 kb
Host smart-096929e9-acd2-472d-9298-f0a40711ce26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891506977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2891506977
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1576811187
Short name T449
Test name
Test status
Simulation time 41013905 ps
CPU time 2.19 seconds
Started Jul 09 05:27:22 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 218172 kb
Host smart-121dad7d-baa5-48f6-8424-57388a2e8c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576811187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1576811187
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3058122990
Short name T451
Test name
Test status
Simulation time 584744232 ps
CPU time 15.62 seconds
Started Jul 09 05:27:17 PM PDT 24
Finished Jul 09 05:27:34 PM PDT 24
Peak memory 225972 kb
Host smart-18d72cea-5b03-4b80-a5cb-8b90c6eb9377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058122990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3058122990
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3180338736
Short name T806
Test name
Test status
Simulation time 2018089366 ps
CPU time 14.79 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:41 PM PDT 24
Peak memory 226000 kb
Host smart-2cf5f34d-ecc0-4d7b-ab84-cfaecb6a9ab6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180338736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3180338736
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4231079384
Short name T827
Test name
Test status
Simulation time 1015667292 ps
CPU time 14.11 seconds
Started Jul 09 05:27:23 PM PDT 24
Finished Jul 09 05:27:38 PM PDT 24
Peak memory 225988 kb
Host smart-bf7f5e01-63a6-4e48-9fb9-96a4a0521005
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231079384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4231079384
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.243963806
Short name T538
Test name
Test status
Simulation time 2734553995 ps
CPU time 11.79 seconds
Started Jul 09 05:27:22 PM PDT 24
Finished Jul 09 05:27:35 PM PDT 24
Peak memory 218108 kb
Host smart-5206bfec-2f6f-4111-8754-b84e339081b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243963806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.243963806
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.219861928
Short name T343
Test name
Test status
Simulation time 80805089 ps
CPU time 1 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:24 PM PDT 24
Peak memory 217672 kb
Host smart-f33c9d42-e2ef-43ad-80c7-4e896321eb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219861928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.219861928
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.490704718
Short name T271
Test name
Test status
Simulation time 1492051371 ps
CPU time 24.46 seconds
Started Jul 09 05:27:24 PM PDT 24
Finished Jul 09 05:27:49 PM PDT 24
Peak memory 250812 kb
Host smart-cdc3d0b5-c1c8-43a8-bf87-40124f37353e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490704718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.490704718
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2771374046
Short name T809
Test name
Test status
Simulation time 275749438 ps
CPU time 7.87 seconds
Started Jul 09 05:27:19 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 242756 kb
Host smart-ec1feaed-2024-44d7-8559-57f6c2e9adbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771374046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2771374046
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1855393890
Short name T603
Test name
Test status
Simulation time 15002781290 ps
CPU time 515.89 seconds
Started Jul 09 05:27:32 PM PDT 24
Finished Jul 09 05:36:09 PM PDT 24
Peak memory 250904 kb
Host smart-caab6ad2-a542-423b-8e27-fa21e64bd8c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855393890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1855393890
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1535918197
Short name T163
Test name
Test status
Simulation time 32653902841 ps
CPU time 470.74 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:35:13 PM PDT 24
Peak memory 332848 kb
Host smart-f0a55336-ac6d-4606-a773-14efe35f2e1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1535918197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1535918197
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1737273948
Short name T800
Test name
Test status
Simulation time 37315188 ps
CPU time 0.86 seconds
Started Jul 09 05:27:24 PM PDT 24
Finished Jul 09 05:27:26 PM PDT 24
Peak memory 208112 kb
Host smart-0f301887-5fb8-464e-82b3-50ad3cd82132
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737273948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1737273948
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3726528412
Short name T377
Test name
Test status
Simulation time 29680634 ps
CPU time 1.02 seconds
Started Jul 09 05:27:28 PM PDT 24
Finished Jul 09 05:27:30 PM PDT 24
Peak memory 208312 kb
Host smart-20de7c96-5696-4264-bff0-14980f532083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726528412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3726528412
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.4266238827
Short name T191
Test name
Test status
Simulation time 1259049402 ps
CPU time 8.99 seconds
Started Jul 09 05:27:26 PM PDT 24
Finished Jul 09 05:27:36 PM PDT 24
Peak memory 218132 kb
Host smart-e3c9a6cd-f86e-40df-90e9-b7dd8ceed543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266238827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.4266238827
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3443328798
Short name T845
Test name
Test status
Simulation time 831979388 ps
CPU time 3.31 seconds
Started Jul 09 05:27:29 PM PDT 24
Finished Jul 09 05:27:33 PM PDT 24
Peak memory 217048 kb
Host smart-f6ec8798-e0e7-40d3-b052-5e3e131075ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443328798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3443328798
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2398818796
Short name T831
Test name
Test status
Simulation time 124540824 ps
CPU time 3.35 seconds
Started Jul 09 05:27:22 PM PDT 24
Finished Jul 09 05:27:27 PM PDT 24
Peak memory 222440 kb
Host smart-66a406cd-0035-4ecc-b26b-fc0d7a11651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398818796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2398818796
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.9841716
Short name T544
Test name
Test status
Simulation time 1576445297 ps
CPU time 10.58 seconds
Started Jul 09 05:27:23 PM PDT 24
Finished Jul 09 05:27:34 PM PDT 24
Peak memory 218868 kb
Host smart-3c30fcdd-9bcc-4fe2-99a4-ecb12b75ace9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9841716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.9841716
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1414164682
Short name T756
Test name
Test status
Simulation time 323598852 ps
CPU time 10.04 seconds
Started Jul 09 05:27:20 PM PDT 24
Finished Jul 09 05:27:31 PM PDT 24
Peak memory 225940 kb
Host smart-c3e81489-a3ab-4bc9-9534-a0b58828fdda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414164682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1414164682
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2166974158
Short name T839
Test name
Test status
Simulation time 535385381 ps
CPU time 8.19 seconds
Started Jul 09 05:27:25 PM PDT 24
Finished Jul 09 05:27:34 PM PDT 24
Peak memory 225900 kb
Host smart-ae92905d-f513-4bf6-9dd2-027729e0f27f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166974158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2166974158
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.577341766
Short name T564
Test name
Test status
Simulation time 531552759 ps
CPU time 10.88 seconds
Started Jul 09 05:27:31 PM PDT 24
Finished Jul 09 05:27:42 PM PDT 24
Peak memory 225972 kb
Host smart-fc017cae-3127-419b-9795-d263f1fd3fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577341766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.577341766
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3647599191
Short name T160
Test name
Test status
Simulation time 289541354 ps
CPU time 1.6 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:29 PM PDT 24
Peak memory 222216 kb
Host smart-cc1836cf-7f08-4c3b-be0b-dee60e1596ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647599191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3647599191
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2085381081
Short name T174
Test name
Test status
Simulation time 1236303182 ps
CPU time 24.42 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:53 PM PDT 24
Peak memory 245680 kb
Host smart-2fc513dd-1c9b-44a1-9092-9c2a8e68f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085381081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2085381081
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1430015843
Short name T782
Test name
Test status
Simulation time 110772753 ps
CPU time 3.39 seconds
Started Jul 09 05:27:24 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 221132 kb
Host smart-50b66de8-77f9-44ed-aaf3-e638a9af8679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430015843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1430015843
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3308775161
Short name T85
Test name
Test status
Simulation time 20292113102 ps
CPU time 215.42 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:31:04 PM PDT 24
Peak memory 283644 kb
Host smart-d9b45f05-3878-4207-a625-6bbbf580bdaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308775161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3308775161
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1326190137
Short name T861
Test name
Test status
Simulation time 23507355 ps
CPU time 0.94 seconds
Started Jul 09 05:27:21 PM PDT 24
Finished Jul 09 05:27:23 PM PDT 24
Peak memory 211888 kb
Host smart-8f53d08a-aa2e-4494-a2a2-5f8fdb762876
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326190137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1326190137
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1097523037
Short name T541
Test name
Test status
Simulation time 83750719 ps
CPU time 1.17 seconds
Started Jul 09 05:27:31 PM PDT 24
Finished Jul 09 05:27:33 PM PDT 24
Peak memory 208800 kb
Host smart-194c13cd-61d4-466e-801c-daf76af53f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097523037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1097523037
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2782039021
Short name T787
Test name
Test status
Simulation time 488694514 ps
CPU time 9.39 seconds
Started Jul 09 05:27:28 PM PDT 24
Finished Jul 09 05:27:38 PM PDT 24
Peak memory 218112 kb
Host smart-63185974-f0b8-49b6-8a3b-601cef40835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782039021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2782039021
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3032662919
Short name T506
Test name
Test status
Simulation time 6591216477 ps
CPU time 14.31 seconds
Started Jul 09 05:27:39 PM PDT 24
Finished Jul 09 05:27:54 PM PDT 24
Peak memory 217752 kb
Host smart-cfcda9f7-2824-4828-8a7c-0087184e9b95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032662919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3032662919
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.637156782
Short name T464
Test name
Test status
Simulation time 234935719 ps
CPU time 3.6 seconds
Started Jul 09 05:27:25 PM PDT 24
Finished Jul 09 05:27:29 PM PDT 24
Peak memory 218092 kb
Host smart-793e7464-8798-442b-868d-3bae4c1eb5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637156782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.637156782
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3170455303
Short name T477
Test name
Test status
Simulation time 2612964197 ps
CPU time 10.64 seconds
Started Jul 09 05:27:29 PM PDT 24
Finished Jul 09 05:27:41 PM PDT 24
Peak memory 226032 kb
Host smart-59dcf26e-8a2c-4908-ad82-9e882619d49a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170455303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3170455303
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.689067422
Short name T482
Test name
Test status
Simulation time 1241096878 ps
CPU time 13.38 seconds
Started Jul 09 05:27:29 PM PDT 24
Finished Jul 09 05:27:43 PM PDT 24
Peak memory 226000 kb
Host smart-cd38d60d-8c54-49d3-ad67-73e95b576a6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689067422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.689067422
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.476119641
Short name T708
Test name
Test status
Simulation time 2942545423 ps
CPU time 7.2 seconds
Started Jul 09 05:27:29 PM PDT 24
Finished Jul 09 05:27:36 PM PDT 24
Peak memory 225236 kb
Host smart-c9ae0bb8-dd55-4690-87ab-f4cc57aa294b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476119641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.476119641
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3382419687
Short name T792
Test name
Test status
Simulation time 278742972 ps
CPU time 8.25 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:37 PM PDT 24
Peak memory 218328 kb
Host smart-d5c068fc-de7c-4538-af17-7459dc32575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382419687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3382419687
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2794809957
Short name T84
Test name
Test status
Simulation time 50187785 ps
CPU time 3.47 seconds
Started Jul 09 05:27:24 PM PDT 24
Finished Jul 09 05:27:28 PM PDT 24
Peak memory 217692 kb
Host smart-0c53a3a6-7e8d-4d03-b3e4-5a1bc4acce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794809957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2794809957
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3298760035
Short name T158
Test name
Test status
Simulation time 944720909 ps
CPU time 30.41 seconds
Started Jul 09 05:27:29 PM PDT 24
Finished Jul 09 05:28:00 PM PDT 24
Peak memory 250892 kb
Host smart-280bfbe4-bf13-4b5e-a62d-c4fc7cf4ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298760035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3298760035
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2398221150
Short name T661
Test name
Test status
Simulation time 126832830 ps
CPU time 3.78 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:32 PM PDT 24
Peak memory 222400 kb
Host smart-c333e4b1-c5d2-4a9c-9cec-5f827277f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398221150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2398221150
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1054115572
Short name T311
Test name
Test status
Simulation time 18289213555 ps
CPU time 101.17 seconds
Started Jul 09 05:27:25 PM PDT 24
Finished Jul 09 05:29:07 PM PDT 24
Peak memory 226044 kb
Host smart-2ab562d0-bb52-42e6-8f15-09c3aee075f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054115572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1054115572
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2581185588
Short name T214
Test name
Test status
Simulation time 47684470116 ps
CPU time 264.69 seconds
Started Jul 09 05:27:26 PM PDT 24
Finished Jul 09 05:31:52 PM PDT 24
Peak memory 283744 kb
Host smart-d51e76cd-0d54-4d12-b3be-1d8732b8cd0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2581185588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2581185588
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2731432850
Short name T520
Test name
Test status
Simulation time 22405661 ps
CPU time 0.96 seconds
Started Jul 09 05:27:25 PM PDT 24
Finished Jul 09 05:27:27 PM PDT 24
Peak memory 211776 kb
Host smart-45979897-90b4-435f-b4a3-0c302e8315ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731432850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2731432850
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1250674045
Short name T322
Test name
Test status
Simulation time 16910752 ps
CPU time 0.8 seconds
Started Jul 09 05:27:32 PM PDT 24
Finished Jul 09 05:27:34 PM PDT 24
Peak memory 208932 kb
Host smart-69e77d0a-adbd-4edb-a59b-936c1b3e10ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250674045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1250674045
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3185436868
Short name T273
Test name
Test status
Simulation time 309632137 ps
CPU time 15.96 seconds
Started Jul 09 05:27:29 PM PDT 24
Finished Jul 09 05:27:45 PM PDT 24
Peak memory 225992 kb
Host smart-b9822f44-0eaa-4a08-90e7-cfd335cd5ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185436868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3185436868
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2353101110
Short name T640
Test name
Test status
Simulation time 169486383 ps
CPU time 2.98 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:31 PM PDT 24
Peak memory 216900 kb
Host smart-399be66a-db9e-47fb-b682-e200786a8f76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353101110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2353101110
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3000058894
Short name T453
Test name
Test status
Simulation time 170836416 ps
CPU time 2.98 seconds
Started Jul 09 05:27:25 PM PDT 24
Finished Jul 09 05:27:29 PM PDT 24
Peak memory 222108 kb
Host smart-d0dadceb-387b-4a8c-ae35-8740584669cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000058894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3000058894
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1418012045
Short name T780
Test name
Test status
Simulation time 461177917 ps
CPU time 11.78 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:40 PM PDT 24
Peak memory 218864 kb
Host smart-462e7743-0623-45af-a14f-0671b792a3df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418012045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1418012045
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2045338497
Short name T518
Test name
Test status
Simulation time 1172067694 ps
CPU time 11.64 seconds
Started Jul 09 05:27:33 PM PDT 24
Finished Jul 09 05:27:45 PM PDT 24
Peak memory 225988 kb
Host smart-7d20c082-ad6e-443b-a103-c67f41bf9ade
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045338497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2045338497
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.318988005
Short name T353
Test name
Test status
Simulation time 328401596 ps
CPU time 11.8 seconds
Started Jul 09 05:27:30 PM PDT 24
Finished Jul 09 05:27:42 PM PDT 24
Peak memory 225844 kb
Host smart-beff4733-9069-4225-8977-7f3a27ee9135
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318988005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.318988005
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1277371028
Short name T630
Test name
Test status
Simulation time 742741322 ps
CPU time 7.5 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:35 PM PDT 24
Peak memory 218272 kb
Host smart-0c623145-d2f1-4f3b-b131-549bda670925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277371028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1277371028
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1641017430
Short name T70
Test name
Test status
Simulation time 42647359 ps
CPU time 2.69 seconds
Started Jul 09 05:27:29 PM PDT 24
Finished Jul 09 05:27:32 PM PDT 24
Peak memory 222788 kb
Host smart-b8b354d0-be08-4153-afc9-ca9f1f906ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641017430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1641017430
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1058835125
Short name T260
Test name
Test status
Simulation time 383343112 ps
CPU time 21.23 seconds
Started Jul 09 05:27:39 PM PDT 24
Finished Jul 09 05:28:00 PM PDT 24
Peak memory 250920 kb
Host smart-7d8ef825-81dd-43ab-be71-c79b24390bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058835125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1058835125
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2723624467
Short name T359
Test name
Test status
Simulation time 297679673 ps
CPU time 9.47 seconds
Started Jul 09 05:27:27 PM PDT 24
Finished Jul 09 05:27:37 PM PDT 24
Peak memory 250896 kb
Host smart-498a50e0-f27c-4fa6-b371-843d665d3ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723624467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2723624467
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3538633486
Short name T805
Test name
Test status
Simulation time 4553130902 ps
CPU time 45.1 seconds
Started Jul 09 05:27:30 PM PDT 24
Finished Jul 09 05:28:16 PM PDT 24
Peak memory 277668 kb
Host smart-fc78e989-06b8-4fa8-aeda-5b4d5fff7dcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538633486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3538633486
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1690699811
Short name T405
Test name
Test status
Simulation time 13334595 ps
CPU time 1.04 seconds
Started Jul 09 05:27:30 PM PDT 24
Finished Jul 09 05:27:31 PM PDT 24
Peak memory 211656 kb
Host smart-b893c18f-840c-4592-830f-e80c79bec362
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690699811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1690699811
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.278876339
Short name T736
Test name
Test status
Simulation time 38139526 ps
CPU time 0.89 seconds
Started Jul 09 05:25:58 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 208888 kb
Host smart-1d75d2a3-54ab-49c5-8462-5d4b6163ccff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278876339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.278876339
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2427856550
Short name T332
Test name
Test status
Simulation time 11514405 ps
CPU time 0.79 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:25:51 PM PDT 24
Peak memory 208724 kb
Host smart-ec7c73be-4805-4a89-8e82-8847cd332a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427856550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2427856550
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.788905309
Short name T41
Test name
Test status
Simulation time 422948280 ps
CPU time 18.19 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:26:09 PM PDT 24
Peak memory 218192 kb
Host smart-f9f246dd-2043-40c8-9bff-c229070f83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788905309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.788905309
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2555565388
Short name T542
Test name
Test status
Simulation time 1080477569 ps
CPU time 7.06 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:26:03 PM PDT 24
Peak memory 217240 kb
Host smart-e50c90f8-b057-4632-84ef-5e2c28dfebad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555565388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2555565388
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1345971256
Short name T35
Test name
Test status
Simulation time 2556600125 ps
CPU time 72.6 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:27:02 PM PDT 24
Peak memory 226004 kb
Host smart-274ab151-2fb8-4f6e-871f-e17b1b700021
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345971256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1345971256
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.413107630
Short name T6
Test name
Test status
Simulation time 1808242045 ps
CPU time 7.46 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:25:57 PM PDT 24
Peak memory 217476 kb
Host smart-7d6fc9ae-9b50-4755-8b67-5ab8967effbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413107630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.413107630
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2811825195
Short name T17
Test name
Test status
Simulation time 139465431 ps
CPU time 3.53 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:25:50 PM PDT 24
Peak memory 221660 kb
Host smart-f7a66dec-9361-41a2-99fb-96e57c160652
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811825195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2811825195
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.30630369
Short name T685
Test name
Test status
Simulation time 1243698251 ps
CPU time 20.24 seconds
Started Jul 09 05:25:52 PM PDT 24
Finished Jul 09 05:26:13 PM PDT 24
Peak memory 217684 kb
Host smart-94b65310-f330-4eff-bf29-a716fbb88c0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30630369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt
ag_regwen_during_op.30630369
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1326789358
Short name T558
Test name
Test status
Simulation time 77759575 ps
CPU time 1.85 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:25:49 PM PDT 24
Peak memory 217536 kb
Host smart-28247727-4192-4b89-9ad9-19a6e65265f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326789358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1326789358
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3130594410
Short name T345
Test name
Test status
Simulation time 11249877312 ps
CPU time 43.3 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:26:30 PM PDT 24
Peak memory 276596 kb
Host smart-b2343614-959a-4a6f-800b-6281ab741c59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130594410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3130594410
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.429445315
Short name T582
Test name
Test status
Simulation time 836216456 ps
CPU time 13.79 seconds
Started Jul 09 05:25:40 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 247496 kb
Host smart-5590b478-34ad-455b-a1a6-2007889464f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429445315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.429445315
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3015412455
Short name T697
Test name
Test status
Simulation time 60624024 ps
CPU time 2.16 seconds
Started Jul 09 05:25:54 PM PDT 24
Finished Jul 09 05:25:57 PM PDT 24
Peak memory 218040 kb
Host smart-dcabddc3-dba4-4a89-8263-f59c89068a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015412455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3015412455
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.997427413
Short name T676
Test name
Test status
Simulation time 707060921 ps
CPU time 19.42 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:26:10 PM PDT 24
Peak memory 217592 kb
Host smart-d8e3d0e1-008f-4d71-afb3-e8e6899d8da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997427413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.997427413
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3365505919
Short name T840
Test name
Test status
Simulation time 565550723 ps
CPU time 14.29 seconds
Started Jul 09 05:25:41 PM PDT 24
Finished Jul 09 05:25:56 PM PDT 24
Peak memory 225808 kb
Host smart-9e463cbd-e426-44c8-80c5-fb33df833143
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365505919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3365505919
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.4013264764
Short name T851
Test name
Test status
Simulation time 263668052 ps
CPU time 10.32 seconds
Started Jul 09 05:25:42 PM PDT 24
Finished Jul 09 05:25:53 PM PDT 24
Peak memory 225896 kb
Host smart-d1333224-df53-4568-a1af-fea997d280ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013264764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.4
013264764
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.943592096
Short name T767
Test name
Test status
Simulation time 428991058 ps
CPU time 10.29 seconds
Started Jul 09 05:25:38 PM PDT 24
Finished Jul 09 05:25:49 PM PDT 24
Peak memory 225344 kb
Host smart-5666604e-401f-45f1-9ff7-f6192591b16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943592096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.943592096
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3472338019
Short name T236
Test name
Test status
Simulation time 36139203 ps
CPU time 2.51 seconds
Started Jul 09 05:25:40 PM PDT 24
Finished Jul 09 05:25:43 PM PDT 24
Peak memory 217564 kb
Host smart-35a284f3-69df-485a-9238-8e929f52d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472338019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3472338019
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.749230121
Short name T577
Test name
Test status
Simulation time 320794933 ps
CPU time 24.24 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 250920 kb
Host smart-1c021eab-d69a-43e6-ae93-a120eb20d8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749230121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.749230121
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.511588862
Short name T466
Test name
Test status
Simulation time 258914702 ps
CPU time 3.14 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:25:52 PM PDT 24
Peak memory 222648 kb
Host smart-20331cbb-1ecd-499f-95df-a54d60e8eafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511588862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.511588862
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.958643928
Short name T526
Test name
Test status
Simulation time 10873595061 ps
CPU time 55.71 seconds
Started Jul 09 05:25:40 PM PDT 24
Finished Jul 09 05:26:36 PM PDT 24
Peak memory 250952 kb
Host smart-b925654d-d3ec-4ca3-aec8-961bfafbb20b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958643928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.958643928
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.4247028343
Short name T95
Test name
Test status
Simulation time 180241230277 ps
CPU time 338.24 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:31:26 PM PDT 24
Peak memory 283716 kb
Host smart-50f8d660-24d2-4c89-af8f-112af7fc9d96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4247028343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.4247028343
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4290612627
Short name T442
Test name
Test status
Simulation time 17843416 ps
CPU time 0.95 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:25:49 PM PDT 24
Peak memory 211748 kb
Host smart-4caae423-25e8-4931-9eea-f756b7458ec6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290612627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.4290612627
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1241386104
Short name T177
Test name
Test status
Simulation time 83173946 ps
CPU time 1.23 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:25:51 PM PDT 24
Peak memory 208904 kb
Host smart-d03f31e2-a565-4b59-913b-9d57f12365d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241386104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1241386104
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.333896647
Short name T147
Test name
Test status
Simulation time 32126382 ps
CPU time 0.9 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:25:59 PM PDT 24
Peak memory 209184 kb
Host smart-6b820509-dd3c-46d5-b8bd-6cdba5791830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333896647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.333896647
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3388656346
Short name T72
Test name
Test status
Simulation time 673877403 ps
CPU time 10.98 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 218068 kb
Host smart-af3e9cab-321b-4e6c-8f3e-bc45dd22c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388656346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3388656346
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3290737829
Short name T613
Test name
Test status
Simulation time 1697957924 ps
CPU time 4.91 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:25:55 PM PDT 24
Peak memory 216988 kb
Host smart-3772614c-73d9-4225-9b26-43cf2a1d4592
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290737829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3290737829
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.4251401043
Short name T365
Test name
Test status
Simulation time 2048314474 ps
CPU time 55.64 seconds
Started Jul 09 05:25:49 PM PDT 24
Finished Jul 09 05:26:47 PM PDT 24
Peak memory 218160 kb
Host smart-3b4ba428-15f4-4aea-976d-31ce2dbafd4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251401043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.4251401043
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2901996756
Short name T4
Test name
Test status
Simulation time 451663120 ps
CPU time 4.63 seconds
Started Jul 09 05:25:43 PM PDT 24
Finished Jul 09 05:25:48 PM PDT 24
Peak memory 217736 kb
Host smart-58c10199-5874-48dd-9f02-0f8b7a0aab37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901996756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
901996756
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.601978082
Short name T400
Test name
Test status
Simulation time 898143961 ps
CPU time 8.13 seconds
Started Jul 09 05:25:50 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 218160 kb
Host smart-75e570d8-d26c-44a6-af27-c341449d37f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601978082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.601978082
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1300253935
Short name T67
Test name
Test status
Simulation time 850433426 ps
CPU time 12.65 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:26:01 PM PDT 24
Peak memory 217580 kb
Host smart-87e1915e-3643-4229-be36-625cc3f0a580
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300253935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1300253935
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1672757644
Short name T308
Test name
Test status
Simulation time 227600557 ps
CPU time 7.46 seconds
Started Jul 09 05:25:49 PM PDT 24
Finished Jul 09 05:25:59 PM PDT 24
Peak memory 217516 kb
Host smart-16e4f792-2e6e-40b5-8c4c-e40d30832039
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672757644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1672757644
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4046984412
Short name T644
Test name
Test status
Simulation time 1618851027 ps
CPU time 42.4 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:26:27 PM PDT 24
Peak memory 269288 kb
Host smart-88eb2183-07e2-4fd4-97b6-76ff87d347db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046984412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4046984412
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1547811059
Short name T189
Test name
Test status
Simulation time 4159179683 ps
CPU time 9.37 seconds
Started Jul 09 05:25:57 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 226420 kb
Host smart-88ed1c06-4e99-45ef-a895-683ad212f296
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547811059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1547811059
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2311279198
Short name T222
Test name
Test status
Simulation time 109335603 ps
CPU time 3.28 seconds
Started Jul 09 05:25:42 PM PDT 24
Finished Jul 09 05:25:45 PM PDT 24
Peak memory 218044 kb
Host smart-6b266986-dc9f-4d66-a67f-60503f0b4205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311279198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2311279198
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3149682860
Short name T83
Test name
Test status
Simulation time 591411346 ps
CPU time 8.97 seconds
Started Jul 09 05:25:44 PM PDT 24
Finished Jul 09 05:25:53 PM PDT 24
Peak memory 217684 kb
Host smart-50058cec-2755-43dc-b554-93738d49a513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149682860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3149682860
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2090508659
Short name T561
Test name
Test status
Simulation time 280503002 ps
CPU time 10.02 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:25:55 PM PDT 24
Peak memory 219416 kb
Host smart-cad5f218-ce22-4f52-af56-f3ca8454f2fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090508659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2090508659
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1753815042
Short name T294
Test name
Test status
Simulation time 1911836033 ps
CPU time 11.42 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 225804 kb
Host smart-c6346c75-1e92-48ee-a491-b0edb84fd629
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753815042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1753815042
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.201016242
Short name T461
Test name
Test status
Simulation time 737885076 ps
CPU time 12.98 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 218072 kb
Host smart-b4cf3f67-ec23-4f31-a6b6-aa0cb036eabb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201016242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.201016242
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2105827118
Short name T729
Test name
Test status
Simulation time 1406356848 ps
CPU time 13.12 seconds
Started Jul 09 05:25:44 PM PDT 24
Finished Jul 09 05:25:57 PM PDT 24
Peak memory 225992 kb
Host smart-6efd7bec-4507-4afa-9455-85a1b99dee0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105827118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2105827118
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3019088531
Short name T553
Test name
Test status
Simulation time 652035610 ps
CPU time 5.62 seconds
Started Jul 09 05:25:43 PM PDT 24
Finished Jul 09 05:25:49 PM PDT 24
Peak memory 217636 kb
Host smart-3f667a29-1828-407f-a2f3-f770abc0c85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019088531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3019088531
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.939743780
Short name T683
Test name
Test status
Simulation time 154809099 ps
CPU time 19.14 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 250920 kb
Host smart-dd705098-ef97-4b0a-9f99-6b39cd9bf0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939743780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.939743780
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1301468993
Short name T779
Test name
Test status
Simulation time 157895187 ps
CPU time 7.56 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:25:56 PM PDT 24
Peak memory 250424 kb
Host smart-5ab443b0-c3fe-433d-a1f7-20fb8f853517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301468993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1301468993
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.852909586
Short name T89
Test name
Test status
Simulation time 4558530025 ps
CPU time 105.09 seconds
Started Jul 09 05:25:51 PM PDT 24
Finished Jul 09 05:27:37 PM PDT 24
Peak memory 283560 kb
Host smart-33f4eca3-ae9d-4bf7-96dc-0e627aa2e136
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852909586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.852909586
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2984847865
Short name T254
Test name
Test status
Simulation time 34524870 ps
CPU time 0.89 seconds
Started Jul 09 05:25:50 PM PDT 24
Finished Jul 09 05:25:52 PM PDT 24
Peak memory 211852 kb
Host smart-4675e7c1-4d2c-43e0-9794-f78d2ba34124
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984847865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2984847865
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.4013141011
Short name T688
Test name
Test status
Simulation time 69840645 ps
CPU time 0.94 seconds
Started Jul 09 05:25:59 PM PDT 24
Finished Jul 09 05:26:01 PM PDT 24
Peak memory 208780 kb
Host smart-b153744b-92fa-41b1-b127-460c6bde0768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013141011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.4013141011
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.720388351
Short name T220
Test name
Test status
Simulation time 34258020 ps
CPU time 0.91 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:25:50 PM PDT 24
Peak memory 209216 kb
Host smart-86d49281-c224-436d-a886-6c229f97f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720388351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.720388351
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2014160122
Short name T192
Test name
Test status
Simulation time 201256018 ps
CPU time 1.26 seconds
Started Jul 09 05:25:58 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 216968 kb
Host smart-afdd069f-b255-4161-a7bd-8b60eeb9c82a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014160122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2014160122
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4017383744
Short name T790
Test name
Test status
Simulation time 9951964638 ps
CPU time 34.41 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 218120 kb
Host smart-f7693929-729b-4684-b054-b74f6f1c423e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017383744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4017383744
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1976738109
Short name T178
Test name
Test status
Simulation time 696985650 ps
CPU time 4.82 seconds
Started Jul 09 05:25:52 PM PDT 24
Finished Jul 09 05:25:58 PM PDT 24
Peak memory 217596 kb
Host smart-dae2de3a-7819-465c-af0e-a1bf80ecd525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976738109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
976738109
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.632414639
Short name T155
Test name
Test status
Simulation time 522276545 ps
CPU time 5.83 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:25:55 PM PDT 24
Peak memory 218196 kb
Host smart-4f9e9389-364f-4e6f-ae7c-0078271ca39b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632414639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.632414639
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2681827624
Short name T785
Test name
Test status
Simulation time 2482388785 ps
CPU time 10.34 seconds
Started Jul 09 05:25:59 PM PDT 24
Finished Jul 09 05:26:11 PM PDT 24
Peak memory 217672 kb
Host smart-73efabb3-2cd0-41dc-bc26-e43a43d63277
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681827624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2681827624
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.113181004
Short name T649
Test name
Test status
Simulation time 240184599 ps
CPU time 4.35 seconds
Started Jul 09 05:25:51 PM PDT 24
Finished Jul 09 05:25:57 PM PDT 24
Peak memory 217616 kb
Host smart-0b616744-8529-485f-aa94-d54b9f4281d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113181004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.113181004
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1215725039
Short name T262
Test name
Test status
Simulation time 5770098919 ps
CPU time 67.87 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:57 PM PDT 24
Peak memory 271176 kb
Host smart-313f8526-f657-42f2-ac01-2fcabd597cb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215725039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1215725039
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.453294862
Short name T264
Test name
Test status
Simulation time 358259299 ps
CPU time 12.14 seconds
Started Jul 09 05:25:51 PM PDT 24
Finished Jul 09 05:26:05 PM PDT 24
Peak memory 218088 kb
Host smart-a04f64d0-e3fd-44ce-9c76-0a3da53910ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453294862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.453294862
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1757405361
Short name T270
Test name
Test status
Simulation time 108360930 ps
CPU time 2.46 seconds
Started Jul 09 05:25:50 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 218136 kb
Host smart-7405d011-b4d8-434c-9d80-1411b6ef5c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757405361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1757405361
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4076399613
Short name T727
Test name
Test status
Simulation time 3391050507 ps
CPU time 6.18 seconds
Started Jul 09 05:25:46 PM PDT 24
Finished Jul 09 05:25:58 PM PDT 24
Peak memory 214836 kb
Host smart-ba6e8b3f-ef28-4fc7-91d3-df5db3c440cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076399613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4076399613
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1432939183
Short name T547
Test name
Test status
Simulation time 403179829 ps
CPU time 11.53 seconds
Started Jul 09 05:25:50 PM PDT 24
Finished Jul 09 05:26:03 PM PDT 24
Peak memory 218792 kb
Host smart-e80ee3b6-7c97-4c28-aada-c7d5f06ce0bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432939183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1432939183
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2984919501
Short name T227
Test name
Test status
Simulation time 1918682292 ps
CPU time 11.5 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:25:58 PM PDT 24
Peak memory 226056 kb
Host smart-99ab7af4-bd5e-489f-9982-c6bf9104f9f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984919501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2984919501
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2746097550
Short name T835
Test name
Test status
Simulation time 269810496 ps
CPU time 7.6 seconds
Started Jul 09 05:25:45 PM PDT 24
Finished Jul 09 05:25:54 PM PDT 24
Peak memory 225984 kb
Host smart-a9eca0e7-277a-4edb-a677-43a32cb6fac1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746097550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
746097550
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2172834395
Short name T854
Test name
Test status
Simulation time 813727414 ps
CPU time 9.61 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:26:07 PM PDT 24
Peak memory 225324 kb
Host smart-d3062880-aab5-4f01-b445-e329bf9c5474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172834395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2172834395
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3369380185
Short name T79
Test name
Test status
Simulation time 76608522 ps
CPU time 0.96 seconds
Started Jul 09 05:25:51 PM PDT 24
Finished Jul 09 05:25:53 PM PDT 24
Peak memory 217644 kb
Host smart-966bc313-da85-4860-aa19-fdcd9dda9779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369380185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3369380185
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1283953638
Short name T723
Test name
Test status
Simulation time 267281795 ps
CPU time 24.21 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:26:22 PM PDT 24
Peak memory 245352 kb
Host smart-40c7b02a-f359-4d30-ba71-f18b059fd3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283953638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1283953638
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2343443244
Short name T282
Test name
Test status
Simulation time 138404834 ps
CPU time 8.56 seconds
Started Jul 09 05:25:53 PM PDT 24
Finished Jul 09 05:26:03 PM PDT 24
Peak memory 250808 kb
Host smart-0a7427b4-4ee5-4720-b291-0197f5fbcf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343443244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2343443244
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2354043006
Short name T290
Test name
Test status
Simulation time 4810311357 ps
CPU time 102.34 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:27:40 PM PDT 24
Peak memory 292032 kb
Host smart-32ff27c8-d950-4c65-ae3c-d2625d767f1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354043006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2354043006
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1963950719
Short name T328
Test name
Test status
Simulation time 41782285 ps
CPU time 1 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:25:57 PM PDT 24
Peak memory 211808 kb
Host smart-35d67bc8-682a-4947-8fcc-e1b522823457
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963950719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1963950719
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.683084386
Short name T299
Test name
Test status
Simulation time 16565672 ps
CPU time 0.93 seconds
Started Jul 09 05:25:59 PM PDT 24
Finished Jul 09 05:26:01 PM PDT 24
Peak memory 208884 kb
Host smart-9f5d1e5d-3bdb-4371-8f07-2a7af752958f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683084386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.683084386
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1641019643
Short name T102
Test name
Test status
Simulation time 535773687 ps
CPU time 14.13 seconds
Started Jul 09 05:25:57 PM PDT 24
Finished Jul 09 05:26:12 PM PDT 24
Peak memory 218192 kb
Host smart-1a1bfd97-7cd4-4704-bd88-4eb5d3eb314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641019643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1641019643
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.4071035905
Short name T36
Test name
Test status
Simulation time 3155707447 ps
CPU time 45.35 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:26:43 PM PDT 24
Peak memory 218796 kb
Host smart-b7e4234b-142f-43fc-af41-4bdf1631f6ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071035905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.4071035905
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1839094824
Short name T652
Test name
Test status
Simulation time 1136823751 ps
CPU time 4.92 seconds
Started Jul 09 05:25:53 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 217628 kb
Host smart-aa706c6f-1bbe-4871-887b-9dd8a2169ba9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839094824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
839094824
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.218275971
Short name T274
Test name
Test status
Simulation time 254018199 ps
CPU time 5.53 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 218180 kb
Host smart-87be0f13-dec8-4b3d-8aab-71d29e51d45c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218275971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.218275971
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.35499358
Short name T283
Test name
Test status
Simulation time 1075937342 ps
CPU time 17.27 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:26:15 PM PDT 24
Peak memory 217660 kb
Host smart-66bdbdba-784b-4341-b5df-254a7316027a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35499358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt
ag_regwen_during_op.35499358
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3483147876
Short name T469
Test name
Test status
Simulation time 167180649 ps
CPU time 4 seconds
Started Jul 09 05:25:58 PM PDT 24
Finished Jul 09 05:26:03 PM PDT 24
Peak memory 217636 kb
Host smart-2bb7d101-7cec-4d6f-8346-58d280458d7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483147876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3483147876
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3997644550
Short name T804
Test name
Test status
Simulation time 4381403872 ps
CPU time 59.87 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:26:49 PM PDT 24
Peak memory 267344 kb
Host smart-eb3e2c2d-17a2-42e4-8935-f699f1abb808
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997644550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3997644550
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1105603633
Short name T665
Test name
Test status
Simulation time 323542681 ps
CPU time 9.94 seconds
Started Jul 09 05:25:57 PM PDT 24
Finished Jul 09 05:26:09 PM PDT 24
Peak memory 250372 kb
Host smart-227fb857-17b9-48b7-a1ce-110c608f4dd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105603633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1105603633
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1287131859
Short name T632
Test name
Test status
Simulation time 346297408 ps
CPU time 3.19 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 222572 kb
Host smart-2474abb5-51f9-4c45-bb3d-6c9d2e5c1b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287131859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1287131859
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2522487197
Short name T436
Test name
Test status
Simulation time 2755184460 ps
CPU time 23.36 seconds
Started Jul 09 05:25:54 PM PDT 24
Finished Jul 09 05:26:19 PM PDT 24
Peak memory 215172 kb
Host smart-fceaf0b3-c80f-4593-ab6e-02cc913912a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522487197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2522487197
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1719752926
Short name T40
Test name
Test status
Simulation time 646343749 ps
CPU time 19.23 seconds
Started Jul 09 05:25:51 PM PDT 24
Finished Jul 09 05:26:12 PM PDT 24
Peak memory 225900 kb
Host smart-7ff14dfd-8816-4396-aefa-8077871e5d4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719752926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1719752926
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3954503738
Short name T58
Test name
Test status
Simulation time 1140071411 ps
CPU time 10.01 seconds
Started Jul 09 05:25:54 PM PDT 24
Finished Jul 09 05:26:06 PM PDT 24
Peak memory 225960 kb
Host smart-9ce69d7f-8b82-4c80-8a1f-2210cd4aef2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954503738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3954503738
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4171001067
Short name T287
Test name
Test status
Simulation time 1974408628 ps
CPU time 9.77 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:26:07 PM PDT 24
Peak memory 218140 kb
Host smart-c2fbce0e-7411-404f-973b-81179f52f7be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171001067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.4
171001067
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1257800151
Short name T391
Test name
Test status
Simulation time 727713500 ps
CPU time 9.09 seconds
Started Jul 09 05:25:49 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 225980 kb
Host smart-89c6f97f-3d40-4087-9b52-621487d0c958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257800151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1257800151
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.855309283
Short name T65
Test name
Test status
Simulation time 83713160 ps
CPU time 1.22 seconds
Started Jul 09 05:25:52 PM PDT 24
Finished Jul 09 05:25:55 PM PDT 24
Peak memory 213544 kb
Host smart-9cf1e56c-286f-4a6f-9eac-029108d4fd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855309283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.855309283
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3964128522
Short name T244
Test name
Test status
Simulation time 900497417 ps
CPU time 30.37 seconds
Started Jul 09 05:25:51 PM PDT 24
Finished Jul 09 05:26:23 PM PDT 24
Peak memory 250756 kb
Host smart-e9928b61-6be6-47fd-a417-3438b2cd3c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964128522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3964128522
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.4276277978
Short name T748
Test name
Test status
Simulation time 404221281 ps
CPU time 7.9 seconds
Started Jul 09 05:25:48 PM PDT 24
Finished Jul 09 05:25:58 PM PDT 24
Peak memory 250912 kb
Host smart-511255a7-c9cd-4350-8d02-66dfb0222eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276277978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4276277978
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3561413537
Short name T61
Test name
Test status
Simulation time 19747160887 ps
CPU time 230.07 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:29:48 PM PDT 24
Peak memory 251000 kb
Host smart-3129c236-0ba7-4976-b03b-424f6066b278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561413537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3561413537
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.4238534008
Short name T182
Test name
Test status
Simulation time 48909388 ps
CPU time 0.86 seconds
Started Jul 09 05:25:47 PM PDT 24
Finished Jul 09 05:25:50 PM PDT 24
Peak memory 211800 kb
Host smart-0bdda723-7063-425b-a0fb-0ac7cf362f1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238534008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.4238534008
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3454462577
Short name T864
Test name
Test status
Simulation time 87368036 ps
CPU time 1.28 seconds
Started Jul 09 05:25:53 PM PDT 24
Finished Jul 09 05:25:56 PM PDT 24
Peak memory 208924 kb
Host smart-32720547-73c2-4169-895a-5f3d062a4fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454462577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3454462577
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2370236024
Short name T218
Test name
Test status
Simulation time 11966504 ps
CPU time 1 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:26:03 PM PDT 24
Peak memory 208956 kb
Host smart-fa38d457-4122-4742-a66e-b9db7430eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370236024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2370236024
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1522672549
Short name T707
Test name
Test status
Simulation time 1097905105 ps
CPU time 14.95 seconds
Started Jul 09 05:25:54 PM PDT 24
Finished Jul 09 05:26:10 PM PDT 24
Peak memory 218096 kb
Host smart-8d535378-0c4f-40b3-9ac1-8d1f9425b5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522672549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1522672549
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3136211857
Short name T764
Test name
Test status
Simulation time 332296068 ps
CPU time 2.52 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:26:00 PM PDT 24
Peak memory 216828 kb
Host smart-23fc1e5e-6c3e-468b-9af4-c8ebd5e0d53f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136211857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3136211857
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.833771003
Short name T749
Test name
Test status
Simulation time 1031233593 ps
CPU time 18.2 seconds
Started Jul 09 05:26:00 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 218208 kb
Host smart-d7395583-a104-4981-926e-a7a21d35eca6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833771003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.833771003
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2151993394
Short name T394
Test name
Test status
Simulation time 179900066 ps
CPU time 4.95 seconds
Started Jul 09 05:25:59 PM PDT 24
Finished Jul 09 05:26:05 PM PDT 24
Peak memory 217712 kb
Host smart-c3e4dea0-cbe3-4cf1-9e72-a3e9af40501e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151993394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
151993394
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1804831708
Short name T669
Test name
Test status
Simulation time 237087604 ps
CPU time 4.71 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:26:01 PM PDT 24
Peak memory 218440 kb
Host smart-24fa4535-cffe-4037-8ae9-5ac6f92def04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804831708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1804831708
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1913003863
Short name T159
Test name
Test status
Simulation time 1311452707 ps
CPU time 34.81 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:26:37 PM PDT 24
Peak memory 217648 kb
Host smart-64a0ee97-e6d1-49af-9071-07090edc3203
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913003863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1913003863
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.548194423
Short name T384
Test name
Test status
Simulation time 315890923 ps
CPU time 5.14 seconds
Started Jul 09 05:25:59 PM PDT 24
Finished Jul 09 05:26:05 PM PDT 24
Peak memory 217520 kb
Host smart-a74353a3-5915-4593-b8e4-855da9d7994c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548194423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.548194423
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.588843181
Short name T401
Test name
Test status
Simulation time 1465539076 ps
CPU time 46.71 seconds
Started Jul 09 05:25:56 PM PDT 24
Finished Jul 09 05:26:45 PM PDT 24
Peak memory 267288 kb
Host smart-d881bd7c-3ae0-4d6b-b9db-4c549ad629cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588843181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.588843181
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1357938566
Short name T629
Test name
Test status
Simulation time 531861184 ps
CPU time 19.98 seconds
Started Jul 09 05:26:00 PM PDT 24
Finished Jul 09 05:26:21 PM PDT 24
Peak memory 250500 kb
Host smart-7df85abb-e34e-40e8-abd3-a04b87b9140a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357938566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1357938566
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.326349180
Short name T586
Test name
Test status
Simulation time 76226081 ps
CPU time 3.2 seconds
Started Jul 09 05:25:59 PM PDT 24
Finished Jul 09 05:26:04 PM PDT 24
Peak memory 222456 kb
Host smart-ceb014f5-8954-442e-8b5c-79feaf96bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326349180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.326349180
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3412457155
Short name T846
Test name
Test status
Simulation time 592770583 ps
CPU time 18.19 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 214692 kb
Host smart-7792bd41-4716-474c-968f-8ee6f76b2273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412457155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3412457155
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2078521179
Short name T853
Test name
Test status
Simulation time 297581535 ps
CPU time 12.42 seconds
Started Jul 09 05:26:07 PM PDT 24
Finished Jul 09 05:26:20 PM PDT 24
Peak memory 226000 kb
Host smart-d4095c16-3625-47c7-b904-4b44dc37daf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078521179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2078521179
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1895603385
Short name T341
Test name
Test status
Simulation time 437527911 ps
CPU time 9.4 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:26:06 PM PDT 24
Peak memory 218200 kb
Host smart-5ba86ed0-e988-4ea7-955e-c151597a51f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895603385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
895603385
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4089044677
Short name T471
Test name
Test status
Simulation time 693530916 ps
CPU time 6.65 seconds
Started Jul 09 05:26:01 PM PDT 24
Finished Jul 09 05:26:08 PM PDT 24
Peak memory 224632 kb
Host smart-06f94eea-96f7-49c2-920d-b2f1090d08f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089044677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4089044677
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3643157846
Short name T378
Test name
Test status
Simulation time 60070917 ps
CPU time 1.31 seconds
Started Jul 09 05:25:53 PM PDT 24
Finished Jul 09 05:25:56 PM PDT 24
Peak memory 217580 kb
Host smart-dc1dda4b-19d2-4d35-902c-0e2f46b80136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643157846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3643157846
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.661532740
Short name T573
Test name
Test status
Simulation time 660562076 ps
CPU time 29.81 seconds
Started Jul 09 05:26:00 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 250936 kb
Host smart-21b62ff3-059b-46c4-8b16-b543309c456b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661532740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.661532740
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4205392125
Short name T252
Test name
Test status
Simulation time 755025093 ps
CPU time 25.83 seconds
Started Jul 09 05:26:04 PM PDT 24
Finished Jul 09 05:26:31 PM PDT 24
Peak memory 250936 kb
Host smart-a788ad55-7e3b-4f86-bebe-f3968f699632
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205392125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4205392125
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2703316388
Short name T830
Test name
Test status
Simulation time 52739490 ps
CPU time 0.89 seconds
Started Jul 09 05:25:55 PM PDT 24
Finished Jul 09 05:25:58 PM PDT 24
Peak memory 211892 kb
Host smart-4781c806-adcf-4ea8-ad33-556da4936c9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703316388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2703316388
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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