Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79813630

1

T1

41204

T2

49773

T3

22837

auto[1]

1258272

1

T1

12107

T2

1188

T3

2871

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79792375

1

T1

39992

T2

49971

T3

21154

auto[1]

1279527

1

T1

13319

T2

990

T3

4554

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6310575	1			T1	9172		T2	6061		T3	9569
auto[IdleSt]	19709776	1			T1	7378		T2	5576		T3	1137
auto[ClkMuxSt]	31582	1			T1	73		T2	56		T8	83
auto[CntIncrSt]	31342	1			T1	72		T2	56		T8	83
auto[CntProgSt]	1379444	1			T1	16404		T2	14748		T8	2433
auto[TransCheckSt]	24643	1			T1	43		T2	44		T8	43
auto[TokenHashSt]	26716612	1			T1	634		T2	3948		T8	976
auto[FlashRmaSt]	30666	1			T1	30		T2	108		T8	123
auto[TokenCheck0St]	10838	1			T1	29		T2	40		T8	31
auto[TokenCheck1St]	7899	1			T1	29		T2	28		T8	30
auto[TransProgSt]	353926	1			T1	715		T2	7345		T8	193
auto[PostTransSt]	11007280	1			T1	6		T2	8556		T8	6
auto[ScrapSt]	145001	1			T1	12		T8	3		T11	3
auto[EscalateSt]	5728518	1			T1	18714		T2	2904		T3	9515
auto[InvalidSt]	9582127	1			T2	1491		T3	5476		T21	8992

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1673	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9582127	1			T2	1491		T3	5476		T21	8992
EscalateSt	5728518	1			T1	18714		T2	2904		T3	9515
ScrapSt	145001	1			T1	12		T8	3		T11	3
PostTransSt	11007280	1			T1	6		T2	8556		T8	6
TransProgSt	353926	1			T1	715		T2	7345		T8	193
TokenCheck1St	7899	1			T1	29		T2	28		T8	30
TokenCheck0St	10838	1			T1	29		T2	40		T8	31
FlashRmaSt	30666	1			T1	30		T2	108		T8	123
TokenHashSt	26716612	1			T1	634		T2	3948		T8	976
TransCheckSt	24643	1			T1	43		T2	44		T8	43
CntProgSt	1379444	1			T1	16404		T2	14748		T8	2433
CntIncrSt	31342	1			T1	72		T2	56		T8	83
ClkMuxSt	31582	1			T1	73		T2	56		T8	83
IdleSt	19709776	1			T1	7378		T2	5576		T3	1137
ResetSt	6310575	1			T1	9172		T2	6061		T3	9569
arcs[ResetSt=>IdleSt]	47347	1			T1	91		T2	67		T3	90
arcs[IdleSt=>ScrapSt]	271	1			T1	4		T8	1		T11	1
arcs[IdleSt=>ClkMuxSt]	31391	1			T1	73		T2	56		T8	83
arcs[ClkMuxSt=>CntIncrSt]	31342	1			T1	72		T2	56		T8	83
arcs[CntIncrSt=>PostTransSt]	1526	1			T13	4		T15	19		T5	10
arcs[CntIncrSt=>CntProgSt]	29756	1			T1	69		T2	56		T8	83
arcs[CntProgSt=>PostTransSt]	4113	1			T2	12		T10	12		T13	8
arcs[CntProgSt=>TransCheckSt]	24643	1			T1	43		T2	44		T8	43
arcs[TransCheckSt=>PostTransSt]	3522	1			T13	10		T15	10		T16	28
arcs[TransCheckSt=>TokenHashSt]	20989	1			T1	43		T2	44		T8	43
arcs[TokenHashSt=>PostTransSt]	9305	1			T2	4		T12	65		T13	22
arcs[TokenHashSt=>FlashRmaSt]	10948	1			T1	30		T2	40		T8	33
arcs[FlashRmaSt=>TokenCheck0St]	10838	1			T1	29		T2	40		T8	31
arcs[TokenCheck0St=>PostTransSt]	2904	1			T2	12		T13	6		T15	12
arcs[TokenCheck0St=>TokenCheck1St]	7899	1			T1	29		T2	28		T8	30
arcs[TokenCheck1St=>PostTransSt]	610	1			T2	1		T13	1		T15	3
arcs[TransProgSt=>PostTransSt]	6455	1			T1	2		T2	27		T8	2
arcs[IdleSt=>EscalateSt]	223	1			T1	13		T29	13		T51	6
arcs[ClkMuxSt=>EscalateSt]	49	1			T1	1		T29	1		T50	1
arcs[CntIncrSt=>EscalateSt]	60	1			T1	3		T11	2		T29	1
arcs[CntProgSt=>EscalateSt]	1000	1			T1	26		T8	40		T11	16
arcs[TransCheckSt=>EscalateSt]	132	1			T11	7		T29	2		T50	7
arcs[TokenHashSt=>EscalateSt]	736	1			T1	13		T8	10		T11	32
arcs[FlashRmaSt=>EscalateSt]	110	1			T1	1		T8	2		T29	2
arcs[TokenCheck0St=>EscalateSt]	35	1			T8	1		T11	2		T29	1
arcs[TokenCheck1St=>EscalateSt]	126	1			T1	5		T8	3		T11	4
arcs[TransProgSt=>EscalateSt]	708	1			T1	22		T8	25		T11	14
arcs[PostTransSt=>EscalateSt]	4380	1			T1	2		T2	12		T8	2
arcs[InvalidSt=>EscalateSt]	11766	1			T2	10		T3	75		T21	49

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6310391	1			T1	9167		T2	6061		T3	9569
auto[0]	auto[IdleSt]	19709620	1			T1	7373		T2	5576		T3	1137
auto[0]	auto[ClkMuxSt]	31550	1			T1	72		T2	56		T8	83
auto[0]	auto[CntIncrSt]	31310	1			T1	70		T2	56		T8	83
auto[0]	auto[CntProgSt]	1378769	1			T1	16389		T2	14748		T8	2404
auto[0]	auto[TransCheckSt]	24545	1			T1	43		T2	44		T8	43
auto[0]	auto[TokenHashSt]	26716117	1			T1	626		T2	3948		T8	969
auto[0]	auto[FlashRmaSt]	30586	1			T1	30		T2	108		T8	121
auto[0]	auto[TokenCheck0St]	10814	1			T1	29		T2	40		T8	30
auto[0]	auto[TokenCheck1St]	7804	1			T1	25		T2	28		T8	29
auto[0]	auto[TransProgSt]	353449	1			T1	695		T2	7345		T8	174
auto[0]	auto[PostTransSt]	11005093	1			T1	4		T2	8551		T8	4
auto[0]	auto[ScrapSt]	144962	1			T1	11		T8	2		T11	2
auto[0]	auto[EscalateSt]	4480596	1			T1	6670		T2	1728		T3	6673
auto[0]	auto[InvalidSt]	9576351	1			T2	1484		T3	5447		T21	8969
auto[1]	auto[ResetSt]	184	1			T1	5		T8	7		T11	3
auto[1]	auto[IdleSt]	156	1			T1	5		T29	8		T51	5
auto[1]	auto[ClkMuxSt]	32	1			T1	1		T50	1		T51	1
auto[1]	auto[CntIncrSt]	32	1			T1	2		T11	2		T50	1
auto[1]	auto[CntProgSt]	675	1			T1	15		T8	29		T11	12
auto[1]	auto[TransCheckSt]	98	1			T11	3		T50	5		T82	5
auto[1]	auto[TokenHashSt]	495	1			T1	8		T8	7		T11	20
auto[1]	auto[FlashRmaSt]	80	1			T8	2		T29	1		T50	3
auto[1]	auto[TokenCheck0St]	24	1			T8	1		T11	1		T29	1
auto[1]	auto[TokenCheck1St]	95	1			T1	4		T8	1		T11	4
auto[1]	auto[TransProgSt]	477	1			T1	20		T8	19		T11	9
auto[1]	auto[PostTransSt]	2187	1			T1	2		T2	5		T8	2
auto[1]	auto[ScrapSt]	39	1			T1	1		T8	1		T11	1
auto[1]	auto[EscalateSt]	1247922	1			T1	12044		T2	1176		T3	2842
auto[1]	auto[InvalidSt]	5776	1			T2	7		T3	29		T21	23

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6310374	1			T1	9164		T2	6061		T3	9569
auto[0]	auto[IdleSt]	19709616	1			T1	7368		T2	5576		T3	1137
auto[0]	auto[ClkMuxSt]	31551	1			T1	73		T2	56		T8	83
auto[0]	auto[CntIncrSt]	31299	1			T1	69		T2	56		T8	83
auto[0]	auto[CntProgSt]	1378803	1			T1	16384		T2	14748		T8	2409
auto[0]	auto[TransCheckSt]	24554	1			T1	43		T2	44		T8	43
auto[0]	auto[TokenHashSt]	26716114	1			T1	625		T2	3948		T8	969
auto[0]	auto[FlashRmaSt]	30597	1			T1	29		T2	108		T8	121
auto[0]	auto[TokenCheck0St]	10814	1			T1	29		T2	40		T8	31
auto[0]	auto[TokenCheck1St]	7824	1			T1	26		T2	28		T8	27
auto[0]	auto[TransProgSt]	353472	1			T1	704		T2	7345		T8	174
auto[0]	auto[PostTransSt]	11005003	1			T1	5		T2	8549		T8	5
auto[0]	auto[ScrapSt]	144963	1			T1	8		T8	3		T11	2
auto[0]	auto[EscalateSt]	4459581	1			T1	5465		T2	1924		T3	5007
auto[0]	auto[InvalidSt]	9576137	1			T2	1488		T3	5430		T21	8966
auto[1]	auto[ResetSt]	201	1			T1	8		T8	5		T11	4
auto[1]	auto[IdleSt]	160	1			T1	10		T29	10		T51	6
auto[1]	auto[ClkMuxSt]	31	1			T29	1		T203	2		T204	1
auto[1]	auto[CntIncrSt]	43	1			T1	3		T11	1		T29	1
auto[1]	auto[CntProgSt]	641	1			T1	20		T8	24		T11	11
auto[1]	auto[TransCheckSt]	89	1			T11	5		T29	2		T50	5
auto[1]	auto[TokenHashSt]	498	1			T1	9		T8	7		T11	24
auto[1]	auto[FlashRmaSt]	69	1			T1	1		T8	2		T29	2
auto[1]	auto[TokenCheck0St]	24	1			T11	2		T89	1		T204	2
auto[1]	auto[TokenCheck1St]	75	1			T1	3		T8	3		T11	2
auto[1]	auto[TransProgSt]	454	1			T1	11		T8	19		T11	8
auto[1]	auto[PostTransSt]	2277	1			T1	1		T2	7		T8	1
auto[1]	auto[ScrapSt]	38	1			T1	4		T11	1		T82	3
auto[1]	auto[EscalateSt]	1268937	1			T1	13249		T2	980		T3	4508
auto[1]	auto[InvalidSt]	5990	1			T2	3		T3	46		T21	26