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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 97.92 95.84 93.38 100.00 98.52 99.00 95.94


Total test records in report: 988
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T815 /workspace/coverage/default/49.lc_ctrl_errors.1519468665 Jul 10 07:02:38 PM PDT 24 Jul 10 07:02:50 PM PDT 24 332743440 ps
T816 /workspace/coverage/default/35.lc_ctrl_jtag_access.2208121752 Jul 10 07:01:18 PM PDT 24 Jul 10 07:01:22 PM PDT 24 574444255 ps
T817 /workspace/coverage/default/8.lc_ctrl_smoke.2040314025 Jul 10 06:57:40 PM PDT 24 Jul 10 06:57:45 PM PDT 24 196130825 ps
T818 /workspace/coverage/default/17.lc_ctrl_jtag_access.1502181747 Jul 10 06:59:16 PM PDT 24 Jul 10 06:59:36 PM PDT 24 3076819201 ps
T819 /workspace/coverage/default/12.lc_ctrl_sec_mubi.3252095795 Jul 10 06:58:35 PM PDT 24 Jul 10 06:58:46 PM PDT 24 470522663 ps
T820 /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2703341916 Jul 10 07:01:08 PM PDT 24 Jul 10 07:04:27 PM PDT 24 41558877932 ps
T821 /workspace/coverage/default/19.lc_ctrl_prog_failure.2459818835 Jul 10 06:59:33 PM PDT 24 Jul 10 06:59:36 PM PDT 24 151934090 ps
T822 /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2635959770 Jul 10 07:01:03 PM PDT 24 Jul 10 07:01:04 PM PDT 24 29887384 ps
T823 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3343205338 Jul 10 06:58:02 PM PDT 24 Jul 10 06:58:24 PM PDT 24 1037324680 ps
T824 /workspace/coverage/default/29.lc_ctrl_errors.570755397 Jul 10 07:00:41 PM PDT 24 Jul 10 07:00:52 PM PDT 24 1326687254 ps
T825 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3411308795 Jul 10 07:00:22 PM PDT 24 Jul 10 07:00:35 PM PDT 24 932958728 ps
T826 /workspace/coverage/default/17.lc_ctrl_state_failure.2697789919 Jul 10 06:59:09 PM PDT 24 Jul 10 06:59:38 PM PDT 24 824044903 ps
T827 /workspace/coverage/default/6.lc_ctrl_stress_all.2300934507 Jul 10 06:57:25 PM PDT 24 Jul 10 06:58:06 PM PDT 24 3003123232 ps
T828 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1640152202 Jul 10 06:56:53 PM PDT 24 Jul 10 06:56:55 PM PDT 24 15115392 ps
T829 /workspace/coverage/default/42.lc_ctrl_smoke.2479004258 Jul 10 07:02:00 PM PDT 24 Jul 10 07:02:03 PM PDT 24 35390643 ps
T830 /workspace/coverage/default/26.lc_ctrl_jtag_access.1949890423 Jul 10 07:00:27 PM PDT 24 Jul 10 07:00:43 PM PDT 24 662295992 ps
T831 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.119257464 Jul 10 06:56:10 PM PDT 24 Jul 10 06:56:52 PM PDT 24 3657389430 ps
T832 /workspace/coverage/default/14.lc_ctrl_jtag_access.318163041 Jul 10 06:58:50 PM PDT 24 Jul 10 06:58:54 PM PDT 24 4558673402 ps
T833 /workspace/coverage/default/29.lc_ctrl_smoke.2460157074 Jul 10 07:00:32 PM PDT 24 Jul 10 07:00:35 PM PDT 24 67976124 ps
T834 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2844982624 Jul 10 07:00:30 PM PDT 24 Jul 10 07:00:44 PM PDT 24 800193698 ps
T835 /workspace/coverage/default/24.lc_ctrl_prog_failure.3210053921 Jul 10 07:00:10 PM PDT 24 Jul 10 07:00:15 PM PDT 24 256365661 ps
T836 /workspace/coverage/default/49.lc_ctrl_prog_failure.170769253 Jul 10 07:02:38 PM PDT 24 Jul 10 07:02:44 PM PDT 24 89828655 ps
T837 /workspace/coverage/default/37.lc_ctrl_prog_failure.1320135576 Jul 10 07:01:22 PM PDT 24 Jul 10 07:01:28 PM PDT 24 134863646 ps
T838 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1138385407 Jul 10 06:59:28 PM PDT 24 Jul 10 07:00:10 PM PDT 24 5540017763 ps
T839 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1742173473 Jul 10 06:55:40 PM PDT 24 Jul 10 06:55:42 PM PDT 24 13932707 ps
T840 /workspace/coverage/default/16.lc_ctrl_stress_all.1677427715 Jul 10 06:59:09 PM PDT 24 Jul 10 06:59:17 PM PDT 24 183540511 ps
T841 /workspace/coverage/default/16.lc_ctrl_jtag_errors.3236055218 Jul 10 06:59:10 PM PDT 24 Jul 10 07:00:04 PM PDT 24 3207302753 ps
T842 /workspace/coverage/default/35.lc_ctrl_errors.3178125413 Jul 10 07:01:17 PM PDT 24 Jul 10 07:01:27 PM PDT 24 893519385 ps
T843 /workspace/coverage/default/47.lc_ctrl_sec_mubi.789726194 Jul 10 07:02:24 PM PDT 24 Jul 10 07:02:40 PM PDT 24 358282319 ps
T844 /workspace/coverage/default/23.lc_ctrl_stress_all.3692912327 Jul 10 07:00:11 PM PDT 24 Jul 10 07:05:59 PM PDT 24 59260142165 ps
T845 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1790579265 Jul 10 07:00:52 PM PDT 24 Jul 10 07:01:15 PM PDT 24 11279825421 ps
T846 /workspace/coverage/default/7.lc_ctrl_security_escalation.2971634297 Jul 10 06:57:33 PM PDT 24 Jul 10 06:57:48 PM PDT 24 1573603003 ps
T847 /workspace/coverage/default/26.lc_ctrl_security_escalation.2500220886 Jul 10 07:00:22 PM PDT 24 Jul 10 07:00:34 PM PDT 24 809310839 ps
T151 /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4179755825 Jul 10 06:56:00 PM PDT 24 Jul 10 06:59:58 PM PDT 24 15191243664 ps
T848 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1691473856 Jul 10 06:56:30 PM PDT 24 Jul 10 06:56:38 PM PDT 24 1662386828 ps
T849 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1327208314 Jul 10 06:57:02 PM PDT 24 Jul 10 06:58:51 PM PDT 24 28473385712 ps
T850 /workspace/coverage/default/19.lc_ctrl_errors.3820511469 Jul 10 06:59:33 PM PDT 24 Jul 10 06:59:42 PM PDT 24 827947257 ps
T851 /workspace/coverage/default/0.lc_ctrl_state_post_trans.2633536557 Jul 10 06:55:12 PM PDT 24 Jul 10 06:55:20 PM PDT 24 751477913 ps
T852 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1120336729 Jul 10 07:00:33 PM PDT 24 Jul 10 07:00:44 PM PDT 24 387734897 ps
T853 /workspace/coverage/default/34.lc_ctrl_jtag_access.2161031597 Jul 10 07:01:07 PM PDT 24 Jul 10 07:01:15 PM PDT 24 1685989936 ps
T854 /workspace/coverage/default/14.lc_ctrl_errors.1294846079 Jul 10 06:58:51 PM PDT 24 Jul 10 06:59:06 PM PDT 24 1329821824 ps
T855 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1908386909 Jul 10 07:01:44 PM PDT 24 Jul 10 07:01:46 PM PDT 24 73081519 ps
T856 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.135936780 Jul 10 06:59:48 PM PDT 24 Jul 10 07:00:01 PM PDT 24 1456879648 ps
T857 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.713442020 Jul 10 06:57:00 PM PDT 24 Jul 10 06:57:10 PM PDT 24 814394312 ps
T858 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.779561287 Jul 10 07:01:30 PM PDT 24 Jul 10 07:01:45 PM PDT 24 312115102 ps
T859 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3023931479 Jul 10 06:59:42 PM PDT 24 Jul 10 06:59:55 PM PDT 24 1473746922 ps
T860 /workspace/coverage/default/20.lc_ctrl_alert_test.1404818763 Jul 10 06:59:52 PM PDT 24 Jul 10 06:59:53 PM PDT 24 43413495 ps
T861 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3146046392 Jul 10 07:01:56 PM PDT 24 Jul 10 07:02:14 PM PDT 24 1620009476 ps
T101 /workspace/coverage/default/4.lc_ctrl_sec_cm.3598256773 Jul 10 06:56:55 PM PDT 24 Jul 10 06:57:19 PM PDT 24 234314588 ps
T862 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.595818243 Jul 10 07:02:09 PM PDT 24 Jul 10 07:02:17 PM PDT 24 342421775 ps
T863 /workspace/coverage/default/9.lc_ctrl_jtag_errors.3860607135 Jul 10 06:58:03 PM PDT 24 Jul 10 06:59:29 PM PDT 24 2918849847 ps
T864 /workspace/coverage/default/17.lc_ctrl_sec_mubi.3262798836 Jul 10 06:59:17 PM PDT 24 Jul 10 06:59:36 PM PDT 24 1745291351 ps
T865 /workspace/coverage/default/41.lc_ctrl_errors.1444431534 Jul 10 07:01:54 PM PDT 24 Jul 10 07:02:07 PM PDT 24 805813957 ps
T121 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2407365064 Jul 10 05:52:41 PM PDT 24 Jul 10 05:52:44 PM PDT 24 14845314 ps
T111 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1804980876 Jul 10 05:52:41 PM PDT 24 Jul 10 05:52:47 PM PDT 24 550620699 ps
T115 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3246882508 Jul 10 05:52:35 PM PDT 24 Jul 10 05:52:39 PM PDT 24 1515076435 ps
T120 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3263113598 Jul 10 05:52:15 PM PDT 24 Jul 10 05:52:21 PM PDT 24 54762734 ps
T179 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.452175322 Jul 10 05:52:48 PM PDT 24 Jul 10 05:52:50 PM PDT 24 51460605 ps
T122 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3075191167 Jul 10 05:52:51 PM PDT 24 Jul 10 05:52:54 PM PDT 24 95830897 ps
T145 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2746776111 Jul 10 05:52:28 PM PDT 24 Jul 10 05:52:30 PM PDT 24 148825449 ps
T159 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2152470974 Jul 10 05:52:59 PM PDT 24 Jul 10 05:53:04 PM PDT 24 46793995 ps
T147 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3296050494 Jul 10 05:52:33 PM PDT 24 Jul 10 05:52:49 PM PDT 24 5652470081 ps
T866 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1704597985 Jul 10 05:52:39 PM PDT 24 Jul 10 05:53:01 PM PDT 24 1790547419 ps
T116 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1170249731 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:48 PM PDT 24 108576161 ps
T146 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3771788611 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:21 PM PDT 24 62060459 ps
T867 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.942935080 Jul 10 05:52:44 PM PDT 24 Jul 10 05:52:48 PM PDT 24 178119909 ps
T868 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.912314688 Jul 10 05:52:17 PM PDT 24 Jul 10 05:52:26 PM PDT 24 2011092097 ps
T869 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.996885580 Jul 10 05:52:31 PM PDT 24 Jul 10 05:52:34 PM PDT 24 167119627 ps
T112 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3313174105 Jul 10 05:52:09 PM PDT 24 Jul 10 05:52:17 PM PDT 24 514514634 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4216732983 Jul 10 05:52:20 PM PDT 24 Jul 10 05:53:09 PM PDT 24 11002093152 ps
T191 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2566960293 Jul 10 05:52:39 PM PDT 24 Jul 10 05:52:42 PM PDT 24 76890724 ps
T142 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.689661133 Jul 10 05:52:15 PM PDT 24 Jul 10 05:52:20 PM PDT 24 46655524 ps
T117 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.213329653 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:22 PM PDT 24 321307435 ps
T160 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.914385063 Jul 10 05:52:58 PM PDT 24 Jul 10 05:53:03 PM PDT 24 18921813 ps
T152 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2965391007 Jul 10 05:52:57 PM PDT 24 Jul 10 05:53:02 PM PDT 24 86456007 ps
T153 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3957942778 Jul 10 05:52:17 PM PDT 24 Jul 10 05:52:23 PM PDT 24 106363425 ps
T143 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1902420329 Jul 10 05:52:44 PM PDT 24 Jul 10 05:53:12 PM PDT 24 1239585212 ps
T113 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4277025095 Jul 10 05:52:53 PM PDT 24 Jul 10 05:52:57 PM PDT 24 85678219 ps
T871 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2649700920 Jul 10 05:52:37 PM PDT 24 Jul 10 05:52:39 PM PDT 24 50143229 ps
T154 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3144665743 Jul 10 05:52:50 PM PDT 24 Jul 10 05:52:53 PM PDT 24 51037225 ps
T130 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3949638827 Jul 10 05:52:47 PM PDT 24 Jul 10 05:52:51 PM PDT 24 81825545 ps
T155 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2250871117 Jul 10 05:52:33 PM PDT 24 Jul 10 05:52:35 PM PDT 24 18340220 ps
T192 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3050279795 Jul 10 05:52:46 PM PDT 24 Jul 10 05:52:49 PM PDT 24 29319676 ps
T144 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.251714637 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:23 PM PDT 24 369887491 ps
T180 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.437002923 Jul 10 05:52:29 PM PDT 24 Jul 10 05:52:32 PM PDT 24 31225335 ps
T127 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4253587447 Jul 10 05:52:53 PM PDT 24 Jul 10 05:52:57 PM PDT 24 157718182 ps
T118 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.81974284 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:01 PM PDT 24 275030750 ps
T119 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1640168751 Jul 10 05:52:50 PM PDT 24 Jul 10 05:52:53 PM PDT 24 66114767 ps
T872 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2791056014 Jul 10 05:52:39 PM PDT 24 Jul 10 05:52:42 PM PDT 24 129259998 ps
T873 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4129240511 Jul 10 05:52:29 PM PDT 24 Jul 10 05:52:32 PM PDT 24 16953125 ps
T874 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2396336031 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:45 PM PDT 24 46501520 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1763229140 Jul 10 05:52:11 PM PDT 24 Jul 10 05:52:19 PM PDT 24 304827962 ps
T193 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1220560850 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:45 PM PDT 24 27763153 ps
T194 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.130399415 Jul 10 05:52:50 PM PDT 24 Jul 10 05:52:53 PM PDT 24 35850901 ps
T156 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.813585262 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:02 PM PDT 24 1039137022 ps
T876 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3153829891 Jul 10 05:52:37 PM PDT 24 Jul 10 05:52:41 PM PDT 24 295159871 ps
T157 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.704183100 Jul 10 05:52:15 PM PDT 24 Jul 10 05:52:21 PM PDT 24 41635939 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1559948922 Jul 10 05:52:18 PM PDT 24 Jul 10 05:52:25 PM PDT 24 149385476 ps
T878 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.7996739 Jul 10 05:52:26 PM PDT 24 Jul 10 05:52:29 PM PDT 24 1071938338 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2280547258 Jul 10 05:52:25 PM PDT 24 Jul 10 05:52:27 PM PDT 24 61831309 ps
T880 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1034114713 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:46 PM PDT 24 20439116 ps
T195 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4059210992 Jul 10 05:52:17 PM PDT 24 Jul 10 05:52:22 PM PDT 24 15807180 ps
T881 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.201966482 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:02 PM PDT 24 1405728411 ps
T882 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.561512323 Jul 10 05:52:26 PM PDT 24 Jul 10 05:52:28 PM PDT 24 49497868 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2555743173 Jul 10 05:52:44 PM PDT 24 Jul 10 05:52:47 PM PDT 24 84454723 ps
T125 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1781959826 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:24 PM PDT 24 238574517 ps
T139 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2622338430 Jul 10 05:52:49 PM PDT 24 Jul 10 05:52:52 PM PDT 24 175346154 ps
T884 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3271290777 Jul 10 05:52:51 PM PDT 24 Jul 10 05:52:53 PM PDT 24 37143457 ps
T196 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2231834001 Jul 10 05:52:21 PM PDT 24 Jul 10 05:52:25 PM PDT 24 70275451 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1791588210 Jul 10 05:52:36 PM PDT 24 Jul 10 05:52:42 PM PDT 24 634981374 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.930532564 Jul 10 05:52:28 PM PDT 24 Jul 10 05:52:32 PM PDT 24 65379453 ps
T887 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3168219677 Jul 10 05:52:43 PM PDT 24 Jul 10 05:52:49 PM PDT 24 340611367 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1213040885 Jul 10 05:52:26 PM PDT 24 Jul 10 05:52:29 PM PDT 24 16049097 ps
T889 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3982854962 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:02 PM PDT 24 108295165 ps
T132 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1042990243 Jul 10 05:52:48 PM PDT 24 Jul 10 05:52:52 PM PDT 24 152349644 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1670265935 Jul 10 05:52:41 PM PDT 24 Jul 10 05:52:44 PM PDT 24 70849405 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3378225624 Jul 10 05:52:51 PM PDT 24 Jul 10 05:52:58 PM PDT 24 359310991 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4230165470 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:00 PM PDT 24 82557745 ps
T893 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4158108951 Jul 10 05:52:37 PM PDT 24 Jul 10 05:52:40 PM PDT 24 487060945 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.10702830 Jul 10 05:52:15 PM PDT 24 Jul 10 05:52:21 PM PDT 24 41307995 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1793803574 Jul 10 05:52:19 PM PDT 24 Jul 10 05:52:25 PM PDT 24 271222845 ps
T181 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1997235732 Jul 10 05:52:47 PM PDT 24 Jul 10 05:52:50 PM PDT 24 37306530 ps
T896 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2945463209 Jul 10 05:52:41 PM PDT 24 Jul 10 05:52:46 PM PDT 24 172478684 ps
T182 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4276295441 Jul 10 05:52:24 PM PDT 24 Jul 10 05:52:27 PM PDT 24 22048467 ps
T897 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2815033068 Jul 10 05:52:53 PM PDT 24 Jul 10 05:52:55 PM PDT 24 53875904 ps
T898 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2918275659 Jul 10 05:52:51 PM PDT 24 Jul 10 05:52:53 PM PDT 24 67415874 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1891933406 Jul 10 05:52:36 PM PDT 24 Jul 10 05:52:39 PM PDT 24 195478290 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4020654084 Jul 10 05:52:20 PM PDT 24 Jul 10 05:52:25 PM PDT 24 194180822 ps
T124 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2567285599 Jul 10 05:52:53 PM PDT 24 Jul 10 05:52:56 PM PDT 24 21817622 ps
T901 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4160069660 Jul 10 05:52:26 PM PDT 24 Jul 10 05:52:29 PM PDT 24 14136082 ps
T902 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.653319648 Jul 10 05:52:25 PM PDT 24 Jul 10 05:52:28 PM PDT 24 20504744 ps
T903 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.513274916 Jul 10 05:52:13 PM PDT 24 Jul 10 05:52:21 PM PDT 24 1745301119 ps
T135 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3972167530 Jul 10 05:52:48 PM PDT 24 Jul 10 05:52:52 PM PDT 24 138187826 ps
T904 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2654348029 Jul 10 05:52:47 PM PDT 24 Jul 10 05:52:50 PM PDT 24 36017363 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1542824730 Jul 10 05:52:39 PM PDT 24 Jul 10 05:52:42 PM PDT 24 82700656 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2773666955 Jul 10 05:52:41 PM PDT 24 Jul 10 05:52:52 PM PDT 24 2394624830 ps
T133 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1120729184 Jul 10 05:52:52 PM PDT 24 Jul 10 05:52:56 PM PDT 24 115277925 ps
T907 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3443119242 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:02 PM PDT 24 900696184 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3928072229 Jul 10 05:52:14 PM PDT 24 Jul 10 05:52:20 PM PDT 24 89669035 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1740008577 Jul 10 05:52:28 PM PDT 24 Jul 10 05:52:31 PM PDT 24 664580366 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3542718387 Jul 10 05:52:48 PM PDT 24 Jul 10 05:52:51 PM PDT 24 26715485 ps
T911 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1466871873 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:46 PM PDT 24 28931280 ps
T912 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3954617214 Jul 10 05:52:54 PM PDT 24 Jul 10 05:52:56 PM PDT 24 152714694 ps
T183 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3806749014 Jul 10 05:52:47 PM PDT 24 Jul 10 05:52:50 PM PDT 24 23593720 ps
T913 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.53324720 Jul 10 05:52:15 PM PDT 24 Jul 10 05:52:26 PM PDT 24 2659456934 ps
T914 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3001552270 Jul 10 05:52:35 PM PDT 24 Jul 10 05:52:38 PM PDT 24 231958546 ps
T126 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2399173051 Jul 10 05:52:57 PM PDT 24 Jul 10 05:53:03 PM PDT 24 308538052 ps
T915 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4112973981 Jul 10 05:52:55 PM PDT 24 Jul 10 05:52:59 PM PDT 24 17120745 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2731298089 Jul 10 05:52:26 PM PDT 24 Jul 10 05:52:29 PM PDT 24 180096158 ps
T917 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.834648384 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:00 PM PDT 24 46878246 ps
T918 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4045091392 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:23 PM PDT 24 74983851 ps
T919 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.169305383 Jul 10 05:52:40 PM PDT 24 Jul 10 05:52:44 PM PDT 24 96989488 ps
T920 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1045759768 Jul 10 05:52:15 PM PDT 24 Jul 10 05:52:32 PM PDT 24 4854540408 ps
T921 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2097026003 Jul 10 05:52:44 PM PDT 24 Jul 10 05:52:47 PM PDT 24 175583541 ps
T922 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2935790795 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:21 PM PDT 24 198510106 ps
T923 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1943486553 Jul 10 05:53:01 PM PDT 24 Jul 10 05:53:06 PM PDT 24 26038320 ps
T924 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2428006907 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:21 PM PDT 24 110869047 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.918864918 Jul 10 05:52:20 PM PDT 24 Jul 10 05:52:24 PM PDT 24 30672866 ps
T926 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1811147948 Jul 10 05:52:49 PM PDT 24 Jul 10 05:52:52 PM PDT 24 22570087 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.501081542 Jul 10 05:52:21 PM PDT 24 Jul 10 05:52:25 PM PDT 24 17705082 ps
T928 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2292605770 Jul 10 05:52:51 PM PDT 24 Jul 10 05:52:54 PM PDT 24 51339464 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.681630265 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:46 PM PDT 24 37707709 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1621543934 Jul 10 05:52:35 PM PDT 24 Jul 10 05:52:38 PM PDT 24 65271950 ps
T931 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2744469184 Jul 10 05:52:17 PM PDT 24 Jul 10 05:52:23 PM PDT 24 344507431 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3985618849 Jul 10 05:52:28 PM PDT 24 Jul 10 05:52:31 PM PDT 24 29117297 ps
T138 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3870395621 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:48 PM PDT 24 112566968 ps
T184 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.775549912 Jul 10 05:52:51 PM PDT 24 Jul 10 05:52:53 PM PDT 24 42669231 ps
T185 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4178940273 Jul 10 05:52:38 PM PDT 24 Jul 10 05:52:41 PM PDT 24 32163489 ps
T128 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.822786618 Jul 10 05:52:19 PM PDT 24 Jul 10 05:52:26 PM PDT 24 217782824 ps
T933 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.210323702 Jul 10 05:52:54 PM PDT 24 Jul 10 05:52:57 PM PDT 24 26017109 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1096943450 Jul 10 05:52:13 PM PDT 24 Jul 10 05:52:20 PM PDT 24 120566697 ps
T935 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2894894871 Jul 10 05:52:53 PM PDT 24 Jul 10 05:52:55 PM PDT 24 12391648 ps
T123 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1729824904 Jul 10 05:52:39 PM PDT 24 Jul 10 05:52:45 PM PDT 24 323805016 ps
T936 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3343001827 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:00 PM PDT 24 140781539 ps
T937 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3301605974 Jul 10 05:52:44 PM PDT 24 Jul 10 05:52:47 PM PDT 24 648433754 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3547630502 Jul 10 05:52:11 PM PDT 24 Jul 10 05:52:17 PM PDT 24 188289726 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.758421695 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:11 PM PDT 24 4272748232 ps
T940 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.592728956 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:22 PM PDT 24 39562123 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3633669454 Jul 10 05:52:29 PM PDT 24 Jul 10 05:52:36 PM PDT 24 579985209 ps
T186 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2917380134 Jul 10 05:52:21 PM PDT 24 Jul 10 05:52:25 PM PDT 24 279809068 ps
T942 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2104245254 Jul 10 05:52:55 PM PDT 24 Jul 10 05:52:59 PM PDT 24 58599740 ps
T943 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3006845811 Jul 10 05:52:41 PM PDT 24 Jul 10 05:52:44 PM PDT 24 19951006 ps
T944 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.312327910 Jul 10 05:52:38 PM PDT 24 Jul 10 05:52:57 PM PDT 24 37524611444 ps
T945 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3329165549 Jul 10 05:52:26 PM PDT 24 Jul 10 05:52:29 PM PDT 24 24760716 ps
T946 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1435254010 Jul 10 05:52:38 PM PDT 24 Jul 10 05:52:40 PM PDT 24 12546292 ps
T947 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3371179513 Jul 10 05:52:27 PM PDT 24 Jul 10 05:52:30 PM PDT 24 401978844 ps
T948 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2745827230 Jul 10 05:52:54 PM PDT 24 Jul 10 05:52:57 PM PDT 24 22393804 ps
T949 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.936792075 Jul 10 05:52:12 PM PDT 24 Jul 10 05:52:23 PM PDT 24 1244875505 ps
T950 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3237777785 Jul 10 05:52:53 PM PDT 24 Jul 10 05:52:58 PM PDT 24 59927664 ps
T137 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1193738280 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:23 PM PDT 24 271216619 ps
T951 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3157092539 Jul 10 05:52:49 PM PDT 24 Jul 10 05:52:52 PM PDT 24 55470084 ps
T952 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2287746221 Jul 10 05:52:38 PM PDT 24 Jul 10 05:52:41 PM PDT 24 27508786 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3480795559 Jul 10 05:52:45 PM PDT 24 Jul 10 05:52:56 PM PDT 24 372801410 ps
T954 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.929819917 Jul 10 05:52:37 PM PDT 24 Jul 10 05:52:40 PM PDT 24 130985162 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.78427749 Jul 10 05:52:22 PM PDT 24 Jul 10 05:52:27 PM PDT 24 226923999 ps
T956 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2259613582 Jul 10 05:52:25 PM PDT 24 Jul 10 05:52:30 PM PDT 24 3493265187 ps
T141 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3395493701 Jul 10 05:52:54 PM PDT 24 Jul 10 05:52:59 PM PDT 24 330200413 ps
T957 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1006813839 Jul 10 05:52:47 PM PDT 24 Jul 10 05:52:50 PM PDT 24 52257885 ps
T187 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1740070645 Jul 10 05:52:50 PM PDT 24 Jul 10 05:52:52 PM PDT 24 25225916 ps
T958 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3472405126 Jul 10 05:52:55 PM PDT 24 Jul 10 05:52:59 PM PDT 24 44116466 ps
T959 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3815026801 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:45 PM PDT 24 18245061 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2862336993 Jul 10 05:52:43 PM PDT 24 Jul 10 05:52:46 PM PDT 24 64735898 ps
T188 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2319094127 Jul 10 05:52:17 PM PDT 24 Jul 10 05:52:22 PM PDT 24 20673300 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3195776290 Jul 10 05:52:19 PM PDT 24 Jul 10 05:52:24 PM PDT 24 22183210 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3467819288 Jul 10 05:52:19 PM PDT 24 Jul 10 05:52:28 PM PDT 24 745472054 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3664788946 Jul 10 05:52:27 PM PDT 24 Jul 10 05:52:32 PM PDT 24 44587815 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3725671083 Jul 10 05:52:38 PM PDT 24 Jul 10 05:52:40 PM PDT 24 64345044 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.931285901 Jul 10 05:52:19 PM PDT 24 Jul 10 05:52:31 PM PDT 24 833028402 ps
T966 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2815336799 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:21 PM PDT 24 83031628 ps
T967 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3102203415 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:01 PM PDT 24 31421288 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1503494548 Jul 10 05:52:16 PM PDT 24 Jul 10 05:52:29 PM PDT 24 942056117 ps
T140 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3870327610 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:49 PM PDT 24 838709090 ps
T969 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3505120904 Jul 10 05:52:50 PM PDT 24 Jul 10 05:52:56 PM PDT 24 153322855 ps
T136 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3985637612 Jul 10 05:52:51 PM PDT 24 Jul 10 05:52:55 PM PDT 24 59995871 ps
T970 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1893143168 Jul 10 05:52:10 PM PDT 24 Jul 10 05:52:17 PM PDT 24 88169319 ps
T971 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3934039318 Jul 10 05:52:46 PM PDT 24 Jul 10 05:53:02 PM PDT 24 1246760858 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2466196655 Jul 10 05:52:19 PM PDT 24 Jul 10 05:52:24 PM PDT 24 62207515 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1891332734 Jul 10 05:52:25 PM PDT 24 Jul 10 05:52:30 PM PDT 24 605999713 ps
T974 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2037444139 Jul 10 05:52:49 PM PDT 24 Jul 10 05:52:52 PM PDT 24 93188867 ps
T189 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.312538645 Jul 10 05:52:20 PM PDT 24 Jul 10 05:52:24 PM PDT 24 28462592 ps
T131 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.283227031 Jul 10 05:52:21 PM PDT 24 Jul 10 05:52:26 PM PDT 24 92458164 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2997798702 Jul 10 05:52:15 PM PDT 24 Jul 10 05:52:21 PM PDT 24 29158704 ps
T976 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1599436994 Jul 10 05:52:40 PM PDT 24 Jul 10 05:52:54 PM PDT 24 1814032870 ps
T977 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.831361557 Jul 10 05:52:20 PM PDT 24 Jul 10 05:52:25 PM PDT 24 76834891 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2495606732 Jul 10 05:52:56 PM PDT 24 Jul 10 05:53:01 PM PDT 24 2802803934 ps
T979 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1059892449 Jul 10 05:52:47 PM PDT 24 Jul 10 05:52:49 PM PDT 24 44611229 ps
T980 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3482512901 Jul 10 05:52:36 PM PDT 24 Jul 10 05:52:39 PM PDT 24 698259052 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3923310214 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:46 PM PDT 24 94141221 ps
T190 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1929610830 Jul 10 05:52:53 PM PDT 24 Jul 10 05:52:56 PM PDT 24 14574042 ps
T982 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4076054366 Jul 10 05:52:55 PM PDT 24 Jul 10 05:53:00 PM PDT 24 102641790 ps
T983 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1674208913 Jul 10 05:52:49 PM PDT 24 Jul 10 05:52:51 PM PDT 24 26424173 ps
T129 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1250359431 Jul 10 05:52:42 PM PDT 24 Jul 10 05:52:46 PM PDT 24 297617500 ps
T984 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3684042499 Jul 10 05:52:36 PM PDT 24 Jul 10 05:52:38 PM PDT 24 157424476 ps
T985 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.94110236 Jul 10 05:52:55 PM PDT 24 Jul 10 05:52:58 PM PDT 24 45073420 ps
T986 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.817148819 Jul 10 05:52:19 PM PDT 24 Jul 10 05:52:24 PM PDT 24 35616949 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3503191508 Jul 10 05:52:41 PM PDT 24 Jul 10 05:52:54 PM PDT 24 1821154011 ps
T134 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1239918113 Jul 10 05:52:58 PM PDT 24 Jul 10 05:53:05 PM PDT 24 955930434 ps
T988 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3070302399 Jul 10 05:52:47 PM PDT 24 Jul 10 05:52:50 PM PDT 24 32189116 ps

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4046610064
Short name T11
Test name
Test status
Simulation time 1208029866 ps
CPU time 9.42 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:01:17 PM PDT 24
Peak memory 226004 kb
Host smart-790c666d-4ece-4872-99d0-0546a11568cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046610064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4046610064
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1515158957
Short name T5
Test name
Test status
Simulation time 4453948579 ps
CPU time 60.31 seconds
Started Jul 10 06:58:25 PM PDT 24
Finished Jul 10 06:59:26 PM PDT 24
Peak memory 267424 kb
Host smart-2956ff65-2fb5-4658-b917-ef6c81de7022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515158957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1515158957
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1671293908
Short name T24
Test name
Test status
Simulation time 30527026063 ps
CPU time 295.62 seconds
Started Jul 10 06:59:51 PM PDT 24
Finished Jul 10 07:04:48 PM PDT 24
Peak memory 316504 kb
Host smart-a1359aad-3327-4659-bb7b-d74478ad7e22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1671293908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1671293908
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.608958181
Short name T2
Test name
Test status
Simulation time 530893089 ps
CPU time 14.9 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:14 PM PDT 24
Peak memory 218852 kb
Host smart-3ef2de0b-0b8d-4fae-a5aa-fcd1d9f22121
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608958181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.608958181
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2471724540
Short name T1
Test name
Test status
Simulation time 555368374 ps
CPU time 17.94 seconds
Started Jul 10 07:02:16 PM PDT 24
Finished Jul 10 07:02:35 PM PDT 24
Peak memory 226032 kb
Host smart-48f62a8b-7bcb-40bf-bb38-f379e9b5da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471724540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2471724540
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1089987652
Short name T4
Test name
Test status
Simulation time 1164175789 ps
CPU time 9.36 seconds
Started Jul 10 07:00:12 PM PDT 24
Finished Jul 10 07:00:23 PM PDT 24
Peak memory 217408 kb
Host smart-e339daa6-b587-4abd-9f1d-0a706df30aa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089987652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1089987652
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3313174105
Short name T112
Test name
Test status
Simulation time 514514634 ps
CPU time 3.22 seconds
Started Jul 10 05:52:09 PM PDT 24
Finished Jul 10 05:52:17 PM PDT 24
Peak memory 217532 kb
Host smart-531b23bd-2c56-46b9-9c7e-30a0cfa04d83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313174105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3313174105
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2127308675
Short name T52
Test name
Test status
Simulation time 109301727 ps
CPU time 24.91 seconds
Started Jul 10 06:55:39 PM PDT 24
Finished Jul 10 06:56:05 PM PDT 24
Peak memory 268864 kb
Host smart-a38683bb-9288-4398-8501-c75aa2019805
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127308675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2127308675
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4179755825
Short name T151
Test name
Test status
Simulation time 15191243664 ps
CPU time 236.71 seconds
Started Jul 10 06:56:00 PM PDT 24
Finished Jul 10 06:59:58 PM PDT 24
Peak memory 264984 kb
Host smart-240d110b-8cf3-4261-a45f-0b2e35569c67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4179755825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.4179755825
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.625587581
Short name T55
Test name
Test status
Simulation time 34611754448 ps
CPU time 209.19 seconds
Started Jul 10 06:56:24 PM PDT 24
Finished Jul 10 06:59:53 PM PDT 24
Peak memory 283920 kb
Host smart-dbee59d0-25b0-4abb-92a5-9c9cc64b5d3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=625587581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.625587581
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1804980876
Short name T111
Test name
Test status
Simulation time 550620699 ps
CPU time 4.06 seconds
Started Jul 10 05:52:41 PM PDT 24
Finished Jul 10 05:52:47 PM PDT 24
Peak memory 217500 kb
Host smart-3d92a3f0-6050-41fb-a2d8-cf18c66c4856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804980876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1804980876
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1640290417
Short name T9
Test name
Test status
Simulation time 22950529 ps
CPU time 1.29 seconds
Started Jul 10 07:00:33 PM PDT 24
Finished Jul 10 07:00:36 PM PDT 24
Peak memory 209000 kb
Host smart-ee31b270-8447-40dd-91ea-406e0798a7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640290417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1640290417
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2277652852
Short name T16
Test name
Test status
Simulation time 531660223 ps
CPU time 10.01 seconds
Started Jul 10 06:58:32 PM PDT 24
Finished Jul 10 06:58:43 PM PDT 24
Peak memory 226012 kb
Host smart-13c4d68c-1edb-4de4-a883-f639f007d3b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277652852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2277652852
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.437002923
Short name T180
Test name
Test status
Simulation time 31225335 ps
CPU time 1.39 seconds
Started Jul 10 05:52:29 PM PDT 24
Finished Jul 10 05:52:32 PM PDT 24
Peak memory 209324 kb
Host smart-121dd8a8-2554-45a8-9f66-50acf20c4e6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437002923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.437002923
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.689661133
Short name T142
Test name
Test status
Simulation time 46655524 ps
CPU time 1.28 seconds
Started Jul 10 05:52:15 PM PDT 24
Finished Jul 10 05:52:20 PM PDT 24
Peak memory 210776 kb
Host smart-dd7e3434-3ae1-4e48-9f2e-c56442119cd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689661133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.689661133
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4266395238
Short name T57
Test name
Test status
Simulation time 38137608131 ps
CPU time 328.15 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:05:40 PM PDT 24
Peak memory 497020 kb
Host smart-3f56ed47-714f-4aa2-9949-da4db05a1d13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4266395238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.4266395238
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.822786618
Short name T128
Test name
Test status
Simulation time 217782824 ps
CPU time 3.08 seconds
Started Jul 10 05:52:19 PM PDT 24
Finished Jul 10 05:52:26 PM PDT 24
Peak memory 222340 kb
Host smart-c2c8722f-9826-4c00-922e-03157e981286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822786618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.822786618
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.692447785
Short name T29
Test name
Test status
Simulation time 1301431618 ps
CPU time 13.16 seconds
Started Jul 10 07:01:15 PM PDT 24
Finished Jul 10 07:01:29 PM PDT 24
Peak memory 224908 kb
Host smart-4d50694e-27de-4c93-8ae1-716f7776747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692447785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.692447785
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.705028110
Short name T90
Test name
Test status
Simulation time 60386682365 ps
CPU time 245.35 seconds
Started Jul 10 07:00:40 PM PDT 24
Finished Jul 10 07:04:46 PM PDT 24
Peak memory 283596 kb
Host smart-4d5b1abe-bb9c-4aad-bd59-84214cda06e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=705028110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.705028110
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.150570574
Short name T44
Test name
Test status
Simulation time 284214422 ps
CPU time 14.59 seconds
Started Jul 10 06:58:03 PM PDT 24
Finished Jul 10 06:58:18 PM PDT 24
Peak memory 218152 kb
Host smart-0dc29a87-bdcb-4e2c-8f4d-9757892dccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150570574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.150570574
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3972167530
Short name T135
Test name
Test status
Simulation time 138187826 ps
CPU time 3.07 seconds
Started Jul 10 05:52:48 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 222328 kb
Host smart-55e4721e-c2bf-439f-a301-5de0d7acf0e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972167530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3972167530
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3396003289
Short name T46
Test name
Test status
Simulation time 837164805 ps
CPU time 19.49 seconds
Started Jul 10 06:58:13 PM PDT 24
Finished Jul 10 06:58:33 PM PDT 24
Peak memory 225980 kb
Host smart-c632adb8-a2b2-4e3a-bfdf-e0d72acab190
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396003289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3396003289
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.4285841192
Short name T34
Test name
Test status
Simulation time 298445145 ps
CPU time 4.87 seconds
Started Jul 10 07:00:45 PM PDT 24
Finished Jul 10 07:00:51 PM PDT 24
Peak memory 217092 kb
Host smart-008151bb-189e-44a2-a9be-c35a4d95c623
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285841192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.4285841192
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3985637612
Short name T136
Test name
Test status
Simulation time 59995871 ps
CPU time 2.72 seconds
Started Jul 10 05:52:51 PM PDT 24
Finished Jul 10 05:52:55 PM PDT 24
Peak memory 217520 kb
Host smart-df315ab5-4490-4b6b-92a9-5c650088cb16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985637612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3985637612
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1239918113
Short name T134
Test name
Test status
Simulation time 955930434 ps
CPU time 4.32 seconds
Started Jul 10 05:52:58 PM PDT 24
Finished Jul 10 05:53:05 PM PDT 24
Peak memory 217520 kb
Host smart-d035514b-c7be-4ad9-b80c-70af2cff0708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239918113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1239918113
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2231834001
Short name T196
Test name
Test status
Simulation time 70275451 ps
CPU time 1.22 seconds
Started Jul 10 05:52:21 PM PDT 24
Finished Jul 10 05:52:25 PM PDT 24
Peak memory 209360 kb
Host smart-c6f8b73b-a600-4736-b2eb-891d0b1c861c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231834001 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2231834001
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3326499293
Short name T18
Test name
Test status
Simulation time 109203187850 ps
CPU time 527.81 seconds
Started Jul 10 06:57:54 PM PDT 24
Finished Jul 10 07:06:43 PM PDT 24
Peak memory 264356 kb
Host smart-9ca02da3-46d2-4cf7-ad34-f0e6525abf55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3326499293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3326499293
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1279846784
Short name T14
Test name
Test status
Simulation time 39183684 ps
CPU time 0.82 seconds
Started Jul 10 07:01:30 PM PDT 24
Finished Jul 10 07:01:32 PM PDT 24
Peak memory 211820 kb
Host smart-ffa40d3d-ef85-462c-b891-69ae6a0e1a11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279846784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1279846784
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1170249731
Short name T116
Test name
Test status
Simulation time 108576161 ps
CPU time 4.19 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:48 PM PDT 24
Peak memory 217480 kb
Host smart-67bfc999-e670-4f6b-9f30-9a770ffb6c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170249731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1170249731
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1193738280
Short name T137
Test name
Test status
Simulation time 271216619 ps
CPU time 3.26 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:23 PM PDT 24
Peak memory 217536 kb
Host smart-d24aa723-4449-4b58-b805-70c6db0480ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193738280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1193738280
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.81974284
Short name T118
Test name
Test status
Simulation time 275030750 ps
CPU time 1.9 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:01 PM PDT 24
Peak memory 221500 kb
Host smart-0ee6ab75-702c-496c-980d-507b2cea2b39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81974284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_er
r.81974284
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.4034409570
Short name T739
Test name
Test status
Simulation time 13869794 ps
CPU time 0.82 seconds
Started Jul 10 06:55:23 PM PDT 24
Finished Jul 10 06:55:24 PM PDT 24
Peak memory 209040 kb
Host smart-26757970-d6f6-44f9-8888-84fde55f6208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034409570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4034409570
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.605284920
Short name T198
Test name
Test status
Simulation time 11114128 ps
CPU time 0.93 seconds
Started Jul 10 06:57:00 PM PDT 24
Finished Jul 10 06:57:02 PM PDT 24
Peak memory 208924 kb
Host smart-423da850-b9d2-401e-9a68-0f3542d6a133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605284920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.605284920
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3804507945
Short name T12
Test name
Test status
Simulation time 259814616 ps
CPU time 10.17 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 07:00:01 PM PDT 24
Peak memory 226112 kb
Host smart-ba5cf410-9470-407b-9935-343323028f94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804507945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3804507945
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.283227031
Short name T131
Test name
Test status
Simulation time 92458164 ps
CPU time 2.21 seconds
Started Jul 10 05:52:21 PM PDT 24
Finished Jul 10 05:52:26 PM PDT 24
Peak memory 221992 kb
Host smart-1911401c-5e80-406b-88b2-ad419af5c420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283227031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.283227031
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1640168751
Short name T119
Test name
Test status
Simulation time 66114767 ps
CPU time 2.11 seconds
Started Jul 10 05:52:50 PM PDT 24
Finished Jul 10 05:52:53 PM PDT 24
Peak memory 221828 kb
Host smart-76e6e410-7b30-4306-a886-bca62b812c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640168751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1640168751
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2622338430
Short name T139
Test name
Test status
Simulation time 175346154 ps
CPU time 2.37 seconds
Started Jul 10 05:52:49 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 217668 kb
Host smart-ac1e8eb1-8f5a-48c5-ad21-7518fa6fd592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622338430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2622338430
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2399173051
Short name T126
Test name
Test status
Simulation time 308538052 ps
CPU time 2.68 seconds
Started Jul 10 05:52:57 PM PDT 24
Finished Jul 10 05:53:03 PM PDT 24
Peak memory 217532 kb
Host smart-5f46be2f-66bd-4dda-94cd-a37b9918da82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399173051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2399173051
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1729824904
Short name T123
Test name
Test status
Simulation time 323805016 ps
CPU time 3.57 seconds
Started Jul 10 05:52:39 PM PDT 24
Finished Jul 10 05:52:45 PM PDT 24
Peak memory 222188 kb
Host smart-8f71769d-1868-4934-bcb6-9ca6f16534a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729824904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1729824904
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.917519911
Short name T49
Test name
Test status
Simulation time 31684316018 ps
CPU time 247.61 seconds
Started Jul 10 06:59:25 PM PDT 24
Finished Jul 10 07:03:33 PM PDT 24
Peak memory 276900 kb
Host smart-f1c53ee4-bccb-40c0-9810-161f6c25077d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917519911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.917519911
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3828235488
Short name T8
Test name
Test status
Simulation time 298910123 ps
CPU time 10.1 seconds
Started Jul 10 06:58:02 PM PDT 24
Finished Jul 10 06:58:13 PM PDT 24
Peak memory 218360 kb
Host smart-57aa673a-30fb-453a-9f46-d962c0cdfead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828235488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3828235488
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1096943450
Short name T934
Test name
Test status
Simulation time 120566697 ps
CPU time 1.29 seconds
Started Jul 10 05:52:13 PM PDT 24
Finished Jul 10 05:52:20 PM PDT 24
Peak memory 209204 kb
Host smart-948bed4c-d92e-4b9c-9b15-77c51f4fd1c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096943450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1096943450
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2250871117
Short name T155
Test name
Test status
Simulation time 18340220 ps
CPU time 1.01 seconds
Started Jul 10 05:52:33 PM PDT 24
Finished Jul 10 05:52:35 PM PDT 24
Peak memory 209892 kb
Host smart-1da1255f-946a-4f62-b796-7507d004f2db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250871117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2250871117
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3263113598
Short name T120
Test name
Test status
Simulation time 54762734 ps
CPU time 1.39 seconds
Started Jul 10 05:52:15 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 219152 kb
Host smart-c300dabf-3180-4946-b893-a4a4fd6cac54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263113598 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3263113598
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.918864918
Short name T925
Test name
Test status
Simulation time 30672866 ps
CPU time 0.86 seconds
Started Jul 10 05:52:20 PM PDT 24
Finished Jul 10 05:52:24 PM PDT 24
Peak memory 209004 kb
Host smart-e9699fcb-2f00-4d76-947a-efb4c050b945
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918864918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.918864918
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3547630502
Short name T938
Test name
Test status
Simulation time 188289726 ps
CPU time 1.77 seconds
Started Jul 10 05:52:11 PM PDT 24
Finished Jul 10 05:52:17 PM PDT 24
Peak memory 209108 kb
Host smart-84d2a4e6-c2bc-42cb-9de3-8ef0b18383aa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547630502 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3547630502
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.936792075
Short name T949
Test name
Test status
Simulation time 1244875505 ps
CPU time 6.26 seconds
Started Jul 10 05:52:12 PM PDT 24
Finished Jul 10 05:52:23 PM PDT 24
Peak memory 216976 kb
Host smart-7ba4f958-06a8-474f-8b0d-f5fa2775d25d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936792075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.936792075
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4216732983
Short name T870
Test name
Test status
Simulation time 11002093152 ps
CPU time 45.56 seconds
Started Jul 10 05:52:20 PM PDT 24
Finished Jul 10 05:53:09 PM PDT 24
Peak memory 209332 kb
Host smart-1291e5a0-9ce5-4e0d-a9f6-753f1f6069f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216732983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4216732983
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1763229140
Short name T875
Test name
Test status
Simulation time 304827962 ps
CPU time 2.55 seconds
Started Jul 10 05:52:11 PM PDT 24
Finished Jul 10 05:52:19 PM PDT 24
Peak memory 210704 kb
Host smart-5e1c51c5-eb1a-4cbc-b815-a7c4f813a5a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763229140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1763229140
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4020654084
Short name T900
Test name
Test status
Simulation time 194180822 ps
CPU time 1.44 seconds
Started Jul 10 05:52:20 PM PDT 24
Finished Jul 10 05:52:25 PM PDT 24
Peak memory 217588 kb
Host smart-ffdeb474-fced-4800-884b-364f41a8df53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402065
4084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4020654084
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2466196655
Short name T972
Test name
Test status
Simulation time 62207515 ps
CPU time 1.32 seconds
Started Jul 10 05:52:19 PM PDT 24
Finished Jul 10 05:52:24 PM PDT 24
Peak memory 209008 kb
Host smart-9aba9c99-50dd-43ab-b9e1-c86f174121bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466196655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2466196655
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1893143168
Short name T970
Test name
Test status
Simulation time 88169319 ps
CPU time 1.34 seconds
Started Jul 10 05:52:10 PM PDT 24
Finished Jul 10 05:52:17 PM PDT 24
Peak memory 217544 kb
Host smart-14422caa-d247-4ca0-aa33-8d8147d318af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893143168 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1893143168
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3985618849
Short name T932
Test name
Test status
Simulation time 29117297 ps
CPU time 1.06 seconds
Started Jul 10 05:52:28 PM PDT 24
Finished Jul 10 05:52:31 PM PDT 24
Peak memory 209308 kb
Host smart-acfea9c6-5d0a-48e4-a804-6632747089c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985618849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3985618849
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2319094127
Short name T188
Test name
Test status
Simulation time 20673300 ps
CPU time 1.41 seconds
Started Jul 10 05:52:17 PM PDT 24
Finished Jul 10 05:52:22 PM PDT 24
Peak memory 209332 kb
Host smart-593e5110-4f95-43c2-980a-52a466a3a14b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319094127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2319094127
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3928072229
Short name T908
Test name
Test status
Simulation time 89669035 ps
CPU time 1.38 seconds
Started Jul 10 05:52:14 PM PDT 24
Finished Jul 10 05:52:20 PM PDT 24
Peak memory 209292 kb
Host smart-6f803e6e-0cd1-4349-bf0f-55925da1f1f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928072229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3928072229
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2997798702
Short name T975
Test name
Test status
Simulation time 29158704 ps
CPU time 0.99 seconds
Started Jul 10 05:52:15 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 209948 kb
Host smart-763567d4-53f7-45f0-81a3-7da4f05995c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997798702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2997798702
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2815336799
Short name T966
Test name
Test status
Simulation time 83031628 ps
CPU time 1.45 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 217592 kb
Host smart-548ad8c4-3d72-4603-98dc-d3e774777609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815336799 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2815336799
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.312538645
Short name T189
Test name
Test status
Simulation time 28462592 ps
CPU time 1.08 seconds
Started Jul 10 05:52:20 PM PDT 24
Finished Jul 10 05:52:24 PM PDT 24
Peak memory 217252 kb
Host smart-5ff6e8b2-dd4a-4644-921e-d9711c218a86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312538645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.312538645
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.930532564
Short name T886
Test name
Test status
Simulation time 65379453 ps
CPU time 2.14 seconds
Started Jul 10 05:52:28 PM PDT 24
Finished Jul 10 05:52:32 PM PDT 24
Peak memory 209180 kb
Host smart-de157309-ac35-4f73-9b7c-fe49218f16a5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930532564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.930532564
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1503494548
Short name T968
Test name
Test status
Simulation time 942056117 ps
CPU time 8.52 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:29 PM PDT 24
Peak memory 209256 kb
Host smart-d9491075-f476-47aa-b0a4-46355efd48dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503494548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1503494548
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3296050494
Short name T147
Test name
Test status
Simulation time 5652470081 ps
CPU time 15.82 seconds
Started Jul 10 05:52:33 PM PDT 24
Finished Jul 10 05:52:49 PM PDT 24
Peak memory 209304 kb
Host smart-f185ea19-a295-4b2c-a3e4-58cd72b90423
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296050494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3296050494
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2744469184
Short name T931
Test name
Test status
Simulation time 344507431 ps
CPU time 1.65 seconds
Started Jul 10 05:52:17 PM PDT 24
Finished Jul 10 05:52:23 PM PDT 24
Peak memory 217468 kb
Host smart-06075cff-a161-4570-9cf2-31b26598a9f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744469184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2744469184
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2731298089
Short name T916
Test name
Test status
Simulation time 180096158 ps
CPU time 2.37 seconds
Started Jul 10 05:52:26 PM PDT 24
Finished Jul 10 05:52:29 PM PDT 24
Peak memory 217596 kb
Host smart-59d2aee6-fdf2-4f85-86f9-fcfcf4a26cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273129
8089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2731298089
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2746776111
Short name T145
Test name
Test status
Simulation time 148825449 ps
CPU time 1.13 seconds
Started Jul 10 05:52:28 PM PDT 24
Finished Jul 10 05:52:30 PM PDT 24
Peak memory 209284 kb
Host smart-3ddd32f0-5c24-43e1-86dd-44224d5fd2a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746776111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2746776111
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.592728956
Short name T940
Test name
Test status
Simulation time 39562123 ps
CPU time 1.88 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:22 PM PDT 24
Peak memory 209272 kb
Host smart-3d7f5aea-6fd2-4393-a1e3-0fe9d8de2184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592728956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.592728956
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.513274916
Short name T903
Test name
Test status
Simulation time 1745301119 ps
CPU time 3.02 seconds
Started Jul 10 05:52:13 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 217580 kb
Host smart-350a7bbb-8dc7-4682-84b2-7956f89beb44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513274916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.513274916
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3271290777
Short name T884
Test name
Test status
Simulation time 37143457 ps
CPU time 1.26 seconds
Started Jul 10 05:52:51 PM PDT 24
Finished Jul 10 05:52:53 PM PDT 24
Peak memory 219056 kb
Host smart-c2a7579d-d34e-4387-8b92-efede2600005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271290777 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3271290777
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3806749014
Short name T183
Test name
Test status
Simulation time 23593720 ps
CPU time 0.87 seconds
Started Jul 10 05:52:47 PM PDT 24
Finished Jul 10 05:52:50 PM PDT 24
Peak memory 209380 kb
Host smart-12c5c458-01e0-40c5-9fc5-8f8129085e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806749014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3806749014
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3157092539
Short name T951
Test name
Test status
Simulation time 55470084 ps
CPU time 1.05 seconds
Started Jul 10 05:52:49 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 209336 kb
Host smart-d55c58de-0939-487c-bd4c-59fdc1db3f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157092539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3157092539
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1006813839
Short name T957
Test name
Test status
Simulation time 52257885 ps
CPU time 1.24 seconds
Started Jul 10 05:52:47 PM PDT 24
Finished Jul 10 05:52:50 PM PDT 24
Peak memory 218780 kb
Host smart-c05d2dd0-c70d-4ba7-9dc3-5b968c101142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006813839 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1006813839
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.452175322
Short name T179
Test name
Test status
Simulation time 51460605 ps
CPU time 1.02 seconds
Started Jul 10 05:52:48 PM PDT 24
Finished Jul 10 05:52:50 PM PDT 24
Peak memory 209516 kb
Host smart-1920facf-596a-491a-b5b8-490d9c9baae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452175322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.452175322
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3144665743
Short name T154
Test name
Test status
Simulation time 51037225 ps
CPU time 1.46 seconds
Started Jul 10 05:52:50 PM PDT 24
Finished Jul 10 05:52:53 PM PDT 24
Peak memory 209336 kb
Host smart-004d4527-b67d-4f0d-abdd-81ee3618d486
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144665743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3144665743
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2037444139
Short name T974
Test name
Test status
Simulation time 93188867 ps
CPU time 1.81 seconds
Started Jul 10 05:52:49 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 218492 kb
Host smart-213e06ab-4ad0-40f8-8812-b4efed8b6294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037444139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2037444139
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1674208913
Short name T983
Test name
Test status
Simulation time 26424173 ps
CPU time 1.28 seconds
Started Jul 10 05:52:49 PM PDT 24
Finished Jul 10 05:52:51 PM PDT 24
Peak memory 218684 kb
Host smart-19d8552b-cab4-46d7-a83d-6f17c91ae7f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674208913 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1674208913
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3472405126
Short name T958
Test name
Test status
Simulation time 44116466 ps
CPU time 0.83 seconds
Started Jul 10 05:52:55 PM PDT 24
Finished Jul 10 05:52:59 PM PDT 24
Peak memory 208684 kb
Host smart-0ef170e4-6619-41f2-b0c2-b0b1513926b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472405126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3472405126
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3050279795
Short name T192
Test name
Test status
Simulation time 29319676 ps
CPU time 1.51 seconds
Started Jul 10 05:52:46 PM PDT 24
Finished Jul 10 05:52:49 PM PDT 24
Peak memory 209336 kb
Host smart-d744de0b-246e-4f2b-b68a-aadfdd4a151e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050279795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3050279795
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3949638827
Short name T130
Test name
Test status
Simulation time 81825545 ps
CPU time 2.77 seconds
Started Jul 10 05:52:47 PM PDT 24
Finished Jul 10 05:52:51 PM PDT 24
Peak memory 217596 kb
Host smart-baf410e2-dcfb-4d99-8298-5982a4be5180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949638827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3949638827
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2918275659
Short name T898
Test name
Test status
Simulation time 67415874 ps
CPU time 1.44 seconds
Started Jul 10 05:52:51 PM PDT 24
Finished Jul 10 05:52:53 PM PDT 24
Peak memory 218344 kb
Host smart-8cbb772f-39c0-4983-baec-c5e6879c6eee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918275659 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2918275659
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2894894871
Short name T935
Test name
Test status
Simulation time 12391648 ps
CPU time 1.04 seconds
Started Jul 10 05:52:53 PM PDT 24
Finished Jul 10 05:52:55 PM PDT 24
Peak memory 209180 kb
Host smart-4fbc3d8e-57ee-4f3c-afff-1be44ad3623d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894894871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2894894871
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.130399415
Short name T194
Test name
Test status
Simulation time 35850901 ps
CPU time 1.39 seconds
Started Jul 10 05:52:50 PM PDT 24
Finished Jul 10 05:52:53 PM PDT 24
Peak memory 211260 kb
Host smart-9046d919-d297-44db-9630-e51fc8bee809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130399415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.130399415
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3505120904
Short name T969
Test name
Test status
Simulation time 153322855 ps
CPU time 5.01 seconds
Started Jul 10 05:52:50 PM PDT 24
Finished Jul 10 05:52:56 PM PDT 24
Peak memory 217480 kb
Host smart-13d5f31e-6fa1-4156-a80a-a8b540457015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505120904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3505120904
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1811147948
Short name T926
Test name
Test status
Simulation time 22570087 ps
CPU time 1.38 seconds
Started Jul 10 05:52:49 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 220392 kb
Host smart-05c9c612-67b8-4cf3-97e8-d4e07a997f7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811147948 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1811147948
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1740070645
Short name T187
Test name
Test status
Simulation time 25225916 ps
CPU time 0.9 seconds
Started Jul 10 05:52:50 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 208872 kb
Host smart-b7894256-cdef-4b29-97ef-cec7b0589194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740070645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1740070645
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3070302399
Short name T988
Test name
Test status
Simulation time 32189116 ps
CPU time 1.02 seconds
Started Jul 10 05:52:47 PM PDT 24
Finished Jul 10 05:52:50 PM PDT 24
Peak memory 209336 kb
Host smart-6511d2c7-897d-44bf-b7bd-4f9ea51bb63a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070302399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3070302399
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4253587447
Short name T127
Test name
Test status
Simulation time 157718182 ps
CPU time 3.4 seconds
Started Jul 10 05:52:53 PM PDT 24
Finished Jul 10 05:52:57 PM PDT 24
Peak memory 217804 kb
Host smart-6da1ed40-7941-4c2e-adcc-9d7eb1f95988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253587447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4253587447
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2815033068
Short name T897
Test name
Test status
Simulation time 53875904 ps
CPU time 1.34 seconds
Started Jul 10 05:52:53 PM PDT 24
Finished Jul 10 05:52:55 PM PDT 24
Peak memory 219492 kb
Host smart-72b6d9ca-3e47-4b64-9da3-7b9459192660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815033068 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2815033068
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1059892449
Short name T979
Test name
Test status
Simulation time 44611229 ps
CPU time 0.94 seconds
Started Jul 10 05:52:47 PM PDT 24
Finished Jul 10 05:52:49 PM PDT 24
Peak memory 209332 kb
Host smart-b2371be4-3ef7-4a5d-9b22-58663cd1fc58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059892449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1059892449
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.210323702
Short name T933
Test name
Test status
Simulation time 26017109 ps
CPU time 1.44 seconds
Started Jul 10 05:52:54 PM PDT 24
Finished Jul 10 05:52:57 PM PDT 24
Peak memory 217500 kb
Host smart-b22273c8-4297-4985-bee3-eff8a18b09e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210323702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.210323702
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4277025095
Short name T113
Test name
Test status
Simulation time 85678219 ps
CPU time 3.34 seconds
Started Jul 10 05:52:53 PM PDT 24
Finished Jul 10 05:52:57 PM PDT 24
Peak memory 217436 kb
Host smart-4fb2b416-4d67-4d71-bca6-363a7d9bb8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277025095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4277025095
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1042990243
Short name T132
Test name
Test status
Simulation time 152349644 ps
CPU time 2.87 seconds
Started Jul 10 05:52:48 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 222340 kb
Host smart-71cc9172-190f-4e25-beb9-a4d085c08b01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042990243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1042990243
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3954617214
Short name T912
Test name
Test status
Simulation time 152714694 ps
CPU time 1.3 seconds
Started Jul 10 05:52:54 PM PDT 24
Finished Jul 10 05:52:56 PM PDT 24
Peak memory 218624 kb
Host smart-a794d921-e151-484e-8d6e-ef7a7c8a397c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954617214 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3954617214
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1943486553
Short name T923
Test name
Test status
Simulation time 26038320 ps
CPU time 1.03 seconds
Started Jul 10 05:53:01 PM PDT 24
Finished Jul 10 05:53:06 PM PDT 24
Peak memory 209352 kb
Host smart-23dcb833-2551-4281-9e63-685d107ac737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943486553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1943486553
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3343001827
Short name T936
Test name
Test status
Simulation time 140781539 ps
CPU time 1 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:00 PM PDT 24
Peak memory 208976 kb
Host smart-b840cad2-a99b-4974-b7a1-93ed21481122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343001827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3343001827
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2104245254
Short name T942
Test name
Test status
Simulation time 58599740 ps
CPU time 1.76 seconds
Started Jul 10 05:52:55 PM PDT 24
Finished Jul 10 05:52:59 PM PDT 24
Peak memory 217460 kb
Host smart-0dba043c-5262-4e8b-b82c-1f1efdca51e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104245254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2104245254
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2152470974
Short name T159
Test name
Test status
Simulation time 46793995 ps
CPU time 1.26 seconds
Started Jul 10 05:52:59 PM PDT 24
Finished Jul 10 05:53:04 PM PDT 24
Peak memory 217588 kb
Host smart-945b03ed-62ab-42f6-bed2-b6329d314cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152470974 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2152470974
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4112973981
Short name T915
Test name
Test status
Simulation time 17120745 ps
CPU time 1.21 seconds
Started Jul 10 05:52:55 PM PDT 24
Finished Jul 10 05:52:59 PM PDT 24
Peak memory 209324 kb
Host smart-51263ae4-4a7d-4456-8a49-2fda86ff8d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112973981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4112973981
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2965391007
Short name T152
Test name
Test status
Simulation time 86456007 ps
CPU time 1.78 seconds
Started Jul 10 05:52:57 PM PDT 24
Finished Jul 10 05:53:02 PM PDT 24
Peak memory 211276 kb
Host smart-dac8ee6b-0af0-4d03-967b-3da969b6998f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965391007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2965391007
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4076054366
Short name T982
Test name
Test status
Simulation time 102641790 ps
CPU time 2.35 seconds
Started Jul 10 05:52:55 PM PDT 24
Finished Jul 10 05:53:00 PM PDT 24
Peak memory 217480 kb
Host smart-9186deb5-fdb5-40da-9920-cae03f92ffd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076054366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4076054366
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2567285599
Short name T124
Test name
Test status
Simulation time 21817622 ps
CPU time 1.58 seconds
Started Jul 10 05:52:53 PM PDT 24
Finished Jul 10 05:52:56 PM PDT 24
Peak memory 219364 kb
Host smart-2caddd19-afed-43ff-8af5-ad8f3e86d0ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567285599 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2567285599
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2745827230
Short name T948
Test name
Test status
Simulation time 22393804 ps
CPU time 0.88 seconds
Started Jul 10 05:52:54 PM PDT 24
Finished Jul 10 05:52:57 PM PDT 24
Peak memory 209264 kb
Host smart-9cffaead-465e-494e-ae62-d56d19d07e79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745827230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2745827230
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.94110236
Short name T985
Test name
Test status
Simulation time 45073420 ps
CPU time 1.07 seconds
Started Jul 10 05:52:55 PM PDT 24
Finished Jul 10 05:52:58 PM PDT 24
Peak memory 209336 kb
Host smart-6a16b1cf-bd48-439a-9b62-1b7a2891283c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94110236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
same_csr_outstanding.94110236
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3237777785
Short name T950
Test name
Test status
Simulation time 59927664 ps
CPU time 3.33 seconds
Started Jul 10 05:52:53 PM PDT 24
Finished Jul 10 05:52:58 PM PDT 24
Peak memory 218500 kb
Host smart-a68fee7a-6d5c-42af-8765-56d453412a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237777785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3237777785
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3395493701
Short name T141
Test name
Test status
Simulation time 330200413 ps
CPU time 2.73 seconds
Started Jul 10 05:52:54 PM PDT 24
Finished Jul 10 05:52:59 PM PDT 24
Peak memory 222332 kb
Host smart-310f78fa-e356-4b2e-b7b3-c4d25339da12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395493701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3395493701
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.914385063
Short name T160
Test name
Test status
Simulation time 18921813 ps
CPU time 1.18 seconds
Started Jul 10 05:52:58 PM PDT 24
Finished Jul 10 05:53:03 PM PDT 24
Peak memory 217724 kb
Host smart-dd3e730c-7ab1-4537-8d56-fbb8d97797b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914385063 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.914385063
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1929610830
Short name T190
Test name
Test status
Simulation time 14574042 ps
CPU time 1.06 seconds
Started Jul 10 05:52:53 PM PDT 24
Finished Jul 10 05:52:56 PM PDT 24
Peak memory 209332 kb
Host smart-3150301e-6d0a-4c8c-ab62-bdbc0c3734cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929610830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1929610830
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.834648384
Short name T917
Test name
Test status
Simulation time 46878246 ps
CPU time 1.05 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:00 PM PDT 24
Peak memory 209304 kb
Host smart-75afc7f7-879b-4409-a74e-371cb06e2e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834648384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.834648384
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.813585262
Short name T156
Test name
Test status
Simulation time 1039137022 ps
CPU time 3.68 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:02 PM PDT 24
Peak memory 217480 kb
Host smart-022cd6dc-d694-4438-9f9a-31d88bbdbd80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813585262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.813585262
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1120729184
Short name T133
Test name
Test status
Simulation time 115277925 ps
CPU time 3.01 seconds
Started Jul 10 05:52:52 PM PDT 24
Finished Jul 10 05:52:56 PM PDT 24
Peak memory 217648 kb
Host smart-f260a85e-db26-462f-bb19-58f24a8d4108
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120729184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1120729184
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.817148819
Short name T986
Test name
Test status
Simulation time 35616949 ps
CPU time 1.18 seconds
Started Jul 10 05:52:19 PM PDT 24
Finished Jul 10 05:52:24 PM PDT 24
Peak memory 209304 kb
Host smart-4e17b228-ef73-4dce-bd79-02397531f329
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817148819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.817148819
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.653319648
Short name T902
Test name
Test status
Simulation time 20504744 ps
CPU time 1.2 seconds
Started Jul 10 05:52:25 PM PDT 24
Finished Jul 10 05:52:28 PM PDT 24
Peak memory 209128 kb
Host smart-90cca7d2-0328-40f1-a131-7fe1a6aba61b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653319648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.653319648
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4276295441
Short name T182
Test name
Test status
Simulation time 22048467 ps
CPU time 1.17 seconds
Started Jul 10 05:52:24 PM PDT 24
Finished Jul 10 05:52:27 PM PDT 24
Peak memory 217864 kb
Host smart-fa277c89-bb7c-4a6b-9260-66f024716b44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276295441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.4276295441
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.704183100
Short name T157
Test name
Test status
Simulation time 41635939 ps
CPU time 1.42 seconds
Started Jul 10 05:52:15 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 220936 kb
Host smart-493e57ec-d6a3-4c4c-9f82-f420b9473d33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704183100 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.704183100
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4160069660
Short name T901
Test name
Test status
Simulation time 14136082 ps
CPU time 0.84 seconds
Started Jul 10 05:52:26 PM PDT 24
Finished Jul 10 05:52:29 PM PDT 24
Peak memory 208652 kb
Host smart-7edf811c-66a8-40d8-9fa9-a1fbfc88e070
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160069660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4160069660
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2428006907
Short name T924
Test name
Test status
Simulation time 110869047 ps
CPU time 1.32 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 208636 kb
Host smart-db022e02-0946-4a35-b821-a13ab4ba9217
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428006907 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2428006907
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.912314688
Short name T868
Test name
Test status
Simulation time 2011092097 ps
CPU time 4.68 seconds
Started Jul 10 05:52:17 PM PDT 24
Finished Jul 10 05:52:26 PM PDT 24
Peak memory 217032 kb
Host smart-57e9bbe2-5fe8-4d7b-949f-b1a4a3e353cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912314688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.912314688
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1045759768
Short name T920
Test name
Test status
Simulation time 4854540408 ps
CPU time 12.83 seconds
Started Jul 10 05:52:15 PM PDT 24
Finished Jul 10 05:52:32 PM PDT 24
Peak memory 217384 kb
Host smart-f039a8eb-4206-4659-a6c8-db2d4e5088a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045759768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1045759768
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.213329653
Short name T117
Test name
Test status
Simulation time 321307435 ps
CPU time 1.81 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:22 PM PDT 24
Peak memory 218616 kb
Host smart-ac5657a8-52df-46b2-81b7-2efc40b18c1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213329
653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.213329653
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3771788611
Short name T146
Test name
Test status
Simulation time 62060459 ps
CPU time 1.68 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 209252 kb
Host smart-1fa3ebaa-9d56-42aa-8bd8-01a2884cb250
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771788611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3771788611
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.10702830
Short name T894
Test name
Test status
Simulation time 41307995 ps
CPU time 1.53 seconds
Started Jul 10 05:52:15 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 217504 kb
Host smart-03831bf2-eea4-463e-b042-c1aeaa6f0cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702830 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.10702830
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3957942778
Short name T153
Test name
Test status
Simulation time 106363425 ps
CPU time 1.94 seconds
Started Jul 10 05:52:17 PM PDT 24
Finished Jul 10 05:52:23 PM PDT 24
Peak memory 209336 kb
Host smart-0b3cfd64-b3a2-4db6-9245-3535b07a45e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957942778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3957942778
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4045091392
Short name T918
Test name
Test status
Simulation time 74983851 ps
CPU time 3.21 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:23 PM PDT 24
Peak memory 217416 kb
Host smart-0f56c475-945e-45d4-a7eb-9d7b589e38c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045091392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.4045091392
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2917380134
Short name T186
Test name
Test status
Simulation time 279809068 ps
CPU time 1.55 seconds
Started Jul 10 05:52:21 PM PDT 24
Finished Jul 10 05:52:25 PM PDT 24
Peak memory 209336 kb
Host smart-d62511bd-1efd-49d6-b7d5-08c99551d343
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917380134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2917380134
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2280547258
Short name T879
Test name
Test status
Simulation time 61831309 ps
CPU time 1.16 seconds
Started Jul 10 05:52:25 PM PDT 24
Finished Jul 10 05:52:27 PM PDT 24
Peak memory 209332 kb
Host smart-009a0b2a-bf0d-43bc-b091-78032f428b78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280547258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2280547258
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.501081542
Short name T927
Test name
Test status
Simulation time 17705082 ps
CPU time 1.28 seconds
Started Jul 10 05:52:21 PM PDT 24
Finished Jul 10 05:52:25 PM PDT 24
Peak memory 219144 kb
Host smart-26c4204c-4411-429f-b9b4-36574a70b338
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501081542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.501081542
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3195776290
Short name T961
Test name
Test status
Simulation time 22183210 ps
CPU time 1.2 seconds
Started Jul 10 05:52:19 PM PDT 24
Finished Jul 10 05:52:24 PM PDT 24
Peak memory 217572 kb
Host smart-e0adddb3-5477-4a0f-be8b-156b1e2f0ea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195776290 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3195776290
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3329165549
Short name T945
Test name
Test status
Simulation time 24760716 ps
CPU time 0.84 seconds
Started Jul 10 05:52:26 PM PDT 24
Finished Jul 10 05:52:29 PM PDT 24
Peak memory 209268 kb
Host smart-1c3b6498-acdb-4afb-9e12-c8b9d53183f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329165549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3329165549
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2935790795
Short name T922
Test name
Test status
Simulation time 198510106 ps
CPU time 1.15 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:21 PM PDT 24
Peak memory 209164 kb
Host smart-923dcc85-4f10-4f25-ab20-15c5a46493b4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935790795 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2935790795
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2259613582
Short name T956
Test name
Test status
Simulation time 3493265187 ps
CPU time 3.4 seconds
Started Jul 10 05:52:25 PM PDT 24
Finished Jul 10 05:52:30 PM PDT 24
Peak memory 209288 kb
Host smart-976a491b-9f4f-4ac6-813a-ec480b1c97ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259613582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2259613582
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.53324720
Short name T913
Test name
Test status
Simulation time 2659456934 ps
CPU time 6.53 seconds
Started Jul 10 05:52:15 PM PDT 24
Finished Jul 10 05:52:26 PM PDT 24
Peak memory 209416 kb
Host smart-98d5fb09-2874-4035-97e0-8c801619a0a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53324720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.53324720
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.251714637
Short name T144
Test name
Test status
Simulation time 369887491 ps
CPU time 2.9 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:23 PM PDT 24
Peak memory 217468 kb
Host smart-c7330b09-e3f2-4b1b-ad8f-db81e355f459
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251714637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.251714637
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1559948922
Short name T877
Test name
Test status
Simulation time 149385476 ps
CPU time 2.51 seconds
Started Jul 10 05:52:18 PM PDT 24
Finished Jul 10 05:52:25 PM PDT 24
Peak memory 217740 kb
Host smart-1a3aa8dd-4d3f-4b23-9dda-b634b327c2c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155994
8922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1559948922
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1740008577
Short name T909
Test name
Test status
Simulation time 664580366 ps
CPU time 1.38 seconds
Started Jul 10 05:52:28 PM PDT 24
Finished Jul 10 05:52:31 PM PDT 24
Peak memory 217400 kb
Host smart-4e22795f-0746-4e30-882a-d4104a1bc894
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740008577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1740008577
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4059210992
Short name T195
Test name
Test status
Simulation time 15807180 ps
CPU time 1.08 seconds
Started Jul 10 05:52:17 PM PDT 24
Finished Jul 10 05:52:22 PM PDT 24
Peak memory 217560 kb
Host smart-96aacd40-e694-4680-bd70-f2838ce14418
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059210992 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.4059210992
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.831361557
Short name T977
Test name
Test status
Simulation time 76834891 ps
CPU time 1.51 seconds
Started Jul 10 05:52:20 PM PDT 24
Finished Jul 10 05:52:25 PM PDT 24
Peak memory 211372 kb
Host smart-0267c224-98de-4ca8-a6e6-048fdcbda4dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831361557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.831361557
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3664788946
Short name T963
Test name
Test status
Simulation time 44587815 ps
CPU time 3.5 seconds
Started Jul 10 05:52:27 PM PDT 24
Finished Jul 10 05:52:32 PM PDT 24
Peak memory 217568 kb
Host smart-bc29674f-bbad-4cf9-b1b8-2f06e230dd82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664788946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3664788946
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1781959826
Short name T125
Test name
Test status
Simulation time 238574517 ps
CPU time 4.03 seconds
Started Jul 10 05:52:16 PM PDT 24
Finished Jul 10 05:52:24 PM PDT 24
Peak memory 217652 kb
Host smart-8b61f1a1-9b92-4ca4-9fa3-9be1d33ac2a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781959826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1781959826
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4129240511
Short name T873
Test name
Test status
Simulation time 16953125 ps
CPU time 1 seconds
Started Jul 10 05:52:29 PM PDT 24
Finished Jul 10 05:52:32 PM PDT 24
Peak memory 209336 kb
Host smart-27c5ff9d-8099-4929-b412-946793ba30de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129240511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4129240511
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1621543934
Short name T930
Test name
Test status
Simulation time 65271950 ps
CPU time 2.71 seconds
Started Jul 10 05:52:35 PM PDT 24
Finished Jul 10 05:52:38 PM PDT 24
Peak memory 217292 kb
Host smart-6d2f35c2-7b28-451e-aa1c-17b85cfa796f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621543934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1621543934
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1213040885
Short name T888
Test name
Test status
Simulation time 16049097 ps
CPU time 1.15 seconds
Started Jul 10 05:52:26 PM PDT 24
Finished Jul 10 05:52:29 PM PDT 24
Peak memory 209736 kb
Host smart-da7721b7-d485-4030-9f85-757a64894451
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213040885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1213040885
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3001552270
Short name T914
Test name
Test status
Simulation time 231958546 ps
CPU time 1.13 seconds
Started Jul 10 05:52:35 PM PDT 24
Finished Jul 10 05:52:38 PM PDT 24
Peak memory 217708 kb
Host smart-fed4415e-6b59-474e-9ca8-ea79b03e2996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001552270 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3001552270
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.561512323
Short name T882
Test name
Test status
Simulation time 49497868 ps
CPU time 1.06 seconds
Started Jul 10 05:52:26 PM PDT 24
Finished Jul 10 05:52:28 PM PDT 24
Peak memory 209332 kb
Host smart-4e417662-fe64-419a-ae34-4d9e8f780df9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561512323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.561512323
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.996885580
Short name T869
Test name
Test status
Simulation time 167119627 ps
CPU time 1.82 seconds
Started Jul 10 05:52:31 PM PDT 24
Finished Jul 10 05:52:34 PM PDT 24
Peak memory 208776 kb
Host smart-10b96e99-2858-4ed4-b6aa-f97e1912a0c4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996885580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.996885580
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.78427749
Short name T955
Test name
Test status
Simulation time 226923999 ps
CPU time 2.9 seconds
Started Jul 10 05:52:22 PM PDT 24
Finished Jul 10 05:52:27 PM PDT 24
Peak memory 208980 kb
Host smart-37875adf-bea8-40eb-ab24-d8c906433177
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78427749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.lc_ctrl_jtag_csr_aliasing.78427749
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.931285901
Short name T965
Test name
Test status
Simulation time 833028402 ps
CPU time 7.85 seconds
Started Jul 10 05:52:19 PM PDT 24
Finished Jul 10 05:52:31 PM PDT 24
Peak memory 216964 kb
Host smart-3843823a-490b-476a-abd9-eab5a35eb759
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931285901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.931285901
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.7996739
Short name T878
Test name
Test status
Simulation time 1071938338 ps
CPU time 1.37 seconds
Started Jul 10 05:52:26 PM PDT 24
Finished Jul 10 05:52:29 PM PDT 24
Peak memory 210696 kb
Host smart-3323fa84-af42-4879-ba68-c0d0efcb3c74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7996739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base
_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.lc_ctrl_jtag_csr_hw_reset.7996739
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3467819288
Short name T962
Test name
Test status
Simulation time 745472054 ps
CPU time 5.1 seconds
Started Jul 10 05:52:19 PM PDT 24
Finished Jul 10 05:52:28 PM PDT 24
Peak memory 217780 kb
Host smart-b3ba6102-8095-4897-993e-9e828a835426
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346781
9288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3467819288
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3371179513
Short name T947
Test name
Test status
Simulation time 401978844 ps
CPU time 2.33 seconds
Started Jul 10 05:52:27 PM PDT 24
Finished Jul 10 05:52:30 PM PDT 24
Peak memory 217448 kb
Host smart-10e6e945-5018-4c81-af7a-27a0db9292cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371179513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3371179513
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1793803574
Short name T895
Test name
Test status
Simulation time 271222845 ps
CPU time 1.96 seconds
Started Jul 10 05:52:19 PM PDT 24
Finished Jul 10 05:52:25 PM PDT 24
Peak memory 211344 kb
Host smart-b50b843d-3a2e-4693-bd8a-8786da78d8bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793803574 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1793803574
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1891933406
Short name T899
Test name
Test status
Simulation time 195478290 ps
CPU time 1.98 seconds
Started Jul 10 05:52:36 PM PDT 24
Finished Jul 10 05:52:39 PM PDT 24
Peak memory 211292 kb
Host smart-d25e26ec-540f-45af-a1e3-ed424e15e771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891933406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1891933406
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3633669454
Short name T941
Test name
Test status
Simulation time 579985209 ps
CPU time 5.9 seconds
Started Jul 10 05:52:29 PM PDT 24
Finished Jul 10 05:52:36 PM PDT 24
Peak memory 217480 kb
Host smart-a243e749-3132-4820-9f23-744e18ad4787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633669454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3633669454
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1891332734
Short name T973
Test name
Test status
Simulation time 605999713 ps
CPU time 3.93 seconds
Started Jul 10 05:52:25 PM PDT 24
Finished Jul 10 05:52:30 PM PDT 24
Peak memory 217536 kb
Host smart-d2fdf3f3-26a3-46f9-9d20-d0fd892959b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891332734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1891332734
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3102203415
Short name T967
Test name
Test status
Simulation time 31421288 ps
CPU time 2.14 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:01 PM PDT 24
Peak memory 219152 kb
Host smart-96fc7954-bc92-434a-9979-8c00811f295e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102203415 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3102203415
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4178940273
Short name T185
Test name
Test status
Simulation time 32163489 ps
CPU time 0.93 seconds
Started Jul 10 05:52:38 PM PDT 24
Finished Jul 10 05:52:41 PM PDT 24
Peak memory 208624 kb
Host smart-86a7553a-59a2-4df3-af22-53f1a2beedd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178940273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.4178940273
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1542824730
Short name T905
Test name
Test status
Simulation time 82700656 ps
CPU time 1.95 seconds
Started Jul 10 05:52:39 PM PDT 24
Finished Jul 10 05:52:42 PM PDT 24
Peak memory 209172 kb
Host smart-77816262-d9d1-4160-b488-edd086504435
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542824730 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1542824730
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1902420329
Short name T143
Test name
Test status
Simulation time 1239585212 ps
CPU time 26.68 seconds
Started Jul 10 05:52:44 PM PDT 24
Finished Jul 10 05:53:12 PM PDT 24
Peak memory 209252 kb
Host smart-c877fb22-89ad-4873-976f-6e57478dcc22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902420329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1902420329
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1704597985
Short name T866
Test name
Test status
Simulation time 1790547419 ps
CPU time 20.59 seconds
Started Jul 10 05:52:39 PM PDT 24
Finished Jul 10 05:53:01 PM PDT 24
Peak memory 209008 kb
Host smart-e820b21a-ab73-44d2-a249-f05185dbe0f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704597985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1704597985
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4158108951
Short name T893
Test name
Test status
Simulation time 487060945 ps
CPU time 1.84 seconds
Started Jul 10 05:52:37 PM PDT 24
Finished Jul 10 05:52:40 PM PDT 24
Peak memory 210900 kb
Host smart-191b1460-ae48-444e-975a-8d1b9ebe3ae2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158108951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4158108951
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3246882508
Short name T115
Test name
Test status
Simulation time 1515076435 ps
CPU time 2.92 seconds
Started Jul 10 05:52:35 PM PDT 24
Finished Jul 10 05:52:39 PM PDT 24
Peak memory 221328 kb
Host smart-dca95bc8-7013-4c5a-ab68-b93d37514885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324688
2508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3246882508
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3153829891
Short name T876
Test name
Test status
Simulation time 295159871 ps
CPU time 2.62 seconds
Started Jul 10 05:52:37 PM PDT 24
Finished Jul 10 05:52:41 PM PDT 24
Peak memory 209260 kb
Host smart-8cfbb250-21be-4199-8b76-8f928ed2239d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153829891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3153829891
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.929819917
Short name T954
Test name
Test status
Simulation time 130985162 ps
CPU time 1.03 seconds
Started Jul 10 05:52:37 PM PDT 24
Finished Jul 10 05:52:40 PM PDT 24
Peak memory 209360 kb
Host smart-fef31f34-b332-48b2-9acb-bfdde6824eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929819917 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.929819917
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2287746221
Short name T952
Test name
Test status
Simulation time 27508786 ps
CPU time 1.26 seconds
Started Jul 10 05:52:38 PM PDT 24
Finished Jul 10 05:52:41 PM PDT 24
Peak memory 209416 kb
Host smart-501855bc-38fb-4cef-9efb-d79200f374b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287746221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2287746221
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3482512901
Short name T980
Test name
Test status
Simulation time 698259052 ps
CPU time 2.19 seconds
Started Jul 10 05:52:36 PM PDT 24
Finished Jul 10 05:52:39 PM PDT 24
Peak memory 217468 kb
Host smart-1ba49065-ae20-41a4-85cc-385d8c1cba71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482512901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3482512901
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3725671083
Short name T964
Test name
Test status
Simulation time 64345044 ps
CPU time 1.44 seconds
Started Jul 10 05:52:38 PM PDT 24
Finished Jul 10 05:52:40 PM PDT 24
Peak memory 219228 kb
Host smart-82132c29-07e5-4b47-a9c5-480a4f228212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725671083 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3725671083
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1435254010
Short name T946
Test name
Test status
Simulation time 12546292 ps
CPU time 0.88 seconds
Started Jul 10 05:52:38 PM PDT 24
Finished Jul 10 05:52:40 PM PDT 24
Peak memory 209428 kb
Host smart-fd937473-7d32-4626-ad0a-e4346f91190c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435254010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1435254010
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2791056014
Short name T872
Test name
Test status
Simulation time 129259998 ps
CPU time 1.56 seconds
Started Jul 10 05:52:39 PM PDT 24
Finished Jul 10 05:52:42 PM PDT 24
Peak memory 209152 kb
Host smart-26e1598a-5976-4b36-8f6a-78ba552ee3a0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791056014 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2791056014
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3503191508
Short name T987
Test name
Test status
Simulation time 1821154011 ps
CPU time 11.82 seconds
Started Jul 10 05:52:41 PM PDT 24
Finished Jul 10 05:52:54 PM PDT 24
Peak memory 217244 kb
Host smart-27248d77-a567-4002-b855-0dc753bf7f30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503191508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3503191508
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.312327910
Short name T944
Test name
Test status
Simulation time 37524611444 ps
CPU time 17.67 seconds
Started Jul 10 05:52:38 PM PDT 24
Finished Jul 10 05:52:57 PM PDT 24
Peak memory 209388 kb
Host smart-fe1b926e-6582-49c5-8ba3-2a7f73d1f5e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312327910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.312327910
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1791588210
Short name T885
Test name
Test status
Simulation time 634981374 ps
CPU time 4.33 seconds
Started Jul 10 05:52:36 PM PDT 24
Finished Jul 10 05:52:42 PM PDT 24
Peak memory 210936 kb
Host smart-9193c513-123d-4908-86c4-f1d9283c6fc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791588210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1791588210
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2649700920
Short name T871
Test name
Test status
Simulation time 50143229 ps
CPU time 1.57 seconds
Started Jul 10 05:52:37 PM PDT 24
Finished Jul 10 05:52:39 PM PDT 24
Peak memory 218788 kb
Host smart-a69b88c4-d6f2-44e3-8b31-7bdfd9cd58a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264970
0920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2649700920
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.169305383
Short name T919
Test name
Test status
Simulation time 96989488 ps
CPU time 2.77 seconds
Started Jul 10 05:52:40 PM PDT 24
Finished Jul 10 05:52:44 PM PDT 24
Peak memory 209244 kb
Host smart-498c40d8-4c8d-428c-906d-cc762495907d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169305383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.169305383
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3684042499
Short name T984
Test name
Test status
Simulation time 157424476 ps
CPU time 1.42 seconds
Started Jul 10 05:52:36 PM PDT 24
Finished Jul 10 05:52:38 PM PDT 24
Peak memory 209544 kb
Host smart-9933d257-6749-47c9-affc-f80652e15c1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684042499 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3684042499
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2566960293
Short name T191
Test name
Test status
Simulation time 76890724 ps
CPU time 1.28 seconds
Started Jul 10 05:52:39 PM PDT 24
Finished Jul 10 05:52:42 PM PDT 24
Peak memory 209308 kb
Host smart-72d2154f-3100-45e2-a729-16003a4a0cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566960293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2566960293
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3443119242
Short name T907
Test name
Test status
Simulation time 900696184 ps
CPU time 3.61 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:02 PM PDT 24
Peak memory 217468 kb
Host smart-5c699fec-bab8-4afb-9de4-82f625410b27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443119242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3443119242
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3870395621
Short name T138
Test name
Test status
Simulation time 112566968 ps
CPU time 4.06 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:48 PM PDT 24
Peak memory 217536 kb
Host smart-3354fa3b-bff4-435b-9ac7-091f4a44f35c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870395621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3870395621
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2654348029
Short name T904
Test name
Test status
Simulation time 36017363 ps
CPU time 1.4 seconds
Started Jul 10 05:52:47 PM PDT 24
Finished Jul 10 05:52:50 PM PDT 24
Peak memory 222824 kb
Host smart-8e182080-2e46-46c5-b1f2-605ab8ebcbec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654348029 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2654348029
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2407365064
Short name T121
Test name
Test status
Simulation time 14845314 ps
CPU time 0.91 seconds
Started Jul 10 05:52:41 PM PDT 24
Finished Jul 10 05:52:44 PM PDT 24
Peak memory 209268 kb
Host smart-bf30281b-9364-4463-a36f-b8e4211dfd4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407365064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2407365064
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2945463209
Short name T896
Test name
Test status
Simulation time 172478684 ps
CPU time 4.05 seconds
Started Jul 10 05:52:41 PM PDT 24
Finished Jul 10 05:52:46 PM PDT 24
Peak memory 208748 kb
Host smart-60ebfd14-81e7-4b8a-a4be-3f59ab02fe25
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945463209 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2945463209
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2773666955
Short name T906
Test name
Test status
Simulation time 2394624830 ps
CPU time 10.5 seconds
Started Jul 10 05:52:41 PM PDT 24
Finished Jul 10 05:52:52 PM PDT 24
Peak memory 217384 kb
Host smart-dffa5340-7c70-4e85-992c-7a1fc55d6580
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773666955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2773666955
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.758421695
Short name T939
Test name
Test status
Simulation time 4272748232 ps
CPU time 12.48 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:11 PM PDT 24
Peak memory 209336 kb
Host smart-fcd09199-7946-444e-a921-3240553e9bc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758421695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.758421695
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.942935080
Short name T867
Test name
Test status
Simulation time 178119909 ps
CPU time 1.63 seconds
Started Jul 10 05:52:44 PM PDT 24
Finished Jul 10 05:52:48 PM PDT 24
Peak memory 217460 kb
Host smart-8f5a6b1c-f368-432f-b933-0c26ee3a31a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942935080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.942935080
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3923310214
Short name T981
Test name
Test status
Simulation time 94141221 ps
CPU time 1.36 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:46 PM PDT 24
Peak memory 217676 kb
Host smart-6c6509f4-1ad1-4dec-af21-2c3c667bb07b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392331
0214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3923310214
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3982854962
Short name T889
Test name
Test status
Simulation time 108295165 ps
CPU time 3.17 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:02 PM PDT 24
Peak memory 209260 kb
Host smart-94345dc8-541b-4f2f-adbd-96708c07f129
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982854962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3982854962
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3006845811
Short name T943
Test name
Test status
Simulation time 19951006 ps
CPU time 1.3 seconds
Started Jul 10 05:52:41 PM PDT 24
Finished Jul 10 05:52:44 PM PDT 24
Peak memory 217540 kb
Host smart-1f275a50-ab27-4c85-adee-ee73a3c7d311
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006845811 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3006845811
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3075191167
Short name T122
Test name
Test status
Simulation time 95830897 ps
CPU time 1.37 seconds
Started Jul 10 05:52:51 PM PDT 24
Finished Jul 10 05:52:54 PM PDT 24
Peak memory 209428 kb
Host smart-64bca9a6-80b0-4de3-b3ef-94d2b1182b6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075191167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3075191167
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1466871873
Short name T911
Test name
Test status
Simulation time 28931280 ps
CPU time 2.1 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:46 PM PDT 24
Peak memory 217512 kb
Host smart-b9426555-994b-4a2c-82a7-839a7f659153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466871873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1466871873
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1250359431
Short name T129
Test name
Test status
Simulation time 297617500 ps
CPU time 2.8 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:46 PM PDT 24
Peak memory 222484 kb
Host smart-7f733595-6349-4cdb-a20c-9f8969255e16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250359431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1250359431
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1034114713
Short name T880
Test name
Test status
Simulation time 20439116 ps
CPU time 1.57 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:46 PM PDT 24
Peak memory 219196 kb
Host smart-85ba8dc8-c03a-4744-8252-294efde8931e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034114713 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1034114713
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1997235732
Short name T181
Test name
Test status
Simulation time 37306530 ps
CPU time 0.97 seconds
Started Jul 10 05:52:47 PM PDT 24
Finished Jul 10 05:52:50 PM PDT 24
Peak memory 209336 kb
Host smart-e486fbe7-bb70-4aec-ad22-8f2a3747d7a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997235732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1997235732
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3301605974
Short name T937
Test name
Test status
Simulation time 648433754 ps
CPU time 2.02 seconds
Started Jul 10 05:52:44 PM PDT 24
Finished Jul 10 05:52:47 PM PDT 24
Peak memory 209180 kb
Host smart-676fc20a-ce8f-47d1-8958-ebc47d3639dd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301605974 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3301605974
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3480795559
Short name T953
Test name
Test status
Simulation time 372801410 ps
CPU time 9.34 seconds
Started Jul 10 05:52:45 PM PDT 24
Finished Jul 10 05:52:56 PM PDT 24
Peak memory 217280 kb
Host smart-cfd0ef68-353a-49ae-9fc8-6501db59eb44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480795559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3480795559
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3934039318
Short name T971
Test name
Test status
Simulation time 1246760858 ps
CPU time 14.66 seconds
Started Jul 10 05:52:46 PM PDT 24
Finished Jul 10 05:53:02 PM PDT 24
Peak memory 209428 kb
Host smart-cf7b9977-e2b3-4ebd-af49-200574cdcdd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934039318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3934039318
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2097026003
Short name T921
Test name
Test status
Simulation time 175583541 ps
CPU time 2 seconds
Started Jul 10 05:52:44 PM PDT 24
Finished Jul 10 05:52:47 PM PDT 24
Peak memory 217440 kb
Host smart-fe76412c-3f78-40fd-900f-4f859d81e8f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097026003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2097026003
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3378225624
Short name T891
Test name
Test status
Simulation time 359310991 ps
CPU time 5.02 seconds
Started Jul 10 05:52:51 PM PDT 24
Finished Jul 10 05:52:58 PM PDT 24
Peak memory 218260 kb
Host smart-03434f0d-e6c0-4036-b460-f1633c05df03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337822
5624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3378225624
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2555743173
Short name T883
Test name
Test status
Simulation time 84454723 ps
CPU time 1.56 seconds
Started Jul 10 05:52:44 PM PDT 24
Finished Jul 10 05:52:47 PM PDT 24
Peak memory 217316 kb
Host smart-00f21bb0-353e-4228-9e20-f069ab372456
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555743173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2555743173
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.681630265
Short name T929
Test name
Test status
Simulation time 37707709 ps
CPU time 1.94 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:46 PM PDT 24
Peak memory 217528 kb
Host smart-2c64d1ad-7c04-4e74-b041-465bf1742d6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681630265 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.681630265
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4230165470
Short name T892
Test name
Test status
Simulation time 82557745 ps
CPU time 1.09 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:00 PM PDT 24
Peak memory 209244 kb
Host smart-763dfae0-a615-4658-9a3d-0dedfe504643
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230165470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4230165470
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3542718387
Short name T910
Test name
Test status
Simulation time 26715485 ps
CPU time 1.93 seconds
Started Jul 10 05:52:48 PM PDT 24
Finished Jul 10 05:52:51 PM PDT 24
Peak memory 218668 kb
Host smart-cb0f9c94-87f8-49b3-b63b-d84a7193a45a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542718387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3542718387
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3815026801
Short name T959
Test name
Test status
Simulation time 18245061 ps
CPU time 1.26 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:45 PM PDT 24
Peak memory 217516 kb
Host smart-88b9f0e7-d508-43ff-9fe8-ce4b42f23ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815026801 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3815026801
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.775549912
Short name T184
Test name
Test status
Simulation time 42669231 ps
CPU time 0.86 seconds
Started Jul 10 05:52:51 PM PDT 24
Finished Jul 10 05:52:53 PM PDT 24
Peak memory 209156 kb
Host smart-e8f46fb6-33bc-4912-8897-9ff5530dd758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775549912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.775549912
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2396336031
Short name T874
Test name
Test status
Simulation time 46501520 ps
CPU time 1.2 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:45 PM PDT 24
Peak memory 208752 kb
Host smart-6bc20081-14e5-4948-b842-66e927af170a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396336031 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2396336031
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2495606732
Short name T978
Test name
Test status
Simulation time 2802803934 ps
CPU time 2.83 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:01 PM PDT 24
Peak memory 209384 kb
Host smart-e65f9c12-df84-4208-a7ab-f690b63d0c96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495606732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2495606732
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1599436994
Short name T976
Test name
Test status
Simulation time 1814032870 ps
CPU time 11.8 seconds
Started Jul 10 05:52:40 PM PDT 24
Finished Jul 10 05:52:54 PM PDT 24
Peak memory 209224 kb
Host smart-76f36d90-a107-40d2-8638-40c4cbe72534
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599436994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1599436994
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.201966482
Short name T881
Test name
Test status
Simulation time 1405728411 ps
CPU time 3.75 seconds
Started Jul 10 05:52:56 PM PDT 24
Finished Jul 10 05:53:02 PM PDT 24
Peak memory 217460 kb
Host smart-a9deb381-58b6-469d-b91c-c33c890954de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201966482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.201966482
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2292605770
Short name T928
Test name
Test status
Simulation time 51339464 ps
CPU time 1.44 seconds
Started Jul 10 05:52:51 PM PDT 24
Finished Jul 10 05:52:54 PM PDT 24
Peak memory 217632 kb
Host smart-02ec995e-3fe1-482b-a0fb-cd9ac323e33a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229260
5770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2292605770
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2862336993
Short name T960
Test name
Test status
Simulation time 64735898 ps
CPU time 1.32 seconds
Started Jul 10 05:52:43 PM PDT 24
Finished Jul 10 05:52:46 PM PDT 24
Peak memory 209268 kb
Host smart-98665953-2892-4ced-b61d-f87ba4c4e30f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862336993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2862336993
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1220560850
Short name T193
Test name
Test status
Simulation time 27763153 ps
CPU time 1 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:45 PM PDT 24
Peak memory 209368 kb
Host smart-babdaebc-6759-4929-bca1-8e25ac261bc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220560850 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1220560850
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1670265935
Short name T890
Test name
Test status
Simulation time 70849405 ps
CPU time 1.44 seconds
Started Jul 10 05:52:41 PM PDT 24
Finished Jul 10 05:52:44 PM PDT 24
Peak memory 209336 kb
Host smart-54334234-1fe9-4e98-baf4-e658fdd91a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670265935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1670265935
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3168219677
Short name T887
Test name
Test status
Simulation time 340611367 ps
CPU time 3.51 seconds
Started Jul 10 05:52:43 PM PDT 24
Finished Jul 10 05:52:49 PM PDT 24
Peak memory 217804 kb
Host smart-b5ec991c-761b-4e3c-9cd5-a81408f59c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168219677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3168219677
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3870327610
Short name T140
Test name
Test status
Simulation time 838709090 ps
CPU time 4.76 seconds
Started Jul 10 05:52:42 PM PDT 24
Finished Jul 10 05:52:49 PM PDT 24
Peak memory 217592 kb
Host smart-72d84f79-8abb-497e-ba82-70f8a242868e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870327610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3870327610
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3103246810
Short name T410
Test name
Test status
Simulation time 47771052 ps
CPU time 1.08 seconds
Started Jul 10 06:55:39 PM PDT 24
Finished Jul 10 06:55:41 PM PDT 24
Peak memory 208984 kb
Host smart-c389bb6f-3bff-43f6-ad06-2a261e966ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103246810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3103246810
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3048196993
Short name T389
Test name
Test status
Simulation time 221488127 ps
CPU time 8.99 seconds
Started Jul 10 06:55:11 PM PDT 24
Finished Jul 10 06:55:20 PM PDT 24
Peak memory 218228 kb
Host smart-51986413-a124-44dc-b268-741a3454a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048196993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3048196993
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2996799438
Short name T35
Test name
Test status
Simulation time 363968926 ps
CPU time 10.41 seconds
Started Jul 10 06:55:22 PM PDT 24
Finished Jul 10 06:55:33 PM PDT 24
Peak memory 217196 kb
Host smart-254a0d60-8ecc-4ec9-842a-620eb0a22217
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996799438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2996799438
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3959612561
Short name T381
Test name
Test status
Simulation time 10035365595 ps
CPU time 39.27 seconds
Started Jul 10 06:55:21 PM PDT 24
Finished Jul 10 06:56:02 PM PDT 24
Peak memory 218868 kb
Host smart-5ec73f96-e15c-42f7-ad77-b6621aa195ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959612561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3959612561
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.973535603
Short name T65
Test name
Test status
Simulation time 1029207926 ps
CPU time 7.15 seconds
Started Jul 10 06:55:31 PM PDT 24
Finished Jul 10 06:55:39 PM PDT 24
Peak memory 217620 kb
Host smart-8b12a9b1-563e-4c6f-ab9c-be60716de78a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973535603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.973535603
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3284798938
Short name T329
Test name
Test status
Simulation time 5352567481 ps
CPU time 8.33 seconds
Started Jul 10 06:55:22 PM PDT 24
Finished Jul 10 06:55:31 PM PDT 24
Peak memory 218300 kb
Host smart-e865ddec-103e-4495-8b0b-6dcf0d508d5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284798938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3284798938
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3328737213
Short name T661
Test name
Test status
Simulation time 920467470 ps
CPU time 13.19 seconds
Started Jul 10 06:55:30 PM PDT 24
Finished Jul 10 06:55:44 PM PDT 24
Peak memory 217700 kb
Host smart-b531df93-85ef-45a1-b519-5336d2820388
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328737213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3328737213
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.426907782
Short name T228
Test name
Test status
Simulation time 55566736 ps
CPU time 1.62 seconds
Started Jul 10 06:55:23 PM PDT 24
Finished Jul 10 06:55:25 PM PDT 24
Peak memory 217716 kb
Host smart-96305f52-a592-442a-aa69-7e6f881ad935
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426907782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.426907782
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.928334011
Short name T469
Test name
Test status
Simulation time 2096625378 ps
CPU time 69.23 seconds
Started Jul 10 07:05:12 PM PDT 24
Finished Jul 10 07:06:24 PM PDT 24
Peak memory 267428 kb
Host smart-cf0f12d6-fb34-4c18-bba3-a16f74a0c70f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928334011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.928334011
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2406754101
Short name T575
Test name
Test status
Simulation time 369382129 ps
CPU time 10.86 seconds
Started Jul 10 06:55:21 PM PDT 24
Finished Jul 10 06:55:32 PM PDT 24
Peak memory 250480 kb
Host smart-f01827d9-a67e-46ca-a1ff-643718de98bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406754101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2406754101
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3482329710
Short name T621
Test name
Test status
Simulation time 18445081 ps
CPU time 1.56 seconds
Started Jul 10 06:55:12 PM PDT 24
Finished Jul 10 06:55:14 PM PDT 24
Peak memory 221896 kb
Host smart-4888e040-54e9-46d9-9585-f90642c1d590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482329710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3482329710
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.154920829
Short name T423
Test name
Test status
Simulation time 727441181 ps
CPU time 20.18 seconds
Started Jul 10 06:55:22 PM PDT 24
Finished Jul 10 06:55:43 PM PDT 24
Peak memory 217732 kb
Host smart-18f07b9c-b1cf-43f6-aec8-ad8d9237cf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154920829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.154920829
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2124210041
Short name T523
Test name
Test status
Simulation time 409072108 ps
CPU time 13.17 seconds
Started Jul 10 06:55:30 PM PDT 24
Finished Jul 10 06:55:44 PM PDT 24
Peak memory 218956 kb
Host smart-16049ba7-806b-4b6d-af17-62d28b0acd12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124210041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2124210041
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3733817811
Short name T587
Test name
Test status
Simulation time 1288832322 ps
CPU time 8.99 seconds
Started Jul 10 06:55:30 PM PDT 24
Finished Jul 10 06:55:39 PM PDT 24
Peak memory 225540 kb
Host smart-9dddde05-81ff-452b-823c-0606c797be15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733817811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3733817811
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2192723214
Short name T764
Test name
Test status
Simulation time 2192289275 ps
CPU time 18 seconds
Started Jul 10 06:55:30 PM PDT 24
Finished Jul 10 06:55:49 PM PDT 24
Peak memory 218204 kb
Host smart-820bd525-0c77-4c91-b211-5e572e74a5b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192723214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
192723214
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1653467441
Short name T489
Test name
Test status
Simulation time 268158496 ps
CPU time 10.09 seconds
Started Jul 10 06:55:11 PM PDT 24
Finished Jul 10 06:55:22 PM PDT 24
Peak memory 226112 kb
Host smart-2abff009-b934-4d1a-966d-e07992492db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653467441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1653467441
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2840665028
Short name T19
Test name
Test status
Simulation time 199942655 ps
CPU time 5.81 seconds
Started Jul 10 06:55:13 PM PDT 24
Finished Jul 10 06:55:19 PM PDT 24
Peak memory 223332 kb
Host smart-c76f658d-9f00-4be0-bc38-34df98f92347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840665028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2840665028
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.4099335028
Short name T256
Test name
Test status
Simulation time 394039241 ps
CPU time 27.48 seconds
Started Jul 10 06:55:13 PM PDT 24
Finished Jul 10 06:55:41 PM PDT 24
Peak memory 250976 kb
Host smart-c1676c25-1bc9-44a4-8a0a-7e3a382d002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099335028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.4099335028
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2633536557
Short name T851
Test name
Test status
Simulation time 751477913 ps
CPU time 7.43 seconds
Started Jul 10 06:55:12 PM PDT 24
Finished Jul 10 06:55:20 PM PDT 24
Peak memory 247376 kb
Host smart-39a8d54f-b7dc-45c6-bcf9-4f8f97b9a771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633536557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2633536557
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1077346598
Short name T350
Test name
Test status
Simulation time 15596632309 ps
CPU time 128.92 seconds
Started Jul 10 06:55:31 PM PDT 24
Finished Jul 10 06:57:41 PM PDT 24
Peak memory 254160 kb
Host smart-136c03ca-0272-4214-9f99-4320a35be042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077346598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1077346598
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.160153210
Short name T550
Test name
Test status
Simulation time 34784543 ps
CPU time 1.19 seconds
Started Jul 10 06:55:12 PM PDT 24
Finished Jul 10 06:55:13 PM PDT 24
Peak memory 213036 kb
Host smart-e556ed06-57de-4d20-bf5e-034b72f45651
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160153210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.160153210
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.398908370
Short name T705
Test name
Test status
Simulation time 67610202 ps
CPU time 1.08 seconds
Started Jul 10 06:56:01 PM PDT 24
Finished Jul 10 06:56:03 PM PDT 24
Peak memory 209168 kb
Host smart-f266e188-6dd0-42a3-893a-0532d3dc7a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398908370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.398908370
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1333899448
Short name T200
Test name
Test status
Simulation time 11095792 ps
CPU time 0.95 seconds
Started Jul 10 06:55:46 PM PDT 24
Finished Jul 10 06:55:47 PM PDT 24
Peak memory 208964 kb
Host smart-cc62f6dd-fa52-4d7d-820d-ba97daede586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333899448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1333899448
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2708245966
Short name T771
Test name
Test status
Simulation time 1514922158 ps
CPU time 11.94 seconds
Started Jul 10 06:55:39 PM PDT 24
Finished Jul 10 06:55:52 PM PDT 24
Peak memory 218188 kb
Host smart-a58affcd-6c4f-467a-bb8a-f9d1db807a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708245966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2708245966
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1793399345
Short name T568
Test name
Test status
Simulation time 380966902 ps
CPU time 5.32 seconds
Started Jul 10 06:55:52 PM PDT 24
Finished Jul 10 06:55:58 PM PDT 24
Peak memory 217080 kb
Host smart-a9080690-3ada-4195-bfb3-8ef0a25de5af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793399345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1793399345
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2672669961
Short name T367
Test name
Test status
Simulation time 68916008535 ps
CPU time 112.89 seconds
Started Jul 10 06:55:53 PM PDT 24
Finished Jul 10 06:57:47 PM PDT 24
Peak memory 219960 kb
Host smart-cece1462-216b-4d79-8eb9-eebb31948a17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672669961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2672669961
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.222277363
Short name T261
Test name
Test status
Simulation time 787853263 ps
CPU time 5.69 seconds
Started Jul 10 06:55:52 PM PDT 24
Finished Jul 10 06:55:58 PM PDT 24
Peak memory 217812 kb
Host smart-40512b98-1740-4a05-9b7b-bcef65f5b2b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222277363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.222277363
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3530081724
Short name T814
Test name
Test status
Simulation time 1352542365 ps
CPU time 19.07 seconds
Started Jul 10 06:55:53 PM PDT 24
Finished Jul 10 06:56:13 PM PDT 24
Peak memory 224240 kb
Host smart-30a353f2-bbc5-4f86-89ab-ba41ead6662f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530081724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3530081724
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.198181916
Short name T68
Test name
Test status
Simulation time 2854630297 ps
CPU time 29.13 seconds
Started Jul 10 06:55:52 PM PDT 24
Finished Jul 10 06:56:22 PM PDT 24
Peak memory 217768 kb
Host smart-3edb3ecc-7474-4bed-821a-af081106ff5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198181916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.198181916
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.522687209
Short name T428
Test name
Test status
Simulation time 449394995 ps
CPU time 13.38 seconds
Started Jul 10 06:55:52 PM PDT 24
Finished Jul 10 06:56:06 PM PDT 24
Peak memory 217720 kb
Host smart-b2cb7a3e-fa37-4323-8c60-cef6a2f6cc5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522687209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.522687209
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2901930229
Short name T795
Test name
Test status
Simulation time 4261127001 ps
CPU time 86.39 seconds
Started Jul 10 06:55:52 PM PDT 24
Finished Jul 10 06:57:20 PM PDT 24
Peak memory 283792 kb
Host smart-11964725-16bf-49f5-8b2c-a5f530941896
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901930229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2901930229
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2558541826
Short name T787
Test name
Test status
Simulation time 1698211255 ps
CPU time 10.91 seconds
Started Jul 10 06:55:53 PM PDT 24
Finished Jul 10 06:56:05 PM PDT 24
Peak memory 250412 kb
Host smart-aeaf4d16-13e6-4016-82a5-9476316a10ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558541826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2558541826
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2665557896
Short name T234
Test name
Test status
Simulation time 111234441 ps
CPU time 2.3 seconds
Started Jul 10 06:55:39 PM PDT 24
Finished Jul 10 06:55:42 PM PDT 24
Peak memory 218272 kb
Host smart-ae3861fa-298f-45d6-98ec-a5bc1792a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665557896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2665557896
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.974308857
Short name T104
Test name
Test status
Simulation time 747433074 ps
CPU time 14.87 seconds
Started Jul 10 06:55:44 PM PDT 24
Finished Jul 10 06:55:59 PM PDT 24
Peak memory 217768 kb
Host smart-9c4477ea-d34b-4237-a1ba-c9f890e4eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974308857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.974308857
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4277005522
Short name T53
Test name
Test status
Simulation time 912494698 ps
CPU time 39.62 seconds
Started Jul 10 06:56:00 PM PDT 24
Finished Jul 10 06:56:41 PM PDT 24
Peak memory 284588 kb
Host smart-7ec9e46b-d0b5-4359-85c7-c9503d7b16ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277005522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4277005522
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4250995669
Short name T303
Test name
Test status
Simulation time 430563265 ps
CPU time 9.55 seconds
Started Jul 10 06:55:52 PM PDT 24
Finished Jul 10 06:56:03 PM PDT 24
Peak memory 226028 kb
Host smart-72454a26-b766-4faa-8956-cf6c9d37cdac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250995669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4250995669
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2578931394
Short name T450
Test name
Test status
Simulation time 1274157679 ps
CPU time 15.41 seconds
Started Jul 10 06:56:01 PM PDT 24
Finished Jul 10 06:56:18 PM PDT 24
Peak memory 226048 kb
Host smart-80d46b32-d7a7-4440-a492-f4d5a257b75b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578931394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2578931394
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2125842035
Short name T675
Test name
Test status
Simulation time 907085903 ps
CPU time 11.39 seconds
Started Jul 10 06:55:52 PM PDT 24
Finished Jul 10 06:56:04 PM PDT 24
Peak memory 218224 kb
Host smart-f53a73d1-a89c-46f3-a75e-24edb98f7ffe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125842035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
125842035
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.806725096
Short name T547
Test name
Test status
Simulation time 2230665413 ps
CPU time 6.46 seconds
Started Jul 10 06:55:47 PM PDT 24
Finished Jul 10 06:55:54 PM PDT 24
Peak memory 218332 kb
Host smart-3888e327-3dfa-426b-a8ed-5ce6cb132b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806725096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.806725096
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.462357673
Short name T801
Test name
Test status
Simulation time 128019404 ps
CPU time 1.94 seconds
Started Jul 10 06:55:39 PM PDT 24
Finished Jul 10 06:55:42 PM PDT 24
Peak memory 214056 kb
Host smart-8d2227b2-a17f-46f1-b445-f65eda18f0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462357673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.462357673
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.896487323
Short name T236
Test name
Test status
Simulation time 1273772741 ps
CPU time 27.56 seconds
Started Jul 10 06:55:40 PM PDT 24
Finished Jul 10 06:56:09 PM PDT 24
Peak memory 250880 kb
Host smart-e7cd8463-831a-4d87-b5ac-9a7dee04ea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896487323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.896487323
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3395147635
Short name T554
Test name
Test status
Simulation time 79363273 ps
CPU time 6.58 seconds
Started Jul 10 06:55:39 PM PDT 24
Finished Jul 10 06:55:47 PM PDT 24
Peak memory 250488 kb
Host smart-ce299b8f-d2b8-4928-873c-2c3931e1aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395147635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3395147635
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.600182975
Short name T598
Test name
Test status
Simulation time 16315133553 ps
CPU time 190.41 seconds
Started Jul 10 06:56:01 PM PDT 24
Finished Jul 10 06:59:13 PM PDT 24
Peak memory 422092 kb
Host smart-ce50a3ad-1491-4e50-bcaa-42cea079afdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600182975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.600182975
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1742173473
Short name T839
Test name
Test status
Simulation time 13932707 ps
CPU time 1.13 seconds
Started Jul 10 06:55:40 PM PDT 24
Finished Jul 10 06:55:42 PM PDT 24
Peak memory 213000 kb
Host smart-50bdc062-6972-480a-b9ee-f2debac38a67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742173473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1742173473
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1555426390
Short name T293
Test name
Test status
Simulation time 102445430 ps
CPU time 1.25 seconds
Started Jul 10 06:58:10 PM PDT 24
Finished Jul 10 06:58:13 PM PDT 24
Peak memory 209032 kb
Host smart-af4b70b5-2ace-4a71-be6d-fbc7c445aeee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555426390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1555426390
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1898918811
Short name T612
Test name
Test status
Simulation time 261562524 ps
CPU time 2.17 seconds
Started Jul 10 06:58:10 PM PDT 24
Finished Jul 10 06:58:14 PM PDT 24
Peak memory 217188 kb
Host smart-9ee14829-a862-4d89-ae7d-1057518f824b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898918811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1898918811
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1983542053
Short name T343
Test name
Test status
Simulation time 5372982288 ps
CPU time 20.52 seconds
Started Jul 10 06:58:12 PM PDT 24
Finished Jul 10 06:58:33 PM PDT 24
Peak memory 226104 kb
Host smart-01a26145-db34-4976-996e-76307da262e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983542053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1983542053
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2383279004
Short name T791
Test name
Test status
Simulation time 1667421787 ps
CPU time 6.24 seconds
Started Jul 10 06:58:11 PM PDT 24
Finished Jul 10 06:58:19 PM PDT 24
Peak memory 218228 kb
Host smart-971d0e64-5d28-45c3-8837-fc4f3d603ab8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383279004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2383279004
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2595071398
Short name T585
Test name
Test status
Simulation time 604187187 ps
CPU time 8.94 seconds
Started Jul 10 06:58:10 PM PDT 24
Finished Jul 10 06:58:20 PM PDT 24
Peak memory 217716 kb
Host smart-624fc89e-f2b4-462b-b484-10bf4964da66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595071398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2595071398
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3988283670
Short name T95
Test name
Test status
Simulation time 3966361364 ps
CPU time 127.43 seconds
Started Jul 10 06:58:12 PM PDT 24
Finished Jul 10 07:00:21 PM PDT 24
Peak memory 283708 kb
Host smart-a72be33d-70e8-4191-95ee-0119921d0ce2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988283670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3988283670
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1604837966
Short name T387
Test name
Test status
Simulation time 1567243620 ps
CPU time 25.29 seconds
Started Jul 10 06:58:12 PM PDT 24
Finished Jul 10 06:58:38 PM PDT 24
Peak memory 250972 kb
Host smart-2eea1106-9b08-4bed-ba59-cb474c7c6efe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604837966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1604837966
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1892322942
Short name T566
Test name
Test status
Simulation time 84444436 ps
CPU time 3.09 seconds
Started Jul 10 06:58:05 PM PDT 24
Finished Jul 10 06:58:09 PM PDT 24
Peak memory 222560 kb
Host smart-01bac4f6-0460-4e9e-8946-63443675947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892322942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1892322942
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2297997488
Short name T812
Test name
Test status
Simulation time 886575633 ps
CPU time 11.29 seconds
Started Jul 10 06:58:13 PM PDT 24
Finished Jul 10 06:58:25 PM PDT 24
Peak memory 226044 kb
Host smart-77f6f7f1-5b5a-474f-8f87-7045604b4462
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297997488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2297997488
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1242112488
Short name T272
Test name
Test status
Simulation time 3167950776 ps
CPU time 16.19 seconds
Started Jul 10 06:58:11 PM PDT 24
Finished Jul 10 06:58:28 PM PDT 24
Peak memory 226036 kb
Host smart-06ccfe36-aabe-4913-a7bf-f5912c62cbc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242112488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1242112488
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.224770086
Short name T77
Test name
Test status
Simulation time 288723042 ps
CPU time 7.96 seconds
Started Jul 10 06:58:04 PM PDT 24
Finished Jul 10 06:58:13 PM PDT 24
Peak memory 217716 kb
Host smart-88f1e808-b0c4-4ad9-aa81-cf095f7a45c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224770086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.224770086
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3272182465
Short name T412
Test name
Test status
Simulation time 1009953327 ps
CPU time 20.77 seconds
Started Jul 10 06:58:05 PM PDT 24
Finished Jul 10 06:58:27 PM PDT 24
Peak memory 250980 kb
Host smart-cd01acd7-7379-4bd1-8771-37b05d5902b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272182465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3272182465
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3514332191
Short name T297
Test name
Test status
Simulation time 146061201 ps
CPU time 3.05 seconds
Started Jul 10 06:58:03 PM PDT 24
Finished Jul 10 06:58:07 PM PDT 24
Peak memory 218212 kb
Host smart-11b6d9df-75fb-4663-966e-bb7f4eeddcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514332191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3514332191
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3740464909
Short name T426
Test name
Test status
Simulation time 14433558492 ps
CPU time 64.25 seconds
Started Jul 10 06:58:09 PM PDT 24
Finished Jul 10 06:59:14 PM PDT 24
Peak memory 251032 kb
Host smart-05c3a7d4-37a7-42ea-897e-92ed81b39c01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740464909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3740464909
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1089339976
Short name T239
Test name
Test status
Simulation time 32674216 ps
CPU time 0.88 seconds
Started Jul 10 06:58:04 PM PDT 24
Finished Jul 10 06:58:06 PM PDT 24
Peak memory 211864 kb
Host smart-d943e02f-9b56-4c0b-a1a7-e34580655cad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089339976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1089339976
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1180636458
Short name T70
Test name
Test status
Simulation time 24016564 ps
CPU time 1.2 seconds
Started Jul 10 06:58:26 PM PDT 24
Finished Jul 10 06:58:28 PM PDT 24
Peak memory 209064 kb
Host smart-fef03372-f57a-4e60-87a0-71eb27fae23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180636458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1180636458
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2163701599
Short name T589
Test name
Test status
Simulation time 479983188 ps
CPU time 12.27 seconds
Started Jul 10 06:58:19 PM PDT 24
Finished Jul 10 06:58:32 PM PDT 24
Peak memory 218232 kb
Host smart-6f0f8209-440b-4607-8ed8-08c8a8e4776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163701599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2163701599
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1642610469
Short name T714
Test name
Test status
Simulation time 120646520 ps
CPU time 3.89 seconds
Started Jul 10 06:58:17 PM PDT 24
Finished Jul 10 06:58:22 PM PDT 24
Peak memory 217160 kb
Host smart-2bd23285-48b7-4447-b78c-39d88ba85364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642610469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1642610469
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2364472691
Short name T806
Test name
Test status
Simulation time 1184991048 ps
CPU time 35.41 seconds
Started Jul 10 06:58:20 PM PDT 24
Finished Jul 10 06:58:56 PM PDT 24
Peak memory 217640 kb
Host smart-ee3ae533-2e2f-4441-9402-12a4694a686a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364472691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2364472691
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4042595050
Short name T627
Test name
Test status
Simulation time 665686156 ps
CPU time 4.71 seconds
Started Jul 10 06:58:17 PM PDT 24
Finished Jul 10 06:58:22 PM PDT 24
Peak memory 218228 kb
Host smart-03818706-1750-4a1b-9dde-3fc32cda84f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042595050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4042595050
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1631676626
Short name T73
Test name
Test status
Simulation time 424870328 ps
CPU time 3.1 seconds
Started Jul 10 06:58:20 PM PDT 24
Finished Jul 10 06:58:24 PM PDT 24
Peak memory 217152 kb
Host smart-70eba553-aeae-42f6-9eee-6fe35009845b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631676626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1631676626
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2666219364
Short name T299
Test name
Test status
Simulation time 7854890794 ps
CPU time 50.71 seconds
Started Jul 10 06:58:17 PM PDT 24
Finished Jul 10 06:59:09 PM PDT 24
Peak memory 267484 kb
Host smart-a09f239f-20a1-40e8-b18e-1ad5940b6894
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666219364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2666219364
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.649563848
Short name T682
Test name
Test status
Simulation time 1406166902 ps
CPU time 6.38 seconds
Started Jul 10 06:58:18 PM PDT 24
Finished Jul 10 06:58:25 PM PDT 24
Peak memory 224636 kb
Host smart-65e05d21-3ab5-4749-a3e9-e15f675bf2d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649563848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.649563848
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.4005041407
Short name T255
Test name
Test status
Simulation time 57172314 ps
CPU time 3.49 seconds
Started Jul 10 06:58:16 PM PDT 24
Finished Jul 10 06:58:21 PM PDT 24
Peak memory 218192 kb
Host smart-8c969f2a-576a-4cc7-8239-2b1b2db25988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005041407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.4005041407
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3346324537
Short name T513
Test name
Test status
Simulation time 227611969 ps
CPU time 10.57 seconds
Started Jul 10 06:58:19 PM PDT 24
Finished Jul 10 06:58:30 PM PDT 24
Peak memory 226032 kb
Host smart-55d10410-8d72-484e-aa32-6812a7b3427f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346324537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3346324537
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.96883234
Short name T721
Test name
Test status
Simulation time 5455447797 ps
CPU time 13.28 seconds
Started Jul 10 06:58:18 PM PDT 24
Finished Jul 10 06:58:32 PM PDT 24
Peak memory 226080 kb
Host smart-f8cfdd90-0fc4-47cf-8cae-7ac700a0db23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96883234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_dig
est.96883234
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3648334754
Short name T525
Test name
Test status
Simulation time 324058861 ps
CPU time 11.43 seconds
Started Jul 10 06:58:17 PM PDT 24
Finished Jul 10 06:58:29 PM PDT 24
Peak memory 218236 kb
Host smart-889c3eef-b319-481b-875d-58362ba26da8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648334754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3648334754
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.381744095
Short name T715
Test name
Test status
Simulation time 269631159 ps
CPU time 10.79 seconds
Started Jul 10 06:58:17 PM PDT 24
Finished Jul 10 06:58:28 PM PDT 24
Peak memory 226048 kb
Host smart-916e94f8-082b-4aa1-b656-4a5b143f6ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381744095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.381744095
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4268195499
Short name T542
Test name
Test status
Simulation time 83755347 ps
CPU time 1.43 seconds
Started Jul 10 06:58:10 PM PDT 24
Finished Jul 10 06:58:13 PM PDT 24
Peak memory 213796 kb
Host smart-e1f7a213-b723-480b-8d8a-cc1b822ca6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268195499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4268195499
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1326271972
Short name T365
Test name
Test status
Simulation time 503825773 ps
CPU time 28.71 seconds
Started Jul 10 06:58:19 PM PDT 24
Finished Jul 10 06:58:49 PM PDT 24
Peak memory 251184 kb
Host smart-a7510921-daf3-4996-9b1b-50bfb81d5435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326271972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1326271972
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3374890657
Short name T573
Test name
Test status
Simulation time 188736245 ps
CPU time 7.94 seconds
Started Jul 10 06:58:18 PM PDT 24
Finished Jul 10 06:58:26 PM PDT 24
Peak memory 250972 kb
Host smart-067454a2-6523-4624-aa56-333e27ebe2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374890657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3374890657
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2223711822
Short name T392
Test name
Test status
Simulation time 104999169 ps
CPU time 0.87 seconds
Started Jul 10 06:58:10 PM PDT 24
Finished Jul 10 06:58:12 PM PDT 24
Peak memory 212992 kb
Host smart-80e2d773-49c5-4cd9-83c6-871b7975c7d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223711822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2223711822
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2035123747
Short name T86
Test name
Test status
Simulation time 14769658 ps
CPU time 0.85 seconds
Started Jul 10 06:58:33 PM PDT 24
Finished Jul 10 06:58:35 PM PDT 24
Peak memory 208968 kb
Host smart-6b39e7df-4996-49e5-9218-3a5ebd788548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035123747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2035123747
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2729785031
Short name T371
Test name
Test status
Simulation time 1141981373 ps
CPU time 10.15 seconds
Started Jul 10 06:58:24 PM PDT 24
Finished Jul 10 06:58:35 PM PDT 24
Peak memory 218172 kb
Host smart-8e98c667-7f5b-4f67-b1dc-745636f5c062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729785031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2729785031
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3649730940
Short name T770
Test name
Test status
Simulation time 141092640 ps
CPU time 2.3 seconds
Started Jul 10 06:58:32 PM PDT 24
Finished Jul 10 06:58:35 PM PDT 24
Peak memory 217168 kb
Host smart-0feb182c-fc30-44f7-9e22-6016bcc4e138
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649730940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3649730940
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2189615059
Short name T48
Test name
Test status
Simulation time 3979551791 ps
CPU time 63.31 seconds
Started Jul 10 06:58:35 PM PDT 24
Finished Jul 10 06:59:39 PM PDT 24
Peak memory 226216 kb
Host smart-35f66254-08b1-4456-a7f5-7f22e9533719
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189615059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2189615059
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2987856779
Short name T519
Test name
Test status
Simulation time 345379128 ps
CPU time 9.69 seconds
Started Jul 10 06:58:25 PM PDT 24
Finished Jul 10 06:58:35 PM PDT 24
Peak memory 218200 kb
Host smart-6e0a666b-768f-4d7f-954d-a6666f8826ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987856779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2987856779
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3992004810
Short name T334
Test name
Test status
Simulation time 323898649 ps
CPU time 9.54 seconds
Started Jul 10 06:58:25 PM PDT 24
Finished Jul 10 06:58:36 PM PDT 24
Peak memory 217724 kb
Host smart-9934e298-f9a9-4918-b1d1-ff5a2c8df555
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992004810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3992004810
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1456665120
Short name T218
Test name
Test status
Simulation time 3066842222 ps
CPU time 101.38 seconds
Started Jul 10 06:58:26 PM PDT 24
Finished Jul 10 07:00:09 PM PDT 24
Peak memory 275612 kb
Host smart-29a6058d-b9c1-4664-b3bb-509347cfdf1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456665120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1456665120
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3231667711
Short name T798
Test name
Test status
Simulation time 8504483646 ps
CPU time 14.89 seconds
Started Jul 10 06:58:26 PM PDT 24
Finished Jul 10 06:58:42 PM PDT 24
Peak memory 251024 kb
Host smart-84f79070-1300-4c46-b5e3-63b5880cb93f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231667711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3231667711
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1055088281
Short name T448
Test name
Test status
Simulation time 161144874 ps
CPU time 3.3 seconds
Started Jul 10 06:58:27 PM PDT 24
Finished Jul 10 06:58:31 PM PDT 24
Peak memory 218224 kb
Host smart-832d794c-ca2f-406e-b145-62c215313f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055088281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1055088281
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3252095795
Short name T819
Test name
Test status
Simulation time 470522663 ps
CPU time 10.5 seconds
Started Jul 10 06:58:35 PM PDT 24
Finished Jul 10 06:58:46 PM PDT 24
Peak memory 218952 kb
Host smart-ee3ad380-e106-4382-b53d-1a3de67ca63a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252095795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3252095795
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1886236724
Short name T304
Test name
Test status
Simulation time 510328582 ps
CPU time 17.8 seconds
Started Jul 10 06:58:32 PM PDT 24
Finished Jul 10 06:58:50 PM PDT 24
Peak memory 226104 kb
Host smart-e338e0cc-03a8-4885-b04b-5f6cca3cc020
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886236724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1886236724
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.33111216
Short name T703
Test name
Test status
Simulation time 313247757 ps
CPU time 8.7 seconds
Started Jul 10 06:58:26 PM PDT 24
Finished Jul 10 06:58:36 PM PDT 24
Peak memory 225008 kb
Host smart-a5a22113-8c86-4c82-ab8b-a28f48c21f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33111216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.33111216
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.528032306
Short name T602
Test name
Test status
Simulation time 24391193 ps
CPU time 1.29 seconds
Started Jul 10 06:58:25 PM PDT 24
Finished Jul 10 06:58:28 PM PDT 24
Peak memory 217712 kb
Host smart-21d88d31-71fe-4c93-8883-7bfca71f4ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528032306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.528032306
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3769737555
Short name T570
Test name
Test status
Simulation time 227003416 ps
CPU time 24.7 seconds
Started Jul 10 06:58:25 PM PDT 24
Finished Jul 10 06:58:51 PM PDT 24
Peak memory 250992 kb
Host smart-9194a6d9-2a63-42b8-94be-38ec40bc9d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769737555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3769737555
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.996713292
Short name T505
Test name
Test status
Simulation time 90506099 ps
CPU time 7.69 seconds
Started Jul 10 06:58:26 PM PDT 24
Finished Jul 10 06:58:34 PM PDT 24
Peak memory 250936 kb
Host smart-19803ddf-b859-4983-8f5b-bf279a8086fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996713292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.996713292
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3896824480
Short name T332
Test name
Test status
Simulation time 49671867944 ps
CPU time 50.12 seconds
Started Jul 10 06:58:32 PM PDT 24
Finished Jul 10 06:59:23 PM PDT 24
Peak memory 226180 kb
Host smart-62a2e237-98a2-4b9b-9d28-7057f1c66723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896824480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3896824480
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1626401217
Short name T411
Test name
Test status
Simulation time 79666175077 ps
CPU time 384.07 seconds
Started Jul 10 06:58:33 PM PDT 24
Finished Jul 10 07:04:57 PM PDT 24
Peak memory 283984 kb
Host smart-a1340370-aa80-4d2b-b7ac-14b2c8f1dd8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1626401217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.1626401217
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2996883297
Short name T321
Test name
Test status
Simulation time 38536703 ps
CPU time 0.84 seconds
Started Jul 10 06:58:25 PM PDT 24
Finished Jul 10 06:58:27 PM PDT 24
Peak memory 211816 kb
Host smart-87c52d69-ab43-47c9-ac3d-f6400612b282
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996883297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2996883297
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3395625327
Short name T460
Test name
Test status
Simulation time 55384044 ps
CPU time 0.86 seconds
Started Jul 10 06:58:42 PM PDT 24
Finished Jul 10 06:58:43 PM PDT 24
Peak memory 208956 kb
Host smart-a698db3c-0f69-490e-9bf4-05b2b36f8e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395625327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3395625327
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3391645217
Short name T169
Test name
Test status
Simulation time 2189897792 ps
CPU time 16.39 seconds
Started Jul 10 06:58:42 PM PDT 24
Finished Jul 10 06:59:00 PM PDT 24
Peak memory 226092 kb
Host smart-2afc09d6-2772-4714-828c-255e0cc27228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391645217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3391645217
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.973148361
Short name T420
Test name
Test status
Simulation time 937427721 ps
CPU time 3.77 seconds
Started Jul 10 06:58:43 PM PDT 24
Finished Jul 10 06:58:48 PM PDT 24
Peak memory 217104 kb
Host smart-d4fc9189-6e10-4aaa-aa2f-86209421db22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973148361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.973148361
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1490056735
Short name T594
Test name
Test status
Simulation time 7160151499 ps
CPU time 33.17 seconds
Started Jul 10 06:58:42 PM PDT 24
Finished Jul 10 06:59:16 PM PDT 24
Peak memory 218948 kb
Host smart-f10899c4-7567-4a41-8df7-8ed5a097e4b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490056735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1490056735
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3383905839
Short name T490
Test name
Test status
Simulation time 1108405990 ps
CPU time 8.43 seconds
Started Jul 10 06:58:44 PM PDT 24
Finished Jul 10 06:58:53 PM PDT 24
Peak memory 218236 kb
Host smart-4cedcd6b-9da5-4458-8bb5-d6cd6a6ebada
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383905839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3383905839
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1800608480
Short name T548
Test name
Test status
Simulation time 343590710 ps
CPU time 1.83 seconds
Started Jul 10 06:58:42 PM PDT 24
Finished Jul 10 06:58:45 PM PDT 24
Peak memory 217704 kb
Host smart-31dd81a3-74df-4a9d-9ea5-02c4c2a3e9b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800608480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1800608480
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2159685503
Short name T340
Test name
Test status
Simulation time 4006446102 ps
CPU time 52.33 seconds
Started Jul 10 06:58:43 PM PDT 24
Finished Jul 10 06:59:36 PM PDT 24
Peak memory 252904 kb
Host smart-db9054a6-b9d9-4fff-b573-d8343782fe52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159685503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2159685503
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3277457392
Short name T251
Test name
Test status
Simulation time 490394907 ps
CPU time 8.56 seconds
Started Jul 10 06:58:46 PM PDT 24
Finished Jul 10 06:58:55 PM PDT 24
Peak memory 223088 kb
Host smart-d7d16565-e7a4-4bc7-af9a-4bc9929acd14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277457392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3277457392
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2966133553
Short name T213
Test name
Test status
Simulation time 81199662 ps
CPU time 2.54 seconds
Started Jul 10 06:58:43 PM PDT 24
Finished Jul 10 06:58:47 PM PDT 24
Peak memory 218216 kb
Host smart-43bc39d8-9d8d-4947-a4c3-611796bda178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966133553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2966133553
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1239183314
Short name T580
Test name
Test status
Simulation time 2490141101 ps
CPU time 14.88 seconds
Started Jul 10 06:58:44 PM PDT 24
Finished Jul 10 06:59:00 PM PDT 24
Peak memory 220260 kb
Host smart-c4a84bd7-0073-49fe-b4ef-0b5d91ee0437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239183314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1239183314
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2185732346
Short name T330
Test name
Test status
Simulation time 785072074 ps
CPU time 14.58 seconds
Started Jul 10 06:58:45 PM PDT 24
Finished Jul 10 06:59:00 PM PDT 24
Peak memory 226032 kb
Host smart-cf43ccb3-69aa-43b7-9cb0-166174aabd42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185732346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2185732346
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2473207699
Short name T391
Test name
Test status
Simulation time 273525649 ps
CPU time 7.36 seconds
Started Jul 10 06:58:42 PM PDT 24
Finished Jul 10 06:58:50 PM PDT 24
Peak memory 226032 kb
Host smart-a89d0018-cdfb-4c7c-ba72-fe807d6e2371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473207699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2473207699
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2267801394
Short name T543
Test name
Test status
Simulation time 268898173 ps
CPU time 10.55 seconds
Started Jul 10 06:58:43 PM PDT 24
Finished Jul 10 06:58:55 PM PDT 24
Peak memory 226028 kb
Host smart-96922b4d-71e5-42e9-b7d5-764c50713cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267801394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2267801394
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3846206188
Short name T230
Test name
Test status
Simulation time 16756742 ps
CPU time 1.48 seconds
Started Jul 10 06:58:41 PM PDT 24
Finished Jul 10 06:58:43 PM PDT 24
Peak memory 217744 kb
Host smart-a4a9431f-a040-4c6e-b725-2d48d65dfd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846206188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3846206188
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2254378727
Short name T501
Test name
Test status
Simulation time 268320400 ps
CPU time 27.68 seconds
Started Jul 10 06:58:44 PM PDT 24
Finished Jul 10 06:59:13 PM PDT 24
Peak memory 250968 kb
Host smart-ee089215-1369-415e-b6a7-26920db14109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254378727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2254378727
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1126215121
Short name T479
Test name
Test status
Simulation time 194109533 ps
CPU time 8 seconds
Started Jul 10 06:58:43 PM PDT 24
Finished Jul 10 06:58:52 PM PDT 24
Peak memory 250912 kb
Host smart-1be3bfff-6eb7-4bef-9630-2e350ffe040f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126215121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1126215121
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2490420852
Short name T456
Test name
Test status
Simulation time 12538035 ps
CPU time 1.01 seconds
Started Jul 10 06:58:42 PM PDT 24
Finished Jul 10 06:58:43 PM PDT 24
Peak memory 211856 kb
Host smart-58cfef2a-c542-4117-a967-70b877628cb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490420852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2490420852
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2970973095
Short name T652
Test name
Test status
Simulation time 17316457 ps
CPU time 0.85 seconds
Started Jul 10 06:58:59 PM PDT 24
Finished Jul 10 06:59:00 PM PDT 24
Peak memory 208756 kb
Host smart-add55b98-fecb-46f3-a884-a52f33f55971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970973095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2970973095
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1294846079
Short name T854
Test name
Test status
Simulation time 1329821824 ps
CPU time 14.73 seconds
Started Jul 10 06:58:51 PM PDT 24
Finished Jul 10 06:59:06 PM PDT 24
Peak memory 218296 kb
Host smart-e6265d1e-8a88-40e8-a594-557628960a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294846079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1294846079
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.318163041
Short name T832
Test name
Test status
Simulation time 4558673402 ps
CPU time 3.53 seconds
Started Jul 10 06:58:50 PM PDT 24
Finished Jul 10 06:58:54 PM PDT 24
Peak memory 217540 kb
Host smart-c742e340-3609-4b94-98e4-2aa79c846848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318163041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.318163041
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2871090656
Short name T317
Test name
Test status
Simulation time 1501227092 ps
CPU time 49.4 seconds
Started Jul 10 06:58:55 PM PDT 24
Finished Jul 10 06:59:45 PM PDT 24
Peak memory 218832 kb
Host smart-293b4d98-1152-436e-b846-cd28cea1d60f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871090656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2871090656
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2729368566
Short name T322
Test name
Test status
Simulation time 322581201 ps
CPU time 2.2 seconds
Started Jul 10 06:58:55 PM PDT 24
Finished Jul 10 06:58:58 PM PDT 24
Peak memory 218172 kb
Host smart-f6f3edd3-528b-4816-8ebe-d0eac11adfcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729368566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2729368566
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2406150966
Short name T716
Test name
Test status
Simulation time 3757020254 ps
CPU time 11.04 seconds
Started Jul 10 06:58:53 PM PDT 24
Finished Jul 10 06:59:04 PM PDT 24
Peak memory 217748 kb
Host smart-aaecb334-a6e5-4039-8e21-9de1de21ecc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406150966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2406150966
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2909497768
Short name T766
Test name
Test status
Simulation time 10650805154 ps
CPU time 63.63 seconds
Started Jul 10 06:58:55 PM PDT 24
Finished Jul 10 06:59:59 PM PDT 24
Peak memory 283776 kb
Host smart-b02b023f-717e-4d69-a871-44772d75dbe4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909497768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2909497768
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.506120264
Short name T244
Test name
Test status
Simulation time 3052800526 ps
CPU time 7.96 seconds
Started Jul 10 06:58:50 PM PDT 24
Finished Jul 10 06:58:59 PM PDT 24
Peak memory 226448 kb
Host smart-96d9aa9a-370d-45ba-8200-b55ea3702353
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506120264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.506120264
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.535561039
Short name T336
Test name
Test status
Simulation time 26896893 ps
CPU time 1.77 seconds
Started Jul 10 06:58:54 PM PDT 24
Finished Jul 10 06:58:56 PM PDT 24
Peak memory 218224 kb
Host smart-7393e355-f45b-4e5c-8ffe-460ec1d7e03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535561039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.535561039
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.326583321
Short name T408
Test name
Test status
Simulation time 1656732843 ps
CPU time 13.39 seconds
Started Jul 10 06:58:53 PM PDT 24
Finished Jul 10 06:59:07 PM PDT 24
Peak memory 218840 kb
Host smart-c3c6a0e0-6ed6-46c2-a473-eb5ce684fb11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326583321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.326583321
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2159653654
Short name T796
Test name
Test status
Simulation time 529760922 ps
CPU time 9.54 seconds
Started Jul 10 06:59:02 PM PDT 24
Finished Jul 10 06:59:12 PM PDT 24
Peak memory 226032 kb
Host smart-47e28a45-3499-4d12-9c9b-346d65c4679b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159653654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2159653654
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2268135219
Short name T60
Test name
Test status
Simulation time 2025894943 ps
CPU time 16.15 seconds
Started Jul 10 06:58:51 PM PDT 24
Finished Jul 10 06:59:08 PM PDT 24
Peak memory 218248 kb
Host smart-13d7eba5-2428-450f-88c3-38294439f506
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268135219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2268135219
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1052803128
Short name T203
Test name
Test status
Simulation time 235148321 ps
CPU time 9.8 seconds
Started Jul 10 06:58:50 PM PDT 24
Finished Jul 10 06:59:01 PM PDT 24
Peak memory 218292 kb
Host smart-67541606-8e92-4ae1-995d-346d68bd9080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052803128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1052803128
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1239646462
Short name T76
Test name
Test status
Simulation time 215336225 ps
CPU time 2.56 seconds
Started Jul 10 06:58:45 PM PDT 24
Finished Jul 10 06:58:49 PM PDT 24
Peak memory 217716 kb
Host smart-74b4a8f4-0cb8-4217-9b26-c92751feb1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239646462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1239646462
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1919485376
Short name T453
Test name
Test status
Simulation time 940417998 ps
CPU time 23.51 seconds
Started Jul 10 06:58:53 PM PDT 24
Finished Jul 10 06:59:17 PM PDT 24
Peak memory 250960 kb
Host smart-9c85d898-5c54-487f-8461-951782de1447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919485376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1919485376
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2300493630
Short name T611
Test name
Test status
Simulation time 343064489 ps
CPU time 3.29 seconds
Started Jul 10 06:58:52 PM PDT 24
Finished Jul 10 06:58:56 PM PDT 24
Peak memory 218212 kb
Host smart-d7a07d21-35de-4ab4-9963-8ae2b7e3cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300493630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2300493630
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2243327087
Short name T301
Test name
Test status
Simulation time 9158025329 ps
CPU time 104.14 seconds
Started Jul 10 06:59:01 PM PDT 24
Finished Jul 10 07:00:46 PM PDT 24
Peak memory 273940 kb
Host smart-c582dd56-89bf-4b35-8203-0bd7925b1399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243327087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2243327087
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3289931812
Short name T691
Test name
Test status
Simulation time 34491817 ps
CPU time 0.9 seconds
Started Jul 10 06:58:51 PM PDT 24
Finished Jul 10 06:58:53 PM PDT 24
Peak memory 212012 kb
Host smart-9d0fb21c-9317-4f89-bd87-99978537cf89
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289931812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3289931812
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2044278492
Short name T699
Test name
Test status
Simulation time 25363816 ps
CPU time 1.05 seconds
Started Jul 10 06:59:00 PM PDT 24
Finished Jul 10 06:59:01 PM PDT 24
Peak memory 208976 kb
Host smart-566fc098-7253-4342-b9d9-2fad9f35acc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044278492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2044278492
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.165827595
Short name T497
Test name
Test status
Simulation time 1209147821 ps
CPU time 15.1 seconds
Started Jul 10 06:59:00 PM PDT 24
Finished Jul 10 06:59:16 PM PDT 24
Peak memory 218208 kb
Host smart-47c913c4-436c-4609-80b9-ddb192910979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165827595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.165827595
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1596954122
Short name T311
Test name
Test status
Simulation time 37284814 ps
CPU time 1.22 seconds
Started Jul 10 06:59:04 PM PDT 24
Finished Jul 10 06:59:06 PM PDT 24
Peak memory 217168 kb
Host smart-38ee7d5b-a395-47ea-b7a7-c9a5a62e22fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596954122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1596954122
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.657014951
Short name T225
Test name
Test status
Simulation time 2103969277 ps
CPU time 37.9 seconds
Started Jul 10 06:59:01 PM PDT 24
Finished Jul 10 06:59:39 PM PDT 24
Peak memory 218228 kb
Host smart-1996f3da-3d6e-4861-bc13-13e3d6a0e29f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657014951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.657014951
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1347166906
Short name T529
Test name
Test status
Simulation time 4225952068 ps
CPU time 9.38 seconds
Started Jul 10 06:59:01 PM PDT 24
Finished Jul 10 06:59:11 PM PDT 24
Peak memory 226132 kb
Host smart-e951cf25-3db6-495c-8af0-0e29a1387b38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347166906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1347166906
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3511211122
Short name T262
Test name
Test status
Simulation time 727632649 ps
CPU time 6.15 seconds
Started Jul 10 06:59:04 PM PDT 24
Finished Jul 10 06:59:11 PM PDT 24
Peak memory 217608 kb
Host smart-9820e1c3-9f8d-45c3-aebc-ec4a48906743
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511211122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3511211122
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1432502967
Short name T686
Test name
Test status
Simulation time 2796468346 ps
CPU time 58.32 seconds
Started Jul 10 06:58:59 PM PDT 24
Finished Jul 10 06:59:58 PM PDT 24
Peak memory 269592 kb
Host smart-b99555a4-7e05-418f-89ae-072e7242ffa0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432502967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1432502967
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2269805157
Short name T374
Test name
Test status
Simulation time 1829423036 ps
CPU time 18.66 seconds
Started Jul 10 06:59:00 PM PDT 24
Finished Jul 10 06:59:20 PM PDT 24
Peak memory 251168 kb
Host smart-d67db461-a5a3-47a0-84b5-c9598777c5a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269805157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2269805157
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2611687622
Short name T811
Test name
Test status
Simulation time 80296359 ps
CPU time 3.65 seconds
Started Jul 10 06:58:59 PM PDT 24
Finished Jul 10 06:59:04 PM PDT 24
Peak memory 218208 kb
Host smart-e40e75f4-c506-4a47-b9ee-58aa6e77527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611687622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2611687622
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1313023914
Short name T438
Test name
Test status
Simulation time 231434403 ps
CPU time 9.5 seconds
Started Jul 10 06:59:00 PM PDT 24
Finished Jul 10 06:59:10 PM PDT 24
Peak memory 226032 kb
Host smart-50741531-8ddf-439c-ad7d-937f801d3911
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313023914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1313023914
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1478260130
Short name T445
Test name
Test status
Simulation time 1211425255 ps
CPU time 12.98 seconds
Started Jul 10 06:59:04 PM PDT 24
Finished Jul 10 06:59:18 PM PDT 24
Peak memory 226028 kb
Host smart-5c831576-f3ff-4818-8ff5-935c0a36ae2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478260130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1478260130
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1395982215
Short name T762
Test name
Test status
Simulation time 287940349 ps
CPU time 8.6 seconds
Started Jul 10 06:59:00 PM PDT 24
Finished Jul 10 06:59:09 PM PDT 24
Peak memory 218252 kb
Host smart-5fc85b15-cac2-4072-9fc4-e4a4574364f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395982215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1395982215
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3935401108
Short name T773
Test name
Test status
Simulation time 315854518 ps
CPU time 13.62 seconds
Started Jul 10 06:59:03 PM PDT 24
Finished Jul 10 06:59:18 PM PDT 24
Peak memory 226052 kb
Host smart-6670a5a8-4935-4e5a-a287-32cf3fc88e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935401108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3935401108
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.859599310
Short name T718
Test name
Test status
Simulation time 106828981 ps
CPU time 6.07 seconds
Started Jul 10 06:59:03 PM PDT 24
Finished Jul 10 06:59:09 PM PDT 24
Peak memory 217808 kb
Host smart-d0a68550-62ce-4f1d-90c9-7364d1294a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859599310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.859599310
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3784411588
Short name T212
Test name
Test status
Simulation time 761855852 ps
CPU time 20.77 seconds
Started Jul 10 06:59:01 PM PDT 24
Finished Jul 10 06:59:23 PM PDT 24
Peak memory 246612 kb
Host smart-3a5f2def-d038-46d4-9d5f-e478ffe9422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784411588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3784411588
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2089279712
Short name T808
Test name
Test status
Simulation time 195724171 ps
CPU time 8.7 seconds
Started Jul 10 06:59:03 PM PDT 24
Finished Jul 10 06:59:13 PM PDT 24
Peak memory 250876 kb
Host smart-629351a5-74a8-4e75-a2cf-61d352a9764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089279712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2089279712
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.768014330
Short name T382
Test name
Test status
Simulation time 18534458611 ps
CPU time 601.08 seconds
Started Jul 10 06:59:01 PM PDT 24
Finished Jul 10 07:09:03 PM PDT 24
Peak memory 404752 kb
Host smart-ca20d109-9f24-4186-bce0-e09f2f0d198e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768014330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.768014330
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1704235360
Short name T672
Test name
Test status
Simulation time 41983448 ps
CPU time 0.79 seconds
Started Jul 10 06:59:00 PM PDT 24
Finished Jul 10 06:59:01 PM PDT 24
Peak memory 207180 kb
Host smart-ffc72b17-3d77-4f63-8691-1c3b01ff405e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704235360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1704235360
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.796695366
Short name T273
Test name
Test status
Simulation time 40787403 ps
CPU time 1.04 seconds
Started Jul 10 06:59:09 PM PDT 24
Finished Jul 10 06:59:12 PM PDT 24
Peak memory 208980 kb
Host smart-a0547761-85d7-476e-a09d-b612a2a3cc87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796695366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.796695366
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2708519065
Short name T527
Test name
Test status
Simulation time 1043172926 ps
CPU time 9.48 seconds
Started Jul 10 06:59:11 PM PDT 24
Finished Jul 10 06:59:23 PM PDT 24
Peak memory 218236 kb
Host smart-42345f53-1409-4e3e-8090-3530acbae183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708519065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2708519065
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1921073459
Short name T7
Test name
Test status
Simulation time 7586689994 ps
CPU time 12.87 seconds
Started Jul 10 06:59:10 PM PDT 24
Finished Jul 10 06:59:25 PM PDT 24
Peak memory 217724 kb
Host smart-94fb8e95-f406-40d9-b40f-577313c61d34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921073459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1921073459
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3236055218
Short name T841
Test name
Test status
Simulation time 3207302753 ps
CPU time 51.58 seconds
Started Jul 10 06:59:10 PM PDT 24
Finished Jul 10 07:00:04 PM PDT 24
Peak memory 218920 kb
Host smart-40a0848e-ad2a-4119-b78f-36ae0e95430f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236055218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3236055218
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1394157525
Short name T388
Test name
Test status
Simulation time 526254549 ps
CPU time 9.5 seconds
Started Jul 10 06:59:09 PM PDT 24
Finished Jul 10 06:59:21 PM PDT 24
Peak memory 218152 kb
Host smart-05344ec7-1298-4a11-942c-e63b82247248
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394157525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1394157525
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.82248438
Short name T772
Test name
Test status
Simulation time 153464968 ps
CPU time 3.39 seconds
Started Jul 10 06:59:08 PM PDT 24
Finished Jul 10 06:59:12 PM PDT 24
Peak memory 217708 kb
Host smart-67ce4cca-5d20-40f1-85b7-275c024d9fe5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82248438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.82248438
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3735059744
Short name T741
Test name
Test status
Simulation time 7959814713 ps
CPU time 77.26 seconds
Started Jul 10 06:59:09 PM PDT 24
Finished Jul 10 07:00:28 PM PDT 24
Peak memory 283732 kb
Host smart-e0194eef-cffe-41d1-bcb7-f180938ec397
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735059744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3735059744
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.252362661
Short name T753
Test name
Test status
Simulation time 1657207003 ps
CPU time 13.4 seconds
Started Jul 10 06:59:10 PM PDT 24
Finished Jul 10 06:59:27 PM PDT 24
Peak memory 226020 kb
Host smart-41cc9599-02e6-42c4-aba3-21714e253fe3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252362661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.252362661
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3713904564
Short name T31
Test name
Test status
Simulation time 313000415 ps
CPU time 3.11 seconds
Started Jul 10 06:59:08 PM PDT 24
Finished Jul 10 06:59:12 PM PDT 24
Peak memory 218216 kb
Host smart-4874cdc9-da9c-44eb-b084-153008403487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713904564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3713904564
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.668093783
Short name T318
Test name
Test status
Simulation time 2680514749 ps
CPU time 19.21 seconds
Started Jul 10 06:59:11 PM PDT 24
Finished Jul 10 06:59:32 PM PDT 24
Peak memory 226108 kb
Host smart-9883c72e-676f-470c-83c9-d6f9b4cc6c18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668093783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.668093783
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.601193791
Short name T747
Test name
Test status
Simulation time 2505133392 ps
CPU time 13.89 seconds
Started Jul 10 06:59:12 PM PDT 24
Finished Jul 10 06:59:27 PM PDT 24
Peak memory 226096 kb
Host smart-ac0119dc-105e-488d-8a9e-03e898bd0719
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601193791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.601193791
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2380932138
Short name T419
Test name
Test status
Simulation time 477369278 ps
CPU time 8.72 seconds
Started Jul 10 06:59:11 PM PDT 24
Finished Jul 10 06:59:22 PM PDT 24
Peak memory 218244 kb
Host smart-bba73b5c-71d0-44e0-bcd7-5f91844dc1d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380932138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2380932138
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.361578240
Short name T562
Test name
Test status
Simulation time 287918557 ps
CPU time 7.92 seconds
Started Jul 10 06:59:08 PM PDT 24
Finished Jul 10 06:59:17 PM PDT 24
Peak memory 225412 kb
Host smart-749b57a5-da22-4049-986e-a47c53f8c0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361578240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.361578240
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3466581257
Short name T81
Test name
Test status
Simulation time 146930892 ps
CPU time 2.48 seconds
Started Jul 10 06:59:00 PM PDT 24
Finished Jul 10 06:59:03 PM PDT 24
Peak memory 217728 kb
Host smart-6fd68d69-d0be-435a-bcb3-8e5de4162fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466581257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3466581257
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1866406508
Short name T730
Test name
Test status
Simulation time 373344637 ps
CPU time 20.46 seconds
Started Jul 10 06:59:09 PM PDT 24
Finished Jul 10 06:59:32 PM PDT 24
Peak memory 250980 kb
Host smart-abaeb7b3-87bc-4f84-9a4d-79752afbc25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866406508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1866406508
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2522255544
Short name T789
Test name
Test status
Simulation time 52643881 ps
CPU time 6.6 seconds
Started Jul 10 06:59:09 PM PDT 24
Finished Jul 10 06:59:18 PM PDT 24
Peak memory 247444 kb
Host smart-4eb500d1-61cb-41b3-bb2c-14148289ba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522255544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2522255544
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1677427715
Short name T840
Test name
Test status
Simulation time 183540511 ps
CPU time 4.82 seconds
Started Jul 10 06:59:09 PM PDT 24
Finished Jul 10 06:59:17 PM PDT 24
Peak memory 225952 kb
Host smart-a02181cf-37db-4beb-a47d-e7eaee096358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677427715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1677427715
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.62413729
Short name T59
Test name
Test status
Simulation time 8660964416 ps
CPU time 285.27 seconds
Started Jul 10 06:59:08 PM PDT 24
Finished Jul 10 07:03:54 PM PDT 24
Peak memory 267592 kb
Host smart-ee4d46b5-2e4b-490c-9ae1-c1db6be28e29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=62413729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.62413729
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4234299214
Short name T754
Test name
Test status
Simulation time 12478354 ps
CPU time 1.04 seconds
Started Jul 10 06:59:08 PM PDT 24
Finished Jul 10 06:59:11 PM PDT 24
Peak memory 211896 kb
Host smart-8b42eae6-50fe-454d-af78-a212c68dd882
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234299214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.4234299214
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1149763501
Short name T601
Test name
Test status
Simulation time 92588825 ps
CPU time 0.95 seconds
Started Jul 10 06:59:16 PM PDT 24
Finished Jul 10 06:59:18 PM PDT 24
Peak memory 209028 kb
Host smart-7cbf7580-3be9-46aa-82ca-b23e57ca982b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149763501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1149763501
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.4089307713
Short name T163
Test name
Test status
Simulation time 2371780164 ps
CPU time 14.37 seconds
Started Jul 10 06:59:08 PM PDT 24
Finished Jul 10 06:59:23 PM PDT 24
Peak memory 218960 kb
Host smart-da8eaee6-0d46-4336-aa92-a7368e5a7f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089307713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4089307713
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1502181747
Short name T818
Test name
Test status
Simulation time 3076819201 ps
CPU time 18.15 seconds
Started Jul 10 06:59:16 PM PDT 24
Finished Jul 10 06:59:36 PM PDT 24
Peak memory 217776 kb
Host smart-b8545fb3-2c14-48fd-acf9-366dd41f433b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502181747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1502181747
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2984887310
Short name T220
Test name
Test status
Simulation time 1408920914 ps
CPU time 45.37 seconds
Started Jul 10 06:59:17 PM PDT 24
Finished Jul 10 07:00:04 PM PDT 24
Peak memory 218240 kb
Host smart-ca22c41c-1cb2-4763-a9fa-eabfb8438d04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984887310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2984887310
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3641622703
Short name T569
Test name
Test status
Simulation time 5821266886 ps
CPU time 19.27 seconds
Started Jul 10 06:59:17 PM PDT 24
Finished Jul 10 06:59:38 PM PDT 24
Peak memory 218300 kb
Host smart-b5772ba7-b278-4823-9db3-f686eb5b272c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641622703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3641622703
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.212816327
Short name T756
Test name
Test status
Simulation time 935234080 ps
CPU time 3.7 seconds
Started Jul 10 06:59:16 PM PDT 24
Finished Jul 10 06:59:21 PM PDT 24
Peak memory 217688 kb
Host smart-1d81461c-7e40-4f9d-a9d0-4346c2fadf62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212816327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
212816327
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3105262503
Short name T109
Test name
Test status
Simulation time 10390728011 ps
CPU time 82.38 seconds
Started Jul 10 06:59:17 PM PDT 24
Finished Jul 10 07:00:41 PM PDT 24
Peak memory 278604 kb
Host smart-e8e6687d-5ce9-4590-9cdf-f5afcd156abe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105262503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3105262503
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2462363223
Short name T719
Test name
Test status
Simulation time 842767520 ps
CPU time 11.83 seconds
Started Jul 10 06:59:15 PM PDT 24
Finished Jul 10 06:59:28 PM PDT 24
Peak memory 250964 kb
Host smart-66d76d52-af57-4338-9805-fefec3483b9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462363223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2462363223
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.223553226
Short name T404
Test name
Test status
Simulation time 496804425 ps
CPU time 4.18 seconds
Started Jul 10 06:59:10 PM PDT 24
Finished Jul 10 06:59:17 PM PDT 24
Peak memory 218188 kb
Host smart-aa5467e4-6892-48d0-a69d-b0d56a9ad75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223553226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.223553226
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3262798836
Short name T864
Test name
Test status
Simulation time 1745291351 ps
CPU time 18.27 seconds
Started Jul 10 06:59:17 PM PDT 24
Finished Jul 10 06:59:36 PM PDT 24
Peak memory 226000 kb
Host smart-f8ddd579-9581-43c2-be26-a9e88936befa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262798836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3262798836
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1671448439
Short name T534
Test name
Test status
Simulation time 501532913 ps
CPU time 14.21 seconds
Started Jul 10 06:59:19 PM PDT 24
Finished Jul 10 06:59:33 PM PDT 24
Peak memory 226052 kb
Host smart-197f1214-caa4-4b92-a335-8da083a6bd22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671448439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1671448439
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.259220279
Short name T751
Test name
Test status
Simulation time 3160103472 ps
CPU time 12.55 seconds
Started Jul 10 06:59:16 PM PDT 24
Finished Jul 10 06:59:29 PM PDT 24
Peak memory 226076 kb
Host smart-30922f13-bd3f-47f9-a6d9-0a040957f621
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259220279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.259220279
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2065941276
Short name T384
Test name
Test status
Simulation time 344819197 ps
CPU time 8.35 seconds
Started Jul 10 06:59:11 PM PDT 24
Finished Jul 10 06:59:21 PM PDT 24
Peak memory 218300 kb
Host smart-9fbfced5-15de-4a76-8a08-7fef6265376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065941276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2065941276
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.728356319
Short name T291
Test name
Test status
Simulation time 90647618 ps
CPU time 1.7 seconds
Started Jul 10 06:59:12 PM PDT 24
Finished Jul 10 06:59:15 PM PDT 24
Peak memory 223144 kb
Host smart-6f619ba2-496b-40e1-b258-a548ff434591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728356319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.728356319
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2697789919
Short name T826
Test name
Test status
Simulation time 824044903 ps
CPU time 27.15 seconds
Started Jul 10 06:59:09 PM PDT 24
Finished Jul 10 06:59:38 PM PDT 24
Peak memory 250976 kb
Host smart-66aaeefc-763c-4c30-9cdf-9e3a7cd5d4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697789919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2697789919
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3870026414
Short name T407
Test name
Test status
Simulation time 68216926 ps
CPU time 7.33 seconds
Started Jul 10 06:59:08 PM PDT 24
Finished Jul 10 06:59:16 PM PDT 24
Peak memory 248692 kb
Host smart-c3fbda2b-5daa-4625-b996-da7ec2adbb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870026414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3870026414
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2060526969
Short name T347
Test name
Test status
Simulation time 5739505481 ps
CPU time 54.96 seconds
Started Jul 10 06:59:16 PM PDT 24
Finished Jul 10 07:00:13 PM PDT 24
Peak memory 267424 kb
Host smart-e49a513c-69ae-4e49-a36c-18d5f7275f41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060526969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2060526969
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2518475844
Short name T98
Test name
Test status
Simulation time 13479618 ps
CPU time 0.93 seconds
Started Jul 10 06:59:08 PM PDT 24
Finished Jul 10 06:59:10 PM PDT 24
Peak memory 211884 kb
Host smart-32abaf17-8c9b-4a70-ac8f-f180e80ebac5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518475844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2518475844
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1668374930
Short name T359
Test name
Test status
Simulation time 84957714 ps
CPU time 0.88 seconds
Started Jul 10 06:59:35 PM PDT 24
Finished Jul 10 06:59:37 PM PDT 24
Peak memory 208768 kb
Host smart-bfb9a0d3-d6f2-41d3-b740-b9c16a525d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668374930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1668374930
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3707624191
Short name T586
Test name
Test status
Simulation time 1539686157 ps
CPU time 13.69 seconds
Started Jul 10 06:59:19 PM PDT 24
Finished Jul 10 06:59:34 PM PDT 24
Peak memory 218056 kb
Host smart-7984124d-f3eb-42a3-837f-72a4b4a522c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707624191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3707624191
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.209786607
Short name T779
Test name
Test status
Simulation time 1270189908 ps
CPU time 12.22 seconds
Started Jul 10 06:59:27 PM PDT 24
Finished Jul 10 06:59:40 PM PDT 24
Peak memory 217292 kb
Host smart-7981fc1e-3e6e-4ddb-b1bc-5f4eecdf599b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209786607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.209786607
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1726381491
Short name T56
Test name
Test status
Simulation time 1309990445 ps
CPU time 24.01 seconds
Started Jul 10 06:59:26 PM PDT 24
Finished Jul 10 06:59:51 PM PDT 24
Peak memory 225632 kb
Host smart-5fe8f155-4ec1-4a33-aba0-a391b43abe34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726381491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1726381491
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2538798313
Short name T484
Test name
Test status
Simulation time 6846639713 ps
CPU time 6.45 seconds
Started Jul 10 06:59:26 PM PDT 24
Finished Jul 10 06:59:34 PM PDT 24
Peak memory 218196 kb
Host smart-9c7d8705-4e08-466e-8440-554e51c2e3e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538798313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2538798313
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1541514176
Short name T637
Test name
Test status
Simulation time 1237821981 ps
CPU time 8.67 seconds
Started Jul 10 06:59:25 PM PDT 24
Finished Jul 10 06:59:34 PM PDT 24
Peak memory 217704 kb
Host smart-f0c69bae-dea9-4128-b81d-431ec80c396e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541514176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1541514176
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1138385407
Short name T838
Test name
Test status
Simulation time 5540017763 ps
CPU time 41.67 seconds
Started Jul 10 06:59:28 PM PDT 24
Finished Jul 10 07:00:10 PM PDT 24
Peak memory 267380 kb
Host smart-1a7ebd60-5511-46bb-ac83-9386622df666
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138385407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1138385407
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3851820325
Short name T604
Test name
Test status
Simulation time 569130883 ps
CPU time 12.92 seconds
Started Jul 10 06:59:26 PM PDT 24
Finished Jul 10 06:59:40 PM PDT 24
Peak memory 250976 kb
Host smart-01ed9575-ff32-4394-b1a5-2bf95bf7aa4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851820325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3851820325
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1066340490
Short name T622
Test name
Test status
Simulation time 208512501 ps
CPU time 2.55 seconds
Started Jul 10 06:59:19 PM PDT 24
Finished Jul 10 06:59:22 PM PDT 24
Peak memory 218120 kb
Host smart-7ed6bfe3-23c7-4337-8909-f08becabf035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066340490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1066340490
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2821319521
Short name T97
Test name
Test status
Simulation time 575702942 ps
CPU time 13.23 seconds
Started Jul 10 06:59:26 PM PDT 24
Finished Jul 10 06:59:40 PM PDT 24
Peak memory 226048 kb
Host smart-904ed113-f01b-4b48-96ed-606bf1a151ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821319521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2821319521
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3774581757
Short name T532
Test name
Test status
Simulation time 820912933 ps
CPU time 6.49 seconds
Started Jul 10 06:59:26 PM PDT 24
Finished Jul 10 06:59:33 PM PDT 24
Peak memory 226032 kb
Host smart-3a99e461-aa64-43ec-87ab-821046d63ef9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774581757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3774581757
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2200429933
Short name T755
Test name
Test status
Simulation time 1036186522 ps
CPU time 10.23 seconds
Started Jul 10 06:59:26 PM PDT 24
Finished Jul 10 06:59:37 PM PDT 24
Peak memory 218232 kb
Host smart-6390a21f-bef6-4741-8237-b3998c1616a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200429933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2200429933
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.716627891
Short name T720
Test name
Test status
Simulation time 1807380021 ps
CPU time 12.74 seconds
Started Jul 10 06:59:26 PM PDT 24
Finished Jul 10 06:59:40 PM PDT 24
Peak memory 225516 kb
Host smart-b4f3a399-7bf7-4fa2-b549-6606c703df15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716627891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.716627891
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2075625352
Short name T546
Test name
Test status
Simulation time 90487202 ps
CPU time 3.03 seconds
Started Jul 10 06:59:17 PM PDT 24
Finished Jul 10 06:59:21 PM PDT 24
Peak memory 217780 kb
Host smart-747a3260-512c-49ba-b551-1690e2ab1cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075625352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2075625352
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2462355498
Short name T394
Test name
Test status
Simulation time 1232165042 ps
CPU time 33.4 seconds
Started Jul 10 06:59:15 PM PDT 24
Finished Jul 10 06:59:50 PM PDT 24
Peak memory 250996 kb
Host smart-da1d05cd-6700-4c88-b853-8a28491af2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462355498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2462355498
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2162015620
Short name T231
Test name
Test status
Simulation time 53115882 ps
CPU time 7.78 seconds
Started Jul 10 06:59:15 PM PDT 24
Finished Jul 10 06:59:24 PM PDT 24
Peak memory 250968 kb
Host smart-7f8cdeeb-4c7f-49e4-b865-7e9d7f2106c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162015620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2162015620
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.149799568
Short name T581
Test name
Test status
Simulation time 20149399 ps
CPU time 0.95 seconds
Started Jul 10 06:59:16 PM PDT 24
Finished Jul 10 06:59:19 PM PDT 24
Peak memory 212036 kb
Host smart-2ee46b39-a47c-43b4-bac7-2246a6251e37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149799568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.149799568
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2117980542
Short name T71
Test name
Test status
Simulation time 19269674 ps
CPU time 0.91 seconds
Started Jul 10 06:59:31 PM PDT 24
Finished Jul 10 06:59:32 PM PDT 24
Peak memory 208972 kb
Host smart-468d9d05-f924-4e14-beac-ac6dfb516e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117980542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2117980542
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3820511469
Short name T850
Test name
Test status
Simulation time 827947257 ps
CPU time 7.92 seconds
Started Jul 10 06:59:33 PM PDT 24
Finished Jul 10 06:59:42 PM PDT 24
Peak memory 226044 kb
Host smart-c3ec4b48-9d0c-4668-b256-39d06801bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820511469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3820511469
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3182089709
Short name T765
Test name
Test status
Simulation time 302330593 ps
CPU time 3.76 seconds
Started Jul 10 06:59:34 PM PDT 24
Finished Jul 10 06:59:39 PM PDT 24
Peak memory 217080 kb
Host smart-b77a9724-3ddd-47e0-86a3-340cd4d40f63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182089709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3182089709
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1916771562
Short name T727
Test name
Test status
Simulation time 9086762204 ps
CPU time 28.04 seconds
Started Jul 10 06:59:35 PM PDT 24
Finished Jul 10 07:00:04 PM PDT 24
Peak memory 218380 kb
Host smart-fc8b96fd-f86a-4579-8a90-2a044ec1f83b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916771562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1916771562
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2520007809
Short name T107
Test name
Test status
Simulation time 207394832 ps
CPU time 3.85 seconds
Started Jul 10 06:59:33 PM PDT 24
Finished Jul 10 06:59:38 PM PDT 24
Peak memory 221764 kb
Host smart-1d0ab7c3-19d4-4869-82d0-651be19420ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520007809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2520007809
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2689898812
Short name T79
Test name
Test status
Simulation time 254893266 ps
CPU time 7.04 seconds
Started Jul 10 06:59:32 PM PDT 24
Finished Jul 10 06:59:41 PM PDT 24
Peak memory 217656 kb
Host smart-a80b9710-13ef-4540-afc8-b0f5f53e86f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689898812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2689898812
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.706582948
Short name T216
Test name
Test status
Simulation time 2134187993 ps
CPU time 37.16 seconds
Started Jul 10 06:59:32 PM PDT 24
Finished Jul 10 07:00:11 PM PDT 24
Peak memory 251080 kb
Host smart-9bef0eac-c947-44c5-9d52-465e826eddb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706582948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.706582948
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.36442775
Short name T704
Test name
Test status
Simulation time 277205787 ps
CPU time 14.4 seconds
Started Jul 10 06:59:33 PM PDT 24
Finished Jul 10 06:59:49 PM PDT 24
Peak memory 251020 kb
Host smart-0f8c1f1f-5733-409e-aa4c-d8ea1fe802a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36442775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_j
tag_state_post_trans.36442775
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2459818835
Short name T821
Test name
Test status
Simulation time 151934090 ps
CPU time 2.3 seconds
Started Jul 10 06:59:33 PM PDT 24
Finished Jul 10 06:59:36 PM PDT 24
Peak memory 218300 kb
Host smart-27219ac4-bd55-4754-816a-7ee8d7531ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459818835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2459818835
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2477985893
Short name T446
Test name
Test status
Simulation time 1510976337 ps
CPU time 13.47 seconds
Started Jul 10 06:59:32 PM PDT 24
Finished Jul 10 06:59:47 PM PDT 24
Peak memory 225968 kb
Host smart-28da8f91-c60e-420e-a5a4-3d15f9e65ceb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477985893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2477985893
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2442180221
Short name T363
Test name
Test status
Simulation time 1652046833 ps
CPU time 9.67 seconds
Started Jul 10 06:59:34 PM PDT 24
Finished Jul 10 06:59:45 PM PDT 24
Peak memory 218236 kb
Host smart-df22f7ee-72f1-42f2-b13d-018ace5c2b93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442180221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2442180221
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.308081729
Short name T504
Test name
Test status
Simulation time 1509832195 ps
CPU time 9.67 seconds
Started Jul 10 06:59:34 PM PDT 24
Finished Jul 10 06:59:45 PM PDT 24
Peak memory 226104 kb
Host smart-408b5b1d-804e-4027-9930-99a11aa86d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308081729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.308081729
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3007133384
Short name T793
Test name
Test status
Simulation time 218765861 ps
CPU time 2.69 seconds
Started Jul 10 06:59:34 PM PDT 24
Finished Jul 10 06:59:38 PM PDT 24
Peak memory 214864 kb
Host smart-3f8dd309-3de6-4504-a8e9-306ae267bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007133384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3007133384
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1356957352
Short name T282
Test name
Test status
Simulation time 2463084848 ps
CPU time 34.03 seconds
Started Jul 10 06:59:32 PM PDT 24
Finished Jul 10 07:00:08 PM PDT 24
Peak memory 246324 kb
Host smart-ddb4deb5-3207-4f61-a2fa-aafad3e6d914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356957352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1356957352
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3665914703
Short name T173
Test name
Test status
Simulation time 129416994 ps
CPU time 9.31 seconds
Started Jul 10 06:59:33 PM PDT 24
Finished Jul 10 06:59:43 PM PDT 24
Peak memory 251044 kb
Host smart-5f075f15-f46e-4fa4-9d24-adbb52da9c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665914703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3665914703
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2848908350
Short name T776
Test name
Test status
Simulation time 52497245081 ps
CPU time 132.99 seconds
Started Jul 10 06:59:33 PM PDT 24
Finished Jul 10 07:01:48 PM PDT 24
Peak memory 267352 kb
Host smart-7f104e87-3f59-4939-b30a-5221d5836a19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848908350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2848908350
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1954037173
Short name T114
Test name
Test status
Simulation time 7027386877 ps
CPU time 273.1 seconds
Started Jul 10 06:59:34 PM PDT 24
Finished Jul 10 07:04:08 PM PDT 24
Peak memory 253060 kb
Host smart-dbbc96a4-e2ae-419a-b35f-2a31b9ed55bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1954037173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1954037173
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1086131100
Short name T313
Test name
Test status
Simulation time 37072348 ps
CPU time 0.88 seconds
Started Jul 10 06:59:34 PM PDT 24
Finished Jul 10 06:59:36 PM PDT 24
Peak memory 213104 kb
Host smart-390b5a79-66a4-471e-b7c0-d31d58ed4d7d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086131100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1086131100
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1405598638
Short name T375
Test name
Test status
Simulation time 18200894 ps
CPU time 1.13 seconds
Started Jul 10 06:56:25 PM PDT 24
Finished Jul 10 06:56:27 PM PDT 24
Peak memory 208976 kb
Host smart-e0f30b00-aa3b-4194-a0ec-c73d2ba4d2e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405598638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1405598638
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2269533377
Short name T742
Test name
Test status
Simulation time 19089129 ps
CPU time 0.8 seconds
Started Jul 10 06:56:08 PM PDT 24
Finished Jul 10 06:56:10 PM PDT 24
Peak memory 208944 kb
Host smart-430ac84f-260f-4964-9803-e19738459954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269533377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2269533377
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2185137541
Short name T43
Test name
Test status
Simulation time 3502075990 ps
CPU time 10.02 seconds
Started Jul 10 06:56:10 PM PDT 24
Finished Jul 10 06:56:21 PM PDT 24
Peak memory 219048 kb
Host smart-bab6d461-715e-4195-b4c0-8226da13020f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185137541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2185137541
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.304840349
Short name T503
Test name
Test status
Simulation time 447385934 ps
CPU time 5.98 seconds
Started Jul 10 06:56:15 PM PDT 24
Finished Jul 10 06:56:22 PM PDT 24
Peak memory 217200 kb
Host smart-a2f7893b-3f94-4d4b-946e-91ebc59bbe0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304840349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.304840349
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.103650672
Short name T495
Test name
Test status
Simulation time 3035136649 ps
CPU time 27.42 seconds
Started Jul 10 06:56:15 PM PDT 24
Finished Jul 10 06:56:43 PM PDT 24
Peak memory 218936 kb
Host smart-ae4cbadb-ecb4-4b36-9678-9a525426f6af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103650672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.103650672
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.809479221
Short name T784
Test name
Test status
Simulation time 1176840325 ps
CPU time 8.54 seconds
Started Jul 10 06:56:17 PM PDT 24
Finished Jul 10 06:56:26 PM PDT 24
Peak memory 217636 kb
Host smart-d45ce9f9-55e1-4ab2-b02c-2fadec1ef408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809479221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.809479221
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2694083723
Short name T677
Test name
Test status
Simulation time 64776205 ps
CPU time 2.68 seconds
Started Jul 10 06:56:10 PM PDT 24
Finished Jul 10 06:56:13 PM PDT 24
Peak memory 221512 kb
Host smart-110f9273-e15e-467a-80f0-8ffde4635fda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694083723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2694083723
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.9400032
Short name T584
Test name
Test status
Simulation time 1224417378 ps
CPU time 5.26 seconds
Started Jul 10 06:56:16 PM PDT 24
Finished Jul 10 06:56:22 PM PDT 24
Peak memory 217732 kb
Host smart-61141629-5907-492e-8aa5-125dc9866df8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9400032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_re
gwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_regwen_during_op.9400032
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.875371558
Short name T736
Test name
Test status
Simulation time 549547440 ps
CPU time 8.2 seconds
Started Jul 10 06:56:08 PM PDT 24
Finished Jul 10 06:56:17 PM PDT 24
Peak memory 217656 kb
Host smart-3407b5a3-57f1-4b13-97ff-94d981d71014
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875371558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.875371558
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.119257464
Short name T831
Test name
Test status
Simulation time 3657389430 ps
CPU time 40.18 seconds
Started Jul 10 06:56:10 PM PDT 24
Finished Jul 10 06:56:52 PM PDT 24
Peak memory 278196 kb
Host smart-0cd52eab-daab-4827-a085-21f5f8db167e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119257464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.119257464
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1248630562
Short name T631
Test name
Test status
Simulation time 1607138631 ps
CPU time 13.42 seconds
Started Jul 10 06:56:07 PM PDT 24
Finished Jul 10 06:56:22 PM PDT 24
Peak memory 222236 kb
Host smart-9e9f4ce5-f050-42bb-9e37-89c25ae1c371
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248630562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1248630562
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3785298578
Short name T267
Test name
Test status
Simulation time 68590966 ps
CPU time 3.68 seconds
Started Jul 10 06:56:11 PM PDT 24
Finished Jul 10 06:56:15 PM PDT 24
Peak memory 218212 kb
Host smart-44dc61ed-7833-4d12-8a5e-d56641ee0de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785298578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3785298578
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1472591063
Short name T653
Test name
Test status
Simulation time 1482357300 ps
CPU time 14.48 seconds
Started Jul 10 06:56:09 PM PDT 24
Finished Jul 10 06:56:24 PM PDT 24
Peak memory 214832 kb
Host smart-a8a8c9dc-a7cd-43bd-b99d-f39a560b028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472591063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1472591063
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2964946655
Short name T100
Test name
Test status
Simulation time 210851625 ps
CPU time 39.45 seconds
Started Jul 10 06:56:24 PM PDT 24
Finished Jul 10 06:57:04 PM PDT 24
Peak memory 268872 kb
Host smart-d04df5cb-2b46-4246-b73f-c1716b3c1319
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964946655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2964946655
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2334347240
Short name T300
Test name
Test status
Simulation time 2109352770 ps
CPU time 12.64 seconds
Started Jul 10 06:56:24 PM PDT 24
Finished Jul 10 06:56:37 PM PDT 24
Peak memory 218236 kb
Host smart-63546d06-ebdd-4ee3-bb7b-b182a97f0722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334347240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2334347240
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1853735595
Short name T528
Test name
Test status
Simulation time 1261067390 ps
CPU time 9.14 seconds
Started Jul 10 06:56:25 PM PDT 24
Finished Jul 10 06:56:35 PM PDT 24
Peak memory 218232 kb
Host smart-5225085c-11b6-49de-8c23-ef63f60bc4e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853735595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
853735595
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3897797518
Short name T558
Test name
Test status
Simulation time 554038874 ps
CPU time 8.66 seconds
Started Jul 10 06:56:09 PM PDT 24
Finished Jul 10 06:56:18 PM PDT 24
Peak memory 218360 kb
Host smart-50a7cb52-8ebc-4258-b6b7-3d1721395d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897797518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3897797518
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2613198610
Short name T66
Test name
Test status
Simulation time 19670512 ps
CPU time 1.36 seconds
Started Jul 10 06:56:01 PM PDT 24
Finished Jul 10 06:56:03 PM PDT 24
Peak memory 213784 kb
Host smart-21707f3f-214e-4090-ba01-0503b14c9c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613198610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2613198610
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3934078954
Short name T3
Test name
Test status
Simulation time 988894849 ps
CPU time 31.88 seconds
Started Jul 10 06:56:02 PM PDT 24
Finished Jul 10 06:56:35 PM PDT 24
Peak memory 251040 kb
Host smart-8042e691-87f3-4382-9077-25a771c45750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934078954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3934078954
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3184050618
Short name T735
Test name
Test status
Simulation time 146017043 ps
CPU time 8.58 seconds
Started Jul 10 06:56:01 PM PDT 24
Finished Jul 10 06:56:11 PM PDT 24
Peak memory 251052 kb
Host smart-d999c410-cc48-423f-887d-e49b3a5eb632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184050618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3184050618
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.926946068
Short name T349
Test name
Test status
Simulation time 12280354171 ps
CPU time 86.63 seconds
Started Jul 10 06:56:30 PM PDT 24
Finished Jul 10 06:57:57 PM PDT 24
Peak memory 278996 kb
Host smart-9cec5eaf-3313-4df7-aa36-ee1419259b7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926946068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.926946068
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2082454518
Short name T665
Test name
Test status
Simulation time 128396703 ps
CPU time 0.91 seconds
Started Jul 10 06:56:00 PM PDT 24
Finished Jul 10 06:56:01 PM PDT 24
Peak memory 211920 kb
Host smart-380afbe4-bdf4-45ce-8667-41f5a2c8c666
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082454518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2082454518
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1404818763
Short name T860
Test name
Test status
Simulation time 43413495 ps
CPU time 0.83 seconds
Started Jul 10 06:59:52 PM PDT 24
Finished Jul 10 06:59:53 PM PDT 24
Peak memory 208956 kb
Host smart-c06a4750-ea40-4186-8cba-d3da41fce059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404818763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1404818763
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.638808911
Short name T13
Test name
Test status
Simulation time 410953389 ps
CPU time 9.79 seconds
Started Jul 10 06:59:44 PM PDT 24
Finished Jul 10 06:59:55 PM PDT 24
Peak memory 218216 kb
Host smart-a83058d4-08c6-4ef6-b596-8634246b8aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638808911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.638808911
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3039024720
Short name T463
Test name
Test status
Simulation time 2044908849 ps
CPU time 5.33 seconds
Started Jul 10 06:59:45 PM PDT 24
Finished Jul 10 06:59:51 PM PDT 24
Peak memory 217180 kb
Host smart-d4a158c1-41db-4c67-8d56-cd6f76aa426b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039024720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3039024720
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3499693529
Short name T309
Test name
Test status
Simulation time 429768501 ps
CPU time 3.17 seconds
Started Jul 10 06:59:40 PM PDT 24
Finished Jul 10 06:59:43 PM PDT 24
Peak memory 218160 kb
Host smart-a7934775-d1c2-4e02-bd79-5f9b22f0c1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499693529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3499693529
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2267561802
Short name T517
Test name
Test status
Simulation time 901632703 ps
CPU time 15.78 seconds
Started Jul 10 06:59:39 PM PDT 24
Finished Jul 10 06:59:56 PM PDT 24
Peak memory 226032 kb
Host smart-08895d01-af77-46bd-95af-052669b02e50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267561802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2267561802
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3023931479
Short name T859
Test name
Test status
Simulation time 1473746922 ps
CPU time 12.44 seconds
Started Jul 10 06:59:42 PM PDT 24
Finished Jul 10 06:59:55 PM PDT 24
Peak memory 225924 kb
Host smart-86b9598c-56f1-497f-8172-9a820c82bc54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023931479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3023931479
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1600694956
Short name T685
Test name
Test status
Simulation time 493340236 ps
CPU time 11.54 seconds
Started Jul 10 06:59:40 PM PDT 24
Finished Jul 10 06:59:52 PM PDT 24
Peak memory 218300 kb
Host smart-0ae823c8-8432-4039-8642-be7cc5aaf1ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600694956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1600694956
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.258292530
Short name T217
Test name
Test status
Simulation time 637999920 ps
CPU time 7.2 seconds
Started Jul 10 06:59:41 PM PDT 24
Finished Jul 10 06:59:49 PM PDT 24
Peak memory 218372 kb
Host smart-379fbc42-5f9a-407f-b783-bc4194484e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258292530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.258292530
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.4065337354
Short name T494
Test name
Test status
Simulation time 58735986 ps
CPU time 3.1 seconds
Started Jul 10 06:59:44 PM PDT 24
Finished Jul 10 06:59:49 PM PDT 24
Peak memory 217716 kb
Host smart-df62359c-468f-44ad-900a-7b0e856d5035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065337354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.4065337354
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1053983714
Short name T695
Test name
Test status
Simulation time 1282131751 ps
CPU time 19.85 seconds
Started Jul 10 06:59:40 PM PDT 24
Finished Jul 10 07:00:00 PM PDT 24
Peak memory 250992 kb
Host smart-a57620d2-186b-4d85-9967-1581202adce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053983714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1053983714
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1488880177
Short name T809
Test name
Test status
Simulation time 83152416 ps
CPU time 6.52 seconds
Started Jul 10 06:59:41 PM PDT 24
Finished Jul 10 06:59:48 PM PDT 24
Peak memory 246884 kb
Host smart-b2d90b15-a65f-46a2-8e39-f79319f17151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488880177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1488880177
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3487653573
Short name T352
Test name
Test status
Simulation time 19662060051 ps
CPU time 70.94 seconds
Started Jul 10 06:59:41 PM PDT 24
Finished Jul 10 07:00:53 PM PDT 24
Peak memory 250996 kb
Host smart-00d90465-ff26-44a4-8872-821fce8b439b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487653573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3487653573
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1829121161
Short name T47
Test name
Test status
Simulation time 48443662284 ps
CPU time 240.51 seconds
Started Jul 10 06:59:41 PM PDT 24
Finished Jul 10 07:03:42 PM PDT 24
Peak memory 280400 kb
Host smart-b1623a4e-cb8f-487c-bf82-9d74effe98d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1829121161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1829121161
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3101161373
Short name T642
Test name
Test status
Simulation time 18089203 ps
CPU time 0.94 seconds
Started Jul 10 06:59:41 PM PDT 24
Finished Jul 10 06:59:42 PM PDT 24
Peak memory 212932 kb
Host smart-08d0ad0a-8257-4f93-8073-15df5e793eee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101161373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3101161373
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.828258562
Short name T385
Test name
Test status
Simulation time 14760614 ps
CPU time 1.12 seconds
Started Jul 10 06:59:51 PM PDT 24
Finished Jul 10 06:59:53 PM PDT 24
Peak memory 209072 kb
Host smart-84d1c9b7-8d89-423d-b5c3-8e9214e64897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828258562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.828258562
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.294803970
Short name T524
Test name
Test status
Simulation time 917564283 ps
CPU time 16.78 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 07:00:08 PM PDT 24
Peak memory 226028 kb
Host smart-70669ae7-3dc5-426b-a9ee-8ecd42e9dca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294803970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.294803970
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.147887826
Short name T312
Test name
Test status
Simulation time 624267044 ps
CPU time 7.55 seconds
Started Jul 10 06:59:51 PM PDT 24
Finished Jul 10 06:59:59 PM PDT 24
Peak memory 217048 kb
Host smart-44fb33a2-500e-4c58-9e6e-a6753f3f7a0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147887826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.147887826
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1137355956
Short name T537
Test name
Test status
Simulation time 47925035 ps
CPU time 2.38 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 06:59:53 PM PDT 24
Peak memory 218216 kb
Host smart-c3032c5e-234d-4520-a2e0-6832378a8a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137355956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1137355956
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1054833170
Short name T366
Test name
Test status
Simulation time 971293004 ps
CPU time 12 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 07:00:03 PM PDT 24
Peak memory 226044 kb
Host smart-eee11013-6d2d-4e2b-b2b9-9c9748e0d16d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054833170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1054833170
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.135936780
Short name T856
Test name
Test status
Simulation time 1456879648 ps
CPU time 11.57 seconds
Started Jul 10 06:59:48 PM PDT 24
Finished Jul 10 07:00:01 PM PDT 24
Peak memory 218232 kb
Host smart-3d3334c8-b0f7-4e63-b5cd-fcef5495aea1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135936780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.135936780
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.162556830
Short name T454
Test name
Test status
Simulation time 870767392 ps
CPU time 16.36 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 07:00:07 PM PDT 24
Peak memory 218316 kb
Host smart-2345607d-fe89-4e3c-97e2-00fa7804c759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162556830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.162556830
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3019609985
Short name T290
Test name
Test status
Simulation time 71937517 ps
CPU time 2.23 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 06:59:53 PM PDT 24
Peak memory 217716 kb
Host smart-856a3e4b-d69c-43d2-bf1e-950d16298a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019609985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3019609985
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.737137101
Short name T500
Test name
Test status
Simulation time 570663814 ps
CPU time 22.43 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 07:00:13 PM PDT 24
Peak memory 251048 kb
Host smart-c0fa4ea5-6fb6-4c13-9b6a-614b38cd62ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737137101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.737137101
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.453354143
Short name T639
Test name
Test status
Simulation time 144198810 ps
CPU time 3.07 seconds
Started Jul 10 06:59:48 PM PDT 24
Finished Jul 10 06:59:52 PM PDT 24
Peak memory 226360 kb
Host smart-576f1c00-23aa-4f61-8062-ea6f0e3304ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453354143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.453354143
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.756722428
Short name T22
Test name
Test status
Simulation time 604683689 ps
CPU time 44.33 seconds
Started Jul 10 06:59:51 PM PDT 24
Finished Jul 10 07:00:36 PM PDT 24
Peak memory 250984 kb
Host smart-7456f4a2-79d2-47e6-a3c5-2085f9276880
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756722428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.756722428
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3671285164
Short name T222
Test name
Test status
Simulation time 21024620 ps
CPU time 1 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 06:59:52 PM PDT 24
Peak memory 217720 kb
Host smart-c4f7e8c2-2639-483c-9989-38a24c140815
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671285164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3671285164
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3867405385
Short name T768
Test name
Test status
Simulation time 21193837 ps
CPU time 1.06 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:01 PM PDT 24
Peak memory 208968 kb
Host smart-bdf0f30f-f1ac-4306-926e-37bb9a71b2b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867405385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3867405385
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3409218416
Short name T396
Test name
Test status
Simulation time 1379690519 ps
CPU time 16.76 seconds
Started Jul 10 07:00:00 PM PDT 24
Finished Jul 10 07:00:18 PM PDT 24
Peak memory 218220 kb
Host smart-a26b3b22-d345-4a7b-b84b-098ace849e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409218416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3409218416
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3536696615
Short name T565
Test name
Test status
Simulation time 563373839 ps
CPU time 14.28 seconds
Started Jul 10 07:00:01 PM PDT 24
Finished Jul 10 07:00:16 PM PDT 24
Peak memory 217716 kb
Host smart-de675776-1e0a-4625-a935-d8a829d8fffe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536696615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3536696615
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3534417636
Short name T590
Test name
Test status
Simulation time 326274469 ps
CPU time 3.12 seconds
Started Jul 10 07:00:02 PM PDT 24
Finished Jul 10 07:00:06 PM PDT 24
Peak memory 222424 kb
Host smart-20edcc8d-f1f7-49eb-83f5-e9b3856c42b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534417636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3534417636
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2062848803
Short name T759
Test name
Test status
Simulation time 3822779325 ps
CPU time 15.89 seconds
Started Jul 10 07:00:01 PM PDT 24
Finished Jul 10 07:00:18 PM PDT 24
Peak memory 226076 kb
Host smart-b00f8643-0bb8-4002-8a9f-9a88d5e40b3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062848803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2062848803
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3117215502
Short name T235
Test name
Test status
Simulation time 314304062 ps
CPU time 8.97 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:09 PM PDT 24
Peak memory 226100 kb
Host smart-b269687a-8448-4f54-bcda-c440cd161843
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117215502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3117215502
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1655438414
Short name T319
Test name
Test status
Simulation time 367138065 ps
CPU time 12.8 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:13 PM PDT 24
Peak memory 218236 kb
Host smart-b4de37d4-8a62-49b9-a7dc-b13c51a248db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655438414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1655438414
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2302851549
Short name T327
Test name
Test status
Simulation time 240629569 ps
CPU time 8.77 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:09 PM PDT 24
Peak memory 224712 kb
Host smart-ecadaecc-dc56-44bf-bba0-6f9b5011d959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302851549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2302851549
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2282605975
Short name T468
Test name
Test status
Simulation time 62338011 ps
CPU time 2.18 seconds
Started Jul 10 06:59:50 PM PDT 24
Finished Jul 10 06:59:53 PM PDT 24
Peak memory 217740 kb
Host smart-63a9f619-361c-4166-8aed-c47e967c895f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282605975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2282605975
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4011378182
Short name T439
Test name
Test status
Simulation time 170879857 ps
CPU time 22.39 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:23 PM PDT 24
Peak memory 250976 kb
Host smart-3fcf5141-ff8c-48e1-ad7b-f8787a03dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011378182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4011378182
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1432007582
Short name T552
Test name
Test status
Simulation time 69743885 ps
CPU time 2.98 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:03 PM PDT 24
Peak memory 222360 kb
Host smart-b34df1e0-ad61-48d6-9f23-67ad73ceb155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432007582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1432007582
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2820119511
Short name T284
Test name
Test status
Simulation time 4433221024 ps
CPU time 38.85 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:40 PM PDT 24
Peak memory 251036 kb
Host smart-10661a42-20d3-4a3e-801b-099228d55fe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820119511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2820119511
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.401809508
Short name T149
Test name
Test status
Simulation time 47127608778 ps
CPU time 611.56 seconds
Started Jul 10 07:00:00 PM PDT 24
Finished Jul 10 07:10:13 PM PDT 24
Peak memory 496872 kb
Host smart-43461f06-8ab9-4b22-b65d-b594ad240cdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=401809508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.401809508
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1144041774
Short name T640
Test name
Test status
Simulation time 30890888 ps
CPU time 0.92 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:02 PM PDT 24
Peak memory 211916 kb
Host smart-a3e7e916-b9e7-44d9-aaf1-908bd74190d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144041774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1144041774
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3441077684
Short name T424
Test name
Test status
Simulation time 66654051 ps
CPU time 0.96 seconds
Started Jul 10 07:00:09 PM PDT 24
Finished Jul 10 07:00:12 PM PDT 24
Peak memory 208988 kb
Host smart-dc99ce2a-20f1-438c-870d-b59b53954e82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441077684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3441077684
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2499676617
Short name T214
Test name
Test status
Simulation time 1762545139 ps
CPU time 16.44 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:17 PM PDT 24
Peak memory 226036 kb
Host smart-38215fb4-dc84-4eab-ad42-5bf930531e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499676617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2499676617
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.372772669
Short name T592
Test name
Test status
Simulation time 5028775272 ps
CPU time 11.78 seconds
Started Jul 10 07:00:00 PM PDT 24
Finished Jul 10 07:00:13 PM PDT 24
Peak memory 217724 kb
Host smart-7e245c16-2805-4353-9d3e-bbb31c96216e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372772669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.372772669
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.88287455
Short name T608
Test name
Test status
Simulation time 431682787 ps
CPU time 3.58 seconds
Started Jul 10 07:00:07 PM PDT 24
Finished Jul 10 07:00:11 PM PDT 24
Peak memory 222720 kb
Host smart-b46e1fb4-42ff-4a55-8bdd-64e3e2798540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88287455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.88287455
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1777230532
Short name T625
Test name
Test status
Simulation time 2995103286 ps
CPU time 13.15 seconds
Started Jul 10 07:00:12 PM PDT 24
Finished Jul 10 07:00:26 PM PDT 24
Peak memory 226028 kb
Host smart-915c2cc2-d096-4363-a0d2-b66b226f0735
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777230532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1777230532
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3758309064
Short name T516
Test name
Test status
Simulation time 211186625 ps
CPU time 7.96 seconds
Started Jul 10 06:59:59 PM PDT 24
Finished Jul 10 07:00:09 PM PDT 24
Peak memory 218168 kb
Host smart-2145b002-f767-47b8-b242-ce12eae2c21b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758309064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3758309064
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2873229626
Short name T341
Test name
Test status
Simulation time 984328582 ps
CPU time 13.89 seconds
Started Jul 10 07:00:00 PM PDT 24
Finished Jul 10 07:00:16 PM PDT 24
Peak memory 226020 kb
Host smart-33777b8d-406b-46bc-b9ef-e384892c953e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873229626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2873229626
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.170349861
Short name T551
Test name
Test status
Simulation time 57870558 ps
CPU time 1.51 seconds
Started Jul 10 06:59:58 PM PDT 24
Finished Jul 10 07:00:00 PM PDT 24
Peak memory 213876 kb
Host smart-bc2702ad-3249-4171-a6e3-c3d5d17b78e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170349861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.170349861
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.987827431
Short name T210
Test name
Test status
Simulation time 308027221 ps
CPU time 27.05 seconds
Started Jul 10 07:00:00 PM PDT 24
Finished Jul 10 07:00:28 PM PDT 24
Peak memory 251080 kb
Host smart-9573d782-40ad-4041-bdf7-58be36866e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987827431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.987827431
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3995605991
Short name T335
Test name
Test status
Simulation time 104477363 ps
CPU time 9.17 seconds
Started Jul 10 07:00:00 PM PDT 24
Finished Jul 10 07:00:10 PM PDT 24
Peak memory 250972 kb
Host smart-00becdb3-b7be-4959-a95d-1f8d9ea166d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995605991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3995605991
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3692912327
Short name T844
Test name
Test status
Simulation time 59260142165 ps
CPU time 346.43 seconds
Started Jul 10 07:00:11 PM PDT 24
Finished Jul 10 07:05:59 PM PDT 24
Peak memory 283784 kb
Host smart-c78d8440-ace3-41b4-bcf6-44493700a56a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692912327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3692912327
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.266358470
Short name T440
Test name
Test status
Simulation time 28872863 ps
CPU time 0.94 seconds
Started Jul 10 07:00:02 PM PDT 24
Finished Jul 10 07:00:04 PM PDT 24
Peak memory 212828 kb
Host smart-9071eee1-b80e-420c-85d8-d35bc99180b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266358470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.266358470
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3759511994
Short name T215
Test name
Test status
Simulation time 28661796 ps
CPU time 1.03 seconds
Started Jul 10 07:00:09 PM PDT 24
Finished Jul 10 07:00:11 PM PDT 24
Peak memory 208948 kb
Host smart-fc0753ac-1af2-46e7-9c8e-04e8e26718e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759511994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3759511994
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1717728047
Short name T342
Test name
Test status
Simulation time 578299616 ps
CPU time 12.8 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:00:25 PM PDT 24
Peak memory 218212 kb
Host smart-9fb1286c-35b3-4dd1-b455-692937671ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717728047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1717728047
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3210053921
Short name T835
Test name
Test status
Simulation time 256365661 ps
CPU time 3.33 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:00:15 PM PDT 24
Peak memory 218232 kb
Host smart-0b415e71-903e-47d4-b444-3f00a107261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210053921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3210053921
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1474240166
Short name T732
Test name
Test status
Simulation time 1862305956 ps
CPU time 13.6 seconds
Started Jul 10 07:00:09 PM PDT 24
Finished Jul 10 07:00:24 PM PDT 24
Peak memory 226020 kb
Host smart-544bc869-b476-465a-a6fa-248db82a984a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474240166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1474240166
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1570993504
Short name T373
Test name
Test status
Simulation time 1686980647 ps
CPU time 8.89 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:00:21 PM PDT 24
Peak memory 218224 kb
Host smart-94eb4c3b-ad6b-42d7-bdf2-002c31048f7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570993504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1570993504
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3725995395
Short name T82
Test name
Test status
Simulation time 185408679 ps
CPU time 8.67 seconds
Started Jul 10 07:00:12 PM PDT 24
Finished Jul 10 07:00:22 PM PDT 24
Peak memory 226040 kb
Host smart-d14cf577-5a9d-4835-87c0-14b54f341525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725995395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3725995395
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1792398531
Short name T706
Test name
Test status
Simulation time 52619931 ps
CPU time 2.83 seconds
Started Jul 10 07:00:09 PM PDT 24
Finished Jul 10 07:00:14 PM PDT 24
Peak memory 217740 kb
Host smart-8a7349b5-0374-4efe-a7c4-52b13c260899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792398531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1792398531
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.830311155
Short name T471
Test name
Test status
Simulation time 4458299220 ps
CPU time 24.51 seconds
Started Jul 10 07:00:09 PM PDT 24
Finished Jul 10 07:00:34 PM PDT 24
Peak memory 251036 kb
Host smart-623c7e23-c992-4a04-9376-b2a39875140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830311155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.830311155
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.690566131
Short name T325
Test name
Test status
Simulation time 62736957 ps
CPU time 8.26 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:00:21 PM PDT 24
Peak memory 250992 kb
Host smart-45e74f25-57a6-491b-8579-4201a8c3a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690566131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.690566131
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1245528686
Short name T248
Test name
Test status
Simulation time 2833653650 ps
CPU time 45.11 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:00:57 PM PDT 24
Peak memory 268304 kb
Host smart-a926c623-4ab2-432e-936c-8f8bbcf88918
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245528686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1245528686
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4174210956
Short name T197
Test name
Test status
Simulation time 16487193 ps
CPU time 0.94 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:00:13 PM PDT 24
Peak memory 212900 kb
Host smart-2086ffcd-d4ca-4b09-9cdb-92b0e8558d75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174210956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.4174210956
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2595242890
Short name T99
Test name
Test status
Simulation time 17530274 ps
CPU time 0.86 seconds
Started Jul 10 07:00:24 PM PDT 24
Finished Jul 10 07:00:27 PM PDT 24
Peak memory 208956 kb
Host smart-4e2ee98d-a49f-4a64-9eb2-28cceba68294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595242890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2595242890
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2465969377
Short name T310
Test name
Test status
Simulation time 301904266 ps
CPU time 11.85 seconds
Started Jul 10 07:00:23 PM PDT 24
Finished Jul 10 07:00:36 PM PDT 24
Peak memory 218220 kb
Host smart-32af6879-414f-4a59-89d2-42bc81525b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465969377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2465969377
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3265445372
Short name T572
Test name
Test status
Simulation time 554871146 ps
CPU time 7.29 seconds
Started Jul 10 07:00:22 PM PDT 24
Finished Jul 10 07:00:31 PM PDT 24
Peak memory 217532 kb
Host smart-c9a8c572-5fb2-4aef-8adf-b7ed851a0d0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265445372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3265445372
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2088226835
Short name T333
Test name
Test status
Simulation time 19034469 ps
CPU time 1.7 seconds
Started Jul 10 07:00:25 PM PDT 24
Finished Jul 10 07:00:28 PM PDT 24
Peak memory 222028 kb
Host smart-9fb33b6b-5940-4ed2-b815-7001d7631536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088226835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2088226835
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.509221898
Short name T679
Test name
Test status
Simulation time 180801103 ps
CPU time 9.49 seconds
Started Jul 10 07:00:23 PM PDT 24
Finished Jul 10 07:00:34 PM PDT 24
Peak memory 218236 kb
Host smart-9fe3ee32-f605-4740-8a13-4be95c8c546f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509221898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.509221898
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3246430931
Short name T797
Test name
Test status
Simulation time 350066017 ps
CPU time 8.06 seconds
Started Jul 10 07:00:27 PM PDT 24
Finished Jul 10 07:00:36 PM PDT 24
Peak memory 226048 kb
Host smart-f12e31ea-2849-4dea-b848-b133ade57b81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246430931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3246430931
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2167451659
Short name T298
Test name
Test status
Simulation time 322542640 ps
CPU time 10.5 seconds
Started Jul 10 07:00:23 PM PDT 24
Finished Jul 10 07:00:36 PM PDT 24
Peak memory 218144 kb
Host smart-00bf07a6-867f-42b7-ac57-11ec7bc66399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167451659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2167451659
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1805745492
Short name T400
Test name
Test status
Simulation time 1206370398 ps
CPU time 9.96 seconds
Started Jul 10 07:00:22 PM PDT 24
Finished Jul 10 07:00:33 PM PDT 24
Peak memory 218300 kb
Host smart-89fd9b1e-1c0b-490a-afa5-5b7793f4d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805745492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1805745492
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3136491622
Short name T559
Test name
Test status
Simulation time 44703667 ps
CPU time 2.87 seconds
Started Jul 10 07:00:12 PM PDT 24
Finished Jul 10 07:00:16 PM PDT 24
Peak memory 217912 kb
Host smart-05df0ad9-879b-4702-a123-f3839bda8c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136491622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3136491622
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3649495214
Short name T289
Test name
Test status
Simulation time 191947442 ps
CPU time 21.32 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:00:34 PM PDT 24
Peak memory 250980 kb
Host smart-e38a6502-a40f-4705-93d7-add61fc64170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649495214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3649495214
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2177922319
Short name T33
Test name
Test status
Simulation time 275249489 ps
CPU time 6.28 seconds
Started Jul 10 07:00:11 PM PDT 24
Finished Jul 10 07:00:19 PM PDT 24
Peak memory 246372 kb
Host smart-dc8ceb59-2c3f-4aec-b470-35847469eded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177922319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2177922319
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.66647739
Short name T785
Test name
Test status
Simulation time 7206172170 ps
CPU time 89.24 seconds
Started Jul 10 07:00:23 PM PDT 24
Finished Jul 10 07:01:54 PM PDT 24
Peak memory 267936 kb
Host smart-fc882b73-91d3-4be7-ac4e-fba44c34689f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66647739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.lc_ctrl_stress_all.66647739
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2261405869
Short name T435
Test name
Test status
Simulation time 35709574 ps
CPU time 0.85 seconds
Started Jul 10 07:00:10 PM PDT 24
Finished Jul 10 07:00:13 PM PDT 24
Peak memory 211864 kb
Host smart-e95e92f9-756b-443b-9c9e-4c41390f6c65
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261405869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2261405869
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2930109191
Short name T724
Test name
Test status
Simulation time 118783477 ps
CPU time 1 seconds
Started Jul 10 07:00:24 PM PDT 24
Finished Jul 10 07:00:27 PM PDT 24
Peak memory 208968 kb
Host smart-f35aa996-63d0-4096-805c-9728946715fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930109191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2930109191
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1045150551
Short name T15
Test name
Test status
Simulation time 560638327 ps
CPU time 22.82 seconds
Started Jul 10 07:00:23 PM PDT 24
Finished Jul 10 07:00:48 PM PDT 24
Peak memory 218196 kb
Host smart-edf175c3-a8bd-420b-b67d-18dbc31a966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045150551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1045150551
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1949890423
Short name T830
Test name
Test status
Simulation time 662295992 ps
CPU time 15.38 seconds
Started Jul 10 07:00:27 PM PDT 24
Finished Jul 10 07:00:43 PM PDT 24
Peak memory 217500 kb
Host smart-731491f7-ffcf-4c57-81a7-7055fd55e481
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949890423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1949890423
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1949353423
Short name T281
Test name
Test status
Simulation time 16804214 ps
CPU time 1.74 seconds
Started Jul 10 07:00:22 PM PDT 24
Finished Jul 10 07:00:25 PM PDT 24
Peak memory 218232 kb
Host smart-8574e736-d3db-4372-badc-04a2caef3f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949353423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1949353423
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3750005258
Short name T356
Test name
Test status
Simulation time 230095629 ps
CPU time 7.75 seconds
Started Jul 10 07:00:21 PM PDT 24
Finished Jul 10 07:00:30 PM PDT 24
Peak memory 226048 kb
Host smart-6317691c-847d-4921-8beb-496160ede97b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750005258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3750005258
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3411308795
Short name T825
Test name
Test status
Simulation time 932958728 ps
CPU time 11.7 seconds
Started Jul 10 07:00:22 PM PDT 24
Finished Jul 10 07:00:35 PM PDT 24
Peak memory 218236 kb
Host smart-4cbf79fb-5a7c-49e5-88ec-9eba70046cee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411308795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3411308795
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2500220886
Short name T847
Test name
Test status
Simulation time 809310839 ps
CPU time 10.95 seconds
Started Jul 10 07:00:22 PM PDT 24
Finished Jul 10 07:00:34 PM PDT 24
Peak memory 218360 kb
Host smart-5dd8c376-9994-4dc6-bd77-f37f2c415082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500220886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2500220886
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.4004478329
Short name T277
Test name
Test status
Simulation time 42434827 ps
CPU time 0.95 seconds
Started Jul 10 07:00:24 PM PDT 24
Finished Jul 10 07:00:27 PM PDT 24
Peak memory 212208 kb
Host smart-17e6963d-8240-4e4b-8154-d6ca681e5ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004478329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.4004478329
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3025666163
Short name T88
Test name
Test status
Simulation time 697950885 ps
CPU time 22.58 seconds
Started Jul 10 07:00:22 PM PDT 24
Finished Jul 10 07:00:46 PM PDT 24
Peak memory 250892 kb
Host smart-2babc943-8dd3-4083-b75b-3c7bf87b352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025666163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3025666163
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3135229733
Short name T328
Test name
Test status
Simulation time 212982316 ps
CPU time 3.52 seconds
Started Jul 10 07:00:21 PM PDT 24
Finished Jul 10 07:00:25 PM PDT 24
Peak memory 218196 kb
Host smart-a505b398-d4cd-499d-aaff-179e30d23d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135229733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3135229733
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2434843305
Short name T561
Test name
Test status
Simulation time 40779706365 ps
CPU time 315.93 seconds
Started Jul 10 07:00:21 PM PDT 24
Finished Jul 10 07:05:38 PM PDT 24
Peak memory 267444 kb
Host smart-2de7f30e-a160-4d09-86ae-65f9e53c3940
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434843305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2434843305
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.856446251
Short name T624
Test name
Test status
Simulation time 13675954 ps
CPU time 1.15 seconds
Started Jul 10 07:00:23 PM PDT 24
Finished Jul 10 07:00:26 PM PDT 24
Peak memory 211968 kb
Host smart-439a614f-1ca5-4815-917c-46fb34e8e5f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856446251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.856446251
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3496775953
Short name T348
Test name
Test status
Simulation time 23011066 ps
CPU time 1 seconds
Started Jul 10 07:00:30 PM PDT 24
Finished Jul 10 07:00:31 PM PDT 24
Peak memory 208912 kb
Host smart-df608572-4642-4a78-8a26-8651285c3059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496775953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3496775953
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.723450358
Short name T696
Test name
Test status
Simulation time 349697100 ps
CPU time 12.38 seconds
Started Jul 10 07:00:23 PM PDT 24
Finished Jul 10 07:00:37 PM PDT 24
Peak memory 226012 kb
Host smart-d7654eaa-35cd-48e8-a55b-8936cfb71dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723450358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.723450358
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1176839863
Short name T723
Test name
Test status
Simulation time 1107548088 ps
CPU time 6.99 seconds
Started Jul 10 07:00:32 PM PDT 24
Finished Jul 10 07:00:40 PM PDT 24
Peak memory 217344 kb
Host smart-ee63afa8-2d0d-4964-b5d4-845ac298fc4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176839863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1176839863
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.91990356
Short name T10
Test name
Test status
Simulation time 67063756 ps
CPU time 2.94 seconds
Started Jul 10 07:00:22 PM PDT 24
Finished Jul 10 07:00:26 PM PDT 24
Peak memory 222528 kb
Host smart-7bb5951d-17be-4ebd-8746-70044dcac7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91990356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.91990356
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3271822487
Short name T769
Test name
Test status
Simulation time 1223628351 ps
CPU time 13.63 seconds
Started Jul 10 07:00:31 PM PDT 24
Finished Jul 10 07:00:45 PM PDT 24
Peak memory 226044 kb
Host smart-d05cd159-738e-44d7-9152-a2d4a0c517d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271822487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3271822487
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.138209714
Short name T803
Test name
Test status
Simulation time 391225486 ps
CPU time 13.57 seconds
Started Jul 10 07:00:32 PM PDT 24
Finished Jul 10 07:00:46 PM PDT 24
Peak memory 218204 kb
Host smart-c985e5a9-1892-4e7c-9e87-7c6e09c1d03a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138209714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.138209714
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3078094050
Short name T533
Test name
Test status
Simulation time 245189770 ps
CPU time 9.94 seconds
Started Jul 10 07:00:32 PM PDT 24
Finished Jul 10 07:00:43 PM PDT 24
Peak memory 226108 kb
Host smart-7c529a10-4e20-46e9-9e6c-677bf942e837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078094050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3078094050
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2113458239
Short name T786
Test name
Test status
Simulation time 20675487 ps
CPU time 1.19 seconds
Started Jul 10 07:00:24 PM PDT 24
Finished Jul 10 07:00:27 PM PDT 24
Peak memory 217732 kb
Host smart-467e02b3-f915-4b68-8c8f-4a433a70f383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113458239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2113458239
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3311667372
Short name T774
Test name
Test status
Simulation time 1210350914 ps
CPU time 35.24 seconds
Started Jul 10 07:00:24 PM PDT 24
Finished Jul 10 07:01:01 PM PDT 24
Peak memory 250992 kb
Host smart-db37d2ca-3b0b-465f-b92b-0a37449fb89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311667372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3311667372
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2609326371
Short name T709
Test name
Test status
Simulation time 83939973 ps
CPU time 7.1 seconds
Started Jul 10 07:00:25 PM PDT 24
Finished Jul 10 07:00:34 PM PDT 24
Peak memory 251172 kb
Host smart-f43231c9-e2e9-4e21-9e91-fc1a5ff31a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609326371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2609326371
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.152207079
Short name T647
Test name
Test status
Simulation time 10524498942 ps
CPU time 81.4 seconds
Started Jul 10 07:00:31 PM PDT 24
Finished Jul 10 07:01:54 PM PDT 24
Peak memory 267424 kb
Host smart-fb73c231-5a86-403f-86fd-f5af25483893
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152207079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.152207079
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3997524782
Short name T655
Test name
Test status
Simulation time 9799036561 ps
CPU time 252.95 seconds
Started Jul 10 07:00:31 PM PDT 24
Finished Jul 10 07:04:45 PM PDT 24
Peak memory 251136 kb
Host smart-57104b4d-b08e-43b9-961f-d1acd4c2707d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3997524782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3997524782
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3595505411
Short name T353
Test name
Test status
Simulation time 31581679 ps
CPU time 0.85 seconds
Started Jul 10 07:00:23 PM PDT 24
Finished Jul 10 07:00:25 PM PDT 24
Peak memory 208652 kb
Host smart-bcae7d87-e3ee-4960-bc7e-fda3afda1ab8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595505411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3595505411
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.275731492
Short name T804
Test name
Test status
Simulation time 1878333520 ps
CPU time 14.14 seconds
Started Jul 10 07:00:34 PM PDT 24
Finished Jul 10 07:00:49 PM PDT 24
Peak memory 218200 kb
Host smart-071f4166-57a2-4276-9c88-d77174dc2714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275731492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.275731492
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3671419156
Short name T370
Test name
Test status
Simulation time 615787679 ps
CPU time 15.61 seconds
Started Jul 10 07:00:32 PM PDT 24
Finished Jul 10 07:00:49 PM PDT 24
Peak memory 217272 kb
Host smart-84c9c30c-4556-4a46-8b3b-413a16e31fe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671419156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3671419156
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2954623753
Short name T257
Test name
Test status
Simulation time 86712586 ps
CPU time 3.28 seconds
Started Jul 10 07:00:31 PM PDT 24
Finished Jul 10 07:00:35 PM PDT 24
Peak memory 222788 kb
Host smart-4f392771-9481-4cad-a559-7fd3dc620139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954623753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2954623753
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1071638762
Short name T402
Test name
Test status
Simulation time 204107652 ps
CPU time 9.51 seconds
Started Jul 10 07:00:32 PM PDT 24
Finished Jul 10 07:00:42 PM PDT 24
Peak memory 226032 kb
Host smart-308efbce-080d-496d-9285-a5f4df5155a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071638762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1071638762
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2844982624
Short name T834
Test name
Test status
Simulation time 800193698 ps
CPU time 13.37 seconds
Started Jul 10 07:00:30 PM PDT 24
Finished Jul 10 07:00:44 PM PDT 24
Peak memory 226044 kb
Host smart-dfb8b1a4-c692-46b9-b98a-ad94ffa82999
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844982624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2844982624
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1120336729
Short name T852
Test name
Test status
Simulation time 387734897 ps
CPU time 9.78 seconds
Started Jul 10 07:00:33 PM PDT 24
Finished Jul 10 07:00:44 PM PDT 24
Peak memory 218300 kb
Host smart-f97cca77-7d64-4a7c-b1b5-097c7b21aad7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120336729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1120336729
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.4263633592
Short name T738
Test name
Test status
Simulation time 350423374 ps
CPU time 8.18 seconds
Started Jul 10 07:00:30 PM PDT 24
Finished Jul 10 07:00:39 PM PDT 24
Peak memory 218356 kb
Host smart-d39118fe-4c6e-445f-a307-5fe5b6737e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263633592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4263633592
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2690829319
Short name T698
Test name
Test status
Simulation time 102134034 ps
CPU time 3.94 seconds
Started Jul 10 07:00:31 PM PDT 24
Finished Jul 10 07:00:36 PM PDT 24
Peak memory 214384 kb
Host smart-48f66d1b-b9a1-4140-8a16-0facbd00119c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690829319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2690829319
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.4116212111
Short name T409
Test name
Test status
Simulation time 613134809 ps
CPU time 24.18 seconds
Started Jul 10 07:00:31 PM PDT 24
Finished Jul 10 07:00:57 PM PDT 24
Peak memory 251048 kb
Host smart-521fb35d-e45b-45a4-b48e-1831386c0bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116212111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.4116212111
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3142136904
Short name T415
Test name
Test status
Simulation time 78875856 ps
CPU time 3.78 seconds
Started Jul 10 07:00:34 PM PDT 24
Finished Jul 10 07:00:39 PM PDT 24
Peak memory 222368 kb
Host smart-8e33ce14-0eaa-408a-ad64-6c4cf8aee411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142136904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3142136904
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3538676834
Short name T596
Test name
Test status
Simulation time 11466350247 ps
CPU time 117.55 seconds
Started Jul 10 07:00:34 PM PDT 24
Finished Jul 10 07:02:32 PM PDT 24
Peak memory 247768 kb
Host smart-6ec5225a-6a5f-4f45-b804-dc8925c879ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538676834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3538676834
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2526187126
Short name T259
Test name
Test status
Simulation time 36327115 ps
CPU time 0.84 seconds
Started Jul 10 07:00:32 PM PDT 24
Finished Jul 10 07:00:34 PM PDT 24
Peak memory 211936 kb
Host smart-32b113ff-c59c-463a-96fa-2b619b7493f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526187126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2526187126
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1770493945
Short name T574
Test name
Test status
Simulation time 91329822 ps
CPU time 0.97 seconds
Started Jul 10 07:00:40 PM PDT 24
Finished Jul 10 07:00:41 PM PDT 24
Peak memory 209060 kb
Host smart-f3727c2f-787e-4810-9df6-2b141a3a639a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770493945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1770493945
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.570755397
Short name T824
Test name
Test status
Simulation time 1326687254 ps
CPU time 10.65 seconds
Started Jul 10 07:00:41 PM PDT 24
Finished Jul 10 07:00:52 PM PDT 24
Peak memory 218236 kb
Host smart-55614e2d-ad8c-4080-9624-6092d71a637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570755397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.570755397
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.4066023425
Short name T712
Test name
Test status
Simulation time 310622166 ps
CPU time 2.98 seconds
Started Jul 10 07:00:40 PM PDT 24
Finished Jul 10 07:00:44 PM PDT 24
Peak memory 218328 kb
Host smart-c14dc413-194d-4a6f-88df-7e0dfcdd24fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066023425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4066023425
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1390525958
Short name T644
Test name
Test status
Simulation time 311238613 ps
CPU time 13.31 seconds
Started Jul 10 07:00:44 PM PDT 24
Finished Jul 10 07:00:58 PM PDT 24
Peak memory 218540 kb
Host smart-0c5486ce-b421-4787-b574-389ad81dbcdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390525958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1390525958
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1822412626
Short name T689
Test name
Test status
Simulation time 1059649694 ps
CPU time 11.69 seconds
Started Jul 10 07:00:41 PM PDT 24
Finished Jul 10 07:00:53 PM PDT 24
Peak memory 226012 kb
Host smart-ca84312a-f337-4382-93c1-1e81e76a21c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822412626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1822412626
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1746133473
Short name T657
Test name
Test status
Simulation time 1398579855 ps
CPU time 11.55 seconds
Started Jul 10 07:00:44 PM PDT 24
Finished Jul 10 07:00:56 PM PDT 24
Peak memory 226032 kb
Host smart-88704519-e55c-4b6f-af39-6834f395f825
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746133473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1746133473
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.273378727
Short name T442
Test name
Test status
Simulation time 236020343 ps
CPU time 10.12 seconds
Started Jul 10 07:00:40 PM PDT 24
Finished Jul 10 07:00:50 PM PDT 24
Peak memory 218356 kb
Host smart-70ff15e3-dabc-4032-b712-f34accac9093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273378727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.273378727
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2460157074
Short name T833
Test name
Test status
Simulation time 67976124 ps
CPU time 1.56 seconds
Started Jul 10 07:00:32 PM PDT 24
Finished Jul 10 07:00:35 PM PDT 24
Peak memory 217724 kb
Host smart-5d8a86e4-3b22-4ca3-970c-7f27d5e8688a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460157074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2460157074
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.409116413
Short name T243
Test name
Test status
Simulation time 224620936 ps
CPU time 29.64 seconds
Started Jul 10 07:00:39 PM PDT 24
Finished Jul 10 07:01:09 PM PDT 24
Peak memory 250952 kb
Host smart-6e57098e-8cc0-41b4-a6db-528dfe32b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409116413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.409116413
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3980220115
Short name T249
Test name
Test status
Simulation time 44121685 ps
CPU time 2.98 seconds
Started Jul 10 07:00:41 PM PDT 24
Finished Jul 10 07:00:45 PM PDT 24
Peak memory 226396 kb
Host smart-c08136aa-234c-4d40-b4f2-256c492aff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980220115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3980220115
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2878380757
Short name T58
Test name
Test status
Simulation time 2143325625 ps
CPU time 61.46 seconds
Started Jul 10 07:00:41 PM PDT 24
Finished Jul 10 07:01:43 PM PDT 24
Peak memory 271828 kb
Host smart-2ffd96ac-111f-4f1e-a2ce-1bf6ad2a9482
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878380757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2878380757
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4017844688
Short name T549
Test name
Test status
Simulation time 20703701 ps
CPU time 1.03 seconds
Started Jul 10 07:00:41 PM PDT 24
Finished Jul 10 07:00:43 PM PDT 24
Peak memory 212896 kb
Host smart-145e538e-8c28-48bb-9df4-8e752233360a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017844688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4017844688
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.14191112
Short name T595
Test name
Test status
Simulation time 23279990 ps
CPU time 1.05 seconds
Started Jul 10 06:56:41 PM PDT 24
Finished Jul 10 06:56:43 PM PDT 24
Peak memory 209036 kb
Host smart-e5f58c8e-0294-4739-a7cc-e5707cfc0fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.14191112
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1840280363
Short name T201
Test name
Test status
Simulation time 21821196 ps
CPU time 0.82 seconds
Started Jul 10 06:56:33 PM PDT 24
Finished Jul 10 06:56:34 PM PDT 24
Peak memory 208860 kb
Host smart-ee603a04-fdcc-44bf-b88a-753f5b6c8930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840280363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1840280363
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2239480755
Short name T708
Test name
Test status
Simulation time 1669523375 ps
CPU time 11.02 seconds
Started Jul 10 06:56:24 PM PDT 24
Finished Jul 10 06:56:36 PM PDT 24
Peak memory 218240 kb
Host smart-bf8aaa29-f9fc-41e0-afb4-71d8be56500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239480755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2239480755
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3568315392
Short name T609
Test name
Test status
Simulation time 136832675 ps
CPU time 3.78 seconds
Started Jul 10 06:56:31 PM PDT 24
Finished Jul 10 06:56:36 PM PDT 24
Peak memory 217272 kb
Host smart-216a1a2f-194a-41bb-bdaa-72cd9ed4da33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568315392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3568315392
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.61722488
Short name T725
Test name
Test status
Simulation time 4001092854 ps
CPU time 32.02 seconds
Started Jul 10 06:56:30 PM PDT 24
Finished Jul 10 06:57:03 PM PDT 24
Peak memory 218936 kb
Host smart-a91131f0-283c-4536-869f-7f81672d59c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61722488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_erro
rs.61722488
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1227567170
Short name T464
Test name
Test status
Simulation time 93421758 ps
CPU time 2.05 seconds
Started Jul 10 06:56:33 PM PDT 24
Finished Jul 10 06:56:36 PM PDT 24
Peak memory 217640 kb
Host smart-d8a0d836-1268-415a-8eac-f5ff9ae023ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227567170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
227567170
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1691473856
Short name T848
Test name
Test status
Simulation time 1662386828 ps
CPU time 7.48 seconds
Started Jul 10 06:56:30 PM PDT 24
Finished Jul 10 06:56:38 PM PDT 24
Peak memory 218300 kb
Host smart-8114f2e7-8462-4933-8642-816e9f50a1b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691473856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1691473856
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.727669100
Short name T749
Test name
Test status
Simulation time 9480995984 ps
CPU time 36.9 seconds
Started Jul 10 06:56:42 PM PDT 24
Finished Jul 10 06:57:19 PM PDT 24
Peak memory 217792 kb
Host smart-78f333c3-13bb-4f4e-81d3-c0cd7264cefe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727669100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.727669100
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1000205950
Short name T737
Test name
Test status
Simulation time 276229003 ps
CPU time 5.44 seconds
Started Jul 10 06:56:30 PM PDT 24
Finished Jul 10 06:56:36 PM PDT 24
Peak memory 217696 kb
Host smart-19ed1c31-2f93-410d-ba95-9ebc3d9e1508
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000205950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1000205950
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.659649072
Short name T626
Test name
Test status
Simulation time 3327425718 ps
CPU time 42.41 seconds
Started Jul 10 06:56:31 PM PDT 24
Finished Jul 10 06:57:14 PM PDT 24
Peak memory 251216 kb
Host smart-3238ea01-3ca7-4d80-8f6a-556a8d5568b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659649072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.659649072
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.100700193
Short name T491
Test name
Test status
Simulation time 1446505408 ps
CPU time 15.24 seconds
Started Jul 10 06:56:32 PM PDT 24
Finished Jul 10 06:56:48 PM PDT 24
Peak memory 247600 kb
Host smart-20fb476f-3c47-490f-b821-56e2d3554291
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100700193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.100700193
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4009339329
Short name T618
Test name
Test status
Simulation time 104645586 ps
CPU time 2.11 seconds
Started Jul 10 06:56:24 PM PDT 24
Finished Jul 10 06:56:27 PM PDT 24
Peak memory 222084 kb
Host smart-e812d0f1-33db-4f07-9126-d51f5f89153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009339329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4009339329
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2338827743
Short name T591
Test name
Test status
Simulation time 993139988 ps
CPU time 13.95 seconds
Started Jul 10 06:56:31 PM PDT 24
Finished Jul 10 06:56:46 PM PDT 24
Peak memory 214884 kb
Host smart-998628ab-f355-407d-a597-697f9a3c1e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338827743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2338827743
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2019505077
Short name T54
Test name
Test status
Simulation time 461535573 ps
CPU time 22.92 seconds
Started Jul 10 06:56:41 PM PDT 24
Finished Jul 10 06:57:05 PM PDT 24
Peak memory 268692 kb
Host smart-49aa7498-de13-4700-9b00-1104f9c6dee8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019505077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2019505077
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3652265774
Short name T492
Test name
Test status
Simulation time 3187747421 ps
CPU time 21.92 seconds
Started Jul 10 06:56:40 PM PDT 24
Finished Jul 10 06:57:02 PM PDT 24
Peak memory 226120 kb
Host smart-627e206e-e99f-4bbf-9b74-13ea3c70b7bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652265774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3652265774
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2534370091
Short name T681
Test name
Test status
Simulation time 448270795 ps
CPU time 12.79 seconds
Started Jul 10 06:56:41 PM PDT 24
Finished Jul 10 06:56:54 PM PDT 24
Peak memory 226036 kb
Host smart-f3a402ca-495d-456b-9be5-dc2d564f8c38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534370091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2534370091
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2773567313
Short name T443
Test name
Test status
Simulation time 3341740793 ps
CPU time 16.24 seconds
Started Jul 10 06:56:42 PM PDT 24
Finished Jul 10 06:56:59 PM PDT 24
Peak memory 218300 kb
Host smart-6e8e06af-c74c-4e65-bce3-a3f90d578630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773567313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
773567313
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3135151426
Short name T807
Test name
Test status
Simulation time 201416905 ps
CPU time 9.15 seconds
Started Jul 10 06:56:22 PM PDT 24
Finished Jul 10 06:56:32 PM PDT 24
Peak memory 218324 kb
Host smart-fb249ad5-7f1f-4d56-b8ee-56704748673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135151426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3135151426
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2567469873
Short name T577
Test name
Test status
Simulation time 52064638 ps
CPU time 3.52 seconds
Started Jul 10 06:56:30 PM PDT 24
Finished Jul 10 06:56:34 PM PDT 24
Peak memory 217716 kb
Host smart-7e723ea9-278b-4cd6-9590-417720ca092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567469873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2567469873
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1880102025
Short name T302
Test name
Test status
Simulation time 477907253 ps
CPU time 22.25 seconds
Started Jul 10 06:56:23 PM PDT 24
Finished Jul 10 06:56:46 PM PDT 24
Peak memory 251096 kb
Host smart-35ae2f88-0a11-4554-8117-efb227298fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880102025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1880102025
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.15023531
Short name T480
Test name
Test status
Simulation time 170829076 ps
CPU time 6.82 seconds
Started Jul 10 06:56:25 PM PDT 24
Finished Jul 10 06:56:32 PM PDT 24
Peak memory 250524 kb
Host smart-e86aa5c8-bb0c-4df3-8125-c7582666cd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15023531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.15023531
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1437061531
Short name T781
Test name
Test status
Simulation time 6993152762 ps
CPU time 225.82 seconds
Started Jul 10 06:56:42 PM PDT 24
Finished Jul 10 07:00:28 PM PDT 24
Peak memory 267360 kb
Host smart-31dc0c8b-7068-44bd-98bd-a758adff25d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437061531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1437061531
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3871767956
Short name T170
Test name
Test status
Simulation time 8096839197 ps
CPU time 182.62 seconds
Started Jul 10 06:56:42 PM PDT 24
Finished Jul 10 06:59:45 PM PDT 24
Peak memory 279900 kb
Host smart-75b4df37-9baf-4d73-92b2-20acb0172c55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3871767956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3871767956
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.4188030973
Short name T162
Test name
Test status
Simulation time 41400523 ps
CPU time 0.9 seconds
Started Jul 10 06:56:25 PM PDT 24
Finished Jul 10 06:56:27 PM PDT 24
Peak memory 211860 kb
Host smart-597c7d56-d954-45c0-8ae7-52252e429ab6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188030973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.4188030973
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1587792183
Short name T280
Test name
Test status
Simulation time 28607568 ps
CPU time 1.03 seconds
Started Jul 10 07:00:50 PM PDT 24
Finished Jul 10 07:00:52 PM PDT 24
Peak memory 208952 kb
Host smart-4a6d3976-f4c8-4f12-a102-c651fcb0e7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587792183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1587792183
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1888040127
Short name T649
Test name
Test status
Simulation time 863510349 ps
CPU time 9.21 seconds
Started Jul 10 07:00:41 PM PDT 24
Finished Jul 10 07:00:51 PM PDT 24
Peak memory 226020 kb
Host smart-e32821b6-9399-4aa7-892a-b48c90e3189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888040127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1888040127
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2915496838
Short name T499
Test name
Test status
Simulation time 3397689835 ps
CPU time 8.92 seconds
Started Jul 10 07:00:42 PM PDT 24
Finished Jul 10 07:00:52 PM PDT 24
Peak memory 217792 kb
Host smart-6c5f03aa-cfa2-4967-b370-ee3dcf186428
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915496838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2915496838
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3441265383
Short name T658
Test name
Test status
Simulation time 106359462 ps
CPU time 3.48 seconds
Started Jul 10 07:00:43 PM PDT 24
Finished Jul 10 07:00:47 PM PDT 24
Peak memory 218212 kb
Host smart-0673bd64-8edc-49d4-8b85-b8e22ab0d8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441265383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3441265383
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.233323728
Short name T92
Test name
Test status
Simulation time 1067395504 ps
CPU time 14.32 seconds
Started Jul 10 07:00:51 PM PDT 24
Finished Jul 10 07:01:07 PM PDT 24
Peak memory 218884 kb
Host smart-e5afb931-268d-4c39-bb20-373e857a11c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233323728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.233323728
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1790579265
Short name T845
Test name
Test status
Simulation time 11279825421 ps
CPU time 21.25 seconds
Started Jul 10 07:00:52 PM PDT 24
Finished Jul 10 07:01:15 PM PDT 24
Peak memory 226076 kb
Host smart-16d03a1a-fc5b-472f-8a4b-d5c00c9cb88a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790579265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1790579265
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2607495488
Short name T778
Test name
Test status
Simulation time 337996586 ps
CPU time 8.94 seconds
Started Jul 10 07:00:52 PM PDT 24
Finished Jul 10 07:01:03 PM PDT 24
Peak memory 218316 kb
Host smart-c89bffea-d27e-49ae-b1c2-7dfd17b9faf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607495488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2607495488
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1758446099
Short name T582
Test name
Test status
Simulation time 1268257349 ps
CPU time 11.32 seconds
Started Jul 10 07:00:46 PM PDT 24
Finished Jul 10 07:00:58 PM PDT 24
Peak memory 218288 kb
Host smart-b892f24a-d3eb-4d5c-8b2e-94c27c1a804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758446099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1758446099
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2266709662
Short name T397
Test name
Test status
Simulation time 163605839 ps
CPU time 5.18 seconds
Started Jul 10 07:00:39 PM PDT 24
Finished Jul 10 07:00:45 PM PDT 24
Peak memory 223308 kb
Host smart-cdb52916-3d41-4a22-b7a1-0e760726f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266709662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2266709662
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1827607970
Short name T344
Test name
Test status
Simulation time 501101804 ps
CPU time 27.17 seconds
Started Jul 10 07:00:42 PM PDT 24
Finished Jul 10 07:01:10 PM PDT 24
Peak memory 250996 kb
Host smart-bfba1e0c-c775-4507-8104-701950623cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827607970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1827607970
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2194194720
Short name T421
Test name
Test status
Simulation time 76151503 ps
CPU time 7.69 seconds
Started Jul 10 07:00:42 PM PDT 24
Finished Jul 10 07:00:50 PM PDT 24
Peak memory 251040 kb
Host smart-1da207ff-137d-46dc-b4b3-6890efe77247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194194720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2194194720
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.949999373
Short name T606
Test name
Test status
Simulation time 13537885308 ps
CPU time 166.91 seconds
Started Jul 10 07:00:50 PM PDT 24
Finished Jul 10 07:03:37 PM PDT 24
Peak memory 283624 kb
Host smart-4af8fb8c-379b-4f09-9be3-f65180fb5633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949999373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.949999373
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2432134453
Short name T541
Test name
Test status
Simulation time 13857204 ps
CPU time 1.04 seconds
Started Jul 10 07:00:41 PM PDT 24
Finished Jul 10 07:00:43 PM PDT 24
Peak memory 211916 kb
Host smart-20e5a0be-f435-4c46-93b1-9e75143f5a75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432134453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2432134453
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2492444729
Short name T292
Test name
Test status
Simulation time 14925603 ps
CPU time 0.95 seconds
Started Jul 10 07:01:00 PM PDT 24
Finished Jul 10 07:01:03 PM PDT 24
Peak memory 209168 kb
Host smart-602f4a19-75bc-44f3-b9ad-7d8d836b0af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492444729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2492444729
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1381209182
Short name T729
Test name
Test status
Simulation time 352765471 ps
CPU time 14.09 seconds
Started Jul 10 07:00:54 PM PDT 24
Finished Jul 10 07:01:08 PM PDT 24
Peak memory 226024 kb
Host smart-9839b7f3-3800-4944-8021-ae2aeb17dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381209182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1381209182
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2870084760
Short name T571
Test name
Test status
Simulation time 396944571 ps
CPU time 5.75 seconds
Started Jul 10 07:00:51 PM PDT 24
Finished Jul 10 07:00:58 PM PDT 24
Peak memory 217340 kb
Host smart-16f27e03-25e1-4a85-bbf3-bab2865c9a53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870084760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2870084760
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3815704443
Short name T780
Test name
Test status
Simulation time 88173369 ps
CPU time 4.54 seconds
Started Jul 10 07:00:52 PM PDT 24
Finished Jul 10 07:00:58 PM PDT 24
Peak memory 218220 kb
Host smart-62c3cad8-276c-4322-86b8-0c721b8dea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815704443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3815704443
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.312849382
Short name T465
Test name
Test status
Simulation time 1820249442 ps
CPU time 9.65 seconds
Started Jul 10 07:01:00 PM PDT 24
Finished Jul 10 07:01:11 PM PDT 24
Peak memory 219548 kb
Host smart-9e90939f-46d1-4435-8c9d-da4531fe3bef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312849382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.312849382
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3694634982
Short name T315
Test name
Test status
Simulation time 1288516956 ps
CPU time 14.04 seconds
Started Jul 10 07:01:01 PM PDT 24
Finished Jul 10 07:01:16 PM PDT 24
Peak memory 226032 kb
Host smart-d6e4eeb1-011b-43b2-90aa-c4c5a9188b31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694634982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3694634982
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3306806830
Short name T386
Test name
Test status
Simulation time 777001442 ps
CPU time 16.35 seconds
Started Jul 10 07:01:00 PM PDT 24
Finished Jul 10 07:01:18 PM PDT 24
Peak memory 218236 kb
Host smart-1107220d-33e4-4b82-9e5d-73267a9f0401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306806830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3306806830
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.651679881
Short name T493
Test name
Test status
Simulation time 490762856 ps
CPU time 15.64 seconds
Started Jul 10 07:00:52 PM PDT 24
Finished Jul 10 07:01:09 PM PDT 24
Peak memory 218428 kb
Host smart-889c108c-8445-488c-a0a3-bf9f41a221fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651679881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.651679881
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.415747245
Short name T67
Test name
Test status
Simulation time 112618204 ps
CPU time 6.63 seconds
Started Jul 10 07:00:50 PM PDT 24
Finished Jul 10 07:00:58 PM PDT 24
Peak memory 217844 kb
Host smart-ad0afda5-92dd-4aed-92e2-9e0fa754dd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415747245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.415747245
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3876539133
Short name T364
Test name
Test status
Simulation time 2704503744 ps
CPU time 27.8 seconds
Started Jul 10 07:00:52 PM PDT 24
Finished Jul 10 07:01:21 PM PDT 24
Peak memory 251036 kb
Host smart-a5e3a189-6186-49a3-a7f8-b45263ce470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876539133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3876539133
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.431158613
Short name T512
Test name
Test status
Simulation time 592364910 ps
CPU time 5.51 seconds
Started Jul 10 07:00:52 PM PDT 24
Finished Jul 10 07:00:59 PM PDT 24
Peak memory 226408 kb
Host smart-6468f809-9847-4493-9cc5-ffc3dece58de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431158613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.431158613
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3156765903
Short name T597
Test name
Test status
Simulation time 6596671525 ps
CPU time 113.4 seconds
Started Jul 10 07:01:04 PM PDT 24
Finished Jul 10 07:02:58 PM PDT 24
Peak memory 246112 kb
Host smart-56fc4b79-d496-475d-8ff3-6ea6e6c06b58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156765903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3156765903
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2470596980
Short name T148
Test name
Test status
Simulation time 31268155897 ps
CPU time 272.39 seconds
Started Jul 10 07:00:59 PM PDT 24
Finished Jul 10 07:05:32 PM PDT 24
Peak memory 283928 kb
Host smart-f3f164b1-8b87-4c14-aeb2-75d8ff1fc579
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2470596980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2470596980
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2733694997
Short name T457
Test name
Test status
Simulation time 21243794 ps
CPU time 0.99 seconds
Started Jul 10 07:00:50 PM PDT 24
Finished Jul 10 07:00:52 PM PDT 24
Peak memory 211936 kb
Host smart-f06e9798-ea94-4543-9c12-bb6c847bdc12
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733694997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2733694997
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.717924550
Short name T102
Test name
Test status
Simulation time 35555002 ps
CPU time 1.08 seconds
Started Jul 10 07:01:01 PM PDT 24
Finished Jul 10 07:01:03 PM PDT 24
Peak memory 209164 kb
Host smart-55722cf6-dd35-4b4d-a98d-c4cf8f14aa27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717924550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.717924550
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.508024832
Short name T339
Test name
Test status
Simulation time 899357474 ps
CPU time 14.35 seconds
Started Jul 10 07:00:59 PM PDT 24
Finished Jul 10 07:01:14 PM PDT 24
Peak memory 226056 kb
Host smart-acd7869e-57db-409d-a757-5d4e4312e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508024832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.508024832
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3821832129
Short name T38
Test name
Test status
Simulation time 943917444 ps
CPU time 4.23 seconds
Started Jul 10 07:01:00 PM PDT 24
Finished Jul 10 07:01:05 PM PDT 24
Peak memory 217232 kb
Host smart-7e508c56-774f-4e7c-b749-8156f66869a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821832129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3821832129
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2050229609
Short name T208
Test name
Test status
Simulation time 65283793 ps
CPU time 2.73 seconds
Started Jul 10 07:00:59 PM PDT 24
Finished Jul 10 07:01:03 PM PDT 24
Peak memory 218208 kb
Host smart-b0ad5ac5-696b-4758-a418-30c0b76d6f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050229609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2050229609
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3136374203
Short name T358
Test name
Test status
Simulation time 2607305777 ps
CPU time 16.25 seconds
Started Jul 10 07:01:00 PM PDT 24
Finished Jul 10 07:01:18 PM PDT 24
Peak memory 226100 kb
Host smart-0290c8c7-3862-431e-a2bd-e9f5d9a9c2d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136374203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3136374203
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4025996655
Short name T466
Test name
Test status
Simulation time 544065236 ps
CPU time 10.75 seconds
Started Jul 10 07:01:01 PM PDT 24
Finished Jul 10 07:01:13 PM PDT 24
Peak memory 218248 kb
Host smart-7eb3cc9c-cd75-4fa0-a4a8-874a751d0e3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025996655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4025996655
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.583085134
Short name T746
Test name
Test status
Simulation time 470394295 ps
CPU time 15.4 seconds
Started Jul 10 07:01:01 PM PDT 24
Finished Jul 10 07:01:18 PM PDT 24
Peak memory 218304 kb
Host smart-c929d24c-b1c0-46a3-91b0-f8cd6fc5e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583085134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.583085134
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.505451139
Short name T477
Test name
Test status
Simulation time 351166756 ps
CPU time 5.65 seconds
Started Jul 10 07:00:59 PM PDT 24
Finished Jul 10 07:01:06 PM PDT 24
Peak memory 217704 kb
Host smart-0981fa20-bf11-42c1-96f9-0c115a517f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505451139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.505451139
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3387376070
Short name T467
Test name
Test status
Simulation time 528491138 ps
CPU time 25.29 seconds
Started Jul 10 07:01:04 PM PDT 24
Finished Jul 10 07:01:30 PM PDT 24
Peak memory 250988 kb
Host smart-000fca91-321f-45bf-a28e-7dbcc7fa2668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387376070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3387376070
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.217165761
Short name T713
Test name
Test status
Simulation time 141307830 ps
CPU time 2.74 seconds
Started Jul 10 07:01:00 PM PDT 24
Finished Jul 10 07:01:04 PM PDT 24
Peak memory 222412 kb
Host smart-647438e4-2000-4d25-88f1-0641511f2d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217165761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.217165761
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.909025221
Short name T403
Test name
Test status
Simulation time 7095407674 ps
CPU time 161.72 seconds
Started Jul 10 07:01:01 PM PDT 24
Finished Jul 10 07:03:43 PM PDT 24
Peak memory 283792 kb
Host smart-039c246c-5ac8-4db5-870c-fa61a96964c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909025221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.909025221
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2094340507
Short name T578
Test name
Test status
Simulation time 13232675 ps
CPU time 0.9 seconds
Started Jul 10 07:01:04 PM PDT 24
Finished Jul 10 07:01:05 PM PDT 24
Peak memory 211856 kb
Host smart-e06a6163-f697-437b-a691-c3e93975f667
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094340507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2094340507
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.636882708
Short name T314
Test name
Test status
Simulation time 182059918 ps
CPU time 1 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:01:09 PM PDT 24
Peak memory 208928 kb
Host smart-b0e8f0f6-d909-4622-a7b9-2fc4a67e5b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636882708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.636882708
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3233045197
Short name T634
Test name
Test status
Simulation time 328931642 ps
CPU time 10.13 seconds
Started Jul 10 07:01:00 PM PDT 24
Finished Jul 10 07:01:11 PM PDT 24
Peak memory 218232 kb
Host smart-576bf75c-8e66-48f0-ad7c-aadea3953ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233045197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3233045197
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3540031781
Short name T444
Test name
Test status
Simulation time 1003461473 ps
CPU time 11.58 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:01:20 PM PDT 24
Peak memory 217444 kb
Host smart-bb1c66ae-a535-45d7-bdb2-1a2c00b672d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540031781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3540031781
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1373382432
Short name T433
Test name
Test status
Simulation time 27477684 ps
CPU time 2.06 seconds
Started Jul 10 07:00:59 PM PDT 24
Finished Jul 10 07:01:02 PM PDT 24
Peak memory 218216 kb
Host smart-ab9c95e1-0043-471c-8e15-f598d4f9cf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373382432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1373382432
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.485792565
Short name T250
Test name
Test status
Simulation time 1599581522 ps
CPU time 15.32 seconds
Started Jul 10 07:01:09 PM PDT 24
Finished Jul 10 07:01:25 PM PDT 24
Peak memory 226024 kb
Host smart-9dc85404-420f-4b8e-b8d4-ae7fef5c01b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485792565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.485792565
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.233441756
Short name T790
Test name
Test status
Simulation time 2972274044 ps
CPU time 12.61 seconds
Started Jul 10 07:01:06 PM PDT 24
Finished Jul 10 07:01:19 PM PDT 24
Peak memory 218300 kb
Host smart-98c42ef5-8869-4690-add2-063e6b9a09d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233441756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.233441756
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.240835003
Short name T694
Test name
Test status
Simulation time 1301897960 ps
CPU time 12.42 seconds
Started Jul 10 07:00:58 PM PDT 24
Finished Jul 10 07:01:12 PM PDT 24
Peak memory 225272 kb
Host smart-5936a51d-18db-4cb7-8d94-4626211676cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240835003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.240835003
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3204688556
Short name T662
Test name
Test status
Simulation time 593234865 ps
CPU time 3.31 seconds
Started Jul 10 07:00:59 PM PDT 24
Finished Jul 10 07:01:03 PM PDT 24
Peak memory 217684 kb
Host smart-fba5e77b-dd05-4432-9e67-0be9bca40e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204688556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3204688556
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2788139218
Short name T526
Test name
Test status
Simulation time 1378245278 ps
CPU time 28.83 seconds
Started Jul 10 07:00:58 PM PDT 24
Finished Jul 10 07:01:28 PM PDT 24
Peak memory 250980 kb
Host smart-959201ea-8e08-4e21-973b-095741434896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788139218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2788139218
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2061350897
Short name T84
Test name
Test status
Simulation time 147178875 ps
CPU time 10.48 seconds
Started Jul 10 07:00:58 PM PDT 24
Finished Jul 10 07:01:09 PM PDT 24
Peak memory 250520 kb
Host smart-a7b778ea-a7bf-4ea8-8866-122feb4ce22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061350897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2061350897
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2096750057
Short name T372
Test name
Test status
Simulation time 4667213758 ps
CPU time 118.03 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:03:06 PM PDT 24
Peak memory 283008 kb
Host smart-14e644ff-a90f-4d89-88a1-0dcd181b16bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096750057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2096750057
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2703341916
Short name T820
Test name
Test status
Simulation time 41558877932 ps
CPU time 198.2 seconds
Started Jul 10 07:01:08 PM PDT 24
Finished Jul 10 07:04:27 PM PDT 24
Peak memory 272660 kb
Host smart-9cb1ac26-d4e2-4fa7-a4c5-a9bf5bc5e17b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2703341916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2703341916
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2635959770
Short name T822
Test name
Test status
Simulation time 29887384 ps
CPU time 0.97 seconds
Started Jul 10 07:01:03 PM PDT 24
Finished Jul 10 07:01:04 PM PDT 24
Peak memory 211852 kb
Host smart-63b5b752-ccf8-49e6-81f1-871546a44ccf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635959770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2635959770
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2787455821
Short name T286
Test name
Test status
Simulation time 56490536 ps
CPU time 1.06 seconds
Started Jul 10 07:01:13 PM PDT 24
Finished Jul 10 07:01:15 PM PDT 24
Peak memory 209032 kb
Host smart-f17564c3-33c3-49f1-a016-a59b0a10732a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787455821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2787455821
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1238689701
Short name T307
Test name
Test status
Simulation time 2898895657 ps
CPU time 13.75 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:01:22 PM PDT 24
Peak memory 219004 kb
Host smart-75ae34ea-e583-44c1-bb87-adf6a398e5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238689701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1238689701
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2161031597
Short name T853
Test name
Test status
Simulation time 1685989936 ps
CPU time 7.32 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:01:15 PM PDT 24
Peak memory 217408 kb
Host smart-c4a2b424-34b6-46ca-a5a3-4bbff4b824cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161031597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2161031597
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2328139308
Short name T743
Test name
Test status
Simulation time 128274465 ps
CPU time 1.53 seconds
Started Jul 10 07:01:08 PM PDT 24
Finished Jul 10 07:01:10 PM PDT 24
Peak memory 218148 kb
Host smart-37dfb0c6-77f6-4a79-afaa-e12438755d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328139308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2328139308
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1904498300
Short name T496
Test name
Test status
Simulation time 342206666 ps
CPU time 10.19 seconds
Started Jul 10 07:01:08 PM PDT 24
Finished Jul 10 07:01:19 PM PDT 24
Peak memory 218960 kb
Host smart-d9801623-6bf5-4650-9d47-30a6bae320d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904498300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1904498300
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3526133845
Short name T174
Test name
Test status
Simulation time 259413537 ps
CPU time 11.93 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:01:20 PM PDT 24
Peak memory 225964 kb
Host smart-83ab1be7-9c5b-4cb9-8acc-91c30096187c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526133845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3526133845
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3001035110
Short name T320
Test name
Test status
Simulation time 604018539 ps
CPU time 13.45 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:01:22 PM PDT 24
Peak memory 218220 kb
Host smart-049d5979-2529-4efd-a184-a009176d5132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001035110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3001035110
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.830496074
Short name T75
Test name
Test status
Simulation time 23991440 ps
CPU time 1.62 seconds
Started Jul 10 07:01:06 PM PDT 24
Finished Jul 10 07:01:09 PM PDT 24
Peak memory 217740 kb
Host smart-659215f8-655c-46cd-81ed-cec28a54bd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830496074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.830496074
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2297694288
Short name T643
Test name
Test status
Simulation time 878156266 ps
CPU time 21.47 seconds
Started Jul 10 07:01:10 PM PDT 24
Finished Jul 10 07:01:32 PM PDT 24
Peak memory 251044 kb
Host smart-97fd8ef7-3c4f-4e89-937d-191861866eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297694288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2297694288
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3131920090
Short name T455
Test name
Test status
Simulation time 190426751 ps
CPU time 6.31 seconds
Started Jul 10 07:01:09 PM PDT 24
Finished Jul 10 07:01:16 PM PDT 24
Peak memory 246272 kb
Host smart-dcd8eab8-920d-4c19-a197-628548b8cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131920090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3131920090
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4131285207
Short name T206
Test name
Test status
Simulation time 9854567974 ps
CPU time 194.59 seconds
Started Jul 10 07:01:09 PM PDT 24
Finished Jul 10 07:04:24 PM PDT 24
Peak memory 284016 kb
Host smart-3c47edb7-4b0d-4655-9d1c-d1cbc3c6225c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131285207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4131285207
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3607489274
Short name T150
Test name
Test status
Simulation time 109609319667 ps
CPU time 1024.42 seconds
Started Jul 10 07:01:07 PM PDT 24
Finished Jul 10 07:18:13 PM PDT 24
Peak memory 496804 kb
Host smart-1640ced8-161e-4749-8e4f-bc4658f6d31f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3607489274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3607489274
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2137719680
Short name T378
Test name
Test status
Simulation time 10809359 ps
CPU time 1.01 seconds
Started Jul 10 07:01:05 PM PDT 24
Finished Jul 10 07:01:07 PM PDT 24
Peak memory 211900 kb
Host smart-f02f8fc2-ac25-4547-a36c-c2fce4a60600
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137719680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2137719680
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3682505235
Short name T161
Test name
Test status
Simulation time 13828045 ps
CPU time 0.87 seconds
Started Jul 10 07:01:15 PM PDT 24
Finished Jul 10 07:01:17 PM PDT 24
Peak memory 208808 kb
Host smart-db042235-3336-4ebb-ab7d-2f2eec49d95f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682505235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3682505235
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3178125413
Short name T842
Test name
Test status
Simulation time 893519385 ps
CPU time 8.89 seconds
Started Jul 10 07:01:17 PM PDT 24
Finished Jul 10 07:01:27 PM PDT 24
Peak memory 218236 kb
Host smart-89bb666d-eeed-45ac-8f36-568ebb2425a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178125413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3178125413
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2208121752
Short name T816
Test name
Test status
Simulation time 574444255 ps
CPU time 3.89 seconds
Started Jul 10 07:01:18 PM PDT 24
Finished Jul 10 07:01:22 PM PDT 24
Peak memory 217764 kb
Host smart-a24625cc-c340-4136-b456-1cec78572fd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208121752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2208121752
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2616820962
Short name T583
Test name
Test status
Simulation time 54148518 ps
CPU time 2.43 seconds
Started Jul 10 07:01:17 PM PDT 24
Finished Jul 10 07:01:20 PM PDT 24
Peak memory 222252 kb
Host smart-baf0dd25-40c8-4ccf-9002-cd5b56064d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616820962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2616820962
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.420416336
Short name T482
Test name
Test status
Simulation time 3547520532 ps
CPU time 17.43 seconds
Started Jul 10 07:01:16 PM PDT 24
Finished Jul 10 07:01:34 PM PDT 24
Peak memory 226100 kb
Host smart-f270b504-7cf4-4b7d-b7c1-b2e76891ecbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420416336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.420416336
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.75044176
Short name T676
Test name
Test status
Simulation time 775466168 ps
CPU time 6.83 seconds
Started Jul 10 07:01:14 PM PDT 24
Finished Jul 10 07:01:22 PM PDT 24
Peak memory 218240 kb
Host smart-42587b0b-70f4-434f-9b46-d4e4b0ab8c86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75044176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.75044176
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2339401014
Short name T607
Test name
Test status
Simulation time 13973336 ps
CPU time 1.32 seconds
Started Jul 10 07:01:15 PM PDT 24
Finished Jul 10 07:01:17 PM PDT 24
Peak memory 213660 kb
Host smart-71d2bb10-1b7e-4518-82b5-5b7cb112d51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339401014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2339401014
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1560361177
Short name T431
Test name
Test status
Simulation time 1480354262 ps
CPU time 28.59 seconds
Started Jul 10 07:01:14 PM PDT 24
Finished Jul 10 07:01:43 PM PDT 24
Peak memory 250972 kb
Host smart-c8f95632-20ba-42fe-914a-63d548fb3faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560361177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1560361177
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.322671424
Short name T165
Test name
Test status
Simulation time 1266586680 ps
CPU time 7.33 seconds
Started Jul 10 07:01:16 PM PDT 24
Finished Jul 10 07:01:24 PM PDT 24
Peak memory 250516 kb
Host smart-e9de8fcd-0873-4a72-9079-0209396d1c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322671424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.322671424
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3871757602
Short name T80
Test name
Test status
Simulation time 12176734053 ps
CPU time 261.17 seconds
Started Jul 10 07:01:18 PM PDT 24
Finished Jul 10 07:05:40 PM PDT 24
Peak memory 221752 kb
Host smart-6f86a966-6283-4c3c-8a09-3873b9dd7e49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871757602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3871757602
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.387243437
Short name T202
Test name
Test status
Simulation time 12097136 ps
CPU time 1.02 seconds
Started Jul 10 07:01:14 PM PDT 24
Finished Jul 10 07:01:15 PM PDT 24
Peak memory 211856 kb
Host smart-d12129c5-76a6-4c71-8aa2-3c5fea876c71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387243437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.387243437
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3547892999
Short name T518
Test name
Test status
Simulation time 21916255 ps
CPU time 0.94 seconds
Started Jul 10 07:01:29 PM PDT 24
Finished Jul 10 07:01:31 PM PDT 24
Peak memory 209016 kb
Host smart-9bfdce43-5a0d-48ad-9c0a-fa171ecb4b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547892999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3547892999
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3586047698
Short name T232
Test name
Test status
Simulation time 364287482 ps
CPU time 12.73 seconds
Started Jul 10 07:01:14 PM PDT 24
Finished Jul 10 07:01:28 PM PDT 24
Peak memory 226048 kb
Host smart-ab7b76b6-d024-473e-b951-e4e5d968ef31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586047698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3586047698
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1515824620
Short name T650
Test name
Test status
Simulation time 853699076 ps
CPU time 20.41 seconds
Started Jul 10 07:01:23 PM PDT 24
Finished Jul 10 07:01:45 PM PDT 24
Peak memory 217492 kb
Host smart-d86eb1e9-4b54-4325-989a-e334c1bb92a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515824620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1515824620
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.617532918
Short name T209
Test name
Test status
Simulation time 120699412 ps
CPU time 5.26 seconds
Started Jul 10 07:01:14 PM PDT 24
Finished Jul 10 07:01:20 PM PDT 24
Peak memory 218212 kb
Host smart-fd160b9d-72d2-440f-83ae-97bca9405b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617532918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.617532918
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3896024332
Short name T62
Test name
Test status
Simulation time 250766171 ps
CPU time 10.25 seconds
Started Jul 10 07:01:30 PM PDT 24
Finished Jul 10 07:01:41 PM PDT 24
Peak memory 226048 kb
Host smart-6869ada6-e517-488a-a7e0-46df71f3611c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896024332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3896024332
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1805588817
Short name T296
Test name
Test status
Simulation time 401646708 ps
CPU time 15.56 seconds
Started Jul 10 07:01:21 PM PDT 24
Finished Jul 10 07:01:38 PM PDT 24
Peak memory 226044 kb
Host smart-062c966a-e1b0-4b8a-afd4-5a6567dc0ef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805588817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1805588817
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1166323881
Short name T393
Test name
Test status
Simulation time 1167542656 ps
CPU time 12.62 seconds
Started Jul 10 07:01:24 PM PDT 24
Finished Jul 10 07:01:37 PM PDT 24
Peak memory 218252 kb
Host smart-3455a19f-3db5-4af5-b0b8-70cae0eccfd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166323881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1166323881
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3347651961
Short name T51
Test name
Test status
Simulation time 1258986709 ps
CPU time 14.16 seconds
Started Jul 10 07:01:14 PM PDT 24
Finished Jul 10 07:01:29 PM PDT 24
Peak memory 226052 kb
Host smart-30682893-8ee3-4c21-9768-95f3855e82a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347651961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3347651961
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2947250474
Short name T380
Test name
Test status
Simulation time 132829701 ps
CPU time 2.64 seconds
Started Jul 10 07:01:15 PM PDT 24
Finished Jul 10 07:01:18 PM PDT 24
Peak memory 223724 kb
Host smart-95e7e2da-5e47-4ee6-bd4a-83832d2bc250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947250474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2947250474
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2952865696
Short name T414
Test name
Test status
Simulation time 877716891 ps
CPU time 35.72 seconds
Started Jul 10 07:01:15 PM PDT 24
Finished Jul 10 07:01:51 PM PDT 24
Peak memory 250904 kb
Host smart-697dace1-c60a-4911-8953-84d0980d8f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952865696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2952865696
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.987899877
Short name T172
Test name
Test status
Simulation time 357689725 ps
CPU time 6.7 seconds
Started Jul 10 07:01:14 PM PDT 24
Finished Jul 10 07:01:22 PM PDT 24
Peak memory 250552 kb
Host smart-e9a82125-3764-4400-8021-2613dab8b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987899877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.987899877
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2304831500
Short name T103
Test name
Test status
Simulation time 11428021884 ps
CPU time 43.57 seconds
Started Jul 10 07:01:22 PM PDT 24
Finished Jul 10 07:02:07 PM PDT 24
Peak memory 226100 kb
Host smart-7772703d-a2d7-406d-a89b-7bb80018c485
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304831500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2304831500
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2985951608
Short name T521
Test name
Test status
Simulation time 42789920 ps
CPU time 0.97 seconds
Started Jul 10 07:01:18 PM PDT 24
Finished Jul 10 07:01:20 PM PDT 24
Peak memory 211920 kb
Host smart-d0fb498c-6f1a-4431-a7e6-748fb3516bbe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985951608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2985951608
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2961085989
Short name T295
Test name
Test status
Simulation time 54716846 ps
CPU time 1.15 seconds
Started Jul 10 07:01:32 PM PDT 24
Finished Jul 10 07:01:34 PM PDT 24
Peak memory 208972 kb
Host smart-619b23c8-f0d6-4b19-a63e-17e9425f49e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961085989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2961085989
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2534154661
Short name T242
Test name
Test status
Simulation time 864189512 ps
CPU time 10.43 seconds
Started Jul 10 07:01:22 PM PDT 24
Finished Jul 10 07:01:34 PM PDT 24
Peak memory 218224 kb
Host smart-83489de6-b22d-4239-a1c2-f590316573c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534154661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2534154661
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.4057453646
Short name T96
Test name
Test status
Simulation time 371825201 ps
CPU time 5.26 seconds
Started Jul 10 07:01:24 PM PDT 24
Finished Jul 10 07:01:30 PM PDT 24
Peak memory 217480 kb
Host smart-75b6472c-3b7d-4207-80b3-80cba45da761
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057453646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.4057453646
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1320135576
Short name T837
Test name
Test status
Simulation time 134863646 ps
CPU time 5.39 seconds
Started Jul 10 07:01:22 PM PDT 24
Finished Jul 10 07:01:28 PM PDT 24
Peak memory 222476 kb
Host smart-8129020a-4f0e-408f-8e38-c6f2b2b3989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320135576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1320135576
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.956057310
Short name T481
Test name
Test status
Simulation time 236329415 ps
CPU time 11.07 seconds
Started Jul 10 07:01:30 PM PDT 24
Finished Jul 10 07:01:42 PM PDT 24
Peak memory 226040 kb
Host smart-761d2eeb-0297-4b56-b4c7-1df97bbfca83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956057310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.956057310
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.779561287
Short name T858
Test name
Test status
Simulation time 312115102 ps
CPU time 14.09 seconds
Started Jul 10 07:01:30 PM PDT 24
Finished Jul 10 07:01:45 PM PDT 24
Peak memory 226036 kb
Host smart-052b4681-1b55-41c2-b1cb-1712e5d47492
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779561287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.779561287
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3521228273
Short name T264
Test name
Test status
Simulation time 1778820366 ps
CPU time 15.35 seconds
Started Jul 10 07:01:31 PM PDT 24
Finished Jul 10 07:01:48 PM PDT 24
Peak memory 218216 kb
Host smart-d88d3982-950c-40ee-a1f1-d889b01fbb1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521228273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3521228273
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2671941739
Short name T630
Test name
Test status
Simulation time 3531870906 ps
CPU time 10.58 seconds
Started Jul 10 07:01:30 PM PDT 24
Finished Jul 10 07:01:42 PM PDT 24
Peak memory 226096 kb
Host smart-bf740941-394a-40fc-954c-0e05f0c2874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671941739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2671941739
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2191329523
Short name T615
Test name
Test status
Simulation time 64245386 ps
CPU time 1.29 seconds
Started Jul 10 07:01:23 PM PDT 24
Finished Jul 10 07:01:25 PM PDT 24
Peak memory 217820 kb
Host smart-3c50787b-e23c-4922-af2a-304cfcd886d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191329523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2191329523
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2839936889
Short name T536
Test name
Test status
Simulation time 439441513 ps
CPU time 24.42 seconds
Started Jul 10 07:01:23 PM PDT 24
Finished Jul 10 07:01:48 PM PDT 24
Peak memory 250980 kb
Host smart-c1813036-eaf9-4b64-8118-ffbfc62d1510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839936889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2839936889
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1826789329
Short name T693
Test name
Test status
Simulation time 2214834976 ps
CPU time 7.8 seconds
Started Jul 10 07:01:25 PM PDT 24
Finished Jul 10 07:01:34 PM PDT 24
Peak memory 247520 kb
Host smart-5fcc0a89-8ba9-4430-9397-8d408825be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826789329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1826789329
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1673402806
Short name T362
Test name
Test status
Simulation time 1958342062 ps
CPU time 36.66 seconds
Started Jul 10 07:01:31 PM PDT 24
Finished Jul 10 07:02:08 PM PDT 24
Peak memory 251044 kb
Host smart-a4ce3cfc-87db-43f3-9f2f-ed659a33da03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673402806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1673402806
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.414520193
Short name T750
Test name
Test status
Simulation time 12423434 ps
CPU time 1.07 seconds
Started Jul 10 07:01:23 PM PDT 24
Finished Jul 10 07:01:24 PM PDT 24
Peak memory 211928 kb
Host smart-3741d7f4-4df8-48f4-8471-83202bb11a93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414520193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.414520193
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1340814578
Short name T28
Test name
Test status
Simulation time 88099257 ps
CPU time 1.11 seconds
Started Jul 10 07:01:30 PM PDT 24
Finished Jul 10 07:01:32 PM PDT 24
Peak memory 208964 kb
Host smart-0a7a190e-5577-4cf4-b2c5-b6d3b96116c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340814578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1340814578
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2017627040
Short name T726
Test name
Test status
Simulation time 461326432 ps
CPU time 15.41 seconds
Started Jul 10 07:01:31 PM PDT 24
Finished Jul 10 07:01:48 PM PDT 24
Peak memory 218224 kb
Host smart-d6e5d1ad-31f1-4bdb-83c3-21463ae6080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017627040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2017627040
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4287926738
Short name T556
Test name
Test status
Simulation time 1068470212 ps
CPU time 24.27 seconds
Started Jul 10 07:01:31 PM PDT 24
Finished Jul 10 07:01:56 PM PDT 24
Peak memory 217336 kb
Host smart-cb8a8308-e18c-4e45-a7e4-c9273d515a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287926738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4287926738
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.331167455
Short name T226
Test name
Test status
Simulation time 403590194 ps
CPU time 3.57 seconds
Started Jul 10 07:01:32 PM PDT 24
Finished Jul 10 07:01:36 PM PDT 24
Peak memory 222568 kb
Host smart-3fb0436b-c725-4ed1-b2c8-a3a29abae66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331167455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.331167455
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2168885818
Short name T276
Test name
Test status
Simulation time 1345132455 ps
CPU time 15.39 seconds
Started Jul 10 07:01:31 PM PDT 24
Finished Jul 10 07:01:47 PM PDT 24
Peak memory 226020 kb
Host smart-edf61bee-fc50-4e21-91ea-5231366633ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168885818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2168885818
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3362161318
Short name T211
Test name
Test status
Simulation time 793108839 ps
CPU time 9.02 seconds
Started Jul 10 07:01:32 PM PDT 24
Finished Jul 10 07:01:42 PM PDT 24
Peak memory 226032 kb
Host smart-d52d6838-2fd2-48b8-b0c4-61e3347d7109
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362161318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3362161318
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3776918951
Short name T553
Test name
Test status
Simulation time 331123097 ps
CPU time 11.65 seconds
Started Jul 10 07:01:31 PM PDT 24
Finished Jul 10 07:01:44 PM PDT 24
Peak memory 218248 kb
Host smart-d033e4c4-59c6-4542-a691-dec9a2194787
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776918951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3776918951
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.63743344
Short name T671
Test name
Test status
Simulation time 977087070 ps
CPU time 11.22 seconds
Started Jul 10 07:01:33 PM PDT 24
Finished Jul 10 07:01:45 PM PDT 24
Peak memory 218284 kb
Host smart-6f8ef4d0-f719-4a5b-a467-4ecaa9460995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63743344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.63743344
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3854936401
Short name T246
Test name
Test status
Simulation time 48907648 ps
CPU time 2.91 seconds
Started Jul 10 07:01:31 PM PDT 24
Finished Jul 10 07:01:35 PM PDT 24
Peak memory 214716 kb
Host smart-1ff63315-60ef-44f1-aca7-0fcf10f44f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854936401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3854936401
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2511124142
Short name T418
Test name
Test status
Simulation time 180208215 ps
CPU time 19.31 seconds
Started Jul 10 07:01:29 PM PDT 24
Finished Jul 10 07:01:50 PM PDT 24
Peak memory 250976 kb
Host smart-df64f8e7-f2ed-4c30-aa8b-64bef127a4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511124142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2511124142
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1245741869
Short name T238
Test name
Test status
Simulation time 73914123 ps
CPU time 8.26 seconds
Started Jul 10 07:01:29 PM PDT 24
Finished Jul 10 07:01:38 PM PDT 24
Peak memory 250960 kb
Host smart-e21184f0-f498-432d-a8a4-5d90482e6b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245741869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1245741869
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.990907805
Short name T458
Test name
Test status
Simulation time 39545666009 ps
CPU time 178.83 seconds
Started Jul 10 07:01:32 PM PDT 24
Finished Jul 10 07:04:32 PM PDT 24
Peak memory 275036 kb
Host smart-cd9ce691-8a37-4f52-b265-3562c6feecba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990907805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.990907805
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3059686032
Short name T758
Test name
Test status
Simulation time 59844238 ps
CPU time 1 seconds
Started Jul 10 07:01:37 PM PDT 24
Finished Jul 10 07:01:38 PM PDT 24
Peak memory 208964 kb
Host smart-d6e1a2bc-34a7-4a90-b0b1-e2b44936c63c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059686032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3059686032
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.660226447
Short name T610
Test name
Test status
Simulation time 784223383 ps
CPU time 8.25 seconds
Started Jul 10 07:01:36 PM PDT 24
Finished Jul 10 07:01:44 PM PDT 24
Peak memory 218288 kb
Host smart-fe2eb090-2f21-4d03-98b7-0674300d2087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660226447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.660226447
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2674272005
Short name T39
Test name
Test status
Simulation time 95438422 ps
CPU time 2.95 seconds
Started Jul 10 07:01:40 PM PDT 24
Finished Jul 10 07:01:43 PM PDT 24
Peak memory 217084 kb
Host smart-c99caf3c-5681-443a-a455-673121b12ace
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674272005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2674272005
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.789110617
Short name T669
Test name
Test status
Simulation time 123110422 ps
CPU time 2.81 seconds
Started Jul 10 07:01:37 PM PDT 24
Finished Jul 10 07:01:41 PM PDT 24
Peak memory 218208 kb
Host smart-3840d718-8f1b-4857-8942-a0567b990c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789110617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.789110617
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.478376728
Short name T761
Test name
Test status
Simulation time 293029874 ps
CPU time 14.98 seconds
Started Jul 10 07:01:37 PM PDT 24
Finished Jul 10 07:01:53 PM PDT 24
Peak memory 226028 kb
Host smart-80053664-a14f-403e-9772-86d0f4c6d9af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478376728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.478376728
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3008097612
Short name T623
Test name
Test status
Simulation time 2560283848 ps
CPU time 13.35 seconds
Started Jul 10 07:01:39 PM PDT 24
Finished Jul 10 07:01:53 PM PDT 24
Peak memory 226092 kb
Host smart-1b8e9cfb-37f5-4d61-a9c4-b522d2858011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008097612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3008097612
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2826599446
Short name T265
Test name
Test status
Simulation time 4120976534 ps
CPU time 13.63 seconds
Started Jul 10 07:01:38 PM PDT 24
Finished Jul 10 07:01:53 PM PDT 24
Peak memory 226096 kb
Host smart-356bcfda-acff-41f1-9e58-eb79c9e943e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826599446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2826599446
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3003052936
Short name T241
Test name
Test status
Simulation time 301153734 ps
CPU time 11.3 seconds
Started Jul 10 07:01:42 PM PDT 24
Finished Jul 10 07:01:53 PM PDT 24
Peak memory 224984 kb
Host smart-ede8cf84-f203-4903-838c-88b1f96707bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003052936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3003052936
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.854225075
Short name T654
Test name
Test status
Simulation time 15068473 ps
CPU time 1.22 seconds
Started Jul 10 07:01:41 PM PDT 24
Finished Jul 10 07:01:43 PM PDT 24
Peak memory 217696 kb
Host smart-a9e843f4-cda3-4279-9b9f-d4d98258fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854225075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.854225075
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1106970847
Short name T41
Test name
Test status
Simulation time 301391969 ps
CPU time 33.21 seconds
Started Jul 10 07:01:41 PM PDT 24
Finished Jul 10 07:02:15 PM PDT 24
Peak memory 250964 kb
Host smart-d0200b57-7e21-4102-a19a-eafbd096780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106970847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1106970847
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.194729946
Short name T205
Test name
Test status
Simulation time 199359583 ps
CPU time 7.19 seconds
Started Jul 10 07:01:40 PM PDT 24
Finished Jul 10 07:01:48 PM PDT 24
Peak memory 250988 kb
Host smart-edef0d22-ad77-49c1-b280-0fafacbead48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194729946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.194729946
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2748775924
Short name T659
Test name
Test status
Simulation time 7801857509 ps
CPU time 138.58 seconds
Started Jul 10 07:01:36 PM PDT 24
Finished Jul 10 07:03:56 PM PDT 24
Peak memory 283740 kb
Host smart-dd8d130b-3310-4792-962a-7840abc26ce4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748775924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2748775924
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3167189112
Short name T560
Test name
Test status
Simulation time 11444420 ps
CPU time 0.9 seconds
Started Jul 10 07:01:36 PM PDT 24
Finished Jul 10 07:01:38 PM PDT 24
Peak memory 211964 kb
Host smart-ba9f69a9-9f03-4250-867d-23920800bdfe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167189112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3167189112
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.653849785
Short name T522
Test name
Test status
Simulation time 27981104 ps
CPU time 0.88 seconds
Started Jul 10 06:56:54 PM PDT 24
Finished Jul 10 06:56:55 PM PDT 24
Peak memory 209016 kb
Host smart-3b15f9a6-dc41-46ff-be39-e979d8b77793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653849785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.653849785
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.286837308
Short name T345
Test name
Test status
Simulation time 1997302537 ps
CPU time 13.01 seconds
Started Jul 10 06:56:46 PM PDT 24
Finished Jul 10 06:57:00 PM PDT 24
Peak memory 226080 kb
Host smart-2a56c8d2-84e4-41c4-9eff-b47fea08c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286837308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.286837308
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1391555032
Short name T36
Test name
Test status
Simulation time 287836033 ps
CPU time 3.76 seconds
Started Jul 10 06:57:00 PM PDT 24
Finished Jul 10 06:57:05 PM PDT 24
Peak memory 216960 kb
Host smart-d8ccec97-7640-4aee-8e57-b7db72597cad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391555032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1391555032
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1567505670
Short name T42
Test name
Test status
Simulation time 3069542905 ps
CPU time 43.53 seconds
Started Jul 10 06:56:47 PM PDT 24
Finished Jul 10 06:57:32 PM PDT 24
Peak memory 219940 kb
Host smart-0e389d19-cb93-4801-adf1-da5b1fcf831d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567505670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1567505670
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1290692193
Short name T641
Test name
Test status
Simulation time 137698531 ps
CPU time 2.88 seconds
Started Jul 10 06:56:47 PM PDT 24
Finished Jul 10 06:56:51 PM PDT 24
Peak memory 217816 kb
Host smart-35164c06-f9db-43f8-ab8c-02800c5432d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290692193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
290692193
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.550055400
Short name T395
Test name
Test status
Simulation time 1633998790 ps
CPU time 6.2 seconds
Started Jul 10 06:56:48 PM PDT 24
Finished Jul 10 06:56:55 PM PDT 24
Peak memory 222936 kb
Host smart-2dab88ae-40de-43a5-bd34-50ef6853792b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550055400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.550055400
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3028462496
Short name T538
Test name
Test status
Simulation time 10741050993 ps
CPU time 10.79 seconds
Started Jul 10 06:56:46 PM PDT 24
Finished Jul 10 06:56:58 PM PDT 24
Peak memory 217896 kb
Host smart-bed8b8ec-1118-43ac-b8d4-012a6bfd17e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028462496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3028462496
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.555089768
Short name T515
Test name
Test status
Simulation time 152008052 ps
CPU time 2.76 seconds
Started Jul 10 06:56:48 PM PDT 24
Finished Jul 10 06:56:51 PM PDT 24
Peak memory 217696 kb
Host smart-c8a3ca08-1419-4fe4-b225-36ed116775c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555089768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.555089768
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2130353733
Short name T429
Test name
Test status
Simulation time 1250841345 ps
CPU time 50.31 seconds
Started Jul 10 06:56:47 PM PDT 24
Finished Jul 10 06:57:38 PM PDT 24
Peak memory 267352 kb
Host smart-32c6db88-9de6-4db5-951d-b7f636bf75b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130353733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2130353733
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1687860660
Short name T648
Test name
Test status
Simulation time 457453982 ps
CPU time 12.72 seconds
Started Jul 10 06:57:01 PM PDT 24
Finished Jul 10 06:57:15 PM PDT 24
Peak memory 250880 kb
Host smart-b530204e-91f9-4faf-be66-cb6f986ceb78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687860660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1687860660
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4068953278
Short name T279
Test name
Test status
Simulation time 220907347 ps
CPU time 2.99 seconds
Started Jul 10 06:56:55 PM PDT 24
Finished Jul 10 06:56:59 PM PDT 24
Peak memory 218204 kb
Host smart-879ef410-42fe-486d-84c6-6605e3072eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068953278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4068953278
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1298443888
Short name T30
Test name
Test status
Simulation time 2507298177 ps
CPU time 15.75 seconds
Started Jul 10 06:56:47 PM PDT 24
Finished Jul 10 06:57:04 PM PDT 24
Peak memory 217760 kb
Host smart-90da4d69-1d5f-49c6-a9fa-91c35e4c1ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298443888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1298443888
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3598256773
Short name T101
Test name
Test status
Simulation time 234314588 ps
CPU time 22.77 seconds
Started Jul 10 06:56:55 PM PDT 24
Finished Jul 10 06:57:19 PM PDT 24
Peak memory 281588 kb
Host smart-f52c2071-2f19-472d-9208-68d218b7d24e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598256773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3598256773
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2911074079
Short name T678
Test name
Test status
Simulation time 1296643462 ps
CPU time 15.17 seconds
Started Jul 10 06:56:46 PM PDT 24
Finished Jul 10 06:57:02 PM PDT 24
Peak memory 226036 kb
Host smart-203f9070-a636-4e25-bd8c-01587cf375a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911074079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2911074079
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.713442020
Short name T857
Test name
Test status
Simulation time 814394312 ps
CPU time 9.43 seconds
Started Jul 10 06:57:00 PM PDT 24
Finished Jul 10 06:57:10 PM PDT 24
Peak memory 225976 kb
Host smart-9f817e65-e4c3-44bb-b124-4d0fa3ba027d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713442020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.713442020
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1530503206
Short name T308
Test name
Test status
Simulation time 1178198000 ps
CPU time 7.05 seconds
Started Jul 10 06:56:48 PM PDT 24
Finished Jul 10 06:56:56 PM PDT 24
Peak memory 218244 kb
Host smart-38f8f71c-718a-43a9-b906-32045c9f7f62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530503206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
530503206
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2441331138
Short name T690
Test name
Test status
Simulation time 291320766 ps
CPU time 8.45 seconds
Started Jul 10 06:57:00 PM PDT 24
Finished Jul 10 06:57:09 PM PDT 24
Peak memory 218204 kb
Host smart-2b8c5689-a548-4e3f-a35c-de3a3b35da91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441331138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2441331138
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2487456198
Short name T383
Test name
Test status
Simulation time 821427373 ps
CPU time 7.9 seconds
Started Jul 10 06:56:41 PM PDT 24
Finished Jul 10 06:56:50 PM PDT 24
Peak memory 217716 kb
Host smart-4c94720c-6694-41ee-b91f-4e2ea6edbca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487456198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2487456198
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.46206674
Short name T287
Test name
Test status
Simulation time 1494616013 ps
CPU time 31.85 seconds
Started Jul 10 06:56:48 PM PDT 24
Finished Jul 10 06:57:21 PM PDT 24
Peak memory 250888 kb
Host smart-27e3601d-2a70-4e8d-8dce-dbfc4fcdbd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46206674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.46206674
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3518270699
Short name T360
Test name
Test status
Simulation time 68279196 ps
CPU time 8.1 seconds
Started Jul 10 06:56:48 PM PDT 24
Finished Jul 10 06:56:58 PM PDT 24
Peak memory 250992 kb
Host smart-d271f8e7-ec20-4fe9-828f-000b94951f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518270699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3518270699
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2604991405
Short name T346
Test name
Test status
Simulation time 6768216062 ps
CPU time 55.6 seconds
Started Jul 10 06:57:02 PM PDT 24
Finished Jul 10 06:57:59 PM PDT 24
Peak memory 251028 kb
Host smart-bc35b24d-3287-4f20-b62a-833cff7f8870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604991405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2604991405
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1078795737
Short name T800
Test name
Test status
Simulation time 38696838 ps
CPU time 0.84 seconds
Started Jul 10 06:56:39 PM PDT 24
Finished Jul 10 06:56:40 PM PDT 24
Peak memory 211960 kb
Host smart-bd5564ad-bb92-4978-9041-eb27ea34077b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078795737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1078795737
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.140171696
Short name T688
Test name
Test status
Simulation time 108884476 ps
CPU time 0.92 seconds
Started Jul 10 07:01:43 PM PDT 24
Finished Jul 10 07:01:45 PM PDT 24
Peak memory 209012 kb
Host smart-a454c36a-8725-4b9f-a72c-3a45cbc98ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140171696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.140171696
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2263554233
Short name T680
Test name
Test status
Simulation time 530224589 ps
CPU time 9.87 seconds
Started Jul 10 07:01:47 PM PDT 24
Finished Jul 10 07:01:58 PM PDT 24
Peak memory 218216 kb
Host smart-30363ceb-77d7-497f-b222-670da48de1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263554233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2263554233
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1903505010
Short name T288
Test name
Test status
Simulation time 219136841 ps
CPU time 1.34 seconds
Started Jul 10 07:01:47 PM PDT 24
Finished Jul 10 07:01:50 PM PDT 24
Peak memory 217160 kb
Host smart-12a844d5-2b10-4565-ac6c-9f8a9d0e3c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903505010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1903505010
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3975410467
Short name T673
Test name
Test status
Simulation time 313494453 ps
CPU time 3.27 seconds
Started Jul 10 07:01:46 PM PDT 24
Finished Jul 10 07:01:51 PM PDT 24
Peak memory 222184 kb
Host smart-82a682a2-6fe0-4bc8-9344-0bf97ded0372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975410467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3975410467
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3058816849
Short name T390
Test name
Test status
Simulation time 1725961980 ps
CPU time 9.72 seconds
Started Jul 10 07:01:45 PM PDT 24
Finished Jul 10 07:01:56 PM PDT 24
Peak memory 226044 kb
Host smart-7d944e5b-0bd0-48e5-b342-3f426aa8c438
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058816849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3058816849
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1227604769
Short name T748
Test name
Test status
Simulation time 2534941100 ps
CPU time 11.97 seconds
Started Jul 10 07:01:46 PM PDT 24
Finished Jul 10 07:02:00 PM PDT 24
Peak memory 218280 kb
Host smart-85c4046d-10e7-4f4a-89ce-6a15aa5dfeba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227604769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1227604769
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3362566819
Short name T576
Test name
Test status
Simulation time 374696236 ps
CPU time 13.91 seconds
Started Jul 10 07:01:45 PM PDT 24
Finished Jul 10 07:02:00 PM PDT 24
Peak memory 226040 kb
Host smart-2c550bd7-ee49-4863-8844-276319f285ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362566819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3362566819
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.694444319
Short name T775
Test name
Test status
Simulation time 694491195 ps
CPU time 2.38 seconds
Started Jul 10 07:01:45 PM PDT 24
Finished Jul 10 07:01:49 PM PDT 24
Peak memory 217704 kb
Host smart-3d4ad5ae-beed-4886-b45b-cbc0c60e5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694444319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.694444319
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.551316161
Short name T91
Test name
Test status
Simulation time 955629781 ps
CPU time 20.72 seconds
Started Jul 10 07:01:47 PM PDT 24
Finished Jul 10 07:02:09 PM PDT 24
Peak memory 250940 kb
Host smart-f589c11e-448c-4bb3-a72a-18d7e0433b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551316161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.551316161
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3152279331
Short name T520
Test name
Test status
Simulation time 64527946 ps
CPU time 3.81 seconds
Started Jul 10 07:01:47 PM PDT 24
Finished Jul 10 07:01:52 PM PDT 24
Peak memory 226028 kb
Host smart-3b8a9367-2e86-494d-9440-1261c36b396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152279331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3152279331
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2802021023
Short name T452
Test name
Test status
Simulation time 31236444130 ps
CPU time 215.62 seconds
Started Jul 10 07:01:44 PM PDT 24
Finished Jul 10 07:05:21 PM PDT 24
Peak memory 331896 kb
Host smart-8c6f5591-ed74-488d-93ff-9e514a159baf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802021023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2802021023
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2257291607
Short name T530
Test name
Test status
Simulation time 14099189 ps
CPU time 1.07 seconds
Started Jul 10 07:01:45 PM PDT 24
Finished Jul 10 07:01:47 PM PDT 24
Peak memory 211928 kb
Host smart-5e5e6a6d-3314-45fa-98f3-84e5b85d00db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257291607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2257291607
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1630122158
Short name T271
Test name
Test status
Simulation time 12835822 ps
CPU time 0.85 seconds
Started Jul 10 07:01:54 PM PDT 24
Finished Jul 10 07:01:55 PM PDT 24
Peak memory 208800 kb
Host smart-0e2ee291-9c3b-40df-ab59-4d1411977b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630122158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1630122158
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1444431534
Short name T865
Test name
Test status
Simulation time 805813957 ps
CPU time 12.39 seconds
Started Jul 10 07:01:54 PM PDT 24
Finished Jul 10 07:02:07 PM PDT 24
Peak memory 218220 kb
Host smart-c9fe3f79-2916-4c84-9a1f-2a4fe7b98625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444431534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1444431534
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2377138250
Short name T510
Test name
Test status
Simulation time 609856916 ps
CPU time 2.77 seconds
Started Jul 10 07:01:55 PM PDT 24
Finished Jul 10 07:01:59 PM PDT 24
Peak memory 217124 kb
Host smart-ddc4cb77-2bf2-410a-9d00-25ead068143d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377138250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2377138250
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4166672029
Short name T731
Test name
Test status
Simulation time 139556007 ps
CPU time 2.43 seconds
Started Jul 10 07:01:54 PM PDT 24
Finished Jul 10 07:01:58 PM PDT 24
Peak memory 222216 kb
Host smart-3b8d0cb4-b7a7-4edb-a081-91bfa5bd46f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166672029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4166672029
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3042445979
Short name T663
Test name
Test status
Simulation time 433803013 ps
CPU time 12.38 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:13 PM PDT 24
Peak memory 218784 kb
Host smart-088ddee2-1bf3-436e-bb0e-afb12903453c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042445979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3042445979
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3146046392
Short name T861
Test name
Test status
Simulation time 1620009476 ps
CPU time 17.76 seconds
Started Jul 10 07:01:56 PM PDT 24
Finished Jul 10 07:02:14 PM PDT 24
Peak memory 226044 kb
Host smart-7cc2087a-fd7e-4deb-8399-d4baa10d3db5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146046392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3146046392
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.565639014
Short name T447
Test name
Test status
Simulation time 210262136 ps
CPU time 7.07 seconds
Started Jul 10 07:01:55 PM PDT 24
Finished Jul 10 07:02:03 PM PDT 24
Peak memory 218304 kb
Host smart-a0a4312c-ab9a-436b-8025-500c00fb9ef5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565639014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.565639014
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.865740005
Short name T651
Test name
Test status
Simulation time 420920888 ps
CPU time 15.19 seconds
Started Jul 10 07:01:54 PM PDT 24
Finished Jul 10 07:02:10 PM PDT 24
Peak memory 225480 kb
Host smart-4bf1e567-79d3-4472-80fc-f7b69e0608e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865740005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.865740005
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1809024553
Short name T240
Test name
Test status
Simulation time 435911791 ps
CPU time 4.38 seconds
Started Jul 10 07:01:46 PM PDT 24
Finished Jul 10 07:01:51 PM PDT 24
Peak memory 217700 kb
Host smart-0b635119-4e16-4bfb-af98-7d0e4767796b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809024553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1809024553
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.724098904
Short name T110
Test name
Test status
Simulation time 504759358 ps
CPU time 30.47 seconds
Started Jul 10 07:01:46 PM PDT 24
Finished Jul 10 07:02:18 PM PDT 24
Peak memory 251196 kb
Host smart-8b4c8434-2b71-4ae1-9f8d-75499c9117d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724098904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.724098904
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1775243433
Short name T398
Test name
Test status
Simulation time 280132600 ps
CPU time 5.94 seconds
Started Jul 10 07:01:55 PM PDT 24
Finished Jul 10 07:02:02 PM PDT 24
Peak memory 246588 kb
Host smart-89eca04b-0516-4fe0-a0f4-92a2675dbe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775243433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1775243433
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1416238009
Short name T323
Test name
Test status
Simulation time 7675636475 ps
CPU time 225.39 seconds
Started Jul 10 07:01:53 PM PDT 24
Finished Jul 10 07:05:39 PM PDT 24
Peak memory 250992 kb
Host smart-e2388aa2-b60a-489a-a0bd-10f80d2a7bf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416238009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1416238009
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3991998425
Short name T656
Test name
Test status
Simulation time 81256442330 ps
CPU time 524.54 seconds
Started Jul 10 07:01:53 PM PDT 24
Finished Jul 10 07:10:38 PM PDT 24
Peak memory 259336 kb
Host smart-95ee28ce-79e7-4e2b-bea5-7da1b142f644
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3991998425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3991998425
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1908386909
Short name T855
Test name
Test status
Simulation time 73081519 ps
CPU time 0.85 seconds
Started Jul 10 07:01:44 PM PDT 24
Finished Jul 10 07:01:46 PM PDT 24
Peak memory 211832 kb
Host smart-ecaf2645-0b84-4274-87f8-8ba1b12b6b6d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908386909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1908386909
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.272140621
Short name T106
Test name
Test status
Simulation time 36406518 ps
CPU time 0.93 seconds
Started Jul 10 07:01:59 PM PDT 24
Finished Jul 10 07:02:00 PM PDT 24
Peak memory 209012 kb
Host smart-a5f1811d-17f1-45c6-ac4d-5be49d327468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272140621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.272140621
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3518668837
Short name T692
Test name
Test status
Simulation time 913826783 ps
CPU time 19.3 seconds
Started Jul 10 07:01:55 PM PDT 24
Finished Jul 10 07:02:15 PM PDT 24
Peak memory 218232 kb
Host smart-7fdfd767-ceda-42ef-95b5-38265226edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518668837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3518668837
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3110770128
Short name T37
Test name
Test status
Simulation time 246206692 ps
CPU time 6.88 seconds
Started Jul 10 07:01:55 PM PDT 24
Finished Jul 10 07:02:02 PM PDT 24
Peak memory 217092 kb
Host smart-b3ba3786-5b1d-402b-b09f-073580bf336c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110770128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3110770128
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3690543599
Short name T462
Test name
Test status
Simulation time 168016010 ps
CPU time 3.16 seconds
Started Jul 10 07:01:53 PM PDT 24
Finished Jul 10 07:01:57 PM PDT 24
Peak memory 222560 kb
Host smart-d3226a9c-d635-4d80-ab20-bd1d4544cf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690543599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3690543599
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.884257354
Short name T45
Test name
Test status
Simulation time 245046960 ps
CPU time 9.74 seconds
Started Jul 10 07:01:52 PM PDT 24
Finished Jul 10 07:02:03 PM PDT 24
Peak memory 218276 kb
Host smart-388ed7b0-0668-4024-a04c-bec63abd8d6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884257354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.884257354
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.980430028
Short name T483
Test name
Test status
Simulation time 245293018 ps
CPU time 7.98 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:09 PM PDT 24
Peak memory 226012 kb
Host smart-42483bb3-7d61-4e0f-9af2-d11a6f7c69d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980430028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.980430028
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2046317991
Short name T710
Test name
Test status
Simulation time 2375212300 ps
CPU time 8.36 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:10 PM PDT 24
Peak memory 218312 kb
Host smart-7bbc4573-0326-4822-bd88-befe55345d2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046317991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2046317991
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3741718569
Short name T50
Test name
Test status
Simulation time 697424618 ps
CPU time 9.02 seconds
Started Jul 10 07:01:58 PM PDT 24
Finished Jul 10 07:02:07 PM PDT 24
Peak memory 224792 kb
Host smart-a4a30c6d-7d97-4e6a-871c-a0c98176c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741718569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3741718569
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2479004258
Short name T829
Test name
Test status
Simulation time 35390643 ps
CPU time 2.65 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:03 PM PDT 24
Peak memory 214744 kb
Host smart-09e315d7-9932-4871-8311-5e90f01291b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479004258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2479004258
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2811596973
Short name T782
Test name
Test status
Simulation time 452012363 ps
CPU time 18.87 seconds
Started Jul 10 07:01:55 PM PDT 24
Finished Jul 10 07:02:15 PM PDT 24
Peak memory 250992 kb
Host smart-74348bfe-ee2b-4e0a-bf29-5fe2a14d0052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811596973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2811596973
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.741125656
Short name T707
Test name
Test status
Simulation time 466778919 ps
CPU time 8.54 seconds
Started Jul 10 07:01:58 PM PDT 24
Finished Jul 10 07:02:07 PM PDT 24
Peak memory 250916 kb
Host smart-d5ef49bc-f25f-4f8a-a1af-70204c2d0772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741125656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.741125656
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3184051327
Short name T158
Test name
Test status
Simulation time 40695780636 ps
CPU time 572.15 seconds
Started Jul 10 07:02:02 PM PDT 24
Finished Jul 10 07:11:36 PM PDT 24
Peak memory 277176 kb
Host smart-2a1e944d-1afb-4861-83e9-a60e3bbf84ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184051327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3184051327
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2532342990
Short name T603
Test name
Test status
Simulation time 20328893 ps
CPU time 0.95 seconds
Started Jul 10 07:01:54 PM PDT 24
Finished Jul 10 07:01:55 PM PDT 24
Peak memory 211924 kb
Host smart-433a5fff-e27c-4a52-a49b-d56e23a08a90
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532342990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2532342990
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3794949199
Short name T579
Test name
Test status
Simulation time 89077298 ps
CPU time 0.81 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:01 PM PDT 24
Peak memory 208780 kb
Host smart-6125c22b-dffa-4d9f-9dd6-d6f35d89f796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794949199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3794949199
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3858767103
Short name T635
Test name
Test status
Simulation time 275245697 ps
CPU time 9.58 seconds
Started Jul 10 07:02:02 PM PDT 24
Finished Jul 10 07:02:13 PM PDT 24
Peak memory 218220 kb
Host smart-08ca9c86-0092-4158-8234-c1ba148a2e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858767103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3858767103
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4162316328
Short name T700
Test name
Test status
Simulation time 1191210173 ps
CPU time 6.63 seconds
Started Jul 10 07:02:01 PM PDT 24
Finished Jul 10 07:02:08 PM PDT 24
Peak memory 217452 kb
Host smart-611bdcb1-bec3-4a6e-bbaa-c7af3866b687
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162316328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4162316328
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.4229210130
Short name T441
Test name
Test status
Simulation time 95959724 ps
CPU time 2.03 seconds
Started Jul 10 07:02:01 PM PDT 24
Finished Jul 10 07:02:04 PM PDT 24
Peak memory 222204 kb
Host smart-473f4305-0f24-4691-ae11-aef693d0827d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229210130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.4229210130
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.639497105
Short name T461
Test name
Test status
Simulation time 329073776 ps
CPU time 13.91 seconds
Started Jul 10 07:02:01 PM PDT 24
Finished Jul 10 07:02:16 PM PDT 24
Peak memory 226052 kb
Host smart-ad6df008-88bc-4cc1-ae0f-55530223e515
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639497105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.639497105
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.896436164
Short name T702
Test name
Test status
Simulation time 787378233 ps
CPU time 17.63 seconds
Started Jul 10 07:02:03 PM PDT 24
Finished Jul 10 07:02:22 PM PDT 24
Peak memory 225936 kb
Host smart-2a02c5bd-77b6-45f1-96ef-f13c9bba45ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896436164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.896436164
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1900252340
Short name T783
Test name
Test status
Simulation time 1213639117 ps
CPU time 7.45 seconds
Started Jul 10 07:02:01 PM PDT 24
Finished Jul 10 07:02:10 PM PDT 24
Peak memory 218200 kb
Host smart-e19660da-f697-492d-a7d6-e3e44218fb16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900252340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1900252340
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1859659791
Short name T266
Test name
Test status
Simulation time 401847753 ps
CPU time 8.33 seconds
Started Jul 10 07:02:02 PM PDT 24
Finished Jul 10 07:02:11 PM PDT 24
Peak memory 225328 kb
Host smart-20c960c8-b304-4c2b-8038-1a984e399435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859659791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1859659791
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1208688318
Short name T78
Test name
Test status
Simulation time 60391151 ps
CPU time 3.36 seconds
Started Jul 10 07:01:59 PM PDT 24
Finished Jul 10 07:02:03 PM PDT 24
Peak memory 217720 kb
Host smart-f1e1214d-c3d5-4894-b7f4-78ac251f9d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208688318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1208688318
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.369816436
Short name T701
Test name
Test status
Simulation time 287547893 ps
CPU time 25.53 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:26 PM PDT 24
Peak memory 250984 kb
Host smart-c3add093-8992-456a-9c03-481fe426bf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369816436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.369816436
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1316116809
Short name T361
Test name
Test status
Simulation time 261711089 ps
CPU time 4.36 seconds
Started Jul 10 07:01:59 PM PDT 24
Finished Jul 10 07:02:05 PM PDT 24
Peak memory 222360 kb
Host smart-d37120bc-329a-4cf5-a50b-ac57270ee550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316116809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1316116809
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.928860653
Short name T616
Test name
Test status
Simulation time 5588238928 ps
CPU time 138.9 seconds
Started Jul 10 07:02:01 PM PDT 24
Finished Jul 10 07:04:21 PM PDT 24
Peak memory 283768 kb
Host smart-e99cc6ef-a23b-4937-a78a-f3196066be7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928860653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.928860653
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3361948933
Short name T683
Test name
Test status
Simulation time 66109755884 ps
CPU time 202.84 seconds
Started Jul 10 07:02:01 PM PDT 24
Finished Jul 10 07:05:25 PM PDT 24
Peak memory 300292 kb
Host smart-887b76c9-13f6-4237-bbfd-3459b4e21dd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3361948933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3361948933
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1831711653
Short name T506
Test name
Test status
Simulation time 31632194 ps
CPU time 0.88 seconds
Started Jul 10 07:02:01 PM PDT 24
Finished Jul 10 07:02:03 PM PDT 24
Peak memory 211880 kb
Host smart-db676f9d-2f7c-4a8b-add9-2329b8ef8139
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831711653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1831711653
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.278585729
Short name T245
Test name
Test status
Simulation time 38265493 ps
CPU time 0.79 seconds
Started Jul 10 07:02:15 PM PDT 24
Finished Jul 10 07:02:17 PM PDT 24
Peak memory 208992 kb
Host smart-e9912440-3666-4a29-9c34-114f96e3d83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278585729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.278585729
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1485974501
Short name T794
Test name
Test status
Simulation time 373734355 ps
CPU time 18.37 seconds
Started Jul 10 07:02:08 PM PDT 24
Finished Jul 10 07:02:27 PM PDT 24
Peak memory 218156 kb
Host smart-9acf1a8c-7f69-46b9-ba4d-531233a8bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485974501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1485974501
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.403997465
Short name T40
Test name
Test status
Simulation time 1223279486 ps
CPU time 7.19 seconds
Started Jul 10 07:02:09 PM PDT 24
Finished Jul 10 07:02:17 PM PDT 24
Peak memory 217248 kb
Host smart-95f49f30-eaf9-45cb-aaa1-438717d7e7af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403997465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.403997465
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1579137332
Short name T227
Test name
Test status
Simulation time 57957821 ps
CPU time 3.13 seconds
Started Jul 10 07:01:59 PM PDT 24
Finished Jul 10 07:02:02 PM PDT 24
Peak memory 222336 kb
Host smart-68bbeef2-16ea-4e0d-b785-6110b49cab3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579137332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1579137332
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3010336443
Short name T535
Test name
Test status
Simulation time 322686798 ps
CPU time 15.93 seconds
Started Jul 10 07:02:16 PM PDT 24
Finished Jul 10 07:02:33 PM PDT 24
Peak memory 226032 kb
Host smart-4f405c69-5f59-4fb1-aa8b-9be31e544f03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010336443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3010336443
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1447057645
Short name T17
Test name
Test status
Simulation time 1814944057 ps
CPU time 13.73 seconds
Started Jul 10 07:02:10 PM PDT 24
Finished Jul 10 07:02:25 PM PDT 24
Peak memory 226048 kb
Host smart-a81488ac-ed0e-4396-b7c5-8ec24d221dab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447057645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1447057645
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.595818243
Short name T862
Test name
Test status
Simulation time 342421775 ps
CPU time 7.11 seconds
Started Jul 10 07:02:09 PM PDT 24
Finished Jul 10 07:02:17 PM PDT 24
Peak memory 218232 kb
Host smart-a160f765-4862-41be-9bde-e798ab5e2a64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595818243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.595818243
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4220509373
Short name T221
Test name
Test status
Simulation time 23568560 ps
CPU time 1.54 seconds
Started Jul 10 07:02:01 PM PDT 24
Finished Jul 10 07:02:04 PM PDT 24
Peak memory 222132 kb
Host smart-d20fa37e-79f8-4d19-ac0f-9d0d154952f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220509373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4220509373
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2477685514
Short name T645
Test name
Test status
Simulation time 1085770754 ps
CPU time 27.98 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:29 PM PDT 24
Peak memory 250932 kb
Host smart-f54b4e96-4fa8-4c5b-bdd8-a8177d2c5131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477685514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2477685514
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.473770894
Short name T369
Test name
Test status
Simulation time 383702049 ps
CPU time 9.73 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:11 PM PDT 24
Peak memory 250984 kb
Host smart-f9c80e0a-048b-4117-beb5-4d6a4cbbf030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473770894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.473770894
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1094411127
Short name T422
Test name
Test status
Simulation time 4203432717 ps
CPU time 231.37 seconds
Started Jul 10 07:02:09 PM PDT 24
Finished Jul 10 07:06:02 PM PDT 24
Peak memory 300192 kb
Host smart-3b2f417c-8b4d-4f32-ad02-c98c1add2cff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094411127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1094411127
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3443148336
Short name T617
Test name
Test status
Simulation time 34581858 ps
CPU time 0.97 seconds
Started Jul 10 07:02:00 PM PDT 24
Finished Jul 10 07:02:02 PM PDT 24
Peak memory 211884 kb
Host smart-ed776990-fd27-4ce4-95e5-5284fa6d757a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443148336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3443148336
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2375473035
Short name T437
Test name
Test status
Simulation time 62856698 ps
CPU time 1.11 seconds
Started Jul 10 07:02:17 PM PDT 24
Finished Jul 10 07:02:19 PM PDT 24
Peak memory 209048 kb
Host smart-f31addf5-b0a4-4c4b-b4d3-2198e5a2211c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375473035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2375473035
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1405231588
Short name T563
Test name
Test status
Simulation time 672274712 ps
CPU time 11.07 seconds
Started Jul 10 07:02:16 PM PDT 24
Finished Jul 10 07:02:28 PM PDT 24
Peak memory 218148 kb
Host smart-3275f1c1-5aad-4f5e-a0e4-cf4f8a3c7243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405231588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1405231588
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.698690724
Short name T813
Test name
Test status
Simulation time 540735967 ps
CPU time 12.35 seconds
Started Jul 10 07:02:16 PM PDT 24
Finished Jul 10 07:02:29 PM PDT 24
Peak memory 217344 kb
Host smart-aeb76fca-55e5-411d-9570-5d3eff3b847e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698690724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.698690724
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1290734968
Short name T711
Test name
Test status
Simulation time 19614336 ps
CPU time 1.48 seconds
Started Jul 10 07:02:19 PM PDT 24
Finished Jul 10 07:02:21 PM PDT 24
Peak memory 218212 kb
Host smart-be0a026c-93ab-446e-b8ac-e1359942fb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290734968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1290734968
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2579390872
Short name T799
Test name
Test status
Simulation time 1857550111 ps
CPU time 12.86 seconds
Started Jul 10 07:02:15 PM PDT 24
Finished Jul 10 07:02:29 PM PDT 24
Peak memory 219020 kb
Host smart-9dbfaf8f-880a-4d57-858c-fd44ff9e2fc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579390872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2579390872
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2983698971
Short name T436
Test name
Test status
Simulation time 1168436705 ps
CPU time 10.47 seconds
Started Jul 10 07:02:19 PM PDT 24
Finished Jul 10 07:02:30 PM PDT 24
Peak memory 226032 kb
Host smart-d259b2e7-e445-4def-b7e1-8f59f925b26a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983698971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2983698971
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.623893502
Short name T283
Test name
Test status
Simulation time 3610438979 ps
CPU time 13.06 seconds
Started Jul 10 07:02:16 PM PDT 24
Finished Jul 10 07:02:30 PM PDT 24
Peak memory 218300 kb
Host smart-df1b24cc-7b9c-4f9f-ad01-1b01c2a44fce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623893502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.623893502
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2161077164
Short name T355
Test name
Test status
Simulation time 671151609 ps
CPU time 13.06 seconds
Started Jul 10 07:02:18 PM PDT 24
Finished Jul 10 07:02:32 PM PDT 24
Peak memory 226036 kb
Host smart-f6fc8c8d-fb22-4c46-a807-a072d0b9eae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161077164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2161077164
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3729634681
Short name T555
Test name
Test status
Simulation time 219513139 ps
CPU time 2.35 seconds
Started Jul 10 07:02:18 PM PDT 24
Finished Jul 10 07:02:21 PM PDT 24
Peak memory 214596 kb
Host smart-6410fff9-6afc-4abf-a8a5-2a86b29d2f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729634681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3729634681
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1596257724
Short name T237
Test name
Test status
Simulation time 277063783 ps
CPU time 23.25 seconds
Started Jul 10 07:02:09 PM PDT 24
Finished Jul 10 07:02:33 PM PDT 24
Peak memory 251060 kb
Host smart-1cafc223-0614-4322-b9d4-48a6f652af74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596257724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1596257724
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.326942031
Short name T486
Test name
Test status
Simulation time 114965900 ps
CPU time 7.72 seconds
Started Jul 10 07:02:09 PM PDT 24
Finished Jul 10 07:02:17 PM PDT 24
Peak memory 250984 kb
Host smart-3745ccb2-21d5-4529-9081-9fe89664c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326942031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.326942031
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2922182332
Short name T94
Test name
Test status
Simulation time 4421494752 ps
CPU time 127.34 seconds
Started Jul 10 07:02:15 PM PDT 24
Finished Jul 10 07:04:23 PM PDT 24
Peak memory 276512 kb
Host smart-488d16c7-1156-4784-9e0d-fdcf7778c678
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922182332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2922182332
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1902458693
Short name T633
Test name
Test status
Simulation time 14309768 ps
CPU time 1.08 seconds
Started Jul 10 07:02:10 PM PDT 24
Finished Jul 10 07:02:12 PM PDT 24
Peak memory 211928 kb
Host smart-4c89dfc5-07b2-4101-8edf-ccb7df3d33c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902458693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1902458693
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1343653297
Short name T502
Test name
Test status
Simulation time 33330072 ps
CPU time 0.87 seconds
Started Jul 10 07:02:24 PM PDT 24
Finished Jul 10 07:02:25 PM PDT 24
Peak memory 209000 kb
Host smart-c803b459-7141-43c3-9134-665f3b0ae503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343653297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1343653297
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2996960308
Short name T752
Test name
Test status
Simulation time 254248992 ps
CPU time 9.44 seconds
Started Jul 10 07:02:16 PM PDT 24
Finished Jul 10 07:02:27 PM PDT 24
Peak memory 218148 kb
Host smart-6f309835-ed00-4ec3-bf3b-7f7f7d72b497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996960308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2996960308
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.4150040259
Short name T451
Test name
Test status
Simulation time 1063989271 ps
CPU time 4.11 seconds
Started Jul 10 07:02:23 PM PDT 24
Finished Jul 10 07:02:28 PM PDT 24
Peak memory 217108 kb
Host smart-64142299-2c99-47b9-8d20-47401c70cabb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150040259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.4150040259
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.827160818
Short name T539
Test name
Test status
Simulation time 89921952 ps
CPU time 2.76 seconds
Started Jul 10 07:02:17 PM PDT 24
Finished Jul 10 07:02:20 PM PDT 24
Peak memory 218212 kb
Host smart-5c44e991-5b59-41e1-9a6e-fc1ab4668f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827160818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.827160818
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.928167015
Short name T87
Test name
Test status
Simulation time 857674922 ps
CPU time 9.86 seconds
Started Jul 10 07:02:24 PM PDT 24
Finished Jul 10 07:02:35 PM PDT 24
Peak memory 226032 kb
Host smart-eb8bd37a-082e-463e-bd84-3d3ff664a418
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928167015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.928167015
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4052897502
Short name T509
Test name
Test status
Simulation time 278276833 ps
CPU time 10.44 seconds
Started Jul 10 07:02:24 PM PDT 24
Finished Jul 10 07:02:36 PM PDT 24
Peak memory 218236 kb
Host smart-6645445f-2a3b-4eec-8d2a-ac7025ce8951
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052897502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4052897502
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2588902540
Short name T89
Test name
Test status
Simulation time 1023118477 ps
CPU time 7.97 seconds
Started Jul 10 07:02:25 PM PDT 24
Finished Jul 10 07:02:34 PM PDT 24
Peak memory 225068 kb
Host smart-d3ca8b04-83e1-4fda-b337-fbd5a9523b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588902540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2588902540
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2125404270
Short name T728
Test name
Test status
Simulation time 675939959 ps
CPU time 1.97 seconds
Started Jul 10 07:02:18 PM PDT 24
Finished Jul 10 07:02:21 PM PDT 24
Peak memory 214156 kb
Host smart-da4555c4-f832-4b8d-85b9-0faad2c807c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125404270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2125404270
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3012940599
Short name T105
Test name
Test status
Simulation time 280248404 ps
CPU time 26.88 seconds
Started Jul 10 07:02:21 PM PDT 24
Finished Jul 10 07:02:48 PM PDT 24
Peak memory 246880 kb
Host smart-4e945d59-2f2c-4110-bc78-731747fff6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012940599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3012940599
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3473886234
Short name T406
Test name
Test status
Simulation time 132036865 ps
CPU time 3.57 seconds
Started Jul 10 07:02:16 PM PDT 24
Finished Jul 10 07:02:20 PM PDT 24
Peak memory 222952 kb
Host smart-ad526df3-ba5f-4f0c-88b3-8c43c2392ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473886234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3473886234
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.759023369
Short name T788
Test name
Test status
Simulation time 8089779618 ps
CPU time 166.01 seconds
Started Jul 10 07:02:23 PM PDT 24
Finished Jul 10 07:05:10 PM PDT 24
Peak memory 283072 kb
Host smart-6587382a-48c4-46ca-ad3d-3342e8601f0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759023369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.759023369
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2531159459
Short name T253
Test name
Test status
Simulation time 60825326 ps
CPU time 0.84 seconds
Started Jul 10 07:02:16 PM PDT 24
Finished Jul 10 07:02:18 PM PDT 24
Peak memory 211884 kb
Host smart-1bf87c0a-b59d-4616-a9e4-3b8e5da6084e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531159459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2531159459
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2191825746
Short name T72
Test name
Test status
Simulation time 81966423 ps
CPU time 0.95 seconds
Started Jul 10 07:02:34 PM PDT 24
Finished Jul 10 07:02:35 PM PDT 24
Peak memory 208976 kb
Host smart-9695d08c-cdaa-42b3-a908-cc3b87241973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191825746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2191825746
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1809962492
Short name T425
Test name
Test status
Simulation time 1007258019 ps
CPU time 12.66 seconds
Started Jul 10 07:02:24 PM PDT 24
Finished Jul 10 07:02:38 PM PDT 24
Peak memory 218232 kb
Host smart-d348a913-204f-4edc-8b01-0fb8f5874d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809962492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1809962492
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2244097653
Short name T6
Test name
Test status
Simulation time 3867255532 ps
CPU time 12.19 seconds
Started Jul 10 07:02:24 PM PDT 24
Finished Jul 10 07:02:37 PM PDT 24
Peak memory 217948 kb
Host smart-d5385ada-b7e6-418a-9e32-f9fc2bc37db3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244097653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2244097653
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2915648714
Short name T171
Test name
Test status
Simulation time 45219871 ps
CPU time 2.88 seconds
Started Jul 10 07:02:22 PM PDT 24
Finished Jul 10 07:02:25 PM PDT 24
Peak memory 222300 kb
Host smart-bdbb6908-e6b5-4a11-9978-e07509c7e15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915648714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2915648714
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.789726194
Short name T843
Test name
Test status
Simulation time 358282319 ps
CPU time 15.41 seconds
Started Jul 10 07:02:24 PM PDT 24
Finished Jul 10 07:02:40 PM PDT 24
Peak memory 226036 kb
Host smart-fc831ce4-7083-4104-ad11-30f2b206f3f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789726194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.789726194
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.886277241
Short name T20
Test name
Test status
Simulation time 6232209083 ps
CPU time 10.41 seconds
Started Jul 10 07:02:32 PM PDT 24
Finished Jul 10 07:02:44 PM PDT 24
Peak memory 226188 kb
Host smart-fdee08cd-591e-4b58-9d05-0ca9a60453ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886277241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.886277241
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1428450608
Short name T61
Test name
Test status
Simulation time 299868792 ps
CPU time 11.06 seconds
Started Jul 10 07:02:24 PM PDT 24
Finished Jul 10 07:02:37 PM PDT 24
Peak memory 218304 kb
Host smart-f62e5fc5-25a6-40b2-b975-69b01b46ca1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428450608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1428450608
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1618118749
Short name T83
Test name
Test status
Simulation time 324300392 ps
CPU time 11.89 seconds
Started Jul 10 07:02:23 PM PDT 24
Finished Jul 10 07:02:36 PM PDT 24
Peak memory 226052 kb
Host smart-59eee47b-46e3-4991-b829-4241954c8209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618118749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1618118749
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1877570048
Short name T399
Test name
Test status
Simulation time 286460899 ps
CPU time 9.91 seconds
Started Jul 10 07:02:23 PM PDT 24
Finished Jul 10 07:02:33 PM PDT 24
Peak memory 217728 kb
Host smart-02ae8dbd-804e-450d-a040-2a43010d76e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877570048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1877570048
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3522883859
Short name T377
Test name
Test status
Simulation time 231924732 ps
CPU time 27.03 seconds
Started Jul 10 07:02:26 PM PDT 24
Finished Jul 10 07:02:53 PM PDT 24
Peak memory 247680 kb
Host smart-64fb95ef-457c-4fb2-a624-c674c8ddbae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522883859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3522883859
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1549171935
Short name T564
Test name
Test status
Simulation time 156305868 ps
CPU time 7.41 seconds
Started Jul 10 07:02:24 PM PDT 24
Finished Jul 10 07:02:33 PM PDT 24
Peak memory 250988 kb
Host smart-920e9778-d4ec-43c7-97f3-b7e37f1d47b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549171935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1549171935
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2532585599
Short name T459
Test name
Test status
Simulation time 9347007186 ps
CPU time 211.95 seconds
Started Jul 10 07:02:30 PM PDT 24
Finished Jul 10 07:06:03 PM PDT 24
Peak memory 271384 kb
Host smart-dd22d093-e20e-4f59-acb5-589442cbe375
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532585599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2532585599
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3795341927
Short name T405
Test name
Test status
Simulation time 39641576 ps
CPU time 0.85 seconds
Started Jul 10 07:02:25 PM PDT 24
Finished Jul 10 07:02:27 PM PDT 24
Peak memory 211856 kb
Host smart-760ece71-ae58-41b5-bbe5-57afcf47d35f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795341927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3795341927
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3632067041
Short name T285
Test name
Test status
Simulation time 47064170 ps
CPU time 0.87 seconds
Started Jul 10 07:02:36 PM PDT 24
Finished Jul 10 07:02:38 PM PDT 24
Peak memory 208980 kb
Host smart-8d551edb-7c6d-4f8f-b004-a24a310a883a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632067041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3632067041
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3493545006
Short name T722
Test name
Test status
Simulation time 285871426 ps
CPU time 14.89 seconds
Started Jul 10 07:02:33 PM PDT 24
Finished Jul 10 07:02:49 PM PDT 24
Peak memory 226016 kb
Host smart-d467ead5-6dba-4a6b-bbae-4ac4fc34a6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493545006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3493545006
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2287267531
Short name T629
Test name
Test status
Simulation time 721796830 ps
CPU time 4.98 seconds
Started Jul 10 07:02:34 PM PDT 24
Finished Jul 10 07:02:40 PM PDT 24
Peak memory 217080 kb
Host smart-494a95cb-c60c-4cb2-addd-42f0fe76d8b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287267531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2287267531
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3021857648
Short name T488
Test name
Test status
Simulation time 259479787 ps
CPU time 3.67 seconds
Started Jul 10 07:02:35 PM PDT 24
Finished Jul 10 07:02:39 PM PDT 24
Peak memory 218216 kb
Host smart-d5177e1e-a7f0-49b3-990e-0734928170ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021857648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3021857648
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.4182767197
Short name T545
Test name
Test status
Simulation time 748963230 ps
CPU time 15.36 seconds
Started Jul 10 07:02:31 PM PDT 24
Finished Jul 10 07:02:47 PM PDT 24
Peak memory 218884 kb
Host smart-2973bf2d-ed85-44b4-a3fc-e5322375ecd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182767197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.4182767197
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1980638388
Short name T487
Test name
Test status
Simulation time 276698535 ps
CPU time 11.28 seconds
Started Jul 10 07:02:33 PM PDT 24
Finished Jul 10 07:02:45 PM PDT 24
Peak memory 226020 kb
Host smart-97a0d1a3-0579-422a-8755-9e0f0074d319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980638388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1980638388
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2546253349
Short name T379
Test name
Test status
Simulation time 362210000 ps
CPU time 12.04 seconds
Started Jul 10 07:02:30 PM PDT 24
Finished Jul 10 07:02:43 PM PDT 24
Peak memory 218236 kb
Host smart-10cf93e9-e6e2-449d-a887-07641d9958ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546253349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2546253349
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1650959402
Short name T204
Test name
Test status
Simulation time 450460242 ps
CPU time 8.82 seconds
Started Jul 10 07:02:32 PM PDT 24
Finished Jul 10 07:02:41 PM PDT 24
Peak memory 224860 kb
Host smart-82e2b1e9-533f-427d-be86-ac46e6527f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650959402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1650959402
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2163191971
Short name T511
Test name
Test status
Simulation time 531574512 ps
CPU time 8.53 seconds
Started Jul 10 07:02:31 PM PDT 24
Finished Jul 10 07:02:41 PM PDT 24
Peak memory 217716 kb
Host smart-6d0803fb-a08e-47e5-b0fd-fb6e70371b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163191971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2163191971
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.317677002
Short name T687
Test name
Test status
Simulation time 153357987 ps
CPU time 18.72 seconds
Started Jul 10 07:02:35 PM PDT 24
Finished Jul 10 07:02:54 PM PDT 24
Peak memory 250964 kb
Host smart-420f5670-a719-4b08-884b-c60438d17df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317677002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.317677002
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.768156717
Short name T247
Test name
Test status
Simulation time 879854171 ps
CPU time 7.7 seconds
Started Jul 10 07:02:33 PM PDT 24
Finished Jul 10 07:02:41 PM PDT 24
Peak memory 250976 kb
Host smart-67a91734-8f91-4c61-8723-0beac3fc5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768156717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.768156717
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3275027886
Short name T175
Test name
Test status
Simulation time 16791050514 ps
CPU time 99.6 seconds
Started Jul 10 07:02:33 PM PDT 24
Finished Jul 10 07:04:13 PM PDT 24
Peak memory 276444 kb
Host smart-e78e9ed4-c370-4963-8088-338f20fad0db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275027886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3275027886
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1096023836
Short name T599
Test name
Test status
Simulation time 36726778 ps
CPU time 0.73 seconds
Started Jul 10 07:02:31 PM PDT 24
Finished Jul 10 07:02:33 PM PDT 24
Peak memory 207116 kb
Host smart-e61da543-9f59-4941-9218-e29e221bae9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096023836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1096023836
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.962228831
Short name T475
Test name
Test status
Simulation time 74831900 ps
CPU time 1.12 seconds
Started Jul 10 07:02:41 PM PDT 24
Finished Jul 10 07:02:43 PM PDT 24
Peak memory 209080 kb
Host smart-fc701703-e0ec-449c-8994-bf45082d54d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962228831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.962228831
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1519468665
Short name T815
Test name
Test status
Simulation time 332743440 ps
CPU time 10.36 seconds
Started Jul 10 07:02:38 PM PDT 24
Finished Jul 10 07:02:50 PM PDT 24
Peak memory 226056 kb
Host smart-1863150d-efdf-4c9c-b50f-443f2fa69088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519468665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1519468665
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1736592138
Short name T427
Test name
Test status
Simulation time 3021065205 ps
CPU time 18.09 seconds
Started Jul 10 07:02:38 PM PDT 24
Finished Jul 10 07:02:57 PM PDT 24
Peak memory 217780 kb
Host smart-f0d818f0-6bf4-4758-a18f-c30c1378964c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736592138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1736592138
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.170769253
Short name T836
Test name
Test status
Simulation time 89828655 ps
CPU time 4.43 seconds
Started Jul 10 07:02:38 PM PDT 24
Finished Jul 10 07:02:44 PM PDT 24
Peak memory 218192 kb
Host smart-f23ae126-1a89-45cb-ab18-cc4b9b167925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170769253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.170769253
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.448497864
Short name T628
Test name
Test status
Simulation time 1255235973 ps
CPU time 11.31 seconds
Started Jul 10 07:02:41 PM PDT 24
Finished Jul 10 07:02:53 PM PDT 24
Peak memory 225940 kb
Host smart-3dd8f79f-2035-431d-80bb-6d6a853075e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448497864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.448497864
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.101975445
Short name T740
Test name
Test status
Simulation time 351053057 ps
CPU time 9.94 seconds
Started Jul 10 07:02:39 PM PDT 24
Finished Jul 10 07:02:50 PM PDT 24
Peak memory 226104 kb
Host smart-c46c9112-d013-47aa-8274-93accaefd1c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101975445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.101975445
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.579337061
Short name T810
Test name
Test status
Simulation time 613005483 ps
CPU time 11.81 seconds
Started Jul 10 07:02:40 PM PDT 24
Finished Jul 10 07:02:53 PM PDT 24
Peak memory 218352 kb
Host smart-55d78fae-98b4-4e63-b629-c71ddced1815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579337061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.579337061
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1327152276
Short name T588
Test name
Test status
Simulation time 44692614 ps
CPU time 2.06 seconds
Started Jul 10 07:02:34 PM PDT 24
Finished Jul 10 07:02:36 PM PDT 24
Peak memory 214396 kb
Host smart-1b26929e-3e4b-4c86-94b0-d29a177a843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327152276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1327152276
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.11956687
Short name T27
Test name
Test status
Simulation time 804817022 ps
CPU time 26.96 seconds
Started Jul 10 07:02:31 PM PDT 24
Finished Jul 10 07:02:59 PM PDT 24
Peak memory 250980 kb
Host smart-75504fc3-7829-4b1d-8564-963e9211445b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11956687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.11956687
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.675715369
Short name T306
Test name
Test status
Simulation time 234935563 ps
CPU time 7.01 seconds
Started Jul 10 07:02:30 PM PDT 24
Finished Jul 10 07:02:38 PM PDT 24
Peak memory 245036 kb
Host smart-48b07a21-94b5-4ce0-a2fc-8a3ad5534127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675715369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.675715369
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2702587871
Short name T166
Test name
Test status
Simulation time 25349977186 ps
CPU time 104.02 seconds
Started Jul 10 07:02:41 PM PDT 24
Finished Jul 10 07:04:26 PM PDT 24
Peak memory 251032 kb
Host smart-a5eda6e9-c038-4d4a-a128-a554e1d94277
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702587871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2702587871
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.1430648473
Short name T531
Test name
Test status
Simulation time 12796672146 ps
CPU time 251.61 seconds
Started Jul 10 07:02:38 PM PDT 24
Finished Jul 10 07:06:50 PM PDT 24
Peak memory 279032 kb
Host smart-db701ad3-0cf7-465b-a30a-b4f1eef9fafc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1430648473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.1430648473
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.743076523
Short name T763
Test name
Test status
Simulation time 13809574 ps
CPU time 0.91 seconds
Started Jul 10 07:02:31 PM PDT 24
Finished Jul 10 07:02:33 PM PDT 24
Peak memory 211872 kb
Host smart-70f069b2-6ecb-496f-8a5d-069e83be64c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743076523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.743076523
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3276149028
Short name T331
Test name
Test status
Simulation time 14084397 ps
CPU time 1.07 seconds
Started Jul 10 06:57:12 PM PDT 24
Finished Jul 10 06:57:14 PM PDT 24
Peak memory 208984 kb
Host smart-59224d1c-0e83-4ffc-b479-64e8b2156220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276149028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3276149028
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1049679126
Short name T613
Test name
Test status
Simulation time 41752413 ps
CPU time 0.94 seconds
Started Jul 10 06:57:02 PM PDT 24
Finished Jul 10 06:57:04 PM PDT 24
Peak memory 208852 kb
Host smart-a7750e83-24fd-47c6-a6a4-730f0de117e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049679126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1049679126
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3193419919
Short name T224
Test name
Test status
Simulation time 1032820992 ps
CPU time 14.49 seconds
Started Jul 10 06:57:03 PM PDT 24
Finished Jul 10 06:57:18 PM PDT 24
Peak memory 225968 kb
Host smart-4d047d04-d58c-43fc-9103-77f010b7738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193419919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3193419919
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2143541263
Short name T108
Test name
Test status
Simulation time 981333001 ps
CPU time 7.63 seconds
Started Jul 10 06:57:03 PM PDT 24
Finished Jul 10 06:57:12 PM PDT 24
Peak memory 217180 kb
Host smart-75366c02-728d-44fd-a04a-173e57d18717
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143541263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2143541263
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1402340021
Short name T600
Test name
Test status
Simulation time 3477815566 ps
CPU time 93.43 seconds
Started Jul 10 06:57:02 PM PDT 24
Finished Jul 10 06:58:37 PM PDT 24
Peak memory 218868 kb
Host smart-560cb4f4-cfa0-4689-b44b-dab3d0e24bcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402340021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1402340021
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.824323954
Short name T666
Test name
Test status
Simulation time 3825056356 ps
CPU time 10.12 seconds
Started Jul 10 06:57:03 PM PDT 24
Finished Jul 10 06:57:14 PM PDT 24
Peak memory 217828 kb
Host smart-611c2ddc-5625-41ee-96d0-d9089aef50a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824323954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.824323954
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2555574148
Short name T668
Test name
Test status
Simulation time 193726609 ps
CPU time 2.16 seconds
Started Jul 10 06:57:01 PM PDT 24
Finished Jul 10 06:57:04 PM PDT 24
Peak memory 218236 kb
Host smart-cbbe678d-3440-41f5-8f2e-b63100e73f1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555574148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2555574148
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.4148059722
Short name T684
Test name
Test status
Simulation time 912166505 ps
CPU time 14.75 seconds
Started Jul 10 06:57:09 PM PDT 24
Finished Jul 10 06:57:25 PM PDT 24
Peak memory 217708 kb
Host smart-61363ba3-f020-42dd-8b47-c160917c0ab6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148059722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.4148059722
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2498066276
Short name T305
Test name
Test status
Simulation time 80262873 ps
CPU time 2.68 seconds
Started Jul 10 06:57:03 PM PDT 24
Finished Jul 10 06:57:07 PM PDT 24
Peak memory 217700 kb
Host smart-2f67a591-e85b-4615-b581-ccbd75afe785
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498066276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2498066276
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1327208314
Short name T849
Test name
Test status
Simulation time 28473385712 ps
CPU time 107.71 seconds
Started Jul 10 06:57:02 PM PDT 24
Finished Jul 10 06:58:51 PM PDT 24
Peak memory 267432 kb
Host smart-8ed647b3-5807-4d7e-8cf1-46620d45e1b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327208314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1327208314
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3047650039
Short name T324
Test name
Test status
Simulation time 684690986 ps
CPU time 10.67 seconds
Started Jul 10 06:57:02 PM PDT 24
Finished Jul 10 06:57:14 PM PDT 24
Peak memory 246428 kb
Host smart-92f47e98-fd75-4257-9af2-2576b5abf7ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047650039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3047650039
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.904299054
Short name T717
Test name
Test status
Simulation time 291947778 ps
CPU time 3.74 seconds
Started Jul 10 06:57:03 PM PDT 24
Finished Jul 10 06:57:08 PM PDT 24
Peak memory 222500 kb
Host smart-5336e928-3b22-4c27-a409-456543d2aca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904299054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.904299054
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.729449294
Short name T674
Test name
Test status
Simulation time 270848599 ps
CPU time 7.46 seconds
Started Jul 10 06:57:03 PM PDT 24
Finished Jul 10 06:57:12 PM PDT 24
Peak memory 217736 kb
Host smart-d1d0d5ca-065c-4cc7-bdae-321409b817af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729449294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.729449294
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.632361585
Short name T449
Test name
Test status
Simulation time 1042669063 ps
CPU time 11.83 seconds
Started Jul 10 06:57:09 PM PDT 24
Finished Jul 10 06:57:22 PM PDT 24
Peak memory 226024 kb
Host smart-7b73e1cc-ecbd-49f1-af0a-638c37c2609c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632361585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.632361585
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.90852097
Short name T316
Test name
Test status
Simulation time 1225167537 ps
CPU time 12.95 seconds
Started Jul 10 06:57:11 PM PDT 24
Finished Jul 10 06:57:25 PM PDT 24
Peak memory 225936 kb
Host smart-c811778f-0174-4c3b-8418-344582998a89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90852097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dige
st.90852097
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.947861104
Short name T269
Test name
Test status
Simulation time 2960885421 ps
CPU time 13.49 seconds
Started Jul 10 06:57:09 PM PDT 24
Finished Jul 10 06:57:23 PM PDT 24
Peak memory 218952 kb
Host smart-12e03eb6-dc5f-4978-9037-b245eab03a00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947861104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.947861104
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1905635267
Short name T664
Test name
Test status
Simulation time 168892581 ps
CPU time 8.48 seconds
Started Jul 10 06:57:01 PM PDT 24
Finished Jul 10 06:57:10 PM PDT 24
Peak memory 218244 kb
Host smart-3e2ac2d9-8b24-45f7-bc65-b84e73dcd691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905635267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1905635267
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3448396173
Short name T168
Test name
Test status
Simulation time 29926590 ps
CPU time 2.43 seconds
Started Jul 10 06:56:56 PM PDT 24
Finished Jul 10 06:56:59 PM PDT 24
Peak memory 214404 kb
Host smart-d25376fc-73ac-4a25-8e28-d25061bd0c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448396173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3448396173
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2670964450
Short name T252
Test name
Test status
Simulation time 232895481 ps
CPU time 25.86 seconds
Started Jul 10 06:56:54 PM PDT 24
Finished Jul 10 06:57:21 PM PDT 24
Peak memory 251032 kb
Host smart-3beace7d-c95d-4525-97c6-ff8fede70986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670964450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2670964450
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2264988592
Short name T744
Test name
Test status
Simulation time 163060306 ps
CPU time 6.42 seconds
Started Jul 10 06:56:55 PM PDT 24
Finished Jul 10 06:57:02 PM PDT 24
Peak memory 246140 kb
Host smart-c83d4ac4-2b64-4029-8dd7-84198956e1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264988592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2264988592
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3374287548
Short name T268
Test name
Test status
Simulation time 1143971459 ps
CPU time 47.65 seconds
Started Jul 10 06:57:12 PM PDT 24
Finished Jul 10 06:58:00 PM PDT 24
Peak memory 267372 kb
Host smart-8be1690e-10fe-4ffe-9b5b-741c9b80cb34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374287548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3374287548
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1685682343
Short name T507
Test name
Test status
Simulation time 101003206111 ps
CPU time 562.8 seconds
Started Jul 10 06:57:10 PM PDT 24
Finished Jul 10 07:06:34 PM PDT 24
Peak memory 333060 kb
Host smart-6d92eb1f-3601-4bad-9170-9d80930e7eac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1685682343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1685682343
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1640152202
Short name T828
Test name
Test status
Simulation time 15115392 ps
CPU time 1.11 seconds
Started Jul 10 06:56:53 PM PDT 24
Finished Jul 10 06:56:55 PM PDT 24
Peak memory 212044 kb
Host smart-7dd49421-dd12-40f3-8c65-e7c5d4e06169
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640152202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1640152202
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3346445369
Short name T69
Test name
Test status
Simulation time 33441019 ps
CPU time 1.02 seconds
Started Jul 10 06:57:24 PM PDT 24
Finished Jul 10 06:57:27 PM PDT 24
Peak memory 209036 kb
Host smart-60b05584-18ac-4750-839b-7ef0e84ee9a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346445369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3346445369
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3562743935
Short name T733
Test name
Test status
Simulation time 13830253 ps
CPU time 1.01 seconds
Started Jul 10 06:57:19 PM PDT 24
Finished Jul 10 06:57:21 PM PDT 24
Peak memory 209008 kb
Host smart-41e4ddb0-e68b-4686-aac2-3ea1b15b53da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562743935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3562743935
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4270534556
Short name T223
Test name
Test status
Simulation time 2241497891 ps
CPU time 11.66 seconds
Started Jul 10 06:57:11 PM PDT 24
Finished Jul 10 06:57:23 PM PDT 24
Peak memory 218288 kb
Host smart-4132ee6c-a09e-40bb-a30d-19abf250b5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270534556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4270534556
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.453992627
Short name T25
Test name
Test status
Simulation time 65020002 ps
CPU time 1.51 seconds
Started Jul 10 06:57:17 PM PDT 24
Finished Jul 10 06:57:19 PM PDT 24
Peak memory 217164 kb
Host smart-38583aa2-331d-45c2-9fef-8e59ca19126a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453992627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.453992627
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2167542115
Short name T233
Test name
Test status
Simulation time 3706238364 ps
CPU time 57.13 seconds
Started Jul 10 06:57:19 PM PDT 24
Finished Jul 10 06:58:17 PM PDT 24
Peak memory 218992 kb
Host smart-f8184aec-80be-4a32-9b13-e9eee45ec5ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167542115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2167542115
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.4088213118
Short name T64
Test name
Test status
Simulation time 1957372305 ps
CPU time 14.78 seconds
Started Jul 10 06:57:16 PM PDT 24
Finished Jul 10 06:57:31 PM PDT 24
Peak memory 217784 kb
Host smart-9497a5ee-b76b-4245-aaaa-1abc33d49d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088213118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4
088213118
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2885431929
Short name T432
Test name
Test status
Simulation time 946652564 ps
CPU time 6.97 seconds
Started Jul 10 06:57:18 PM PDT 24
Finished Jul 10 06:57:26 PM PDT 24
Peak memory 218220 kb
Host smart-56d4f53a-e15d-47dd-8e9c-cbe8340885f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885431929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2885431929
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1242739085
Short name T294
Test name
Test status
Simulation time 2785860199 ps
CPU time 17.93 seconds
Started Jul 10 06:57:19 PM PDT 24
Finished Jul 10 06:57:38 PM PDT 24
Peak memory 217836 kb
Host smart-ab18d77f-fb57-4c64-82a7-53458cf46d22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242739085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1242739085
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1242289900
Short name T605
Test name
Test status
Simulation time 499980671 ps
CPU time 2.35 seconds
Started Jul 10 06:57:21 PM PDT 24
Finished Jul 10 06:57:24 PM PDT 24
Peak memory 217700 kb
Host smart-1449139a-bf59-40ef-ab5d-5b1c9a6322ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242289900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1242289900
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2401350036
Short name T430
Test name
Test status
Simulation time 3212433152 ps
CPU time 68.07 seconds
Started Jul 10 06:57:18 PM PDT 24
Finished Jul 10 06:58:27 PM PDT 24
Peak memory 267396 kb
Host smart-4bb794af-e211-4f43-a6c9-9501c7fe83b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401350036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2401350036
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1753181951
Short name T23
Test name
Test status
Simulation time 1226286077 ps
CPU time 7.3 seconds
Started Jul 10 06:57:17 PM PDT 24
Finished Jul 10 06:57:25 PM PDT 24
Peak memory 222120 kb
Host smart-f8c110c1-38e1-4601-a302-c69c52ffd8af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753181951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1753181951
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1641985622
Short name T229
Test name
Test status
Simulation time 30534618 ps
CPU time 1.68 seconds
Started Jul 10 06:57:09 PM PDT 24
Finished Jul 10 06:57:11 PM PDT 24
Peak memory 218228 kb
Host smart-8abb8cce-8d3d-40da-84ab-5f738e0cb07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641985622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1641985622
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2497354108
Short name T176
Test name
Test status
Simulation time 793795502 ps
CPU time 13.48 seconds
Started Jul 10 06:57:17 PM PDT 24
Finished Jul 10 06:57:31 PM PDT 24
Peak memory 217752 kb
Host smart-40bc0535-9e1a-4fde-a18f-0f078600177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497354108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2497354108
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1381197561
Short name T32
Test name
Test status
Simulation time 185085187 ps
CPU time 9.25 seconds
Started Jul 10 06:57:24 PM PDT 24
Finished Jul 10 06:57:34 PM PDT 24
Peak memory 226008 kb
Host smart-a5643ad8-2be3-43c9-bf11-aba49bb05ca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381197561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1381197561
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2012224497
Short name T357
Test name
Test status
Simulation time 634889414 ps
CPU time 11.92 seconds
Started Jul 10 06:57:16 PM PDT 24
Finished Jul 10 06:57:29 PM PDT 24
Peak memory 218216 kb
Host smart-fbc909eb-862b-40d1-8096-7ca5d7fa2b6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012224497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
012224497
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3361063435
Short name T614
Test name
Test status
Simulation time 836940143 ps
CPU time 15.51 seconds
Started Jul 10 06:57:18 PM PDT 24
Finished Jul 10 06:57:34 PM PDT 24
Peak memory 226036 kb
Host smart-dacde620-7de2-40a8-9160-212f3f6e4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361063435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3361063435
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.579142183
Short name T351
Test name
Test status
Simulation time 27642366 ps
CPU time 1.81 seconds
Started Jul 10 06:57:09 PM PDT 24
Finished Jul 10 06:57:12 PM PDT 24
Peak memory 217684 kb
Host smart-5f39f9a5-6647-4281-8635-8d346d4f54c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579142183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.579142183
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3593679936
Short name T258
Test name
Test status
Simulation time 883541198 ps
CPU time 20.97 seconds
Started Jul 10 06:57:09 PM PDT 24
Finished Jul 10 06:57:31 PM PDT 24
Peak memory 250992 kb
Host smart-79b7a2b2-0c0a-4f2d-a84a-72aa1fa285a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593679936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3593679936
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2003406608
Short name T167
Test name
Test status
Simulation time 166680029 ps
CPU time 9.03 seconds
Started Jul 10 06:57:12 PM PDT 24
Finished Jul 10 06:57:21 PM PDT 24
Peak memory 251000 kb
Host smart-6410d1ab-91e3-4192-9a5e-658b75d10bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003406608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2003406608
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2300934507
Short name T827
Test name
Test status
Simulation time 3003123232 ps
CPU time 39.91 seconds
Started Jul 10 06:57:25 PM PDT 24
Finished Jul 10 06:58:06 PM PDT 24
Peak memory 226108 kb
Host smart-43cbe3f9-0299-44d7-a045-9abb7d8b09b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300934507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2300934507
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3709745991
Short name T567
Test name
Test status
Simulation time 14011282 ps
CPU time 1.06 seconds
Started Jul 10 06:57:13 PM PDT 24
Finished Jul 10 06:57:14 PM PDT 24
Peak memory 211896 kb
Host smart-b02768e1-7de7-4db5-b08e-615a368e59e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709745991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3709745991
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1505607803
Short name T368
Test name
Test status
Simulation time 168074876 ps
CPU time 1.6 seconds
Started Jul 10 06:57:41 PM PDT 24
Finished Jul 10 06:57:44 PM PDT 24
Peak memory 208996 kb
Host smart-f5d6913b-9c15-4f3f-9986-f43400659e49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505607803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1505607803
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3495883317
Short name T199
Test name
Test status
Simulation time 52640834 ps
CPU time 0.96 seconds
Started Jul 10 06:57:32 PM PDT 24
Finished Jul 10 06:57:34 PM PDT 24
Peak memory 209012 kb
Host smart-4a09472b-9440-4e63-9f0f-a8932204373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495883317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3495883317
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.741267314
Short name T734
Test name
Test status
Simulation time 1484312728 ps
CPU time 12.67 seconds
Started Jul 10 06:57:42 PM PDT 24
Finished Jul 10 06:57:55 PM PDT 24
Peak memory 218352 kb
Host smart-5b6a4a53-c586-42fc-b9f0-7032968e7028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741267314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.741267314
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2071524495
Short name T660
Test name
Test status
Simulation time 352620140 ps
CPU time 6.26 seconds
Started Jul 10 06:57:32 PM PDT 24
Finished Jul 10 06:57:39 PM PDT 24
Peak memory 217428 kb
Host smart-e4903dbe-3b33-41c5-9ff3-f395db63ddf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071524495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2071524495
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2819770034
Short name T767
Test name
Test status
Simulation time 7513606943 ps
CPU time 34.4 seconds
Started Jul 10 06:57:31 PM PDT 24
Finished Jul 10 06:58:07 PM PDT 24
Peak memory 218288 kb
Host smart-0c5bf222-c760-41b9-a139-d48374d7e6de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819770034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2819770034
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3947955737
Short name T620
Test name
Test status
Simulation time 876766475 ps
CPU time 6.64 seconds
Started Jul 10 06:57:32 PM PDT 24
Finished Jul 10 06:57:40 PM PDT 24
Peak memory 217788 kb
Host smart-8326be52-e322-4a71-ba76-8604f7d6a700
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947955737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
947955737
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3637005825
Short name T26
Test name
Test status
Simulation time 713272877 ps
CPU time 11.56 seconds
Started Jul 10 06:57:34 PM PDT 24
Finished Jul 10 06:57:47 PM PDT 24
Peak memory 223304 kb
Host smart-d528f747-84ba-4425-8d17-7aad5aeddd63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637005825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3637005825
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3420624999
Short name T636
Test name
Test status
Simulation time 2324684711 ps
CPU time 11.74 seconds
Started Jul 10 06:57:33 PM PDT 24
Finished Jul 10 06:57:46 PM PDT 24
Peak memory 217772 kb
Host smart-80d79ae3-6a13-40cf-abe1-4a1199c674ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420624999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3420624999
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.954607456
Short name T667
Test name
Test status
Simulation time 6763657486 ps
CPU time 10.54 seconds
Started Jul 10 06:57:31 PM PDT 24
Finished Jul 10 06:57:43 PM PDT 24
Peak memory 217888 kb
Host smart-4e96e785-e728-4e9a-985e-695ca0b04b4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954607456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.954607456
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.942169916
Short name T326
Test name
Test status
Simulation time 8928764300 ps
CPU time 40.31 seconds
Started Jul 10 06:57:34 PM PDT 24
Finished Jul 10 06:58:16 PM PDT 24
Peak memory 251668 kb
Host smart-0ee50b8e-a9fa-485a-9f6f-077ce45df827
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942169916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.942169916
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.654911383
Short name T638
Test name
Test status
Simulation time 365845159 ps
CPU time 11.97 seconds
Started Jul 10 06:57:34 PM PDT 24
Finished Jul 10 06:57:47 PM PDT 24
Peak memory 247668 kb
Host smart-b0c22adf-b8ec-46aa-9211-582445b5082f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654911383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.654911383
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.626183661
Short name T777
Test name
Test status
Simulation time 83249697 ps
CPU time 2.8 seconds
Started Jul 10 06:57:27 PM PDT 24
Finished Jul 10 06:57:31 PM PDT 24
Peak memory 218300 kb
Host smart-358b66bc-21d0-47e2-b5bf-8cb4465da65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626183661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.626183661
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2507450210
Short name T74
Test name
Test status
Simulation time 241007933 ps
CPU time 7.24 seconds
Started Jul 10 06:57:32 PM PDT 24
Finished Jul 10 06:57:41 PM PDT 24
Peak memory 214408 kb
Host smart-391db993-608c-4eb5-9e7c-2d0f5469f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507450210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2507450210
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3187880165
Short name T207
Test name
Test status
Simulation time 302966923 ps
CPU time 13.52 seconds
Started Jul 10 06:57:33 PM PDT 24
Finished Jul 10 06:57:48 PM PDT 24
Peak memory 226024 kb
Host smart-3f90c48e-6dea-4431-8fa2-7aacd663771b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187880165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3187880165
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.213308807
Short name T278
Test name
Test status
Simulation time 4698353550 ps
CPU time 21.02 seconds
Started Jul 10 06:57:40 PM PDT 24
Finished Jul 10 06:58:02 PM PDT 24
Peak memory 226080 kb
Host smart-017623d8-6afa-422f-9e44-b2a62a59917c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213308807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.213308807
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.224656480
Short name T263
Test name
Test status
Simulation time 323840892 ps
CPU time 8.87 seconds
Started Jul 10 06:57:41 PM PDT 24
Finished Jul 10 06:57:50 PM PDT 24
Peak memory 218236 kb
Host smart-81d4796b-ed39-4a0f-a1f6-00ad1fe6abee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224656480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.224656480
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2971634297
Short name T846
Test name
Test status
Simulation time 1573603003 ps
CPU time 13.08 seconds
Started Jul 10 06:57:33 PM PDT 24
Finished Jul 10 06:57:48 PM PDT 24
Peak memory 218408 kb
Host smart-889b34c2-f430-449a-9632-be9a06ccc564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971634297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2971634297
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.4046283714
Short name T805
Test name
Test status
Simulation time 16596879 ps
CPU time 1.17 seconds
Started Jul 10 06:57:25 PM PDT 24
Finished Jul 10 06:57:27 PM PDT 24
Peak memory 212092 kb
Host smart-947c8960-7711-44e3-8a8b-5801fcbdcb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046283714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.4046283714
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3974290973
Short name T21
Test name
Test status
Simulation time 493411318 ps
CPU time 22.57 seconds
Started Jul 10 06:57:25 PM PDT 24
Finished Jul 10 06:57:48 PM PDT 24
Peak memory 251056 kb
Host smart-977360de-66ac-42a1-a5be-9488dbf3c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974290973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3974290973
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2168138700
Short name T757
Test name
Test status
Simulation time 77601594 ps
CPU time 6.91 seconds
Started Jul 10 06:57:27 PM PDT 24
Finished Jul 10 06:57:34 PM PDT 24
Peak memory 250608 kb
Host smart-31733288-eb48-4104-9e06-39b3b1192a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168138700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2168138700
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2974961754
Short name T593
Test name
Test status
Simulation time 10962855527 ps
CPU time 330.68 seconds
Started Jul 10 06:57:42 PM PDT 24
Finished Jul 10 07:03:14 PM PDT 24
Peak memory 283808 kb
Host smart-1569980d-60fa-4b57-9395-14098d1f7372
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974961754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2974961754
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4110325561
Short name T544
Test name
Test status
Simulation time 12217086 ps
CPU time 0.76 seconds
Started Jul 10 06:57:26 PM PDT 24
Finished Jul 10 06:57:27 PM PDT 24
Peak memory 208128 kb
Host smart-b5be50c8-672c-4098-8451-d0291f2183d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110325561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.4110325561
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3193774189
Short name T274
Test name
Test status
Simulation time 137894049 ps
CPU time 1.07 seconds
Started Jul 10 06:57:56 PM PDT 24
Finished Jul 10 06:57:58 PM PDT 24
Peak memory 208924 kb
Host smart-6c66727d-772e-4902-bdeb-e12faa942ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193774189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3193774189
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3890109308
Short name T514
Test name
Test status
Simulation time 13754589 ps
CPU time 0.85 seconds
Started Jul 10 06:57:40 PM PDT 24
Finished Jul 10 06:57:42 PM PDT 24
Peak memory 208976 kb
Host smart-fbc8ec97-11f2-4c97-bca2-44f1fe17cde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890109308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3890109308
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3183965356
Short name T219
Test name
Test status
Simulation time 241195168 ps
CPU time 11.43 seconds
Started Jul 10 06:57:44 PM PDT 24
Finished Jul 10 06:57:56 PM PDT 24
Peak memory 218232 kb
Host smart-29574a7f-7ce6-47fa-b77c-bf2eac61ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183965356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3183965356
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2546777228
Short name T178
Test name
Test status
Simulation time 1533994664 ps
CPU time 3.45 seconds
Started Jul 10 06:57:50 PM PDT 24
Finished Jul 10 06:57:54 PM PDT 24
Peak memory 217152 kb
Host smart-bde906d3-f73e-454f-9664-36509b91cf0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546777228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2546777228
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1703690596
Short name T376
Test name
Test status
Simulation time 3569252486 ps
CPU time 53.25 seconds
Started Jul 10 06:57:48 PM PDT 24
Finished Jul 10 06:58:42 PM PDT 24
Peak memory 218980 kb
Host smart-c26f1227-db96-4e0f-a3ce-adbc73be63e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703690596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1703690596
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1078487195
Short name T177
Test name
Test status
Simulation time 97843693 ps
CPU time 3.3 seconds
Started Jul 10 06:57:49 PM PDT 24
Finished Jul 10 06:57:53 PM PDT 24
Peak memory 217552 kb
Host smart-5eef4d23-17da-424d-8c45-3e47bd72ce8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078487195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
078487195
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1819664786
Short name T557
Test name
Test status
Simulation time 1590160695 ps
CPU time 11.1 seconds
Started Jul 10 06:57:49 PM PDT 24
Finished Jul 10 06:58:01 PM PDT 24
Peak memory 223120 kb
Host smart-958d6e51-512e-4a24-8ce4-971d08500503
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819664786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1819664786
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1394640053
Short name T337
Test name
Test status
Simulation time 4019830629 ps
CPU time 28.72 seconds
Started Jul 10 06:57:52 PM PDT 24
Finished Jul 10 06:58:21 PM PDT 24
Peak memory 217764 kb
Host smart-f13af807-1229-4cd4-9220-9c7cef36e13d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394640053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1394640053
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.746162853
Short name T470
Test name
Test status
Simulation time 777383535 ps
CPU time 5.92 seconds
Started Jul 10 06:57:48 PM PDT 24
Finished Jul 10 06:57:55 PM PDT 24
Peak memory 217740 kb
Host smart-e4f93d31-d68f-41d0-83cb-63bdfff25e9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746162853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.746162853
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1973613894
Short name T540
Test name
Test status
Simulation time 4950514026 ps
CPU time 54.05 seconds
Started Jul 10 06:57:49 PM PDT 24
Finished Jul 10 06:58:44 PM PDT 24
Peak memory 267488 kb
Host smart-aa4f4eed-e0b0-4560-90cd-9e7c239a4679
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973613894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1973613894
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3174835555
Short name T401
Test name
Test status
Simulation time 1801903208 ps
CPU time 11.54 seconds
Started Jul 10 06:57:52 PM PDT 24
Finished Jul 10 06:58:04 PM PDT 24
Peak memory 248736 kb
Host smart-5b69e524-8089-4669-b14b-68912e6b9743
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174835555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3174835555
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3239279964
Short name T760
Test name
Test status
Simulation time 56883885 ps
CPU time 1.81 seconds
Started Jul 10 06:57:44 PM PDT 24
Finished Jul 10 06:57:46 PM PDT 24
Peak memory 222080 kb
Host smart-9dce9a2c-c1a9-4fc2-8537-46e469645187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239279964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3239279964
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4023949434
Short name T63
Test name
Test status
Simulation time 3165179577 ps
CPU time 25.6 seconds
Started Jul 10 06:57:39 PM PDT 24
Finished Jul 10 06:58:05 PM PDT 24
Peak memory 214772 kb
Host smart-023911bf-7e06-4fc8-9cc9-873ed671a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023949434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4023949434
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.624184266
Short name T354
Test name
Test status
Simulation time 255757381 ps
CPU time 13.83 seconds
Started Jul 10 06:57:48 PM PDT 24
Finished Jul 10 06:58:03 PM PDT 24
Peak memory 226064 kb
Host smart-f1598f42-1917-4362-9a71-30407218cfed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624184266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.624184266
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1710240315
Short name T413
Test name
Test status
Simulation time 1388502099 ps
CPU time 9.2 seconds
Started Jul 10 06:57:56 PM PDT 24
Finished Jul 10 06:58:06 PM PDT 24
Peak memory 226036 kb
Host smart-ec7399a7-9003-44bb-b96c-dcfc684faf98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710240315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1710240315
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.462625696
Short name T697
Test name
Test status
Simulation time 176361556 ps
CPU time 7.13 seconds
Started Jul 10 06:57:49 PM PDT 24
Finished Jul 10 06:57:57 PM PDT 24
Peak memory 218316 kb
Host smart-161b01bb-0319-4bc4-81fe-b2564be2f66d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462625696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.462625696
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.673884563
Short name T476
Test name
Test status
Simulation time 915213629 ps
CPU time 6.99 seconds
Started Jul 10 06:57:40 PM PDT 24
Finished Jul 10 06:57:48 PM PDT 24
Peak memory 218484 kb
Host smart-948a1fad-1e91-475b-8445-68976d1fce9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673884563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.673884563
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2040314025
Short name T817
Test name
Test status
Simulation time 196130825 ps
CPU time 3.48 seconds
Started Jul 10 06:57:40 PM PDT 24
Finished Jul 10 06:57:45 PM PDT 24
Peak memory 215088 kb
Host smart-38de01a7-6c7b-4201-a098-f414d3c81acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040314025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2040314025
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1802150448
Short name T164
Test name
Test status
Simulation time 216254379 ps
CPU time 19.52 seconds
Started Jul 10 06:57:42 PM PDT 24
Finished Jul 10 06:58:03 PM PDT 24
Peak memory 250980 kb
Host smart-96dcc473-6825-40f5-b5e8-e4bedfa75aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802150448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1802150448
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3564405543
Short name T485
Test name
Test status
Simulation time 57249458 ps
CPU time 8.56 seconds
Started Jul 10 06:57:43 PM PDT 24
Finished Jul 10 06:57:52 PM PDT 24
Peak memory 251012 kb
Host smart-e30fa196-7a78-422e-a42a-745b37f86b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564405543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3564405543
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1395318689
Short name T802
Test name
Test status
Simulation time 3365609684 ps
CPU time 55.05 seconds
Started Jul 10 06:57:55 PM PDT 24
Finished Jul 10 06:58:51 PM PDT 24
Peak memory 226112 kb
Host smart-5c61af19-4ee7-4d7b-9598-35bd0f711c12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395318689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1395318689
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1024622701
Short name T85
Test name
Test status
Simulation time 58493556 ps
CPU time 0.71 seconds
Started Jul 10 06:57:40 PM PDT 24
Finished Jul 10 06:57:42 PM PDT 24
Peak memory 207472 kb
Host smart-12b5394c-abd8-4907-bc89-bb8bad9182ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024622701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1024622701
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3748004610
Short name T498
Test name
Test status
Simulation time 42637185 ps
CPU time 0.97 seconds
Started Jul 10 06:58:03 PM PDT 24
Finished Jul 10 06:58:05 PM PDT 24
Peak memory 208968 kb
Host smart-bc1ebd52-e672-4c5a-b85e-0178ee6ca714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748004610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3748004610
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2125612677
Short name T270
Test name
Test status
Simulation time 10550761 ps
CPU time 0.96 seconds
Started Jul 10 06:57:58 PM PDT 24
Finished Jul 10 06:58:00 PM PDT 24
Peak memory 209260 kb
Host smart-a57c75a4-7a42-4008-aeb1-e82323c248a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125612677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2125612677
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2420839611
Short name T478
Test name
Test status
Simulation time 493278134 ps
CPU time 15.12 seconds
Started Jul 10 06:57:55 PM PDT 24
Finished Jul 10 06:58:11 PM PDT 24
Peak memory 218224 kb
Host smart-b072f591-c709-4236-b350-f36e71daadd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420839611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2420839611
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1665967974
Short name T646
Test name
Test status
Simulation time 4194639402 ps
CPU time 23.72 seconds
Started Jul 10 06:58:08 PM PDT 24
Finished Jul 10 06:58:32 PM PDT 24
Peak memory 217668 kb
Host smart-7106db17-663e-4f5d-9701-5f045fe2aa53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665967974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1665967974
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3860607135
Short name T863
Test name
Test status
Simulation time 2918849847 ps
CPU time 85.02 seconds
Started Jul 10 06:58:03 PM PDT 24
Finished Jul 10 06:59:29 PM PDT 24
Peak memory 220220 kb
Host smart-bd49c51f-2eff-45ac-8c98-d532641ec51e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860607135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3860607135
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2656178505
Short name T619
Test name
Test status
Simulation time 154916482 ps
CPU time 4.7 seconds
Started Jul 10 06:58:03 PM PDT 24
Finished Jul 10 06:58:09 PM PDT 24
Peak memory 217660 kb
Host smart-9acab673-0327-4c00-a5d7-67dcb20b3339
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656178505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
656178505
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2434239575
Short name T260
Test name
Test status
Simulation time 685383386 ps
CPU time 18.15 seconds
Started Jul 10 06:58:01 PM PDT 24
Finished Jul 10 06:58:20 PM PDT 24
Peak memory 224276 kb
Host smart-445232c4-d8a0-40b4-91d9-25c155fddfb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434239575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2434239575
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1386877502
Short name T745
Test name
Test status
Simulation time 1532325921 ps
CPU time 24.02 seconds
Started Jul 10 06:58:02 PM PDT 24
Finished Jul 10 06:58:26 PM PDT 24
Peak memory 217636 kb
Host smart-194c8ec5-8b91-42b6-987d-df58d6a5c5b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386877502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1386877502
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.514701345
Short name T473
Test name
Test status
Simulation time 522125565 ps
CPU time 7.85 seconds
Started Jul 10 06:57:55 PM PDT 24
Finished Jul 10 06:58:03 PM PDT 24
Peak memory 217700 kb
Host smart-9b408d3d-cca5-4d62-bb7f-e9ef098be656
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514701345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.514701345
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.560993105
Short name T508
Test name
Test status
Simulation time 10887933640 ps
CPU time 78.94 seconds
Started Jul 10 06:57:55 PM PDT 24
Finished Jul 10 06:59:15 PM PDT 24
Peak memory 277636 kb
Host smart-0c9dce8b-f850-4083-bc90-b2107bf23436
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560993105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.560993105
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3343205338
Short name T823
Test name
Test status
Simulation time 1037324680 ps
CPU time 21.57 seconds
Started Jul 10 06:58:02 PM PDT 24
Finished Jul 10 06:58:24 PM PDT 24
Peak memory 250968 kb
Host smart-f3430829-5391-4995-b27b-50a140cb507b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343205338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3343205338
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.82037339
Short name T254
Test name
Test status
Simulation time 39933424 ps
CPU time 1.52 seconds
Started Jul 10 06:57:58 PM PDT 24
Finished Jul 10 06:58:00 PM PDT 24
Peak memory 218228 kb
Host smart-01522283-c77a-40c0-8c51-8a7a64b1ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82037339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.82037339
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2318094420
Short name T434
Test name
Test status
Simulation time 202035575 ps
CPU time 13.79 seconds
Started Jul 10 06:57:56 PM PDT 24
Finished Jul 10 06:58:10 PM PDT 24
Peak memory 217708 kb
Host smart-5247593e-fc57-4280-adfe-29ae4d4c12cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318094420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2318094420
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1160476541
Short name T338
Test name
Test status
Simulation time 602147101 ps
CPU time 10.23 seconds
Started Jul 10 06:58:08 PM PDT 24
Finished Jul 10 06:58:18 PM PDT 24
Peak memory 225936 kb
Host smart-ee14b7ea-f53e-4fae-bce6-bd1a922a54a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160476541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1160476541
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3462193924
Short name T417
Test name
Test status
Simulation time 477601010 ps
CPU time 13.8 seconds
Started Jul 10 06:58:08 PM PDT 24
Finished Jul 10 06:58:22 PM PDT 24
Peak memory 225936 kb
Host smart-eef41304-02a9-40bb-bdab-60741f9a49ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462193924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3462193924
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2898449430
Short name T670
Test name
Test status
Simulation time 358236793 ps
CPU time 10.54 seconds
Started Jul 10 06:58:04 PM PDT 24
Finished Jul 10 06:58:16 PM PDT 24
Peak memory 226048 kb
Host smart-f7f182f5-9927-4c8b-b3fc-126699c416b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898449430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
898449430
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1023459796
Short name T792
Test name
Test status
Simulation time 329892335 ps
CPU time 8.7 seconds
Started Jul 10 06:57:56 PM PDT 24
Finished Jul 10 06:58:06 PM PDT 24
Peak memory 225316 kb
Host smart-501eef56-dcc1-4edf-aa63-c0c8ef948422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023459796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1023459796
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.79220751
Short name T275
Test name
Test status
Simulation time 104662038 ps
CPU time 2.04 seconds
Started Jul 10 06:57:55 PM PDT 24
Finished Jul 10 06:57:58 PM PDT 24
Peak memory 214204 kb
Host smart-29f40030-e171-46bd-a33d-008932e6f518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79220751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.79220751
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1885420832
Short name T474
Test name
Test status
Simulation time 259812626 ps
CPU time 31.16 seconds
Started Jul 10 06:57:55 PM PDT 24
Finished Jul 10 06:58:26 PM PDT 24
Peak memory 250984 kb
Host smart-57e83004-8c4f-4783-929d-cb68647ce3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885420832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1885420832
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3777739561
Short name T472
Test name
Test status
Simulation time 380136507 ps
CPU time 7.31 seconds
Started Jul 10 06:57:54 PM PDT 24
Finished Jul 10 06:58:02 PM PDT 24
Peak memory 250944 kb
Host smart-769a80a9-0310-4d24-8fe6-8cd4c939a20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777739561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3777739561
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4023153674
Short name T416
Test name
Test status
Simulation time 1801713569 ps
CPU time 16.32 seconds
Started Jul 10 06:58:03 PM PDT 24
Finished Jul 10 06:58:21 PM PDT 24
Peak memory 226004 kb
Host smart-e2383514-908c-4cba-8234-b50ebb89cca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023153674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4023153674
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3572216169
Short name T93
Test name
Test status
Simulation time 139689077099 ps
CPU time 552.39 seconds
Started Jul 10 06:58:02 PM PDT 24
Finished Jul 10 07:07:15 PM PDT 24
Peak memory 259344 kb
Host smart-a2d8f0e8-9535-488e-9442-8536e9a1826d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3572216169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3572216169
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3505026052
Short name T632
Test name
Test status
Simulation time 21047574 ps
CPU time 0.91 seconds
Started Jul 10 06:57:58 PM PDT 24
Finished Jul 10 06:57:59 PM PDT 24
Peak memory 211880 kb
Host smart-56f37ad4-fee7-4917-9248-24c0acfffefd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505026052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3505026052
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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