Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51125 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1837 |
1 |
|
|
T11 |
6 |
|
T12 |
9 |
|
T14 |
7 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52360 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
602 |
1 |
|
|
T15 |
9 |
|
T18 |
14 |
|
T19 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51030 |
1 |
|
|
T2 |
10 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1932 |
1 |
|
|
T2 |
1 |
|
T14 |
21 |
|
T32 |
13 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51094 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1868 |
1 |
|
|
T14 |
22 |
|
T32 |
6 |
|
T33 |
6 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51060 |
1 |
|
|
T2 |
10 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1902 |
1 |
|
|
T2 |
1 |
|
T14 |
15 |
|
T32 |
5 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48554 |
1 |
|
|
T2 |
5 |
|
T4 |
9 |
|
T5 |
20 |
no_err_inj |
4408 |
1 |
|
|
T2 |
6 |
|
T7 |
15 |
|
T14 |
21 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51085 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1877 |
1 |
|
|
T11 |
10 |
|
T12 |
14 |
|
T14 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52391 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
571 |
1 |
|
|
T15 |
13 |
|
T18 |
10 |
|
T19 |
18 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35888 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[1] |
17074 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
148 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51044 |
1 |
|
|
T2 |
10 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1918 |
1 |
|
|
T2 |
1 |
|
T14 |
16 |
|
T32 |
6 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51100 |
1 |
|
|
T2 |
10 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1862 |
1 |
|
|
T2 |
1 |
|
T14 |
33 |
|
T32 |
4 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51132 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1830 |
1 |
|
|
T14 |
25 |
|
T32 |
9 |
|
T33 |
10 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51140 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1822 |
1 |
|
|
T11 |
9 |
|
T12 |
10 |
|
T14 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50581 |
1 |
|
|
T2 |
11 |
|
T11 |
63 |
|
T12 |
63 |
auto[1] |
2381 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T20 |
14 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52431 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
531 |
1 |
|
|
T15 |
10 |
|
T18 |
8 |
|
T19 |
17 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52373 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
589 |
1 |
|
|
T15 |
17 |
|
T18 |
13 |
|
T19 |
31 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52416 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
546 |
1 |
|
|
T15 |
12 |
|
T18 |
7 |
|
T19 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50805 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[1] |
2157 |
1 |
|
|
T2 |
11 |
|
T14 |
12 |
|
T80 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49115 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
3847 |
1 |
|
|
T42 |
98 |
|
T43 |
51 |
|
T44 |
93 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51066 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1896 |
1 |
|
|
T14 |
20 |
|
T32 |
4 |
|
T33 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51028 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1934 |
1 |
|
|
T14 |
32 |
|
T32 |
3 |
|
T33 |
10 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51073 |
1 |
|
|
T2 |
10 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1889 |
1 |
|
|
T2 |
1 |
|
T14 |
29 |
|
T32 |
4 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51085 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1877 |
1 |
|
|
T11 |
8 |
|
T12 |
5 |
|
T14 |
13 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47349 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
5613 |
1 |
|
|
T11 |
6 |
|
T12 |
7 |
|
T14 |
7 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49202 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
3760 |
1 |
|
|
T13 |
80 |
|
T54 |
52 |
|
T55 |
68 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52962 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51109 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1853 |
1 |
|
|
T11 |
7 |
|
T12 |
7 |
|
T14 |
11 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51027 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1935 |
1 |
|
|
T11 |
10 |
|
T12 |
5 |
|
T14 |
5 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51080 |
1 |
|
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
20 |
auto[1] |
1882 |
1 |
|
|
T11 |
7 |
|
T12 |
6 |
|
T14 |
10 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47461 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
no_err_inj |
3344 |
1 |
|
|
T7 |
15 |
|
T14 |
17 |
|
T35 |
18 |
auto[1] |
err_inj |
1093 |
1 |
|
|
T2 |
5 |
|
T14 |
8 |
|
T80 |
7 |
auto[1] |
no_err_inj |
1064 |
1 |
|
|
T2 |
6 |
|
T14 |
4 |
|
T80 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48979 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1826 |
1 |
|
|
T14 |
32 |
|
T32 |
3 |
|
T33 |
10 |
auto[1] |
auto[0] |
2049 |
1 |
|
|
T2 |
11 |
|
T14 |
12 |
|
T80 |
15 |
auto[1] |
auto[1] |
108 |
1 |
|
|
T225 |
1 |
|
T87 |
1 |
|
T57 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49065 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1740 |
1 |
|
|
T14 |
31 |
|
T32 |
4 |
|
T33 |
13 |
auto[1] |
auto[0] |
2035 |
1 |
|
|
T2 |
10 |
|
T14 |
10 |
|
T80 |
14 |
auto[1] |
auto[1] |
122 |
1 |
|
|
T2 |
1 |
|
T14 |
2 |
|
T80 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49034 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1771 |
1 |
|
|
T14 |
27 |
|
T32 |
4 |
|
T33 |
10 |
auto[1] |
auto[0] |
2039 |
1 |
|
|
T2 |
10 |
|
T14 |
10 |
|
T80 |
14 |
auto[1] |
auto[1] |
118 |
1 |
|
|
T2 |
1 |
|
T14 |
2 |
|
T80 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49050 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1755 |
1 |
|
|
T14 |
21 |
|
T32 |
6 |
|
T33 |
6 |
auto[1] |
auto[0] |
2044 |
1 |
|
|
T2 |
11 |
|
T14 |
11 |
|
T80 |
13 |
auto[1] |
auto[1] |
113 |
1 |
|
|
T14 |
1 |
|
T80 |
2 |
|
T226 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49029 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1776 |
1 |
|
|
T14 |
15 |
|
T32 |
5 |
|
T33 |
7 |
auto[1] |
auto[0] |
2031 |
1 |
|
|
T2 |
10 |
|
T14 |
12 |
|
T80 |
15 |
auto[1] |
auto[1] |
126 |
1 |
|
|
T2 |
1 |
|
T225 |
1 |
|
T57 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49010 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1795 |
1 |
|
|
T14 |
20 |
|
T32 |
13 |
|
T33 |
11 |
auto[1] |
auto[0] |
2020 |
1 |
|
|
T2 |
10 |
|
T14 |
11 |
|
T80 |
14 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T80 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34901 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
57 |
auto[0] |
auto[1] |
987 |
1 |
|
|
T11 |
6 |
|
T12 |
9 |
|
T14 |
7 |
auto[1] |
auto[0] |
16224 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
148 |
auto[1] |
auto[1] |
850 |
1 |
|
|
T21 |
16 |
|
T56 |
9 |
|
T81 |
4 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34850 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
53 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T11 |
10 |
|
T12 |
14 |
|
T14 |
9 |
auto[1] |
auto[0] |
16235 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
148 |
auto[1] |
auto[1] |
839 |
1 |
|
|
T21 |
14 |
|
T56 |
10 |
|
T81 |
4 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34513 |
1 |
|
|
T11 |
63 |
|
T12 |
63 |
|
T13 |
80 |
auto[0] |
auto[1] |
1375 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T20 |
14 |
auto[1] |
auto[0] |
16068 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
148 |
auto[1] |
auto[1] |
1006 |
1 |
|
|
T227 |
8 |
|
T228 |
10 |
|
T229 |
10 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34927 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
54 |
auto[0] |
auto[1] |
961 |
1 |
|
|
T11 |
9 |
|
T12 |
10 |
|
T14 |
10 |
auto[1] |
auto[0] |
16213 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
148 |
auto[1] |
auto[1] |
861 |
1 |
|
|
T21 |
10 |
|
T56 |
7 |
|
T81 |
8 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31110 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
57 |
auto[0] |
auto[1] |
4778 |
1 |
|
|
T11 |
6 |
|
T12 |
7 |
|
T14 |
7 |
auto[1] |
auto[0] |
16239 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
148 |
auto[1] |
auto[1] |
835 |
1 |
|
|
T21 |
20 |
|
T56 |
9 |
|
T81 |
10 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34760 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1128 |
1 |
|
|
T14 |
12 |
|
T32 |
3 |
|
T33 |
10 |
auto[1] |
auto[0] |
16268 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
128 |
auto[1] |
auto[1] |
806 |
1 |
|
|
T14 |
20 |
|
T22 |
12 |
|
T230 |
9 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34807 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1081 |
1 |
|
|
T14 |
5 |
|
T32 |
4 |
|
T33 |
7 |
auto[1] |
auto[0] |
16259 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
133 |
auto[1] |
auto[1] |
815 |
1 |
|
|
T14 |
15 |
|
T22 |
13 |
|
T230 |
8 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34815 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1073 |
1 |
|
|
T14 |
9 |
|
T32 |
4 |
|
T33 |
13 |
auto[1] |
auto[0] |
16285 |
1 |
|
|
T2 |
10 |
|
T7 |
15 |
|
T14 |
124 |
auto[1] |
auto[1] |
789 |
1 |
|
|
T2 |
1 |
|
T14 |
24 |
|
T22 |
4 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34770 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1118 |
1 |
|
|
T14 |
6 |
|
T32 |
6 |
|
T33 |
10 |
auto[1] |
auto[0] |
16274 |
1 |
|
|
T2 |
10 |
|
T7 |
15 |
|
T14 |
138 |
auto[1] |
auto[1] |
800 |
1 |
|
|
T2 |
1 |
|
T14 |
10 |
|
T22 |
8 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34797 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1091 |
1 |
|
|
T14 |
6 |
|
T32 |
6 |
|
T33 |
6 |
auto[1] |
auto[0] |
16297 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
132 |
auto[1] |
auto[1] |
777 |
1 |
|
|
T14 |
16 |
|
T22 |
9 |
|
T230 |
6 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34754 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1134 |
1 |
|
|
T14 |
7 |
|
T32 |
13 |
|
T33 |
11 |
auto[1] |
auto[0] |
16276 |
1 |
|
|
T2 |
10 |
|
T7 |
15 |
|
T14 |
134 |
auto[1] |
auto[1] |
798 |
1 |
|
|
T2 |
1 |
|
T14 |
14 |
|
T22 |
10 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34822 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
56 |
auto[0] |
auto[1] |
1066 |
1 |
|
|
T11 |
7 |
|
T12 |
6 |
|
T14 |
10 |
auto[1] |
auto[0] |
16258 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
148 |
auto[1] |
auto[1] |
816 |
1 |
|
|
T21 |
11 |
|
T56 |
12 |
|
T81 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34848 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
53 |
auto[0] |
auto[1] |
1040 |
1 |
|
|
T11 |
10 |
|
T12 |
5 |
|
T14 |
5 |
auto[1] |
auto[0] |
16179 |
1 |
|
|
T2 |
11 |
|
T7 |
15 |
|
T14 |
148 |
auto[1] |
auto[1] |
895 |
1 |
|
|
T21 |
7 |
|
T56 |
11 |
|
T81 |
8 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34548 |
1 |
|
|
T4 |
9 |
|
T5 |
20 |
|
T11 |
63 |
auto[0] |
auto[1] |
1340 |
1 |
|
|
T80 |
15 |
|
T225 |
12 |
|
T226 |
12 |
auto[1] |
auto[0] |
16257 |
1 |
|
|
T7 |
15 |
|
T14 |
136 |
|
T21 |
99 |
auto[1] |
auto[1] |
817 |
1 |
|
|
T2 |
11 |
|
T14 |
12 |
|
T57 |
22 |