Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102151307

1

T1

1213

T2

59965

T3

2823

auto[1]

1400621

1

T2

196

T4

693

T5

1089

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102133078

1

T1

1213

T2

59965

T3

2823

auto[1]

1418850

1

T2

196

T4

198

T5

891

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7193242	1			T1	102		T2	1204		T3	196
auto[IdleSt]	23632436	1			T1	16		T2	17459		T3	2627
auto[ClkMuxSt]	34921	1			T1	1		T2	6		T10	1
auto[CntIncrSt]	34680	1			T1	1		T2	6		T10	1
auto[CntProgSt]	1928276	1			T1	23		T2	26		T10	2
auto[TransCheckSt]	26727	1			T1	1		T2	6		T10	1
auto[TokenHashSt]	37660341	1			T1	11		T2	273		T10	314
auto[FlashRmaSt]	34023	1			T2	6		T11	19		T12	49
auto[TokenCheck0St]	11839	1			T2	6		T11	19		T12	26
auto[TokenCheck1St]	8680	1			T2	6		T11	11		T12	13
auto[TransProgSt]	542421	1			T2	27		T11	1833		T12	22
auto[PostTransSt]	13628948	1			T1	1058		T2	21153		T10	1264
auto[ScrapSt]	272034	1			T7	563		T34	1462		T35	44
auto[EscalateSt]	6805776	1			T2	10428		T4	1195		T5	2789
auto[InvalidSt]	11735640	1			T2	9554		T15	3553		T18	1865

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1944	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11735640	1			T2	9554		T15	3553		T18	1865
EscalateSt	6805776	1			T2	10428		T4	1195		T5	2789
ScrapSt	272034	1			T7	563		T34	1462		T35	44
PostTransSt	13628948	1			T1	1058		T2	21153		T10	1264
TransProgSt	542421	1			T2	27		T11	1833		T12	22
TokenCheck1St	8680	1			T2	6		T11	11		T12	13
TokenCheck0St	11839	1			T2	6		T11	19		T12	26
FlashRmaSt	34023	1			T2	6		T11	19		T12	49
TokenHashSt	37660341	1			T1	11		T2	273		T10	314
TransCheckSt	26727	1			T1	1		T2	6		T10	1
CntProgSt	1928276	1			T1	23		T2	26		T10	2
CntIncrSt	34680	1			T1	1		T2	6		T10	1
ClkMuxSt	34921	1			T1	1		T2	6		T10	1
IdleSt	23632436	1			T1	16		T2	17459		T3	2627
ResetSt	7193242	1			T1	102		T2	1204		T3	196
arcs[ResetSt=>IdleSt]	53243	1			T1	1		T2	12		T3	1
arcs[IdleSt=>ScrapSt]	289	1			T7	2		T34	1		T35	1
arcs[IdleSt=>ClkMuxSt]	34742	1			T1	1		T2	6		T10	1
arcs[ClkMuxSt=>CntIncrSt]	34680	1			T1	1		T2	6		T10	1
arcs[CntIncrSt=>PostTransSt]	1937	1			T11	10		T12	5		T14	5
arcs[CntIncrSt=>CntProgSt]	32674	1			T1	1		T2	6		T10	1
arcs[CntProgSt=>PostTransSt]	4785	1			T4	9		T5	20		T11	6
arcs[CntProgSt=>TransCheckSt]	26727	1			T1	1		T2	6		T10	1
arcs[TransCheckSt=>PostTransSt]	3787	1			T11	7		T12	6		T13	34
arcs[TransCheckSt=>TokenHashSt]	22819	1			T1	1		T2	6		T10	1
arcs[TokenHashSt=>PostTransSt]	10208	1			T1	1		T10	1		T11	21
arcs[TokenHashSt=>FlashRmaSt]	11938	1			T2	6		T11	19		T12	26
arcs[FlashRmaSt=>TokenCheck0St]	11839	1			T2	6		T11	19		T12	26
arcs[TokenCheck0St=>PostTransSt]	3132	1			T11	8		T12	13		T13	23
arcs[TokenCheck0St=>TokenCheck1St]	8680	1			T2	6		T11	11		T12	13
arcs[TokenCheck1St=>PostTransSt]	638	1			T11	2		T12	1		T13	11
arcs[TransProgSt=>PostTransSt]	7141	1			T2	6		T11	9		T12	12
arcs[IdleSt=>EscalateSt]	210	1			T45	11		T46	5		T47	4
arcs[ClkMuxSt=>EscalateSt]	62	1			T42	2		T43	2		T44	1
arcs[CntIncrSt=>EscalateSt]	69	1			T42	2		T43	1		T44	3
arcs[CntProgSt=>EscalateSt]	1162	1			T42	45		T43	21		T44	39
arcs[TransCheckSt=>EscalateSt]	121	1			T45	1		T47	12		T51	6
arcs[TokenHashSt=>EscalateSt]	673	1			T36	1		T42	7		T43	7
arcs[FlashRmaSt=>EscalateSt]	99	1			T42	2		T43	1		T44	5
arcs[TokenCheck0St=>EscalateSt]	27	1			T42	2		T44	1		T45	2
arcs[TokenCheck1St=>EscalateSt]	152	1			T42	2		T43	2		T44	2
arcs[TransProgSt=>EscalateSt]	749	1			T42	23		T43	10		T44	21
arcs[PostTransSt=>EscalateSt]	5036	1			T4	9		T5	20		T11	6
arcs[InvalidSt=>EscalateSt]	13913	1			T2	4		T15	17		T18	13

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7193077	1			T1	102		T2	1204		T3	196
auto[0]	auto[IdleSt]	23632281	1			T1	16		T2	17459		T3	2627
auto[0]	auto[ClkMuxSt]	34882	1			T1	1		T2	6		T10	1
auto[0]	auto[CntIncrSt]	34630	1			T1	1		T2	6		T10	1
auto[0]	auto[CntProgSt]	1927505	1			T1	23		T2	26		T10	2
auto[0]	auto[TransCheckSt]	26654	1			T1	1		T2	6		T10	1
auto[0]	auto[TokenHashSt]	37659863	1			T1	11		T2	273		T10	314
auto[0]	auto[FlashRmaSt]	33953	1			T2	6		T11	19		T12	49
auto[0]	auto[TokenCheck0St]	11826	1			T2	6		T11	19		T12	26
auto[0]	auto[TokenCheck1St]	8576	1			T2	6		T11	11		T12	13
auto[0]	auto[TransProgSt]	541936	1			T2	27		T11	1833		T12	22
auto[0]	auto[PostTransSt]	13626442	1			T1	1058		T2	21153		T10	1264
auto[0]	auto[ScrapSt]	271994	1			T7	563		T34	1462		T35	44
auto[0]	auto[EscalateSt]	5417013	1			T2	10234		T4	509		T5	1711
auto[0]	auto[InvalidSt]	11728731	1			T2	9552		T15	3541		T18	1857
auto[1]	auto[ResetSt]	165	1			T42	5		T43	4		T44	9
auto[1]	auto[IdleSt]	155	1			T45	8		T46	3		T47	2
auto[1]	auto[ClkMuxSt]	39	1			T42	2		T43	1		T44	1
auto[1]	auto[CntIncrSt]	50	1			T42	1		T44	3		T46	2
auto[1]	auto[CntProgSt]	771	1			T42	30		T43	15		T44	27
auto[1]	auto[TransCheckSt]	73	1			T45	1		T47	6		T51	4
auto[1]	auto[TokenHashSt]	478	1			T36	1		T42	7		T43	4
auto[1]	auto[FlashRmaSt]	70	1			T42	1		T44	4		T45	2
auto[1]	auto[TokenCheck0St]	13	1			T42	1		T44	1		T47	1
auto[1]	auto[TokenCheck1St]	104	1			T42	2		T45	3		T46	2
auto[1]	auto[TransProgSt]	485	1			T42	16		T43	5		T44	13
auto[1]	auto[PostTransSt]	2506	1			T4	7		T5	11		T11	2
auto[1]	auto[ScrapSt]	40	1			T42	2		T44	2		T47	4
auto[1]	auto[EscalateSt]	1388763	1			T2	194		T4	686		T5	1078
auto[1]	auto[InvalidSt]	6909	1			T2	2		T15	12		T18	8

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7193061	1			T1	102		T2	1204		T3	196
auto[0]	auto[IdleSt]	23632302	1			T1	16		T2	17459		T3	2627
auto[0]	auto[ClkMuxSt]	34877	1			T1	1		T2	6		T10	1
auto[0]	auto[CntIncrSt]	34637	1			T1	1		T2	6		T10	1
auto[0]	auto[CntProgSt]	1927499	1			T1	23		T2	26		T10	2
auto[0]	auto[TransCheckSt]	26651	1			T1	1		T2	6		T10	1
auto[0]	auto[TokenHashSt]	37659898	1			T1	11		T2	273		T10	314
auto[0]	auto[FlashRmaSt]	33964	1			T2	6		T11	19		T12	49
auto[0]	auto[TokenCheck0St]	11818	1			T2	6		T11	19		T12	26
auto[0]	auto[TokenCheck1St]	8573	1			T2	6		T11	11		T12	13
auto[0]	auto[TransProgSt]	541907	1			T2	27		T11	1833		T12	22
auto[0]	auto[PostTransSt]	13626336	1			T1	1058		T2	21153		T10	1264
auto[0]	auto[ScrapSt]	272003	1			T7	563		T34	1462		T35	44
auto[0]	auto[EscalateSt]	5398972	1			T2	10234		T4	999		T5	1907
auto[0]	auto[InvalidSt]	11728636	1			T2	9552		T15	3548		T18	1860
auto[1]	auto[ResetSt]	181	1			T42	7		T43	5		T44	6
auto[1]	auto[IdleSt]	134	1			T45	8		T46	3		T47	3
auto[1]	auto[ClkMuxSt]	44	1			T42	1		T43	1		T44	1
auto[1]	auto[CntIncrSt]	43	1			T42	1		T43	1		T44	2
auto[1]	auto[CntProgSt]	777	1			T42	31		T43	15		T44	26
auto[1]	auto[TransCheckSt]	76	1			T45	1		T47	10		T51	5
auto[1]	auto[TokenHashSt]	443	1			T42	4		T43	5		T224	1
auto[1]	auto[FlashRmaSt]	59	1			T42	1		T43	1		T44	2
auto[1]	auto[TokenCheck0St]	21	1			T42	1		T45	2		T47	1
auto[1]	auto[TokenCheck1St]	107	1			T42	2		T43	2		T44	2
auto[1]	auto[TransProgSt]	514	1			T42	13		T43	8		T44	14
auto[1]	auto[PostTransSt]	2612	1			T4	2		T5	9		T11	4
auto[1]	auto[ScrapSt]	31	1			T42	2		T44	1		T47	4
auto[1]	auto[EscalateSt]	1406804	1			T2	194		T4	196		T5	882
auto[1]	auto[InvalidSt]	7004	1			T2	2		T15	5		T18	5