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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.89 97.92 95.75 93.38 97.62 98.52 98.76 96.29


Total test records in report: 992
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T823 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3066631437 Jul 11 05:20:35 PM PDT 24 Jul 11 05:20:52 PM PDT 24 1289870883 ps
T824 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1990149214 Jul 11 05:19:48 PM PDT 24 Jul 11 05:20:07 PM PDT 24 243672831 ps
T825 /workspace/coverage/default/47.lc_ctrl_sec_mubi.3153831773 Jul 11 05:21:54 PM PDT 24 Jul 11 05:22:11 PM PDT 24 3989053011 ps
T826 /workspace/coverage/default/24.lc_ctrl_sec_mubi.3965202349 Jul 11 05:20:49 PM PDT 24 Jul 11 05:21:09 PM PDT 24 1387550791 ps
T827 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.994959557 Jul 11 05:19:26 PM PDT 24 Jul 11 05:19:38 PM PDT 24 900269359 ps
T828 /workspace/coverage/default/42.lc_ctrl_sec_mubi.3077210981 Jul 11 05:21:37 PM PDT 24 Jul 11 05:21:54 PM PDT 24 979738102 ps
T829 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2601668402 Jul 11 05:19:06 PM PDT 24 Jul 11 05:19:12 PM PDT 24 137434630 ps
T830 /workspace/coverage/default/13.lc_ctrl_smoke.3909751844 Jul 11 05:19:59 PM PDT 24 Jul 11 05:20:07 PM PDT 24 37729443 ps
T75 /workspace/coverage/default/22.lc_ctrl_smoke.2800207198 Jul 11 05:20:49 PM PDT 24 Jul 11 05:20:56 PM PDT 24 248686960 ps
T831 /workspace/coverage/default/32.lc_ctrl_security_escalation.94451908 Jul 11 05:21:09 PM PDT 24 Jul 11 05:21:27 PM PDT 24 677547885 ps
T832 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1898270889 Jul 11 05:20:58 PM PDT 24 Jul 11 05:21:12 PM PDT 24 271809766 ps
T833 /workspace/coverage/default/4.lc_ctrl_smoke.47564580 Jul 11 05:19:02 PM PDT 24 Jul 11 05:19:04 PM PDT 24 66381062 ps
T834 /workspace/coverage/default/41.lc_ctrl_errors.4162638912 Jul 11 05:21:34 PM PDT 24 Jul 11 05:21:53 PM PDT 24 355500459 ps
T835 /workspace/coverage/default/27.lc_ctrl_prog_failure.117336675 Jul 11 05:20:57 PM PDT 24 Jul 11 05:21:06 PM PDT 24 89687161 ps
T836 /workspace/coverage/default/8.lc_ctrl_security_escalation.625027695 Jul 11 05:19:36 PM PDT 24 Jul 11 05:19:50 PM PDT 24 4563786748 ps
T837 /workspace/coverage/default/9.lc_ctrl_state_post_trans.4053797463 Jul 11 05:19:49 PM PDT 24 Jul 11 05:19:54 PM PDT 24 153913267 ps
T838 /workspace/coverage/default/9.lc_ctrl_alert_test.1112888654 Jul 11 05:19:54 PM PDT 24 Jul 11 05:20:02 PM PDT 24 12202403 ps
T839 /workspace/coverage/default/12.lc_ctrl_state_post_trans.1893434411 Jul 11 05:19:58 PM PDT 24 Jul 11 05:20:12 PM PDT 24 264797582 ps
T840 /workspace/coverage/default/42.lc_ctrl_jtag_access.651911405 Jul 11 05:21:39 PM PDT 24 Jul 11 05:21:55 PM PDT 24 5217675434 ps
T841 /workspace/coverage/default/6.lc_ctrl_sec_mubi.2103961429 Jul 11 05:19:21 PM PDT 24 Jul 11 05:19:34 PM PDT 24 768857312 ps
T842 /workspace/coverage/default/15.lc_ctrl_jtag_access.290123057 Jul 11 05:20:18 PM PDT 24 Jul 11 05:20:23 PM PDT 24 581042694 ps
T843 /workspace/coverage/default/47.lc_ctrl_errors.1598269206 Jul 11 05:21:53 PM PDT 24 Jul 11 05:22:09 PM PDT 24 218268607 ps
T844 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3047105447 Jul 11 05:21:34 PM PDT 24 Jul 11 05:21:40 PM PDT 24 33904756 ps
T845 /workspace/coverage/default/25.lc_ctrl_state_post_trans.3218115770 Jul 11 05:20:55 PM PDT 24 Jul 11 05:21:04 PM PDT 24 228025371 ps
T846 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.510365611 Jul 11 05:18:30 PM PDT 24 Jul 11 05:19:07 PM PDT 24 15146574150 ps
T847 /workspace/coverage/default/28.lc_ctrl_prog_failure.2528453685 Jul 11 05:20:55 PM PDT 24 Jul 11 05:21:05 PM PDT 24 313570614 ps
T848 /workspace/coverage/default/49.lc_ctrl_sec_mubi.1158572842 Jul 11 05:22:01 PM PDT 24 Jul 11 05:22:18 PM PDT 24 382524288 ps
T849 /workspace/coverage/default/35.lc_ctrl_stress_all.4020712350 Jul 11 05:21:32 PM PDT 24 Jul 11 05:24:05 PM PDT 24 4382684094 ps
T850 /workspace/coverage/default/1.lc_ctrl_state_failure.3489622682 Jul 11 05:18:53 PM PDT 24 Jul 11 05:19:19 PM PDT 24 800384531 ps
T851 /workspace/coverage/default/13.lc_ctrl_jtag_errors.599314167 Jul 11 05:20:22 PM PDT 24 Jul 11 05:21:11 PM PDT 24 1656468798 ps
T852 /workspace/coverage/default/1.lc_ctrl_smoke.3353066023 Jul 11 05:18:32 PM PDT 24 Jul 11 05:18:34 PM PDT 24 75924252 ps
T853 /workspace/coverage/default/40.lc_ctrl_errors.1942564124 Jul 11 05:21:42 PM PDT 24 Jul 11 05:22:04 PM PDT 24 554258319 ps
T854 /workspace/coverage/default/21.lc_ctrl_jtag_access.1570235147 Jul 11 05:20:54 PM PDT 24 Jul 11 05:21:10 PM PDT 24 819715212 ps
T855 /workspace/coverage/default/26.lc_ctrl_security_escalation.3425173114 Jul 11 05:20:58 PM PDT 24 Jul 11 05:21:16 PM PDT 24 1203803417 ps
T856 /workspace/coverage/default/8.lc_ctrl_jtag_priority.371894328 Jul 11 05:19:40 PM PDT 24 Jul 11 05:19:48 PM PDT 24 378209019 ps
T857 /workspace/coverage/default/2.lc_ctrl_security_escalation.1575644986 Jul 11 05:18:54 PM PDT 24 Jul 11 05:19:06 PM PDT 24 1188106357 ps
T858 /workspace/coverage/default/12.lc_ctrl_sec_mubi.1675652311 Jul 11 05:20:23 PM PDT 24 Jul 11 05:20:36 PM PDT 24 207058329 ps
T859 /workspace/coverage/default/38.lc_ctrl_prog_failure.2705641004 Jul 11 05:21:20 PM PDT 24 Jul 11 05:21:25 PM PDT 24 146911295 ps
T860 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3637094536 Jul 11 05:21:15 PM PDT 24 Jul 11 05:21:19 PM PDT 24 41361200 ps
T861 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3195028481 Jul 11 05:21:43 PM PDT 24 Jul 11 05:21:52 PM PDT 24 30656629 ps
T862 /workspace/coverage/default/37.lc_ctrl_jtag_access.798631715 Jul 11 05:21:19 PM PDT 24 Jul 11 05:21:28 PM PDT 24 6614389043 ps
T863 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3537088773 Jul 11 05:19:08 PM PDT 24 Jul 11 05:19:19 PM PDT 24 206154148 ps
T864 /workspace/coverage/default/26.lc_ctrl_jtag_access.2818935991 Jul 11 05:20:54 PM PDT 24 Jul 11 05:21:04 PM PDT 24 824559803 ps
T865 /workspace/coverage/default/46.lc_ctrl_stress_all.600946751 Jul 11 05:21:47 PM PDT 24 Jul 11 05:25:36 PM PDT 24 19424615597 ps
T866 /workspace/coverage/default/3.lc_ctrl_smoke.4209131377 Jul 11 05:18:49 PM PDT 24 Jul 11 05:18:51 PM PDT 24 102929923 ps
T76 /workspace/coverage/default/36.lc_ctrl_stress_all.1736964398 Jul 11 05:21:20 PM PDT 24 Jul 11 05:22:37 PM PDT 24 6821384091 ps
T176 /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.780304607 Jul 11 05:21:43 PM PDT 24 Jul 11 05:41:34 PM PDT 24 109797634159 ps
T186 /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1827546803 Jul 11 05:19:19 PM PDT 24 Jul 11 05:21:28 PM PDT 24 26795510267 ps
T187 /workspace/coverage/default/46.lc_ctrl_smoke.717669449 Jul 11 05:21:54 PM PDT 24 Jul 11 05:22:04 PM PDT 24 208166291 ps
T188 /workspace/coverage/default/10.lc_ctrl_security_escalation.3061618078 Jul 11 05:19:55 PM PDT 24 Jul 11 05:20:13 PM PDT 24 315340126 ps
T189 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4069356450 Jul 11 05:21:44 PM PDT 24 Jul 11 05:22:03 PM PDT 24 1152080191 ps
T190 /workspace/coverage/default/21.lc_ctrl_prog_failure.3945403447 Jul 11 05:20:35 PM PDT 24 Jul 11 05:20:39 PM PDT 24 34089154 ps
T191 /workspace/coverage/default/7.lc_ctrl_sec_mubi.667383721 Jul 11 05:19:28 PM PDT 24 Jul 11 05:19:42 PM PDT 24 291730471 ps
T192 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1479188797 Jul 11 05:20:35 PM PDT 24 Jul 11 05:20:46 PM PDT 24 279822192 ps
T193 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2227817792 Jul 11 05:20:51 PM PDT 24 Jul 11 05:21:13 PM PDT 24 691341081 ps
T194 /workspace/coverage/default/48.lc_ctrl_sec_token_mux.38309100 Jul 11 05:22:04 PM PDT 24 Jul 11 05:22:21 PM PDT 24 239093073 ps
T867 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2955424425 Jul 11 05:18:25 PM PDT 24 Jul 11 05:18:41 PM PDT 24 3449100935 ps
T127 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.785472106 Jul 11 06:23:23 PM PDT 24 Jul 11 06:24:04 PM PDT 24 3297287475 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1453695019 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:37 PM PDT 24 138087318 ps
T153 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3817423966 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:35 PM PDT 24 83053447 ps
T129 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1719102852 Jul 11 06:23:23 PM PDT 24 Jul 11 06:23:36 PM PDT 24 15174617 ps
T149 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3835456712 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:35 PM PDT 24 166965800 ps
T868 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2647605495 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:37 PM PDT 24 98566160 ps
T117 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2947702138 Jul 11 06:23:29 PM PDT 24 Jul 11 06:23:42 PM PDT 24 342719629 ps
T113 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1806433604 Jul 11 06:23:43 PM PDT 24 Jul 11 06:23:53 PM PDT 24 200303104 ps
T122 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2048657162 Jul 11 06:23:14 PM PDT 24 Jul 11 06:23:29 PM PDT 24 22099164 ps
T120 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4187768287 Jul 11 06:23:38 PM PDT 24 Jul 11 06:23:48 PM PDT 24 17837141 ps
T166 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1353533087 Jul 11 06:23:16 PM PDT 24 Jul 11 06:23:30 PM PDT 24 51272283 ps
T123 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1515898185 Jul 11 06:23:28 PM PDT 24 Jul 11 06:23:41 PM PDT 24 47959847 ps
T869 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1441490966 Jul 11 06:23:30 PM PDT 24 Jul 11 06:23:42 PM PDT 24 165059873 ps
T870 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2657557923 Jul 11 06:23:16 PM PDT 24 Jul 11 06:23:51 PM PDT 24 1870814164 ps
T114 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.551709408 Jul 11 06:23:16 PM PDT 24 Jul 11 06:23:33 PM PDT 24 100403656 ps
T152 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1934741153 Jul 11 06:23:17 PM PDT 24 Jul 11 06:23:34 PM PDT 24 1383832031 ps
T115 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.411891604 Jul 11 06:23:51 PM PDT 24 Jul 11 06:24:00 PM PDT 24 114455774 ps
T136 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.266232976 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:36 PM PDT 24 58563750 ps
T200 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2021349578 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:36 PM PDT 24 39407439 ps
T167 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3166286759 Jul 11 06:23:49 PM PDT 24 Jul 11 06:23:58 PM PDT 24 74109248 ps
T871 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.548311066 Jul 11 06:23:28 PM PDT 24 Jul 11 06:23:41 PM PDT 24 1857778669 ps
T872 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2407259649 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:34 PM PDT 24 32941212 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.433785350 Jul 11 06:23:19 PM PDT 24 Jul 11 06:23:35 PM PDT 24 118754046 ps
T212 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2875338407 Jul 11 06:23:48 PM PDT 24 Jul 11 06:23:57 PM PDT 24 40365484 ps
T121 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1448544782 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:44 PM PDT 24 68679930 ps
T118 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3692878505 Jul 11 06:23:47 PM PDT 24 Jul 11 06:23:56 PM PDT 24 51336683 ps
T213 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3832510414 Jul 11 06:23:41 PM PDT 24 Jul 11 06:23:50 PM PDT 24 29425425 ps
T201 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1567329124 Jul 11 06:23:17 PM PDT 24 Jul 11 06:23:33 PM PDT 24 102668585 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3184849862 Jul 11 06:23:17 PM PDT 24 Jul 11 06:23:49 PM PDT 24 3011826051 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2198922062 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:35 PM PDT 24 101670840 ps
T138 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294651211 Jul 11 06:23:14 PM PDT 24 Jul 11 06:23:32 PM PDT 24 263561466 ps
T876 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3791902959 Jul 11 06:23:53 PM PDT 24 Jul 11 06:24:02 PM PDT 24 33994699 ps
T877 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2082494357 Jul 11 06:23:43 PM PDT 24 Jul 11 06:23:53 PM PDT 24 194267408 ps
T202 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.310694517 Jul 11 06:23:42 PM PDT 24 Jul 11 06:23:50 PM PDT 24 42562643 ps
T214 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1219430228 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:43 PM PDT 24 18764067 ps
T215 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1603063521 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:34 PM PDT 24 27667302 ps
T878 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1702481885 Jul 11 06:23:27 PM PDT 24 Jul 11 06:24:05 PM PDT 24 5026896007 ps
T879 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3950359805 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:44 PM PDT 24 457913466 ps
T130 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3751558194 Jul 11 06:23:36 PM PDT 24 Jul 11 06:23:47 PM PDT 24 228118611 ps
T203 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1918310367 Jul 11 06:23:18 PM PDT 24 Jul 11 06:23:32 PM PDT 24 13898811 ps
T880 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.66467443 Jul 11 06:23:34 PM PDT 24 Jul 11 06:23:49 PM PDT 24 355902955 ps
T150 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4238058552 Jul 11 06:23:17 PM PDT 24 Jul 11 06:23:38 PM PDT 24 2595551083 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2451335250 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:35 PM PDT 24 219528683 ps
T119 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2782381806 Jul 11 06:23:45 PM PDT 24 Jul 11 06:23:53 PM PDT 24 110522017 ps
T131 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3124176482 Jul 11 06:23:46 PM PDT 24 Jul 11 06:23:55 PM PDT 24 143530042 ps
T216 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1266070570 Jul 11 06:23:44 PM PDT 24 Jul 11 06:23:52 PM PDT 24 24600473 ps
T132 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4293239864 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:35 PM PDT 24 165264590 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3034326258 Jul 11 06:23:26 PM PDT 24 Jul 11 06:23:39 PM PDT 24 212095258 ps
T883 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4168062785 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:43 PM PDT 24 39407232 ps
T204 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.581438976 Jul 11 06:23:17 PM PDT 24 Jul 11 06:23:32 PM PDT 24 16583188 ps
T217 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1433893798 Jul 11 06:23:39 PM PDT 24 Jul 11 06:23:48 PM PDT 24 42458453 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.297886401 Jul 11 06:23:32 PM PDT 24 Jul 11 06:23:49 PM PDT 24 2139483004 ps
T124 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2145291888 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:37 PM PDT 24 28133900 ps
T151 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4223228080 Jul 11 06:23:11 PM PDT 24 Jul 11 06:23:28 PM PDT 24 384998427 ps
T885 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3251457867 Jul 11 06:23:32 PM PDT 24 Jul 11 06:24:00 PM PDT 24 14883336856 ps
T886 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3922486880 Jul 11 06:23:27 PM PDT 24 Jul 11 06:23:39 PM PDT 24 58809109 ps
T126 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2596244445 Jul 11 06:23:43 PM PDT 24 Jul 11 06:23:53 PM PDT 24 628883412 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2506396960 Jul 11 06:23:14 PM PDT 24 Jul 11 06:23:30 PM PDT 24 231497877 ps
T142 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2637660864 Jul 11 06:23:27 PM PDT 24 Jul 11 06:23:40 PM PDT 24 306411365 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1737769227 Jul 11 06:23:13 PM PDT 24 Jul 11 06:24:13 PM PDT 24 2218884039 ps
T889 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.866208366 Jul 11 06:23:24 PM PDT 24 Jul 11 06:23:38 PM PDT 24 252597960 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.463683751 Jul 11 06:23:17 PM PDT 24 Jul 11 06:23:31 PM PDT 24 56823611 ps
T891 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3742702723 Jul 11 06:23:18 PM PDT 24 Jul 11 06:23:33 PM PDT 24 180559666 ps
T892 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.184375395 Jul 11 06:23:48 PM PDT 24 Jul 11 06:23:56 PM PDT 24 15939097 ps
T205 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1954721622 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:43 PM PDT 24 44437610 ps
T133 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1999919423 Jul 11 06:23:38 PM PDT 24 Jul 11 06:23:50 PM PDT 24 119312146 ps
T206 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.845076122 Jul 11 06:23:36 PM PDT 24 Jul 11 06:23:46 PM PDT 24 19175115 ps
T893 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1454457783 Jul 11 06:23:33 PM PDT 24 Jul 11 06:23:45 PM PDT 24 72368679 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.71827727 Jul 11 06:23:14 PM PDT 24 Jul 11 06:23:38 PM PDT 24 6236957430 ps
T895 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3711762334 Jul 11 06:23:37 PM PDT 24 Jul 11 06:23:47 PM PDT 24 13423503 ps
T896 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1176895831 Jul 11 06:23:38 PM PDT 24 Jul 11 06:23:48 PM PDT 24 81939969 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2567385991 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:36 PM PDT 24 72976562 ps
T898 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.139015246 Jul 11 06:23:34 PM PDT 24 Jul 11 06:23:48 PM PDT 24 375592182 ps
T134 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1082487123 Jul 11 06:23:42 PM PDT 24 Jul 11 06:23:53 PM PDT 24 110758524 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1260951888 Jul 11 06:23:36 PM PDT 24 Jul 11 06:23:47 PM PDT 24 222680971 ps
T900 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.115788420 Jul 11 06:23:37 PM PDT 24 Jul 11 06:23:49 PM PDT 24 210995906 ps
T125 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1060348090 Jul 11 06:23:18 PM PDT 24 Jul 11 06:23:33 PM PDT 24 188695901 ps
T901 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2570534386 Jul 11 06:23:40 PM PDT 24 Jul 11 06:23:52 PM PDT 24 191330687 ps
T902 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2661586738 Jul 11 06:23:42 PM PDT 24 Jul 11 06:23:52 PM PDT 24 964452077 ps
T903 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.757113484 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:35 PM PDT 24 39401416 ps
T904 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.444612186 Jul 11 06:23:29 PM PDT 24 Jul 11 06:23:42 PM PDT 24 145990667 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3557114328 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:34 PM PDT 24 65652836 ps
T906 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1754915228 Jul 11 06:23:39 PM PDT 24 Jul 11 06:23:48 PM PDT 24 58155164 ps
T907 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3863941528 Jul 11 06:23:53 PM PDT 24 Jul 11 06:24:02 PM PDT 24 18345826 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2402973266 Jul 11 06:23:16 PM PDT 24 Jul 11 06:23:31 PM PDT 24 50736266 ps
T909 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.238185586 Jul 11 06:23:15 PM PDT 24 Jul 11 06:23:30 PM PDT 24 33092283 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1684347218 Jul 11 06:23:30 PM PDT 24 Jul 11 06:23:41 PM PDT 24 25973157 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3583343350 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:37 PM PDT 24 97677268 ps
T207 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3675203090 Jul 11 06:23:28 PM PDT 24 Jul 11 06:23:40 PM PDT 24 48844893 ps
T912 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3296458855 Jul 11 06:23:27 PM PDT 24 Jul 11 06:23:40 PM PDT 24 198068652 ps
T913 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1879019196 Jul 11 06:23:17 PM PDT 24 Jul 11 06:23:33 PM PDT 24 339478180 ps
T914 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.882620694 Jul 11 06:23:23 PM PDT 24 Jul 11 06:23:37 PM PDT 24 56912193 ps
T915 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.693495008 Jul 11 06:23:13 PM PDT 24 Jul 11 06:23:28 PM PDT 24 65136421 ps
T916 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4027402930 Jul 11 06:23:46 PM PDT 24 Jul 11 06:23:55 PM PDT 24 33772261 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.407162241 Jul 11 06:23:13 PM PDT 24 Jul 11 06:23:29 PM PDT 24 65010879 ps
T145 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.492387281 Jul 11 06:23:53 PM PDT 24 Jul 11 06:24:04 PM PDT 24 78351321 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2793423392 Jul 11 06:23:12 PM PDT 24 Jul 11 06:23:27 PM PDT 24 102032303 ps
T919 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3224243913 Jul 11 06:23:41 PM PDT 24 Jul 11 06:23:49 PM PDT 24 34676491 ps
T920 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1189801307 Jul 11 06:23:44 PM PDT 24 Jul 11 06:23:52 PM PDT 24 67722797 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.162918293 Jul 11 06:23:18 PM PDT 24 Jul 11 06:23:32 PM PDT 24 68173751 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1771303122 Jul 11 06:23:28 PM PDT 24 Jul 11 06:23:41 PM PDT 24 31467400 ps
T923 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.828274787 Jul 11 06:23:40 PM PDT 24 Jul 11 06:23:50 PM PDT 24 46474287 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3401489464 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:35 PM PDT 24 15335170 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.552483076 Jul 11 06:23:27 PM PDT 24 Jul 11 06:23:40 PM PDT 24 14809743 ps
T926 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2619370141 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:45 PM PDT 24 311702795 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3150943924 Jul 11 06:23:13 PM PDT 24 Jul 11 06:23:30 PM PDT 24 1068766424 ps
T928 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4191581207 Jul 11 06:23:42 PM PDT 24 Jul 11 06:23:51 PM PDT 24 24288277 ps
T929 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2493739520 Jul 11 06:23:26 PM PDT 24 Jul 11 06:23:39 PM PDT 24 41319255 ps
T208 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2376407158 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:35 PM PDT 24 17964226 ps
T209 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3213419696 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:34 PM PDT 24 52885898 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.984817280 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:35 PM PDT 24 16345922 ps
T931 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.933104510 Jul 11 06:23:15 PM PDT 24 Jul 11 06:23:35 PM PDT 24 451908548 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1142792921 Jul 11 06:23:14 PM PDT 24 Jul 11 06:23:29 PM PDT 24 46934932 ps
T933 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3807743062 Jul 11 06:23:39 PM PDT 24 Jul 11 06:23:49 PM PDT 24 109868122 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.234208150 Jul 11 06:23:11 PM PDT 24 Jul 11 06:23:29 PM PDT 24 80878057 ps
T935 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2724048037 Jul 11 06:23:42 PM PDT 24 Jul 11 06:23:51 PM PDT 24 30419395 ps
T936 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2289381212 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:45 PM PDT 24 611737583 ps
T146 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1523057591 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:37 PM PDT 24 296316799 ps
T937 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3189594150 Jul 11 06:23:40 PM PDT 24 Jul 11 06:23:49 PM PDT 24 15068342 ps
T938 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1858017095 Jul 11 06:23:40 PM PDT 24 Jul 11 06:23:49 PM PDT 24 24538905 ps
T939 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1775368511 Jul 11 06:23:45 PM PDT 24 Jul 11 06:23:52 PM PDT 24 48219132 ps
T940 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1366265239 Jul 11 06:23:38 PM PDT 24 Jul 11 06:23:47 PM PDT 24 26161506 ps
T143 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.807132879 Jul 11 06:23:42 PM PDT 24 Jul 11 06:23:51 PM PDT 24 162299025 ps
T941 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4201960848 Jul 11 06:23:29 PM PDT 24 Jul 11 06:23:50 PM PDT 24 439973787 ps
T942 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4162135713 Jul 11 06:23:34 PM PDT 24 Jul 11 06:23:45 PM PDT 24 26441427 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2973871365 Jul 11 06:23:39 PM PDT 24 Jul 11 06:23:49 PM PDT 24 255531387 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1110935380 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:36 PM PDT 24 65331559 ps
T945 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1085479690 Jul 11 06:23:32 PM PDT 24 Jul 11 06:23:44 PM PDT 24 96400215 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2746462844 Jul 11 06:23:37 PM PDT 24 Jul 11 06:23:48 PM PDT 24 829313397 ps
T947 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.766015021 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:39 PM PDT 24 370531629 ps
T948 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.451594875 Jul 11 06:23:34 PM PDT 24 Jul 11 06:23:45 PM PDT 24 39110570 ps
T949 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4167404194 Jul 11 06:23:30 PM PDT 24 Jul 11 06:23:42 PM PDT 24 33810244 ps
T950 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3726775403 Jul 11 06:23:27 PM PDT 24 Jul 11 06:23:40 PM PDT 24 36519233 ps
T951 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.360892412 Jul 11 06:23:43 PM PDT 24 Jul 11 06:23:52 PM PDT 24 44917946 ps
T952 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3625635519 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:36 PM PDT 24 225816845 ps
T147 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1427558097 Jul 11 06:23:30 PM PDT 24 Jul 11 06:23:43 PM PDT 24 65240129 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1880528774 Jul 11 06:23:34 PM PDT 24 Jul 11 06:23:46 PM PDT 24 184933607 ps
T954 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3856272782 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:35 PM PDT 24 135968571 ps
T955 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4189618983 Jul 11 06:23:53 PM PDT 24 Jul 11 06:24:02 PM PDT 24 16107273 ps
T956 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3517495474 Jul 11 06:23:48 PM PDT 24 Jul 11 06:23:56 PM PDT 24 159186283 ps
T957 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1012435803 Jul 11 06:23:36 PM PDT 24 Jul 11 06:23:49 PM PDT 24 81570864 ps
T958 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3333342437 Jul 11 06:23:30 PM PDT 24 Jul 11 06:23:44 PM PDT 24 106030910 ps
T959 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.734647114 Jul 11 06:23:29 PM PDT 24 Jul 11 06:23:41 PM PDT 24 100497584 ps
T139 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2670200448 Jul 11 06:23:34 PM PDT 24 Jul 11 06:23:47 PM PDT 24 736887871 ps
T210 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4251877286 Jul 11 06:23:29 PM PDT 24 Jul 11 06:23:40 PM PDT 24 27317906 ps
T135 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3721416098 Jul 11 06:23:44 PM PDT 24 Jul 11 06:23:53 PM PDT 24 60972819 ps
T960 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3061854169 Jul 11 06:23:15 PM PDT 24 Jul 11 06:23:42 PM PDT 24 5531056800 ps
T961 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1037154166 Jul 11 06:23:39 PM PDT 24 Jul 11 06:23:50 PM PDT 24 72237437 ps
T962 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.902985379 Jul 11 06:23:33 PM PDT 24 Jul 11 06:23:44 PM PDT 24 38112682 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2708561594 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:57 PM PDT 24 648933144 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3911594911 Jul 11 06:23:38 PM PDT 24 Jul 11 06:23:58 PM PDT 24 486638925 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1219490392 Jul 11 06:23:18 PM PDT 24 Jul 11 06:23:34 PM PDT 24 364449014 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1377619025 Jul 11 06:23:18 PM PDT 24 Jul 11 06:23:40 PM PDT 24 1643454635 ps
T148 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2212085617 Jul 11 06:23:14 PM PDT 24 Jul 11 06:23:30 PM PDT 24 55536095 ps
T967 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3406659329 Jul 11 06:23:18 PM PDT 24 Jul 11 06:23:32 PM PDT 24 14952423 ps
T968 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2778108498 Jul 11 06:23:38 PM PDT 24 Jul 11 06:23:48 PM PDT 24 13449865 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2716054118 Jul 11 06:23:30 PM PDT 24 Jul 11 06:23:42 PM PDT 24 12779307 ps
T211 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1959561964 Jul 11 06:23:46 PM PDT 24 Jul 11 06:23:55 PM PDT 24 14294855 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.880517893 Jul 11 06:23:25 PM PDT 24 Jul 11 06:23:39 PM PDT 24 856045698 ps
T144 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2669132014 Jul 11 06:23:41 PM PDT 24 Jul 11 06:23:52 PM PDT 24 401569269 ps
T971 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.907590517 Jul 11 06:23:42 PM PDT 24 Jul 11 06:23:53 PM PDT 24 49860158 ps
T140 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1841954488 Jul 11 06:23:21 PM PDT 24 Jul 11 06:23:36 PM PDT 24 473848043 ps
T972 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.462850529 Jul 11 06:23:35 PM PDT 24 Jul 11 06:23:46 PM PDT 24 186998763 ps
T973 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2296802196 Jul 11 06:23:45 PM PDT 24 Jul 11 06:23:53 PM PDT 24 21957722 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2142648767 Jul 11 06:23:16 PM PDT 24 Jul 11 06:23:33 PM PDT 24 87778913 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3322272414 Jul 11 06:23:22 PM PDT 24 Jul 11 06:23:36 PM PDT 24 132461791 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2640548172 Jul 11 06:23:11 PM PDT 24 Jul 11 06:23:25 PM PDT 24 26617691 ps
T977 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.384170635 Jul 11 06:23:42 PM PDT 24 Jul 11 06:23:53 PM PDT 24 437592902 ps
T978 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4164440400 Jul 11 06:23:47 PM PDT 24 Jul 11 06:23:57 PM PDT 24 45810086 ps
T979 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1681421286 Jul 11 06:23:29 PM PDT 24 Jul 11 06:23:42 PM PDT 24 23333786 ps
T980 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3352751946 Jul 11 06:23:51 PM PDT 24 Jul 11 06:24:00 PM PDT 24 119742140 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3964098410 Jul 11 06:23:32 PM PDT 24 Jul 11 06:23:47 PM PDT 24 661237188 ps
T982 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1130125579 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:43 PM PDT 24 13546630 ps
T983 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3331714826 Jul 11 06:23:47 PM PDT 24 Jul 11 06:23:56 PM PDT 24 180422962 ps
T984 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.241252178 Jul 11 06:23:41 PM PDT 24 Jul 11 06:23:50 PM PDT 24 157287786 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.713922601 Jul 11 06:23:20 PM PDT 24 Jul 11 06:23:34 PM PDT 24 162031938 ps
T986 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2916840773 Jul 11 06:23:38 PM PDT 24 Jul 11 06:23:47 PM PDT 24 22748751 ps
T141 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2429060879 Jul 11 06:23:52 PM PDT 24 Jul 11 06:24:01 PM PDT 24 368903545 ps
T137 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2222273245 Jul 11 06:23:41 PM PDT 24 Jul 11 06:23:52 PM PDT 24 111485740 ps
T987 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4288204505 Jul 11 06:23:12 PM PDT 24 Jul 11 06:23:29 PM PDT 24 65697341 ps
T988 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1353675281 Jul 11 06:23:31 PM PDT 24 Jul 11 06:23:43 PM PDT 24 69449799 ps
T989 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.909340105 Jul 11 06:23:30 PM PDT 24 Jul 11 06:23:55 PM PDT 24 2562649814 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4087407884 Jul 11 06:23:32 PM PDT 24 Jul 11 06:23:44 PM PDT 24 83389256 ps
T991 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2994831176 Jul 11 06:23:47 PM PDT 24 Jul 11 06:23:55 PM PDT 24 105747942 ps
T992 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2882537552 Jul 11 06:23:44 PM PDT 24 Jul 11 06:24:02 PM PDT 24 477073383 ps

Test location /workspace/coverage/default/10.lc_ctrl_errors.4273818540
Short name T11
Test name
Test status
Simulation time 379696835 ps
CPU time 15.71 seconds
Started Jul 11 05:19:57 PM PDT 24
Finished Jul 11 05:20:19 PM PDT 24
Peak memory 225984 kb
Host smart-71541295-11ed-475f-9c89-497fa637dfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273818540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.4273818540
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2767471044
Short name T14
Test name
Test status
Simulation time 65141197325 ps
CPU time 169.74 seconds
Started Jul 11 05:21:19 PM PDT 24
Finished Jul 11 05:24:12 PM PDT 24
Peak memory 310160 kb
Host smart-3e8369db-6118-41d7-97fc-33a57a6998b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767471044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2767471044
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.481329361
Short name T42
Test name
Test status
Simulation time 710521480 ps
CPU time 10.32 seconds
Started Jul 11 05:19:52 PM PDT 24
Finished Jul 11 05:20:07 PM PDT 24
Peak memory 218208 kb
Host smart-d539cffb-b267-4fab-a707-d58328c5cba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481329361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.481329361
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3197315472
Short name T18
Test name
Test status
Simulation time 226994725 ps
CPU time 10.1 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:20:01 PM PDT 24
Peak memory 225900 kb
Host smart-8ef99658-be8c-48c7-a7a6-8e0948c401f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197315472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3197315472
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.258066926
Short name T89
Test name
Test status
Simulation time 12197457958 ps
CPU time 212.93 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:25:27 PM PDT 24
Peak memory 283712 kb
Host smart-542c2fc1-e852-448e-b702-6f90fd7aab0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=258066926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.258066926
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.4098398915
Short name T320
Test name
Test status
Simulation time 1411654068 ps
CPU time 9.04 seconds
Started Jul 11 05:19:59 PM PDT 24
Finished Jul 11 05:20:14 PM PDT 24
Peak memory 218220 kb
Host smart-639cab08-3f98-43d4-980c-89a1bcda8d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098398915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.4098398915
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2159804489
Short name T6
Test name
Test status
Simulation time 621034464 ps
CPU time 15.14 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:19 PM PDT 24
Peak memory 217580 kb
Host smart-a5a2c53a-6d27-4bbf-8b35-043d00e346de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159804489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2159804489
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3235986355
Short name T49
Test name
Test status
Simulation time 249054582 ps
CPU time 22.05 seconds
Started Jul 11 05:18:52 PM PDT 24
Finished Jul 11 05:19:18 PM PDT 24
Peak memory 269436 kb
Host smart-b324daae-6f59-4cd2-98b6-0337fc2124c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235986355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3235986355
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.551709408
Short name T114
Test name
Test status
Simulation time 100403656 ps
CPU time 2.81 seconds
Started Jul 11 06:23:16 PM PDT 24
Finished Jul 11 06:23:33 PM PDT 24
Peak memory 222696 kb
Host smart-b9586e01-de4a-4dba-86f0-ef0252a51a74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551709408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.551709408
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1116250484
Short name T88
Test name
Test status
Simulation time 216803708354 ps
CPU time 457.71 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:27:38 PM PDT 24
Peak memory 266468 kb
Host smart-7533bc58-b48d-4bf1-a2ff-56d82a1ec4b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1116250484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1116250484
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3492878798
Short name T110
Test name
Test status
Simulation time 75223717169 ps
CPU time 581.18 seconds
Started Jul 11 05:18:53 PM PDT 24
Finished Jul 11 05:28:38 PM PDT 24
Peak memory 279452 kb
Host smart-1efd45a7-cb10-4d07-b4b2-28c10f6ae712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492878798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3492878798
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294651211
Short name T138
Test name
Test status
Simulation time 263561466 ps
CPU time 4.09 seconds
Started Jul 11 06:23:14 PM PDT 24
Finished Jul 11 06:23:32 PM PDT 24
Peak memory 219232 kb
Host smart-41c34c3e-3785-4255-a9d9-10b480adbec3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129465
1211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294651211
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2858525618
Short name T13
Test name
Test status
Simulation time 292580990 ps
CPU time 10.93 seconds
Started Jul 11 05:21:18 PM PDT 24
Finished Jul 11 05:21:32 PM PDT 24
Peak memory 218440 kb
Host smart-d9c27e75-5282-4c25-b9e7-7d3dc438bc08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858525618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2858525618
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3165471811
Short name T3
Test name
Test status
Simulation time 100844229 ps
CPU time 1.4 seconds
Started Jul 11 05:20:47 PM PDT 24
Finished Jul 11 05:20:51 PM PDT 24
Peak memory 208844 kb
Host smart-bcaa8ef5-338d-4e01-a2ff-fc633e2fba3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165471811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3165471811
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.581438976
Short name T204
Test name
Test status
Simulation time 16583188 ps
CPU time 1.13 seconds
Started Jul 11 06:23:17 PM PDT 24
Finished Jul 11 06:23:32 PM PDT 24
Peak memory 209636 kb
Host smart-0dfa1ed9-4618-411b-bbeb-2e46cf191571
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581438976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.581438976
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3972663054
Short name T19
Test name
Test status
Simulation time 1570023794 ps
CPU time 14.02 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:34 PM PDT 24
Peak memory 219860 kb
Host smart-2c061582-8720-49ed-bd76-7ba636d42a69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972663054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3972663054
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3013009051
Short name T87
Test name
Test status
Simulation time 15390001570 ps
CPU time 185.31 seconds
Started Jul 11 05:20:50 PM PDT 24
Finished Jul 11 05:24:00 PM PDT 24
Peak memory 487632 kb
Host smart-913d504a-add9-44ca-90fb-7012e6ed4d37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3013009051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3013009051
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1999919423
Short name T133
Test name
Test status
Simulation time 119312146 ps
CPU time 3.51 seconds
Started Jul 11 06:23:38 PM PDT 24
Finished Jul 11 06:23:50 PM PDT 24
Peak memory 218032 kb
Host smart-5aa8dc67-1d2a-4d1c-98ac-6d51da941d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999919423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1999919423
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1060348090
Short name T125
Test name
Test status
Simulation time 188695901 ps
CPU time 2.74 seconds
Started Jul 11 06:23:18 PM PDT 24
Finished Jul 11 06:23:33 PM PDT 24
Peak memory 213560 kb
Host smart-1e5d67b3-f611-4b59-a34f-3d600020cdeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060348090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1060348090
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3124176482
Short name T131
Test name
Test status
Simulation time 143530042 ps
CPU time 3.24 seconds
Started Jul 11 06:23:46 PM PDT 24
Finished Jul 11 06:23:55 PM PDT 24
Peak memory 222320 kb
Host smart-b98da4a3-99f5-4a2f-82bf-25159228eb0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124176482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3124176482
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1448544782
Short name T121
Test name
Test status
Simulation time 68679930 ps
CPU time 2.02 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:44 PM PDT 24
Peak memory 221860 kb
Host smart-853d2091-a727-4474-96e2-1ecd0c7a34c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448544782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1448544782
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2947702138
Short name T117
Test name
Test status
Simulation time 342719629 ps
CPU time 1.8 seconds
Started Jul 11 06:23:29 PM PDT 24
Finished Jul 11 06:23:42 PM PDT 24
Peak memory 217720 kb
Host smart-c1010771-e610-4970-983c-753a5b861548
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294770
2138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2947702138
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2048657162
Short name T122
Test name
Test status
Simulation time 22099164 ps
CPU time 1.5 seconds
Started Jul 11 06:23:14 PM PDT 24
Finished Jul 11 06:23:29 PM PDT 24
Peak memory 217516 kb
Host smart-60d3bb96-444f-4ab3-ac2d-861cc24cc788
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048657162 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2048657162
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1049131896
Short name T91
Test name
Test status
Simulation time 23614373871 ps
CPU time 448.2 seconds
Started Jul 11 05:21:43 PM PDT 24
Finished Jul 11 05:29:20 PM PDT 24
Peak memory 405612 kb
Host smart-f8cd11c5-6d03-457b-a762-ab349e1d5483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1049131896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.1049131896
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4263011347
Short name T78
Test name
Test status
Simulation time 19315476 ps
CPU time 0.98 seconds
Started Jul 11 05:20:27 PM PDT 24
Finished Jul 11 05:20:30 PM PDT 24
Peak memory 211840 kb
Host smart-78b1bb76-3541-4673-ae20-6ce2fae1c9c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263011347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.4263011347
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2782381806
Short name T119
Test name
Test status
Simulation time 110522017 ps
CPU time 1.84 seconds
Started Jul 11 06:23:45 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 221924 kb
Host smart-c7c34a75-46ca-4dd1-b093-84ae511d705c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782381806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2782381806
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3692878505
Short name T118
Test name
Test status
Simulation time 51336683 ps
CPU time 2.55 seconds
Started Jul 11 06:23:47 PM PDT 24
Finished Jul 11 06:23:56 PM PDT 24
Peak memory 217544 kb
Host smart-274d901b-c850-4426-9f77-2f4d74d795b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692878505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3692878505
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.807132879
Short name T143
Test name
Test status
Simulation time 162299025 ps
CPU time 1.93 seconds
Started Jul 11 06:23:42 PM PDT 24
Finished Jul 11 06:23:51 PM PDT 24
Peak memory 222040 kb
Host smart-82d182e2-edeb-49df-8b95-4f5cbc1d8054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807132879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.807132879
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2001065214
Short name T327
Test name
Test status
Simulation time 5463564333 ps
CPU time 45.6 seconds
Started Jul 11 05:19:52 PM PDT 24
Finished Jul 11 05:20:43 PM PDT 24
Peak memory 268460 kb
Host smart-3bc95898-5251-4346-8ffb-96c49a1c9870
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001065214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2001065214
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.995559012
Short name T223
Test name
Test status
Simulation time 18961974 ps
CPU time 0.9 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:18:54 PM PDT 24
Peak memory 208876 kb
Host smart-97be14e7-a8dd-40f9-b6dc-b34ce0a5ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995559012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.995559012
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2019759650
Short name T60
Test name
Test status
Simulation time 20654652 ps
CPU time 0.81 seconds
Started Jul 11 05:18:52 PM PDT 24
Finished Jul 11 05:18:57 PM PDT 24
Peak memory 208924 kb
Host smart-f522245d-f97b-4508-8fd9-85ff4804c40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019759650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2019759650
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2188461373
Short name T222
Test name
Test status
Simulation time 13800695 ps
CPU time 1.01 seconds
Started Jul 11 05:19:04 PM PDT 24
Finished Jul 11 05:19:08 PM PDT 24
Peak memory 209192 kb
Host smart-75de5e6e-a6ab-4c00-a717-3653f8f65942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188461373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2188461373
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1919501238
Short name T219
Test name
Test status
Simulation time 23142461 ps
CPU time 0.97 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:44 PM PDT 24
Peak memory 208832 kb
Host smart-6872784c-e3c5-489f-a6ad-d0eb3d7a4a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919501238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1919501238
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1899193602
Short name T33
Test name
Test status
Simulation time 1230675814 ps
CPU time 31.98 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:22:19 PM PDT 24
Peak memory 246004 kb
Host smart-62171392-21b9-4d83-8c89-6f8ea23c59d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899193602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1899193602
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2222273245
Short name T137
Test name
Test status
Simulation time 111485740 ps
CPU time 4.16 seconds
Started Jul 11 06:23:41 PM PDT 24
Finished Jul 11 06:23:52 PM PDT 24
Peak memory 217548 kb
Host smart-3960e81e-522a-4323-97e0-d82a70ce5799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222273245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2222273245
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.492387281
Short name T145
Test name
Test status
Simulation time 78351321 ps
CPU time 3.52 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:04 PM PDT 24
Peak memory 217484 kb
Host smart-c47ec9fe-a021-4c75-bdf9-e961a5681a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492387281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.492387281
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1841954488
Short name T140
Test name
Test status
Simulation time 473848043 ps
CPU time 2.07 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:36 PM PDT 24
Peak memory 221524 kb
Host smart-4097a2f8-a4db-4e3b-b6ff-9f2529de40da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841954488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1841954488
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2670200448
Short name T139
Test name
Test status
Simulation time 736887871 ps
CPU time 2.76 seconds
Started Jul 11 06:23:34 PM PDT 24
Finished Jul 11 06:23:47 PM PDT 24
Peak memory 222236 kb
Host smart-82d89b72-40d8-4d2d-924b-72384f210aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670200448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2670200448
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2530013522
Short name T40
Test name
Test status
Simulation time 1793194663 ps
CPU time 28.51 seconds
Started Jul 11 05:20:12 PM PDT 24
Finished Jul 11 05:20:43 PM PDT 24
Peak memory 218040 kb
Host smart-adee3250-09e6-4f99-b57e-2c3aa5d9ca14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530013522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2530013522
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.888616245
Short name T4
Test name
Test status
Simulation time 265736285 ps
CPU time 2.29 seconds
Started Jul 11 05:20:44 PM PDT 24
Finished Jul 11 05:20:48 PM PDT 24
Peak memory 218096 kb
Host smart-19efe3b8-a85d-4162-a05c-ef22db50cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888616245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.888616245
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3236883284
Short name T35
Test name
Test status
Simulation time 152533585 ps
CPU time 2.89 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:19:57 PM PDT 24
Peak memory 214816 kb
Host smart-2daabdb9-5e98-4164-8226-631a795231bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236883284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3236883284
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2793423392
Short name T918
Test name
Test status
Simulation time 102032303 ps
CPU time 1.6 seconds
Started Jul 11 06:23:12 PM PDT 24
Finished Jul 11 06:23:27 PM PDT 24
Peak memory 217688 kb
Host smart-bc473ef6-f6f5-47ab-bf28-5e475f173e6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793423392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2793423392
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1142792921
Short name T932
Test name
Test status
Simulation time 46934932 ps
CPU time 1.55 seconds
Started Jul 11 06:23:14 PM PDT 24
Finished Jul 11 06:23:29 PM PDT 24
Peak memory 209468 kb
Host smart-70f1316a-3129-44e4-9866-888651d176c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142792921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1142792921
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2640548172
Short name T976
Test name
Test status
Simulation time 26617691 ps
CPU time 1.27 seconds
Started Jul 11 06:23:11 PM PDT 24
Finished Jul 11 06:23:25 PM PDT 24
Peak memory 217748 kb
Host smart-5a0ec240-5d86-47df-b1f1-2ffad67b32bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640548172 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2640548172
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.238185586
Short name T909
Test name
Test status
Simulation time 33092283 ps
CPU time 1.14 seconds
Started Jul 11 06:23:15 PM PDT 24
Finished Jul 11 06:23:30 PM PDT 24
Peak memory 209356 kb
Host smart-24686882-8313-471f-a0bf-1da593d47779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238185586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.238185586
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.693495008
Short name T915
Test name
Test status
Simulation time 65136421 ps
CPU time 1.17 seconds
Started Jul 11 06:23:13 PM PDT 24
Finished Jul 11 06:23:28 PM PDT 24
Peak memory 208692 kb
Host smart-363704e1-0d25-4307-be3b-ec4a3f744dd6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693495008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.693495008
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.933104510
Short name T931
Test name
Test status
Simulation time 451908548 ps
CPU time 5.97 seconds
Started Jul 11 06:23:15 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 209080 kb
Host smart-079e4dc4-008b-4a7c-8d58-c24dffc91696
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933104510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.933104510
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1737769227
Short name T888
Test name
Test status
Simulation time 2218884039 ps
CPU time 45.94 seconds
Started Jul 11 06:23:13 PM PDT 24
Finished Jul 11 06:24:13 PM PDT 24
Peak memory 209100 kb
Host smart-7628af2b-b0c6-4bad-a486-526a954c4bde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737769227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1737769227
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1934741153
Short name T152
Test name
Test status
Simulation time 1383832031 ps
CPU time 3.04 seconds
Started Jul 11 06:23:17 PM PDT 24
Finished Jul 11 06:23:34 PM PDT 24
Peak memory 210844 kb
Host smart-c8c3ee09-d045-4b0e-a2f5-aef9e8c3552b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934741153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1934741153
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2506396960
Short name T887
Test name
Test status
Simulation time 231497877 ps
CPU time 2.17 seconds
Started Jul 11 06:23:14 PM PDT 24
Finished Jul 11 06:23:30 PM PDT 24
Peak memory 217424 kb
Host smart-681790dd-add2-429d-8d55-1e5238e8eb47
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506396960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2506396960
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.407162241
Short name T917
Test name
Test status
Simulation time 65010879 ps
CPU time 2.05 seconds
Started Jul 11 06:23:13 PM PDT 24
Finished Jul 11 06:23:29 PM PDT 24
Peak memory 217560 kb
Host smart-45ad60d1-e49c-42cf-9ab9-0bfad9b4b9fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407162241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.407162241
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.234208150
Short name T934
Test name
Test status
Simulation time 80878057 ps
CPU time 3.24 seconds
Started Jul 11 06:23:11 PM PDT 24
Finished Jul 11 06:23:29 PM PDT 24
Peak memory 217484 kb
Host smart-368fdf1c-bd49-4677-8503-f735197509f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234208150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.234208150
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2212085617
Short name T148
Test name
Test status
Simulation time 55536095 ps
CPU time 2.19 seconds
Started Jul 11 06:23:14 PM PDT 24
Finished Jul 11 06:23:30 PM PDT 24
Peak memory 221608 kb
Host smart-80b652d5-e369-44e6-adf2-6428dcc3080c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212085617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2212085617
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1567329124
Short name T201
Test name
Test status
Simulation time 102668585 ps
CPU time 1.34 seconds
Started Jul 11 06:23:17 PM PDT 24
Finished Jul 11 06:23:33 PM PDT 24
Peak memory 209464 kb
Host smart-ee7661db-93b7-4301-b7ef-7bfd45dd936f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567329124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1567329124
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3213419696
Short name T209
Test name
Test status
Simulation time 52885898 ps
CPU time 1.34 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:34 PM PDT 24
Peak memory 209256 kb
Host smart-ae9bca67-2693-4db6-96a2-7f4d3565ee60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213419696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3213419696
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1918310367
Short name T203
Test name
Test status
Simulation time 13898811 ps
CPU time 1.19 seconds
Started Jul 11 06:23:18 PM PDT 24
Finished Jul 11 06:23:32 PM PDT 24
Peak memory 210484 kb
Host smart-f582e441-6c8c-486a-a97f-fcbbf395c76e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918310367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1918310367
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2402973266
Short name T908
Test name
Test status
Simulation time 50736266 ps
CPU time 1 seconds
Started Jul 11 06:23:16 PM PDT 24
Finished Jul 11 06:23:31 PM PDT 24
Peak memory 217632 kb
Host smart-bb17dd04-93ab-42a4-b79c-348df468e847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402973266 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2402973266
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3406659329
Short name T967
Test name
Test status
Simulation time 14952423 ps
CPU time 0.87 seconds
Started Jul 11 06:23:18 PM PDT 24
Finished Jul 11 06:23:32 PM PDT 24
Peak memory 208964 kb
Host smart-2ace37fd-9246-42dd-b12d-57e961b0757b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406659329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3406659329
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4288204505
Short name T987
Test name
Test status
Simulation time 65697341 ps
CPU time 2.25 seconds
Started Jul 11 06:23:12 PM PDT 24
Finished Jul 11 06:23:29 PM PDT 24
Peak memory 208744 kb
Host smart-257277db-6d6d-4bf7-8b34-ceaccbe99ebd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288204505 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.4288204505
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.71827727
Short name T894
Test name
Test status
Simulation time 6236957430 ps
CPU time 9.35 seconds
Started Jul 11 06:23:14 PM PDT 24
Finished Jul 11 06:23:38 PM PDT 24
Peak memory 209308 kb
Host smart-146efb91-8869-4b39-956f-de11b2ee192e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71827727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.lc_ctrl_jtag_csr_aliasing.71827727
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3061854169
Short name T960
Test name
Test status
Simulation time 5531056800 ps
CPU time 13.79 seconds
Started Jul 11 06:23:15 PM PDT 24
Finished Jul 11 06:23:42 PM PDT 24
Peak memory 209136 kb
Host smart-afb27395-7537-4cd9-9218-1e9357396731
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061854169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3061854169
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2451335250
Short name T881
Test name
Test status
Simulation time 219528683 ps
CPU time 1.34 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 210704 kb
Host smart-c1e926bd-4350-47f5-8f92-d4d33f1c6f93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451335250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2451335250
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3150943924
Short name T927
Test name
Test status
Simulation time 1068766424 ps
CPU time 2.83 seconds
Started Jul 11 06:23:13 PM PDT 24
Finished Jul 11 06:23:30 PM PDT 24
Peak memory 218672 kb
Host smart-c0741368-7f0a-4b05-8615-3a9ca726ec30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315094
3924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3150943924
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4223228080
Short name T151
Test name
Test status
Simulation time 384998427 ps
CPU time 2.64 seconds
Started Jul 11 06:23:11 PM PDT 24
Finished Jul 11 06:23:28 PM PDT 24
Peak memory 209248 kb
Host smart-643b177c-1311-4a40-9bca-28f05288c330
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223228080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.4223228080
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1353533087
Short name T166
Test name
Test status
Simulation time 51272283 ps
CPU time 1.11 seconds
Started Jul 11 06:23:16 PM PDT 24
Finished Jul 11 06:23:30 PM PDT 24
Peak memory 209236 kb
Host smart-684c410a-b540-40a3-9a06-33aa31adf73b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353533087 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1353533087
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1603063521
Short name T215
Test name
Test status
Simulation time 27667302 ps
CPU time 1.01 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:34 PM PDT 24
Peak memory 217564 kb
Host smart-5a9ff21f-397a-4487-95f4-3bfd6e9e3723
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603063521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1603063521
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2142648767
Short name T974
Test name
Test status
Simulation time 87778913 ps
CPU time 2.96 seconds
Started Jul 11 06:23:16 PM PDT 24
Finished Jul 11 06:23:33 PM PDT 24
Peak memory 218520 kb
Host smart-576df509-3457-4114-9b84-ba433bec8203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142648767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2142648767
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4187768287
Short name T120
Test name
Test status
Simulation time 17837141 ps
CPU time 0.98 seconds
Started Jul 11 06:23:38 PM PDT 24
Finished Jul 11 06:23:48 PM PDT 24
Peak memory 217680 kb
Host smart-bb3c086b-b797-4f50-b12b-82450c850042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187768287 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4187768287
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2916840773
Short name T986
Test name
Test status
Simulation time 22748751 ps
CPU time 0.85 seconds
Started Jul 11 06:23:38 PM PDT 24
Finished Jul 11 06:23:47 PM PDT 24
Peak memory 209356 kb
Host smart-ed2e4d67-498b-489e-8775-1f088f4a1340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916840773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2916840773
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1176895831
Short name T896
Test name
Test status
Simulation time 81939969 ps
CPU time 2.15 seconds
Started Jul 11 06:23:38 PM PDT 24
Finished Jul 11 06:23:48 PM PDT 24
Peak memory 211632 kb
Host smart-499f2629-15b4-440b-bc5b-26072ce0b140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176895831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1176895831
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3751558194
Short name T130
Test name
Test status
Simulation time 228118611 ps
CPU time 1.87 seconds
Started Jul 11 06:23:36 PM PDT 24
Finished Jul 11 06:23:47 PM PDT 24
Peak memory 221492 kb
Host smart-cdb57e79-b7d3-4a27-955e-7b53d0e09658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751558194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3751558194
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4191581207
Short name T928
Test name
Test status
Simulation time 24288277 ps
CPU time 1.86 seconds
Started Jul 11 06:23:42 PM PDT 24
Finished Jul 11 06:23:51 PM PDT 24
Peak memory 217552 kb
Host smart-397450a4-560e-4df8-9f50-a64f609a302a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191581207 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4191581207
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2778108498
Short name T968
Test name
Test status
Simulation time 13449865 ps
CPU time 1.03 seconds
Started Jul 11 06:23:38 PM PDT 24
Finished Jul 11 06:23:48 PM PDT 24
Peak memory 217512 kb
Host smart-91f91c72-9179-43db-95c2-68850a57b9e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778108498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2778108498
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.828274787
Short name T923
Test name
Test status
Simulation time 46474287 ps
CPU time 2.04 seconds
Started Jul 11 06:23:40 PM PDT 24
Finished Jul 11 06:23:50 PM PDT 24
Peak memory 209296 kb
Host smart-8baf41c8-df33-4e62-912e-4cd9ed23127e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828274787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.828274787
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1012435803
Short name T957
Test name
Test status
Simulation time 81570864 ps
CPU time 3.5 seconds
Started Jul 11 06:23:36 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 217492 kb
Host smart-1ba5d4fb-24de-4feb-b198-65b3025ef7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012435803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1012435803
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3352751946
Short name T980
Test name
Test status
Simulation time 119742140 ps
CPU time 1.06 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 217560 kb
Host smart-f1ea5ec0-7c97-41ad-abf3-a242518c46cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352751946 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3352751946
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.845076122
Short name T206
Test name
Test status
Simulation time 19175115 ps
CPU time 0.88 seconds
Started Jul 11 06:23:36 PM PDT 24
Finished Jul 11 06:23:46 PM PDT 24
Peak memory 209356 kb
Host smart-a4eeba2b-10a9-404c-bf0b-5a642cf21214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845076122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.845076122
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1366265239
Short name T940
Test name
Test status
Simulation time 26161506 ps
CPU time 1.05 seconds
Started Jul 11 06:23:38 PM PDT 24
Finished Jul 11 06:23:47 PM PDT 24
Peak memory 209360 kb
Host smart-c0ba8b99-38ab-4ce6-855b-997a904e4bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366265239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1366265239
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1037154166
Short name T961
Test name
Test status
Simulation time 72237437 ps
CPU time 3.06 seconds
Started Jul 11 06:23:39 PM PDT 24
Finished Jul 11 06:23:50 PM PDT 24
Peak memory 217572 kb
Host smart-cd468c38-be0b-4149-b26c-b22c6af53844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037154166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1037154166
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.115788420
Short name T900
Test name
Test status
Simulation time 210995906 ps
CPU time 2.74 seconds
Started Jul 11 06:23:37 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 217616 kb
Host smart-a3a7bfb0-c649-46c3-9d99-6094a667e95e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115788420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.115788420
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3224243913
Short name T919
Test name
Test status
Simulation time 34676491 ps
CPU time 0.99 seconds
Started Jul 11 06:23:41 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 217472 kb
Host smart-a5f21c29-4d99-4782-8e86-33b8ef815342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224243913 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3224243913
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1775368511
Short name T939
Test name
Test status
Simulation time 48219132 ps
CPU time 1.02 seconds
Started Jul 11 06:23:45 PM PDT 24
Finished Jul 11 06:23:52 PM PDT 24
Peak memory 217560 kb
Host smart-9bceefff-307d-4582-a8d8-7fda5fba6e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775368511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1775368511
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1266070570
Short name T216
Test name
Test status
Simulation time 24600473 ps
CPU time 1.06 seconds
Started Jul 11 06:23:44 PM PDT 24
Finished Jul 11 06:23:52 PM PDT 24
Peak memory 209464 kb
Host smart-2a9e729a-195b-444c-8988-476858bc0df6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266070570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1266070570
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2596244445
Short name T126
Test name
Test status
Simulation time 628883412 ps
CPU time 3.14 seconds
Started Jul 11 06:23:43 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 217492 kb
Host smart-d2190ec3-4cc0-4bf2-9339-1e961066485a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596244445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2596244445
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2669132014
Short name T144
Test name
Test status
Simulation time 401569269 ps
CPU time 4.01 seconds
Started Jul 11 06:23:41 PM PDT 24
Finished Jul 11 06:23:52 PM PDT 24
Peak memory 217620 kb
Host smart-58a9795a-2be7-45f1-96ad-d50b5a46e8c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669132014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2669132014
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1858017095
Short name T938
Test name
Test status
Simulation time 24538905 ps
CPU time 1.2 seconds
Started Jul 11 06:23:40 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 221048 kb
Host smart-fb0e7374-aa73-40de-a5d0-2fab881d3a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858017095 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1858017095
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3189594150
Short name T937
Test name
Test status
Simulation time 15068342 ps
CPU time 1.07 seconds
Started Jul 11 06:23:40 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 208900 kb
Host smart-a46cc3f6-d809-4852-b5dd-16205dd3ea64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189594150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3189594150
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.360892412
Short name T951
Test name
Test status
Simulation time 44917946 ps
CPU time 1 seconds
Started Jul 11 06:23:43 PM PDT 24
Finished Jul 11 06:23:52 PM PDT 24
Peak memory 209432 kb
Host smart-62f64534-7249-40b8-9d0e-955da9696284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360892412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.360892412
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.384170635
Short name T977
Test name
Test status
Simulation time 437592902 ps
CPU time 4.55 seconds
Started Jul 11 06:23:42 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 217692 kb
Host smart-f46680c2-74d6-4137-86ad-e430eb62451c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384170635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.384170635
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4189618983
Short name T955
Test name
Test status
Simulation time 16107273 ps
CPU time 1.27 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 218452 kb
Host smart-a9d554e3-e05a-4b76-8b33-0a173dffb47a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189618983 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.4189618983
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.310694517
Short name T202
Test name
Test status
Simulation time 42562643 ps
CPU time 0.9 seconds
Started Jul 11 06:23:42 PM PDT 24
Finished Jul 11 06:23:50 PM PDT 24
Peak memory 209352 kb
Host smart-1cac1a24-9207-4fd5-9fd0-0644de9d28ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310694517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.310694517
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2994831176
Short name T991
Test name
Test status
Simulation time 105747942 ps
CPU time 1.4 seconds
Started Jul 11 06:23:47 PM PDT 24
Finished Jul 11 06:23:55 PM PDT 24
Peak memory 209324 kb
Host smart-4d534177-8ef0-4c29-9b8c-34211f5b67e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994831176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2994831176
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1082487123
Short name T134
Test name
Test status
Simulation time 110758524 ps
CPU time 4.53 seconds
Started Jul 11 06:23:42 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 217504 kb
Host smart-4f87881a-7b71-4f6c-83b2-faa43bcb2cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082487123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1082487123
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3721416098
Short name T135
Test name
Test status
Simulation time 60972819 ps
CPU time 1.91 seconds
Started Jul 11 06:23:44 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 212956 kb
Host smart-e8a1a981-5de1-4d1a-b0b6-e557c448c1fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721416098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3721416098
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1189801307
Short name T920
Test name
Test status
Simulation time 67722797 ps
CPU time 1.01 seconds
Started Jul 11 06:23:44 PM PDT 24
Finished Jul 11 06:23:52 PM PDT 24
Peak memory 218700 kb
Host smart-96c2eb98-8ee2-4882-b495-7c2dba7c4895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189801307 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1189801307
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3791902959
Short name T876
Test name
Test status
Simulation time 33994699 ps
CPU time 0.97 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 209288 kb
Host smart-2cc61177-d58b-4c81-8688-c61fb9f4f894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791902959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3791902959
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3832510414
Short name T213
Test name
Test status
Simulation time 29425425 ps
CPU time 1.11 seconds
Started Jul 11 06:23:41 PM PDT 24
Finished Jul 11 06:23:50 PM PDT 24
Peak memory 209472 kb
Host smart-53f3ac1b-9501-424a-9cfc-945160d2ffbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832510414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3832510414
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1806433604
Short name T113
Test name
Test status
Simulation time 200303104 ps
CPU time 2.9 seconds
Started Jul 11 06:23:43 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 217576 kb
Host smart-500f26ca-18d6-48d6-b9da-c9950d8a4be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806433604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1806433604
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2429060879
Short name T141
Test name
Test status
Simulation time 368903545 ps
CPU time 2.67 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 221772 kb
Host smart-272de245-2920-4f69-b26d-633232e8babe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429060879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2429060879
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3166286759
Short name T167
Test name
Test status
Simulation time 74109248 ps
CPU time 1.66 seconds
Started Jul 11 06:23:49 PM PDT 24
Finished Jul 11 06:23:58 PM PDT 24
Peak memory 219168 kb
Host smart-77e618ad-4ae1-489b-a361-da514d277e5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166286759 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3166286759
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1959561964
Short name T211
Test name
Test status
Simulation time 14294855 ps
CPU time 1.09 seconds
Started Jul 11 06:23:46 PM PDT 24
Finished Jul 11 06:23:55 PM PDT 24
Peak memory 209080 kb
Host smart-7fb9a06f-9212-434d-941a-6e66c6f78eac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959561964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1959561964
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2875338407
Short name T212
Test name
Test status
Simulation time 40365484 ps
CPU time 1.33 seconds
Started Jul 11 06:23:48 PM PDT 24
Finished Jul 11 06:23:57 PM PDT 24
Peak memory 209440 kb
Host smart-1de56c47-704f-4a85-90cb-1fc6e8959ac5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875338407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2875338407
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2661586738
Short name T902
Test name
Test status
Simulation time 964452077 ps
CPU time 2.98 seconds
Started Jul 11 06:23:42 PM PDT 24
Finished Jul 11 06:23:52 PM PDT 24
Peak memory 217472 kb
Host smart-8331d0c9-85b2-404f-b6da-eb69b1d9d054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661586738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2661586738
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3331714826
Short name T983
Test name
Test status
Simulation time 180422962 ps
CPU time 1.64 seconds
Started Jul 11 06:23:47 PM PDT 24
Finished Jul 11 06:23:56 PM PDT 24
Peak memory 217564 kb
Host smart-4bd1067a-0752-4328-9953-80e42674e463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331714826 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3331714826
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3863941528
Short name T907
Test name
Test status
Simulation time 18345826 ps
CPU time 0.94 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 208940 kb
Host smart-1c2de2a1-d86f-4b13-94f0-de3401a724a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863941528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3863941528
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2296802196
Short name T973
Test name
Test status
Simulation time 21957722 ps
CPU time 1.52 seconds
Started Jul 11 06:23:45 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 217612 kb
Host smart-3d0c4a39-5ffe-4205-aa36-bc4956c0ea83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296802196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2296802196
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4027402930
Short name T916
Test name
Test status
Simulation time 33772261 ps
CPU time 2.47 seconds
Started Jul 11 06:23:46 PM PDT 24
Finished Jul 11 06:23:55 PM PDT 24
Peak memory 218544 kb
Host smart-ddb38cd1-d49f-4232-8f03-3d88abf10103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027402930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4027402930
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4164440400
Short name T978
Test name
Test status
Simulation time 45810086 ps
CPU time 1.76 seconds
Started Jul 11 06:23:47 PM PDT 24
Finished Jul 11 06:23:57 PM PDT 24
Peak memory 217672 kb
Host smart-03709689-88a5-455f-990d-bf564b4fada7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164440400 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.4164440400
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.184375395
Short name T892
Test name
Test status
Simulation time 15939097 ps
CPU time 1.12 seconds
Started Jul 11 06:23:48 PM PDT 24
Finished Jul 11 06:23:56 PM PDT 24
Peak memory 209100 kb
Host smart-4e7b9cd0-a2b0-4566-8a89-38910b3ee074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184375395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.184375395
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3517495474
Short name T956
Test name
Test status
Simulation time 159186283 ps
CPU time 1.41 seconds
Started Jul 11 06:23:48 PM PDT 24
Finished Jul 11 06:23:56 PM PDT 24
Peak memory 217640 kb
Host smart-44f5753a-ea46-4da4-b9a8-78a6068ba61d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517495474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3517495474
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.411891604
Short name T115
Test name
Test status
Simulation time 114455774 ps
CPU time 1.41 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 217556 kb
Host smart-5d33faba-42a0-4d73-8c87-6afeda37981e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411891604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.411891604
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.162918293
Short name T921
Test name
Test status
Simulation time 68173751 ps
CPU time 0.96 seconds
Started Jul 11 06:23:18 PM PDT 24
Finished Jul 11 06:23:32 PM PDT 24
Peak memory 209356 kb
Host smart-34d86cd7-1f06-4d2f-bd0a-e0bff9a9a40a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162918293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.162918293
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3583343350
Short name T911
Test name
Test status
Simulation time 97677268 ps
CPU time 1.92 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:37 PM PDT 24
Peak memory 209348 kb
Host smart-17bb285c-4569-4c03-a1b1-3dc6b032251f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583343350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3583343350
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3557114328
Short name T905
Test name
Test status
Simulation time 65652836 ps
CPU time 1.24 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:34 PM PDT 24
Peak memory 218040 kb
Host smart-a7a5041a-9369-46b8-97fa-64ecc438737a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557114328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3557114328
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.266232976
Short name T136
Test name
Test status
Simulation time 58563750 ps
CPU time 0.99 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:36 PM PDT 24
Peak memory 217696 kb
Host smart-4fd73d8a-56a1-4884-8b18-3022cf77ce3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266232976 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.266232976
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2407259649
Short name T872
Test name
Test status
Simulation time 32941212 ps
CPU time 1.09 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:34 PM PDT 24
Peak memory 209324 kb
Host smart-fbd357ab-c6b5-448a-a207-69e28d9e7815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407259649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2407259649
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1110935380
Short name T944
Test name
Test status
Simulation time 65331559 ps
CPU time 1.32 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:36 PM PDT 24
Peak memory 209216 kb
Host smart-2b8c1d38-da81-485d-b2c2-34cc17ac4586
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110935380 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1110935380
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1377619025
Short name T966
Test name
Test status
Simulation time 1643454635 ps
CPU time 8.95 seconds
Started Jul 11 06:23:18 PM PDT 24
Finished Jul 11 06:23:40 PM PDT 24
Peak memory 217160 kb
Host smart-d5cb9c29-cdaa-4d9c-975c-97caf412b14f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377619025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1377619025
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3184849862
Short name T874
Test name
Test status
Simulation time 3011826051 ps
CPU time 19.88 seconds
Started Jul 11 06:23:17 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 209248 kb
Host smart-58d8a499-7046-440e-b24e-349fc97e03f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184849862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3184849862
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.433785350
Short name T873
Test name
Test status
Simulation time 118754046 ps
CPU time 3.61 seconds
Started Jul 11 06:23:19 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 217464 kb
Host smart-5aa4b0c5-301d-497f-a2c3-9b9b2ab4bbb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433785350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.433785350
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1879019196
Short name T913
Test name
Test status
Simulation time 339478180 ps
CPU time 2.22 seconds
Started Jul 11 06:23:17 PM PDT 24
Finished Jul 11 06:23:33 PM PDT 24
Peak memory 217632 kb
Host smart-0a25e099-c33b-4fdb-a830-3ef54558f167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187901
9196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1879019196
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3856272782
Short name T954
Test name
Test status
Simulation time 135968571 ps
CPU time 1.4 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 209292 kb
Host smart-ccb87216-3f14-423a-8a5c-e90b39477be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856272782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3856272782
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.880517893
Short name T970
Test name
Test status
Simulation time 856045698 ps
CPU time 1.51 seconds
Started Jul 11 06:23:25 PM PDT 24
Finished Jul 11 06:23:39 PM PDT 24
Peak memory 211508 kb
Host smart-6030c237-da6a-4574-b95a-956b9b838b4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880517893 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.880517893
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2493739520
Short name T929
Test name
Test status
Simulation time 41319255 ps
CPU time 1.43 seconds
Started Jul 11 06:23:26 PM PDT 24
Finished Jul 11 06:23:39 PM PDT 24
Peak memory 211448 kb
Host smart-a1ec2249-25bb-4859-b2b1-94fc615bfed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493739520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2493739520
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.463683751
Short name T890
Test name
Test status
Simulation time 56823611 ps
CPU time 2.02 seconds
Started Jul 11 06:23:17 PM PDT 24
Finished Jul 11 06:23:31 PM PDT 24
Peak memory 217572 kb
Host smart-c7e16ab8-0597-499a-8f39-38fdfd9bb841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463683751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.463683751
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2021349578
Short name T200
Test name
Test status
Simulation time 39407439 ps
CPU time 1.39 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:36 PM PDT 24
Peak memory 209420 kb
Host smart-182cd064-b535-4e70-829a-368876465998
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021349578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2021349578
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3835456712
Short name T149
Test name
Test status
Simulation time 166965800 ps
CPU time 1.32 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 209348 kb
Host smart-0e891ac6-049b-44c2-880b-daf69e25dbc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835456712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3835456712
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1954721622
Short name T205
Test name
Test status
Simulation time 44437610 ps
CPU time 1.03 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:43 PM PDT 24
Peak memory 209636 kb
Host smart-c0f852d7-408d-4b97-9020-403511534634
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954721622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1954721622
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4293239864
Short name T132
Test name
Test status
Simulation time 165264590 ps
CPU time 1.1 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 219504 kb
Host smart-ce14a862-e62d-41e0-a2ea-3eaaa6a1f855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293239864 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.4293239864
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.713922601
Short name T985
Test name
Test status
Simulation time 162031938 ps
CPU time 1.06 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:34 PM PDT 24
Peak memory 209356 kb
Host smart-aeba7ee8-9c45-43b6-b634-68d58c788b5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713922601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.713922601
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3817423966
Short name T153
Test name
Test status
Simulation time 83053447 ps
CPU time 1.35 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 208720 kb
Host smart-381169c7-ba62-41f2-9e90-06332f129ac1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817423966 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3817423966
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4238058552
Short name T150
Test name
Test status
Simulation time 2595551083 ps
CPU time 6.86 seconds
Started Jul 11 06:23:17 PM PDT 24
Finished Jul 11 06:23:38 PM PDT 24
Peak memory 217388 kb
Host smart-5b490081-85a0-468b-9ee6-60cd146924ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238058552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4238058552
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2657557923
Short name T870
Test name
Test status
Simulation time 1870814164 ps
CPU time 21.44 seconds
Started Jul 11 06:23:16 PM PDT 24
Finished Jul 11 06:23:51 PM PDT 24
Peak memory 217080 kb
Host smart-7caef849-4a91-451b-90dd-7563596887aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657557923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2657557923
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1219490392
Short name T965
Test name
Test status
Simulation time 364449014 ps
CPU time 2.76 seconds
Started Jul 11 06:23:18 PM PDT 24
Finished Jul 11 06:23:34 PM PDT 24
Peak memory 217488 kb
Host smart-0cbf0c51-4d5f-40a3-9a0e-929303320d78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219490392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1219490392
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3742702723
Short name T891
Test name
Test status
Simulation time 180559666 ps
CPU time 2.75 seconds
Started Jul 11 06:23:18 PM PDT 24
Finished Jul 11 06:23:33 PM PDT 24
Peak memory 218652 kb
Host smart-f263de73-87d0-4c3c-b364-4741cc5d3353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374270
2723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3742702723
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2567385991
Short name T897
Test name
Test status
Simulation time 72976562 ps
CPU time 1.57 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:36 PM PDT 24
Peak memory 209288 kb
Host smart-ba1e7168-af6e-4076-a059-f0d6f677761e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567385991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2567385991
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3401489464
Short name T924
Test name
Test status
Simulation time 15335170 ps
CPU time 1.01 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 209364 kb
Host smart-191f5b01-81ae-4d1c-8fe3-6b0f4da16035
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401489464 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3401489464
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3322272414
Short name T975
Test name
Test status
Simulation time 132461791 ps
CPU time 1.5 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:36 PM PDT 24
Peak memory 217668 kb
Host smart-85d6a1b0-492c-486e-8d00-c5439240b28c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322272414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3322272414
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.866208366
Short name T889
Test name
Test status
Simulation time 252597960 ps
CPU time 2.58 seconds
Started Jul 11 06:23:24 PM PDT 24
Finished Jul 11 06:23:38 PM PDT 24
Peak memory 217500 kb
Host smart-0245ba4a-9290-48fa-99f1-f78c808b20c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866208366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.866208366
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1523057591
Short name T146
Test name
Test status
Simulation time 296316799 ps
CPU time 2.94 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:37 PM PDT 24
Peak memory 217560 kb
Host smart-a7e48356-dd39-40c6-b42c-4b49c4340796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523057591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1523057591
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2376407158
Short name T208
Test name
Test status
Simulation time 17964226 ps
CPU time 1.13 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 209360 kb
Host smart-d681cd28-c392-4ee3-bb6c-c83fb6721ab8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376407158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2376407158
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2198922062
Short name T875
Test name
Test status
Simulation time 101670840 ps
CPU time 1.65 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 217288 kb
Host smart-e37d474f-d034-4a7f-aa6f-eb4638ed2165
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198922062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2198922062
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1719102852
Short name T129
Test name
Test status
Simulation time 15174617 ps
CPU time 1.18 seconds
Started Jul 11 06:23:23 PM PDT 24
Finished Jul 11 06:23:36 PM PDT 24
Peak memory 209804 kb
Host smart-5503b8a5-6250-460a-83fe-d16a7a5e998d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719102852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1719102852
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.882620694
Short name T914
Test name
Test status
Simulation time 56912193 ps
CPU time 1.53 seconds
Started Jul 11 06:23:23 PM PDT 24
Finished Jul 11 06:23:37 PM PDT 24
Peak memory 223156 kb
Host smart-38bc3e7d-06b5-4052-85f4-47e099a2838b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882620694 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.882620694
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2716054118
Short name T969
Test name
Test status
Simulation time 12779307 ps
CPU time 0.89 seconds
Started Jul 11 06:23:30 PM PDT 24
Finished Jul 11 06:23:42 PM PDT 24
Peak memory 209344 kb
Host smart-28d3caf7-d2aa-4919-958c-d9b60ae58ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716054118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2716054118
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2647605495
Short name T868
Test name
Test status
Simulation time 98566160 ps
CPU time 2.8 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:37 PM PDT 24
Peak memory 208720 kb
Host smart-65350bb1-0ff1-4954-972c-23aabb7ae4b3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647605495 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2647605495
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.766015021
Short name T947
Test name
Test status
Simulation time 370531629 ps
CPU time 5.88 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:39 PM PDT 24
Peak memory 209084 kb
Host smart-db24663a-69b2-418b-8477-50c13b0bebcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766015021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.766015021
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.785472106
Short name T127
Test name
Test status
Simulation time 3297287475 ps
CPU time 28.34 seconds
Started Jul 11 06:23:23 PM PDT 24
Finished Jul 11 06:24:04 PM PDT 24
Peak memory 209376 kb
Host smart-2bf3cdbd-6099-4f9a-bc2c-5414a9bf3681
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785472106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.785472106
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1453695019
Short name T128
Test name
Test status
Simulation time 138087318 ps
CPU time 2.23 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:37 PM PDT 24
Peak memory 217488 kb
Host smart-19b0c9b7-c746-4122-87be-b70f00471608
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453695019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1453695019
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3625635519
Short name T952
Test name
Test status
Simulation time 225816845 ps
CPU time 2.75 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:36 PM PDT 24
Peak memory 217620 kb
Host smart-a54594c2-7644-4099-b8c9-51a093e230b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362563
5519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3625635519
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.757113484
Short name T903
Test name
Test status
Simulation time 39401416 ps
CPU time 1.66 seconds
Started Jul 11 06:23:21 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 217444 kb
Host smart-3bd692ca-3e49-43d1-b229-507c3832e3cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757113484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.757113484
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.984817280
Short name T930
Test name
Test status
Simulation time 16345922 ps
CPU time 1.2 seconds
Started Jul 11 06:23:20 PM PDT 24
Finished Jul 11 06:23:35 PM PDT 24
Peak memory 209460 kb
Host smart-6863748e-28b5-4ec4-a9fe-a44c4d1ad611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984817280 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.984817280
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.734647114
Short name T959
Test name
Test status
Simulation time 100497584 ps
CPU time 2.08 seconds
Started Jul 11 06:23:29 PM PDT 24
Finished Jul 11 06:23:41 PM PDT 24
Peak memory 209356 kb
Host smart-b827f063-8e01-4dfc-8e41-82de7365a99d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734647114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.734647114
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2145291888
Short name T124
Test name
Test status
Simulation time 28133900 ps
CPU time 1.99 seconds
Started Jul 11 06:23:22 PM PDT 24
Finished Jul 11 06:23:37 PM PDT 24
Peak memory 217756 kb
Host smart-3ffdf124-d211-4b39-8e21-8cbbd06d3ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145291888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2145291888
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.444612186
Short name T904
Test name
Test status
Simulation time 145990667 ps
CPU time 1.15 seconds
Started Jul 11 06:23:29 PM PDT 24
Finished Jul 11 06:23:42 PM PDT 24
Peak memory 220512 kb
Host smart-9d64c56e-6a00-462c-a34b-027b243180ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444612186 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.444612186
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3675203090
Short name T207
Test name
Test status
Simulation time 48844893 ps
CPU time 0.88 seconds
Started Jul 11 06:23:28 PM PDT 24
Finished Jul 11 06:23:40 PM PDT 24
Peak memory 209292 kb
Host smart-4e79ae09-e219-43f9-b667-29473bee0fcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675203090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3675203090
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1684347218
Short name T910
Test name
Test status
Simulation time 25973157 ps
CPU time 0.97 seconds
Started Jul 11 06:23:30 PM PDT 24
Finished Jul 11 06:23:41 PM PDT 24
Peak memory 209152 kb
Host smart-7e2dcdfa-49d4-4670-8010-c66b56637320
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684347218 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1684347218
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4201960848
Short name T941
Test name
Test status
Simulation time 439973787 ps
CPU time 10.65 seconds
Started Jul 11 06:23:29 PM PDT 24
Finished Jul 11 06:23:50 PM PDT 24
Peak memory 217148 kb
Host smart-8374d7e3-2ac8-4ba8-a9bf-8a02a375ac4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201960848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4201960848
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1702481885
Short name T878
Test name
Test status
Simulation time 5026896007 ps
CPU time 26.45 seconds
Started Jul 11 06:23:27 PM PDT 24
Finished Jul 11 06:24:05 PM PDT 24
Peak memory 209376 kb
Host smart-b6dc4256-ea87-4978-9c0e-2d2ec6be61f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702481885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1702481885
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.548311066
Short name T871
Test name
Test status
Simulation time 1857778669 ps
CPU time 1.91 seconds
Started Jul 11 06:23:28 PM PDT 24
Finished Jul 11 06:23:41 PM PDT 24
Peak memory 210928 kb
Host smart-dc4ac430-8e54-4fec-ba70-213dc40fb5fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548311066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.548311066
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3034326258
Short name T882
Test name
Test status
Simulation time 212095258 ps
CPU time 1.24 seconds
Started Jul 11 06:23:26 PM PDT 24
Finished Jul 11 06:23:39 PM PDT 24
Peak memory 209252 kb
Host smart-ea7c5c5f-57ea-4a5d-9f1a-aa6c43f2d9fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034326258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3034326258
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.552483076
Short name T925
Test name
Test status
Simulation time 14809743 ps
CPU time 1.02 seconds
Started Jul 11 06:23:27 PM PDT 24
Finished Jul 11 06:23:40 PM PDT 24
Peak memory 209364 kb
Host smart-3a697423-2a06-44e8-a8b0-f184ec0133af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552483076 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.552483076
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4167404194
Short name T949
Test name
Test status
Simulation time 33810244 ps
CPU time 1.27 seconds
Started Jul 11 06:23:30 PM PDT 24
Finished Jul 11 06:23:42 PM PDT 24
Peak memory 217556 kb
Host smart-34fdf67e-1b9f-4acf-961a-97ddf8e4feda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167404194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.4167404194
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1681421286
Short name T979
Test name
Test status
Simulation time 23333786 ps
CPU time 1.47 seconds
Started Jul 11 06:23:29 PM PDT 24
Finished Jul 11 06:23:42 PM PDT 24
Peak memory 217568 kb
Host smart-b2ab135f-7311-4198-8d14-9c0ce9ba208a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681421286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1681421286
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2637660864
Short name T142
Test name
Test status
Simulation time 306411365 ps
CPU time 2.09 seconds
Started Jul 11 06:23:27 PM PDT 24
Finished Jul 11 06:23:40 PM PDT 24
Peak memory 222244 kb
Host smart-400ec8c6-56e3-4fbc-8041-f6b1177fe146
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637660864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2637660864
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4087407884
Short name T990
Test name
Test status
Simulation time 83389256 ps
CPU time 1.31 seconds
Started Jul 11 06:23:32 PM PDT 24
Finished Jul 11 06:23:44 PM PDT 24
Peak memory 217648 kb
Host smart-d87ec7be-96ed-4e25-822a-c3b8d477283a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087407884 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.4087407884
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4251877286
Short name T210
Test name
Test status
Simulation time 27317906 ps
CPU time 0.94 seconds
Started Jul 11 06:23:29 PM PDT 24
Finished Jul 11 06:23:40 PM PDT 24
Peak memory 209356 kb
Host smart-752e6852-8ac1-4262-ac82-d823efd4c301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251877286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4251877286
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3922486880
Short name T886
Test name
Test status
Simulation time 58809109 ps
CPU time 1.19 seconds
Started Jul 11 06:23:27 PM PDT 24
Finished Jul 11 06:23:39 PM PDT 24
Peak memory 209240 kb
Host smart-15a6601e-2c0d-46d2-865b-f72d8472d493
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922486880 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3922486880
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.139015246
Short name T898
Test name
Test status
Simulation time 375592182 ps
CPU time 4.08 seconds
Started Jul 11 06:23:34 PM PDT 24
Finished Jul 11 06:23:48 PM PDT 24
Peak memory 208892 kb
Host smart-ec6ab0c4-0449-41e3-8bc4-cc703c194275
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139015246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.139015246
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.909340105
Short name T989
Test name
Test status
Simulation time 2562649814 ps
CPU time 14.73 seconds
Started Jul 11 06:23:30 PM PDT 24
Finished Jul 11 06:23:55 PM PDT 24
Peak memory 209364 kb
Host smart-962d6e8b-e162-4841-87d8-bbeba6aef7a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909340105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.909340105
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3333342437
Short name T958
Test name
Test status
Simulation time 106030910 ps
CPU time 3.21 seconds
Started Jul 11 06:23:30 PM PDT 24
Finished Jul 11 06:23:44 PM PDT 24
Peak memory 210804 kb
Host smart-07d71ff8-a736-4872-aa6d-6be420189dbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333342437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3333342437
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3296458855
Short name T912
Test name
Test status
Simulation time 198068652 ps
CPU time 1.95 seconds
Started Jul 11 06:23:27 PM PDT 24
Finished Jul 11 06:23:40 PM PDT 24
Peak memory 217544 kb
Host smart-1726ee25-e71b-4696-a4d0-f09a4746d660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329645
8855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3296458855
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3726775403
Short name T950
Test name
Test status
Simulation time 36519233 ps
CPU time 1.56 seconds
Started Jul 11 06:23:27 PM PDT 24
Finished Jul 11 06:23:40 PM PDT 24
Peak memory 217420 kb
Host smart-1941e290-e372-4722-af32-255f0557fc0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726775403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3726775403
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1515898185
Short name T123
Test name
Test status
Simulation time 47959847 ps
CPU time 2.06 seconds
Started Jul 11 06:23:28 PM PDT 24
Finished Jul 11 06:23:41 PM PDT 24
Peak memory 209468 kb
Host smart-11900a99-a797-48de-a5a3-ad6b23406459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515898185 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1515898185
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4162135713
Short name T942
Test name
Test status
Simulation time 26441427 ps
CPU time 1.42 seconds
Started Jul 11 06:23:34 PM PDT 24
Finished Jul 11 06:23:45 PM PDT 24
Peak memory 209272 kb
Host smart-0fcf59f1-a59e-47f2-8524-f8572a4597bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162135713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.4162135713
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1771303122
Short name T922
Test name
Test status
Simulation time 31467400 ps
CPU time 1.83 seconds
Started Jul 11 06:23:28 PM PDT 24
Finished Jul 11 06:23:41 PM PDT 24
Peak memory 217640 kb
Host smart-e6806dff-9dd7-4242-a714-040d4abfc4a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771303122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1771303122
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1427558097
Short name T147
Test name
Test status
Simulation time 65240129 ps
CPU time 2.08 seconds
Started Jul 11 06:23:30 PM PDT 24
Finished Jul 11 06:23:43 PM PDT 24
Peak memory 221900 kb
Host smart-674f2750-9789-45ae-bcf7-90c3b8c8f609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427558097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1427558097
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3807743062
Short name T933
Test name
Test status
Simulation time 109868122 ps
CPU time 1.58 seconds
Started Jul 11 06:23:39 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 218744 kb
Host smart-d621127b-5362-4328-ac3f-b3f41a062ad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807743062 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3807743062
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1219430228
Short name T214
Test name
Test status
Simulation time 18764067 ps
CPU time 1.05 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:43 PM PDT 24
Peak memory 217524 kb
Host smart-d1f6888a-0a41-4562-9c51-cab4d6405ae5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219430228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1219430228
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1441490966
Short name T869
Test name
Test status
Simulation time 165059873 ps
CPU time 1.65 seconds
Started Jul 11 06:23:30 PM PDT 24
Finished Jul 11 06:23:42 PM PDT 24
Peak memory 209200 kb
Host smart-3346d1a0-2712-4f90-8401-15764d81af93
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441490966 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1441490966
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3251457867
Short name T885
Test name
Test status
Simulation time 14883336856 ps
CPU time 17.71 seconds
Started Jul 11 06:23:32 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 209560 kb
Host smart-b30b8f80-3b93-4e0b-bc5e-a874e164e27b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251457867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3251457867
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.66467443
Short name T880
Test name
Test status
Simulation time 355902955 ps
CPU time 4.78 seconds
Started Jul 11 06:23:34 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 217208 kb
Host smart-07e7b0d6-d210-4a46-8d9c-2657540fab06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66467443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.66467443
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2289381212
Short name T936
Test name
Test status
Simulation time 611737583 ps
CPU time 2.77 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:45 PM PDT 24
Peak memory 217548 kb
Host smart-9ef7ae09-0da5-40bf-ad48-abee918de84f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289381212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2289381212
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2619370141
Short name T926
Test name
Test status
Simulation time 311702795 ps
CPU time 3.14 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:45 PM PDT 24
Peak memory 218580 kb
Host smart-7359626d-fe3c-4440-ae47-16c433ec325a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261937
0141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2619370141
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4168062785
Short name T883
Test name
Test status
Simulation time 39407232 ps
CPU time 1.6 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:43 PM PDT 24
Peak memory 209284 kb
Host smart-d79b0b6e-0c95-4782-850d-a99427beb1af
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168062785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.4168062785
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1085479690
Short name T945
Test name
Test status
Simulation time 96400215 ps
CPU time 1.18 seconds
Started Jul 11 06:23:32 PM PDT 24
Finished Jul 11 06:23:44 PM PDT 24
Peak memory 209348 kb
Host smart-8272bc15-b8a7-4efe-a158-1e48b725d00a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085479690 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1085479690
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.462850529
Short name T972
Test name
Test status
Simulation time 186998763 ps
CPU time 1.13 seconds
Started Jul 11 06:23:35 PM PDT 24
Finished Jul 11 06:23:46 PM PDT 24
Peak memory 217504 kb
Host smart-0970681d-85e8-413e-b82e-0d83b0e3a53e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462850529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.462850529
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1260951888
Short name T899
Test name
Test status
Simulation time 222680971 ps
CPU time 2.33 seconds
Started Jul 11 06:23:36 PM PDT 24
Finished Jul 11 06:23:47 PM PDT 24
Peak memory 217508 kb
Host smart-1518eae4-17e1-4290-b778-2377fe8c4b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260951888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1260951888
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.902985379
Short name T962
Test name
Test status
Simulation time 38112682 ps
CPU time 1.4 seconds
Started Jul 11 06:23:33 PM PDT 24
Finished Jul 11 06:23:44 PM PDT 24
Peak memory 217744 kb
Host smart-6dd44e34-3c8d-41d0-adc6-686bb85a2cd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902985379 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.902985379
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.451594875
Short name T948
Test name
Test status
Simulation time 39110570 ps
CPU time 0.83 seconds
Started Jul 11 06:23:34 PM PDT 24
Finished Jul 11 06:23:45 PM PDT 24
Peak memory 209256 kb
Host smart-0eca93f4-4220-432e-b885-efebd24dba74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451594875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.451594875
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1454457783
Short name T893
Test name
Test status
Simulation time 72368679 ps
CPU time 2.59 seconds
Started Jul 11 06:23:33 PM PDT 24
Finished Jul 11 06:23:45 PM PDT 24
Peak memory 208772 kb
Host smart-7b7b6342-b672-4004-b8b1-3c85dab30d83
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454457783 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1454457783
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2708561594
Short name T963
Test name
Test status
Simulation time 648933144 ps
CPU time 14.82 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:57 PM PDT 24
Peak memory 209064 kb
Host smart-8181c749-40a0-4230-b528-efb18261c4db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708561594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2708561594
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.297886401
Short name T884
Test name
Test status
Simulation time 2139483004 ps
CPU time 6.66 seconds
Started Jul 11 06:23:32 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 209332 kb
Host smart-92ebf657-7dbb-479c-8585-05e5fd5a89db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297886401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.297886401
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3950359805
Short name T879
Test name
Test status
Simulation time 457913466 ps
CPU time 2.79 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:44 PM PDT 24
Peak memory 210992 kb
Host smart-b59460cc-1da2-4d6e-9668-548b2bd4beda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950359805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3950359805
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3964098410
Short name T981
Test name
Test status
Simulation time 661237188 ps
CPU time 3.94 seconds
Started Jul 11 06:23:32 PM PDT 24
Finished Jul 11 06:23:47 PM PDT 24
Peak memory 217628 kb
Host smart-059347d3-72fa-4729-a931-cfc8b80073cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396409
8410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3964098410
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1353675281
Short name T988
Test name
Test status
Simulation time 69449799 ps
CPU time 1.13 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:43 PM PDT 24
Peak memory 209212 kb
Host smart-bb57bf79-edf3-4d0c-8c0e-e8c7f1d48d47
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353675281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1353675281
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1130125579
Short name T982
Test name
Test status
Simulation time 13546630 ps
CPU time 1.12 seconds
Started Jul 11 06:23:31 PM PDT 24
Finished Jul 11 06:23:43 PM PDT 24
Peak memory 209424 kb
Host smart-a066a479-3372-45ff-bc87-f1b58bc1abf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130125579 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1130125579
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1433893798
Short name T217
Test name
Test status
Simulation time 42458453 ps
CPU time 1.56 seconds
Started Jul 11 06:23:39 PM PDT 24
Finished Jul 11 06:23:48 PM PDT 24
Peak memory 211452 kb
Host smart-0f99c569-8aea-4808-9c47-f93f6ea6f2a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433893798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1433893798
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1880528774
Short name T953
Test name
Test status
Simulation time 184933607 ps
CPU time 2.27 seconds
Started Jul 11 06:23:34 PM PDT 24
Finished Jul 11 06:23:46 PM PDT 24
Peak memory 217532 kb
Host smart-c4ae1233-1001-4096-9b31-8c216b751b1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880528774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1880528774
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1754915228
Short name T906
Test name
Test status
Simulation time 58155164 ps
CPU time 1.25 seconds
Started Jul 11 06:23:39 PM PDT 24
Finished Jul 11 06:23:48 PM PDT 24
Peak memory 219608 kb
Host smart-62db4d30-d065-4e67-a115-a73606bf3fee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754915228 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1754915228
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3711762334
Short name T895
Test name
Test status
Simulation time 13423503 ps
CPU time 0.83 seconds
Started Jul 11 06:23:37 PM PDT 24
Finished Jul 11 06:23:47 PM PDT 24
Peak memory 209300 kb
Host smart-21a93547-9069-4728-88ec-100e9bab359e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711762334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3711762334
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2746462844
Short name T946
Test name
Test status
Simulation time 829313397 ps
CPU time 2.17 seconds
Started Jul 11 06:23:37 PM PDT 24
Finished Jul 11 06:23:48 PM PDT 24
Peak memory 209128 kb
Host smart-27175d0a-dc95-4966-9026-033bb66f6781
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746462844 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2746462844
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2882537552
Short name T992
Test name
Test status
Simulation time 477073383 ps
CPU time 10.93 seconds
Started Jul 11 06:23:44 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 209224 kb
Host smart-2d691375-3a3f-4f9f-9248-6f326a3ec8fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882537552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2882537552
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3911594911
Short name T964
Test name
Test status
Simulation time 486638925 ps
CPU time 11.68 seconds
Started Jul 11 06:23:38 PM PDT 24
Finished Jul 11 06:23:58 PM PDT 24
Peak memory 209236 kb
Host smart-1d30a598-fbd9-4be5-bb41-17108995a683
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911594911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3911594911
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2973871365
Short name T943
Test name
Test status
Simulation time 255531387 ps
CPU time 1.86 seconds
Started Jul 11 06:23:39 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 210780 kb
Host smart-28a9bab5-f318-48e3-8899-167c9eccdfe3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973871365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2973871365
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2082494357
Short name T877
Test name
Test status
Simulation time 194267408 ps
CPU time 2.63 seconds
Started Jul 11 06:23:43 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 222932 kb
Host smart-df7a46cc-7d13-454e-a764-81cc1fc80e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208249
4357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2082494357
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2570534386
Short name T901
Test name
Test status
Simulation time 191330687 ps
CPU time 4.29 seconds
Started Jul 11 06:23:40 PM PDT 24
Finished Jul 11 06:23:52 PM PDT 24
Peak memory 209356 kb
Host smart-eabf1fc6-7df0-48bb-a266-7d70c0f58162
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570534386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2570534386
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.241252178
Short name T984
Test name
Test status
Simulation time 157287786 ps
CPU time 1.81 seconds
Started Jul 11 06:23:41 PM PDT 24
Finished Jul 11 06:23:50 PM PDT 24
Peak memory 217540 kb
Host smart-6a7de50e-418a-45ea-bdeb-e119a0bb8685
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241252178 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.241252178
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2724048037
Short name T935
Test name
Test status
Simulation time 30419395 ps
CPU time 1.32 seconds
Started Jul 11 06:23:42 PM PDT 24
Finished Jul 11 06:23:51 PM PDT 24
Peak memory 209224 kb
Host smart-40d0487a-8d55-411f-8a2b-7673b9dff2c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724048037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2724048037
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.907590517
Short name T971
Test name
Test status
Simulation time 49860158 ps
CPU time 3.63 seconds
Started Jul 11 06:23:42 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 218392 kb
Host smart-e383b47c-ad1d-4452-8dab-d886f062108c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907590517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.907590517
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3157074007
Short name T34
Test name
Test status
Simulation time 32867040 ps
CPU time 1.09 seconds
Started Jul 11 05:18:32 PM PDT 24
Finished Jul 11 05:18:34 PM PDT 24
Peak memory 208820 kb
Host smart-6183fb15-9455-44a7-8ee8-63675fbc1ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157074007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3157074007
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3900350448
Short name T758
Test name
Test status
Simulation time 225193395 ps
CPU time 11.71 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:05 PM PDT 24
Peak memory 225904 kb
Host smart-be440caa-5aaf-42f6-91a9-a477aa1afdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900350448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3900350448
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2817868541
Short name T9
Test name
Test status
Simulation time 2236172987 ps
CPU time 5.98 seconds
Started Jul 11 05:18:24 PM PDT 24
Finished Jul 11 05:18:32 PM PDT 24
Peak memory 217332 kb
Host smart-5a8ef636-75c6-4fa0-8d4f-a0c41cfdcd19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817868541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2817868541
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2675010261
Short name T689
Test name
Test status
Simulation time 9028238498 ps
CPU time 42.26 seconds
Started Jul 11 05:18:27 PM PDT 24
Finished Jul 11 05:19:10 PM PDT 24
Peak memory 218796 kb
Host smart-9b39ce8b-7d91-4fd5-87de-7d95a27d6d98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675010261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2675010261
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2866474296
Short name T298
Test name
Test status
Simulation time 2856154894 ps
CPU time 8.62 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:01 PM PDT 24
Peak memory 217688 kb
Host smart-1be396ad-a03c-4420-b347-ae3361ed1d8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866474296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
866474296
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.369985689
Short name T737
Test name
Test status
Simulation time 517619863 ps
CPU time 14.15 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:06 PM PDT 24
Peak memory 218168 kb
Host smart-cf57d3b4-d47b-481f-8a10-77f3ee20d27d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369985689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.369985689
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2955424425
Short name T867
Test name
Test status
Simulation time 3449100935 ps
CPU time 14.29 seconds
Started Jul 11 05:18:25 PM PDT 24
Finished Jul 11 05:18:41 PM PDT 24
Peak memory 217624 kb
Host smart-cbec9f56-4478-4f15-a74d-e2dfee55fbe4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955424425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2955424425
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2723307345
Short name T703
Test name
Test status
Simulation time 1105627726 ps
CPU time 4.11 seconds
Started Jul 11 05:18:29 PM PDT 24
Finished Jul 11 05:18:34 PM PDT 24
Peak memory 217652 kb
Host smart-45d188bc-a504-4b0e-bbad-65b1d231a7ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723307345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2723307345
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2093567735
Short name T315
Test name
Test status
Simulation time 1014609128 ps
CPU time 50.55 seconds
Started Jul 11 05:18:28 PM PDT 24
Finished Jul 11 05:19:20 PM PDT 24
Peak memory 267168 kb
Host smart-ed242ce7-fe7f-4701-b7fd-4135724ffe74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093567735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2093567735
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4082292383
Short name T93
Test name
Test status
Simulation time 1425860223 ps
CPU time 18.43 seconds
Started Jul 11 05:18:28 PM PDT 24
Finished Jul 11 05:18:48 PM PDT 24
Peak memory 250924 kb
Host smart-f8290dd3-8d86-42e3-95ff-77517009588d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082292383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.4082292383
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.554166542
Short name T628
Test name
Test status
Simulation time 91072997 ps
CPU time 2.77 seconds
Started Jul 11 05:18:51 PM PDT 24
Finished Jul 11 05:18:58 PM PDT 24
Peak memory 217544 kb
Host smart-5a657e8c-4d50-4f42-9f6b-37c88379afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554166542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.554166542
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1030027053
Short name T68
Test name
Test status
Simulation time 532509542 ps
CPU time 16.17 seconds
Started Jul 11 05:18:28 PM PDT 24
Finished Jul 11 05:18:46 PM PDT 24
Peak memory 225828 kb
Host smart-e39cbe5d-24e9-4088-b474-94ea47187e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030027053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1030027053
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1391065136
Short name T249
Test name
Test status
Simulation time 372686242 ps
CPU time 15.36 seconds
Started Jul 11 05:18:49 PM PDT 24
Finished Jul 11 05:19:07 PM PDT 24
Peak memory 225896 kb
Host smart-f406d680-5e4a-4ad8-8484-edcf6920fe3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391065136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1391065136
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2794212407
Short name T386
Test name
Test status
Simulation time 2006631420 ps
CPU time 8.87 seconds
Started Jul 11 05:18:29 PM PDT 24
Finished Jul 11 05:18:39 PM PDT 24
Peak memory 218096 kb
Host smart-78ddcc9e-0f24-4d15-9086-cdeba9e46065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794212407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
794212407
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.61823190
Short name T634
Test name
Test status
Simulation time 912966745 ps
CPU time 6.24 seconds
Started Jul 11 05:18:23 PM PDT 24
Finished Jul 11 05:18:30 PM PDT 24
Peak memory 224656 kb
Host smart-e3cd524c-f65c-4c33-87a2-78efcfb9871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61823190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.61823190
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2285224484
Short name T299
Test name
Test status
Simulation time 41039482 ps
CPU time 2.49 seconds
Started Jul 11 05:18:33 PM PDT 24
Finished Jul 11 05:18:36 PM PDT 24
Peak memory 214816 kb
Host smart-db7925fc-178b-4576-b960-3cf728b3e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285224484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2285224484
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1314802425
Short name T561
Test name
Test status
Simulation time 324992387 ps
CPU time 40.37 seconds
Started Jul 11 05:18:29 PM PDT 24
Finished Jul 11 05:19:10 PM PDT 24
Peak memory 250920 kb
Host smart-a54e3af0-ed75-4be7-84a7-f55cbc671823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314802425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1314802425
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2540633102
Short name T507
Test name
Test status
Simulation time 119876092 ps
CPU time 10.37 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:03 PM PDT 24
Peak memory 250932 kb
Host smart-a4aedd11-1e1f-4924-9f6f-da99b9b87f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540633102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2540633102
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.295233224
Short name T494
Test name
Test status
Simulation time 10760148277 ps
CPU time 108.72 seconds
Started Jul 11 05:18:25 PM PDT 24
Finished Jul 11 05:20:16 PM PDT 24
Peak memory 273116 kb
Host smart-abc19bd7-f1b2-4e1c-9043-285e477722df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295233224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.295233224
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.569946724
Short name T155
Test name
Test status
Simulation time 128614011978 ps
CPU time 1044.86 seconds
Started Jul 11 05:18:25 PM PDT 24
Finished Jul 11 05:35:51 PM PDT 24
Peak memory 333008 kb
Host smart-df09a701-adb4-4c19-bbd7-a5566daf29f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=569946724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.569946724
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.4094319544
Short name T457
Test name
Test status
Simulation time 14028225 ps
CPU time 0.89 seconds
Started Jul 11 05:18:28 PM PDT 24
Finished Jul 11 05:18:30 PM PDT 24
Peak memory 211796 kb
Host smart-fab32043-b06e-4b73-b4db-cb3911e7c697
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094319544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.4094319544
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3537756861
Short name T649
Test name
Test status
Simulation time 223276560 ps
CPU time 1.03 seconds
Started Jul 11 05:18:45 PM PDT 24
Finished Jul 11 05:18:47 PM PDT 24
Peak memory 208836 kb
Host smart-2d5a2518-95c8-46bd-b297-d6bea3040541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537756861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3537756861
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4000242374
Short name T287
Test name
Test status
Simulation time 828733296 ps
CPU time 9.76 seconds
Started Jul 11 05:18:52 PM PDT 24
Finished Jul 11 05:19:06 PM PDT 24
Peak memory 218168 kb
Host smart-36c9e01b-9d91-425c-96c4-17ca6aadd73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000242374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4000242374
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.632790904
Short name T526
Test name
Test status
Simulation time 957788224 ps
CPU time 11.6 seconds
Started Jul 11 05:18:32 PM PDT 24
Finished Jul 11 05:18:44 PM PDT 24
Peak memory 217172 kb
Host smart-5b8152d3-55ef-4c71-a3fd-1b78bda670a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632790904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.632790904
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.4059615234
Short name T556
Test name
Test status
Simulation time 2477284767 ps
CPU time 73.9 seconds
Started Jul 11 05:18:28 PM PDT 24
Finished Jul 11 05:19:43 PM PDT 24
Peak memory 219176 kb
Host smart-bf9a4fad-a08a-4e13-9d75-aae814aae716
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059615234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.4059615234
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1952362437
Short name T780
Test name
Test status
Simulation time 960080699 ps
CPU time 9.85 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:02 PM PDT 24
Peak memory 217592 kb
Host smart-213e9568-a5a2-4772-8ae0-82839aa7a9fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952362437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
952362437
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1822527211
Short name T743
Test name
Test status
Simulation time 312871305 ps
CPU time 5.73 seconds
Started Jul 11 05:18:32 PM PDT 24
Finished Jul 11 05:18:39 PM PDT 24
Peak memory 218068 kb
Host smart-7b5d9e99-a0eb-4d0a-8c41-fc86a1fe7f1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822527211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1822527211
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3741729145
Short name T813
Test name
Test status
Simulation time 2583656504 ps
CPU time 24.07 seconds
Started Jul 11 05:18:37 PM PDT 24
Finished Jul 11 05:19:02 PM PDT 24
Peak memory 217688 kb
Host smart-dc7f550b-ca56-4a14-a27a-e24186937de7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741729145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3741729145
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1211293558
Short name T64
Test name
Test status
Simulation time 346429806 ps
CPU time 9.63 seconds
Started Jul 11 05:18:53 PM PDT 24
Finished Jul 11 05:19:06 PM PDT 24
Peak memory 217652 kb
Host smart-8080bd27-f114-4514-a2d3-2b9da78573da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211293558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1211293558
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.510365611
Short name T846
Test name
Test status
Simulation time 15146574150 ps
CPU time 35.65 seconds
Started Jul 11 05:18:30 PM PDT 24
Finished Jul 11 05:19:07 PM PDT 24
Peak memory 250464 kb
Host smart-be4d15d5-b629-4d02-8507-fd6513a632e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510365611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.510365611
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.559637461
Short name T97
Test name
Test status
Simulation time 309692318 ps
CPU time 10.95 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:04 PM PDT 24
Peak memory 250484 kb
Host smart-5d5e6e4f-0cf9-40f8-8b96-9783f0254764
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559637461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.559637461
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1708951573
Short name T538
Test name
Test status
Simulation time 261341970 ps
CPU time 2.89 seconds
Started Jul 11 05:18:53 PM PDT 24
Finished Jul 11 05:19:00 PM PDT 24
Peak memory 222396 kb
Host smart-66613572-900a-43ac-a9a3-4dac8e88ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708951573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1708951573
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.389815396
Short name T821
Test name
Test status
Simulation time 618679359 ps
CPU time 11.89 seconds
Started Jul 11 05:18:52 PM PDT 24
Finished Jul 11 05:19:08 PM PDT 24
Peak memory 217664 kb
Host smart-32830d19-0b65-46e8-b55f-295cc46dd620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389815396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.389815396
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3678611293
Short name T83
Test name
Test status
Simulation time 686741120 ps
CPU time 25.32 seconds
Started Jul 11 05:18:49 PM PDT 24
Finished Jul 11 05:19:16 PM PDT 24
Peak memory 269260 kb
Host smart-4e0a7eec-5164-4056-9570-c73877eb1eed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678611293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3678611293
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2244314110
Short name T488
Test name
Test status
Simulation time 1156988010 ps
CPU time 12.87 seconds
Started Jul 11 05:18:47 PM PDT 24
Finished Jul 11 05:19:01 PM PDT 24
Peak memory 225872 kb
Host smart-0d4583d8-5210-4d06-bbc4-01a7db0e1d79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244314110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2244314110
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3462129890
Short name T622
Test name
Test status
Simulation time 845004104 ps
CPU time 11.68 seconds
Started Jul 11 05:18:44 PM PDT 24
Finished Jul 11 05:18:56 PM PDT 24
Peak memory 225956 kb
Host smart-2a111d5d-6afa-4582-a758-3d4fad0d4894
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462129890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3462129890
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2644754797
Short name T799
Test name
Test status
Simulation time 1833325928 ps
CPU time 12.66 seconds
Started Jul 11 05:18:45 PM PDT 24
Finished Jul 11 05:18:59 PM PDT 24
Peak memory 225972 kb
Host smart-b37bddcc-a249-4abc-ace3-02a8d0b354e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644754797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
644754797
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3301644863
Short name T43
Test name
Test status
Simulation time 191589557 ps
CPU time 7.66 seconds
Started Jul 11 05:18:37 PM PDT 24
Finished Jul 11 05:18:46 PM PDT 24
Peak memory 218204 kb
Host smart-ccad2c52-83ee-4d5c-9fc4-1f737e01c1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301644863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3301644863
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3353066023
Short name T852
Test name
Test status
Simulation time 75924252 ps
CPU time 1.61 seconds
Started Jul 11 05:18:32 PM PDT 24
Finished Jul 11 05:18:34 PM PDT 24
Peak memory 217572 kb
Host smart-2f1d90de-43b3-4b3e-8a83-a38bffaa6acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353066023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3353066023
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3489622682
Short name T850
Test name
Test status
Simulation time 800384531 ps
CPU time 21.91 seconds
Started Jul 11 05:18:53 PM PDT 24
Finished Jul 11 05:19:19 PM PDT 24
Peak memory 246224 kb
Host smart-caf8836f-be5f-4b2c-872f-76fd081462e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489622682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3489622682
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3508157434
Short name T325
Test name
Test status
Simulation time 159961520 ps
CPU time 9.04 seconds
Started Jul 11 05:18:29 PM PDT 24
Finished Jul 11 05:18:39 PM PDT 24
Peak memory 250788 kb
Host smart-380f34c1-1ad5-48de-ab53-e18c8ffca388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508157434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3508157434
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1074965298
Short name T661
Test name
Test status
Simulation time 25412206507 ps
CPU time 804.25 seconds
Started Jul 11 05:18:44 PM PDT 24
Finished Jul 11 05:32:10 PM PDT 24
Peak memory 283876 kb
Host smart-40e634c1-b977-49db-bc37-44c4ea828a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1074965298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1074965298
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1299707987
Short name T705
Test name
Test status
Simulation time 50568920 ps
CPU time 0.83 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:18:54 PM PDT 24
Peak memory 211816 kb
Host smart-70bdf9bb-105c-4f29-b6bc-cac0eafe3a8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299707987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1299707987
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1096133533
Short name T163
Test name
Test status
Simulation time 13832946 ps
CPU time 0.84 seconds
Started Jul 11 05:19:53 PM PDT 24
Finished Jul 11 05:20:01 PM PDT 24
Peak memory 208920 kb
Host smart-10bfa8a1-d9b5-4bf1-bd9a-62d8a55d8900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096133533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1096133533
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.970121806
Short name T532
Test name
Test status
Simulation time 868033153 ps
CPU time 20.25 seconds
Started Jul 11 05:19:57 PM PDT 24
Finished Jul 11 05:20:24 PM PDT 24
Peak memory 217096 kb
Host smart-6f455d73-98e1-4ff6-b357-e7cfc86d5e75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970121806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.970121806
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1425772181
Short name T52
Test name
Test status
Simulation time 3828472245 ps
CPU time 34.66 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:35 PM PDT 24
Peak memory 218864 kb
Host smart-f2435d82-c068-4a18-9fc5-89cfd9cd8492
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425772181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1425772181
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3501535667
Short name T262
Test name
Test status
Simulation time 1642449662 ps
CPU time 11.26 seconds
Started Jul 11 05:19:53 PM PDT 24
Finished Jul 11 05:20:12 PM PDT 24
Peak memory 218124 kb
Host smart-3722168f-4dfe-4e01-ba56-4e58f501ff08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501535667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3501535667
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1813568915
Short name T426
Test name
Test status
Simulation time 2335477254 ps
CPU time 9.35 seconds
Started Jul 11 05:19:55 PM PDT 24
Finished Jul 11 05:20:11 PM PDT 24
Peak memory 217728 kb
Host smart-af98043d-afce-4126-b19a-064606ffb43a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813568915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1813568915
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1906503806
Short name T367
Test name
Test status
Simulation time 508374615 ps
CPU time 8.44 seconds
Started Jul 11 05:19:55 PM PDT 24
Finished Jul 11 05:20:10 PM PDT 24
Peak memory 226252 kb
Host smart-daa68919-3bd7-4955-a262-37c71f0538fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906503806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1906503806
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.240306833
Short name T596
Test name
Test status
Simulation time 215434743 ps
CPU time 3.3 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:04 PM PDT 24
Peak memory 222484 kb
Host smart-9107623c-fa28-430a-b40a-77bc32a9a8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240306833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.240306833
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.139781121
Short name T468
Test name
Test status
Simulation time 6739762579 ps
CPU time 13.48 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:14 PM PDT 24
Peak memory 219380 kb
Host smart-5edca8d3-9954-49ae-a5f8-bbfe14ec7305
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139781121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.139781121
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.458965519
Short name T465
Test name
Test status
Simulation time 533040979 ps
CPU time 11.91 seconds
Started Jul 11 05:19:52 PM PDT 24
Finished Jul 11 05:20:11 PM PDT 24
Peak memory 226232 kb
Host smart-b9ea4207-fd30-4ec0-8bc1-409aa7f0e64e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458965519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.458965519
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2626276912
Short name T55
Test name
Test status
Simulation time 2285981709 ps
CPU time 11.92 seconds
Started Jul 11 05:19:53 PM PDT 24
Finished Jul 11 05:20:12 PM PDT 24
Peak memory 218248 kb
Host smart-7416995d-1285-4bbe-8648-9cbf6e55d9ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626276912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2626276912
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3061618078
Short name T188
Test name
Test status
Simulation time 315340126 ps
CPU time 11.71 seconds
Started Jul 11 05:19:55 PM PDT 24
Finished Jul 11 05:20:13 PM PDT 24
Peak memory 225256 kb
Host smart-2f47f2fd-f6d8-44d4-910a-036b9df66cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061618078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3061618078
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1129278613
Short name T806
Test name
Test status
Simulation time 170902155 ps
CPU time 13.9 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:20:09 PM PDT 24
Peak memory 250784 kb
Host smart-1147bff3-7c93-47f0-bd72-b26902f4f5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129278613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1129278613
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3777754928
Short name T512
Test name
Test status
Simulation time 245600932 ps
CPU time 6.89 seconds
Started Jul 11 05:19:56 PM PDT 24
Finished Jul 11 05:20:09 PM PDT 24
Peak memory 250356 kb
Host smart-d7493861-699e-48d6-b336-d449d6850ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777754928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3777754928
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3217930211
Short name T613
Test name
Test status
Simulation time 34997160838 ps
CPU time 150.64 seconds
Started Jul 11 05:19:53 PM PDT 24
Finished Jul 11 05:22:30 PM PDT 24
Peak memory 405480 kb
Host smart-66971ec1-19c9-48da-aae1-b5dfaa2210a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217930211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3217930211
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2898390266
Short name T161
Test name
Test status
Simulation time 41862346 ps
CPU time 0.96 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:01 PM PDT 24
Peak memory 211852 kb
Host smart-bf50fd07-1738-4dc4-b9ca-9d255815086b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898390266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2898390266
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2884464142
Short name T617
Test name
Test status
Simulation time 34576276 ps
CPU time 1.03 seconds
Started Jul 11 05:20:00 PM PDT 24
Finished Jul 11 05:20:06 PM PDT 24
Peak memory 208812 kb
Host smart-460bc64d-1d40-4853-aec6-040a19b51ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884464142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2884464142
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2941839883
Short name T335
Test name
Test status
Simulation time 299451622 ps
CPU time 13.5 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:14 PM PDT 24
Peak memory 225968 kb
Host smart-4b830916-dc5d-4123-83c3-6f6113df5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941839883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2941839883
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2565332593
Short name T819
Test name
Test status
Simulation time 153047249 ps
CPU time 2.74 seconds
Started Jul 11 05:20:22 PM PDT 24
Finished Jul 11 05:20:28 PM PDT 24
Peak memory 217028 kb
Host smart-b2dccee8-e738-442a-84b8-23ce9fc2f932
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565332593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2565332593
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3318311853
Short name T38
Test name
Test status
Simulation time 3621415397 ps
CPU time 64.54 seconds
Started Jul 11 05:19:52 PM PDT 24
Finished Jul 11 05:21:03 PM PDT 24
Peak memory 218888 kb
Host smart-eeee7690-2f7b-4968-83cb-f417165b6407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318311853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3318311853
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1866334793
Short name T228
Test name
Test status
Simulation time 1312930569 ps
CPU time 4.9 seconds
Started Jul 11 05:19:52 PM PDT 24
Finished Jul 11 05:20:03 PM PDT 24
Peak memory 222832 kb
Host smart-7fc0083c-602f-4c4b-838e-21671843f8ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866334793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1866334793
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2918774404
Short name T783
Test name
Test status
Simulation time 211582838 ps
CPU time 3.43 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:19:57 PM PDT 24
Peak memory 217628 kb
Host smart-5a4780ad-83f7-4a8c-b287-8f3391aab3ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918774404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2918774404
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2507052389
Short name T309
Test name
Test status
Simulation time 5325926851 ps
CPU time 38.13 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:39 PM PDT 24
Peak memory 267476 kb
Host smart-ff67cb42-4393-47b9-871a-94af755892a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507052389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2507052389
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3654290947
Short name T676
Test name
Test status
Simulation time 3156289089 ps
CPU time 17.53 seconds
Started Jul 11 05:19:56 PM PDT 24
Finished Jul 11 05:20:20 PM PDT 24
Peak memory 246568 kb
Host smart-5e2080fb-b31d-4fa6-92f9-489c0a038bdd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654290947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3654290947
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.131414924
Short name T728
Test name
Test status
Simulation time 456528042 ps
CPU time 3.93 seconds
Started Jul 11 05:19:55 PM PDT 24
Finished Jul 11 05:20:06 PM PDT 24
Peak memory 218064 kb
Host smart-7e03490d-8675-4c83-bdd0-72a75f01509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131414924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.131414924
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3505097637
Short name T546
Test name
Test status
Simulation time 238045455 ps
CPU time 8.65 seconds
Started Jul 11 05:20:00 PM PDT 24
Finished Jul 11 05:20:14 PM PDT 24
Peak memory 225948 kb
Host smart-56adceaa-f956-4126-9131-cbed4713bf97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505097637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3505097637
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.890296879
Short name T460
Test name
Test status
Simulation time 1313165149 ps
CPU time 13.73 seconds
Started Jul 11 05:20:22 PM PDT 24
Finished Jul 11 05:20:39 PM PDT 24
Peak memory 225980 kb
Host smart-f786e016-033a-4ca6-8cf6-3f4de8e011fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890296879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.890296879
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1195488104
Short name T523
Test name
Test status
Simulation time 616922180 ps
CPU time 11.3 seconds
Started Jul 11 05:19:56 PM PDT 24
Finished Jul 11 05:20:14 PM PDT 24
Peak memory 226064 kb
Host smart-98351c2b-1245-40c1-807c-2df26fcfe6e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195488104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1195488104
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1663536495
Short name T820
Test name
Test status
Simulation time 16673738 ps
CPU time 1.5 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:02 PM PDT 24
Peak memory 222064 kb
Host smart-423e6d21-8000-4bad-a2d1-ba041bc34cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663536495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1663536495
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1286754045
Short name T753
Test name
Test status
Simulation time 363801977 ps
CPU time 28.74 seconds
Started Jul 11 05:19:53 PM PDT 24
Finished Jul 11 05:20:28 PM PDT 24
Peak memory 250840 kb
Host smart-43c6f258-774b-466e-a5ee-e5514be806f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286754045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1286754045
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2559572144
Short name T274
Test name
Test status
Simulation time 115303457 ps
CPU time 6.36 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:20:02 PM PDT 24
Peak memory 247092 kb
Host smart-c1d5996e-5c71-4e37-8efc-20368ac9f232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559572144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2559572144
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4077424708
Short name T57
Test name
Test status
Simulation time 19479172149 ps
CPU time 173.74 seconds
Started Jul 11 05:20:00 PM PDT 24
Finished Jul 11 05:22:59 PM PDT 24
Peak memory 267648 kb
Host smart-fe65fd1e-5dcd-46b0-b8d0-de1f923e798a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077424708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4077424708
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.4201034469
Short name T154
Test name
Test status
Simulation time 74198708606 ps
CPU time 797.71 seconds
Started Jul 11 05:20:01 PM PDT 24
Finished Jul 11 05:33:23 PM PDT 24
Peak memory 513160 kb
Host smart-f559a6c5-e431-4feb-9a0b-7074bfa6c49e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4201034469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.4201034469
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.869203067
Short name T730
Test name
Test status
Simulation time 18405086 ps
CPU time 0.83 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:02 PM PDT 24
Peak memory 211928 kb
Host smart-ee78c0ac-a190-4a4f-9f80-da44984ccd66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869203067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.869203067
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1757022436
Short name T358
Test name
Test status
Simulation time 156110677 ps
CPU time 0.93 seconds
Started Jul 11 05:19:57 PM PDT 24
Finished Jul 11 05:20:04 PM PDT 24
Peak memory 208932 kb
Host smart-620482bf-2a5b-4485-9de8-7ce4b02e673e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757022436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1757022436
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1171376223
Short name T294
Test name
Test status
Simulation time 8044018667 ps
CPU time 14.19 seconds
Started Jul 11 05:19:59 PM PDT 24
Finished Jul 11 05:20:19 PM PDT 24
Peak memory 225968 kb
Host smart-0c5dea1a-8fe7-4a9b-a52b-a92349c92459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171376223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1171376223
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2339869361
Short name T25
Test name
Test status
Simulation time 654231245 ps
CPU time 12.05 seconds
Started Jul 11 05:20:21 PM PDT 24
Finished Jul 11 05:20:36 PM PDT 24
Peak memory 217344 kb
Host smart-7b795e99-50f7-4ee8-878a-060bf3dd32bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339869361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2339869361
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.691769992
Short name T39
Test name
Test status
Simulation time 10207193186 ps
CPU time 65.71 seconds
Started Jul 11 05:20:07 PM PDT 24
Finished Jul 11 05:21:16 PM PDT 24
Peak memory 218240 kb
Host smart-8d0d4909-3756-4c1c-8c34-aff7db2d910c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691769992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.691769992
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2861258538
Short name T711
Test name
Test status
Simulation time 345716043 ps
CPU time 10.25 seconds
Started Jul 11 05:19:58 PM PDT 24
Finished Jul 11 05:20:14 PM PDT 24
Peak memory 221892 kb
Host smart-f9c81301-09cb-45dc-83e6-435e3c6a4e20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861258538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2861258538
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2279070988
Short name T240
Test name
Test status
Simulation time 206771563 ps
CPU time 1.9 seconds
Started Jul 11 05:20:00 PM PDT 24
Finished Jul 11 05:20:07 PM PDT 24
Peak memory 217756 kb
Host smart-cef51ab3-3dc9-4a90-97e2-4f9c766bf4a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279070988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2279070988
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1365244687
Short name T509
Test name
Test status
Simulation time 1872179408 ps
CPU time 52.06 seconds
Started Jul 11 05:20:01 PM PDT 24
Finished Jul 11 05:20:58 PM PDT 24
Peak memory 276116 kb
Host smart-e3f37771-d9d2-41ab-ba7f-41dd42dee754
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365244687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1365244687
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1546637114
Short name T665
Test name
Test status
Simulation time 5609597920 ps
CPU time 22.05 seconds
Started Jul 11 05:20:25 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 226316 kb
Host smart-c28aa081-5e6d-4287-ac5e-3473f4a1db4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546637114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1546637114
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.217461512
Short name T567
Test name
Test status
Simulation time 95281522 ps
CPU time 4.17 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:31 PM PDT 24
Peak memory 222668 kb
Host smart-1f0dee58-6e90-4d4b-90d1-fe9587dd9066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217461512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.217461512
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1675652311
Short name T858
Test name
Test status
Simulation time 207058329 ps
CPU time 10.37 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:36 PM PDT 24
Peak memory 225980 kb
Host smart-98e4766d-5121-4c3d-9ff4-89b3e17c0d1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675652311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1675652311
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2069946036
Short name T586
Test name
Test status
Simulation time 388719375 ps
CPU time 14.66 seconds
Started Jul 11 05:19:59 PM PDT 24
Finished Jul 11 05:20:19 PM PDT 24
Peak memory 225960 kb
Host smart-14f5bcf8-0e72-4b83-b3a1-cac3a822f4e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069946036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2069946036
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1984031351
Short name T289
Test name
Test status
Simulation time 863960867 ps
CPU time 8.26 seconds
Started Jul 11 05:19:58 PM PDT 24
Finished Jul 11 05:20:12 PM PDT 24
Peak memory 218184 kb
Host smart-713a1325-c46a-483f-b061-23251dbe4335
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984031351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1984031351
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.859313173
Short name T58
Test name
Test status
Simulation time 31898614 ps
CPU time 1.7 seconds
Started Jul 11 05:20:22 PM PDT 24
Finished Jul 11 05:20:27 PM PDT 24
Peak memory 213868 kb
Host smart-bab82313-4cc8-4419-a7da-e48072b45a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859313173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.859313173
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.207353041
Short name T108
Test name
Test status
Simulation time 509309846 ps
CPU time 25.66 seconds
Started Jul 11 05:20:02 PM PDT 24
Finished Jul 11 05:20:32 PM PDT 24
Peak memory 250848 kb
Host smart-f3f684f1-60c9-4f7f-b058-165519829bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207353041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.207353041
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1893434411
Short name T839
Test name
Test status
Simulation time 264797582 ps
CPU time 8.15 seconds
Started Jul 11 05:19:58 PM PDT 24
Finished Jul 11 05:20:12 PM PDT 24
Peak memory 246940 kb
Host smart-8d6687c9-011b-4d80-9c14-2bfe3d3111bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893434411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1893434411
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3393273336
Short name T354
Test name
Test status
Simulation time 19473876478 ps
CPU time 57.74 seconds
Started Jul 11 05:20:03 PM PDT 24
Finished Jul 11 05:21:05 PM PDT 24
Peak memory 250852 kb
Host smart-1e0803db-782f-48ff-a405-a905ece4b86f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393273336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3393273336
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.55326854
Short name T261
Test name
Test status
Simulation time 18628600 ps
CPU time 1.39 seconds
Started Jul 11 05:19:57 PM PDT 24
Finished Jul 11 05:20:05 PM PDT 24
Peak memory 217568 kb
Host smart-f641f8c0-9877-4733-81fe-c22e675012a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55326854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_volatile_unlock_smoke.55326854
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3553004535
Short name T592
Test name
Test status
Simulation time 139235351 ps
CPU time 0.97 seconds
Started Jul 11 05:20:21 PM PDT 24
Finished Jul 11 05:20:25 PM PDT 24
Peak memory 208940 kb
Host smart-59ef9584-bed5-467a-9c1b-b49eab5a957e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553004535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3553004535
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2101171402
Short name T686
Test name
Test status
Simulation time 274904536 ps
CPU time 9.94 seconds
Started Jul 11 05:19:59 PM PDT 24
Finished Jul 11 05:20:15 PM PDT 24
Peak memory 218020 kb
Host smart-c4a817ca-30bd-47ed-ab77-25bdfcee99e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101171402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2101171402
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1722240485
Short name T684
Test name
Test status
Simulation time 513253185 ps
CPU time 13.06 seconds
Started Jul 11 05:19:59 PM PDT 24
Finished Jul 11 05:20:17 PM PDT 24
Peak memory 217148 kb
Host smart-ffee23cf-4317-4ead-a924-398f99ab78b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722240485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1722240485
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.599314167
Short name T851
Test name
Test status
Simulation time 1656468798 ps
CPU time 46.3 seconds
Started Jul 11 05:20:22 PM PDT 24
Finished Jul 11 05:21:11 PM PDT 24
Peak memory 218172 kb
Host smart-7df57f76-136d-4153-8011-9901470650c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599314167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.599314167
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2985658486
Short name T229
Test name
Test status
Simulation time 820870435 ps
CPU time 5.57 seconds
Started Jul 11 05:20:01 PM PDT 24
Finished Jul 11 05:20:12 PM PDT 24
Peak memory 218144 kb
Host smart-8153195c-3d26-4247-8a6b-c7ef2e9cae1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985658486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2985658486
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1415337031
Short name T618
Test name
Test status
Simulation time 630012735 ps
CPU time 9.68 seconds
Started Jul 11 05:20:01 PM PDT 24
Finished Jul 11 05:20:16 PM PDT 24
Peak memory 217644 kb
Host smart-582acd2c-5e64-46c4-828d-b31421d06b00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415337031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1415337031
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2841346329
Short name T22
Test name
Test status
Simulation time 8979992407 ps
CPU time 47.53 seconds
Started Jul 11 05:19:58 PM PDT 24
Finished Jul 11 05:20:51 PM PDT 24
Peak memory 250976 kb
Host smart-7d215e88-d9b9-4646-b72b-0bd00c055415
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841346329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2841346329
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.360336460
Short name T683
Test name
Test status
Simulation time 378847539 ps
CPU time 7.84 seconds
Started Jul 11 05:20:03 PM PDT 24
Finished Jul 11 05:20:15 PM PDT 24
Peak memory 217964 kb
Host smart-7a2ab962-5152-49cf-bd35-faea42c4f770
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360336460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.360336460
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.349448725
Short name T361
Test name
Test status
Simulation time 33212133 ps
CPU time 1.94 seconds
Started Jul 11 05:20:22 PM PDT 24
Finished Jul 11 05:20:26 PM PDT 24
Peak memory 218168 kb
Host smart-7e4e6988-81c7-4926-a721-822e27c76067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349448725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.349448725
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.760359377
Short name T655
Test name
Test status
Simulation time 751462215 ps
CPU time 10.34 seconds
Started Jul 11 05:20:01 PM PDT 24
Finished Jul 11 05:20:16 PM PDT 24
Peak memory 225896 kb
Host smart-4f1b00c3-75c8-45b4-ac7d-df370823afa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760359377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.760359377
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3012815422
Short name T244
Test name
Test status
Simulation time 1724393898 ps
CPU time 9.9 seconds
Started Jul 11 05:20:08 PM PDT 24
Finished Jul 11 05:20:20 PM PDT 24
Peak memory 225984 kb
Host smart-c309332b-c6b1-4a22-b172-348814c0fa64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012815422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3012815422
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1339216858
Short name T46
Test name
Test status
Simulation time 540815014 ps
CPU time 18.41 seconds
Started Jul 11 05:19:57 PM PDT 24
Finished Jul 11 05:20:21 PM PDT 24
Peak memory 218160 kb
Host smart-4f79bdef-16a1-4142-a607-d07e8456a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339216858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1339216858
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3909751844
Short name T830
Test name
Test status
Simulation time 37729443 ps
CPU time 2.76 seconds
Started Jul 11 05:19:59 PM PDT 24
Finished Jul 11 05:20:07 PM PDT 24
Peak memory 214668 kb
Host smart-7acb1847-6f27-4f11-afd6-a72bba41b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909751844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3909751844
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1511217065
Short name T788
Test name
Test status
Simulation time 3456757803 ps
CPU time 25.91 seconds
Started Jul 11 05:20:02 PM PDT 24
Finished Jul 11 05:20:32 PM PDT 24
Peak memory 247840 kb
Host smart-903e27fe-f311-41d0-a19d-cf2fdac84875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511217065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1511217065
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.346700461
Short name T387
Test name
Test status
Simulation time 135715595 ps
CPU time 9.41 seconds
Started Jul 11 05:19:58 PM PDT 24
Finished Jul 11 05:20:13 PM PDT 24
Peak memory 250928 kb
Host smart-573e58e6-a743-4f6d-a3f1-97d562e3773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346700461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.346700461
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3513634449
Short name T111
Test name
Test status
Simulation time 42659671701 ps
CPU time 386.61 seconds
Started Jul 11 05:20:01 PM PDT 24
Finished Jul 11 05:26:33 PM PDT 24
Peak memory 276784 kb
Host smart-a29a97dd-e94c-4cad-b6d5-c7a52a370d45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513634449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3513634449
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.615915258
Short name T424
Test name
Test status
Simulation time 16332081 ps
CPU time 0.91 seconds
Started Jul 11 05:20:24 PM PDT 24
Finished Jul 11 05:20:28 PM PDT 24
Peak memory 212988 kb
Host smart-4e761e2d-3060-4987-a38a-20734911a76a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615915258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.615915258
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2678758989
Short name T345
Test name
Test status
Simulation time 29106375 ps
CPU time 0.87 seconds
Started Jul 11 05:20:11 PM PDT 24
Finished Jul 11 05:20:13 PM PDT 24
Peak memory 208880 kb
Host smart-3a34f631-5244-489b-a981-92bc87d23b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678758989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2678758989
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.605980805
Short name T37
Test name
Test status
Simulation time 1152090990 ps
CPU time 12.37 seconds
Started Jul 11 05:20:07 PM PDT 24
Finished Jul 11 05:20:22 PM PDT 24
Peak memory 218416 kb
Host smart-d2208d61-bde0-4575-8df7-d17890e0ac48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605980805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.605980805
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.425600633
Short name T28
Test name
Test status
Simulation time 89737677 ps
CPU time 1.86 seconds
Started Jul 11 05:20:12 PM PDT 24
Finished Jul 11 05:20:15 PM PDT 24
Peak memory 217016 kb
Host smart-58023ae9-c6bc-4b1c-b831-69bc3228a99d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425600633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.425600633
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2795527239
Short name T254
Test name
Test status
Simulation time 3046454589 ps
CPU time 86.32 seconds
Started Jul 11 05:20:13 PM PDT 24
Finished Jul 11 05:21:41 PM PDT 24
Peak memory 220116 kb
Host smart-069fcc55-4ea9-4d30-98eb-718dfc618591
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795527239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2795527239
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2888128307
Short name T541
Test name
Test status
Simulation time 720020694 ps
CPU time 4.26 seconds
Started Jul 11 05:20:16 PM PDT 24
Finished Jul 11 05:20:22 PM PDT 24
Peak memory 221684 kb
Host smart-d25e3b53-e8e2-459c-ac46-f5ce7ff4e7e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888128307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2888128307
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.4267156953
Short name T331
Test name
Test status
Simulation time 1583635871 ps
CPU time 6.26 seconds
Started Jul 11 05:20:05 PM PDT 24
Finished Jul 11 05:20:15 PM PDT 24
Peak memory 217700 kb
Host smart-3afc8b97-c5d7-43f0-ade0-c02a8b11e242
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267156953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.4267156953
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2743333823
Short name T392
Test name
Test status
Simulation time 3483812057 ps
CPU time 47.23 seconds
Started Jul 11 05:20:06 PM PDT 24
Finished Jul 11 05:20:56 PM PDT 24
Peak memory 277440 kb
Host smart-981b41d8-737d-4657-b85f-2f823b9b2847
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743333823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2743333823
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2817274080
Short name T763
Test name
Test status
Simulation time 575755647 ps
CPU time 6.7 seconds
Started Jul 11 05:20:08 PM PDT 24
Finished Jul 11 05:20:17 PM PDT 24
Peak memory 224516 kb
Host smart-489c8a3d-2f0b-49b4-bfb3-e6cf3ba7f2e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817274080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2817274080
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3002764093
Short name T439
Test name
Test status
Simulation time 270371630 ps
CPU time 3.55 seconds
Started Jul 11 05:20:06 PM PDT 24
Finished Jul 11 05:20:13 PM PDT 24
Peak memory 218068 kb
Host smart-85a41961-daf0-48d7-a784-8b717bba7be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002764093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3002764093
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1326752015
Short name T16
Test name
Test status
Simulation time 1193231964 ps
CPU time 13.28 seconds
Started Jul 11 05:20:20 PM PDT 24
Finished Jul 11 05:20:36 PM PDT 24
Peak memory 225888 kb
Host smart-cb2c3620-2a41-4aa2-9de5-8555aeac1696
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326752015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1326752015
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4164745462
Short name T781
Test name
Test status
Simulation time 2870577401 ps
CPU time 9.05 seconds
Started Jul 11 05:20:12 PM PDT 24
Finished Jul 11 05:20:22 PM PDT 24
Peak memory 225648 kb
Host smart-b5ba51c4-4456-4230-a4c2-e41c5bf4e9ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164745462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
4164745462
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.653754852
Short name T633
Test name
Test status
Simulation time 3230114976 ps
CPU time 12.63 seconds
Started Jul 11 05:20:07 PM PDT 24
Finished Jul 11 05:20:22 PM PDT 24
Peak memory 226024 kb
Host smart-9f2fd2e9-b65a-4f88-a6ff-6fedf0f6f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653754852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.653754852
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3082732772
Short name T63
Test name
Test status
Simulation time 76738970 ps
CPU time 1.67 seconds
Started Jul 11 05:20:09 PM PDT 24
Finished Jul 11 05:20:13 PM PDT 24
Peak memory 213764 kb
Host smart-8bcdc497-8415-43e9-824d-5296a1ac99b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082732772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3082732772
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2624987053
Short name T614
Test name
Test status
Simulation time 521598270 ps
CPU time 30.24 seconds
Started Jul 11 05:20:05 PM PDT 24
Finished Jul 11 05:20:39 PM PDT 24
Peak memory 250880 kb
Host smart-a31b32f7-fba5-4dca-8bfa-e279dc6e800c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624987053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2624987053
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4203141359
Short name T388
Test name
Test status
Simulation time 122979771 ps
CPU time 8.14 seconds
Started Jul 11 05:20:06 PM PDT 24
Finished Jul 11 05:20:17 PM PDT 24
Peak memory 250828 kb
Host smart-4c36e84f-7904-44cd-b128-b6d09189b8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203141359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4203141359
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1562990508
Short name T456
Test name
Test status
Simulation time 19343305790 ps
CPU time 169.8 seconds
Started Jul 11 05:20:16 PM PDT 24
Finished Jul 11 05:23:08 PM PDT 24
Peak memory 283664 kb
Host smart-e210d2ff-593b-48a4-a042-3ce4fa173621
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562990508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1562990508
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.862315760
Short name T300
Test name
Test status
Simulation time 127945405 ps
CPU time 0.86 seconds
Started Jul 11 05:20:04 PM PDT 24
Finished Jul 11 05:20:09 PM PDT 24
Peak memory 211712 kb
Host smart-cc288d54-3eb1-4c76-a47c-182c77a02105
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862315760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.862315760
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2701027812
Short name T466
Test name
Test status
Simulation time 15790902 ps
CPU time 0.89 seconds
Started Jul 11 05:20:18 PM PDT 24
Finished Jul 11 05:20:22 PM PDT 24
Peak memory 208916 kb
Host smart-e4c84085-4a61-4e88-a29b-6ae8f6b134f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701027812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2701027812
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.4204579240
Short name T396
Test name
Test status
Simulation time 1773928904 ps
CPU time 11.27 seconds
Started Jul 11 05:20:14 PM PDT 24
Finished Jul 11 05:20:27 PM PDT 24
Peak memory 218140 kb
Host smart-76275f49-4511-4a82-888e-e8849a7f3274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204579240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4204579240
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.290123057
Short name T842
Test name
Test status
Simulation time 581042694 ps
CPU time 2.79 seconds
Started Jul 11 05:20:18 PM PDT 24
Finished Jul 11 05:20:23 PM PDT 24
Peak memory 217052 kb
Host smart-19d20c19-4f8c-4a9a-8244-0ccce54d31b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290123057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.290123057
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1669616306
Short name T284
Test name
Test status
Simulation time 315172676 ps
CPU time 9.38 seconds
Started Jul 11 05:20:20 PM PDT 24
Finished Jul 11 05:20:32 PM PDT 24
Peak memory 223008 kb
Host smart-b2259a1c-a746-4a84-b900-953d64acd044
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669616306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1669616306
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.571261084
Short name T690
Test name
Test status
Simulation time 567759605 ps
CPU time 10.81 seconds
Started Jul 11 05:20:16 PM PDT 24
Finished Jul 11 05:20:28 PM PDT 24
Peak memory 217568 kb
Host smart-552af537-9019-4dde-8689-216048bb5e0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571261084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
571261084
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2901233990
Short name T180
Test name
Test status
Simulation time 1240883445 ps
CPU time 35.18 seconds
Started Jul 11 05:20:27 PM PDT 24
Finished Jul 11 05:21:04 PM PDT 24
Peak memory 250920 kb
Host smart-1e7860a4-dc7e-4cc0-a41a-75e19c98654a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901233990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2901233990
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.143291546
Short name T593
Test name
Test status
Simulation time 1277553255 ps
CPU time 12.54 seconds
Started Jul 11 05:20:12 PM PDT 24
Finished Jul 11 05:20:27 PM PDT 24
Peak memory 250444 kb
Host smart-9ec6c4c5-77d3-45db-b734-c104a3e5012d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143291546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.143291546
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3847959991
Short name T5
Test name
Test status
Simulation time 100522144 ps
CPU time 3.64 seconds
Started Jul 11 05:20:18 PM PDT 24
Finished Jul 11 05:20:24 PM PDT 24
Peak memory 218116 kb
Host smart-0ac19068-a630-404e-b740-0dbc337d5102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847959991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3847959991
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3353634409
Short name T237
Test name
Test status
Simulation time 1755981751 ps
CPU time 13.07 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:39 PM PDT 24
Peak memory 219420 kb
Host smart-15ae4826-b762-43a5-9b51-32d859c43e5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353634409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3353634409
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3581557164
Short name T589
Test name
Test status
Simulation time 274446671 ps
CPU time 11.63 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:37 PM PDT 24
Peak memory 225876 kb
Host smart-27b83249-e330-4b5f-9cf6-1c1b015a94a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581557164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3581557164
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2315394174
Short name T471
Test name
Test status
Simulation time 303809210 ps
CPU time 11.89 seconds
Started Jul 11 05:20:27 PM PDT 24
Finished Jul 11 05:20:41 PM PDT 24
Peak memory 218116 kb
Host smart-31ecb953-310b-4a49-a996-bcd82ebdfd01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315394174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2315394174
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3533019515
Short name T47
Test name
Test status
Simulation time 1423447611 ps
CPU time 9.63 seconds
Started Jul 11 05:20:13 PM PDT 24
Finished Jul 11 05:20:24 PM PDT 24
Peak memory 224808 kb
Host smart-440de3b0-eedc-4e91-ae02-e467cae9ca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533019515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3533019515
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1700790578
Short name T384
Test name
Test status
Simulation time 252587129 ps
CPU time 2.96 seconds
Started Jul 11 05:20:11 PM PDT 24
Finished Jul 11 05:20:16 PM PDT 24
Peak memory 214920 kb
Host smart-5b3348eb-cb31-4cc8-b35f-558ac0486774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700790578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1700790578
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.499225977
Short name T418
Test name
Test status
Simulation time 323794565 ps
CPU time 28 seconds
Started Jul 11 05:20:16 PM PDT 24
Finished Jul 11 05:20:46 PM PDT 24
Peak memory 250820 kb
Host smart-b4716cff-8bee-409f-89fe-6f035d2b1982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499225977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.499225977
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1592617911
Short name T319
Test name
Test status
Simulation time 228570709 ps
CPU time 7.26 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:34 PM PDT 24
Peak memory 250852 kb
Host smart-92eed304-1ff8-418d-b2a3-a936f32d42d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592617911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1592617911
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3079175788
Short name T195
Test name
Test status
Simulation time 6705864708 ps
CPU time 165.99 seconds
Started Jul 11 05:20:22 PM PDT 24
Finished Jul 11 05:23:11 PM PDT 24
Peak memory 276716 kb
Host smart-19f5e762-106a-458f-96a1-2291bf7196e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079175788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3079175788
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3705102803
Short name T560
Test name
Test status
Simulation time 15120928 ps
CPU time 0.92 seconds
Started Jul 11 05:20:13 PM PDT 24
Finished Jul 11 05:20:16 PM PDT 24
Peak memory 211888 kb
Host smart-45d3b4c4-06d9-4efa-8d85-095b123219d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705102803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3705102803
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3440819961
Short name T400
Test name
Test status
Simulation time 49751263 ps
CPU time 0.91 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:27 PM PDT 24
Peak memory 208944 kb
Host smart-54dadba4-14f0-4737-8525-e026c6d38248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440819961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3440819961
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4270416631
Short name T241
Test name
Test status
Simulation time 2287243621 ps
CPU time 16.69 seconds
Started Jul 11 05:20:17 PM PDT 24
Finished Jul 11 05:20:37 PM PDT 24
Peak memory 218236 kb
Host smart-12724b01-6caf-4980-a572-f1e37345863c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270416631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4270416631
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3865150186
Short name T198
Test name
Test status
Simulation time 725113953 ps
CPU time 2.94 seconds
Started Jul 11 05:20:27 PM PDT 24
Finished Jul 11 05:20:32 PM PDT 24
Peak memory 217240 kb
Host smart-12ffaec1-7e1e-4402-be54-cb090327767f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865150186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3865150186
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.373246822
Short name T704
Test name
Test status
Simulation time 2455264972 ps
CPU time 35.11 seconds
Started Jul 11 05:20:43 PM PDT 24
Finished Jul 11 05:21:20 PM PDT 24
Peak memory 225724 kb
Host smart-8903fd0d-c487-4e2f-b4bb-d28969ac2287
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373246822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.373246822
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1382735606
Short name T536
Test name
Test status
Simulation time 2012862052 ps
CPU time 14.98 seconds
Started Jul 11 05:20:25 PM PDT 24
Finished Jul 11 05:20:43 PM PDT 24
Peak memory 218076 kb
Host smart-08d2e997-13c6-4cd8-8262-fe3815ff6d63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382735606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1382735606
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2989441595
Short name T342
Test name
Test status
Simulation time 116331459 ps
CPU time 2.37 seconds
Started Jul 11 05:20:21 PM PDT 24
Finished Jul 11 05:20:25 PM PDT 24
Peak memory 217652 kb
Host smart-4b2b0266-80a9-4475-a429-7f67ebd0810c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989441595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2989441595
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1793285753
Short name T773
Test name
Test status
Simulation time 1632193050 ps
CPU time 45.25 seconds
Started Jul 11 05:20:19 PM PDT 24
Finished Jul 11 05:21:06 PM PDT 24
Peak memory 250836 kb
Host smart-3909faf4-a3a2-416d-8fdc-d2cb46ceb16c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793285753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1793285753
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2351600055
Short name T751
Test name
Test status
Simulation time 717046475 ps
CPU time 15.94 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:42 PM PDT 24
Peak memory 242652 kb
Host smart-5bd4ecb6-1e5e-4b15-a18f-8d2ede656fef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351600055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2351600055
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2980294366
Short name T660
Test name
Test status
Simulation time 296312347 ps
CPU time 2.78 seconds
Started Jul 11 05:20:20 PM PDT 24
Finished Jul 11 05:20:25 PM PDT 24
Peak memory 222064 kb
Host smart-bb565c27-86c7-49aa-aa30-f7f75d293b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980294366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2980294366
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2794574609
Short name T607
Test name
Test status
Simulation time 201918683 ps
CPU time 10.06 seconds
Started Jul 11 05:20:20 PM PDT 24
Finished Jul 11 05:20:33 PM PDT 24
Peak memory 225976 kb
Host smart-4b3e9079-0048-4589-9c40-dfe23edf06a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794574609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2794574609
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2215548205
Short name T554
Test name
Test status
Simulation time 1776769173 ps
CPU time 17.45 seconds
Started Jul 11 05:20:17 PM PDT 24
Finished Jul 11 05:20:36 PM PDT 24
Peak memory 225892 kb
Host smart-5760c4e7-e4f6-4cd6-800a-af50c19722bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215548205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2215548205
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.480634599
Short name T776
Test name
Test status
Simulation time 3386776374 ps
CPU time 12.34 seconds
Started Jul 11 05:20:18 PM PDT 24
Finished Jul 11 05:20:33 PM PDT 24
Peak memory 218892 kb
Host smart-ea1c600c-a213-4e30-a0ca-48dad7589a11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480634599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.480634599
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1120113977
Short name T585
Test name
Test status
Simulation time 5187718405 ps
CPU time 17.92 seconds
Started Jul 11 05:20:17 PM PDT 24
Finished Jul 11 05:20:38 PM PDT 24
Peak memory 225968 kb
Host smart-7d5b2adb-1ab0-4723-98df-3fb5f54d2202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120113977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1120113977
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.860462035
Short name T815
Test name
Test status
Simulation time 2192451147 ps
CPU time 5.84 seconds
Started Jul 11 05:20:21 PM PDT 24
Finished Jul 11 05:20:30 PM PDT 24
Peak memory 217720 kb
Host smart-8287175b-3931-492a-93f4-e05dcbac750b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860462035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.860462035
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1280697998
Short name T449
Test name
Test status
Simulation time 620812033 ps
CPU time 25.94 seconds
Started Jul 11 05:20:18 PM PDT 24
Finished Jul 11 05:20:46 PM PDT 24
Peak memory 250820 kb
Host smart-50ae05c6-8844-4af2-8c42-d5ea646a9466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280697998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1280697998
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1760918358
Short name T591
Test name
Test status
Simulation time 83248968 ps
CPU time 8.08 seconds
Started Jul 11 05:20:19 PM PDT 24
Finished Jul 11 05:20:30 PM PDT 24
Peak memory 250828 kb
Host smart-f0eb9022-8848-48bd-93f1-03c1968716d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760918358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1760918358
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1152551565
Short name T797
Test name
Test status
Simulation time 4096313355 ps
CPU time 123.87 seconds
Started Jul 11 05:20:17 PM PDT 24
Finished Jul 11 05:22:24 PM PDT 24
Peak memory 226016 kb
Host smart-1516d958-b46d-4b23-862b-b8372b937a38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152551565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1152551565
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3201176814
Short name T306
Test name
Test status
Simulation time 14481458 ps
CPU time 1.08 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:28 PM PDT 24
Peak memory 208808 kb
Host smart-617f9332-b42e-4e7d-b3dd-9c2f9eca6401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201176814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3201176814
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2920190003
Short name T792
Test name
Test status
Simulation time 257380957 ps
CPU time 10.75 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:37 PM PDT 24
Peak memory 218196 kb
Host smart-ab482ee1-04bb-4174-8a96-13fba2fd7330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920190003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2920190003
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2909307674
Short name T366
Test name
Test status
Simulation time 43683839 ps
CPU time 1.78 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:27 PM PDT 24
Peak memory 217068 kb
Host smart-dd0a30b0-f745-47f4-b78c-02a397c41d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909307674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2909307674
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1237493576
Short name T272
Test name
Test status
Simulation time 26638176894 ps
CPU time 51.81 seconds
Started Jul 11 05:20:44 PM PDT 24
Finished Jul 11 05:21:38 PM PDT 24
Peak memory 218672 kb
Host smart-f9bb4ef3-de58-4822-9fca-63638d1284c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237493576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1237493576
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1656176996
Short name T557
Test name
Test status
Simulation time 383718042 ps
CPU time 3.68 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:30 PM PDT 24
Peak memory 218164 kb
Host smart-0708250c-5b1b-40ae-85af-db37ba27ecbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656176996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1656176996
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3075745609
Short name T490
Test name
Test status
Simulation time 775030089 ps
CPU time 18.65 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:21:06 PM PDT 24
Peak memory 217580 kb
Host smart-dc474e6f-e94e-41c9-a073-2781ce5cdfd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075745609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3075745609
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.512021868
Short name T771
Test name
Test status
Simulation time 5224635901 ps
CPU time 43.24 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:21:24 PM PDT 24
Peak memory 251848 kb
Host smart-ca3edc9b-4bb3-403a-9580-c61fc4ef6d04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512021868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.512021868
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2227817792
Short name T193
Test name
Test status
Simulation time 691341081 ps
CPU time 17.48 seconds
Started Jul 11 05:20:51 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 250872 kb
Host smart-c4626c75-be33-4e8e-b441-2f0e9420c5a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227817792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2227817792
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1008328922
Short name T588
Test name
Test status
Simulation time 70345088 ps
CPU time 3.45 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:20:51 PM PDT 24
Peak memory 222308 kb
Host smart-29c67a86-6c26-4dae-84a7-8ff534a03dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008328922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1008328922
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2663231603
Short name T352
Test name
Test status
Simulation time 288538117 ps
CPU time 12.13 seconds
Started Jul 11 05:20:31 PM PDT 24
Finished Jul 11 05:20:45 PM PDT 24
Peak memory 225976 kb
Host smart-8b6e90f4-539e-453f-a88d-8cd8c7cf1b2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663231603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2663231603
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.63611471
Short name T442
Test name
Test status
Simulation time 264135573 ps
CPU time 8.94 seconds
Started Jul 11 05:20:24 PM PDT 24
Finished Jul 11 05:20:36 PM PDT 24
Peak memory 218184 kb
Host smart-5e4f2475-58d1-417a-b369-243e9fa158f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63611471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.63611471
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3781197202
Short name T542
Test name
Test status
Simulation time 560955665 ps
CPU time 7.59 seconds
Started Jul 11 05:20:29 PM PDT 24
Finished Jul 11 05:20:38 PM PDT 24
Peak memory 224576 kb
Host smart-64a2ef5d-22de-4828-8e66-7b0bc5cd465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781197202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3781197202
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1927535804
Short name T368
Test name
Test status
Simulation time 28264798 ps
CPU time 1.34 seconds
Started Jul 11 05:20:18 PM PDT 24
Finished Jul 11 05:20:22 PM PDT 24
Peak memory 213640 kb
Host smart-60c67d04-afa4-4825-9d05-bf73735ce14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927535804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1927535804
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3651495963
Short name T693
Test name
Test status
Simulation time 236934134 ps
CPU time 26.86 seconds
Started Jul 11 05:20:44 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 250704 kb
Host smart-9a9637d5-4ff5-403c-9727-f65e003a95d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651495963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3651495963
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.651737172
Short name T787
Test name
Test status
Simulation time 234962662 ps
CPU time 7.28 seconds
Started Jul 11 05:20:30 PM PDT 24
Finished Jul 11 05:20:39 PM PDT 24
Peak memory 250916 kb
Host smart-1fdc1e07-645a-4d0a-b11e-f9c691224cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651737172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.651737172
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3330183066
Short name T688
Test name
Test status
Simulation time 4653710877 ps
CPU time 86.37 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:22:14 PM PDT 24
Peak memory 248396 kb
Host smart-bad07918-495b-4167-b46f-fc5c3d47ca10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330183066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3330183066
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2102933604
Short name T726
Test name
Test status
Simulation time 40022320 ps
CPU time 0.89 seconds
Started Jul 11 05:20:38 PM PDT 24
Finished Jul 11 05:20:41 PM PDT 24
Peak memory 211732 kb
Host smart-081e0093-ff6c-4612-b353-884de0fd2ae5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102933604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2102933604
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.4129821557
Short name T610
Test name
Test status
Simulation time 18039505 ps
CPU time 1.13 seconds
Started Jul 11 05:20:32 PM PDT 24
Finished Jul 11 05:20:35 PM PDT 24
Peak memory 208928 kb
Host smart-65e5407e-dc67-4149-8cbb-b4c3a53b3c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129821557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4129821557
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1988561239
Short name T790
Test name
Test status
Simulation time 403550356 ps
CPU time 12.63 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:20:54 PM PDT 24
Peak memory 225892 kb
Host smart-6e90666d-c558-49f2-aa38-e41547ed4e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988561239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1988561239
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3064929555
Short name T405
Test name
Test status
Simulation time 73496994 ps
CPU time 2.35 seconds
Started Jul 11 05:20:25 PM PDT 24
Finished Jul 11 05:20:30 PM PDT 24
Peak memory 216912 kb
Host smart-9fc24e6d-5b29-4fe8-8e88-2a7fdc82d063
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064929555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3064929555
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.300844687
Short name T608
Test name
Test status
Simulation time 6325226812 ps
CPU time 81.07 seconds
Started Jul 11 05:20:50 PM PDT 24
Finished Jul 11 05:22:15 PM PDT 24
Peak memory 218824 kb
Host smart-282cf6e1-5516-49d6-91a6-61a34a64dff5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300844687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.300844687
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1221510548
Short name T453
Test name
Test status
Simulation time 1255847187 ps
CPU time 7.47 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:20:48 PM PDT 24
Peak memory 218076 kb
Host smart-c895d02b-e83d-4e9f-8e60-2386f0e71642
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221510548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1221510548
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2373454770
Short name T513
Test name
Test status
Simulation time 1258706566 ps
CPU time 7.77 seconds
Started Jul 11 05:20:25 PM PDT 24
Finished Jul 11 05:20:36 PM PDT 24
Peak memory 217980 kb
Host smart-219852f5-151f-4a15-beea-f259855e8de8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373454770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2373454770
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.328845867
Short name T417
Test name
Test status
Simulation time 23547850193 ps
CPU time 55.86 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:21:37 PM PDT 24
Peak memory 252460 kb
Host smart-9ac3a3bf-0d15-41f7-8eac-bd57aaf7e2f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328845867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.328845867
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2184011387
Short name T775
Test name
Test status
Simulation time 747357089 ps
CPU time 14.86 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:41 PM PDT 24
Peak memory 245332 kb
Host smart-4cb7b8e7-1a2a-4d4b-abc8-411c87bba1fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184011387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2184011387
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2533752821
Short name T17
Test name
Test status
Simulation time 1396894643 ps
CPU time 17.68 seconds
Started Jul 11 05:20:31 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 218776 kb
Host smart-d17ccf83-8492-4165-81d4-f1519217e917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533752821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2533752821
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1479188797
Short name T192
Test name
Test status
Simulation time 279822192 ps
CPU time 8.78 seconds
Started Jul 11 05:20:35 PM PDT 24
Finished Jul 11 05:20:46 PM PDT 24
Peak memory 225984 kb
Host smart-7dee46ac-2c8f-4821-9928-cffc24cc60fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479188797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1479188797
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1571576737
Short name T233
Test name
Test status
Simulation time 426893570 ps
CPU time 9.78 seconds
Started Jul 11 05:20:24 PM PDT 24
Finished Jul 11 05:20:37 PM PDT 24
Peak memory 225980 kb
Host smart-4d129022-56d8-4f50-8197-4952c58689e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571576737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1571576737
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.981493612
Short name T782
Test name
Test status
Simulation time 965545074 ps
CPU time 9.19 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 225060 kb
Host smart-79a4cdf4-308e-482a-a79c-5aab558cf373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981493612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.981493612
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.193657047
Short name T333
Test name
Test status
Simulation time 703446819 ps
CPU time 2.25 seconds
Started Jul 11 05:20:50 PM PDT 24
Finished Jul 11 05:20:57 PM PDT 24
Peak memory 217520 kb
Host smart-bba31c93-cb62-4648-9cd3-da148e92588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193657047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.193657047
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.330025590
Short name T253
Test name
Test status
Simulation time 1169481067 ps
CPU time 34.62 seconds
Started Jul 11 05:20:31 PM PDT 24
Finished Jul 11 05:21:08 PM PDT 24
Peak memory 250912 kb
Host smart-61ec3255-d85d-4ce5-8031-23a089fdeb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330025590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.330025590
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3554711363
Short name T624
Test name
Test status
Simulation time 74723542 ps
CPU time 3.1 seconds
Started Jul 11 05:20:50 PM PDT 24
Finished Jul 11 05:20:57 PM PDT 24
Peak memory 226252 kb
Host smart-e914cf1d-4176-41e6-9476-8a6b504a0412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554711363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3554711363
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.392596710
Short name T277
Test name
Test status
Simulation time 20404173701 ps
CPU time 271.48 seconds
Started Jul 11 05:20:26 PM PDT 24
Finished Jul 11 05:25:00 PM PDT 24
Peak memory 283780 kb
Host smart-4dff9c68-bd43-4389-a82a-c9d1db07d1be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392596710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.392596710
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3630395828
Short name T723
Test name
Test status
Simulation time 20067352 ps
CPU time 1.24 seconds
Started Jul 11 05:20:23 PM PDT 24
Finished Jul 11 05:20:28 PM PDT 24
Peak memory 212812 kb
Host smart-464ffbb6-2091-4623-8b62-97aa40b70915
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630395828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3630395828
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.945650265
Short name T162
Test name
Test status
Simulation time 33559771 ps
CPU time 0.99 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:20:42 PM PDT 24
Peak memory 208840 kb
Host smart-d0138732-e37a-40d7-8e9c-a68859ed8f01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945650265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.945650265
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2162663714
Short name T242
Test name
Test status
Simulation time 179805437 ps
CPU time 9.58 seconds
Started Jul 11 05:20:55 PM PDT 24
Finished Jul 11 05:21:11 PM PDT 24
Peak memory 218152 kb
Host smart-6b61e502-7896-4797-9459-c8c388f36583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162663714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2162663714
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.367260375
Short name T455
Test name
Test status
Simulation time 1492830819 ps
CPU time 34.88 seconds
Started Jul 11 05:20:34 PM PDT 24
Finished Jul 11 05:21:10 PM PDT 24
Peak memory 217456 kb
Host smart-dca2901b-71b0-484d-8fc6-fc30628cb875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367260375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.367260375
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3384610058
Short name T21
Test name
Test status
Simulation time 23660068971 ps
CPU time 67.39 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:22:08 PM PDT 24
Peak memory 219836 kb
Host smart-99dca3d5-50ab-4cab-99cf-5c5407b5b761
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384610058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3384610058
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3114697325
Short name T577
Test name
Test status
Simulation time 541598622 ps
CPU time 8.84 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:10 PM PDT 24
Peak memory 224228 kb
Host smart-bcb83012-b6ab-43c7-ab7f-eaa9ff56ea38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114697325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3114697325
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1026452063
Short name T7
Test name
Test status
Simulation time 182372922 ps
CPU time 6.14 seconds
Started Jul 11 05:20:31 PM PDT 24
Finished Jul 11 05:20:39 PM PDT 24
Peak memory 217652 kb
Host smart-5130195c-956d-4293-bbb5-b5d011c0ddec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026452063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1026452063
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2751840775
Short name T467
Test name
Test status
Simulation time 4856322464 ps
CPU time 89.81 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 279720 kb
Host smart-4f86d1b4-f19c-4a30-a26b-6a63cee8a6bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751840775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2751840775
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3066631437
Short name T823
Test name
Test status
Simulation time 1289870883 ps
CPU time 15.32 seconds
Started Jul 11 05:20:35 PM PDT 24
Finished Jul 11 05:20:52 PM PDT 24
Peak memory 250936 kb
Host smart-65ab9eab-0e33-4d02-b0b3-b55557f25d7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066631437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3066631437
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1499401653
Short name T651
Test name
Test status
Simulation time 22386623 ps
CPU time 1.67 seconds
Started Jul 11 05:20:30 PM PDT 24
Finished Jul 11 05:20:34 PM PDT 24
Peak memory 218048 kb
Host smart-82a3eaf2-2770-41e1-9953-e10a29e25079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499401653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1499401653
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1451562981
Short name T724
Test name
Test status
Simulation time 1189801545 ps
CPU time 8.83 seconds
Started Jul 11 05:20:42 PM PDT 24
Finished Jul 11 05:20:53 PM PDT 24
Peak memory 225984 kb
Host smart-c9b03a43-c164-4ed3-a6c0-122989fb55ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451562981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1451562981
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3782723743
Short name T590
Test name
Test status
Simulation time 255175995 ps
CPU time 9.33 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:21:09 PM PDT 24
Peak memory 218088 kb
Host smart-63029566-86e7-42aa-96b2-715db1cf70b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782723743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3782723743
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3119689747
Short name T45
Test name
Test status
Simulation time 2374023871 ps
CPU time 12.67 seconds
Started Jul 11 05:20:52 PM PDT 24
Finished Jul 11 05:21:11 PM PDT 24
Peak memory 225300 kb
Host smart-6d519b4f-3574-4938-b61f-16069ae50243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119689747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3119689747
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.53911309
Short name T413
Test name
Test status
Simulation time 36077219 ps
CPU time 2.29 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:04 PM PDT 24
Peak memory 217760 kb
Host smart-1243ba25-bef7-496d-9742-2e924bb4065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53911309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.53911309
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1724176464
Short name T650
Test name
Test status
Simulation time 722880129 ps
CPU time 22.89 seconds
Started Jul 11 05:20:30 PM PDT 24
Finished Jul 11 05:20:55 PM PDT 24
Peak memory 245564 kb
Host smart-d06edd9c-8c2e-4c0c-8826-40cee8526b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724176464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1724176464
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1877604153
Short name T563
Test name
Test status
Simulation time 607744619 ps
CPU time 3.51 seconds
Started Jul 11 05:20:51 PM PDT 24
Finished Jul 11 05:20:59 PM PDT 24
Peak memory 226236 kb
Host smart-77ad2633-688a-4488-8487-6e8eddd82b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877604153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1877604153
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.560132761
Short name T564
Test name
Test status
Simulation time 4764349105 ps
CPU time 162.01 seconds
Started Jul 11 05:20:52 PM PDT 24
Finished Jul 11 05:23:40 PM PDT 24
Peak memory 269512 kb
Host smart-47c833e9-2a1e-4967-a442-78fdc6635f05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560132761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.560132761
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3881430594
Short name T524
Test name
Test status
Simulation time 65503171 ps
CPU time 0.94 seconds
Started Jul 11 05:20:29 PM PDT 24
Finished Jul 11 05:20:32 PM PDT 24
Peak memory 211768 kb
Host smart-fcdc33aa-0cd8-47a0-8c99-fcb7601d4fef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881430594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3881430594
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4094683970
Short name T314
Test name
Test status
Simulation time 21251497 ps
CPU time 0.99 seconds
Started Jul 11 05:18:51 PM PDT 24
Finished Jul 11 05:18:56 PM PDT 24
Peak memory 208892 kb
Host smart-5a5ea74c-72a8-41c8-83f4-d87b1c58936c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094683970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4094683970
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.4193515750
Short name T65
Test name
Test status
Simulation time 42187240 ps
CPU time 0.95 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:18:54 PM PDT 24
Peak memory 208860 kb
Host smart-aad3849c-7bfc-4687-a897-8a9216f3114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193515750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4193515750
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2248318687
Short name T786
Test name
Test status
Simulation time 1602369251 ps
CPU time 14.86 seconds
Started Jul 11 05:18:53 PM PDT 24
Finished Jul 11 05:19:12 PM PDT 24
Peak memory 225972 kb
Host smart-fb4fef7b-d6a6-448a-96f7-1cab2088ea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248318687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2248318687
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1973419252
Short name T599
Test name
Test status
Simulation time 3182748600 ps
CPU time 8.27 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:02 PM PDT 24
Peak memory 217616 kb
Host smart-8d7a6cb3-165c-471a-a7bf-8eec193c8eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973419252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1973419252
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2711677902
Short name T707
Test name
Test status
Simulation time 4507746492 ps
CPU time 116.73 seconds
Started Jul 11 05:18:56 PM PDT 24
Finished Jul 11 05:20:55 PM PDT 24
Peak memory 220068 kb
Host smart-e9f03e50-914d-43d4-a100-a5ec7e862b17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711677902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2711677902
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3512590618
Short name T379
Test name
Test status
Simulation time 47857217 ps
CPU time 1.35 seconds
Started Jul 11 05:18:53 PM PDT 24
Finished Jul 11 05:18:58 PM PDT 24
Peak memory 217276 kb
Host smart-79a5c180-9a5f-4d89-9b33-3e9760172fbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512590618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
512590618
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.343964824
Short name T316
Test name
Test status
Simulation time 1109094851 ps
CPU time 8.67 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:02 PM PDT 24
Peak memory 222836 kb
Host smart-4105639b-9a75-4a19-a65f-658969f56dd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343964824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.343964824
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4224077036
Short name T810
Test name
Test status
Simulation time 6945113132 ps
CPU time 20.56 seconds
Started Jul 11 05:18:51 PM PDT 24
Finished Jul 11 05:19:16 PM PDT 24
Peak memory 217708 kb
Host smart-c15df10d-8484-426e-a3ce-f56bef50d9ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224077036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4224077036
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1390454223
Short name T357
Test name
Test status
Simulation time 233392967 ps
CPU time 2.25 seconds
Started Jul 11 05:18:52 PM PDT 24
Finished Jul 11 05:18:59 PM PDT 24
Peak memory 217536 kb
Host smart-9ce69b0f-8411-426f-9c6b-1aab91b6c779
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390454223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1390454223
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2598848983
Short name T641
Test name
Test status
Simulation time 1579193631 ps
CPU time 62.08 seconds
Started Jul 11 05:18:52 PM PDT 24
Finished Jul 11 05:19:58 PM PDT 24
Peak memory 275476 kb
Host smart-dab87f09-cdab-4165-8853-a91b79e69319
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598848983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2598848983
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.716084623
Short name T469
Test name
Test status
Simulation time 938122289 ps
CPU time 18.39 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:12 PM PDT 24
Peak memory 250892 kb
Host smart-eae15246-62b0-4853-8c32-67b9a0ebb029
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716084623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.716084623
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1535730620
Short name T235
Test name
Test status
Simulation time 347617796 ps
CPU time 1.96 seconds
Started Jul 11 05:18:54 PM PDT 24
Finished Jul 11 05:18:59 PM PDT 24
Peak memory 218156 kb
Host smart-48222435-a533-4929-817f-2f95be2c6e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535730620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1535730620
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.540863647
Short name T432
Test name
Test status
Simulation time 169087107 ps
CPU time 5.29 seconds
Started Jul 11 05:18:53 PM PDT 24
Finished Jul 11 05:19:02 PM PDT 24
Peak memory 214316 kb
Host smart-66cdb0d6-3e52-4bf0-b023-89314242e823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540863647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.540863647
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1004829222
Short name T48
Test name
Test status
Simulation time 1124374863 ps
CPU time 38.94 seconds
Started Jul 11 05:18:51 PM PDT 24
Finished Jul 11 05:19:33 PM PDT 24
Peak memory 284412 kb
Host smart-f0b53ab7-a7b8-4c9e-88da-f3e94b80bc96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004829222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1004829222
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2159924470
Short name T779
Test name
Test status
Simulation time 390161435 ps
CPU time 12.39 seconds
Started Jul 11 05:18:51 PM PDT 24
Finished Jul 11 05:19:07 PM PDT 24
Peak memory 225976 kb
Host smart-3a61229e-e93e-4016-abda-baf583c03910
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159924470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2159924470
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2763246985
Short name T742
Test name
Test status
Simulation time 1648305095 ps
CPU time 9.37 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:19:02 PM PDT 24
Peak memory 225972 kb
Host smart-17b698de-6868-495b-938c-a8f431dc6f4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763246985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
763246985
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1575644986
Short name T857
Test name
Test status
Simulation time 1188106357 ps
CPU time 8.66 seconds
Started Jul 11 05:18:54 PM PDT 24
Finished Jul 11 05:19:06 PM PDT 24
Peak memory 225984 kb
Host smart-04cfa320-5d79-4489-95dd-a9e30927f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575644986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1575644986
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3901997304
Short name T364
Test name
Test status
Simulation time 64859685 ps
CPU time 1.56 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:18:54 PM PDT 24
Peak memory 213704 kb
Host smart-4b86acac-721a-43b3-999a-799f69879a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901997304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3901997304
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.188516924
Short name T654
Test name
Test status
Simulation time 754776540 ps
CPU time 21.56 seconds
Started Jul 11 05:18:54 PM PDT 24
Finished Jul 11 05:19:19 PM PDT 24
Peak memory 250896 kb
Host smart-1a9ff0e5-e0a5-4063-a83b-1b75276957aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188516924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.188516924
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.826413266
Short name T428
Test name
Test status
Simulation time 49860066 ps
CPU time 3.09 seconds
Started Jul 11 05:18:54 PM PDT 24
Finished Jul 11 05:19:01 PM PDT 24
Peak memory 224080 kb
Host smart-8351d590-3e89-4cd4-ab95-5a88457458f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826413266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.826413266
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3751291700
Short name T496
Test name
Test status
Simulation time 41541772855 ps
CPU time 144.83 seconds
Started Jul 11 05:18:53 PM PDT 24
Finished Jul 11 05:21:22 PM PDT 24
Peak memory 283840 kb
Host smart-5e8edbf7-8585-4622-9700-ce3cee7eca5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751291700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3751291700
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3496566678
Short name T798
Test name
Test status
Simulation time 91538908068 ps
CPU time 250.05 seconds
Started Jul 11 05:18:51 PM PDT 24
Finished Jul 11 05:23:06 PM PDT 24
Peak memory 283760 kb
Host smart-790eb7cb-1852-4f3c-9cc4-4f5ac48daaf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3496566678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3496566678
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.773941017
Short name T625
Test name
Test status
Simulation time 14520729 ps
CPU time 1.12 seconds
Started Jul 11 05:18:50 PM PDT 24
Finished Jul 11 05:18:54 PM PDT 24
Peak memory 211832 kb
Host smart-d6cf30cd-4d80-4baa-9b43-da469d988668
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773941017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.773941017
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1845830473
Short name T59
Test name
Test status
Simulation time 17530910 ps
CPU time 1.13 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:20:48 PM PDT 24
Peak memory 208980 kb
Host smart-1aa13913-c8c2-4ca7-9b0b-8ded0329dabb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845830473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1845830473
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3789943379
Short name T801
Test name
Test status
Simulation time 640077412 ps
CPU time 15.39 seconds
Started Jul 11 05:20:51 PM PDT 24
Finished Jul 11 05:21:11 PM PDT 24
Peak memory 225904 kb
Host smart-2f9e2eb9-9e9f-4afd-a2a8-7f51f37b3c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789943379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3789943379
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4060447740
Short name T175
Test name
Test status
Simulation time 496639622 ps
CPU time 6.43 seconds
Started Jul 11 05:20:38 PM PDT 24
Finished Jul 11 05:20:46 PM PDT 24
Peak memory 217304 kb
Host smart-52d62430-3cdc-4f81-9291-1753246570fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060447740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4060447740
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2480883565
Short name T533
Test name
Test status
Simulation time 71717603 ps
CPU time 3.56 seconds
Started Jul 11 05:20:55 PM PDT 24
Finished Jul 11 05:21:05 PM PDT 24
Peak memory 222404 kb
Host smart-31620478-4934-4c60-b813-d9e8cba75909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480883565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2480883565
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4030659824
Short name T317
Test name
Test status
Simulation time 3133568112 ps
CPU time 19.88 seconds
Started Jul 11 05:20:34 PM PDT 24
Finished Jul 11 05:20:56 PM PDT 24
Peak memory 220532 kb
Host smart-794a08cf-f697-4942-a28b-87efc7f83a4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030659824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4030659824
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3178755164
Short name T793
Test name
Test status
Simulation time 1743685754 ps
CPU time 12.75 seconds
Started Jul 11 05:20:35 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 225876 kb
Host smart-e9e99497-2b44-4376-8684-11af553d74ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178755164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3178755164
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1175698735
Short name T745
Test name
Test status
Simulation time 216974200 ps
CPU time 8.38 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 218160 kb
Host smart-6eaab8c7-4229-49bb-8043-287c2832b73f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175698735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1175698735
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3423998591
Short name T493
Test name
Test status
Simulation time 1575413398 ps
CPU time 10.68 seconds
Started Jul 11 05:20:42 PM PDT 24
Finished Jul 11 05:20:54 PM PDT 24
Peak memory 225404 kb
Host smart-f0fe09cb-69cf-4221-8887-8b262ceacd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423998591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3423998591
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2976107107
Short name T72
Test name
Test status
Simulation time 85757899 ps
CPU time 2.53 seconds
Started Jul 11 05:20:34 PM PDT 24
Finished Jul 11 05:20:37 PM PDT 24
Peak memory 222564 kb
Host smart-1825442b-dc57-4be1-b86f-9420db09c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976107107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2976107107
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2475807685
Short name T669
Test name
Test status
Simulation time 764767792 ps
CPU time 28.97 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:21:09 PM PDT 24
Peak memory 250844 kb
Host smart-541f19c1-6d93-4909-a050-e7891442f780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475807685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2475807685
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2058019154
Short name T225
Test name
Test status
Simulation time 77484248 ps
CPU time 6.03 seconds
Started Jul 11 05:20:35 PM PDT 24
Finished Jul 11 05:20:42 PM PDT 24
Peak memory 246916 kb
Host smart-dd931102-ba47-438a-b152-7baf8257c7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058019154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2058019154
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1343039712
Short name T56
Test name
Test status
Simulation time 7051254103 ps
CPU time 107.81 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:22:49 PM PDT 24
Peak memory 268756 kb
Host smart-4501e676-8e74-45bd-a5ca-30a9a8dfcabf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343039712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1343039712
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1630190593
Short name T695
Test name
Test status
Simulation time 21798386304 ps
CPU time 237.13 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:24:57 PM PDT 24
Peak memory 298344 kb
Host smart-9d6d17aa-2617-40bc-9c48-80730c7a1bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1630190593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1630190593
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2983083149
Short name T587
Test name
Test status
Simulation time 18234381 ps
CPU time 1.02 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:02 PM PDT 24
Peak memory 211832 kb
Host smart-6273556a-b1b2-42a3-b6e8-34f0fc3ec211
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983083149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2983083149
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2895538729
Short name T747
Test name
Test status
Simulation time 41912990 ps
CPU time 0.84 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:20:48 PM PDT 24
Peak memory 208680 kb
Host smart-c7617792-8d12-43fa-b89d-0a52ba950fd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895538729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2895538729
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2067496074
Short name T251
Test name
Test status
Simulation time 274663211 ps
CPU time 14.01 seconds
Started Jul 11 05:20:35 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 225900 kb
Host smart-7db8f081-803d-4c26-b09b-9547f4a129c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067496074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2067496074
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1570235147
Short name T854
Test name
Test status
Simulation time 819715212 ps
CPU time 9.55 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:10 PM PDT 24
Peak memory 217136 kb
Host smart-44df346c-7ee2-41d5-9cc7-44f73dadc3a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570235147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1570235147
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3945403447
Short name T190
Test name
Test status
Simulation time 34089154 ps
CPU time 1.8 seconds
Started Jul 11 05:20:35 PM PDT 24
Finished Jul 11 05:20:39 PM PDT 24
Peak memory 218084 kb
Host smart-8c0b1e81-e702-4419-888b-df14ef6f31ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945403447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3945403447
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2177283135
Short name T369
Test name
Test status
Simulation time 532613147 ps
CPU time 21.73 seconds
Started Jul 11 05:20:41 PM PDT 24
Finished Jul 11 05:21:04 PM PDT 24
Peak memory 218900 kb
Host smart-a4627de7-84f6-408f-801b-fc2964b3990b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177283135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2177283135
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1905040452
Short name T491
Test name
Test status
Simulation time 1222293428 ps
CPU time 13.89 seconds
Started Jul 11 05:20:44 PM PDT 24
Finished Jul 11 05:21:00 PM PDT 24
Peak memory 225956 kb
Host smart-b7746eb6-b7eb-4a53-ad3a-7e8a1f248f55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905040452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1905040452
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.527518742
Short name T738
Test name
Test status
Simulation time 1087261925 ps
CPU time 8.11 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:21:07 PM PDT 24
Peak memory 218140 kb
Host smart-0fcfdf52-53db-4e4c-aa70-eb75df9d8e7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527518742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.527518742
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3285102759
Short name T102
Test name
Test status
Simulation time 1841216387 ps
CPU time 11.72 seconds
Started Jul 11 05:20:42 PM PDT 24
Finished Jul 11 05:20:56 PM PDT 24
Peak memory 218312 kb
Host smart-73d75874-ff6a-4c5c-9016-97e0deeebe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285102759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3285102759
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.598783111
Short name T365
Test name
Test status
Simulation time 139489951 ps
CPU time 2.55 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 214536 kb
Host smart-00c79c82-214a-47be-bb93-bbdc1a7b17ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598783111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.598783111
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3936468760
Short name T717
Test name
Test status
Simulation time 446365397 ps
CPU time 22.6 seconds
Started Jul 11 05:20:55 PM PDT 24
Finished Jul 11 05:21:24 PM PDT 24
Peak memory 250904 kb
Host smart-b087a0c9-186c-4f8b-8415-ebad5e32ad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936468760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3936468760
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.316005489
Short name T475
Test name
Test status
Simulation time 41166255 ps
CPU time 6.09 seconds
Started Jul 11 05:20:42 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 247068 kb
Host smart-f35d7e43-5548-40d2-9fb7-e14c0a237e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316005489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.316005489
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1518897964
Short name T800
Test name
Test status
Simulation time 735656793 ps
CPU time 45.12 seconds
Started Jul 11 05:20:42 PM PDT 24
Finished Jul 11 05:21:28 PM PDT 24
Peak memory 250892 kb
Host smart-b4ce6d37-1ae7-4c97-93d9-9fdc2a63d7d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518897964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1518897964
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.541325855
Short name T159
Test name
Test status
Simulation time 109830614766 ps
CPU time 369.09 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:27:08 PM PDT 24
Peak memory 397532 kb
Host smart-96fe6ef7-808e-4759-a2c8-e29fce3ef4d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=541325855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.541325855
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1195574227
Short name T754
Test name
Test status
Simulation time 40976538 ps
CPU time 0.89 seconds
Started Jul 11 05:20:34 PM PDT 24
Finished Jul 11 05:20:37 PM PDT 24
Peak memory 211832 kb
Host smart-74235451-61bc-48a7-bdb5-6904e340c7d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195574227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1195574227
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4019687957
Short name T86
Test name
Test status
Simulation time 31002841 ps
CPU time 1.11 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:02 PM PDT 24
Peak memory 208956 kb
Host smart-1de8f7b5-0109-4f2a-932b-9a04eea39039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019687957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4019687957
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.817937109
Short name T809
Test name
Test status
Simulation time 2788108805 ps
CPU time 9.89 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:20:57 PM PDT 24
Peak memory 218808 kb
Host smart-c1c78cc4-051e-4cc2-af34-e841fcf5af91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817937109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.817937109
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1927504925
Short name T199
Test name
Test status
Simulation time 328292860 ps
CPU time 9.59 seconds
Started Jul 11 05:20:46 PM PDT 24
Finished Jul 11 05:20:57 PM PDT 24
Peak memory 217172 kb
Host smart-71dea069-c320-47ae-9c8f-4df09c4e4e04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927504925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1927504925
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1152725498
Short name T312
Test name
Test status
Simulation time 70588555 ps
CPU time 3.66 seconds
Started Jul 11 05:21:01 PM PDT 24
Finished Jul 11 05:21:09 PM PDT 24
Peak memory 218164 kb
Host smart-eaa7b8f8-739c-4b49-b5a2-151489840587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152725498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1152725498
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3220885678
Short name T518
Test name
Test status
Simulation time 438690839 ps
CPU time 11.38 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:21:10 PM PDT 24
Peak memory 225940 kb
Host smart-19c76176-7851-4e1e-9016-df4652083097
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220885678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3220885678
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3669996686
Short name T476
Test name
Test status
Simulation time 773632370 ps
CPU time 10.51 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 218104 kb
Host smart-89b22667-7684-44d9-a816-37d91d3f5cf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669996686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3669996686
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.750825929
Short name T182
Test name
Test status
Simulation time 1567353606 ps
CPU time 9.76 seconds
Started Jul 11 05:20:42 PM PDT 24
Finished Jul 11 05:20:54 PM PDT 24
Peak memory 218128 kb
Host smart-88205a3b-b32d-4e08-a51a-23b3d3012c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750825929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.750825929
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2800207198
Short name T75
Test name
Test status
Simulation time 248686960 ps
CPU time 3.56 seconds
Started Jul 11 05:20:49 PM PDT 24
Finished Jul 11 05:20:56 PM PDT 24
Peak memory 217756 kb
Host smart-9424a99f-daf7-4bac-b9a5-b9e8c045561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800207198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2800207198
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.348937732
Short name T722
Test name
Test status
Simulation time 459632557 ps
CPU time 27.84 seconds
Started Jul 11 05:20:43 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 250928 kb
Host smart-4bbcafee-1eb9-44be-8fa4-4b0f0cd798a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348937732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.348937732
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1544730197
Short name T671
Test name
Test status
Simulation time 381959448 ps
CPU time 9.72 seconds
Started Jul 11 05:20:46 PM PDT 24
Finished Jul 11 05:20:58 PM PDT 24
Peak memory 250908 kb
Host smart-9725d125-16af-4495-90a8-50e8af267931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544730197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1544730197
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1623821730
Short name T177
Test name
Test status
Simulation time 37570459223 ps
CPU time 168.92 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:23:36 PM PDT 24
Peak memory 283680 kb
Host smart-f3acfd2f-cc84-4ab6-98de-d2b0d26e23ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623821730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1623821730
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1427214669
Short name T158
Test name
Test status
Simulation time 107237718509 ps
CPU time 632.23 seconds
Started Jul 11 05:20:44 PM PDT 24
Finished Jul 11 05:31:18 PM PDT 24
Peak memory 260772 kb
Host smart-b45807fa-30f7-4958-80a5-ca379aa54bec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1427214669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1427214669
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2551984806
Short name T234
Test name
Test status
Simulation time 19149927 ps
CPU time 0.93 seconds
Started Jul 11 05:20:46 PM PDT 24
Finished Jul 11 05:20:49 PM PDT 24
Peak memory 211812 kb
Host smart-b2d86bc9-0260-4ba4-9eb5-8e4bf7b6b6de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551984806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2551984806
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.406405923
Short name T363
Test name
Test status
Simulation time 592318380 ps
CPU time 11.88 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:15 PM PDT 24
Peak memory 218088 kb
Host smart-b81c425a-d2bd-4335-aaaf-cc87083bd007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406405923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.406405923
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1234545095
Short name T276
Test name
Test status
Simulation time 15893550 ps
CPU time 1.63 seconds
Started Jul 11 05:20:57 PM PDT 24
Finished Jul 11 05:21:05 PM PDT 24
Peak memory 218184 kb
Host smart-1d36177d-c917-4177-9595-1afdc3b643fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234545095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1234545095
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2157924940
Short name T715
Test name
Test status
Simulation time 2477954128 ps
CPU time 15.7 seconds
Started Jul 11 05:20:47 PM PDT 24
Finished Jul 11 05:21:05 PM PDT 24
Peak memory 225968 kb
Host smart-aef932fa-1d62-4e2e-a6e0-455199101137
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157924940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2157924940
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3538041292
Short name T734
Test name
Test status
Simulation time 1016306584 ps
CPU time 19.31 seconds
Started Jul 11 05:20:50 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 225964 kb
Host smart-4955f31f-3991-4847-9672-45a1c14069c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538041292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3538041292
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1939147968
Short name T350
Test name
Test status
Simulation time 549283499 ps
CPU time 10.42 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:21:10 PM PDT 24
Peak memory 225936 kb
Host smart-93c5616a-0f4c-4f51-897e-400932ebeb92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939147968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1939147968
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2026075474
Short name T346
Test name
Test status
Simulation time 731193943 ps
CPU time 9.14 seconds
Started Jul 11 05:21:01 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 225412 kb
Host smart-dd028e75-bc5c-41ab-82fe-52d80bda0e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026075474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2026075474
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.424668979
Short name T385
Test name
Test status
Simulation time 156561784 ps
CPU time 6.75 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:08 PM PDT 24
Peak memory 217616 kb
Host smart-d0c64d80-a5d9-4387-92e8-af591125fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424668979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.424668979
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3419095126
Short name T370
Test name
Test status
Simulation time 297875050 ps
CPU time 24.83 seconds
Started Jul 11 05:20:45 PM PDT 24
Finished Jul 11 05:21:11 PM PDT 24
Peak memory 250840 kb
Host smart-7f58ec17-f287-4fac-8063-53950d4f4d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419095126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3419095126
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3500900497
Short name T522
Test name
Test status
Simulation time 312185302 ps
CPU time 7.84 seconds
Started Jul 11 05:20:42 PM PDT 24
Finished Jul 11 05:20:52 PM PDT 24
Peak memory 250776 kb
Host smart-91fe64ef-40d0-489e-8d94-f2d64969ba83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500900497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3500900497
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.29579444
Short name T503
Test name
Test status
Simulation time 9451192822 ps
CPU time 146.97 seconds
Started Jul 11 05:20:47 PM PDT 24
Finished Jul 11 05:23:16 PM PDT 24
Peak memory 250976 kb
Host smart-00c06b40-c615-4343-97e6-b73e7ba0a351
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29579444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.lc_ctrl_stress_all.29579444
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1123136913
Short name T709
Test name
Test status
Simulation time 11999843387 ps
CPU time 297.31 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:26:15 PM PDT 24
Peak memory 283572 kb
Host smart-0e234cce-14be-4e7b-8308-4d5603427938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1123136913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1123136913
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3595439614
Short name T185
Test name
Test status
Simulation time 23915068 ps
CPU time 1.01 seconds
Started Jul 11 05:20:40 PM PDT 24
Finished Jul 11 05:20:43 PM PDT 24
Peak memory 211720 kb
Host smart-c06ed1b4-b955-49c4-a7bd-71afae98effd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595439614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3595439614
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2848605114
Short name T562
Test name
Test status
Simulation time 20267670 ps
CPU time 0.95 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:22 PM PDT 24
Peak memory 208776 kb
Host smart-97e4087c-7285-472b-b349-1f7a9f4a870a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848605114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2848605114
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2720229509
Short name T303
Test name
Test status
Simulation time 1160143888 ps
CPU time 12.41 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:33 PM PDT 24
Peak memory 217656 kb
Host smart-fb5ccc05-fbf2-462f-b5f0-b0a367c78815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720229509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2720229509
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2507405032
Short name T721
Test name
Test status
Simulation time 168110490 ps
CPU time 2.97 seconds
Started Jul 11 05:20:51 PM PDT 24
Finished Jul 11 05:21:00 PM PDT 24
Peak memory 217000 kb
Host smart-9165290f-0370-4e53-9655-456744f1f338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507405032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2507405032
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1755375715
Short name T356
Test name
Test status
Simulation time 540905272 ps
CPU time 2.49 seconds
Started Jul 11 05:20:50 PM PDT 24
Finished Jul 11 05:20:57 PM PDT 24
Peak memory 218164 kb
Host smart-40c81744-d6e8-46c8-86dc-2925ac7280ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755375715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1755375715
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3965202349
Short name T826
Test name
Test status
Simulation time 1387550791 ps
CPU time 16.74 seconds
Started Jul 11 05:20:49 PM PDT 24
Finished Jul 11 05:21:09 PM PDT 24
Peak memory 218860 kb
Host smart-e47f2fe1-ec0c-4338-bc12-82abc0a61f56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965202349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3965202349
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2661759541
Short name T173
Test name
Test status
Simulation time 4633110793 ps
CPU time 19.89 seconds
Started Jul 11 05:20:47 PM PDT 24
Finished Jul 11 05:21:09 PM PDT 24
Peak memory 226040 kb
Host smart-3af151e3-72c7-4f53-84a8-09e905c7c06e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661759541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2661759541
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.200508956
Short name T389
Test name
Test status
Simulation time 373230603 ps
CPU time 7.96 seconds
Started Jul 11 05:20:48 PM PDT 24
Finished Jul 11 05:20:58 PM PDT 24
Peak memory 225300 kb
Host smart-69d3a95e-1a72-4480-8c98-d18a35ec72f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200508956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.200508956
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1822074571
Short name T807
Test name
Test status
Simulation time 562183271 ps
CPU time 10.93 seconds
Started Jul 11 05:20:52 PM PDT 24
Finished Jul 11 05:21:08 PM PDT 24
Peak memory 225972 kb
Host smart-297dbc79-3ec9-4ec0-b08a-1968ddb7f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822074571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1822074571
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1793190579
Short name T485
Test name
Test status
Simulation time 207732366 ps
CPU time 5.87 seconds
Started Jul 11 05:20:51 PM PDT 24
Finished Jul 11 05:21:02 PM PDT 24
Peak memory 217736 kb
Host smart-44454cea-8e99-4d82-8e39-255201af3e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793190579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1793190579
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.10238063
Short name T304
Test name
Test status
Simulation time 487026398 ps
CPU time 24.43 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:21:42 PM PDT 24
Peak memory 250912 kb
Host smart-063778d0-ab97-4767-8094-926d3826eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10238063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.10238063
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.682180009
Short name T279
Test name
Test status
Simulation time 114041543 ps
CPU time 8.32 seconds
Started Jul 11 05:20:52 PM PDT 24
Finished Jul 11 05:21:06 PM PDT 24
Peak memory 250924 kb
Host smart-5e743d40-e89e-44b7-aed0-a482c5cc9c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682180009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.682180009
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2944775004
Short name T664
Test name
Test status
Simulation time 7638542783 ps
CPU time 250.7 seconds
Started Jul 11 05:20:51 PM PDT 24
Finished Jul 11 05:25:06 PM PDT 24
Peak memory 271004 kb
Host smart-26af8898-0ee5-425f-86f6-71ec1e472f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944775004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2944775004
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1636392164
Short name T410
Test name
Test status
Simulation time 14128437 ps
CPU time 0.93 seconds
Started Jul 11 05:20:51 PM PDT 24
Finished Jul 11 05:20:58 PM PDT 24
Peak memory 212820 kb
Host smart-61f93435-b801-42fc-b503-6cf38f2c72b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636392164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1636392164
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.192682052
Short name T283
Test name
Test status
Simulation time 72362403 ps
CPU time 0.93 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:21:18 PM PDT 24
Peak memory 208392 kb
Host smart-89ebced8-dc01-4078-9ba7-4f5bb26cb474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192682052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.192682052
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1540935185
Short name T12
Test name
Test status
Simulation time 1975668475 ps
CPU time 9.56 seconds
Started Jul 11 05:20:47 PM PDT 24
Finished Jul 11 05:20:58 PM PDT 24
Peak memory 218172 kb
Host smart-e58ae571-89e9-4279-9437-e1656a72a625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540935185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1540935185
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3525822750
Short name T29
Test name
Test status
Simulation time 134000173 ps
CPU time 3.2 seconds
Started Jul 11 05:20:48 PM PDT 24
Finished Jul 11 05:20:54 PM PDT 24
Peak memory 217032 kb
Host smart-986e6dcf-8845-4b9d-8fd8-f423d57cd36f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525822750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3525822750
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.355470328
Short name T246
Test name
Test status
Simulation time 246489370 ps
CPU time 2.54 seconds
Started Jul 11 05:20:48 PM PDT 24
Finished Jul 11 05:20:53 PM PDT 24
Peak memory 222236 kb
Host smart-965d5c5d-ab4d-4620-b58c-7c1721dffdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355470328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.355470328
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3138621073
Short name T731
Test name
Test status
Simulation time 942595981 ps
CPU time 11.08 seconds
Started Jul 11 05:20:48 PM PDT 24
Finished Jul 11 05:21:02 PM PDT 24
Peak memory 225844 kb
Host smart-0b586986-9ada-4595-b0ce-4318050fae18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138621073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3138621073
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.398834978
Short name T414
Test name
Test status
Simulation time 650950756 ps
CPU time 11.55 seconds
Started Jul 11 05:20:49 PM PDT 24
Finished Jul 11 05:21:03 PM PDT 24
Peak memory 218184 kb
Host smart-86b0579f-6abb-4959-a44b-ef6679b82e8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398834978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.398834978
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3553970143
Short name T631
Test name
Test status
Simulation time 3561218374 ps
CPU time 10.2 seconds
Started Jul 11 05:20:49 PM PDT 24
Finished Jul 11 05:21:03 PM PDT 24
Peak memory 226052 kb
Host smart-7e79585a-74f1-4da0-a219-2a21497dc6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553970143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3553970143
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.4207183267
Short name T502
Test name
Test status
Simulation time 360702791 ps
CPU time 1.74 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:22 PM PDT 24
Peak memory 213708 kb
Host smart-214dcaca-437c-42a2-9b58-405791c35f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207183267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.4207183267
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.4231005641
Short name T174
Test name
Test status
Simulation time 516993114 ps
CPU time 24.84 seconds
Started Jul 11 05:20:47 PM PDT 24
Finished Jul 11 05:21:15 PM PDT 24
Peak memory 250908 kb
Host smart-9f9f601d-aa4c-417d-87c1-5eb4ef61e6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231005641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.4231005641
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3218115770
Short name T845
Test name
Test status
Simulation time 228025371 ps
CPU time 2.89 seconds
Started Jul 11 05:20:55 PM PDT 24
Finished Jul 11 05:21:04 PM PDT 24
Peak memory 222460 kb
Host smart-50c13dcb-2c32-4b3a-9e82-8572468652bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218115770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3218115770
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2800742416
Short name T23
Test name
Test status
Simulation time 6669929677 ps
CPU time 120.67 seconds
Started Jul 11 05:20:50 PM PDT 24
Finished Jul 11 05:22:55 PM PDT 24
Peak memory 250976 kb
Host smart-1b64011f-dd44-42ac-8291-c1c9289696f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800742416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2800742416
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.344572185
Short name T575
Test name
Test status
Simulation time 23868851 ps
CPU time 0.93 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:01 PM PDT 24
Peak memory 211784 kb
Host smart-67ff4ff8-207b-4f51-b37e-96ae51f76915
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344572185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.344572185
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1119711566
Short name T260
Test name
Test status
Simulation time 75088631 ps
CPU time 0.99 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:21:00 PM PDT 24
Peak memory 208836 kb
Host smart-581bb22b-4dc2-4161-8703-d9348e21d7b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119711566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1119711566
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2357202324
Short name T677
Test name
Test status
Simulation time 1586195022 ps
CPU time 17.83 seconds
Started Jul 11 05:21:12 PM PDT 24
Finished Jul 11 05:21:34 PM PDT 24
Peak memory 218168 kb
Host smart-fd27dc4e-ec21-455e-9662-344be5163718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357202324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2357202324
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2818935991
Short name T864
Test name
Test status
Simulation time 824559803 ps
CPU time 3.6 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:04 PM PDT 24
Peak memory 217032 kb
Host smart-defbcbf6-5bac-4699-84cb-d85487625918
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818935991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2818935991
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2654779397
Short name T727
Test name
Test status
Simulation time 53423200 ps
CPU time 1.99 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:21:02 PM PDT 24
Peak memory 218132 kb
Host smart-b338cb4b-9180-4e06-970f-1fe3ba07526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654779397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2654779397
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.4202472166
Short name T635
Test name
Test status
Simulation time 283442763 ps
CPU time 14.27 seconds
Started Jul 11 05:21:07 PM PDT 24
Finished Jul 11 05:21:25 PM PDT 24
Peak memory 225956 kb
Host smart-7800a832-50fa-46e5-8ebd-7cc432b13af5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202472166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.4202472166
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.4190114976
Short name T481
Test name
Test status
Simulation time 176558898 ps
CPU time 8.53 seconds
Started Jul 11 05:21:11 PM PDT 24
Finished Jul 11 05:21:24 PM PDT 24
Peak memory 225956 kb
Host smart-a61d3160-16f2-4508-a94c-324fc8e3550e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190114976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.4190114976
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1667551869
Short name T678
Test name
Test status
Simulation time 1573656381 ps
CPU time 9.66 seconds
Started Jul 11 05:21:11 PM PDT 24
Finished Jul 11 05:21:25 PM PDT 24
Peak memory 218160 kb
Host smart-b3356a56-f0eb-4a7d-a0ce-74bd50998661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667551869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1667551869
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3425173114
Short name T855
Test name
Test status
Simulation time 1203803417 ps
CPU time 12.33 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:16 PM PDT 24
Peak memory 225408 kb
Host smart-5e31f6f4-c901-4745-94cd-c9b3df24361d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425173114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3425173114
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2784761460
Short name T340
Test name
Test status
Simulation time 184729413 ps
CPU time 1.41 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:22 PM PDT 24
Peak memory 213688 kb
Host smart-7ca70068-124b-4429-8040-857523e679ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784761460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2784761460
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2870787805
Short name T362
Test name
Test status
Simulation time 693824233 ps
CPU time 23.87 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:45 PM PDT 24
Peak memory 250584 kb
Host smart-7f3f265c-2faf-4da1-987b-391d2f815835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870787805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2870787805
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3598858781
Short name T729
Test name
Test status
Simulation time 548170333 ps
CPU time 8.72 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:21:26 PM PDT 24
Peak memory 250924 kb
Host smart-c14c04d3-005c-4abb-9401-622960ba152a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598858781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3598858781
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1469160078
Short name T109
Test name
Test status
Simulation time 109694303286 ps
CPU time 480.11 seconds
Started Jul 11 05:21:02 PM PDT 24
Finished Jul 11 05:29:07 PM PDT 24
Peak memory 267296 kb
Host smart-60ff1c73-02fa-47d0-a7a1-aa29c104f812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469160078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1469160078
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3346448945
Short name T603
Test name
Test status
Simulation time 33187714335 ps
CPU time 260.66 seconds
Started Jul 11 05:21:09 PM PDT 24
Finished Jul 11 05:25:34 PM PDT 24
Peak memory 281660 kb
Host smart-27dc058e-fc67-4ada-89e9-824fed30f1b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3346448945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3346448945
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.316345957
Short name T445
Test name
Test status
Simulation time 46650997 ps
CPU time 0.89 seconds
Started Jul 11 05:20:47 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 211708 kb
Host smart-1bb81674-f900-4c06-bce6-f0001d548e16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316345957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.316345957
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3384625147
Short name T774
Test name
Test status
Simulation time 104499215 ps
CPU time 1.05 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:21:19 PM PDT 24
Peak memory 208900 kb
Host smart-3b770c8f-c4cb-4757-a702-7d64d8b35822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384625147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3384625147
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1714419376
Short name T243
Test name
Test status
Simulation time 2600796358 ps
CPU time 18.79 seconds
Started Jul 11 05:21:00 PM PDT 24
Finished Jul 11 05:21:23 PM PDT 24
Peak memory 218868 kb
Host smart-786e4d62-086a-42da-9dac-27244b857567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714419376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1714419376
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2923675817
Short name T516
Test name
Test status
Simulation time 57293199 ps
CPU time 1.28 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:21:11 PM PDT 24
Peak memory 217632 kb
Host smart-62d504f2-92d2-4f97-8772-f8e839d5d764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923675817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2923675817
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.117336675
Short name T835
Test name
Test status
Simulation time 89687161 ps
CPU time 2.59 seconds
Started Jul 11 05:20:57 PM PDT 24
Finished Jul 11 05:21:06 PM PDT 24
Peak memory 218012 kb
Host smart-5055463d-8394-4aeb-9b8a-44c268c652ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117336675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.117336675
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3754619453
Short name T255
Test name
Test status
Simulation time 478899186 ps
CPU time 15.21 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:16 PM PDT 24
Peak memory 219392 kb
Host smart-79084f9b-d96c-4841-ad51-659e5d9b006a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754619453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3754619453
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2384316265
Short name T435
Test name
Test status
Simulation time 1915149230 ps
CPU time 11.56 seconds
Started Jul 11 05:20:52 PM PDT 24
Finished Jul 11 05:21:10 PM PDT 24
Peak memory 226064 kb
Host smart-94a0f8c5-7dbb-42c3-a84d-aec7d57cd798
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384316265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2384316265
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.676940362
Short name T510
Test name
Test status
Simulation time 640249175 ps
CPU time 13.58 seconds
Started Jul 11 05:20:55 PM PDT 24
Finished Jul 11 05:21:15 PM PDT 24
Peak memory 218088 kb
Host smart-7077bda8-e921-4ee2-9f7a-4f203a0feb32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676940362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.676940362
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.132915187
Short name T623
Test name
Test status
Simulation time 521350169 ps
CPU time 8.15 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:09 PM PDT 24
Peak memory 218296 kb
Host smart-79032c6e-ab7e-47d7-8810-d5165e3fceb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132915187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.132915187
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1775101042
Short name T559
Test name
Test status
Simulation time 1953177081 ps
CPU time 13.23 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:21:31 PM PDT 24
Peak memory 217664 kb
Host smart-b44bcf4d-8911-4665-8885-ec06f57566f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775101042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1775101042
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3125615352
Short name T416
Test name
Test status
Simulation time 715540193 ps
CPU time 20.94 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:42 PM PDT 24
Peak memory 250828 kb
Host smart-193c26a1-b031-4609-beed-67cc2732b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125615352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3125615352
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3234865242
Short name T653
Test name
Test status
Simulation time 42427101 ps
CPU time 2.96 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:15 PM PDT 24
Peak memory 222272 kb
Host smart-08367913-33e5-4ef0-b20b-94949a1f84ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234865242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3234865242
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3350638465
Short name T580
Test name
Test status
Simulation time 10509170090 ps
CPU time 83.42 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:22:44 PM PDT 24
Peak memory 225884 kb
Host smart-66d9cd77-a4f8-43a0-be33-3f27d890e59f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350638465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3350638465
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3938094739
Short name T348
Test name
Test status
Simulation time 128271725 ps
CPU time 0.98 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 211840 kb
Host smart-138ffd77-1f36-4013-822f-91cc8e57ebb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938094739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3938094739
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2625941224
Short name T504
Test name
Test status
Simulation time 34015288 ps
CPU time 1.04 seconds
Started Jul 11 05:20:57 PM PDT 24
Finished Jul 11 05:21:04 PM PDT 24
Peak memory 208812 kb
Host smart-7abb2b36-aed8-4481-bd50-42c60a1d4bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625941224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2625941224
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.76326761
Short name T452
Test name
Test status
Simulation time 4655420636 ps
CPU time 10.92 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 218356 kb
Host smart-527b721d-f813-4345-8646-c10fbca1efae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76326761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.76326761
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1016784550
Short name T658
Test name
Test status
Simulation time 2026312456 ps
CPU time 6.06 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:21:06 PM PDT 24
Peak memory 217168 kb
Host smart-d2779088-d80f-43a3-9755-23c34c0876e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016784550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1016784550
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2528453685
Short name T847
Test name
Test status
Simulation time 313570614 ps
CPU time 3.74 seconds
Started Jul 11 05:20:55 PM PDT 24
Finished Jul 11 05:21:05 PM PDT 24
Peak memory 218164 kb
Host smart-43a44016-502b-4c68-99db-2166e94a0777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528453685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2528453685
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1867254818
Short name T521
Test name
Test status
Simulation time 753042471 ps
CPU time 10.48 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 225844 kb
Host smart-fc66b4ba-7c5e-4ef4-88f0-48eb6ec03ff3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867254818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1867254818
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1898270889
Short name T832
Test name
Test status
Simulation time 271809766 ps
CPU time 9.02 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:12 PM PDT 24
Peak memory 225896 kb
Host smart-c7a499ee-fbdc-4483-9e9f-753bba6a5d71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898270889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1898270889
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3656960788
Short name T99
Test name
Test status
Simulation time 308830824 ps
CPU time 11.42 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:32 PM PDT 24
Peak memory 218032 kb
Host smart-f3bf5676-839f-406b-9c59-a23efacaf7d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656960788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3656960788
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3783161728
Short name T168
Test name
Test status
Simulation time 3203425372 ps
CPU time 10.14 seconds
Started Jul 11 05:20:57 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 225960 kb
Host smart-955e42b4-6d07-4795-a52d-d6f26eae75a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783161728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3783161728
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1343229
Short name T77
Test name
Test status
Simulation time 105710880 ps
CPU time 2.28 seconds
Started Jul 11 05:20:59 PM PDT 24
Finished Jul 11 05:21:06 PM PDT 24
Peak memory 217624 kb
Host smart-322acbf5-d56c-4a68-b030-942194c6591d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1343229
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1713448866
Short name T584
Test name
Test status
Simulation time 172570698 ps
CPU time 20.33 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:21 PM PDT 24
Peak memory 250928 kb
Host smart-25d2cea2-2f1a-4a0b-8e35-b467fc6f2ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713448866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1713448866
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1214140917
Short name T656
Test name
Test status
Simulation time 91368137 ps
CPU time 8.25 seconds
Started Jul 11 05:20:57 PM PDT 24
Finished Jul 11 05:21:11 PM PDT 24
Peak memory 250924 kb
Host smart-64a267f2-5973-4e8a-98dd-ba21643e554c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214140917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1214140917
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.476298527
Short name T495
Test name
Test status
Simulation time 31815150903 ps
CPU time 93.32 seconds
Started Jul 11 05:21:07 PM PDT 24
Finished Jul 11 05:22:45 PM PDT 24
Peak memory 267828 kb
Host smart-488dbd95-a6a3-4360-af4e-d7bddd69bbcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476298527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.476298527
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2196530971
Short name T94
Test name
Test status
Simulation time 314615520568 ps
CPU time 491.05 seconds
Started Jul 11 05:20:57 PM PDT 24
Finished Jul 11 05:29:14 PM PDT 24
Peak memory 349416 kb
Host smart-29dada19-3e22-49e2-aaf9-e9d498ca2cd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2196530971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2196530971
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1119426205
Short name T750
Test name
Test status
Simulation time 22470116 ps
CPU time 0.87 seconds
Started Jul 11 05:20:54 PM PDT 24
Finished Jul 11 05:21:01 PM PDT 24
Peak memory 211712 kb
Host smart-b6fb6fd6-853c-4134-8a8e-d6b197722b76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119426205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1119426205
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3963469362
Short name T761
Test name
Test status
Simulation time 23142097 ps
CPU time 0.83 seconds
Started Jul 11 05:21:01 PM PDT 24
Finished Jul 11 05:21:06 PM PDT 24
Peak memory 208656 kb
Host smart-73c46ba5-fbe4-4a58-bdfe-eb8934c7b5e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963469362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3963469362
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.710114139
Short name T293
Test name
Test status
Simulation time 1705803296 ps
CPU time 17.02 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:21:27 PM PDT 24
Peak memory 218124 kb
Host smart-3d2ac2ad-de2c-4c2b-bf90-baaa86c49b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710114139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.710114139
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2298691599
Short name T391
Test name
Test status
Simulation time 4014481792 ps
CPU time 15.73 seconds
Started Jul 11 05:21:01 PM PDT 24
Finished Jul 11 05:21:21 PM PDT 24
Peak memory 217708 kb
Host smart-d4d18e4e-2cb9-48d4-b499-eec9912be33a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298691599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2298691599
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3976602278
Short name T266
Test name
Test status
Simulation time 240469930 ps
CPU time 1.89 seconds
Started Jul 11 05:20:55 PM PDT 24
Finished Jul 11 05:21:03 PM PDT 24
Peak memory 221996 kb
Host smart-327d9477-b08a-4414-a1e7-671a9f1babd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976602278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3976602278
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1277088794
Short name T757
Test name
Test status
Simulation time 1407191368 ps
CPU time 13.97 seconds
Started Jul 11 05:21:03 PM PDT 24
Finished Jul 11 05:21:21 PM PDT 24
Peak memory 225960 kb
Host smart-cd43987a-5621-43bb-af01-36170dc6c633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277088794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1277088794
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.4022407049
Short name T324
Test name
Test status
Simulation time 276115424 ps
CPU time 7.4 seconds
Started Jul 11 05:21:04 PM PDT 24
Finished Jul 11 05:21:15 PM PDT 24
Peak memory 225984 kb
Host smart-825cf728-7c33-42a7-b2e7-ffa9f4ef010c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022407049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.4022407049
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3103770251
Short name T642
Test name
Test status
Simulation time 2006076567 ps
CPU time 10.03 seconds
Started Jul 11 05:21:04 PM PDT 24
Finished Jul 11 05:21:18 PM PDT 24
Peak memory 218184 kb
Host smart-ed202091-d0ba-4c8d-beef-b0a89c4f97e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103770251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3103770251
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1393000946
Short name T769
Test name
Test status
Simulation time 614508352 ps
CPU time 9.32 seconds
Started Jul 11 05:21:01 PM PDT 24
Finished Jul 11 05:21:15 PM PDT 24
Peak memory 225896 kb
Host smart-f5624a53-33a8-4379-aa33-ddf1550350da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393000946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1393000946
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2376191799
Short name T718
Test name
Test status
Simulation time 844011084 ps
CPU time 3.01 seconds
Started Jul 11 05:21:07 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 223584 kb
Host smart-687fe8a1-cf42-4f0d-95d0-a6a090b3119c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376191799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2376191799
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2013398737
Short name T430
Test name
Test status
Simulation time 274232097 ps
CPU time 26.53 seconds
Started Jul 11 05:20:53 PM PDT 24
Finished Jul 11 05:21:27 PM PDT 24
Peak memory 250964 kb
Host smart-709bb955-3ff5-4b71-9082-fccf877bf772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013398737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2013398737
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.810898564
Short name T802
Test name
Test status
Simulation time 87934582 ps
CPU time 9.71 seconds
Started Jul 11 05:20:58 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 250780 kb
Host smart-dbf0bc6f-b570-4b2d-bf0d-4f395d59d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810898564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.810898564
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.152862452
Short name T62
Test name
Test status
Simulation time 16657544815 ps
CPU time 471.08 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:29:00 PM PDT 24
Peak memory 250912 kb
Host smart-c4c3b278-ca92-4a4f-b472-7f7f221a3859
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152862452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.152862452
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.934223491
Short name T1
Test name
Test status
Simulation time 12400953 ps
CPU time 1 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 211828 kb
Host smart-a8459722-96ec-4d16-9fcd-c9aea62aca93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934223491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.934223491
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2535286372
Short name T423
Test name
Test status
Simulation time 107856120 ps
CPU time 0.96 seconds
Started Jul 11 05:19:07 PM PDT 24
Finished Jul 11 05:19:12 PM PDT 24
Peak memory 208816 kb
Host smart-49899620-37d1-4e47-9f98-104f5d2ec45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535286372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2535286372
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3852036914
Short name T218
Test name
Test status
Simulation time 113451124 ps
CPU time 0.83 seconds
Started Jul 11 05:19:03 PM PDT 24
Finished Jul 11 05:19:06 PM PDT 24
Peak memory 208784 kb
Host smart-10e62fad-cd0c-432b-8271-a31dc30ff43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852036914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3852036914
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3823275258
Short name T458
Test name
Test status
Simulation time 391443655 ps
CPU time 13.45 seconds
Started Jul 11 05:20:39 PM PDT 24
Finished Jul 11 05:20:54 PM PDT 24
Peak memory 218176 kb
Host smart-59147b0e-41ec-4be4-9274-6f163a0c49b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823275258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3823275258
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3951346024
Short name T383
Test name
Test status
Simulation time 396990696 ps
CPU time 5.53 seconds
Started Jul 11 05:19:04 PM PDT 24
Finished Jul 11 05:19:14 PM PDT 24
Peak memory 217416 kb
Host smart-a16d02e6-369c-4597-98c7-c57958e5eab8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951346024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3951346024
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2367252127
Short name T301
Test name
Test status
Simulation time 1091836029 ps
CPU time 22.47 seconds
Started Jul 11 05:19:08 PM PDT 24
Finished Jul 11 05:19:34 PM PDT 24
Peak memory 225932 kb
Host smart-a4ef911c-b2b4-42e5-856e-637e09325721
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367252127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2367252127
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.812918394
Short name T282
Test name
Test status
Simulation time 4694047434 ps
CPU time 16.95 seconds
Started Jul 11 05:19:04 PM PDT 24
Finished Jul 11 05:19:25 PM PDT 24
Peak memory 217648 kb
Host smart-74b65ba3-a4b7-4331-b712-94433ea1bf6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812918394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.812918394
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2601668402
Short name T829
Test name
Test status
Simulation time 137434630 ps
CPU time 1.95 seconds
Started Jul 11 05:19:06 PM PDT 24
Finished Jul 11 05:19:12 PM PDT 24
Peak memory 221404 kb
Host smart-f942fb88-f3ef-4849-9744-82071825993d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601668402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2601668402
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3998087677
Short name T373
Test name
Test status
Simulation time 4923871916 ps
CPU time 21.92 seconds
Started Jul 11 05:19:05 PM PDT 24
Finished Jul 11 05:19:31 PM PDT 24
Peak memory 217748 kb
Host smart-86eca2cc-13ad-4b46-ac5f-195a980a82ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998087677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3998087677
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2558420602
Short name T817
Test name
Test status
Simulation time 216088556 ps
CPU time 7.56 seconds
Started Jul 11 05:19:04 PM PDT 24
Finished Jul 11 05:19:15 PM PDT 24
Peak memory 217524 kb
Host smart-cb834546-f7ee-42c7-9f39-8b98fb7a2b55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558420602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2558420602
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3394756265
Short name T508
Test name
Test status
Simulation time 2134249176 ps
CPU time 73.96 seconds
Started Jul 11 05:19:06 PM PDT 24
Finished Jul 11 05:20:24 PM PDT 24
Peak memory 275516 kb
Host smart-4ad937ce-7757-4795-966f-ca36beed0533
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394756265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3394756265
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2517682174
Short name T484
Test name
Test status
Simulation time 1159477659 ps
CPU time 32.76 seconds
Started Jul 11 05:19:08 PM PDT 24
Finished Jul 11 05:19:44 PM PDT 24
Peak memory 226344 kb
Host smart-c44cadd6-d0ed-49e9-84cd-e6d5ccc522e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517682174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2517682174
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1466740526
Short name T169
Test name
Test status
Simulation time 124556613 ps
CPU time 2.79 seconds
Started Jul 11 05:19:03 PM PDT 24
Finished Jul 11 05:19:09 PM PDT 24
Peak memory 218168 kb
Host smart-3c2246cc-0b14-4408-8ea0-570afaa101d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466740526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1466740526
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3537088773
Short name T863
Test name
Test status
Simulation time 206154148 ps
CPU time 8.05 seconds
Started Jul 11 05:19:08 PM PDT 24
Finished Jul 11 05:19:19 PM PDT 24
Peak memory 217520 kb
Host smart-1107ae5f-fef3-4771-aa61-b49da7a1a865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537088773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3537088773
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2153421067
Short name T82
Test name
Test status
Simulation time 640121794 ps
CPU time 36.58 seconds
Started Jul 11 05:19:08 PM PDT 24
Finished Jul 11 05:19:48 PM PDT 24
Peak memory 281976 kb
Host smart-df554f58-d7ea-4ccd-8fbf-e8573d08ea42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153421067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2153421067
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.907441946
Short name T547
Test name
Test status
Simulation time 349899511 ps
CPU time 12.3 seconds
Started Jul 11 05:19:06 PM PDT 24
Finished Jul 11 05:19:22 PM PDT 24
Peak memory 225868 kb
Host smart-7213e252-142a-477a-82c0-18249ff4f596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907441946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.907441946
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.952265636
Short name T406
Test name
Test status
Simulation time 1470924071 ps
CPU time 11.45 seconds
Started Jul 11 05:19:06 PM PDT 24
Finished Jul 11 05:19:21 PM PDT 24
Peak memory 225964 kb
Host smart-701dd22f-35ad-45fd-b8e0-82c2c4e518e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952265636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.952265636
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2672064248
Short name T54
Test name
Test status
Simulation time 1874611197 ps
CPU time 9.97 seconds
Started Jul 11 05:19:06 PM PDT 24
Finished Jul 11 05:19:20 PM PDT 24
Peak memory 218172 kb
Host smart-a7b106c0-0efd-49e1-90b4-6c4dc0b3b63c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672064248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
672064248
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1530563953
Short name T51
Test name
Test status
Simulation time 6292239688 ps
CPU time 7.56 seconds
Started Jul 11 05:19:09 PM PDT 24
Finished Jul 11 05:19:19 PM PDT 24
Peak memory 225964 kb
Host smart-2d060fbd-849a-45bc-9be2-82bf431a185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530563953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1530563953
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4209131377
Short name T866
Test name
Test status
Simulation time 102929923 ps
CPU time 1.39 seconds
Started Jul 11 05:18:49 PM PDT 24
Finished Jul 11 05:18:51 PM PDT 24
Peak memory 213832 kb
Host smart-3bb7ec77-4cbd-41d1-a90d-8071a0984b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209131377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4209131377
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.774607052
Short name T472
Test name
Test status
Simulation time 330188246 ps
CPU time 29.95 seconds
Started Jul 11 05:18:52 PM PDT 24
Finished Jul 11 05:19:26 PM PDT 24
Peak memory 247108 kb
Host smart-a6d97b0b-229e-4d03-90ac-5a5bad3ab7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774607052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.774607052
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.4224963722
Short name T602
Test name
Test status
Simulation time 335116972 ps
CPU time 8.23 seconds
Started Jul 11 05:19:05 PM PDT 24
Finished Jul 11 05:19:16 PM PDT 24
Peak memory 250920 kb
Host smart-ac8e64fd-27b8-4800-bf4d-75b13c34e428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224963722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4224963722
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1190893814
Short name T61
Test name
Test status
Simulation time 2347388737 ps
CPU time 42.21 seconds
Started Jul 11 05:19:03 PM PDT 24
Finished Jul 11 05:19:46 PM PDT 24
Peak memory 250764 kb
Host smart-3a590624-da12-4656-8185-59876fe20290
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190893814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1190893814
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.686545988
Short name T308
Test name
Test status
Simulation time 23259871 ps
CPU time 0.9 seconds
Started Jul 11 05:18:49 PM PDT 24
Finished Jul 11 05:18:51 PM PDT 24
Peak memory 211860 kb
Host smart-fe4a673b-4c03-4b46-9d0f-6892f801d5a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686545988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.686545988
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.395423185
Short name T85
Test name
Test status
Simulation time 55199870 ps
CPU time 1 seconds
Started Jul 11 05:21:05 PM PDT 24
Finished Jul 11 05:21:10 PM PDT 24
Peak memory 208900 kb
Host smart-bedd46e4-89d4-419c-ab34-05582d455bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395423185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.395423185
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2660385609
Short name T645
Test name
Test status
Simulation time 310806662 ps
CPU time 9.63 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:21 PM PDT 24
Peak memory 226052 kb
Host smart-1798f1d9-199a-40cf-9818-f2b7ea632f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660385609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2660385609
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3240952391
Short name T794
Test name
Test status
Simulation time 1655629767 ps
CPU time 9.57 seconds
Started Jul 11 05:21:26 PM PDT 24
Finished Jul 11 05:21:38 PM PDT 24
Peak memory 217616 kb
Host smart-874a57c2-4415-451d-9f02-b6a663423378
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240952391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3240952391
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1368067934
Short name T749
Test name
Test status
Simulation time 1022154429 ps
CPU time 4.39 seconds
Started Jul 11 05:21:12 PM PDT 24
Finished Jul 11 05:21:21 PM PDT 24
Peak memory 222284 kb
Host smart-b1e8c7b2-a1a9-48d0-b375-e89d01bcaf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368067934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1368067934
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.128169650
Short name T619
Test name
Test status
Simulation time 247673220 ps
CPU time 11.4 seconds
Started Jul 11 05:21:16 PM PDT 24
Finished Jul 11 05:21:31 PM PDT 24
Peak memory 225956 kb
Host smart-6e3dbceb-9d6a-43a1-b3bb-b14f61519c54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128169650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.128169650
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1324651029
Short name T477
Test name
Test status
Simulation time 409593750 ps
CPU time 10.78 seconds
Started Jul 11 05:21:15 PM PDT 24
Finished Jul 11 05:21:29 PM PDT 24
Peak memory 225912 kb
Host smart-bcb4da69-c4ba-43c4-9e7a-39f60cf7b809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324651029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1324651029
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.162368512
Short name T318
Test name
Test status
Simulation time 3197512727 ps
CPU time 6.44 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:18 PM PDT 24
Peak memory 225988 kb
Host smart-727a7690-57a2-4422-a834-b6cd4574af4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162368512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.162368512
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4003736965
Short name T777
Test name
Test status
Simulation time 709281590 ps
CPU time 8.61 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:21:19 PM PDT 24
Peak memory 225184 kb
Host smart-b35189af-eb5f-4f47-9108-14c5ce127855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003736965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4003736965
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1728938021
Short name T74
Test name
Test status
Simulation time 22904753 ps
CPU time 1.66 seconds
Started Jul 11 05:21:00 PM PDT 24
Finished Jul 11 05:21:07 PM PDT 24
Peak memory 214136 kb
Host smart-2ae0b412-7e3e-40e1-adf6-895b8bf0a3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728938021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1728938021
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3248910463
Short name T32
Test name
Test status
Simulation time 2306557447 ps
CPU time 24.91 seconds
Started Jul 11 05:21:12 PM PDT 24
Finished Jul 11 05:21:41 PM PDT 24
Peak memory 250912 kb
Host smart-6515a225-ccfb-49a0-8eb5-6ec5d8ba772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248910463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3248910463
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3226406357
Short name T402
Test name
Test status
Simulation time 67201716 ps
CPU time 3.84 seconds
Started Jul 11 05:21:05 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 222228 kb
Host smart-a7b58b38-4719-4981-9aed-4318819026d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226406357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3226406357
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.286641361
Short name T544
Test name
Test status
Simulation time 2119982804 ps
CPU time 32.18 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:21:42 PM PDT 24
Peak memory 225964 kb
Host smart-26787c85-292c-459e-be5b-55cf30188241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286641361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.286641361
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.808549379
Short name T672
Test name
Test status
Simulation time 9962723769 ps
CPU time 349.49 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:27:01 PM PDT 24
Peak memory 372888 kb
Host smart-17e59651-9d65-43ad-8f6b-585f2e2db6e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=808549379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.808549379
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.419480198
Short name T326
Test name
Test status
Simulation time 22220498 ps
CPU time 0.86 seconds
Started Jul 11 05:21:04 PM PDT 24
Finished Jul 11 05:21:09 PM PDT 24
Peak memory 211748 kb
Host smart-643eb8d3-1964-4c19-b96d-783d76da07bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419480198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.419480198
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1117914099
Short name T84
Test name
Test status
Simulation time 14271058 ps
CPU time 1.03 seconds
Started Jul 11 05:21:07 PM PDT 24
Finished Jul 11 05:21:12 PM PDT 24
Peak memory 208924 kb
Host smart-49768c82-93fb-4c8f-8843-b88ec357b178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117914099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1117914099
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.674149008
Short name T702
Test name
Test status
Simulation time 1578271996 ps
CPU time 16.97 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:30 PM PDT 24
Peak memory 218084 kb
Host smart-336ac465-0153-448d-954f-98b82b0d153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674149008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.674149008
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2558021993
Short name T30
Test name
Test status
Simulation time 893976348 ps
CPU time 11.64 seconds
Started Jul 11 05:21:07 PM PDT 24
Finished Jul 11 05:21:22 PM PDT 24
Peak memory 217416 kb
Host smart-5283fa00-b670-466c-b627-d44db86f9290
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558021993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2558021993
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3958605660
Short name T20
Test name
Test status
Simulation time 70637118 ps
CPU time 3.67 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 218164 kb
Host smart-543afc79-40cc-4b0a-89c8-547b8cd94fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958605660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3958605660
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2736683726
Short name T395
Test name
Test status
Simulation time 1480819401 ps
CPU time 14.11 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:34 PM PDT 24
Peak memory 225980 kb
Host smart-389a47c7-fae2-4248-bc5d-fc248f3bf393
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736683726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2736683726
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1941654916
Short name T336
Test name
Test status
Simulation time 929530763 ps
CPU time 10.05 seconds
Started Jul 11 05:21:05 PM PDT 24
Finished Jul 11 05:21:19 PM PDT 24
Peak memory 218176 kb
Host smart-8a6e760d-653e-4b2c-a994-d0c155eea644
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941654916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1941654916
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.507735399
Short name T44
Test name
Test status
Simulation time 1613287094 ps
CPU time 11.18 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:24 PM PDT 24
Peak memory 224824 kb
Host smart-07b2387d-4bed-4828-8c73-783691b8ae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507735399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.507735399
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3986844526
Short name T685
Test name
Test status
Simulation time 46409656 ps
CPU time 1.98 seconds
Started Jul 11 05:21:07 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 217548 kb
Host smart-e7eafbe7-e3fd-4130-8a9f-ddb5358dc00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986844526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3986844526
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.620113547
Short name T269
Test name
Test status
Simulation time 840337309 ps
CPU time 24.09 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:36 PM PDT 24
Peak memory 245276 kb
Host smart-2499fde5-c973-4d14-b306-270986780f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620113547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.620113547
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1534368708
Short name T474
Test name
Test status
Simulation time 391268245 ps
CPU time 3.62 seconds
Started Jul 11 05:21:05 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 226324 kb
Host smart-692fccf3-1907-40a2-988d-695e3dc5fc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534368708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1534368708
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1271349278
Short name T90
Test name
Test status
Simulation time 74311028742 ps
CPU time 374.09 seconds
Started Jul 11 05:21:27 PM PDT 24
Finished Jul 11 05:27:44 PM PDT 24
Peak memory 273644 kb
Host smart-891ea77b-fa22-4a33-8320-f656652b2c7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271349278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1271349278
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3652925413
Short name T321
Test name
Test status
Simulation time 23739136 ps
CPU time 0.91 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:13 PM PDT 24
Peak memory 211736 kb
Host smart-14cb7f3d-69c7-431c-a3e5-6fae011139b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652925413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3652925413
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3339736956
Short name T437
Test name
Test status
Simulation time 31119515 ps
CPU time 0.92 seconds
Started Jul 11 05:21:16 PM PDT 24
Finished Jul 11 05:21:20 PM PDT 24
Peak memory 208956 kb
Host smart-bd15b290-a801-4f6f-ad3e-e8c274fe9ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339736956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3339736956
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3352091613
Short name T231
Test name
Test status
Simulation time 820294433 ps
CPU time 13.86 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:27 PM PDT 24
Peak memory 225904 kb
Host smart-2c2ef61c-0a6b-4fe8-a2e4-429cda91c1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352091613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3352091613
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3949348264
Short name T778
Test name
Test status
Simulation time 4220145283 ps
CPU time 9.59 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:21:20 PM PDT 24
Peak memory 217900 kb
Host smart-11ec2b1d-9808-49fb-b287-101c86c71ca3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949348264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3949348264
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.477049706
Short name T762
Test name
Test status
Simulation time 65667607 ps
CPU time 3.37 seconds
Started Jul 11 05:21:12 PM PDT 24
Finished Jul 11 05:21:20 PM PDT 24
Peak memory 222352 kb
Host smart-8f5549f4-aa6c-4928-aa88-4ae7a159d8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477049706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.477049706
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4178176750
Short name T740
Test name
Test status
Simulation time 3810766353 ps
CPU time 20.51 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:32 PM PDT 24
Peak memory 226048 kb
Host smart-48da7052-8316-4f39-8b79-ff6368130dd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178176750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4178176750
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2064795044
Short name T479
Test name
Test status
Simulation time 433562435 ps
CPU time 12.14 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:21:22 PM PDT 24
Peak memory 225980 kb
Host smart-2923579c-6d78-4fa4-9c4e-bf5c599e0c04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064795044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2064795044
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1326432398
Short name T666
Test name
Test status
Simulation time 342835010 ps
CPU time 10.3 seconds
Started Jul 11 05:21:07 PM PDT 24
Finished Jul 11 05:21:22 PM PDT 24
Peak memory 218076 kb
Host smart-9bb0a748-fb17-4a7e-9764-12fa2dce2892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326432398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1326432398
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.94451908
Short name T831
Test name
Test status
Simulation time 677547885 ps
CPU time 12.8 seconds
Started Jul 11 05:21:09 PM PDT 24
Finished Jul 11 05:21:27 PM PDT 24
Peak memory 224964 kb
Host smart-b793493f-27b0-403d-9cf1-300ed6dd8233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94451908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.94451908
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3717986958
Short name T70
Test name
Test status
Simulation time 28965018 ps
CPU time 1.65 seconds
Started Jul 11 05:21:08 PM PDT 24
Finished Jul 11 05:21:14 PM PDT 24
Peak memory 213844 kb
Host smart-d853a574-8b08-4e95-8e85-5f9dd1cb8a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717986958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3717986958
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1907657554
Short name T568
Test name
Test status
Simulation time 1281848053 ps
CPU time 28.13 seconds
Started Jul 11 05:21:06 PM PDT 24
Finished Jul 11 05:21:38 PM PDT 24
Peak memory 250836 kb
Host smart-50f29b0c-8166-4a78-a003-74142c76a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907657554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1907657554
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.256897902
Short name T796
Test name
Test status
Simulation time 131376888 ps
CPU time 3.81 seconds
Started Jul 11 05:21:09 PM PDT 24
Finished Jul 11 05:21:17 PM PDT 24
Peak memory 218120 kb
Host smart-6a0e2cc8-1e47-4c75-9520-151ca846b7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256897902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.256897902
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1996739566
Short name T105
Test name
Test status
Simulation time 5390369764 ps
CPU time 48.25 seconds
Started Jul 11 05:21:13 PM PDT 24
Finished Jul 11 05:22:05 PM PDT 24
Peak memory 250844 kb
Host smart-9e557e52-2d04-4b1a-81d6-2b2b2b659b04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996739566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1996739566
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.4083603724
Short name T735
Test name
Test status
Simulation time 15135436990 ps
CPU time 87.77 seconds
Started Jul 11 05:21:16 PM PDT 24
Finished Jul 11 05:22:47 PM PDT 24
Peak memory 259388 kb
Host smart-f045784a-12af-47f5-8ada-33d2358c71a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4083603724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.4083603724
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1756354310
Short name T708
Test name
Test status
Simulation time 50296940 ps
CPU time 0.95 seconds
Started Jul 11 05:21:09 PM PDT 24
Finished Jul 11 05:21:15 PM PDT 24
Peak memory 211908 kb
Host smart-159b619f-1732-4487-913d-ed019e156377
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756354310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1756354310
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.964399640
Short name T278
Test name
Test status
Simulation time 59563236 ps
CPU time 1.03 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:47 PM PDT 24
Peak memory 208832 kb
Host smart-bad5f517-8af4-4d33-9b90-ad4de643fb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964399640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.964399640
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.548857717
Short name T36
Test name
Test status
Simulation time 7352933310 ps
CPU time 12.3 seconds
Started Jul 11 05:21:26 PM PDT 24
Finished Jul 11 05:21:41 PM PDT 24
Peak memory 226024 kb
Host smart-46b8481f-9987-4aba-90e0-4c6d959abb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548857717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.548857717
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2973159810
Short name T343
Test name
Test status
Simulation time 101490614 ps
CPU time 1.83 seconds
Started Jul 11 05:21:10 PM PDT 24
Finished Jul 11 05:21:16 PM PDT 24
Peak memory 217012 kb
Host smart-3f4bb039-86c4-4e33-8795-6a6f5f6697e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973159810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2973159810
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3705102011
Short name T725
Test name
Test status
Simulation time 61759343 ps
CPU time 2.7 seconds
Started Jul 11 05:21:26 PM PDT 24
Finished Jul 11 05:21:31 PM PDT 24
Peak memory 222396 kb
Host smart-19d02f75-d352-4efe-b0e7-275e255ec167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705102011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3705102011
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2858143854
Short name T238
Test name
Test status
Simulation time 194012718 ps
CPU time 8.24 seconds
Started Jul 11 05:21:12 PM PDT 24
Finished Jul 11 05:21:25 PM PDT 24
Peak memory 225972 kb
Host smart-2931c98c-68b9-4cc7-a478-a1c284c39d44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858143854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2858143854
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.503391031
Short name T236
Test name
Test status
Simulation time 2282333789 ps
CPU time 10.02 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:21:55 PM PDT 24
Peak memory 218228 kb
Host smart-5c8e552f-9b99-473d-8d2f-9baf8295d13d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503391031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.503391031
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2028021050
Short name T313
Test name
Test status
Simulation time 973566286 ps
CPU time 9.85 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:21:27 PM PDT 24
Peak memory 218176 kb
Host smart-dff2fb48-d987-4ba3-8d59-80c89d6df35e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028021050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2028021050
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2193267260
Short name T699
Test name
Test status
Simulation time 1577696062 ps
CPU time 8.72 seconds
Started Jul 11 05:21:11 PM PDT 24
Finished Jul 11 05:21:24 PM PDT 24
Peak memory 224860 kb
Host smart-8797f9dd-cadf-4c2b-99c7-1ee31cfacb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193267260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2193267260
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1795485135
Short name T371
Test name
Test status
Simulation time 20071257 ps
CPU time 1.38 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:21:18 PM PDT 24
Peak memory 213652 kb
Host smart-dcae7b90-7abd-4af2-b2f2-fa506173043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795485135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1795485135
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1281705245
Short name T337
Test name
Test status
Simulation time 342207326 ps
CPU time 28.48 seconds
Started Jul 11 05:21:11 PM PDT 24
Finished Jul 11 05:21:44 PM PDT 24
Peak memory 250916 kb
Host smart-499fd9db-61b4-4e37-8add-15fcd2384927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281705245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1281705245
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2327903697
Short name T675
Test name
Test status
Simulation time 134619753 ps
CPU time 6.5 seconds
Started Jul 11 05:21:10 PM PDT 24
Finished Jul 11 05:21:21 PM PDT 24
Peak memory 247488 kb
Host smart-2d9cd92b-3fba-4c8b-9d32-d3ce82240247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327903697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2327903697
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.72214677
Short name T398
Test name
Test status
Simulation time 3632709030 ps
CPU time 52.9 seconds
Started Jul 11 05:21:36 PM PDT 24
Finished Jul 11 05:22:35 PM PDT 24
Peak memory 250988 kb
Host smart-186b8226-2d23-4031-8331-2ae8842c3c64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72214677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.lc_ctrl_stress_all.72214677
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1909804668
Short name T10
Test name
Test status
Simulation time 17609885 ps
CPU time 0.98 seconds
Started Jul 11 05:21:16 PM PDT 24
Finished Jul 11 05:21:19 PM PDT 24
Peak memory 217660 kb
Host smart-d7c0bb1f-cb19-486d-9493-09cc00082a9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909804668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1909804668
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2299390613
Short name T427
Test name
Test status
Simulation time 15114356 ps
CPU time 0.88 seconds
Started Jul 11 05:45:03 PM PDT 24
Finished Jul 11 05:45:06 PM PDT 24
Peak memory 208692 kb
Host smart-e50cefed-4868-40e4-8cd3-1f0fb7efbc28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299390613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2299390613
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.4098890999
Short name T583
Test name
Test status
Simulation time 905438251 ps
CPU time 10.58 seconds
Started Jul 11 05:35:41 PM PDT 24
Finished Jul 11 05:35:57 PM PDT 24
Peak memory 226236 kb
Host smart-fc977951-fddf-4dcc-a360-21286d908c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098890999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.4098890999
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2585825672
Short name T31
Test name
Test status
Simulation time 1407570702 ps
CPU time 6.73 seconds
Started Jul 11 05:34:13 PM PDT 24
Finished Jul 11 05:34:34 PM PDT 24
Peak memory 217208 kb
Host smart-f6be5c8d-68bc-4c20-884b-5a4d9138ea60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585825672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2585825672
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.139081143
Short name T698
Test name
Test status
Simulation time 56396442 ps
CPU time 2.49 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:21:47 PM PDT 24
Peak memory 218156 kb
Host smart-663506ad-12f9-4618-b674-a335e5e4cd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139081143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.139081143
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.808450264
Short name T378
Test name
Test status
Simulation time 301606687 ps
CPU time 13.92 seconds
Started Jul 11 05:21:14 PM PDT 24
Finished Jul 11 05:21:31 PM PDT 24
Peak memory 225980 kb
Host smart-1d5ec554-24f0-4ed7-9357-58b1c43a8abd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808450264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.808450264
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.255159676
Short name T519
Test name
Test status
Simulation time 246067861 ps
CPU time 10.23 seconds
Started Jul 11 05:21:12 PM PDT 24
Finished Jul 11 05:21:26 PM PDT 24
Peak memory 225860 kb
Host smart-648e42be-091f-47a5-a2ff-598aca7cb8c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255159676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.255159676
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2399416493
Short name T347
Test name
Test status
Simulation time 659575702 ps
CPU time 8.86 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 225740 kb
Host smart-bdee0993-fdd2-4c21-8c21-3c7379030f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399416493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2399416493
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3307448514
Short name T692
Test name
Test status
Simulation time 14116074 ps
CPU time 1.33 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:21:46 PM PDT 24
Peak memory 213572 kb
Host smart-4c970fa5-47c7-443e-a746-e3297bb63391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307448514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3307448514
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.137632954
Short name T605
Test name
Test status
Simulation time 160558228 ps
CPU time 25.24 seconds
Started Jul 11 05:21:36 PM PDT 24
Finished Jul 11 05:22:08 PM PDT 24
Peak memory 250948 kb
Host smart-7615e1e4-4ce5-4a10-b111-fbf58f3a8d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137632954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.137632954
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3417629405
Short name T534
Test name
Test status
Simulation time 60563658 ps
CPU time 8.99 seconds
Started Jul 11 05:32:09 PM PDT 24
Finished Jul 11 05:32:21 PM PDT 24
Peak memory 250840 kb
Host smart-c60e7dd8-6871-4ba5-8560-117447b69f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417629405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3417629405
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3353338678
Short name T178
Test name
Test status
Simulation time 8210431805 ps
CPU time 59.46 seconds
Started Jul 11 05:21:18 PM PDT 24
Finished Jul 11 05:22:21 PM PDT 24
Peak memory 267376 kb
Host smart-ac2c147d-1c5b-421e-9db4-df7d71792d4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353338678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3353338678
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.374514072
Short name T116
Test name
Test status
Simulation time 109950271589 ps
CPU time 485.32 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:29:53 PM PDT 24
Peak memory 283780 kb
Host smart-6c614767-9c3d-4788-b523-b34736a3e8a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=374514072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.374514072
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3478521613
Short name T679
Test name
Test status
Simulation time 42375246 ps
CPU time 1.01 seconds
Started Jul 11 05:32:37 PM PDT 24
Finished Jul 11 05:32:40 PM PDT 24
Peak memory 211884 kb
Host smart-ac1280e5-1c7e-4458-b209-5a25890e3dea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478521613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3478521613
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2514842110
Short name T579
Test name
Test status
Simulation time 96238034 ps
CPU time 1.13 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:47 PM PDT 24
Peak memory 208816 kb
Host smart-9d52218b-076b-4b40-a2be-7324ec66acab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514842110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2514842110
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.862831648
Short name T597
Test name
Test status
Simulation time 1304201010 ps
CPU time 13.98 seconds
Started Jul 11 05:21:15 PM PDT 24
Finished Jul 11 05:21:32 PM PDT 24
Peak memory 218100 kb
Host smart-c8aa93d3-dfee-4c4f-bb0a-660a88d787bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862831648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.862831648
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2045904909
Short name T644
Test name
Test status
Simulation time 610808147 ps
CPU time 6.96 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 216860 kb
Host smart-a21ac1d1-6521-462b-9649-595dfaa5ad9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045904909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2045904909
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3684792544
Short name T578
Test name
Test status
Simulation time 712027381 ps
CPU time 3.76 seconds
Started Jul 11 05:21:36 PM PDT 24
Finished Jul 11 05:21:46 PM PDT 24
Peak memory 218164 kb
Host smart-682b9051-3ee3-44fc-9dce-ef8bc275a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684792544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3684792544
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2556942301
Short name T785
Test name
Test status
Simulation time 2135215154 ps
CPU time 16.13 seconds
Started Jul 11 05:21:11 PM PDT 24
Finished Jul 11 05:21:31 PM PDT 24
Peak memory 225896 kb
Host smart-a547abdf-783d-4963-8c64-6316f5bf182a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556942301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2556942301
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.423703648
Short name T639
Test name
Test status
Simulation time 1993735078 ps
CPU time 15.18 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:22:02 PM PDT 24
Peak memory 225896 kb
Host smart-935680de-6a21-4bcb-97ca-ea93eaedd1ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423703648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.423703648
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.132803712
Short name T646
Test name
Test status
Simulation time 352448411 ps
CPU time 8.85 seconds
Started Jul 11 05:21:32 PM PDT 24
Finished Jul 11 05:21:44 PM PDT 24
Peak memory 218200 kb
Host smart-770d6b9a-c791-4689-9b1a-f78c012ec16d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132803712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.132803712
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1720007439
Short name T107
Test name
Test status
Simulation time 153605006 ps
CPU time 6.64 seconds
Started Jul 11 05:21:31 PM PDT 24
Finished Jul 11 05:21:41 PM PDT 24
Peak memory 224660 kb
Host smart-25db663b-35f4-4928-8ef6-68d65138d5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720007439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1720007439
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2836263715
Short name T759
Test name
Test status
Simulation time 148306000 ps
CPU time 2.47 seconds
Started Jul 11 05:21:31 PM PDT 24
Finished Jul 11 05:21:37 PM PDT 24
Peak memory 214368 kb
Host smart-1693cd11-91e1-400f-a28a-97338fedc19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836263715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2836263715
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2230497149
Short name T265
Test name
Test status
Simulation time 1259288521 ps
CPU time 21.8 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 250924 kb
Host smart-c6ede7b9-6dbd-4cc3-af2b-f98f356921d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230497149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2230497149
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3036183056
Short name T765
Test name
Test status
Simulation time 69040523 ps
CPU time 7.54 seconds
Started Jul 11 05:40:10 PM PDT 24
Finished Jul 11 05:40:19 PM PDT 24
Peak memory 250876 kb
Host smart-c382c565-d09d-4b64-b99f-3a9ad94f537f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036183056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3036183056
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.4020712350
Short name T849
Test name
Test status
Simulation time 4382684094 ps
CPU time 149.07 seconds
Started Jul 11 05:21:32 PM PDT 24
Finished Jul 11 05:24:05 PM PDT 24
Peak memory 250848 kb
Host smart-460ad203-c7eb-4ace-82fa-7362e99431a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020712350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.4020712350
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1234273299
Short name T515
Test name
Test status
Simulation time 15346659 ps
CPU time 0.9 seconds
Started Jul 11 05:28:05 PM PDT 24
Finished Jul 11 05:28:08 PM PDT 24
Peak memory 211816 kb
Host smart-5bb7a538-ed29-41e1-bf3a-c2553e5643ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234273299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1234273299
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.12816805
Short name T291
Test name
Test status
Simulation time 42148590 ps
CPU time 1.3 seconds
Started Jul 11 05:21:18 PM PDT 24
Finished Jul 11 05:21:23 PM PDT 24
Peak memory 208992 kb
Host smart-efebe78b-1fcb-4f8f-a77d-e4bade20112a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12816805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.12816805
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2646856996
Short name T581
Test name
Test status
Simulation time 781020069 ps
CPU time 15.26 seconds
Started Jul 11 05:21:26 PM PDT 24
Finished Jul 11 05:21:43 PM PDT 24
Peak memory 225900 kb
Host smart-cae2f92f-143c-4ce7-8d0f-b31fc0be85b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646856996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2646856996
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.719706886
Short name T330
Test name
Test status
Simulation time 645992772 ps
CPU time 3.71 seconds
Started Jul 11 05:21:19 PM PDT 24
Finished Jul 11 05:21:26 PM PDT 24
Peak memory 217128 kb
Host smart-c522a7a4-ed50-4c71-9a46-a62cc8f68722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719706886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.719706886
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1768919851
Short name T267
Test name
Test status
Simulation time 99594010 ps
CPU time 4.3 seconds
Started Jul 11 05:21:27 PM PDT 24
Finished Jul 11 05:21:33 PM PDT 24
Peak memory 218100 kb
Host smart-7feb4625-0566-475a-9052-1a05c9f28338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768919851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1768919851
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.339617507
Short name T259
Test name
Test status
Simulation time 2027233481 ps
CPU time 10.18 seconds
Started Jul 11 05:21:21 PM PDT 24
Finished Jul 11 05:21:34 PM PDT 24
Peak memory 225980 kb
Host smart-9d5f2ab6-7219-4dd5-9398-56c5037a357d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339617507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.339617507
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.501774917
Short name T553
Test name
Test status
Simulation time 542391757 ps
CPU time 12.79 seconds
Started Jul 11 05:21:18 PM PDT 24
Finished Jul 11 05:21:34 PM PDT 24
Peak memory 225876 kb
Host smart-ef4a4f0c-efa4-4d38-bd50-8155a2edb2c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501774917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.501774917
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2747271352
Short name T292
Test name
Test status
Simulation time 496076938 ps
CPU time 9.6 seconds
Started Jul 11 05:21:16 PM PDT 24
Finished Jul 11 05:21:28 PM PDT 24
Peak memory 218188 kb
Host smart-3bf3570c-2e0e-4ac3-bed0-378bda145b8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747271352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2747271352
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1151687269
Short name T281
Test name
Test status
Simulation time 381143694 ps
CPU time 13.63 seconds
Started Jul 11 05:21:26 PM PDT 24
Finished Jul 11 05:21:41 PM PDT 24
Peak memory 225892 kb
Host smart-f9da437f-fba9-4e80-9665-8b8b226368d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151687269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1151687269
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.119674675
Short name T403
Test name
Test status
Simulation time 129981974 ps
CPU time 3.5 seconds
Started Jul 11 05:21:18 PM PDT 24
Finished Jul 11 05:21:25 PM PDT 24
Peak memory 217592 kb
Host smart-e3a545a6-7944-4114-9f8a-287732a2fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119674675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.119674675
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3211640314
Short name T598
Test name
Test status
Simulation time 227739798 ps
CPU time 26.93 seconds
Started Jul 11 05:21:16 PM PDT 24
Finished Jul 11 05:21:46 PM PDT 24
Peak memory 246048 kb
Host smart-7b1a3f48-91cf-45a0-83e1-d1cae0dd0670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211640314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3211640314
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2369061804
Short name T80
Test name
Test status
Simulation time 419627668 ps
CPU time 8.29 seconds
Started Jul 11 05:21:31 PM PDT 24
Finished Jul 11 05:21:42 PM PDT 24
Peak memory 250924 kb
Host smart-8e11621d-4bdf-4cb2-b13e-c1ccf1b461fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369061804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2369061804
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1736964398
Short name T76
Test name
Test status
Simulation time 6821384091 ps
CPU time 73.5 seconds
Started Jul 11 05:21:20 PM PDT 24
Finished Jul 11 05:22:37 PM PDT 24
Peak memory 267188 kb
Host smart-047eeeb9-392e-4d36-a9ec-3b861265346b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736964398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1736964398
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3637094536
Short name T860
Test name
Test status
Simulation time 41361200 ps
CPU time 0.9 seconds
Started Jul 11 05:21:15 PM PDT 24
Finished Jul 11 05:21:19 PM PDT 24
Peak memory 212936 kb
Host smart-80ce4223-eb46-49cf-951e-03a64271d830
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637094536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3637094536
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1123395065
Short name T376
Test name
Test status
Simulation time 37728118 ps
CPU time 1.14 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:21 PM PDT 24
Peak memory 208840 kb
Host smart-4f870177-3bf1-44d0-86ed-be4d11eda98b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123395065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1123395065
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3028016403
Short name T101
Test name
Test status
Simulation time 430772422 ps
CPU time 14.28 seconds
Started Jul 11 05:21:21 PM PDT 24
Finished Jul 11 05:21:38 PM PDT 24
Peak memory 225896 kb
Host smart-24d5908c-8b90-429e-b416-0936bc54e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028016403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3028016403
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.798631715
Short name T862
Test name
Test status
Simulation time 6614389043 ps
CPU time 5.81 seconds
Started Jul 11 05:21:19 PM PDT 24
Finished Jul 11 05:21:28 PM PDT 24
Peak memory 217680 kb
Host smart-a97f45e5-913a-45ad-9761-8a34861f0a24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798631715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.798631715
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4043452677
Short name T448
Test name
Test status
Simulation time 157430948 ps
CPU time 2.79 seconds
Started Jul 11 05:21:17 PM PDT 24
Finished Jul 11 05:21:23 PM PDT 24
Peak memory 218144 kb
Host smart-38b8e6f7-27d6-4502-bacd-b4f0b35a43e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043452677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4043452677
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2711747683
Short name T545
Test name
Test status
Simulation time 333127203 ps
CPU time 16.51 seconds
Started Jul 11 05:21:28 PM PDT 24
Finished Jul 11 05:21:46 PM PDT 24
Peak memory 225900 kb
Host smart-6ad4baa0-e662-4dcb-9f7a-6ae25768e154
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711747683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2711747683
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2690766898
Short name T784
Test name
Test status
Simulation time 1850945337 ps
CPU time 19.79 seconds
Started Jul 11 05:21:19 PM PDT 24
Finished Jul 11 05:21:42 PM PDT 24
Peak memory 225980 kb
Host smart-f4eb0481-6241-47d4-b22b-cdcce2307e97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690766898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2690766898
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2801828040
Short name T529
Test name
Test status
Simulation time 2061601176 ps
CPU time 9.84 seconds
Started Jul 11 05:21:27 PM PDT 24
Finished Jul 11 05:21:39 PM PDT 24
Peak memory 218100 kb
Host smart-84908e92-1750-44c9-a3e6-5a0533d864a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801828040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2801828040
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4190071007
Short name T543
Test name
Test status
Simulation time 373041602 ps
CPU time 13.81 seconds
Started Jul 11 05:21:19 PM PDT 24
Finished Jul 11 05:21:36 PM PDT 24
Peak memory 225892 kb
Host smart-a83c65a3-f37a-4b58-a62d-005a282a5306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190071007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4190071007
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1152023714
Short name T271
Test name
Test status
Simulation time 80266250 ps
CPU time 1.73 seconds
Started Jul 11 05:21:19 PM PDT 24
Finished Jul 11 05:21:24 PM PDT 24
Peak memory 217664 kb
Host smart-0e0dff0e-3b5f-44cc-bbb2-be10846e70c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152023714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1152023714
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.977209235
Short name T540
Test name
Test status
Simulation time 479744612 ps
CPU time 14.68 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:22:01 PM PDT 24
Peak memory 250332 kb
Host smart-8660827e-0c31-4a07-a9af-d89163ae584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977209235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.977209235
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3964788266
Short name T764
Test name
Test status
Simulation time 318402230 ps
CPU time 7.13 seconds
Started Jul 11 05:21:32 PM PDT 24
Finished Jul 11 05:21:43 PM PDT 24
Peak memory 250384 kb
Host smart-db703dc1-01da-4a85-8ed0-895bc9e1254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964788266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3964788266
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.634803913
Short name T566
Test name
Test status
Simulation time 29694474 ps
CPU time 0.86 seconds
Started Jul 11 05:21:20 PM PDT 24
Finished Jul 11 05:21:23 PM PDT 24
Peak memory 211700 kb
Host smart-13776dc2-b52c-4125-93fc-fd7ecbe86ddc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634803913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.634803913
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2502944190
Short name T296
Test name
Test status
Simulation time 42637887 ps
CPU time 0.93 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:21:50 PM PDT 24
Peak memory 208816 kb
Host smart-6f6c943a-7314-421b-a341-ed752da58501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502944190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2502944190
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3646645363
Short name T247
Test name
Test status
Simulation time 260770078 ps
CPU time 9.13 seconds
Started Jul 11 05:21:27 PM PDT 24
Finished Jul 11 05:21:38 PM PDT 24
Peak memory 218088 kb
Host smart-4ed385f0-2a6f-4e41-b54b-5c53fa339fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646645363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3646645363
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3787856138
Short name T360
Test name
Test status
Simulation time 286170068 ps
CPU time 1.77 seconds
Started Jul 11 05:21:32 PM PDT 24
Finished Jul 11 05:21:37 PM PDT 24
Peak memory 217624 kb
Host smart-53cabe4c-d533-401f-b7b5-36a39a2108ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787856138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3787856138
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2705641004
Short name T859
Test name
Test status
Simulation time 146911295 ps
CPU time 1.99 seconds
Started Jul 11 05:21:20 PM PDT 24
Finished Jul 11 05:21:25 PM PDT 24
Peak memory 218180 kb
Host smart-feeaabc3-7cbf-40f0-81a1-ca7f0dee00d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705641004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2705641004
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4082801627
Short name T179
Test name
Test status
Simulation time 333634625 ps
CPU time 16.3 seconds
Started Jul 11 05:21:32 PM PDT 24
Finished Jul 11 05:21:52 PM PDT 24
Peak memory 218264 kb
Host smart-443d79b1-ce2b-4c1b-bb89-7e8ba86504ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082801627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4082801627
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1688100624
Short name T527
Test name
Test status
Simulation time 947726212 ps
CPU time 22.8 seconds
Started Jul 11 05:21:28 PM PDT 24
Finished Jul 11 05:21:53 PM PDT 24
Peak memory 225896 kb
Host smart-147674f8-8f83-466b-86dd-1eaba56c4c24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688100624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1688100624
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.830767329
Short name T609
Test name
Test status
Simulation time 1061493636 ps
CPU time 7.76 seconds
Started Jul 11 05:21:21 PM PDT 24
Finished Jul 11 05:21:31 PM PDT 24
Peak memory 224368 kb
Host smart-c9dd4a14-818a-4823-a13d-13e1e0a27944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830767329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.830767329
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3516513757
Short name T171
Test name
Test status
Simulation time 99073711 ps
CPU time 1.45 seconds
Started Jul 11 05:21:19 PM PDT 24
Finished Jul 11 05:21:24 PM PDT 24
Peak memory 217660 kb
Host smart-c8369cc0-37ad-4eff-8e9e-f3446c6b6f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516513757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3516513757
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.4220447824
Short name T710
Test name
Test status
Simulation time 374216059 ps
CPU time 33.44 seconds
Started Jul 11 05:21:22 PM PDT 24
Finished Jul 11 05:21:58 PM PDT 24
Peak memory 250832 kb
Host smart-88508aba-7b5b-4cce-aad2-730ac29d5025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220447824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.4220447824
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2862624343
Short name T499
Test name
Test status
Simulation time 142338031 ps
CPU time 7.18 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 250832 kb
Host smart-5761a4ad-ec45-4813-a09d-42d0ad24aa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862624343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2862624343
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.98172401
Short name T67
Test name
Test status
Simulation time 18929117502 ps
CPU time 39.81 seconds
Started Jul 11 05:21:18 PM PDT 24
Finished Jul 11 05:22:02 PM PDT 24
Peak memory 221024 kb
Host smart-74f86599-12b7-43ab-94f8-dad0ae65539d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98172401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.lc_ctrl_stress_all.98172401
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1000074529
Short name T323
Test name
Test status
Simulation time 48268003 ps
CPU time 0.91 seconds
Started Jul 11 05:21:21 PM PDT 24
Finished Jul 11 05:21:24 PM PDT 24
Peak memory 212916 kb
Host smart-5d5d7a55-9c03-48ab-b96b-d6301e711b37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000074529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1000074529
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.462816697
Short name T290
Test name
Test status
Simulation time 70361067 ps
CPU time 1.05 seconds
Started Jul 11 05:21:30 PM PDT 24
Finished Jul 11 05:21:33 PM PDT 24
Peak memory 208840 kb
Host smart-777a8340-8540-4dfa-9bce-bfe2560cdefa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462816697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.462816697
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1358244354
Short name T451
Test name
Test status
Simulation time 1739726856 ps
CPU time 13.81 seconds
Started Jul 11 05:21:31 PM PDT 24
Finished Jul 11 05:21:49 PM PDT 24
Peak memory 218112 kb
Host smart-6c9f9a9d-7858-4c8d-bd11-88eddd2556e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358244354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1358244354
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2175904022
Short name T803
Test name
Test status
Simulation time 31340733 ps
CPU time 1.14 seconds
Started Jul 11 05:21:23 PM PDT 24
Finished Jul 11 05:21:26 PM PDT 24
Peak memory 216932 kb
Host smart-c2b8d8a3-ad3a-4aad-95a6-9a61022fe453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175904022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2175904022
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1800755328
Short name T444
Test name
Test status
Simulation time 290351625 ps
CPU time 2.75 seconds
Started Jul 11 05:21:25 PM PDT 24
Finished Jul 11 05:21:29 PM PDT 24
Peak memory 218164 kb
Host smart-7206fe21-3ade-4ad6-a3f6-9c0dfb290c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800755328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1800755328
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3903600670
Short name T766
Test name
Test status
Simulation time 401579014 ps
CPU time 7.42 seconds
Started Jul 11 05:21:27 PM PDT 24
Finished Jul 11 05:21:36 PM PDT 24
Peak memory 225940 kb
Host smart-616c8488-fa9b-4453-a763-906bf8be0fd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903600670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3903600670
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.137947421
Short name T744
Test name
Test status
Simulation time 1077268064 ps
CPU time 9.04 seconds
Started Jul 11 05:21:25 PM PDT 24
Finished Jul 11 05:21:36 PM PDT 24
Peak memory 218080 kb
Host smart-48df56c1-6e12-46cb-8f04-a5b52a3e6cb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137947421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.137947421
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3190300627
Short name T565
Test name
Test status
Simulation time 206285908 ps
CPU time 9.16 seconds
Started Jul 11 05:21:33 PM PDT 24
Finished Jul 11 05:21:47 PM PDT 24
Peak memory 225984 kb
Host smart-8e6f0bf2-ef92-42a5-b915-49af373e13eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190300627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3190300627
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3926419249
Short name T288
Test name
Test status
Simulation time 97319883 ps
CPU time 2.05 seconds
Started Jul 11 05:21:24 PM PDT 24
Finished Jul 11 05:21:28 PM PDT 24
Peak memory 217532 kb
Host smart-56d364cb-447b-44b5-9ec9-765b89298a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926419249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3926419249
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.552610484
Short name T632
Test name
Test status
Simulation time 293507165 ps
CPU time 30.95 seconds
Started Jul 11 05:21:22 PM PDT 24
Finished Jul 11 05:21:55 PM PDT 24
Peak memory 250924 kb
Host smart-4fc9389e-4d00-4975-a6b4-c2c306c6c624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552610484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.552610484
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1386484240
Short name T621
Test name
Test status
Simulation time 157817305 ps
CPU time 3.85 seconds
Started Jul 11 05:21:22 PM PDT 24
Finished Jul 11 05:21:28 PM PDT 24
Peak memory 222300 kb
Host smart-d9e4a26a-9525-4741-b369-afd434af04a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386484240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1386484240
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1392933520
Short name T286
Test name
Test status
Simulation time 45825263912 ps
CPU time 182.1 seconds
Started Jul 11 05:21:25 PM PDT 24
Finished Jul 11 05:24:29 PM PDT 24
Peak memory 249524 kb
Host smart-77e21b01-1377-458a-95f9-6d754496bac9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392933520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1392933520
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.256506901
Short name T514
Test name
Test status
Simulation time 13919634 ps
CPU time 1.08 seconds
Started Jul 11 05:21:23 PM PDT 24
Finished Jul 11 05:21:27 PM PDT 24
Peak memory 211868 kb
Host smart-40936efa-7d98-4e97-ae52-9b2f323def54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256506901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.256506901
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2512138985
Short name T344
Test name
Test status
Simulation time 27473511 ps
CPU time 0.86 seconds
Started Jul 11 05:19:13 PM PDT 24
Finished Jul 11 05:19:17 PM PDT 24
Peak memory 208832 kb
Host smart-63dfcde7-af60-4d96-be10-ea300762d80a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512138985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2512138985
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.787764165
Short name T756
Test name
Test status
Simulation time 2957417268 ps
CPU time 9.29 seconds
Started Jul 11 05:19:06 PM PDT 24
Finished Jul 11 05:19:19 PM PDT 24
Peak memory 218148 kb
Host smart-69d81107-2ba7-432a-8ff9-3b0a21bd850e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787764165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.787764165
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3489021107
Short name T552
Test name
Test status
Simulation time 368844128 ps
CPU time 3.5 seconds
Started Jul 11 05:19:24 PM PDT 24
Finished Jul 11 05:19:29 PM PDT 24
Peak memory 217044 kb
Host smart-781f33d2-6c30-43ef-9a80-a524538ce610
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489021107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3489021107
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3079184744
Short name T517
Test name
Test status
Simulation time 7118484285 ps
CPU time 41.68 seconds
Started Jul 11 05:19:10 PM PDT 24
Finished Jul 11 05:19:55 PM PDT 24
Peak memory 225984 kb
Host smart-d2fb9bd1-36ca-40f6-b438-6fafa377b2e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079184744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3079184744
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2296110248
Short name T436
Test name
Test status
Simulation time 400733168 ps
CPU time 8.66 seconds
Started Jul 11 05:19:10 PM PDT 24
Finished Jul 11 05:19:22 PM PDT 24
Peak memory 217732 kb
Host smart-cd920ef9-1b2d-449f-b7f4-b9f0667d184c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296110248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
296110248
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4111802906
Short name T741
Test name
Test status
Simulation time 277983278 ps
CPU time 4.68 seconds
Started Jul 11 05:19:14 PM PDT 24
Finished Jul 11 05:19:22 PM PDT 24
Peak memory 218424 kb
Host smart-f6abde2e-8889-4f0e-af5a-55b474cb1c00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111802906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4111802906
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2667845610
Short name T789
Test name
Test status
Simulation time 5851881058 ps
CPU time 19.6 seconds
Started Jul 11 05:19:12 PM PDT 24
Finished Jul 11 05:19:35 PM PDT 24
Peak memory 217736 kb
Host smart-ad9c5b6c-b916-4b34-b033-85e2f45efaad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667845610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2667845610
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4036179998
Short name T572
Test name
Test status
Simulation time 593994397 ps
CPU time 8.4 seconds
Started Jul 11 05:19:04 PM PDT 24
Finished Jul 11 05:19:15 PM PDT 24
Peak memory 217656 kb
Host smart-89e423db-e69f-408b-960c-1ed581cf94f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036179998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
4036179998
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.4241333023
Short name T100
Test name
Test status
Simulation time 4201775790 ps
CPU time 32.7 seconds
Started Jul 11 05:19:05 PM PDT 24
Finished Jul 11 05:19:42 PM PDT 24
Peak memory 252088 kb
Host smart-4580817f-e787-4039-8197-ed8ae5b17ec1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241333023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.4241333023
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3090340834
Short name T663
Test name
Test status
Simulation time 3483075852 ps
CPU time 27.92 seconds
Started Jul 11 05:19:06 PM PDT 24
Finished Jul 11 05:19:37 PM PDT 24
Peak memory 250976 kb
Host smart-1a76ef1d-4421-48e7-961b-2308fa0440c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090340834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3090340834
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2535802967
Short name T626
Test name
Test status
Simulation time 36825369 ps
CPU time 1.67 seconds
Started Jul 11 05:19:04 PM PDT 24
Finished Jul 11 05:19:09 PM PDT 24
Peak memory 221768 kb
Host smart-22e6fb4e-e9a2-455d-84c8-c2769f8693e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535802967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2535802967
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.856792652
Short name T196
Test name
Test status
Simulation time 381735679 ps
CPU time 5.67 seconds
Started Jul 11 05:19:08 PM PDT 24
Finished Jul 11 05:19:17 PM PDT 24
Peak memory 214616 kb
Host smart-9c09d31d-7aaf-4c6b-a2d7-1862774de696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856792652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.856792652
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2548169004
Short name T50
Test name
Test status
Simulation time 2566473860 ps
CPU time 37.11 seconds
Started Jul 11 05:19:18 PM PDT 24
Finished Jul 11 05:19:57 PM PDT 24
Peak memory 268604 kb
Host smart-9878d6f6-0d01-46d8-832d-5068fff05800
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548169004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2548169004
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2446689469
Short name T429
Test name
Test status
Simulation time 1781040685 ps
CPU time 19.29 seconds
Started Jul 11 05:19:13 PM PDT 24
Finished Jul 11 05:19:36 PM PDT 24
Peak memory 218816 kb
Host smart-ec7d40a4-3990-4843-875b-8e8f45eb049f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446689469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2446689469
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2755763969
Short name T573
Test name
Test status
Simulation time 1621016314 ps
CPU time 12.77 seconds
Started Jul 11 05:19:15 PM PDT 24
Finished Jul 11 05:19:30 PM PDT 24
Peak memory 225948 kb
Host smart-ea87969c-de02-4bb7-be13-dd2043a3e726
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755763969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2755763969
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.549571879
Short name T397
Test name
Test status
Simulation time 742724662 ps
CPU time 10.55 seconds
Started Jul 11 05:19:12 PM PDT 24
Finished Jul 11 05:19:27 PM PDT 24
Peak memory 225960 kb
Host smart-08075938-31b2-4b4b-9f98-54bb3c92c4d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549571879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.549571879
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1449435241
Short name T486
Test name
Test status
Simulation time 272188007 ps
CPU time 11.29 seconds
Started Jul 11 05:19:04 PM PDT 24
Finished Jul 11 05:19:18 PM PDT 24
Peak memory 225232 kb
Host smart-d35af081-0045-4be0-88a2-13dafd0cd06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449435241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1449435241
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.47564580
Short name T833
Test name
Test status
Simulation time 66381062 ps
CPU time 1.05 seconds
Started Jul 11 05:19:02 PM PDT 24
Finished Jul 11 05:19:04 PM PDT 24
Peak memory 221596 kb
Host smart-7808ace6-2458-4971-a548-b5626c2c6bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47564580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.47564580
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3794777031
Short name T264
Test name
Test status
Simulation time 318574882 ps
CPU time 26.07 seconds
Started Jul 11 05:19:03 PM PDT 24
Finished Jul 11 05:19:30 PM PDT 24
Peak memory 250840 kb
Host smart-7f926208-b13c-40d0-970b-9ed1c7593f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794777031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3794777031
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.833284295
Short name T822
Test name
Test status
Simulation time 88253966 ps
CPU time 8.62 seconds
Started Jul 11 05:19:04 PM PDT 24
Finished Jul 11 05:19:15 PM PDT 24
Peak memory 250828 kb
Host smart-b069222b-07da-4898-a116-de6178418378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833284295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.833284295
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2472273146
Short name T257
Test name
Test status
Simulation time 2730919725 ps
CPU time 92.55 seconds
Started Jul 11 05:19:14 PM PDT 24
Finished Jul 11 05:20:50 PM PDT 24
Peak memory 267272 kb
Host smart-ce59d0d8-f254-4a1b-ac2a-1618e59b459e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472273146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2472273146
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1637261569
Short name T156
Test name
Test status
Simulation time 57997986295 ps
CPU time 256.79 seconds
Started Jul 11 05:19:13 PM PDT 24
Finished Jul 11 05:23:33 PM PDT 24
Peak memory 252192 kb
Host smart-759fbd31-7ccb-4bb7-b22e-bb48be1966c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1637261569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1637261569
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1712445346
Short name T382
Test name
Test status
Simulation time 11270434 ps
CPU time 0.95 seconds
Started Jul 11 05:19:05 PM PDT 24
Finished Jul 11 05:19:10 PM PDT 24
Peak memory 211816 kb
Host smart-443755d1-a428-4081-84c9-9f78ee8abee5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712445346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1712445346
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1390374473
Short name T791
Test name
Test status
Simulation time 106147259 ps
CPU time 1.43 seconds
Started Jul 11 05:21:32 PM PDT 24
Finished Jul 11 05:21:36 PM PDT 24
Peak memory 208996 kb
Host smart-1e50b148-0e6c-4f03-988f-ea96aa14f9b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390374473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1390374473
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1942564124
Short name T853
Test name
Test status
Simulation time 554258319 ps
CPU time 13.12 seconds
Started Jul 11 05:21:42 PM PDT 24
Finished Jul 11 05:22:04 PM PDT 24
Peak memory 218220 kb
Host smart-e0598b70-13d0-4ebd-9c1d-79c784df2be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942564124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1942564124
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2438756726
Short name T667
Test name
Test status
Simulation time 950088727 ps
CPU time 10.65 seconds
Started Jul 11 05:21:33 PM PDT 24
Finished Jul 11 05:21:49 PM PDT 24
Peak memory 217184 kb
Host smart-4b5fd386-e715-4b74-87f9-5a1c6e1c1bb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438756726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2438756726
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1071793247
Short name T285
Test name
Test status
Simulation time 226354288 ps
CPU time 3.48 seconds
Started Jul 11 05:21:29 PM PDT 24
Finished Jul 11 05:21:34 PM PDT 24
Peak memory 222524 kb
Host smart-f409964b-ab6f-4ece-b83c-7fc316f86c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071793247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1071793247
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1920746587
Short name T795
Test name
Test status
Simulation time 693391408 ps
CPU time 18.35 seconds
Started Jul 11 05:21:30 PM PDT 24
Finished Jul 11 05:21:52 PM PDT 24
Peak memory 225896 kb
Host smart-e813270d-7541-4128-8a20-f10e1d7c60e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920746587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1920746587
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1068111641
Short name T302
Test name
Test status
Simulation time 1508740505 ps
CPU time 11.18 seconds
Started Jul 11 05:21:42 PM PDT 24
Finished Jul 11 05:22:02 PM PDT 24
Peak memory 225904 kb
Host smart-8d1b134f-a1de-4a67-83f3-a44eecfb0aa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068111641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1068111641
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.788498902
Short name T374
Test name
Test status
Simulation time 624756222 ps
CPU time 14.87 seconds
Started Jul 11 05:21:30 PM PDT 24
Finished Jul 11 05:21:47 PM PDT 24
Peak memory 218164 kb
Host smart-428a3e54-6aa1-4b15-950b-dc62f0e0461a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788498902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.788498902
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.357957378
Short name T425
Test name
Test status
Simulation time 1807839557 ps
CPU time 13.97 seconds
Started Jul 11 05:21:32 PM PDT 24
Finished Jul 11 05:21:49 PM PDT 24
Peak memory 225956 kb
Host smart-4f7b09a2-f59b-4729-b0e8-5c293a7487a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357957378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.357957378
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3908822905
Short name T550
Test name
Test status
Simulation time 181659895 ps
CPU time 10.85 seconds
Started Jul 11 05:23:53 PM PDT 24
Finished Jul 11 05:24:05 PM PDT 24
Peak memory 223228 kb
Host smart-bf8cb2dd-8439-4ece-9f8c-f3bf3d7605e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908822905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3908822905
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1713425033
Short name T248
Test name
Test status
Simulation time 7276293933 ps
CPU time 27.99 seconds
Started Jul 11 05:21:33 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 250960 kb
Host smart-d6967d46-e625-4cc9-8f9a-c12885ff2f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713425033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1713425033
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1449748016
Short name T329
Test name
Test status
Simulation time 274295540 ps
CPU time 7.01 seconds
Started Jul 11 05:21:29 PM PDT 24
Finished Jul 11 05:21:38 PM PDT 24
Peak memory 250856 kb
Host smart-f25dee1e-24ef-43d0-80bb-64cd33625483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449748016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1449748016
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3456974689
Short name T748
Test name
Test status
Simulation time 2625329450 ps
CPU time 65.03 seconds
Started Jul 11 05:21:31 PM PDT 24
Finished Jul 11 05:22:39 PM PDT 24
Peak memory 247748 kb
Host smart-978a4750-f9e5-44a3-90be-52db9211dfd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456974689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3456974689
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2028658185
Short name T349
Test name
Test status
Simulation time 18710687 ps
CPU time 1.03 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:47 PM PDT 24
Peak memory 217664 kb
Host smart-8d2a8aac-e4b9-499e-bf44-7d7840ba084b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028658185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2028658185
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.386521111
Short name T600
Test name
Test status
Simulation time 16541605 ps
CPU time 1.08 seconds
Started Jul 11 05:21:36 PM PDT 24
Finished Jul 11 05:21:43 PM PDT 24
Peak memory 209016 kb
Host smart-e9380cbe-c1e2-4432-8c3e-c6c019bcb0ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386521111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.386521111
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.4162638912
Short name T834
Test name
Test status
Simulation time 355500459 ps
CPU time 14.12 seconds
Started Jul 11 05:21:34 PM PDT 24
Finished Jul 11 05:21:53 PM PDT 24
Peak memory 218188 kb
Host smart-f09c375f-2410-48aa-9681-43a79e48064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162638912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4162638912
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.581547969
Short name T657
Test name
Test status
Simulation time 229118241 ps
CPU time 2.85 seconds
Started Jul 11 05:21:27 PM PDT 24
Finished Jul 11 05:21:32 PM PDT 24
Peak memory 217196 kb
Host smart-745c7cfe-512f-4513-bdfe-5ce6a6efeb42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581547969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.581547969
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2455724108
Short name T232
Test name
Test status
Simulation time 26490361 ps
CPU time 1.58 seconds
Started Jul 11 05:21:33 PM PDT 24
Finished Jul 11 05:21:40 PM PDT 24
Peak memory 221868 kb
Host smart-73c2607e-fc6e-4d7f-8bcf-6d3cc12f4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455724108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2455724108
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3626367818
Short name T620
Test name
Test status
Simulation time 887335330 ps
CPU time 9.91 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:21:57 PM PDT 24
Peak memory 225888 kb
Host smart-8bcd6c36-4850-43d4-9ba5-5e306d862c2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626367818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3626367818
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.588413991
Short name T450
Test name
Test status
Simulation time 3046102925 ps
CPU time 17.07 seconds
Started Jul 11 05:21:36 PM PDT 24
Finished Jul 11 05:21:59 PM PDT 24
Peak memory 225948 kb
Host smart-1d6d8d02-5553-4ed8-96a0-d883b64aefaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588413991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.588413991
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3980964073
Short name T184
Test name
Test status
Simulation time 1431946555 ps
CPU time 7.76 seconds
Started Jul 11 05:21:41 PM PDT 24
Finished Jul 11 05:21:58 PM PDT 24
Peak memory 218100 kb
Host smart-8d4b25ab-9e11-45a1-9e6b-f977f7dccf60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980964073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3980964073
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3910279487
Short name T473
Test name
Test status
Simulation time 2095525889 ps
CPU time 11.74 seconds
Started Jul 11 05:21:29 PM PDT 24
Finished Jul 11 05:21:42 PM PDT 24
Peak memory 218156 kb
Host smart-bf03d78e-e2d6-4149-876a-ba4d8468b99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910279487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3910279487
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1484628088
Short name T506
Test name
Test status
Simulation time 232348609 ps
CPU time 1.73 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:21:46 PM PDT 24
Peak memory 213844 kb
Host smart-dd09692d-7e85-49f7-b3b8-1c0949c6e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484628088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1484628088
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2786854499
Short name T96
Test name
Test status
Simulation time 276022022 ps
CPU time 22.96 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:22:08 PM PDT 24
Peak memory 250860 kb
Host smart-1552dc77-2d9e-4137-868b-e8853165a56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786854499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2786854499
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.241627216
Short name T359
Test name
Test status
Simulation time 347323906 ps
CPU time 8.16 seconds
Started Jul 11 05:21:32 PM PDT 24
Finished Jul 11 05:21:44 PM PDT 24
Peak memory 250332 kb
Host smart-25bdca4d-6f79-4d44-aa07-9db10b7bbf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241627216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.241627216
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.329734114
Short name T528
Test name
Test status
Simulation time 10658795680 ps
CPU time 104.73 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:23:34 PM PDT 24
Peak memory 283680 kb
Host smart-e4fc7e4a-8c56-4742-99d4-94a1c8a48735
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329734114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.329734114
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.892148289
Short name T687
Test name
Test status
Simulation time 109174807020 ps
CPU time 958.01 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:37:48 PM PDT 24
Peak memory 414940 kb
Host smart-71e00ec7-f32d-4679-a415-2ab6053ee674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=892148289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.892148289
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.395569176
Short name T768
Test name
Test status
Simulation time 14228723 ps
CPU time 0.87 seconds
Started Jul 11 05:21:28 PM PDT 24
Finished Jul 11 05:21:31 PM PDT 24
Peak memory 211720 kb
Host smart-61c02c73-dc51-4bdb-bee7-2c1cbfe185f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395569176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.395569176
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.763939060
Short name T681
Test name
Test status
Simulation time 71236158 ps
CPU time 1.07 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:48 PM PDT 24
Peak memory 208920 kb
Host smart-08483579-6ed6-4381-a992-2e6067dcbe64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763939060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.763939060
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2052207581
Short name T311
Test name
Test status
Simulation time 268169670 ps
CPU time 13.84 seconds
Started Jul 11 05:21:34 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 218108 kb
Host smart-547ec3e5-aac1-4d86-91e0-4bfc1d9fc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052207581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2052207581
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.651911405
Short name T840
Test name
Test status
Simulation time 5217675434 ps
CPU time 8.68 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:55 PM PDT 24
Peak memory 217640 kb
Host smart-49c22d56-c327-4292-81f9-b49c8ea2e800
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651911405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.651911405
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.484887896
Short name T412
Test name
Test status
Simulation time 134575045 ps
CPU time 3.45 seconds
Started Jul 11 05:21:41 PM PDT 24
Finished Jul 11 05:21:53 PM PDT 24
Peak memory 218164 kb
Host smart-94cd672a-17f4-48b8-b6a6-7d5f468bdfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484887896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.484887896
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3077210981
Short name T828
Test name
Test status
Simulation time 979738102 ps
CPU time 10.83 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 225980 kb
Host smart-8fe9f180-eb73-4989-828c-7be8f15531c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077210981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3077210981
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.573307675
Short name T341
Test name
Test status
Simulation time 272251264 ps
CPU time 11.01 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:21:55 PM PDT 24
Peak memory 225984 kb
Host smart-ca808a1f-47ae-4faa-a3ee-23912c4dea05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573307675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.573307675
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4150984071
Short name T470
Test name
Test status
Simulation time 158688823 ps
CPU time 5.83 seconds
Started Jul 11 05:21:35 PM PDT 24
Finished Jul 11 05:21:47 PM PDT 24
Peak memory 225972 kb
Host smart-effb952e-223d-422a-89e3-cb286f05033d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150984071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
4150984071
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2968727907
Short name T629
Test name
Test status
Simulation time 2624655344 ps
CPU time 13.43 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:21:58 PM PDT 24
Peak memory 225948 kb
Host smart-03022d54-0728-49d3-a26b-e06dc53ead3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968727907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2968727907
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.699180291
Short name T297
Test name
Test status
Simulation time 606245854 ps
CPU time 1.94 seconds
Started Jul 11 05:23:07 PM PDT 24
Finished Jul 11 05:23:17 PM PDT 24
Peak memory 214304 kb
Host smart-b0370253-032f-4cc2-a025-e8e58524ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699180291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.699180291
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1370535744
Short name T355
Test name
Test status
Simulation time 1340268319 ps
CPU time 37.22 seconds
Started Jul 11 05:21:35 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 250888 kb
Host smart-743c2940-0eb6-4edf-a88b-727bd02ad482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370535744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1370535744
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3518081441
Short name T755
Test name
Test status
Simulation time 176173869 ps
CPU time 8.41 seconds
Started Jul 11 05:21:35 PM PDT 24
Finished Jul 11 05:21:49 PM PDT 24
Peak memory 250924 kb
Host smart-dcbce962-fe20-41b5-80fa-549f03705fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518081441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3518081441
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.406242976
Short name T73
Test name
Test status
Simulation time 6367598011 ps
CPU time 59.55 seconds
Started Jul 11 05:21:38 PM PDT 24
Finished Jul 11 05:22:44 PM PDT 24
Peak memory 250876 kb
Host smart-b95bd1c4-86f3-44ca-a0ca-d626d5e0a1ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406242976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.406242976
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2048440431
Short name T165
Test name
Test status
Simulation time 84956743508 ps
CPU time 3296.79 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 06:16:44 PM PDT 24
Peak memory 758008 kb
Host smart-fd8a85c3-32e4-4556-807e-8d2f6fa99255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2048440431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.2048440431
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3195028481
Short name T861
Test name
Test status
Simulation time 30656629 ps
CPU time 0.79 seconds
Started Jul 11 05:21:43 PM PDT 24
Finished Jul 11 05:21:52 PM PDT 24
Peak memory 211820 kb
Host smart-a26c24d4-5e55-41ff-9958-2a420373bed9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195028481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3195028481
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2439428907
Short name T818
Test name
Test status
Simulation time 38714723 ps
CPU time 1.17 seconds
Started Jul 11 05:21:44 PM PDT 24
Finished Jul 11 05:21:53 PM PDT 24
Peak memory 209040 kb
Host smart-ad65316e-5457-4a30-9135-d1092968e206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439428907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2439428907
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1428172085
Short name T404
Test name
Test status
Simulation time 1506490903 ps
CPU time 17.61 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:22:07 PM PDT 24
Peak memory 226012 kb
Host smart-22d25813-1e86-4f99-8596-692674607390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428172085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1428172085
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3198406023
Short name T422
Test name
Test status
Simulation time 41754911 ps
CPU time 1.16 seconds
Started Jul 11 05:21:42 PM PDT 24
Finished Jul 11 05:21:52 PM PDT 24
Peak memory 217412 kb
Host smart-fa38bb65-49bd-4556-be13-912983b93d78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198406023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3198406023
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.240983406
Short name T446
Test name
Test status
Simulation time 228174191 ps
CPU time 2.89 seconds
Started Jul 11 05:21:36 PM PDT 24
Finished Jul 11 05:21:45 PM PDT 24
Peak memory 222476 kb
Host smart-bc338650-3393-44cd-9ab8-04ebe9f9d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240983406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.240983406
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4069356450
Short name T189
Test name
Test status
Simulation time 1152080191 ps
CPU time 11.01 seconds
Started Jul 11 05:21:44 PM PDT 24
Finished Jul 11 05:22:03 PM PDT 24
Peak memory 225956 kb
Host smart-90c76433-3daa-4360-8bdf-e4f2bae7e1ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069356450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.4069356450
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1016009263
Short name T480
Test name
Test status
Simulation time 333992354 ps
CPU time 9.61 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:21:57 PM PDT 24
Peak memory 225896 kb
Host smart-c361d501-011d-4976-82ef-401c7b37ded5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016009263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1016009263
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2429103755
Short name T595
Test name
Test status
Simulation time 427857732 ps
CPU time 15.85 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:23 PM PDT 24
Peak memory 225904 kb
Host smart-b5d7ad54-6575-4f52-a8ee-dd3867294643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429103755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2429103755
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.79405662
Short name T814
Test name
Test status
Simulation time 58575631 ps
CPU time 2.43 seconds
Started Jul 11 05:21:44 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 214160 kb
Host smart-55e68a52-fc08-4759-926d-6a4844ebdbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79405662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.79405662
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4183887884
Short name T112
Test name
Test status
Simulation time 1247205637 ps
CPU time 25.63 seconds
Started Jul 11 05:21:37 PM PDT 24
Finished Jul 11 05:22:09 PM PDT 24
Peak memory 250912 kb
Host smart-6d57c349-1672-41e5-8b4a-7b9e726be961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183887884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4183887884
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.568254619
Short name T332
Test name
Test status
Simulation time 71818639 ps
CPU time 7.37 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 250920 kb
Host smart-f24b1382-d88d-4c19-9d3a-9748001a7a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568254619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.568254619
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1481015984
Short name T615
Test name
Test status
Simulation time 5011150412 ps
CPU time 42.61 seconds
Started Jul 11 05:21:41 PM PDT 24
Finished Jul 11 05:22:33 PM PDT 24
Peak memory 225944 kb
Host smart-da33a01d-1c7d-4bf9-8271-28ac9c6f4ec6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481015984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1481015984
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.780304607
Short name T176
Test name
Test status
Simulation time 109797634159 ps
CPU time 1182.27 seconds
Started Jul 11 05:21:43 PM PDT 24
Finished Jul 11 05:41:34 PM PDT 24
Peak memory 389212 kb
Host smart-303d628c-d87a-4169-b303-423bbd5c4308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=780304607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.780304607
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3047105447
Short name T844
Test name
Test status
Simulation time 33904756 ps
CPU time 0.89 seconds
Started Jul 11 05:21:34 PM PDT 24
Finished Jul 11 05:21:40 PM PDT 24
Peak memory 211784 kb
Host smart-0d293839-6fd7-4716-b5b2-7dcbed6940fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047105447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3047105447
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1048186408
Short name T487
Test name
Test status
Simulation time 17912747 ps
CPU time 1.15 seconds
Started Jul 11 05:21:43 PM PDT 24
Finished Jul 11 05:21:53 PM PDT 24
Peak memory 208840 kb
Host smart-f373980f-4274-45a1-a387-4678582c1b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048186408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1048186408
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.784276108
Short name T239
Test name
Test status
Simulation time 1646333277 ps
CPU time 15.63 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:22:05 PM PDT 24
Peak memory 218168 kb
Host smart-90880eb3-bf63-4de6-927a-3f6466387728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784276108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.784276108
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.6762041
Short name T8
Test name
Test status
Simulation time 1277920087 ps
CPU time 4.27 seconds
Started Jul 11 05:21:39 PM PDT 24
Finished Jul 11 05:21:51 PM PDT 24
Peak memory 217116 kb
Host smart-77416bd1-8b2d-4ba7-ac95-1b1ec63db20e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6762041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.6762041
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1058915600
Short name T713
Test name
Test status
Simulation time 268752933 ps
CPU time 3.59 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:21:52 PM PDT 24
Peak memory 222232 kb
Host smart-80e654a2-2a32-41eb-8996-c493f4c145b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058915600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1058915600
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.734229621
Short name T630
Test name
Test status
Simulation time 1130169690 ps
CPU time 13.08 seconds
Started Jul 11 05:21:49 PM PDT 24
Finished Jul 11 05:22:10 PM PDT 24
Peak memory 225976 kb
Host smart-941cbda9-68d8-43b2-b1f4-1226d2a663df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734229621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.734229621
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1456107475
Short name T489
Test name
Test status
Simulation time 2093015129 ps
CPU time 15.41 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:28 PM PDT 24
Peak memory 225896 kb
Host smart-246376d6-cf58-446b-8061-a39d8c08f08d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456107475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1456107475
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2127590064
Short name T250
Test name
Test status
Simulation time 1349037441 ps
CPU time 10.81 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:21:58 PM PDT 24
Peak memory 218096 kb
Host smart-cc4faba3-d2d0-482f-8e32-728d1a41cfde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127590064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2127590064
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2714651755
Short name T525
Test name
Test status
Simulation time 865762929 ps
CPU time 6.31 seconds
Started Jul 11 05:21:46 PM PDT 24
Finished Jul 11 05:22:00 PM PDT 24
Peak memory 224308 kb
Host smart-11de314c-8123-46a2-96a8-44c5b5fb1a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714651755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2714651755
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.178521271
Short name T808
Test name
Test status
Simulation time 40950146 ps
CPU time 2.2 seconds
Started Jul 11 05:21:46 PM PDT 24
Finished Jul 11 05:21:56 PM PDT 24
Peak memory 217528 kb
Host smart-77d622e5-0da6-4e60-ab88-8a19504bd62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178521271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.178521271
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.4227298217
Short name T680
Test name
Test status
Simulation time 1011122890 ps
CPU time 19.25 seconds
Started Jul 11 05:21:51 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 250896 kb
Host smart-350b6af8-2fed-4d97-bdb4-435af529aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227298217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.4227298217
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3824298764
Short name T571
Test name
Test status
Simulation time 151226997 ps
CPU time 6.45 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 250900 kb
Host smart-7592b4f0-5bae-4091-b912-e94b0def3cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824298764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3824298764
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2310162281
Short name T712
Test name
Test status
Simulation time 8096967001 ps
CPU time 170.86 seconds
Started Jul 11 05:21:42 PM PDT 24
Finished Jul 11 05:24:41 PM PDT 24
Peak memory 299908 kb
Host smart-166a3fe7-d51b-4dfc-a6a8-36b35db3d052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310162281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2310162281
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2499855467
Short name T739
Test name
Test status
Simulation time 20854675 ps
CPU time 1.05 seconds
Started Jul 11 05:21:46 PM PDT 24
Finished Jul 11 05:21:55 PM PDT 24
Peak memory 212844 kb
Host smart-798f20f2-5016-4bbf-ac7e-cb1e3f348953
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499855467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2499855467
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1809114557
Short name T377
Test name
Test status
Simulation time 153513336 ps
CPU time 1.16 seconds
Started Jul 11 05:21:49 PM PDT 24
Finished Jul 11 05:21:58 PM PDT 24
Peak memory 208964 kb
Host smart-f0d6c0dd-cf1d-4a52-87aa-622901852ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809114557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1809114557
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2037679482
Short name T224
Test name
Test status
Simulation time 3227432626 ps
CPU time 17.63 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:30 PM PDT 24
Peak memory 225968 kb
Host smart-5271ebfd-5b22-4043-b3e4-c908e14aefbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037679482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2037679482
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.4248056808
Short name T441
Test name
Test status
Simulation time 66337726 ps
CPU time 2.33 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:09 PM PDT 24
Peak memory 217100 kb
Host smart-b199f0ab-f2e1-4ada-bd85-0b9b4fd96ecf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248056808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.4248056808
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.958777905
Short name T804
Test name
Test status
Simulation time 14795366 ps
CPU time 1.55 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:14 PM PDT 24
Peak memory 218008 kb
Host smart-5635eb59-4b95-478f-b2d8-95f81bc8e818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958777905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.958777905
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.335500144
Short name T716
Test name
Test status
Simulation time 1377980527 ps
CPU time 15.97 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:29 PM PDT 24
Peak memory 225920 kb
Host smart-e3bdeeeb-25cb-469b-8b78-7fae5acda3e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335500144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.335500144
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.105774035
Short name T411
Test name
Test status
Simulation time 1337338536 ps
CPU time 21.35 seconds
Started Jul 11 05:21:51 PM PDT 24
Finished Jul 11 05:22:19 PM PDT 24
Peak memory 225980 kb
Host smart-88ffcd52-fb34-4cec-9d3b-e9c464d64c7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105774035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.105774035
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3799504163
Short name T478
Test name
Test status
Simulation time 1551397381 ps
CPU time 13.31 seconds
Started Jul 11 05:21:51 PM PDT 24
Finished Jul 11 05:22:12 PM PDT 24
Peak memory 218048 kb
Host smart-930d7dbf-08c3-4cca-9c31-7a09eeee9c63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799504163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3799504163
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3047416552
Short name T328
Test name
Test status
Simulation time 3001043394 ps
CPU time 13.73 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 218224 kb
Host smart-e3916b4d-2101-48c1-a290-cb3828e25a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047416552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3047416552
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.762198446
Short name T69
Test name
Test status
Simulation time 21520983 ps
CPU time 1.13 seconds
Started Jul 11 05:21:40 PM PDT 24
Finished Jul 11 05:21:50 PM PDT 24
Peak memory 213396 kb
Host smart-dea95a6f-8f23-4909-8409-ecc9de45d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762198446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.762198446
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3256373735
Short name T673
Test name
Test status
Simulation time 801365385 ps
CPU time 6.89 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:14 PM PDT 24
Peak memory 247308 kb
Host smart-3c2c9304-9928-4982-bcbb-cc867f584d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256373735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3256373735
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2749338276
Short name T464
Test name
Test status
Simulation time 84893848590 ps
CPU time 479.55 seconds
Started Jul 11 05:21:46 PM PDT 24
Finished Jul 11 05:29:53 PM PDT 24
Peak memory 276736 kb
Host smart-9cbaca71-cbc9-4182-87e2-6d91a7e4764d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749338276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2749338276
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1744638711
Short name T558
Test name
Test status
Simulation time 32463836 ps
CPU time 0.85 seconds
Started Jul 11 05:21:41 PM PDT 24
Finished Jul 11 05:21:51 PM PDT 24
Peak memory 211692 kb
Host smart-e949c412-aff1-4030-b3c7-b1a1e56f566f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744638711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1744638711
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2671687490
Short name T637
Test name
Test status
Simulation time 15518427 ps
CPU time 1.03 seconds
Started Jul 11 05:21:46 PM PDT 24
Finished Jul 11 05:21:55 PM PDT 24
Peak memory 208956 kb
Host smart-3e85b445-2fa5-438e-bd97-886b161a8eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671687490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2671687490
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2614794457
Short name T732
Test name
Test status
Simulation time 647517711 ps
CPU time 10.48 seconds
Started Jul 11 05:21:48 PM PDT 24
Finished Jul 11 05:22:07 PM PDT 24
Peak memory 225960 kb
Host smart-fbe3431b-e407-4795-8076-c28dabd0005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614794457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2614794457
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1158643623
Short name T26
Test name
Test status
Simulation time 460793526 ps
CPU time 6.41 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:22:01 PM PDT 24
Peak memory 217356 kb
Host smart-cccf84d8-ab47-4007-bd81-b0f37ac3f84b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158643623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1158643623
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4082814162
Short name T270
Test name
Test status
Simulation time 68494339 ps
CPU time 2.42 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:21:57 PM PDT 24
Peak memory 222120 kb
Host smart-476c287f-69fb-4f75-bfb7-d0dc0340475f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082814162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4082814162
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2144590760
Short name T15
Test name
Test status
Simulation time 1303403851 ps
CPU time 9.62 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:22:04 PM PDT 24
Peak memory 225980 kb
Host smart-0abb9d38-3709-4bb9-82b2-ea85f92c56e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144590760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2144590760
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1291515118
Short name T183
Test name
Test status
Simulation time 260612252 ps
CPU time 11.04 seconds
Started Jul 11 05:21:55 PM PDT 24
Finished Jul 11 05:22:12 PM PDT 24
Peak memory 225984 kb
Host smart-42e20d97-654a-48a7-9f3a-bfde52ff3d2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291515118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1291515118
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1062975635
Short name T375
Test name
Test status
Simulation time 2487115460 ps
CPU time 11.73 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 218104 kb
Host smart-b4539143-5c44-46e9-b993-12856f96595c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062975635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1062975635
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3068167599
Short name T770
Test name
Test status
Simulation time 802988676 ps
CPU time 8.89 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:22:03 PM PDT 24
Peak memory 225988 kb
Host smart-4ef24f11-6c19-4501-9f8b-8e3440a6770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068167599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3068167599
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.717669449
Short name T187
Test name
Test status
Simulation time 208166291 ps
CPU time 3.71 seconds
Started Jul 11 05:21:54 PM PDT 24
Finished Jul 11 05:22:04 PM PDT 24
Peak memory 217616 kb
Host smart-6cc95791-2ad1-4a44-9081-e581bb0a6bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717669449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.717669449
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1797926815
Short name T252
Test name
Test status
Simulation time 1047222246 ps
CPU time 19.72 seconds
Started Jul 11 05:21:48 PM PDT 24
Finished Jul 11 05:22:15 PM PDT 24
Peak memory 250852 kb
Host smart-6d51d2b5-1981-454c-ad84-7dbc60882875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797926815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1797926815
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1800329854
Short name T226
Test name
Test status
Simulation time 395857214 ps
CPU time 7.71 seconds
Started Jul 11 05:21:52 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 250992 kb
Host smart-554a975a-9334-4b3e-87ac-84c7146aac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800329854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1800329854
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.600946751
Short name T865
Test name
Test status
Simulation time 19424615597 ps
CPU time 221.65 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:25:36 PM PDT 24
Peak memory 225952 kb
Host smart-ed8c193c-b371-4425-a311-eac5ab3f8522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600946751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.600946751
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.4158478672
Short name T157
Test name
Test status
Simulation time 15307615395 ps
CPU time 276.13 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:26:49 PM PDT 24
Peak memory 364900 kb
Host smart-43de9503-1cdc-491a-b7c4-899326eb1317
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4158478672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.4158478672
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.242296629
Short name T462
Test name
Test status
Simulation time 41541367 ps
CPU time 0.85 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:21:55 PM PDT 24
Peak memory 212800 kb
Host smart-37e3d7a0-3b15-4871-8a5f-d3c76e96ef71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242296629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.242296629
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1583351601
Short name T393
Test name
Test status
Simulation time 74965033 ps
CPU time 1.03 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:14 PM PDT 24
Peak memory 208880 kb
Host smart-fc5fa093-2cb8-443d-941a-ff9b8fad0dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583351601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1583351601
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1598269206
Short name T843
Test name
Test status
Simulation time 218268607 ps
CPU time 9.17 seconds
Started Jul 11 05:21:53 PM PDT 24
Finished Jul 11 05:22:09 PM PDT 24
Peak memory 218108 kb
Host smart-25390615-b240-47c2-a753-2d79d637c176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598269206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1598269206
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2465340482
Short name T736
Test name
Test status
Simulation time 1337805719 ps
CPU time 4.87 seconds
Started Jul 11 05:21:51 PM PDT 24
Finished Jul 11 05:22:03 PM PDT 24
Peak memory 217256 kb
Host smart-9afd62cf-de7a-450a-b1f3-df2d08e2f78f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465340482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2465340482
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.4175394045
Short name T720
Test name
Test status
Simulation time 125239174 ps
CPU time 3.63 seconds
Started Jul 11 05:21:54 PM PDT 24
Finished Jul 11 05:22:04 PM PDT 24
Peak memory 218088 kb
Host smart-17c344e1-5a45-4917-aaed-4ab350a640a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175394045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.4175394045
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3153831773
Short name T825
Test name
Test status
Simulation time 3989053011 ps
CPU time 10.31 seconds
Started Jul 11 05:21:54 PM PDT 24
Finished Jul 11 05:22:11 PM PDT 24
Peak memory 226020 kb
Host smart-9e1f3c52-525d-4fe1-a35d-726486c45723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153831773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3153831773
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2597864110
Short name T500
Test name
Test status
Simulation time 1219801053 ps
CPU time 7.5 seconds
Started Jul 11 05:21:46 PM PDT 24
Finished Jul 11 05:22:00 PM PDT 24
Peak memory 226064 kb
Host smart-0d6c5064-4210-46f0-a5f1-9179e5adf283
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597864110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2597864110
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3815534266
Short name T612
Test name
Test status
Simulation time 320853629 ps
CPU time 9.41 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:22:05 PM PDT 24
Peak memory 225968 kb
Host smart-a1ef2ed3-d351-418d-ab4d-050459e7f2cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815534266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3815534266
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.595769073
Short name T582
Test name
Test status
Simulation time 672085803 ps
CPU time 10.08 seconds
Started Jul 11 05:21:51 PM PDT 24
Finished Jul 11 05:22:08 PM PDT 24
Peak memory 224900 kb
Host smart-50f028d6-5fce-4ebc-9957-80e4b19702ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595769073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.595769073
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.393482961
Short name T643
Test name
Test status
Simulation time 28151973 ps
CPU time 1.98 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:21:56 PM PDT 24
Peak memory 217584 kb
Host smart-484158b2-d94b-4ccd-be0f-91f29759ed82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393482961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.393482961
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.394968811
Short name T433
Test name
Test status
Simulation time 255864480 ps
CPU time 22.62 seconds
Started Jul 11 05:21:47 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 251180 kb
Host smart-289616f3-0920-46da-94b0-d56900326a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394968811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.394968811
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1048920827
Short name T390
Test name
Test status
Simulation time 68284507 ps
CPU time 7 seconds
Started Jul 11 05:21:48 PM PDT 24
Finished Jul 11 05:22:03 PM PDT 24
Peak memory 246416 kb
Host smart-27540fea-1042-4a7f-979d-110cf5021323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048920827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1048920827
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2119894089
Short name T434
Test name
Test status
Simulation time 9607404076 ps
CPU time 78.91 seconds
Started Jul 11 05:21:48 PM PDT 24
Finished Jul 11 05:23:15 PM PDT 24
Peak memory 226064 kb
Host smart-2b23cc4f-e87d-473c-ad38-7505b7354296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119894089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2119894089
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.764290173
Short name T697
Test name
Test status
Simulation time 30461148 ps
CPU time 0.92 seconds
Started Jul 11 05:21:44 PM PDT 24
Finished Jul 11 05:21:53 PM PDT 24
Peak memory 212948 kb
Host smart-240906b8-2218-4634-ae41-765d2aa0c0bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764290173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.764290173
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1301693288
Short name T576
Test name
Test status
Simulation time 27829142 ps
CPU time 1.4 seconds
Started Jul 11 05:21:56 PM PDT 24
Finished Jul 11 05:22:02 PM PDT 24
Peak memory 209012 kb
Host smart-772cf486-36fb-4565-a7a7-d71bd0dc3a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301693288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1301693288
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3940681878
Short name T438
Test name
Test status
Simulation time 430264079 ps
CPU time 12.11 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:19 PM PDT 24
Peak memory 225952 kb
Host smart-ff808e7d-9482-4b10-973c-334ef568b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940681878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3940681878
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.360951499
Short name T431
Test name
Test status
Simulation time 1427144063 ps
CPU time 33.23 seconds
Started Jul 11 05:21:59 PM PDT 24
Finished Jul 11 05:22:37 PM PDT 24
Peak memory 217740 kb
Host smart-3b1c71dd-8659-4f05-b6fb-c58ba3ab2df8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360951499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.360951499
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1106666018
Short name T570
Test name
Test status
Simulation time 44867617 ps
CPU time 2.65 seconds
Started Jul 11 05:21:53 PM PDT 24
Finished Jul 11 05:22:02 PM PDT 24
Peak memory 222224 kb
Host smart-82f830df-052e-49c3-9996-fc4cb75c94d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106666018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1106666018
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3014579264
Short name T447
Test name
Test status
Simulation time 565511880 ps
CPU time 10.34 seconds
Started Jul 11 05:21:52 PM PDT 24
Finished Jul 11 05:22:10 PM PDT 24
Peak memory 225968 kb
Host smart-8919ed5c-3ca6-493a-89d2-9eec162e90fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014579264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3014579264
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.38309100
Short name T194
Test name
Test status
Simulation time 239093073 ps
CPU time 7.04 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:21 PM PDT 24
Peak memory 218148 kb
Host smart-24f3e04e-64b9-41d9-b827-e4ac261f827d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38309100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.38309100
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.502606130
Short name T694
Test name
Test status
Simulation time 840237611 ps
CPU time 11.97 seconds
Started Jul 11 05:21:54 PM PDT 24
Finished Jul 11 05:22:13 PM PDT 24
Peak memory 218156 kb
Host smart-5e6932e4-090f-43c7-9a73-4a45ab805bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502606130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.502606130
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1672161738
Short name T351
Test name
Test status
Simulation time 26532433 ps
CPU time 1.63 seconds
Started Jul 11 05:21:52 PM PDT 24
Finished Jul 11 05:22:01 PM PDT 24
Peak memory 213896 kb
Host smart-634b56e9-6679-45be-be06-04dff9c0bf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672161738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1672161738
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.690549192
Short name T652
Test name
Test status
Simulation time 278409499 ps
CPU time 23.73 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 250920 kb
Host smart-a96976e8-6bf0-4e83-8a77-889c8e8500c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690549192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.690549192
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1851736911
Short name T616
Test name
Test status
Simulation time 89781778 ps
CPU time 6.61 seconds
Started Jul 11 05:21:56 PM PDT 24
Finished Jul 11 05:22:08 PM PDT 24
Peak memory 250456 kb
Host smart-eb8a8113-d3bb-410d-8b62-e09f76daa8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851736911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1851736911
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.589947351
Short name T548
Test name
Test status
Simulation time 36687872223 ps
CPU time 159.99 seconds
Started Jul 11 05:21:54 PM PDT 24
Finished Jul 11 05:24:41 PM PDT 24
Peak memory 302104 kb
Host smart-544c16ce-217c-4591-8006-ee39e82ae072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589947351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.589947351
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3427842527
Short name T662
Test name
Test status
Simulation time 33476033 ps
CPU time 0.95 seconds
Started Jul 11 05:22:02 PM PDT 24
Finished Jul 11 05:22:10 PM PDT 24
Peak memory 211828 kb
Host smart-fae190bb-eef4-4813-a1d4-279dcd7aa36b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427842527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3427842527
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.660112347
Short name T106
Test name
Test status
Simulation time 32134102 ps
CPU time 1.09 seconds
Started Jul 11 05:21:58 PM PDT 24
Finished Jul 11 05:22:04 PM PDT 24
Peak memory 208952 kb
Host smart-8a1309d6-f6be-4e16-b5d1-e0188ef97d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660112347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.660112347
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3458451996
Short name T505
Test name
Test status
Simulation time 663648660 ps
CPU time 11.7 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:24 PM PDT 24
Peak memory 218056 kb
Host smart-97641a53-5212-4061-b270-d6c0b42e1800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458451996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3458451996
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3731839978
Short name T27
Test name
Test status
Simulation time 2748013542 ps
CPU time 16.49 seconds
Started Jul 11 05:21:52 PM PDT 24
Finished Jul 11 05:22:15 PM PDT 24
Peak memory 217468 kb
Host smart-fd5a3e79-d35b-409d-9b19-760bda96550e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731839978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3731839978
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2179411336
Short name T691
Test name
Test status
Simulation time 186155544 ps
CPU time 2.61 seconds
Started Jul 11 05:22:02 PM PDT 24
Finished Jul 11 05:22:11 PM PDT 24
Peak memory 222040 kb
Host smart-37f1d736-5dce-4b2d-a55d-31029de80783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179411336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2179411336
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1158572842
Short name T848
Test name
Test status
Simulation time 382524288 ps
CPU time 10.39 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 225888 kb
Host smart-76932292-2138-42f3-8136-642dd75b0593
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158572842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1158572842
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3181181079
Short name T256
Test name
Test status
Simulation time 713798883 ps
CPU time 13.72 seconds
Started Jul 11 05:21:51 PM PDT 24
Finished Jul 11 05:22:12 PM PDT 24
Peak memory 225964 kb
Host smart-3e5d5d3c-1b04-4d8e-8602-33d2080a5b82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181181079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3181181079
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3338298598
Short name T539
Test name
Test status
Simulation time 2497092902 ps
CPU time 11.92 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 225800 kb
Host smart-d8647879-cfec-4731-a9cd-66cc38959627
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338298598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3338298598
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3157714660
Short name T334
Test name
Test status
Simulation time 355738659 ps
CPU time 8.71 seconds
Started Jul 11 05:21:52 PM PDT 24
Finished Jul 11 05:22:07 PM PDT 24
Peak memory 218120 kb
Host smart-79d0d7f7-7373-41e7-a274-673c27655085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157714660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3157714660
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2714168919
Short name T611
Test name
Test status
Simulation time 12637704 ps
CPU time 1.16 seconds
Started Jul 11 05:22:00 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 211948 kb
Host smart-11821031-5923-4bd4-bfcd-3365f66ed64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714168919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2714168919
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1887704603
Short name T647
Test name
Test status
Simulation time 919275511 ps
CPU time 21.3 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:32 PM PDT 24
Peak memory 250852 kb
Host smart-774ec2d3-086e-4b70-af80-502809a1ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887704603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1887704603
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.283718196
Short name T574
Test name
Test status
Simulation time 78503057 ps
CPU time 8.87 seconds
Started Jul 11 05:21:51 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 250808 kb
Host smart-7f0c32f9-0f40-416c-857f-cee50c4dc034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283718196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.283718196
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.340648049
Short name T41
Test name
Test status
Simulation time 3377230804 ps
CPU time 104.22 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:23:51 PM PDT 24
Peak memory 225948 kb
Host smart-72bd2323-0fb9-424e-b614-8d3f320b3a1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340648049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.340648049
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.276318208
Short name T674
Test name
Test status
Simulation time 18183788 ps
CPU time 1.18 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:16 PM PDT 24
Peak memory 212972 kb
Host smart-2dbad718-bf66-4ccc-a040-14419c498bbe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276318208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.276318208
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.98542295
Short name T307
Test name
Test status
Simulation time 25087046 ps
CPU time 1 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:44 PM PDT 24
Peak memory 208792 kb
Host smart-cda21948-5cf1-4b3d-8eb9-762f08892e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98542295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.98542295
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.4090901747
Short name T221
Test name
Test status
Simulation time 62246103 ps
CPU time 0.96 seconds
Started Jul 11 05:19:18 PM PDT 24
Finished Jul 11 05:19:21 PM PDT 24
Peak memory 208888 kb
Host smart-151e9476-5771-4511-9782-9071eedbd78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090901747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.4090901747
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.924681352
Short name T594
Test name
Test status
Simulation time 259504749 ps
CPU time 7.87 seconds
Started Jul 11 05:19:14 PM PDT 24
Finished Jul 11 05:19:25 PM PDT 24
Peak memory 218400 kb
Host smart-ac6f1311-2bd3-4ca4-a633-0bd53a36dc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924681352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.924681352
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1099634677
Short name T530
Test name
Test status
Simulation time 38365246 ps
CPU time 1.7 seconds
Started Jul 11 05:19:21 PM PDT 24
Finished Jul 11 05:19:25 PM PDT 24
Peak memory 217008 kb
Host smart-f25a0c22-413d-4008-b161-0b2b1f8d4ac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099634677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1099634677
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.108406964
Short name T454
Test name
Test status
Simulation time 1898083560 ps
CPU time 30.82 seconds
Started Jul 11 05:19:25 PM PDT 24
Finished Jul 11 05:19:57 PM PDT 24
Peak memory 225976 kb
Host smart-44925f88-eb36-4356-9d33-913d8b1bad8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108406964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.108406964
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3633378777
Short name T482
Test name
Test status
Simulation time 1047981275 ps
CPU time 4.06 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:47 PM PDT 24
Peak memory 217416 kb
Host smart-143294de-0bba-4303-8c80-7c0df058ff51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633378777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
633378777
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1744919284
Short name T659
Test name
Test status
Simulation time 92246473 ps
CPU time 3.3 seconds
Started Jul 11 05:19:10 PM PDT 24
Finished Jul 11 05:19:18 PM PDT 24
Peak memory 218148 kb
Host smart-7279ada4-10d9-4cde-92c1-5196fc39d30a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744919284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1744919284
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3132349639
Short name T409
Test name
Test status
Simulation time 1112082966 ps
CPU time 33.66 seconds
Started Jul 11 05:19:20 PM PDT 24
Finished Jul 11 05:19:56 PM PDT 24
Peak memory 217568 kb
Host smart-11e7975a-0e22-4664-9e2c-00273bc668b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132349639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3132349639
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2477165008
Short name T104
Test name
Test status
Simulation time 172228464 ps
CPU time 3.78 seconds
Started Jul 11 05:19:15 PM PDT 24
Finished Jul 11 05:19:21 PM PDT 24
Peak memory 217568 kb
Host smart-559f5e36-4950-4210-8904-3c09e56be32e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477165008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2477165008
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3231743534
Short name T230
Test name
Test status
Simulation time 1552430248 ps
CPU time 62.81 seconds
Started Jul 11 05:19:25 PM PDT 24
Finished Jul 11 05:20:29 PM PDT 24
Peak memory 275508 kb
Host smart-cc986269-7e1a-43d5-be28-ebbff9275fcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231743534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3231743534
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.102564545
Short name T295
Test name
Test status
Simulation time 1339401284 ps
CPU time 17.43 seconds
Started Jul 11 05:19:12 PM PDT 24
Finished Jul 11 05:19:34 PM PDT 24
Peak memory 250772 kb
Host smart-64bb2d2e-5cf2-40d3-99d9-069daab6c8ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102564545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.102564545
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2675671814
Short name T440
Test name
Test status
Simulation time 45663841 ps
CPU time 2.55 seconds
Started Jul 11 05:19:12 PM PDT 24
Finished Jul 11 05:19:18 PM PDT 24
Peak memory 222264 kb
Host smart-294433e8-ddff-4b94-a1fb-4338d081bcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675671814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2675671814
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1496586663
Short name T682
Test name
Test status
Simulation time 195229882 ps
CPU time 7.64 seconds
Started Jul 11 05:19:15 PM PDT 24
Finished Jul 11 05:19:25 PM PDT 24
Peak memory 217584 kb
Host smart-79246c57-c35f-407b-a782-148b1000af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496586663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1496586663
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3180098325
Short name T245
Test name
Test status
Simulation time 2750208796 ps
CPU time 20.44 seconds
Started Jul 11 05:19:18 PM PDT 24
Finished Jul 11 05:19:40 PM PDT 24
Peak memory 226024 kb
Host smart-8c3fdf44-659e-47e9-bd7e-f3db9e4b7653
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180098325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3180098325
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2503768436
Short name T322
Test name
Test status
Simulation time 562556158 ps
CPU time 13.16 seconds
Started Jul 11 05:19:31 PM PDT 24
Finished Jul 11 05:19:45 PM PDT 24
Peak memory 225900 kb
Host smart-b4e67f07-646d-4647-ac87-cf68baa7b123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503768436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2503768436
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.257417195
Short name T268
Test name
Test status
Simulation time 1019950222 ps
CPU time 6.36 seconds
Started Jul 11 05:19:20 PM PDT 24
Finished Jul 11 05:19:29 PM PDT 24
Peak memory 225980 kb
Host smart-3012fd73-0336-4efd-8cbf-ddd3ea31c8e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257417195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.257417195
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1018145026
Short name T638
Test name
Test status
Simulation time 547993660 ps
CPU time 13.61 seconds
Started Jul 11 05:19:12 PM PDT 24
Finished Jul 11 05:19:30 PM PDT 24
Peak memory 225892 kb
Host smart-5f52342d-a2d1-4c8a-8f6e-2d28dd73e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018145026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1018145026
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.837245785
Short name T760
Test name
Test status
Simulation time 79562503 ps
CPU time 1.57 seconds
Started Jul 11 05:19:13 PM PDT 24
Finished Jul 11 05:19:18 PM PDT 24
Peak memory 213788 kb
Host smart-100e5683-0fc5-45a8-9968-572c329f7c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837245785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.837245785
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1286978048
Short name T511
Test name
Test status
Simulation time 508863782 ps
CPU time 24.11 seconds
Started Jul 11 05:19:12 PM PDT 24
Finished Jul 11 05:19:40 PM PDT 24
Peak memory 250840 kb
Host smart-1e336212-bb08-495b-83f9-7b1af40a63f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286978048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1286978048
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2731489407
Short name T569
Test name
Test status
Simulation time 67176430 ps
CPU time 3.54 seconds
Started Jul 11 05:19:15 PM PDT 24
Finished Jul 11 05:19:21 PM PDT 24
Peak memory 218080 kb
Host smart-c96d945e-3efe-4200-9eab-b489086b475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731489407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2731489407
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3980274357
Short name T816
Test name
Test status
Simulation time 43356637770 ps
CPU time 220.67 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:23:25 PM PDT 24
Peak memory 283592 kb
Host smart-95dd3def-b4a1-4c57-827d-891d81824c75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980274357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3980274357
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1827546803
Short name T186
Test name
Test status
Simulation time 26795510267 ps
CPU time 127.04 seconds
Started Jul 11 05:19:19 PM PDT 24
Finished Jul 11 05:21:28 PM PDT 24
Peak memory 259456 kb
Host smart-8379571d-c473-45b9-a598-5bf95b745263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1827546803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1827546803
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2150700359
Short name T459
Test name
Test status
Simulation time 23682949 ps
CPU time 0.86 seconds
Started Jul 11 05:19:18 PM PDT 24
Finished Jul 11 05:19:21 PM PDT 24
Peak memory 211832 kb
Host smart-ca3b94d5-4446-4e7d-8699-8cd893fbdbd4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150700359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2150700359
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3141649746
Short name T381
Test name
Test status
Simulation time 96527254 ps
CPU time 0.88 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:45 PM PDT 24
Peak memory 208736 kb
Host smart-a461f4ab-cad5-4203-bc97-13fffe1674b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141649746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3141649746
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.206456754
Short name T66
Test name
Test status
Simulation time 390403299 ps
CPU time 18.19 seconds
Started Jul 11 05:19:21 PM PDT 24
Finished Jul 11 05:19:41 PM PDT 24
Peak memory 218168 kb
Host smart-307b7dbd-7f7d-427a-a069-8152a9d68237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206456754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.206456754
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1034579879
Short name T812
Test name
Test status
Simulation time 63513305 ps
CPU time 1.69 seconds
Started Jul 11 05:19:21 PM PDT 24
Finished Jul 11 05:19:25 PM PDT 24
Peak memory 217024 kb
Host smart-b346c7cf-5857-4f67-adfd-1908ca2100a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034579879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1034579879
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3139605201
Short name T501
Test name
Test status
Simulation time 13076542775 ps
CPU time 87.74 seconds
Started Jul 11 05:19:23 PM PDT 24
Finished Jul 11 05:20:52 PM PDT 24
Peak memory 226000 kb
Host smart-09b39dc9-a0c4-4e2e-879d-80277b382cb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139605201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3139605201
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.312411274
Short name T719
Test name
Test status
Simulation time 708511103 ps
CPU time 5.47 seconds
Started Jul 11 05:19:31 PM PDT 24
Finished Jul 11 05:19:37 PM PDT 24
Peak memory 217604 kb
Host smart-fb04c39a-f8c2-4ab5-8852-9e4ebf2facb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312411274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.312411274
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1990337065
Short name T752
Test name
Test status
Simulation time 1508799255 ps
CPU time 12.01 seconds
Started Jul 11 05:19:21 PM PDT 24
Finished Jul 11 05:19:35 PM PDT 24
Peak memory 223200 kb
Host smart-e4125c42-4924-49b3-9ced-6d6fe7ed1fea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990337065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1990337065
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2280713129
Short name T520
Test name
Test status
Simulation time 1752536653 ps
CPU time 25.27 seconds
Started Jul 11 05:19:20 PM PDT 24
Finished Jul 11 05:19:48 PM PDT 24
Peak memory 217648 kb
Host smart-3042203e-22aa-410b-9218-183a74155623
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280713129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2280713129
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.688721627
Short name T627
Test name
Test status
Simulation time 263436672 ps
CPU time 1.42 seconds
Started Jul 11 05:19:22 PM PDT 24
Finished Jul 11 05:19:25 PM PDT 24
Peak memory 217768 kb
Host smart-bffaae97-3f2c-49bf-87ec-92bb647273ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688721627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.688721627
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3557690285
Short name T275
Test name
Test status
Simulation time 6334315574 ps
CPU time 45.71 seconds
Started Jul 11 05:19:23 PM PDT 24
Finished Jul 11 05:20:10 PM PDT 24
Peak memory 277232 kb
Host smart-6780c064-b22d-4157-a283-ab952447ba4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557690285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3557690285
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1176701348
Short name T172
Test name
Test status
Simulation time 1773441461 ps
CPU time 16.89 seconds
Started Jul 11 05:19:21 PM PDT 24
Finished Jul 11 05:19:40 PM PDT 24
Peak memory 250464 kb
Host smart-92bf997c-b1de-4fb2-b40a-eb375bb09e67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176701348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1176701348
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.4107577027
Short name T310
Test name
Test status
Simulation time 86500104 ps
CPU time 2.5 seconds
Started Jul 11 05:19:41 PM PDT 24
Finished Jul 11 05:19:46 PM PDT 24
Peak memory 218048 kb
Host smart-c1182b9a-e24b-4f25-849d-8101ed805c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107577027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.4107577027
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3273280997
Short name T733
Test name
Test status
Simulation time 417191041 ps
CPU time 14.26 seconds
Started Jul 11 05:19:26 PM PDT 24
Finished Jul 11 05:19:42 PM PDT 24
Peak memory 217604 kb
Host smart-aa161aad-86b4-4643-b670-d1413343613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273280997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3273280997
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2103961429
Short name T841
Test name
Test status
Simulation time 768857312 ps
CPU time 10.84 seconds
Started Jul 11 05:19:21 PM PDT 24
Finished Jul 11 05:19:34 PM PDT 24
Peak memory 218400 kb
Host smart-01c35316-a60e-4e1f-8e14-92db96ae68ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103961429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2103961429
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1231875299
Short name T420
Test name
Test status
Simulation time 280668674 ps
CPU time 7.5 seconds
Started Jul 11 05:19:17 PM PDT 24
Finished Jul 11 05:19:27 PM PDT 24
Peak memory 225896 kb
Host smart-1dfd23bf-3362-4d44-8af5-63c9212f99ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231875299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1231875299
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.994959557
Short name T827
Test name
Test status
Simulation time 900269359 ps
CPU time 9.96 seconds
Started Jul 11 05:19:26 PM PDT 24
Finished Jul 11 05:19:38 PM PDT 24
Peak memory 225908 kb
Host smart-034491b4-c21f-43ce-ac06-043c6d4b587d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994959557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.994959557
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.311407973
Short name T419
Test name
Test status
Simulation time 346172542 ps
CPU time 12.64 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:56 PM PDT 24
Peak memory 218232 kb
Host smart-240ef177-09cf-4f6f-b367-5f2124c6a9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311407973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.311407973
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2046867098
Short name T483
Test name
Test status
Simulation time 91912432 ps
CPU time 1.78 seconds
Started Jul 11 05:19:17 PM PDT 24
Finished Jul 11 05:19:21 PM PDT 24
Peak memory 214124 kb
Host smart-d15e9c53-614e-49d4-a007-621ef442aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046867098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2046867098
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.489119209
Short name T531
Test name
Test status
Simulation time 189865307 ps
CPU time 18.8 seconds
Started Jul 11 05:19:26 PM PDT 24
Finished Jul 11 05:19:47 PM PDT 24
Peak memory 250860 kb
Host smart-25c4967a-822b-4565-9096-53d70841712e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489119209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.489119209
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1711167995
Short name T701
Test name
Test status
Simulation time 88112141 ps
CPU time 6.91 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:49 PM PDT 24
Peak memory 250436 kb
Host smart-9388e8a4-17fd-4d47-a20d-cbb5c131413e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711167995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1711167995
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4236919220
Short name T700
Test name
Test status
Simulation time 15337604633 ps
CPU time 256.37 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:24:00 PM PDT 24
Peak memory 278316 kb
Host smart-b2531ae4-9c6a-46e2-b73c-1b77d4b4fad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236919220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4236919220
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3459253639
Short name T714
Test name
Test status
Simulation time 13116649 ps
CPU time 0.83 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:43 PM PDT 24
Peak memory 211704 kb
Host smart-c9bafc63-3459-4649-9195-34bafb1f1933
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459253639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3459253639
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2474436417
Short name T648
Test name
Test status
Simulation time 47649134 ps
CPU time 0.86 seconds
Started Jul 11 05:19:35 PM PDT 24
Finished Jul 11 05:19:37 PM PDT 24
Peak memory 208712 kb
Host smart-b0036f01-377a-417a-a820-0a8060d2f88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474436417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2474436417
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2237280595
Short name T220
Test name
Test status
Simulation time 28957161 ps
CPU time 0.78 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:19:51 PM PDT 24
Peak memory 208892 kb
Host smart-00b70b71-924c-484a-bc7d-0de7a3ce47b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237280595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2237280595
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.403834992
Short name T305
Test name
Test status
Simulation time 664894862 ps
CPU time 15.71 seconds
Started Jul 11 05:19:45 PM PDT 24
Finished Jul 11 05:20:03 PM PDT 24
Peak memory 218168 kb
Host smart-7da8960d-5227-4b26-9648-511d2ca7c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403834992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.403834992
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3965237131
Short name T551
Test name
Test status
Simulation time 827973899 ps
CPU time 6.25 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:19:56 PM PDT 24
Peak memory 216972 kb
Host smart-bc0a555a-cf30-428c-b9cc-4e65924b18f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965237131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3965237131
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2378894240
Short name T636
Test name
Test status
Simulation time 3973767342 ps
CPU time 50.62 seconds
Started Jul 11 05:19:27 PM PDT 24
Finished Jul 11 05:20:19 PM PDT 24
Peak memory 218884 kb
Host smart-28e9bec3-0e8b-4ada-b3f4-71e40db3483a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378894240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2378894240
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.177095719
Short name T98
Test name
Test status
Simulation time 5198288806 ps
CPU time 13.38 seconds
Started Jul 11 05:19:29 PM PDT 24
Finished Jul 11 05:19:44 PM PDT 24
Peak memory 218032 kb
Host smart-5e1a582d-58c7-4fbe-92cd-1556a07ff1a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177095719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.177095719
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1885255391
Short name T227
Test name
Test status
Simulation time 329783998 ps
CPU time 9.81 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:53 PM PDT 24
Peak memory 218172 kb
Host smart-287509ec-4fb0-4c86-8feb-c24d344719c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885255391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1885255391
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2055818363
Short name T668
Test name
Test status
Simulation time 3895287458 ps
CPU time 20 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:20:03 PM PDT 24
Peak memory 217784 kb
Host smart-257ffffb-6ef3-4b4b-b452-c156531161d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055818363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2055818363
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1902568810
Short name T338
Test name
Test status
Simulation time 217127750 ps
CPU time 6.56 seconds
Started Jul 11 05:19:45 PM PDT 24
Finished Jul 11 05:19:54 PM PDT 24
Peak memory 217652 kb
Host smart-887a7edd-9777-4b18-9194-afc293e4c1f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902568810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1902568810
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3081644891
Short name T805
Test name
Test status
Simulation time 42320964741 ps
CPU time 88.8 seconds
Started Jul 11 05:19:45 PM PDT 24
Finished Jul 11 05:21:16 PM PDT 24
Peak memory 273156 kb
Host smart-551f50b4-9794-4898-b110-6c05ab69eec1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081644891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3081644891
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2253450848
Short name T461
Test name
Test status
Simulation time 610309726 ps
CPU time 16.69 seconds
Started Jul 11 05:19:26 PM PDT 24
Finished Jul 11 05:19:44 PM PDT 24
Peak memory 250820 kb
Host smart-c1bfb99a-7b54-45cc-b5b1-9a8725c4bdc8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253450848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2253450848
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2047513716
Short name T181
Test name
Test status
Simulation time 111976931 ps
CPU time 5.06 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:19:56 PM PDT 24
Peak memory 218084 kb
Host smart-7ea9d045-d724-4940-b3f0-fb8f0531edbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047513716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2047513716
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2665231821
Short name T71
Test name
Test status
Simulation time 531584952 ps
CPU time 17.78 seconds
Started Jul 11 05:19:26 PM PDT 24
Finished Jul 11 05:19:44 PM PDT 24
Peak memory 214172 kb
Host smart-18d01310-fb07-4021-976e-fc426c851720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665231821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2665231821
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.667383721
Short name T191
Test name
Test status
Simulation time 291730471 ps
CPU time 13.39 seconds
Started Jul 11 05:19:28 PM PDT 24
Finished Jul 11 05:19:42 PM PDT 24
Peak memory 225896 kb
Host smart-f3c15ecc-7289-4427-9e32-cf6a22547bd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667383721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.667383721
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3572427247
Short name T535
Test name
Test status
Simulation time 2054401449 ps
CPU time 12.12 seconds
Started Jul 11 05:19:33 PM PDT 24
Finished Jul 11 05:19:47 PM PDT 24
Peak memory 225900 kb
Host smart-74aa152d-997e-486d-bbef-1c381c7db54e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572427247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3572427247
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.418218447
Short name T394
Test name
Test status
Simulation time 246867980 ps
CPU time 9.03 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:19:59 PM PDT 24
Peak memory 218108 kb
Host smart-3776ebc7-abad-4579-8245-c01a57aeee30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418218447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.418218447
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.864272052
Short name T606
Test name
Test status
Simulation time 169743156 ps
CPU time 7.75 seconds
Started Jul 11 05:19:30 PM PDT 24
Finished Jul 11 05:19:39 PM PDT 24
Peak memory 225956 kb
Host smart-55d9f289-a3f7-4370-a1dc-ed4897ab40c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864272052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.864272052
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.366966964
Short name T95
Test name
Test status
Simulation time 164008608 ps
CPU time 1.79 seconds
Started Jul 11 05:19:26 PM PDT 24
Finished Jul 11 05:19:29 PM PDT 24
Peak memory 214212 kb
Host smart-ccfc750c-cf69-495d-84ad-ed92c2324703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366966964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.366966964
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2075371266
Short name T79
Test name
Test status
Simulation time 1247250402 ps
CPU time 18.69 seconds
Started Jul 11 05:19:29 PM PDT 24
Finished Jul 11 05:19:49 PM PDT 24
Peak memory 250928 kb
Host smart-762cb684-c37a-4f15-8628-27503f0cba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075371266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2075371266
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2812398353
Short name T408
Test name
Test status
Simulation time 1342263541 ps
CPU time 7.63 seconds
Started Jul 11 05:19:37 PM PDT 24
Finished Jul 11 05:19:47 PM PDT 24
Peak memory 250956 kb
Host smart-2491f639-d553-42ec-b350-a1539be94714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812398353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2812398353
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3315196911
Short name T772
Test name
Test status
Simulation time 43773501825 ps
CPU time 456.77 seconds
Started Jul 11 05:19:28 PM PDT 24
Finished Jul 11 05:27:06 PM PDT 24
Peak memory 422012 kb
Host smart-e73d718e-af6a-4032-b074-53c20fa98074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315196911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3315196911
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.773831818
Short name T92
Test name
Test status
Simulation time 73349417951 ps
CPU time 780.18 seconds
Started Jul 11 05:19:29 PM PDT 24
Finished Jul 11 05:32:31 PM PDT 24
Peak memory 300232 kb
Host smart-881b377a-1c9c-4c9c-b677-91771f5bbdcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=773831818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.773831818
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1370693285
Short name T263
Test name
Test status
Simulation time 76316578 ps
CPU time 0.96 seconds
Started Jul 11 05:19:28 PM PDT 24
Finished Jul 11 05:19:30 PM PDT 24
Peak memory 211688 kb
Host smart-23d501dc-a48a-4006-9fb3-ca66baa34072
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370693285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1370693285
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3896270589
Short name T273
Test name
Test status
Simulation time 19132195 ps
CPU time 0.92 seconds
Started Jul 11 05:19:41 PM PDT 24
Finished Jul 11 05:19:45 PM PDT 24
Peak memory 208764 kb
Host smart-059aae89-00b9-4f7a-be57-7cb4484e1e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896270589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3896270589
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3998528149
Short name T280
Test name
Test status
Simulation time 13305804 ps
CPU time 0.98 seconds
Started Jul 11 05:19:39 PM PDT 24
Finished Jul 11 05:19:43 PM PDT 24
Peak memory 208940 kb
Host smart-9cfc99fd-07e0-4cf5-a1c1-eb8ec61ddcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998528149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3998528149
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.30758635
Short name T103
Test name
Test status
Simulation time 1238414485 ps
CPU time 15.74 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:20:09 PM PDT 24
Peak memory 218128 kb
Host smart-46c43c6f-ac35-4b8c-a4c2-a83cf355dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30758635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.30758635
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2492898857
Short name T555
Test name
Test status
Simulation time 4411521311 ps
CPU time 26.95 seconds
Started Jul 11 05:19:37 PM PDT 24
Finished Jul 11 05:20:06 PM PDT 24
Peak memory 217852 kb
Host smart-86877ee4-87d0-470f-8e61-110bcd802d4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492898857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2492898857
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.213797748
Short name T492
Test name
Test status
Simulation time 6308248526 ps
CPU time 51.07 seconds
Started Jul 11 05:19:37 PM PDT 24
Finished Jul 11 05:20:30 PM PDT 24
Peak memory 225924 kb
Host smart-013886d7-8a32-4c95-aaff-3c227f016fd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213797748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.213797748
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.371894328
Short name T856
Test name
Test status
Simulation time 378209019 ps
CPU time 4.58 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:48 PM PDT 24
Peak memory 217708 kb
Host smart-2df38cd7-e733-4ccc-9594-857ad01242bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371894328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.371894328
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2645654651
Short name T170
Test name
Test status
Simulation time 427260910 ps
CPU time 7.29 seconds
Started Jul 11 05:19:39 PM PDT 24
Finished Jul 11 05:19:49 PM PDT 24
Peak memory 218300 kb
Host smart-62da7962-4476-4ec7-8805-8041aa176853
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645654651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2645654651
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3700133694
Short name T24
Test name
Test status
Simulation time 2372499507 ps
CPU time 23.93 seconds
Started Jul 11 05:19:38 PM PDT 24
Finished Jul 11 05:20:04 PM PDT 24
Peak memory 217628 kb
Host smart-0170bcea-1d2c-4b3f-a034-fd73a4b11f44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700133694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3700133694
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2450658331
Short name T164
Test name
Test status
Simulation time 2597362430 ps
CPU time 16.28 seconds
Started Jul 11 05:19:43 PM PDT 24
Finished Jul 11 05:20:03 PM PDT 24
Peak memory 217688 kb
Host smart-b59d53e7-035c-4f5c-9922-7a07d88b284d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450658331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2450658331
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2988950134
Short name T421
Test name
Test status
Simulation time 7518087873 ps
CPU time 46.89 seconds
Started Jul 11 05:19:49 PM PDT 24
Finished Jul 11 05:20:39 PM PDT 24
Peak memory 267404 kb
Host smart-1e44266d-d05f-462a-9ae1-51d9fa202b17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988950134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2988950134
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1979483725
Short name T407
Test name
Test status
Simulation time 507711069 ps
CPU time 5.52 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:20:00 PM PDT 24
Peak memory 222792 kb
Host smart-1fcde9cd-eb2a-4b50-9925-6d9678c79204
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979483725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1979483725
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.544958762
Short name T258
Test name
Test status
Simulation time 25140797 ps
CPU time 1.62 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:19:57 PM PDT 24
Peak memory 218120 kb
Host smart-71ddc81a-9fd2-4297-a6fb-b804c37a0446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544958762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.544958762
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1990149214
Short name T824
Test name
Test status
Simulation time 243672831 ps
CPU time 16.26 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:20:07 PM PDT 24
Peak memory 217652 kb
Host smart-353023ae-dd7d-43bf-97cd-c5b71aa1f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990149214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1990149214
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1246883859
Short name T537
Test name
Test status
Simulation time 2111153089 ps
CPU time 10.33 seconds
Started Jul 11 05:19:39 PM PDT 24
Finished Jul 11 05:19:52 PM PDT 24
Peak memory 225980 kb
Host smart-c3615688-acc7-4fad-b40c-1b4bbcdb180e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246883859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1246883859
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3342502325
Short name T640
Test name
Test status
Simulation time 749774635 ps
CPU time 7.93 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:20:02 PM PDT 24
Peak memory 218136 kb
Host smart-4b842049-c3c2-4564-8bd2-11d0c01769cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342502325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
342502325
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.625027695
Short name T836
Test name
Test status
Simulation time 4563786748 ps
CPU time 12.62 seconds
Started Jul 11 05:19:36 PM PDT 24
Finished Jul 11 05:19:50 PM PDT 24
Peak memory 225960 kb
Host smart-46209c57-f040-4229-8b4b-ff66878fd54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625027695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.625027695
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1612815459
Short name T498
Test name
Test status
Simulation time 45301421 ps
CPU time 2.25 seconds
Started Jul 11 05:19:31 PM PDT 24
Finished Jul 11 05:19:35 PM PDT 24
Peak memory 214336 kb
Host smart-44e9f083-8bd1-416c-9325-00e2c681b2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612815459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1612815459
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3119814224
Short name T353
Test name
Test status
Simulation time 5220223285 ps
CPU time 26.33 seconds
Started Jul 11 05:19:42 PM PDT 24
Finished Jul 11 05:20:12 PM PDT 24
Peak memory 250972 kb
Host smart-0b18539f-df53-41c0-83fe-5b1c3520a18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119814224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3119814224
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2698844942
Short name T401
Test name
Test status
Simulation time 53171683 ps
CPU time 8.09 seconds
Started Jul 11 05:19:52 PM PDT 24
Finished Jul 11 05:20:05 PM PDT 24
Peak memory 250876 kb
Host smart-07e14af9-2b1a-4093-a2ac-c08d769946ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698844942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2698844942
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2601700458
Short name T53
Test name
Test status
Simulation time 17371024586 ps
CPU time 185.72 seconds
Started Jul 11 05:19:52 PM PDT 24
Finished Jul 11 05:23:03 PM PDT 24
Peak memory 275900 kb
Host smart-a335018e-dc7b-400e-ad59-f01b3a082108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601700458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2601700458
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3428877038
Short name T380
Test name
Test status
Simulation time 16301071 ps
CPU time 0.87 seconds
Started Jul 11 05:19:31 PM PDT 24
Finished Jul 11 05:19:32 PM PDT 24
Peak memory 211828 kb
Host smart-0d8f2fb3-0ec9-4188-b46b-9269601bad4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428877038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3428877038
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1112888654
Short name T838
Test name
Test status
Simulation time 12202403 ps
CPU time 0.93 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:02 PM PDT 24
Peak memory 208652 kb
Host smart-9b9cebbd-e125-424c-bb0b-fe00637f1e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112888654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1112888654
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.440183778
Short name T604
Test name
Test status
Simulation time 30520120 ps
CPU time 0.78 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:19:56 PM PDT 24
Peak memory 208844 kb
Host smart-cffa0200-5da7-48d5-b481-ed2d1a5093da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440183778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.440183778
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1239034823
Short name T601
Test name
Test status
Simulation time 251228323 ps
CPU time 9.41 seconds
Started Jul 11 05:19:38 PM PDT 24
Finished Jul 11 05:19:50 PM PDT 24
Peak memory 218196 kb
Host smart-791c9631-8b51-425a-a79a-fb3a70a51214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239034823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1239034823
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3533682664
Short name T670
Test name
Test status
Simulation time 3107068442 ps
CPU time 9.14 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:52 PM PDT 24
Peak memory 217728 kb
Host smart-9a40af96-20b0-449a-b169-18bf88d724d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533682664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3533682664
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.172903884
Short name T81
Test name
Test status
Simulation time 17606572523 ps
CPU time 26.63 seconds
Started Jul 11 05:19:37 PM PDT 24
Finished Jul 11 05:20:06 PM PDT 24
Peak memory 218196 kb
Host smart-86399cb2-90a3-4e37-ad38-d95428cfb921
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172903884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.172903884
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1702835698
Short name T197
Test name
Test status
Simulation time 776768849 ps
CPU time 4.33 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:19:54 PM PDT 24
Peak memory 217440 kb
Host smart-ce9013b0-2464-4fa7-b8c7-636f2ee2b874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702835698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
702835698
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.65267903
Short name T160
Test name
Test status
Simulation time 1127241800 ps
CPU time 7.81 seconds
Started Jul 11 05:19:41 PM PDT 24
Finished Jul 11 05:19:52 PM PDT 24
Peak memory 218028 kb
Host smart-4bd09961-d0d4-450d-9c5e-e7bb0a955a54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65267903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_p
rog_failure.65267903
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2408513646
Short name T706
Test name
Test status
Simulation time 855456071 ps
CPU time 15.18 seconds
Started Jul 11 05:19:56 PM PDT 24
Finished Jul 11 05:20:18 PM PDT 24
Peak memory 217548 kb
Host smart-fccfd137-2ffd-4fda-b108-43f46bf567b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408513646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2408513646
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1351912123
Short name T696
Test name
Test status
Simulation time 365427366 ps
CPU time 8.11 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:20:03 PM PDT 24
Peak memory 217560 kb
Host smart-061040ce-ed27-4a21-9579-c6ffe2d79e97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351912123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1351912123
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3946688123
Short name T767
Test name
Test status
Simulation time 2108973153 ps
CPU time 77.82 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:21:08 PM PDT 24
Peak memory 278776 kb
Host smart-a4db73a3-41fc-48c6-8f52-c1c8dd196649
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946688123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3946688123
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1972227614
Short name T2
Test name
Test status
Simulation time 613898041 ps
CPU time 14.31 seconds
Started Jul 11 05:19:36 PM PDT 24
Finished Jul 11 05:19:52 PM PDT 24
Peak memory 250336 kb
Host smart-9c591904-6c3c-465e-93c9-0c6710d4286c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972227614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1972227614
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.98978997
Short name T415
Test name
Test status
Simulation time 77095089 ps
CPU time 2.96 seconds
Started Jul 11 05:19:39 PM PDT 24
Finished Jul 11 05:19:44 PM PDT 24
Peak memory 218164 kb
Host smart-b7aed636-7577-4990-a797-330e0f4bdfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98978997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.98978997
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.4024360624
Short name T497
Test name
Test status
Simulation time 464175204 ps
CPU time 13.19 seconds
Started Jul 11 05:24:45 PM PDT 24
Finished Jul 11 05:25:01 PM PDT 24
Peak memory 214032 kb
Host smart-f6319a5c-a1f8-4039-9d88-dfaabf63ee4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024360624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.4024360624
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1015476794
Short name T399
Test name
Test status
Simulation time 920228646 ps
CPU time 8.28 seconds
Started Jul 11 05:19:53 PM PDT 24
Finished Jul 11 05:20:07 PM PDT 24
Peak memory 225960 kb
Host smart-7f6d8783-c8ce-4d03-accb-a93e7af1712c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015476794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1015476794
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1593153147
Short name T372
Test name
Test status
Simulation time 1152963062 ps
CPU time 8.31 seconds
Started Jul 11 05:19:54 PM PDT 24
Finished Jul 11 05:20:09 PM PDT 24
Peak memory 225972 kb
Host smart-9cad0206-d55c-4c90-9769-c8807e169845
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593153147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1593153147
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1349147437
Short name T443
Test name
Test status
Simulation time 453621392 ps
CPU time 9.22 seconds
Started Jul 11 05:19:51 PM PDT 24
Finished Jul 11 05:20:04 PM PDT 24
Peak memory 218180 kb
Host smart-a3cc50d4-cc22-45e4-8059-66541c3fac43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349147437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
349147437
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.406686774
Short name T339
Test name
Test status
Simulation time 367583080 ps
CPU time 12.41 seconds
Started Jul 11 05:19:40 PM PDT 24
Finished Jul 11 05:19:56 PM PDT 24
Peak memory 218172 kb
Host smart-a867c0ec-6ebc-4ce8-87d3-a26d15acd66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406686774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.406686774
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3841463413
Short name T463
Test name
Test status
Simulation time 518773019 ps
CPU time 2.67 seconds
Started Jul 11 05:19:48 PM PDT 24
Finished Jul 11 05:19:53 PM PDT 24
Peak memory 214408 kb
Host smart-204aa887-b998-4aaa-b2bc-50cf515fdb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841463413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3841463413
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1301278754
Short name T549
Test name
Test status
Simulation time 299585240 ps
CPU time 20.69 seconds
Started Jul 11 05:19:34 PM PDT 24
Finished Jul 11 05:19:57 PM PDT 24
Peak memory 250920 kb
Host smart-48566489-26ef-4b8c-af1e-5af9194e5ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301278754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1301278754
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4053797463
Short name T837
Test name
Test status
Simulation time 153913267 ps
CPU time 3.2 seconds
Started Jul 11 05:19:49 PM PDT 24
Finished Jul 11 05:19:54 PM PDT 24
Peak memory 226228 kb
Host smart-8972082b-2055-4b73-8b8c-7e07c65a49ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053797463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4053797463
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4025529770
Short name T746
Test name
Test status
Simulation time 544199997 ps
CPU time 31.18 seconds
Started Jul 11 05:19:52 PM PDT 24
Finished Jul 11 05:20:30 PM PDT 24
Peak memory 250796 kb
Host smart-b374a338-a4f0-485f-ba9f-a8b3f7bf144c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025529770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4025529770
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4236421908
Short name T811
Test name
Test status
Simulation time 159276473 ps
CPU time 0.95 seconds
Started Jul 11 05:19:39 PM PDT 24
Finished Jul 11 05:19:42 PM PDT 24
Peak memory 211756 kb
Host smart-2cd42b4f-cc16-4aa1-959e-5ea65cbd1fb0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236421908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.4236421908
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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