Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102124274

1

T1

155438

T2

17475

T3

1357

auto[1]

1417203

1

T1

3430

T4

5688

T8

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102118073

1

T1

155536

T2

17475

T3

1357

auto[1]

1423404

1

T1

3332

T4

4317

T8

1287

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7533484	1			T1	21209		T2	4888		T3	119
auto[IdleSt]	20722177	1			T1	9132		T2	2152		T3	70
auto[ClkMuxSt]	35669	1			T2	52		T3	1		T4	31
auto[CntIncrSt]	35366	1			T2	52		T3	1		T4	31
auto[CntProgSt]	1758776	1			T2	414		T3	70		T4	62
auto[TransCheckSt]	27550	1			T2	52		T3	1		T4	16
auto[TokenHashSt]	40467894	1			T2	2071		T3	211		T4	176
auto[FlashRmaSt]	34141	1			T4	37		T9	34		T12	35
auto[TokenCheck0St]	12608	1			T4	16		T9	26		T12	17
auto[TokenCheck1St]	9349	1			T4	16		T9	26		T12	7
auto[TransProgSt]	455772	1			T4	32		T9	175		T12	65
auto[PostTransSt]	12420294	1			T2	7794		T3	884		T4	75529
auto[ScrapSt]	255617	1			T9	3		T11	1114		T34	1522
auto[EscalateSt]	7039775	1			T1	30225		T4	107350		T8	2676
auto[InvalidSt]	12731011	1			T1	98293		T4	274909		T13	167280

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1994	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12731011	1			T1	98293		T4	274909		T13	167280
EscalateSt	7039775	1			T1	30225		T4	107350		T8	2676
ScrapSt	255617	1			T9	3		T11	1114		T34	1522
PostTransSt	12420294	1			T2	7794		T3	884		T4	75529
TransProgSt	455772	1			T4	32		T9	175		T12	65
TokenCheck1St	9349	1			T4	16		T9	26		T12	7
TokenCheck0St	12608	1			T4	16		T9	26		T12	17
FlashRmaSt	34141	1			T4	37		T9	34		T12	35
TokenHashSt	40467894	1			T2	2071		T3	211		T4	176
TransCheckSt	27550	1			T2	52		T3	1		T4	16
CntProgSt	1758776	1			T2	414		T3	70		T4	62
CntIncrSt	35366	1			T2	52		T3	1		T4	31
ClkMuxSt	35669	1			T2	52		T3	1		T4	31
IdleSt	20722177	1			T1	9132		T2	2152		T3	70
ResetSt	7533484	1			T1	21209		T2	4888		T3	119
arcs[ResetSt=>IdleSt]	54669	1			T1	85		T2	53		T3	1
arcs[IdleSt=>ScrapSt]	287	1			T9	1		T11	1		T34	1
arcs[IdleSt=>ClkMuxSt]	35430	1			T2	52		T3	1		T4	31
arcs[ClkMuxSt=>CntIncrSt]	35366	1			T2	52		T3	1		T4	31
arcs[CntIncrSt=>PostTransSt]	1876	1			T12	5		T13	12		T14	18
arcs[CntIncrSt=>CntProgSt]	33428	1			T2	52		T3	1		T4	31
arcs[CntProgSt=>PostTransSt]	4756	1			T4	15		T8	19		T12	5
arcs[CntProgSt=>TransCheckSt]	27550	1			T2	52		T3	1		T4	16
arcs[TransCheckSt=>PostTransSt]	3830	1			T12	7		T13	15		T14	10
arcs[TransCheckSt=>TokenHashSt]	23627	1			T2	52		T3	1		T4	16
arcs[TokenHashSt=>PostTransSt]	10293	1			T2	52		T3	1		T12	17
arcs[TokenHashSt=>FlashRmaSt]	12706	1			T4	16		T9	31		T12	17
arcs[FlashRmaSt=>TokenCheck0St]	12608	1			T4	16		T9	26		T12	17
arcs[TokenCheck0St=>PostTransSt]	3240	1			T12	10		T13	15		T14	8
arcs[TokenCheck0St=>TokenCheck1St]	9349	1			T4	16		T9	26		T12	7
arcs[TokenCheck1St=>PostTransSt]	642	1			T12	1		T14	2		T17	1
arcs[TransProgSt=>PostTransSt]	7848	1			T4	16		T9	2		T12	6
arcs[IdleSt=>EscalateSt]	198	1			T20	6		T46	2		T48	6
arcs[ClkMuxSt=>EscalateSt]	64	1			T9	2		T20	1		T46	2
arcs[CntIncrSt=>EscalateSt]	62	1			T9	2		T46	1		T47	1
arcs[CntProgSt=>EscalateSt]	1122	1			T9	33		T20	15		T46	8
arcs[TransCheckSt=>EscalateSt]	93	1			T20	1		T46	5		T47	2
arcs[TokenHashSt=>EscalateSt]	628	1			T9	11		T20	6		T17	1
arcs[FlashRmaSt=>EscalateSt]	98	1			T9	5		T20	2		T46	2
arcs[TokenCheck0St=>EscalateSt]	19	1			T20	1		T46	1		T51	2
arcs[TokenCheck1St=>EscalateSt]	136	1			T9	1		T20	3		T47	4
arcs[TransProgSt=>EscalateSt]	723	1			T9	23		T20	13		T46	8
arcs[PostTransSt=>EscalateSt]	4971	1			T4	15		T8	19		T9	2
arcs[InvalidSt=>EscalateSt]	14523	1			T1	69		T4	87		T13	69

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7533303	1			T1	21209		T2	4888		T3	119
auto[0]	auto[IdleSt]	20722037	1			T1	9132		T2	2152		T3	70
auto[0]	auto[ClkMuxSt]	35634	1			T2	52		T3	1		T4	31
auto[0]	auto[CntIncrSt]	35331	1			T2	52		T3	1		T4	31
auto[0]	auto[CntProgSt]	1758026	1			T2	414		T3	70		T4	62
auto[0]	auto[TransCheckSt]	27488	1			T2	52		T3	1		T4	16
auto[0]	auto[TokenHashSt]	40467472	1			T2	2071		T3	211		T4	176
auto[0]	auto[FlashRmaSt]	34077	1			T4	37		T9	32		T12	35
auto[0]	auto[TokenCheck0St]	12592	1			T4	16		T9	26		T12	17
auto[0]	auto[TokenCheck1St]	9260	1			T4	16		T9	26		T12	7
auto[0]	auto[TransProgSt]	455293	1			T4	32		T9	161		T12	65
auto[0]	auto[PostTransSt]	12417744	1			T2	7794		T3	884		T4	75521
auto[0]	auto[ScrapSt]	255577	1			T9	2		T11	1114		T34	1522
auto[0]	auto[EscalateSt]	5634656	1			T1	26830		T4	101720		T8	2088
auto[0]	auto[InvalidSt]	12723790	1			T1	98258		T4	274859		T13	167241
auto[1]	auto[ResetSt]	181	1			T9	7		T20	5		T47	6
auto[1]	auto[IdleSt]	140	1			T20	3		T46	1		T48	6
auto[1]	auto[ClkMuxSt]	35	1			T9	1		T20	1		T46	2
auto[1]	auto[CntIncrSt]	35	1			T9	2		T46	1		T47	1
auto[1]	auto[CntProgSt]	750	1			T9	20		T20	10		T46	3
auto[1]	auto[TransCheckSt]	62	1			T20	1		T46	2		T47	2
auto[1]	auto[TokenHashSt]	422	1			T9	8		T20	4		T17	1
auto[1]	auto[FlashRmaSt]	64	1			T9	2		T20	1		T46	1
auto[1]	auto[TokenCheck0St]	16	1			T20	1		T46	1		T51	2
auto[1]	auto[TokenCheck1St]	89	1			T20	3		T47	3		T119	4
auto[1]	auto[TransProgSt]	479	1			T9	14		T20	10		T46	5
auto[1]	auto[PostTransSt]	2550	1			T4	8		T8	6		T9	1
auto[1]	auto[ScrapSt]	40	1			T9	1		T47	1		T119	1
auto[1]	auto[EscalateSt]	1405119	1			T1	3395		T4	5630		T8	588
auto[1]	auto[InvalidSt]	7221	1			T1	35		T4	50		T13	39

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7533291	1			T1	21209		T2	4888		T3	119
auto[0]	auto[IdleSt]	20722041	1			T1	9132		T2	2152		T3	70
auto[0]	auto[ClkMuxSt]	35620	1			T2	52		T3	1		T4	31
auto[0]	auto[CntIncrSt]	35327	1			T2	52		T3	1		T4	31
auto[0]	auto[CntProgSt]	1758036	1			T2	414		T3	70		T4	62
auto[0]	auto[TransCheckSt]	27484	1			T2	52		T3	1		T4	16
auto[0]	auto[TokenHashSt]	40467470	1			T2	2071		T3	211		T4	176
auto[0]	auto[FlashRmaSt]	34082	1			T4	37		T9	30		T12	35
auto[0]	auto[TokenCheck0St]	12596	1			T4	16		T9	26		T12	17
auto[0]	auto[TokenCheck1St]	9266	1			T4	16		T9	25		T12	7
auto[0]	auto[TransProgSt]	455285	1			T4	32		T9	158		T12	65
auto[0]	auto[PostTransSt]	12417802	1			T2	7794		T3	884		T4	75522
auto[0]	auto[ScrapSt]	255576	1			T9	2		T11	1114		T34	1522
auto[0]	auto[EscalateSt]	5628494	1			T1	26927		T4	103077		T8	1402
auto[0]	auto[InvalidSt]	12723709	1			T1	98259		T4	274872		T13	167250
auto[1]	auto[ResetSt]	193	1			T9	8		T20	4		T46	2
auto[1]	auto[IdleSt]	136	1			T20	5		T46	1		T48	4
auto[1]	auto[ClkMuxSt]	49	1			T9	2		T46	2		T47	2
auto[1]	auto[CntIncrSt]	39	1			T9	1		T51	1		T229	1
auto[1]	auto[CntProgSt]	740	1			T9	26		T20	10		T46	7
auto[1]	auto[TransCheckSt]	66	1			T20	1		T46	5		T47	1
auto[1]	auto[TokenHashSt]	424	1			T9	7		T20	5		T46	5
auto[1]	auto[FlashRmaSt]	59	1			T9	4		T20	2		T46	2
auto[1]	auto[TokenCheck0St]	12	1			T46	1		T51	2		T230	1
auto[1]	auto[TokenCheck1St]	83	1			T9	1		T20	2		T47	3
auto[1]	auto[TransProgSt]	487	1			T9	17		T20	9		T46	5
auto[1]	auto[PostTransSt]	2492	1			T4	7		T8	13		T9	2
auto[1]	auto[ScrapSt]	41	1			T9	1		T46	1		T119	1
auto[1]	auto[EscalateSt]	1411281	1			T1	3298		T4	4273		T8	1274
auto[1]	auto[InvalidSt]	7302	1			T1	34		T4	37		T13	30