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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.93 97.92 95.93 93.38 97.62 98.52 99.00 96.11


Total test records in report: 994
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T823 /workspace/coverage/default/12.lc_ctrl_state_post_trans.3490349591 Jul 14 06:21:34 PM PDT 24 Jul 14 06:21:44 PM PDT 24 57820892 ps
T824 /workspace/coverage/default/42.lc_ctrl_security_escalation.1670819200 Jul 14 06:23:09 PM PDT 24 Jul 14 06:23:28 PM PDT 24 10913148421 ps
T825 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3591740668 Jul 14 06:20:51 PM PDT 24 Jul 14 06:21:03 PM PDT 24 1421781691 ps
T826 /workspace/coverage/default/29.lc_ctrl_jtag_access.7193114 Jul 14 06:22:30 PM PDT 24 Jul 14 06:22:39 PM PDT 24 1312224714 ps
T827 /workspace/coverage/default/12.lc_ctrl_prog_failure.561863518 Jul 14 06:21:34 PM PDT 24 Jul 14 06:21:38 PM PDT 24 142590069 ps
T828 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1021560046 Jul 14 06:21:34 PM PDT 24 Jul 14 06:21:44 PM PDT 24 390116037 ps
T829 /workspace/coverage/default/48.lc_ctrl_state_failure.2015052204 Jul 14 06:23:20 PM PDT 24 Jul 14 06:23:44 PM PDT 24 252715861 ps
T176 /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4260321424 Jul 14 06:21:13 PM PDT 24 Jul 14 06:25:56 PM PDT 24 47347295680 ps
T830 /workspace/coverage/default/40.lc_ctrl_state_post_trans.473188681 Jul 14 06:23:02 PM PDT 24 Jul 14 06:23:11 PM PDT 24 84850724 ps
T831 /workspace/coverage/default/10.lc_ctrl_state_failure.4219793171 Jul 14 06:21:21 PM PDT 24 Jul 14 06:21:42 PM PDT 24 195298842 ps
T832 /workspace/coverage/default/15.lc_ctrl_errors.3510797571 Jul 14 06:21:40 PM PDT 24 Jul 14 06:21:51 PM PDT 24 284728374 ps
T833 /workspace/coverage/default/22.lc_ctrl_prog_failure.67440344 Jul 14 06:22:09 PM PDT 24 Jul 14 06:22:12 PM PDT 24 161343269 ps
T177 /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3261648123 Jul 14 06:21:44 PM PDT 24 Jul 14 06:34:38 PM PDT 24 150550544227 ps
T186 /workspace/coverage/default/20.lc_ctrl_prog_failure.1822137080 Jul 14 06:21:58 PM PDT 24 Jul 14 06:22:02 PM PDT 24 126484792 ps
T187 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2994022760 Jul 14 06:22:11 PM PDT 24 Jul 14 06:22:14 PM PDT 24 51455808 ps
T188 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1761123874 Jul 14 06:23:21 PM PDT 24 Jul 14 06:23:32 PM PDT 24 660421538 ps
T189 /workspace/coverage/default/22.lc_ctrl_jtag_access.82994198 Jul 14 06:22:11 PM PDT 24 Jul 14 06:22:16 PM PDT 24 115573887 ps
T190 /workspace/coverage/default/17.lc_ctrl_smoke.13313999 Jul 14 06:21:51 PM PDT 24 Jul 14 06:21:54 PM PDT 24 19655085 ps
T191 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3709162871 Jul 14 06:21:22 PM PDT 24 Jul 14 06:21:34 PM PDT 24 350843886 ps
T192 /workspace/coverage/default/44.lc_ctrl_alert_test.4239590021 Jul 14 06:23:13 PM PDT 24 Jul 14 06:23:15 PM PDT 24 80023138 ps
T193 /workspace/coverage/default/8.lc_ctrl_alert_test.3935966217 Jul 14 06:21:15 PM PDT 24 Jul 14 06:21:16 PM PDT 24 29198385 ps
T194 /workspace/coverage/default/36.lc_ctrl_smoke.3263109129 Jul 14 06:22:49 PM PDT 24 Jul 14 06:22:53 PM PDT 24 68016580 ps
T834 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3679132566 Jul 14 06:21:04 PM PDT 24 Jul 14 06:21:05 PM PDT 24 35275445 ps
T835 /workspace/coverage/default/16.lc_ctrl_state_failure.1405899863 Jul 14 06:21:55 PM PDT 24 Jul 14 06:22:18 PM PDT 24 167241361 ps
T836 /workspace/coverage/default/45.lc_ctrl_sec_mubi.1915796429 Jul 14 06:23:16 PM PDT 24 Jul 14 06:23:28 PM PDT 24 223060305 ps
T837 /workspace/coverage/default/28.lc_ctrl_smoke.2437583907 Jul 14 06:22:25 PM PDT 24 Jul 14 06:22:27 PM PDT 24 115567585 ps
T838 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3652811750 Jul 14 06:20:33 PM PDT 24 Jul 14 06:20:54 PM PDT 24 390576478 ps
T839 /workspace/coverage/default/17.lc_ctrl_stress_all.465385545 Jul 14 06:21:55 PM PDT 24 Jul 14 06:22:13 PM PDT 24 673414339 ps
T840 /workspace/coverage/default/41.lc_ctrl_state_failure.2119113178 Jul 14 06:23:01 PM PDT 24 Jul 14 06:23:25 PM PDT 24 672957245 ps
T841 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3497174308 Jul 14 06:21:35 PM PDT 24 Jul 14 06:21:51 PM PDT 24 368913482 ps
T842 /workspace/coverage/default/1.lc_ctrl_jtag_errors.3210740834 Jul 14 06:20:33 PM PDT 24 Jul 14 06:22:07 PM PDT 24 13875351652 ps
T843 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3778593817 Jul 14 06:21:23 PM PDT 24 Jul 14 06:21:35 PM PDT 24 737309495 ps
T844 /workspace/coverage/default/6.lc_ctrl_state_post_trans.2066818644 Jul 14 06:21:01 PM PDT 24 Jul 14 06:21:10 PM PDT 24 51227509 ps
T845 /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3534671704 Jul 14 06:22:58 PM PDT 24 Jul 14 06:36:06 PM PDT 24 25043923474 ps
T846 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.602628759 Jul 14 06:20:52 PM PDT 24 Jul 14 06:21:44 PM PDT 24 8489838456 ps
T847 /workspace/coverage/default/11.lc_ctrl_jtag_errors.1009652308 Jul 14 06:21:25 PM PDT 24 Jul 14 06:22:30 PM PDT 24 5207085465 ps
T848 /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1017107462 Jul 14 06:22:54 PM PDT 24 Jul 14 06:28:44 PM PDT 24 18446157146 ps
T849 /workspace/coverage/default/35.lc_ctrl_errors.3802692767 Jul 14 06:22:47 PM PDT 24 Jul 14 06:23:03 PM PDT 24 709784823 ps
T850 /workspace/coverage/default/35.lc_ctrl_security_escalation.1852349668 Jul 14 06:22:44 PM PDT 24 Jul 14 06:22:57 PM PDT 24 608718911 ps
T851 /workspace/coverage/default/48.lc_ctrl_stress_all.2648678719 Jul 14 06:23:24 PM PDT 24 Jul 14 06:23:49 PM PDT 24 5522714454 ps
T852 /workspace/coverage/default/21.lc_ctrl_stress_all.2469577469 Jul 14 06:22:09 PM PDT 24 Jul 14 06:24:36 PM PDT 24 18219966235 ps
T42 /workspace/coverage/default/39.lc_ctrl_errors.2186234998 Jul 14 06:22:54 PM PDT 24 Jul 14 06:23:05 PM PDT 24 290158674 ps
T853 /workspace/coverage/default/32.lc_ctrl_sec_mubi.761827506 Jul 14 06:22:38 PM PDT 24 Jul 14 06:22:47 PM PDT 24 777807931 ps
T854 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3522724770 Jul 14 06:21:23 PM PDT 24 Jul 14 06:21:40 PM PDT 24 2780832151 ps
T855 /workspace/coverage/default/7.lc_ctrl_state_post_trans.1445039685 Jul 14 06:20:59 PM PDT 24 Jul 14 06:21:07 PM PDT 24 136994472 ps
T856 /workspace/coverage/default/15.lc_ctrl_state_failure.691976389 Jul 14 06:21:48 PM PDT 24 Jul 14 06:22:14 PM PDT 24 1936005653 ps
T857 /workspace/coverage/default/39.lc_ctrl_state_post_trans.1902841765 Jul 14 06:22:57 PM PDT 24 Jul 14 06:23:06 PM PDT 24 225538710 ps
T858 /workspace/coverage/default/33.lc_ctrl_sec_mubi.502922173 Jul 14 06:22:47 PM PDT 24 Jul 14 06:23:00 PM PDT 24 976980310 ps
T859 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1128267106 Jul 14 06:21:02 PM PDT 24 Jul 14 06:21:47 PM PDT 24 1582850025 ps
T860 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1646152759 Jul 14 06:21:01 PM PDT 24 Jul 14 06:21:11 PM PDT 24 1161521456 ps
T861 /workspace/coverage/default/20.lc_ctrl_errors.1173653742 Jul 14 06:21:58 PM PDT 24 Jul 14 06:22:12 PM PDT 24 1322588678 ps
T862 /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.624093639 Jul 14 06:20:51 PM PDT 24 Jul 14 06:21:03 PM PDT 24 2797727166 ps
T863 /workspace/coverage/default/40.lc_ctrl_smoke.48078153 Jul 14 06:23:01 PM PDT 24 Jul 14 06:23:04 PM PDT 24 829407724 ps
T864 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.315156203 Jul 14 06:23:25 PM PDT 24 Jul 14 06:23:40 PM PDT 24 586632284 ps
T865 /workspace/coverage/default/23.lc_ctrl_state_post_trans.1182551940 Jul 14 06:22:15 PM PDT 24 Jul 14 06:22:24 PM PDT 24 1030251274 ps
T866 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.171655051 Jul 14 06:21:34 PM PDT 24 Jul 14 06:21:44 PM PDT 24 468526135 ps
T168 /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3299755645 Jul 14 06:21:21 PM PDT 24 Jul 14 07:35:44 PM PDT 24 33500832251 ps
T867 /workspace/coverage/default/0.lc_ctrl_smoke.648796767 Jul 14 06:20:24 PM PDT 24 Jul 14 06:20:27 PM PDT 24 74643904 ps
T868 /workspace/coverage/default/37.lc_ctrl_state_failure.2232111839 Jul 14 06:22:49 PM PDT 24 Jul 14 06:23:19 PM PDT 24 2801636708 ps
T135 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3583803035 Jul 14 05:50:09 PM PDT 24 Jul 14 05:50:20 PM PDT 24 1113337971 ps
T124 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3929551093 Jul 14 05:49:53 PM PDT 24 Jul 14 05:49:56 PM PDT 24 365864909 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1714603466 Jul 14 05:50:07 PM PDT 24 Jul 14 05:50:09 PM PDT 24 18369960 ps
T153 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.822931428 Jul 14 05:50:35 PM PDT 24 Jul 14 05:50:37 PM PDT 24 56860895 ps
T156 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3485100709 Jul 14 05:50:07 PM PDT 24 Jul 14 05:50:11 PM PDT 24 440735465 ps
T131 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3100465916 Jul 14 05:49:33 PM PDT 24 Jul 14 05:49:37 PM PDT 24 308379131 ps
T869 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2710685464 Jul 14 05:50:13 PM PDT 24 Jul 14 05:50:14 PM PDT 24 40220394 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1151076624 Jul 14 05:49:20 PM PDT 24 Jul 14 05:49:26 PM PDT 24 897371829 ps
T154 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3684049534 Jul 14 05:50:22 PM PDT 24 Jul 14 05:50:24 PM PDT 24 46204297 ps
T871 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.362960805 Jul 14 05:49:53 PM PDT 24 Jul 14 05:50:00 PM PDT 24 1296364184 ps
T127 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3044587387 Jul 14 05:50:07 PM PDT 24 Jul 14 05:50:09 PM PDT 24 89112305 ps
T132 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.646171692 Jul 14 05:50:32 PM PDT 24 Jul 14 05:50:34 PM PDT 24 78405210 ps
T125 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.33712765 Jul 14 05:49:47 PM PDT 24 Jul 14 05:49:49 PM PDT 24 57395492 ps
T126 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2598772891 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:36 PM PDT 24 120053997 ps
T872 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1061956772 Jul 14 05:49:53 PM PDT 24 Jul 14 05:50:12 PM PDT 24 701225106 ps
T169 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3827740830 Jul 14 05:50:16 PM PDT 24 Jul 14 05:50:17 PM PDT 24 26400133 ps
T128 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.962528729 Jul 14 05:49:53 PM PDT 24 Jul 14 05:49:55 PM PDT 24 59492966 ps
T155 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1135788348 Jul 14 05:49:32 PM PDT 24 Jul 14 05:49:42 PM PDT 24 371408382 ps
T215 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4002817774 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:35 PM PDT 24 17133769 ps
T142 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3447806214 Jul 14 05:49:20 PM PDT 24 Jul 14 05:49:23 PM PDT 24 106234338 ps
T152 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.75969128 Jul 14 05:50:21 PM PDT 24 Jul 14 05:50:23 PM PDT 24 42416365 ps
T216 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4156336071 Jul 14 05:49:52 PM PDT 24 Jul 14 05:49:54 PM PDT 24 138513229 ps
T129 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.793136140 Jul 14 05:50:31 PM PDT 24 Jul 14 05:50:35 PM PDT 24 448752300 ps
T130 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1078516473 Jul 14 05:49:25 PM PDT 24 Jul 14 05:49:28 PM PDT 24 134874510 ps
T873 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.374194571 Jul 14 05:49:51 PM PDT 24 Jul 14 05:49:53 PM PDT 24 47764943 ps
T874 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2005802117 Jul 14 05:49:28 PM PDT 24 Jul 14 05:49:30 PM PDT 24 135724661 ps
T185 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2365293066 Jul 14 05:50:21 PM PDT 24 Jul 14 05:50:22 PM PDT 24 30289270 ps
T145 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1703888260 Jul 14 05:49:54 PM PDT 24 Jul 14 05:49:57 PM PDT 24 103678622 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2023974388 Jul 14 05:49:21 PM PDT 24 Jul 14 05:49:22 PM PDT 24 17839478 ps
T876 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2876997687 Jul 14 05:50:09 PM PDT 24 Jul 14 05:50:13 PM PDT 24 1478921102 ps
T877 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3710930630 Jul 14 05:49:15 PM PDT 24 Jul 14 05:49:18 PM PDT 24 175240989 ps
T146 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1643325003 Jul 14 05:50:05 PM PDT 24 Jul 14 05:50:08 PM PDT 24 76817776 ps
T878 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3209060339 Jul 14 05:49:30 PM PDT 24 Jul 14 05:49:31 PM PDT 24 196351592 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3894872882 Jul 14 05:49:47 PM PDT 24 Jul 14 05:49:49 PM PDT 24 163391244 ps
T140 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3568057190 Jul 14 05:50:15 PM PDT 24 Jul 14 05:50:18 PM PDT 24 255061174 ps
T217 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3283503340 Jul 14 05:49:36 PM PDT 24 Jul 14 05:49:39 PM PDT 24 36869103 ps
T218 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3142704053 Jul 14 05:49:52 PM PDT 24 Jul 14 05:49:54 PM PDT 24 40957411 ps
T137 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.602534041 Jul 14 05:49:28 PM PDT 24 Jul 14 05:49:33 PM PDT 24 118470657 ps
T880 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2512194625 Jul 14 05:49:52 PM PDT 24 Jul 14 05:49:53 PM PDT 24 30837409 ps
T219 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2359975858 Jul 14 05:49:29 PM PDT 24 Jul 14 05:49:31 PM PDT 24 25082429 ps
T199 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3950110552 Jul 14 05:50:21 PM PDT 24 Jul 14 05:50:23 PM PDT 24 15144880 ps
T220 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2410481547 Jul 14 05:50:08 PM PDT 24 Jul 14 05:50:09 PM PDT 24 47397275 ps
T881 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3360932688 Jul 14 05:50:32 PM PDT 24 Jul 14 05:50:35 PM PDT 24 162990662 ps
T200 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2035360703 Jul 14 05:50:31 PM PDT 24 Jul 14 05:50:32 PM PDT 24 71409405 ps
T882 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.379179785 Jul 14 05:50:14 PM PDT 24 Jul 14 05:50:17 PM PDT 24 104261555 ps
T221 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1209737598 Jul 14 05:50:23 PM PDT 24 Jul 14 05:50:25 PM PDT 24 36730842 ps
T201 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1898784168 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:35 PM PDT 24 39435232 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.963661517 Jul 14 05:49:47 PM PDT 24 Jul 14 05:49:56 PM PDT 24 4498537533 ps
T222 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.389398471 Jul 14 05:49:20 PM PDT 24 Jul 14 05:49:21 PM PDT 24 56577199 ps
T884 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2019804703 Jul 14 05:49:41 PM PDT 24 Jul 14 05:49:43 PM PDT 24 165413117 ps
T885 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3527853067 Jul 14 05:49:20 PM PDT 24 Jul 14 05:49:23 PM PDT 24 497191803 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2605670871 Jul 14 05:49:54 PM PDT 24 Jul 14 05:49:57 PM PDT 24 104151209 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3373881787 Jul 14 05:49:49 PM PDT 24 Jul 14 05:49:51 PM PDT 24 13498746 ps
T888 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2121856756 Jul 14 05:50:23 PM PDT 24 Jul 14 05:50:25 PM PDT 24 18931545 ps
T133 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1977885939 Jul 14 05:50:34 PM PDT 24 Jul 14 05:50:40 PM PDT 24 224991215 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2241693918 Jul 14 05:49:40 PM PDT 24 Jul 14 05:49:41 PM PDT 24 92746501 ps
T141 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.395862037 Jul 14 05:49:48 PM PDT 24 Jul 14 05:49:52 PM PDT 24 145733717 ps
T890 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.162300054 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:35 PM PDT 24 12316083 ps
T891 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3067971675 Jul 14 05:49:49 PM PDT 24 Jul 14 05:49:52 PM PDT 24 154793040 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2473970467 Jul 14 05:49:41 PM PDT 24 Jul 14 05:49:44 PM PDT 24 85628051 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4231494955 Jul 14 05:49:19 PM PDT 24 Jul 14 05:49:21 PM PDT 24 38194471 ps
T202 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3563635995 Jul 14 05:50:24 PM PDT 24 Jul 14 05:50:25 PM PDT 24 24771830 ps
T138 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3952035683 Jul 14 05:50:22 PM PDT 24 Jul 14 05:50:25 PM PDT 24 164315701 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2094004304 Jul 14 05:50:14 PM PDT 24 Jul 14 05:50:16 PM PDT 24 17595971 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1886529265 Jul 14 05:49:47 PM PDT 24 Jul 14 05:49:49 PM PDT 24 210126515 ps
T896 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4023375838 Jul 14 05:50:14 PM PDT 24 Jul 14 05:50:17 PM PDT 24 194396428 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.19444195 Jul 14 05:49:38 PM PDT 24 Jul 14 05:49:40 PM PDT 24 39265708 ps
T898 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1134273546 Jul 14 05:49:36 PM PDT 24 Jul 14 05:49:45 PM PDT 24 2197304044 ps
T899 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1971668841 Jul 14 05:50:24 PM PDT 24 Jul 14 05:50:26 PM PDT 24 38690359 ps
T900 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3631215558 Jul 14 05:50:35 PM PDT 24 Jul 14 05:50:37 PM PDT 24 48454006 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2090531331 Jul 14 05:49:47 PM PDT 24 Jul 14 05:49:49 PM PDT 24 27178862 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1643169029 Jul 14 05:49:59 PM PDT 24 Jul 14 05:50:10 PM PDT 24 4075041378 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2050775319 Jul 14 05:49:59 PM PDT 24 Jul 14 05:50:01 PM PDT 24 22848572 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3112757135 Jul 14 05:49:41 PM PDT 24 Jul 14 05:49:44 PM PDT 24 95421505 ps
T203 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1756054904 Jul 14 05:49:33 PM PDT 24 Jul 14 05:49:34 PM PDT 24 16348545 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3598847651 Jul 14 05:49:39 PM PDT 24 Jul 14 05:49:42 PM PDT 24 131538404 ps
T906 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2527315120 Jul 14 05:50:31 PM PDT 24 Jul 14 05:50:36 PM PDT 24 269666292 ps
T907 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1674875773 Jul 14 05:49:26 PM PDT 24 Jul 14 05:49:28 PM PDT 24 119487935 ps
T908 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2170095151 Jul 14 05:50:08 PM PDT 24 Jul 14 05:50:12 PM PDT 24 411380735 ps
T909 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3594909004 Jul 14 05:50:23 PM PDT 24 Jul 14 05:50:29 PM PDT 24 2430655535 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2688437351 Jul 14 05:49:45 PM PDT 24 Jul 14 05:49:48 PM PDT 24 126135509 ps
T911 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3213745676 Jul 14 05:50:16 PM PDT 24 Jul 14 05:50:19 PM PDT 24 194928331 ps
T912 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3112758622 Jul 14 05:50:13 PM PDT 24 Jul 14 05:50:15 PM PDT 24 13697328 ps
T913 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3228905854 Jul 14 05:49:42 PM PDT 24 Jul 14 05:49:44 PM PDT 24 67816710 ps
T914 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.512449299 Jul 14 05:49:25 PM PDT 24 Jul 14 05:49:31 PM PDT 24 421148384 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.498210431 Jul 14 05:49:41 PM PDT 24 Jul 14 05:49:42 PM PDT 24 46215807 ps
T916 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4027550182 Jul 14 05:50:22 PM PDT 24 Jul 14 05:50:27 PM PDT 24 185121926 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1120799631 Jul 14 05:50:22 PM PDT 24 Jul 14 05:50:24 PM PDT 24 89188276 ps
T918 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3880580030 Jul 14 05:50:23 PM PDT 24 Jul 14 05:50:25 PM PDT 24 148964674 ps
T919 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.696913423 Jul 14 05:50:25 PM PDT 24 Jul 14 05:50:26 PM PDT 24 87999852 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2117748480 Jul 14 05:49:41 PM PDT 24 Jul 14 05:49:45 PM PDT 24 2493830258 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1582671906 Jul 14 05:49:56 PM PDT 24 Jul 14 05:49:57 PM PDT 24 68917766 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1519108700 Jul 14 05:49:53 PM PDT 24 Jul 14 05:49:56 PM PDT 24 84968344 ps
T923 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2916251473 Jul 14 05:49:49 PM PDT 24 Jul 14 05:49:52 PM PDT 24 99550375 ps
T924 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3555504931 Jul 14 05:50:37 PM PDT 24 Jul 14 05:50:40 PM PDT 24 29532739 ps
T143 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2574170671 Jul 14 05:50:15 PM PDT 24 Jul 14 05:50:18 PM PDT 24 131351207 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3998188021 Jul 14 05:49:28 PM PDT 24 Jul 14 05:49:35 PM PDT 24 1687767972 ps
T926 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3671868477 Jul 14 05:50:10 PM PDT 24 Jul 14 05:50:12 PM PDT 24 47600093 ps
T927 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.235708737 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:35 PM PDT 24 53209056 ps
T928 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2396102535 Jul 14 05:50:23 PM PDT 24 Jul 14 05:50:26 PM PDT 24 127058882 ps
T204 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.747000884 Jul 14 05:49:18 PM PDT 24 Jul 14 05:49:19 PM PDT 24 72786316 ps
T148 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.355006782 Jul 14 05:49:20 PM PDT 24 Jul 14 05:49:24 PM PDT 24 103905948 ps
T929 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2945995334 Jul 14 05:49:54 PM PDT 24 Jul 14 05:49:57 PM PDT 24 217338887 ps
T930 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1249157777 Jul 14 05:50:22 PM PDT 24 Jul 14 05:50:26 PM PDT 24 852585187 ps
T931 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3525931391 Jul 14 05:50:01 PM PDT 24 Jul 14 05:50:02 PM PDT 24 68542493 ps
T932 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2606531222 Jul 14 05:49:48 PM PDT 24 Jul 14 05:49:50 PM PDT 24 70443713 ps
T933 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1394674400 Jul 14 05:49:50 PM PDT 24 Jul 14 05:49:54 PM PDT 24 49612155 ps
T205 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1944410719 Jul 14 05:50:34 PM PDT 24 Jul 14 05:50:36 PM PDT 24 47610653 ps
T934 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.631730471 Jul 14 05:50:14 PM PDT 24 Jul 14 05:50:16 PM PDT 24 39473708 ps
T935 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1907724279 Jul 14 05:50:35 PM PDT 24 Jul 14 05:50:39 PM PDT 24 621927791 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2522940855 Jul 14 05:49:39 PM PDT 24 Jul 14 05:49:46 PM PDT 24 586047575 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2455601214 Jul 14 05:50:01 PM PDT 24 Jul 14 05:50:03 PM PDT 24 18766401 ps
T206 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2650532600 Jul 14 05:50:22 PM PDT 24 Jul 14 05:50:23 PM PDT 24 87511951 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3801669926 Jul 14 05:49:49 PM PDT 24 Jul 14 05:49:52 PM PDT 24 60213612 ps
T939 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2780639035 Jul 14 05:50:34 PM PDT 24 Jul 14 05:50:36 PM PDT 24 51312058 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3977964696 Jul 14 05:49:20 PM PDT 24 Jul 14 05:49:22 PM PDT 24 67743796 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.333462363 Jul 14 05:49:26 PM PDT 24 Jul 14 05:49:28 PM PDT 24 25246199 ps
T942 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4222921612 Jul 14 05:50:00 PM PDT 24 Jul 14 05:50:04 PM PDT 24 501897158 ps
T943 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3930719252 Jul 14 05:49:18 PM PDT 24 Jul 14 05:49:19 PM PDT 24 38398405 ps
T944 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.711127606 Jul 14 05:49:40 PM PDT 24 Jul 14 05:49:53 PM PDT 24 4377247635 ps
T945 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.609606527 Jul 14 05:49:20 PM PDT 24 Jul 14 05:49:22 PM PDT 24 62102731 ps
T207 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1804503743 Jul 14 05:49:49 PM PDT 24 Jul 14 05:49:51 PM PDT 24 36452762 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3067183109 Jul 14 05:49:32 PM PDT 24 Jul 14 05:49:35 PM PDT 24 852352920 ps
T947 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1283506980 Jul 14 05:50:01 PM PDT 24 Jul 14 05:50:03 PM PDT 24 37551429 ps
T948 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3367914212 Jul 14 05:50:14 PM PDT 24 Jul 14 05:50:23 PM PDT 24 5192545141 ps
T949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3909675715 Jul 14 05:50:08 PM PDT 24 Jul 14 05:50:10 PM PDT 24 305273671 ps
T147 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1558599247 Jul 14 05:49:41 PM PDT 24 Jul 14 05:49:45 PM PDT 24 723717143 ps
T950 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.707948080 Jul 14 05:50:00 PM PDT 24 Jul 14 05:50:03 PM PDT 24 131035077 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1498568544 Jul 14 05:49:40 PM PDT 24 Jul 14 05:49:43 PM PDT 24 166816996 ps
T952 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1937153809 Jul 14 05:50:13 PM PDT 24 Jul 14 05:50:19 PM PDT 24 488358256 ps
T953 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1717909971 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:35 PM PDT 24 113410859 ps
T954 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4280231048 Jul 14 05:50:35 PM PDT 24 Jul 14 05:50:37 PM PDT 24 22723521 ps
T955 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1954652450 Jul 14 05:49:36 PM PDT 24 Jul 14 05:49:39 PM PDT 24 243615961 ps
T956 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1104046598 Jul 14 05:49:49 PM PDT 24 Jul 14 05:49:53 PM PDT 24 702355167 ps
T209 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1606628084 Jul 14 05:49:40 PM PDT 24 Jul 14 05:49:43 PM PDT 24 183338828 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3115176882 Jul 14 05:49:19 PM PDT 24 Jul 14 05:49:35 PM PDT 24 2545700336 ps
T958 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4146438494 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:35 PM PDT 24 28614209 ps
T959 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097072464 Jul 14 05:49:54 PM PDT 24 Jul 14 05:49:57 PM PDT 24 453019284 ps
T960 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3582630184 Jul 14 05:49:34 PM PDT 24 Jul 14 05:49:36 PM PDT 24 254185858 ps
T961 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2257088604 Jul 14 05:50:23 PM PDT 24 Jul 14 05:50:25 PM PDT 24 68637153 ps
T962 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1338999142 Jul 14 05:49:49 PM PDT 24 Jul 14 05:49:57 PM PDT 24 2968965406 ps
T151 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.64374491 Jul 14 05:50:24 PM PDT 24 Jul 14 05:50:27 PM PDT 24 295338442 ps
T208 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3964990741 Jul 14 05:49:40 PM PDT 24 Jul 14 05:49:42 PM PDT 24 15424907 ps
T963 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3514145002 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:36 PM PDT 24 26570859 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3606144114 Jul 14 05:50:16 PM PDT 24 Jul 14 05:50:18 PM PDT 24 222421425 ps
T134 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1260526118 Jul 14 05:50:34 PM PDT 24 Jul 14 05:50:38 PM PDT 24 121372997 ps
T965 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.433152110 Jul 14 05:49:48 PM PDT 24 Jul 14 05:49:50 PM PDT 24 45676657 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.579842082 Jul 14 05:49:39 PM PDT 24 Jul 14 05:49:41 PM PDT 24 40003203 ps
T967 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2298796099 Jul 14 05:49:59 PM PDT 24 Jul 14 05:50:03 PM PDT 24 935690954 ps
T210 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.607176678 Jul 14 05:49:36 PM PDT 24 Jul 14 05:49:38 PM PDT 24 43281121 ps
T968 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1336817019 Jul 14 05:50:34 PM PDT 24 Jul 14 05:50:36 PM PDT 24 48627821 ps
T969 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.92171871 Jul 14 05:49:46 PM PDT 24 Jul 14 05:49:47 PM PDT 24 11666001 ps
T970 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.687885428 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:36 PM PDT 24 142007444 ps
T971 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2660571158 Jul 14 05:49:53 PM PDT 24 Jul 14 05:49:56 PM PDT 24 33938650 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.903367868 Jul 14 05:49:40 PM PDT 24 Jul 14 05:49:42 PM PDT 24 14617092 ps
T973 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2961650941 Jul 14 05:50:31 PM PDT 24 Jul 14 05:50:34 PM PDT 24 193715004 ps
T974 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1231986208 Jul 14 05:50:23 PM PDT 24 Jul 14 05:50:26 PM PDT 24 130021718 ps
T975 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2096864507 Jul 14 05:49:14 PM PDT 24 Jul 14 05:49:18 PM PDT 24 1294059301 ps
T976 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.35284392 Jul 14 05:50:00 PM PDT 24 Jul 14 05:50:10 PM PDT 24 3982728775 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2900446993 Jul 14 05:49:48 PM PDT 24 Jul 14 05:49:50 PM PDT 24 15895226 ps
T978 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.392068411 Jul 14 05:49:38 PM PDT 24 Jul 14 05:49:39 PM PDT 24 43430384 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2916841721 Jul 14 05:50:07 PM PDT 24 Jul 14 05:50:11 PM PDT 24 135301609 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.768758395 Jul 14 05:50:08 PM PDT 24 Jul 14 05:50:10 PM PDT 24 36341155 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2768992444 Jul 14 05:49:26 PM PDT 24 Jul 14 05:49:30 PM PDT 24 150532760 ps
T982 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4022691251 Jul 14 05:50:34 PM PDT 24 Jul 14 05:50:38 PM PDT 24 85184456 ps
T211 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3612384970 Jul 14 05:49:34 PM PDT 24 Jul 14 05:49:36 PM PDT 24 22751372 ps
T212 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1319020206 Jul 14 05:49:39 PM PDT 24 Jul 14 05:49:41 PM PDT 24 39703211 ps
T149 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4285202007 Jul 14 05:50:00 PM PDT 24 Jul 14 05:50:02 PM PDT 24 44364188 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3334690993 Jul 14 05:49:49 PM PDT 24 Jul 14 05:49:52 PM PDT 24 238038550 ps
T984 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.975017764 Jul 14 05:49:41 PM PDT 24 Jul 14 05:49:44 PM PDT 24 177824364 ps
T985 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2411335876 Jul 14 05:50:09 PM PDT 24 Jul 14 05:50:11 PM PDT 24 68758812 ps
T986 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3712978816 Jul 14 05:50:24 PM PDT 24 Jul 14 05:50:25 PM PDT 24 56345783 ps
T150 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3688165183 Jul 14 05:50:07 PM PDT 24 Jul 14 05:50:10 PM PDT 24 285055452 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4066481087 Jul 14 05:50:00 PM PDT 24 Jul 14 05:50:04 PM PDT 24 161982158 ps
T213 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2752826294 Jul 14 05:49:57 PM PDT 24 Jul 14 05:49:58 PM PDT 24 19250278 ps
T214 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1307755304 Jul 14 05:50:32 PM PDT 24 Jul 14 05:50:34 PM PDT 24 30568356 ps
T988 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1729746097 Jul 14 05:49:48 PM PDT 24 Jul 14 05:49:51 PM PDT 24 252266112 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1484309130 Jul 14 05:49:47 PM PDT 24 Jul 14 05:49:49 PM PDT 24 51685513 ps
T990 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1680259868 Jul 14 05:49:39 PM PDT 24 Jul 14 05:49:41 PM PDT 24 30672229 ps
T991 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2977629392 Jul 14 05:49:46 PM PDT 24 Jul 14 05:49:50 PM PDT 24 595968323 ps
T139 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1352742515 Jul 14 05:50:33 PM PDT 24 Jul 14 05:50:38 PM PDT 24 584850409 ps
T144 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.850647873 Jul 14 05:50:24 PM PDT 24 Jul 14 05:50:26 PM PDT 24 209600867 ps
T992 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1563015261 Jul 14 05:50:32 PM PDT 24 Jul 14 05:50:34 PM PDT 24 86882482 ps
T993 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2563207891 Jul 14 05:50:15 PM PDT 24 Jul 14 05:50:16 PM PDT 24 64883578 ps
T994 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.596607657 Jul 14 05:50:23 PM PDT 24 Jul 14 05:50:28 PM PDT 24 128615430 ps

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2335287839
Short name T4
Test name
Test status
Simulation time 25874129248 ps
CPU time 199.87 seconds
Started Jul 14 06:20:31 PM PDT 24
Finished Jul 14 06:23:51 PM PDT 24
Peak memory 315692 kb
Host smart-37bd26bc-9094-40bb-acb8-e2f3ca2128cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335287839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2335287839
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3568938550
Short name T13
Test name
Test status
Simulation time 10097885447 ps
CPU time 306.45 seconds
Started Jul 14 06:22:25 PM PDT 24
Finished Jul 14 06:27:33 PM PDT 24
Peak memory 271500 kb
Host smart-ead36805-ee3c-4833-a843-92afde548831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568938550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3568938550
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.933229626
Short name T20
Test name
Test status
Simulation time 291493870 ps
CPU time 6.8 seconds
Started Jul 14 06:20:53 PM PDT 24
Finished Jul 14 06:21:02 PM PDT 24
Peak memory 224484 kb
Host smart-81099d74-3f34-4a72-9990-86a97a5c5e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933229626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.933229626
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.4099592604
Short name T54
Test name
Test status
Simulation time 1335994709 ps
CPU time 15.9 seconds
Started Jul 14 06:21:19 PM PDT 24
Finished Jul 14 06:21:36 PM PDT 24
Peak memory 226044 kb
Host smart-3d751802-1d60-4261-9260-5d3b93d7c9e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099592604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.4099592604
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1759769627
Short name T9
Test name
Test status
Simulation time 283367058 ps
CPU time 12.41 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:31 PM PDT 24
Peak memory 225972 kb
Host smart-009b0183-75c1-488b-833b-b9f7b92f2eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759769627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1759769627
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3929551093
Short name T124
Test name
Test status
Simulation time 365864909 ps
CPU time 2.43 seconds
Started Jul 14 05:49:53 PM PDT 24
Finished Jul 14 05:49:56 PM PDT 24
Peak memory 217584 kb
Host smart-3c5a75be-f4bd-43c0-bdcd-0eee47e386fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392955
1093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3929551093
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1375771473
Short name T18
Test name
Test status
Simulation time 5654869024 ps
CPU time 16.16 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:49 PM PDT 24
Peak memory 218288 kb
Host smart-1820666d-b840-46ff-9391-327492aaff64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375771473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1375771473
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.175238971
Short name T120
Test name
Test status
Simulation time 82541304767 ps
CPU time 800.75 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:35:40 PM PDT 24
Peak memory 480540 kb
Host smart-38ac67b8-92dd-4499-ba69-def9cdc1d3af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=175238971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.175238971
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.413876293
Short name T49
Test name
Test status
Simulation time 467181179 ps
CPU time 23.69 seconds
Started Jul 14 06:20:54 PM PDT 24
Finished Jul 14 06:21:20 PM PDT 24
Peak memory 269236 kb
Host smart-f6cf3f61-cfb1-440c-9543-50f21ac5d9a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413876293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.413876293
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1927552905
Short name T58
Test name
Test status
Simulation time 33102504128 ps
CPU time 267.98 seconds
Started Jul 14 06:21:38 PM PDT 24
Finished Jul 14 06:26:07 PM PDT 24
Peak memory 282232 kb
Host smart-ff20425d-5f9f-4705-8b4f-89bc3dbc41bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927552905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1927552905
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2598772891
Short name T126
Test name
Test status
Simulation time 120053997 ps
CPU time 3 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:36 PM PDT 24
Peak memory 222244 kb
Host smart-56f632e6-d784-4fd2-b405-4af2b105b7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598772891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2598772891
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.144767448
Short name T6
Test name
Test status
Simulation time 2205558864 ps
CPU time 10.97 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:55 PM PDT 24
Peak memory 217376 kb
Host smart-e3f72713-8c0c-42a7-ae1c-4d9c34ae9f59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144767448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.144767448
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.273854330
Short name T235
Test name
Test status
Simulation time 30625358 ps
CPU time 1.1 seconds
Started Jul 14 06:22:39 PM PDT 24
Finished Jul 14 06:22:41 PM PDT 24
Peak memory 209004 kb
Host smart-86dc2a7b-4ddf-4f8f-954f-77942289f6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273854330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.273854330
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1756054904
Short name T203
Test name
Test status
Simulation time 16348545 ps
CPU time 0.96 seconds
Started Jul 14 05:49:33 PM PDT 24
Finished Jul 14 05:49:34 PM PDT 24
Peak memory 209288 kb
Host smart-af054d5c-e411-4565-982f-09d8cffb59d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756054904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1756054904
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3180598852
Short name T69
Test name
Test status
Simulation time 20850916348 ps
CPU time 739.15 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:33:03 PM PDT 24
Peak memory 283740 kb
Host smart-c458b94a-ea37-4f58-ae8b-bb0ad87806ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3180598852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3180598852
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2008501259
Short name T12
Test name
Test status
Simulation time 440380175 ps
CPU time 10.27 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:20:54 PM PDT 24
Peak memory 226024 kb
Host smart-6969e63d-f3e9-490c-92ba-7ab4aeec1046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008501259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2008501259
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.602534041
Short name T137
Test name
Test status
Simulation time 118470657 ps
CPU time 4.37 seconds
Started Jul 14 05:49:28 PM PDT 24
Finished Jul 14 05:49:33 PM PDT 24
Peak memory 217596 kb
Host smart-8cb00ba3-0d39-476c-b766-48c4a3baf31a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602534041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.602534041
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1977885939
Short name T133
Test name
Test status
Simulation time 224991215 ps
CPU time 4.4 seconds
Started Jul 14 05:50:34 PM PDT 24
Finished Jul 14 05:50:40 PM PDT 24
Peak memory 217612 kb
Host smart-dee5553a-6c7a-446e-8f73-cd49b2e43cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977885939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1977885939
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1558599247
Short name T147
Test name
Test status
Simulation time 723717143 ps
CPU time 3.98 seconds
Started Jul 14 05:49:41 PM PDT 24
Finished Jul 14 05:49:45 PM PDT 24
Peak memory 217540 kb
Host smart-ae0c824b-ac08-43b7-ad88-73d865bec04e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558599247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1558599247
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.395862037
Short name T141
Test name
Test status
Simulation time 145733717 ps
CPU time 3.32 seconds
Started Jul 14 05:49:48 PM PDT 24
Finished Jul 14 05:49:52 PM PDT 24
Peak memory 217488 kb
Host smart-a6a9f76b-3dd6-4175-be6f-0457c0ef59a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395862037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.395862037
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2038721105
Short name T43
Test name
Test status
Simulation time 135976137753 ps
CPU time 358.37 seconds
Started Jul 14 06:22:44 PM PDT 24
Finished Jul 14 06:28:43 PM PDT 24
Peak memory 364376 kb
Host smart-3269cbab-f124-42cd-b20e-7e775ce59d5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2038721105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2038721105
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2427391357
Short name T114
Test name
Test status
Simulation time 996092918 ps
CPU time 22.9 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:21:05 PM PDT 24
Peak memory 282772 kb
Host smart-6b284eed-3a6d-4094-ae1c-8ddd98ef393c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427391357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2427391357
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3655703100
Short name T85
Test name
Test status
Simulation time 182318932 ps
CPU time 6.06 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:20 PM PDT 24
Peak memory 250356 kb
Host smart-5351da77-4187-4007-97d7-1656eb625a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655703100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3655703100
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.389398471
Short name T222
Test name
Test status
Simulation time 56577199 ps
CPU time 0.97 seconds
Started Jul 14 05:49:20 PM PDT 24
Finished Jul 14 05:49:21 PM PDT 24
Peak memory 217480 kb
Host smart-1294e931-a6a9-4c8f-91b4-d7f623c70314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389398471 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.389398471
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.464222919
Short name T103
Test name
Test status
Simulation time 107590489032 ps
CPU time 718.78 seconds
Started Jul 14 06:20:33 PM PDT 24
Finished Jul 14 06:32:32 PM PDT 24
Peak memory 283900 kb
Host smart-8516dd52-672d-4e6e-93f7-bdc0a7686fb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=464222919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.464222919
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2554023288
Short name T3
Test name
Test status
Simulation time 54312987 ps
CPU time 0.88 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:21:53 PM PDT 24
Peak memory 217728 kb
Host smart-5bd28387-7b6a-42bf-8b0c-bc9eacecfa9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554023288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2554023288
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.355006782
Short name T148
Test name
Test status
Simulation time 103905948 ps
CPU time 3.01 seconds
Started Jul 14 05:49:20 PM PDT 24
Finished Jul 14 05:49:24 PM PDT 24
Peak memory 222272 kb
Host smart-1f519511-3b41-4c23-89c8-609ebbc4a423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355006782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.355006782
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.64374491
Short name T151
Test name
Test status
Simulation time 295338442 ps
CPU time 2.64 seconds
Started Jul 14 05:50:24 PM PDT 24
Finished Jul 14 05:50:27 PM PDT 24
Peak memory 222068 kb
Host smart-01212cf0-18c3-4297-873f-419d52cdc1f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64374491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_e
rr.64374491
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1694518940
Short name T227
Test name
Test status
Simulation time 79712654 ps
CPU time 0.9 seconds
Started Jul 14 06:20:24 PM PDT 24
Finished Jul 14 06:20:26 PM PDT 24
Peak memory 209156 kb
Host smart-1ef40b85-cc25-41e0-89fd-74c780d0408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694518940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1694518940
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.677724438
Short name T224
Test name
Test status
Simulation time 14414868 ps
CPU time 0.91 seconds
Started Jul 14 06:20:35 PM PDT 24
Finished Jul 14 06:20:37 PM PDT 24
Peak memory 208768 kb
Host smart-e70a7e4f-806b-4015-9b81-aeafd196427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677724438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.677724438
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1371036647
Short name T644
Test name
Test status
Simulation time 1096291582 ps
CPU time 11.27 seconds
Started Jul 14 06:21:36 PM PDT 24
Finished Jul 14 06:21:48 PM PDT 24
Peak memory 225944 kb
Host smart-cf837f7f-46c5-44a5-a614-6f0f8ea536ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371036647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1371036647
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4261105778
Short name T105
Test name
Test status
Simulation time 40381958 ps
CPU time 0.85 seconds
Started Jul 14 06:21:21 PM PDT 24
Finished Jul 14 06:21:23 PM PDT 24
Peak memory 208912 kb
Host smart-a005ef42-dfca-4ef6-bb06-9bb5d91d013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261105778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4261105778
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1078516473
Short name T130
Test name
Test status
Simulation time 134874510 ps
CPU time 2.55 seconds
Started Jul 14 05:49:25 PM PDT 24
Finished Jul 14 05:49:28 PM PDT 24
Peak memory 217428 kb
Host smart-aff28944-5996-4482-928d-39d3e76453c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078516473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1078516473
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.850647873
Short name T144
Test name
Test status
Simulation time 209600867 ps
CPU time 1.93 seconds
Started Jul 14 05:50:24 PM PDT 24
Finished Jul 14 05:50:26 PM PDT 24
Peak memory 221700 kb
Host smart-1e798600-d39c-4406-bc97-38a52e3d472a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850647873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.850647873
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.793136140
Short name T129
Test name
Test status
Simulation time 448752300 ps
CPU time 3.29 seconds
Started Jul 14 05:50:31 PM PDT 24
Finished Jul 14 05:50:35 PM PDT 24
Peak memory 222216 kb
Host smart-3e49eb92-d4a6-4a80-8c07-7af738281c14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793136140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.793136140
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1352742515
Short name T139
Test name
Test status
Simulation time 584850409 ps
CPU time 4.13 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:38 PM PDT 24
Peak memory 217608 kb
Host smart-b5ce8ccd-6c77-4ade-ae3b-035f7b090ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352742515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1352742515
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3688165183
Short name T150
Test name
Test status
Simulation time 285055452 ps
CPU time 2.71 seconds
Started Jul 14 05:50:07 PM PDT 24
Finished Jul 14 05:50:10 PM PDT 24
Peak memory 222272 kb
Host smart-802149c1-75e9-4a30-9e74-7e6df72bfccc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688165183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3688165183
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.673318018
Short name T25
Test name
Test status
Simulation time 716790246 ps
CPU time 20.72 seconds
Started Jul 14 06:20:23 PM PDT 24
Finished Jul 14 06:20:44 PM PDT 24
Peak memory 225664 kb
Host smart-19f0368b-069a-4dab-afa6-5774a0286e6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673318018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.673318018
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4231494955
Short name T893
Test name
Test status
Simulation time 38194471 ps
CPU time 1.34 seconds
Started Jul 14 05:49:19 PM PDT 24
Finished Jul 14 05:49:21 PM PDT 24
Peak memory 209188 kb
Host smart-8d1b009c-38cf-4122-9e79-0ea285bcb189
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231494955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.4231494955
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3977964696
Short name T940
Test name
Test status
Simulation time 67743796 ps
CPU time 1.1 seconds
Started Jul 14 05:49:20 PM PDT 24
Finished Jul 14 05:49:22 PM PDT 24
Peak memory 208928 kb
Host smart-9184af4d-517e-41d2-b7c6-cecfd5bf7294
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977964696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3977964696
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2023974388
Short name T875
Test name
Test status
Simulation time 17839478 ps
CPU time 0.91 seconds
Started Jul 14 05:49:21 PM PDT 24
Finished Jul 14 05:49:22 PM PDT 24
Peak memory 209804 kb
Host smart-7100bd96-f498-433d-b625-2f66ec82e30d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023974388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2023974388
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.333462363
Short name T941
Test name
Test status
Simulation time 25246199 ps
CPU time 1.62 seconds
Started Jul 14 05:49:26 PM PDT 24
Finished Jul 14 05:49:28 PM PDT 24
Peak memory 217620 kb
Host smart-7e234906-4e93-45dd-8798-da268707379c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333462363 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.333462363
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.747000884
Short name T204
Test name
Test status
Simulation time 72786316 ps
CPU time 0.95 seconds
Started Jul 14 05:49:18 PM PDT 24
Finished Jul 14 05:49:19 PM PDT 24
Peak memory 209092 kb
Host smart-9e09577b-840d-4c0d-b8ec-cd59b810f2a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747000884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.747000884
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3930719252
Short name T943
Test name
Test status
Simulation time 38398405 ps
CPU time 1.15 seconds
Started Jul 14 05:49:18 PM PDT 24
Finished Jul 14 05:49:19 PM PDT 24
Peak memory 208592 kb
Host smart-9fcf3bf8-7411-4793-a585-813a38414228
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930719252 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3930719252
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3115176882
Short name T957
Test name
Test status
Simulation time 2545700336 ps
CPU time 15.29 seconds
Started Jul 14 05:49:19 PM PDT 24
Finished Jul 14 05:49:35 PM PDT 24
Peak memory 209276 kb
Host smart-7a52cf46-7bd9-4b76-ad0a-82f5a96b5034
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115176882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3115176882
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1151076624
Short name T870
Test name
Test status
Simulation time 897371829 ps
CPU time 5.74 seconds
Started Jul 14 05:49:20 PM PDT 24
Finished Jul 14 05:49:26 PM PDT 24
Peak memory 208856 kb
Host smart-829be00a-38ef-4907-8864-a4cd30cfd96f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151076624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1151076624
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2096864507
Short name T975
Test name
Test status
Simulation time 1294059301 ps
CPU time 2.52 seconds
Started Jul 14 05:49:14 PM PDT 24
Finished Jul 14 05:49:18 PM PDT 24
Peak memory 217408 kb
Host smart-ac49f809-ae1d-4563-8721-04b5f703514a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096864507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2096864507
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3447806214
Short name T142
Test name
Test status
Simulation time 106234338 ps
CPU time 2.43 seconds
Started Jul 14 05:49:20 PM PDT 24
Finished Jul 14 05:49:23 PM PDT 24
Peak memory 217660 kb
Host smart-61a01675-62da-4c04-a1ca-07a1d2366631
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344780
6214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3447806214
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3710930630
Short name T877
Test name
Test status
Simulation time 175240989 ps
CPU time 2.24 seconds
Started Jul 14 05:49:15 PM PDT 24
Finished Jul 14 05:49:18 PM PDT 24
Peak memory 209220 kb
Host smart-c33efae8-acf7-4e8c-8f54-574b1382854f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710930630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3710930630
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.609606527
Short name T945
Test name
Test status
Simulation time 62102731 ps
CPU time 0.99 seconds
Started Jul 14 05:49:20 PM PDT 24
Finished Jul 14 05:49:22 PM PDT 24
Peak memory 209272 kb
Host smart-b8a110f3-45b5-45b3-b2ae-c62790a07b2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609606527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.609606527
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3527853067
Short name T885
Test name
Test status
Simulation time 497191803 ps
CPU time 2.68 seconds
Started Jul 14 05:49:20 PM PDT 24
Finished Jul 14 05:49:23 PM PDT 24
Peak memory 217436 kb
Host smart-da96ff9d-d6c7-45c5-95a5-5de179f3fa16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527853067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3527853067
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1954652450
Short name T955
Test name
Test status
Simulation time 243615961 ps
CPU time 1.83 seconds
Started Jul 14 05:49:36 PM PDT 24
Finished Jul 14 05:49:39 PM PDT 24
Peak memory 209268 kb
Host smart-17491223-e7f7-429d-a020-7618d09066bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954652450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1954652450
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3612384970
Short name T211
Test name
Test status
Simulation time 22751372 ps
CPU time 1.05 seconds
Started Jul 14 05:49:34 PM PDT 24
Finished Jul 14 05:49:36 PM PDT 24
Peak memory 209276 kb
Host smart-b98ad7b3-f861-44fa-b9f1-0a5d85964cf1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612384970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3612384970
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1680259868
Short name T990
Test name
Test status
Simulation time 30672229 ps
CPU time 2.21 seconds
Started Jul 14 05:49:39 PM PDT 24
Finished Jul 14 05:49:41 PM PDT 24
Peak memory 217720 kb
Host smart-74aff656-2475-41e7-a265-e187abb241a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680259868 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1680259868
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.607176678
Short name T210
Test name
Test status
Simulation time 43281121 ps
CPU time 0.86 seconds
Started Jul 14 05:49:36 PM PDT 24
Finished Jul 14 05:49:38 PM PDT 24
Peak memory 209116 kb
Host smart-837f17ed-d68d-469b-b6b0-6ddfd5634ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607176678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.607176678
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1674875773
Short name T907
Test name
Test status
Simulation time 119487935 ps
CPU time 1.2 seconds
Started Jul 14 05:49:26 PM PDT 24
Finished Jul 14 05:49:28 PM PDT 24
Peak memory 208604 kb
Host smart-2a144eca-c9c6-4213-85e1-bdab606202e6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674875773 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1674875773
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3998188021
Short name T925
Test name
Test status
Simulation time 1687767972 ps
CPU time 5.68 seconds
Started Jul 14 05:49:28 PM PDT 24
Finished Jul 14 05:49:35 PM PDT 24
Peak memory 209000 kb
Host smart-9338e06d-08c4-4a71-950a-6ed458553fc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998188021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3998188021
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.512449299
Short name T914
Test name
Test status
Simulation time 421148384 ps
CPU time 5.81 seconds
Started Jul 14 05:49:25 PM PDT 24
Finished Jul 14 05:49:31 PM PDT 24
Peak memory 216992 kb
Host smart-1b134181-3c45-4804-8acf-f362dfd457a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512449299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.512449299
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3209060339
Short name T878
Test name
Test status
Simulation time 196351592 ps
CPU time 1.36 seconds
Started Jul 14 05:49:30 PM PDT 24
Finished Jul 14 05:49:31 PM PDT 24
Peak memory 210336 kb
Host smart-ff4ae612-0a25-4766-a4b1-a348891d5a6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209060339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3209060339
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2768992444
Short name T981
Test name
Test status
Simulation time 150532760 ps
CPU time 2.84 seconds
Started Jul 14 05:49:26 PM PDT 24
Finished Jul 14 05:49:30 PM PDT 24
Peak memory 217540 kb
Host smart-3235976c-72a5-46aa-8754-cca74ccfc03d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276899
2444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2768992444
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2005802117
Short name T874
Test name
Test status
Simulation time 135724661 ps
CPU time 1.57 seconds
Started Jul 14 05:49:28 PM PDT 24
Finished Jul 14 05:49:30 PM PDT 24
Peak memory 217464 kb
Host smart-448df14b-3115-4cc9-9bfa-193789062533
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005802117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2005802117
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2359975858
Short name T219
Test name
Test status
Simulation time 25082429 ps
CPU time 1.15 seconds
Started Jul 14 05:49:29 PM PDT 24
Finished Jul 14 05:49:31 PM PDT 24
Peak memory 209228 kb
Host smart-a321dbd3-71ae-418e-9432-530edcf9ea41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359975858 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2359975858
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3283503340
Short name T217
Test name
Test status
Simulation time 36869103 ps
CPU time 1.76 seconds
Started Jul 14 05:49:36 PM PDT 24
Finished Jul 14 05:49:39 PM PDT 24
Peak memory 209204 kb
Host smart-2db69509-b481-41d1-b34d-96a38d432428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283503340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3283503340
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3880580030
Short name T918
Test name
Test status
Simulation time 148964674 ps
CPU time 1.49 seconds
Started Jul 14 05:50:23 PM PDT 24
Finished Jul 14 05:50:25 PM PDT 24
Peak memory 217620 kb
Host smart-047c5245-37bb-4aac-bafc-b778fe73a643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880580030 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3880580030
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3950110552
Short name T199
Test name
Test status
Simulation time 15144880 ps
CPU time 1.09 seconds
Started Jul 14 05:50:21 PM PDT 24
Finished Jul 14 05:50:23 PM PDT 24
Peak memory 209316 kb
Host smart-f4e70435-1325-449f-8c2c-d5faadd0da16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950110552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3950110552
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.75969128
Short name T152
Test name
Test status
Simulation time 42416365 ps
CPU time 1.42 seconds
Started Jul 14 05:50:21 PM PDT 24
Finished Jul 14 05:50:23 PM PDT 24
Peak memory 217520 kb
Host smart-26fda73a-cd01-4c4c-8872-071b87ddba63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75969128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
same_csr_outstanding.75969128
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1249157777
Short name T930
Test name
Test status
Simulation time 852585187 ps
CPU time 4.55 seconds
Started Jul 14 05:50:22 PM PDT 24
Finished Jul 14 05:50:26 PM PDT 24
Peak memory 217392 kb
Host smart-16de51c9-a8b4-43c5-9490-76d9a67be82b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249157777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1249157777
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3952035683
Short name T138
Test name
Test status
Simulation time 164315701 ps
CPU time 2.17 seconds
Started Jul 14 05:50:22 PM PDT 24
Finished Jul 14 05:50:25 PM PDT 24
Peak memory 217508 kb
Host smart-b78159ae-9061-4547-9ad0-d11804e924e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952035683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3952035683
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2365293066
Short name T185
Test name
Test status
Simulation time 30289270 ps
CPU time 0.96 seconds
Started Jul 14 05:50:21 PM PDT 24
Finished Jul 14 05:50:22 PM PDT 24
Peak memory 217484 kb
Host smart-48bcd4b4-8fbe-4be7-b383-6dd568bc3240
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365293066 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2365293066
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2650532600
Short name T206
Test name
Test status
Simulation time 87511951 ps
CPU time 0.84 seconds
Started Jul 14 05:50:22 PM PDT 24
Finished Jul 14 05:50:23 PM PDT 24
Peak memory 209208 kb
Host smart-5f64f76e-7375-497a-905d-42e907806c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650532600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2650532600
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.696913423
Short name T919
Test name
Test status
Simulation time 87999852 ps
CPU time 1.04 seconds
Started Jul 14 05:50:25 PM PDT 24
Finished Jul 14 05:50:26 PM PDT 24
Peak memory 209360 kb
Host smart-3db08755-64f5-430e-8e7a-95eb94fc2de1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696913423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.696913423
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4027550182
Short name T916
Test name
Test status
Simulation time 185121926 ps
CPU time 3.77 seconds
Started Jul 14 05:50:22 PM PDT 24
Finished Jul 14 05:50:27 PM PDT 24
Peak memory 217400 kb
Host smart-a5416b06-cd63-4b59-a963-b4990e8f97aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027550182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4027550182
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2396102535
Short name T928
Test name
Test status
Simulation time 127058882 ps
CPU time 2.76 seconds
Started Jul 14 05:50:23 PM PDT 24
Finished Jul 14 05:50:26 PM PDT 24
Peak memory 217488 kb
Host smart-775531e1-4d42-4ff8-abcd-a5781a710061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396102535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2396102535
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2121856756
Short name T888
Test name
Test status
Simulation time 18931545 ps
CPU time 1.03 seconds
Started Jul 14 05:50:23 PM PDT 24
Finished Jul 14 05:50:25 PM PDT 24
Peak memory 217640 kb
Host smart-bada0c77-4f81-42a0-8c63-23e10bc9dfc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121856756 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2121856756
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3563635995
Short name T202
Test name
Test status
Simulation time 24771830 ps
CPU time 0.98 seconds
Started Jul 14 05:50:24 PM PDT 24
Finished Jul 14 05:50:25 PM PDT 24
Peak memory 208744 kb
Host smart-68b43eaf-dab4-49a4-80ab-c1dae183f558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563635995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3563635995
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3712978816
Short name T986
Test name
Test status
Simulation time 56345783 ps
CPU time 1.01 seconds
Started Jul 14 05:50:24 PM PDT 24
Finished Jul 14 05:50:25 PM PDT 24
Peak memory 217432 kb
Host smart-e38cde11-00e0-441e-87e7-d507615f809d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712978816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3712978816
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3594909004
Short name T909
Test name
Test status
Simulation time 2430655535 ps
CPU time 5.28 seconds
Started Jul 14 05:50:23 PM PDT 24
Finished Jul 14 05:50:29 PM PDT 24
Peak memory 217548 kb
Host smart-c3aaa3f9-df8a-482d-8fe5-2e3f238059d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594909004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3594909004
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1971668841
Short name T899
Test name
Test status
Simulation time 38690359 ps
CPU time 1.66 seconds
Started Jul 14 05:50:24 PM PDT 24
Finished Jul 14 05:50:26 PM PDT 24
Peak memory 219272 kb
Host smart-9dfa6b31-e5f2-49b4-8c58-991b8606e84c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971668841 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1971668841
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3684049534
Short name T154
Test name
Test status
Simulation time 46204297 ps
CPU time 0.85 seconds
Started Jul 14 05:50:22 PM PDT 24
Finished Jul 14 05:50:24 PM PDT 24
Peak memory 209200 kb
Host smart-916f6414-5c4c-4762-b000-ef4cce66be7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684049534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3684049534
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1209737598
Short name T221
Test name
Test status
Simulation time 36730842 ps
CPU time 1.14 seconds
Started Jul 14 05:50:23 PM PDT 24
Finished Jul 14 05:50:25 PM PDT 24
Peak memory 217508 kb
Host smart-58acd74f-b62d-4095-85bb-5bfb87f89a05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209737598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1209737598
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1231986208
Short name T974
Test name
Test status
Simulation time 130021718 ps
CPU time 2.11 seconds
Started Jul 14 05:50:23 PM PDT 24
Finished Jul 14 05:50:26 PM PDT 24
Peak memory 217404 kb
Host smart-97e898db-14af-4527-aa9a-604a4b6d59cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231986208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1231986208
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4146438494
Short name T958
Test name
Test status
Simulation time 28614209 ps
CPU time 1.47 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:35 PM PDT 24
Peak memory 217568 kb
Host smart-6148d5d6-1b3b-4abb-bd30-b48d99dd3f26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146438494 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4146438494
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.646171692
Short name T132
Test name
Test status
Simulation time 78405210 ps
CPU time 0.92 seconds
Started Jul 14 05:50:32 PM PDT 24
Finished Jul 14 05:50:34 PM PDT 24
Peak memory 209244 kb
Host smart-fa132860-a897-48d4-a750-3ebdc8ae2d1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646171692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.646171692
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4002817774
Short name T215
Test name
Test status
Simulation time 17133769 ps
CPU time 1.09 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:35 PM PDT 24
Peak memory 209320 kb
Host smart-6e6b373a-ab31-4ca4-957d-717aba8049a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002817774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.4002817774
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.596607657
Short name T994
Test name
Test status
Simulation time 128615430 ps
CPU time 3.92 seconds
Started Jul 14 05:50:23 PM PDT 24
Finished Jul 14 05:50:28 PM PDT 24
Peak memory 217460 kb
Host smart-b83128e3-ac5d-4407-ae8b-32acb68fdf39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596607657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.596607657
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1260526118
Short name T134
Test name
Test status
Simulation time 121372997 ps
CPU time 3.08 seconds
Started Jul 14 05:50:34 PM PDT 24
Finished Jul 14 05:50:38 PM PDT 24
Peak memory 222036 kb
Host smart-670bca21-bd72-4b94-9b70-42229711befe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260526118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1260526118
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.822931428
Short name T153
Test name
Test status
Simulation time 56860895 ps
CPU time 1.19 seconds
Started Jul 14 05:50:35 PM PDT 24
Finished Jul 14 05:50:37 PM PDT 24
Peak memory 217564 kb
Host smart-ba9681bb-4912-4ae1-af62-91ebc022acac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822931428 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.822931428
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2035360703
Short name T200
Test name
Test status
Simulation time 71409405 ps
CPU time 0.95 seconds
Started Jul 14 05:50:31 PM PDT 24
Finished Jul 14 05:50:32 PM PDT 24
Peak memory 209312 kb
Host smart-01245bd4-87ef-4fa6-a35f-dd72a7d7bd5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035360703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2035360703
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3631215558
Short name T900
Test name
Test status
Simulation time 48454006 ps
CPU time 1.35 seconds
Started Jul 14 05:50:35 PM PDT 24
Finished Jul 14 05:50:37 PM PDT 24
Peak memory 217428 kb
Host smart-b36dd653-dc7a-447b-ba7c-97f30c4f527b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631215558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3631215558
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3360932688
Short name T881
Test name
Test status
Simulation time 162990662 ps
CPU time 2.78 seconds
Started Jul 14 05:50:32 PM PDT 24
Finished Jul 14 05:50:35 PM PDT 24
Peak memory 218568 kb
Host smart-498a0a09-ad8c-4484-8b42-d2d972beda8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360932688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3360932688
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.235708737
Short name T927
Test name
Test status
Simulation time 53209056 ps
CPU time 1.34 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:35 PM PDT 24
Peak memory 218784 kb
Host smart-026195c9-d694-4e49-bf7c-c0e1f5b6db92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235708737 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.235708737
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1307755304
Short name T214
Test name
Test status
Simulation time 30568356 ps
CPU time 0.83 seconds
Started Jul 14 05:50:32 PM PDT 24
Finished Jul 14 05:50:34 PM PDT 24
Peak memory 209168 kb
Host smart-a6ba8b2f-5c24-4055-b4b7-bb7406d57d8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307755304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1307755304
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1563015261
Short name T992
Test name
Test status
Simulation time 86882482 ps
CPU time 1.95 seconds
Started Jul 14 05:50:32 PM PDT 24
Finished Jul 14 05:50:34 PM PDT 24
Peak memory 211440 kb
Host smart-df0a778b-c96c-40c7-aae6-eaeeeaeb4bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563015261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1563015261
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4022691251
Short name T982
Test name
Test status
Simulation time 85184456 ps
CPU time 3.46 seconds
Started Jul 14 05:50:34 PM PDT 24
Finished Jul 14 05:50:38 PM PDT 24
Peak memory 218288 kb
Host smart-35b0242b-3e10-4b69-8cfe-8e69c7d892e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022691251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.4022691251
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1907724279
Short name T935
Test name
Test status
Simulation time 621927791 ps
CPU time 3.11 seconds
Started Jul 14 05:50:35 PM PDT 24
Finished Jul 14 05:50:39 PM PDT 24
Peak memory 222008 kb
Host smart-0552285f-a50d-45b8-b279-a6030d657d48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907724279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1907724279
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1717909971
Short name T953
Test name
Test status
Simulation time 113410859 ps
CPU time 1.72 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:35 PM PDT 24
Peak memory 217588 kb
Host smart-affc37f9-7c3b-4f6c-9af7-86168c918f22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717909971 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1717909971
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1898784168
Short name T201
Test name
Test status
Simulation time 39435232 ps
CPU time 0.96 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:35 PM PDT 24
Peak memory 209444 kb
Host smart-89ae9b17-fd55-456e-ae96-24df14104b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898784168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1898784168
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1336817019
Short name T968
Test name
Test status
Simulation time 48627821 ps
CPU time 1.19 seconds
Started Jul 14 05:50:34 PM PDT 24
Finished Jul 14 05:50:36 PM PDT 24
Peak memory 217484 kb
Host smart-cdf0e1a4-346b-49f1-b89e-ead191897f5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336817019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1336817019
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2961650941
Short name T973
Test name
Test status
Simulation time 193715004 ps
CPU time 2.04 seconds
Started Jul 14 05:50:31 PM PDT 24
Finished Jul 14 05:50:34 PM PDT 24
Peak memory 217512 kb
Host smart-f387f691-b54f-426d-9d61-4b14f8140798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961650941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2961650941
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4280231048
Short name T954
Test name
Test status
Simulation time 22723521 ps
CPU time 1.6 seconds
Started Jul 14 05:50:35 PM PDT 24
Finished Jul 14 05:50:37 PM PDT 24
Peak memory 222040 kb
Host smart-5ed62d9e-b9f6-4bde-a8dc-5bd675813008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280231048 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.4280231048
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1944410719
Short name T205
Test name
Test status
Simulation time 47610653 ps
CPU time 1.01 seconds
Started Jul 14 05:50:34 PM PDT 24
Finished Jul 14 05:50:36 PM PDT 24
Peak memory 208972 kb
Host smart-86700e00-2703-428d-8e66-099bfe48f8db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944410719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1944410719
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3514145002
Short name T963
Test name
Test status
Simulation time 26570859 ps
CPU time 1.49 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:36 PM PDT 24
Peak memory 217808 kb
Host smart-f6df9ed8-4c27-4799-8957-2c0a420a7482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514145002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3514145002
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2780639035
Short name T939
Test name
Test status
Simulation time 51312058 ps
CPU time 1.71 seconds
Started Jul 14 05:50:34 PM PDT 24
Finished Jul 14 05:50:36 PM PDT 24
Peak memory 217368 kb
Host smart-b85fa9e2-fc71-4879-ae11-94e15a475abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780639035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2780639035
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3555504931
Short name T924
Test name
Test status
Simulation time 29532739 ps
CPU time 2 seconds
Started Jul 14 05:50:37 PM PDT 24
Finished Jul 14 05:50:40 PM PDT 24
Peak memory 219564 kb
Host smart-da3a714e-54b8-4612-a32a-533a6231a7cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555504931 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3555504931
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.162300054
Short name T890
Test name
Test status
Simulation time 12316083 ps
CPU time 0.86 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:35 PM PDT 24
Peak memory 208732 kb
Host smart-bc921380-bb7c-441f-806b-cfcc3d53c1d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162300054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.162300054
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.687885428
Short name T970
Test name
Test status
Simulation time 142007444 ps
CPU time 1.65 seconds
Started Jul 14 05:50:33 PM PDT 24
Finished Jul 14 05:50:36 PM PDT 24
Peak memory 211324 kb
Host smart-86a98ba0-5621-4bc6-ac6e-9b3823fe5ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687885428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.687885428
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2527315120
Short name T906
Test name
Test status
Simulation time 269666292 ps
CPU time 4.9 seconds
Started Jul 14 05:50:31 PM PDT 24
Finished Jul 14 05:50:36 PM PDT 24
Peak memory 217344 kb
Host smart-929a54f2-5423-43a4-b061-20a7f6069edb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527315120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2527315120
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.579842082
Short name T966
Test name
Test status
Simulation time 40003203 ps
CPU time 1.42 seconds
Started Jul 14 05:49:39 PM PDT 24
Finished Jul 14 05:49:41 PM PDT 24
Peak memory 209280 kb
Host smart-1c52b49b-7adb-4f1e-8f33-3c937af29e97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579842082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.579842082
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1606628084
Short name T209
Test name
Test status
Simulation time 183338828 ps
CPU time 3.23 seconds
Started Jul 14 05:49:40 PM PDT 24
Finished Jul 14 05:49:43 PM PDT 24
Peak memory 209316 kb
Host smart-ca45eda4-a690-45cc-89dc-ea05cde95711
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606628084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1606628084
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3964990741
Short name T208
Test name
Test status
Simulation time 15424907 ps
CPU time 1.02 seconds
Started Jul 14 05:49:40 PM PDT 24
Finished Jul 14 05:49:42 PM PDT 24
Peak memory 210384 kb
Host smart-70ef8943-5eb9-4aba-a9ba-f0b2f8921d7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964990741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3964990741
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3228905854
Short name T913
Test name
Test status
Simulation time 67816710 ps
CPU time 1.45 seconds
Started Jul 14 05:49:42 PM PDT 24
Finished Jul 14 05:49:44 PM PDT 24
Peak memory 222552 kb
Host smart-263a6115-c094-4012-a13b-3355ce8eff22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228905854 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3228905854
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.903367868
Short name T972
Test name
Test status
Simulation time 14617092 ps
CPU time 1.09 seconds
Started Jul 14 05:49:40 PM PDT 24
Finished Jul 14 05:49:42 PM PDT 24
Peak memory 209060 kb
Host smart-e5c4db6a-ce33-44db-979c-702b92e97ef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903367868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.903367868
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2241693918
Short name T889
Test name
Test status
Simulation time 92746501 ps
CPU time 0.92 seconds
Started Jul 14 05:49:40 PM PDT 24
Finished Jul 14 05:49:41 PM PDT 24
Peak memory 209144 kb
Host smart-9fb36b76-2956-42ea-934e-94a6c00366d0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241693918 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2241693918
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1135788348
Short name T155
Test name
Test status
Simulation time 371408382 ps
CPU time 9.25 seconds
Started Jul 14 05:49:32 PM PDT 24
Finished Jul 14 05:49:42 PM PDT 24
Peak memory 217104 kb
Host smart-621bd72a-4e1a-4ee4-a3b9-3298debe3ea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135788348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1135788348
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1134273546
Short name T898
Test name
Test status
Simulation time 2197304044 ps
CPU time 8.43 seconds
Started Jul 14 05:49:36 PM PDT 24
Finished Jul 14 05:49:45 PM PDT 24
Peak memory 208988 kb
Host smart-28ad681e-9c00-4eee-bb34-46f538285111
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134273546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1134273546
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3582630184
Short name T960
Test name
Test status
Simulation time 254185858 ps
CPU time 1.45 seconds
Started Jul 14 05:49:34 PM PDT 24
Finished Jul 14 05:49:36 PM PDT 24
Peak memory 210280 kb
Host smart-18d5cb69-99c2-4c20-84d3-2af54718cb9b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582630184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3582630184
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3067183109
Short name T946
Test name
Test status
Simulation time 852352920 ps
CPU time 2.2 seconds
Started Jul 14 05:49:32 PM PDT 24
Finished Jul 14 05:49:35 PM PDT 24
Peak memory 217648 kb
Host smart-09d57dad-f5c3-4933-8e8f-5f3a7f28cb74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306718
3109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3067183109
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3100465916
Short name T131
Test name
Test status
Simulation time 308379131 ps
CPU time 2.62 seconds
Started Jul 14 05:49:33 PM PDT 24
Finished Jul 14 05:49:37 PM PDT 24
Peak memory 209228 kb
Host smart-9afba954-6c44-4ca0-bb7c-005025875d4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100465916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3100465916
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.19444195
Short name T897
Test name
Test status
Simulation time 39265708 ps
CPU time 1.28 seconds
Started Jul 14 05:49:38 PM PDT 24
Finished Jul 14 05:49:40 PM PDT 24
Peak memory 217512 kb
Host smart-baeda4d0-5202-4e66-aa34-752e426761fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19444195 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.19444195
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.392068411
Short name T978
Test name
Test status
Simulation time 43430384 ps
CPU time 0.96 seconds
Started Jul 14 05:49:38 PM PDT 24
Finished Jul 14 05:49:39 PM PDT 24
Peak memory 209084 kb
Host smart-7b7d2b56-f2c4-4ad0-b884-48c26744b0ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392068411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.392068411
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2473970467
Short name T892
Test name
Test status
Simulation time 85628051 ps
CPU time 2.49 seconds
Started Jul 14 05:49:41 PM PDT 24
Finished Jul 14 05:49:44 PM PDT 24
Peak memory 218608 kb
Host smart-92cf54f3-a862-4835-bb8c-7c3798073b46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473970467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2473970467
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3894872882
Short name T879
Test name
Test status
Simulation time 163391244 ps
CPU time 1.62 seconds
Started Jul 14 05:49:47 PM PDT 24
Finished Jul 14 05:49:49 PM PDT 24
Peak memory 209260 kb
Host smart-d716bdf3-afd0-454b-bd78-a1fc486756a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894872882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3894872882
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2916251473
Short name T923
Test name
Test status
Simulation time 99550375 ps
CPU time 2.15 seconds
Started Jul 14 05:49:49 PM PDT 24
Finished Jul 14 05:49:52 PM PDT 24
Peak memory 209228 kb
Host smart-1a0ed340-a084-445c-a9e5-dcfd961e02d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916251473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2916251473
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1319020206
Short name T212
Test name
Test status
Simulation time 39703211 ps
CPU time 1.27 seconds
Started Jul 14 05:49:39 PM PDT 24
Finished Jul 14 05:49:41 PM PDT 24
Peak memory 211532 kb
Host smart-6953e8ce-cd78-4f53-936f-08004c5625a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319020206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1319020206
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.33712765
Short name T125
Test name
Test status
Simulation time 57395492 ps
CPU time 1.36 seconds
Started Jul 14 05:49:47 PM PDT 24
Finished Jul 14 05:49:49 PM PDT 24
Peak memory 218644 kb
Host smart-d25094c2-bab5-49e5-8c6f-f06a8f00bcae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33712765 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.33712765
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.92171871
Short name T969
Test name
Test status
Simulation time 11666001 ps
CPU time 1 seconds
Started Jul 14 05:49:46 PM PDT 24
Finished Jul 14 05:49:47 PM PDT 24
Peak memory 209252 kb
Host smart-91ecfa83-f98d-41fc-bb69-66b43b724ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92171871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.92171871
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2019804703
Short name T884
Test name
Test status
Simulation time 165413117 ps
CPU time 1.26 seconds
Started Jul 14 05:49:41 PM PDT 24
Finished Jul 14 05:49:43 PM PDT 24
Peak memory 208624 kb
Host smart-7b63a6ba-3afd-4cc6-93e1-4bc37124b8be
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019804703 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2019804703
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2522940855
Short name T936
Test name
Test status
Simulation time 586047575 ps
CPU time 5.95 seconds
Started Jul 14 05:49:39 PM PDT 24
Finished Jul 14 05:49:46 PM PDT 24
Peak memory 208888 kb
Host smart-b4c01aa3-333f-42ef-ba83-c193ce776a6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522940855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2522940855
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.711127606
Short name T944
Test name
Test status
Simulation time 4377247635 ps
CPU time 12.43 seconds
Started Jul 14 05:49:40 PM PDT 24
Finished Jul 14 05:49:53 PM PDT 24
Peak memory 209304 kb
Host smart-20260ffe-2e70-48ca-b189-05ef82dbf170
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711127606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.711127606
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2117748480
Short name T920
Test name
Test status
Simulation time 2493830258 ps
CPU time 3.74 seconds
Started Jul 14 05:49:41 PM PDT 24
Finished Jul 14 05:49:45 PM PDT 24
Peak memory 210712 kb
Host smart-ec7b0d91-9c5d-4397-8a20-f41b2ff550ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117748480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2117748480
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.975017764
Short name T984
Test name
Test status
Simulation time 177824364 ps
CPU time 2.68 seconds
Started Jul 14 05:49:41 PM PDT 24
Finished Jul 14 05:49:44 PM PDT 24
Peak memory 218580 kb
Host smart-c8b16e3e-dde8-48dc-ac42-9daff50a1cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975017
764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.975017764
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3112757135
Short name T904
Test name
Test status
Simulation time 95421505 ps
CPU time 2.86 seconds
Started Jul 14 05:49:41 PM PDT 24
Finished Jul 14 05:49:44 PM PDT 24
Peak memory 217364 kb
Host smart-8ad1f55a-1007-4598-a1f5-d5efcbc2cb25
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112757135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3112757135
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.498210431
Short name T915
Test name
Test status
Simulation time 46215807 ps
CPU time 1.01 seconds
Started Jul 14 05:49:41 PM PDT 24
Finished Jul 14 05:49:42 PM PDT 24
Peak memory 209404 kb
Host smart-39b5e405-4c89-4271-9d57-d3ce3ddb2b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498210431 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.498210431
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2688437351
Short name T910
Test name
Test status
Simulation time 126135509 ps
CPU time 1.89 seconds
Started Jul 14 05:49:45 PM PDT 24
Finished Jul 14 05:49:48 PM PDT 24
Peak memory 217472 kb
Host smart-7c897d16-0ae0-4095-9acc-e2abd125d9ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688437351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2688437351
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3598847651
Short name T905
Test name
Test status
Simulation time 131538404 ps
CPU time 2.21 seconds
Started Jul 14 05:49:39 PM PDT 24
Finished Jul 14 05:49:42 PM PDT 24
Peak memory 218412 kb
Host smart-a4c3633d-2228-4b29-8fad-0186a5bcb0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598847651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3598847651
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1498568544
Short name T951
Test name
Test status
Simulation time 166816996 ps
CPU time 2.1 seconds
Started Jul 14 05:49:40 PM PDT 24
Finished Jul 14 05:49:43 PM PDT 24
Peak memory 221448 kb
Host smart-2c12525c-0f39-4b8b-91c2-13e2a6018bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498568544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1498568544
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2512194625
Short name T880
Test name
Test status
Simulation time 30837409 ps
CPU time 1.27 seconds
Started Jul 14 05:49:52 PM PDT 24
Finished Jul 14 05:49:53 PM PDT 24
Peak memory 209264 kb
Host smart-6931d976-0191-49b3-9891-b2c9f514aeb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512194625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2512194625
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1886529265
Short name T895
Test name
Test status
Simulation time 210126515 ps
CPU time 2.11 seconds
Started Jul 14 05:49:47 PM PDT 24
Finished Jul 14 05:49:49 PM PDT 24
Peak memory 209208 kb
Host smart-d680d1d8-32c6-4f7b-b087-5188071b4645
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886529265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1886529265
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1804503743
Short name T207
Test name
Test status
Simulation time 36452762 ps
CPU time 1.26 seconds
Started Jul 14 05:49:49 PM PDT 24
Finished Jul 14 05:49:51 PM PDT 24
Peak memory 211608 kb
Host smart-fd95a809-dc93-4c28-916c-5b8f8bbb2e36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804503743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1804503743
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2090531331
Short name T901
Test name
Test status
Simulation time 27178862 ps
CPU time 1.26 seconds
Started Jul 14 05:49:47 PM PDT 24
Finished Jul 14 05:49:49 PM PDT 24
Peak memory 221796 kb
Host smart-a10a5b72-1026-4347-879e-ce46d49f4002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090531331 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2090531331
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3373881787
Short name T887
Test name
Test status
Simulation time 13498746 ps
CPU time 1 seconds
Started Jul 14 05:49:49 PM PDT 24
Finished Jul 14 05:49:51 PM PDT 24
Peak memory 209220 kb
Host smart-04b0c8fd-caa4-4172-92da-c0c7f073d5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373881787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3373881787
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3067971675
Short name T891
Test name
Test status
Simulation time 154793040 ps
CPU time 1.36 seconds
Started Jul 14 05:49:49 PM PDT 24
Finished Jul 14 05:49:52 PM PDT 24
Peak memory 208788 kb
Host smart-b288c470-5e12-4dd9-b1c3-14520a3d56a8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067971675 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3067971675
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2977629392
Short name T991
Test name
Test status
Simulation time 595968323 ps
CPU time 3.8 seconds
Started Jul 14 05:49:46 PM PDT 24
Finished Jul 14 05:49:50 PM PDT 24
Peak memory 217008 kb
Host smart-70f18584-82ed-441e-80e4-a928ed62f076
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977629392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2977629392
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.963661517
Short name T883
Test name
Test status
Simulation time 4498537533 ps
CPU time 9.21 seconds
Started Jul 14 05:49:47 PM PDT 24
Finished Jul 14 05:49:56 PM PDT 24
Peak memory 209340 kb
Host smart-94c3c8fd-9339-4525-8e57-9c374bef855d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963661517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.963661517
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2606531222
Short name T932
Test name
Test status
Simulation time 70443713 ps
CPU time 1.46 seconds
Started Jul 14 05:49:48 PM PDT 24
Finished Jul 14 05:49:50 PM PDT 24
Peak memory 210632 kb
Host smart-78b3772c-bd84-4c12-bee9-653fed6b5510
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606531222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2606531222
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3801669926
Short name T938
Test name
Test status
Simulation time 60213612 ps
CPU time 1.61 seconds
Started Jul 14 05:49:49 PM PDT 24
Finished Jul 14 05:49:52 PM PDT 24
Peak memory 218924 kb
Host smart-18918dd2-27e3-4997-bda5-11ff3989395d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380166
9926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3801669926
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1729746097
Short name T988
Test name
Test status
Simulation time 252266112 ps
CPU time 1.95 seconds
Started Jul 14 05:49:48 PM PDT 24
Finished Jul 14 05:49:51 PM PDT 24
Peak memory 209228 kb
Host smart-2fffe976-62c5-4b3b-a636-e012c4339100
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729746097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1729746097
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1484309130
Short name T989
Test name
Test status
Simulation time 51685513 ps
CPU time 1.17 seconds
Started Jul 14 05:49:47 PM PDT 24
Finished Jul 14 05:49:49 PM PDT 24
Peak memory 217488 kb
Host smart-f0b47a8c-df92-464d-8446-73f277645f64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484309130 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1484309130
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2900446993
Short name T977
Test name
Test status
Simulation time 15895226 ps
CPU time 1.14 seconds
Started Jul 14 05:49:48 PM PDT 24
Finished Jul 14 05:49:50 PM PDT 24
Peak memory 209232 kb
Host smart-6f4c887c-fd5e-41e1-a696-dc8ff0a39362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900446993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2900446993
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1394674400
Short name T933
Test name
Test status
Simulation time 49612155 ps
CPU time 3.89 seconds
Started Jul 14 05:49:50 PM PDT 24
Finished Jul 14 05:49:54 PM PDT 24
Peak memory 218392 kb
Host smart-2d36b003-387e-48ea-b84d-7d9de4d9af41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394674400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1394674400
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2660571158
Short name T971
Test name
Test status
Simulation time 33938650 ps
CPU time 2.06 seconds
Started Jul 14 05:49:53 PM PDT 24
Finished Jul 14 05:49:56 PM PDT 24
Peak memory 219672 kb
Host smart-fc64bf5b-7a2e-4773-a58b-e6b040ce3844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660571158 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2660571158
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2752826294
Short name T213
Test name
Test status
Simulation time 19250278 ps
CPU time 0.92 seconds
Started Jul 14 05:49:57 PM PDT 24
Finished Jul 14 05:49:58 PM PDT 24
Peak memory 209056 kb
Host smart-7862b6c1-df10-4b5a-95e2-dd269aa91850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752826294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2752826294
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1582671906
Short name T921
Test name
Test status
Simulation time 68917766 ps
CPU time 0.89 seconds
Started Jul 14 05:49:56 PM PDT 24
Finished Jul 14 05:49:57 PM PDT 24
Peak memory 209104 kb
Host smart-c689519a-47df-45bc-845e-3625e28ff738
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582671906 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1582671906
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1104046598
Short name T956
Test name
Test status
Simulation time 702355167 ps
CPU time 3.84 seconds
Started Jul 14 05:49:49 PM PDT 24
Finished Jul 14 05:49:53 PM PDT 24
Peak memory 208900 kb
Host smart-e189633d-47cc-4baa-b2a2-147e885d2e48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104046598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1104046598
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1338999142
Short name T962
Test name
Test status
Simulation time 2968965406 ps
CPU time 7.13 seconds
Started Jul 14 05:49:49 PM PDT 24
Finished Jul 14 05:49:57 PM PDT 24
Peak memory 209292 kb
Host smart-7e02add4-8229-423d-a73f-f2f2af8e5bab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338999142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1338999142
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.433152110
Short name T965
Test name
Test status
Simulation time 45676657 ps
CPU time 1.29 seconds
Started Jul 14 05:49:48 PM PDT 24
Finished Jul 14 05:49:50 PM PDT 24
Peak memory 210620 kb
Host smart-994a3c01-c1e6-4db9-a0b5-8df124b187ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433152110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.433152110
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097072464
Short name T959
Test name
Test status
Simulation time 453019284 ps
CPU time 2.51 seconds
Started Jul 14 05:49:54 PM PDT 24
Finished Jul 14 05:49:57 PM PDT 24
Peak memory 219248 kb
Host smart-be87510d-24ee-4027-9465-dd058628dcf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209707
2464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097072464
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3334690993
Short name T983
Test name
Test status
Simulation time 238038550 ps
CPU time 2.06 seconds
Started Jul 14 05:49:49 PM PDT 24
Finished Jul 14 05:49:52 PM PDT 24
Peak memory 209228 kb
Host smart-552498f2-4856-4b58-a77b-4e7dae7298df
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334690993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3334690993
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4156336071
Short name T216
Test name
Test status
Simulation time 138513229 ps
CPU time 1.4 seconds
Started Jul 14 05:49:52 PM PDT 24
Finished Jul 14 05:49:54 PM PDT 24
Peak memory 217412 kb
Host smart-84d6d0c3-898d-4b7b-b5a5-bc1b80cee065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156336071 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4156336071
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2605670871
Short name T886
Test name
Test status
Simulation time 104151209 ps
CPU time 1.4 seconds
Started Jul 14 05:49:54 PM PDT 24
Finished Jul 14 05:49:57 PM PDT 24
Peak memory 209320 kb
Host smart-e610a8bf-7918-44f1-9fd1-4bf98e8c9384
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605670871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2605670871
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1703888260
Short name T145
Test name
Test status
Simulation time 103678622 ps
CPU time 1.88 seconds
Started Jul 14 05:49:54 PM PDT 24
Finished Jul 14 05:49:57 PM PDT 24
Peak memory 217600 kb
Host smart-8aea973c-a758-47b4-a040-e0cadeca51d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703888260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1703888260
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.962528729
Short name T128
Test name
Test status
Simulation time 59492966 ps
CPU time 1.91 seconds
Started Jul 14 05:49:53 PM PDT 24
Finished Jul 14 05:49:55 PM PDT 24
Peak memory 221736 kb
Host smart-f5dabfbb-23d4-4856-8f42-046c693d3dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962528729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.962528729
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2455601214
Short name T937
Test name
Test status
Simulation time 18766401 ps
CPU time 1.26 seconds
Started Jul 14 05:50:01 PM PDT 24
Finished Jul 14 05:50:03 PM PDT 24
Peak memory 217564 kb
Host smart-8668aef3-0b61-4bf9-90c5-9f3cb20bb078
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455601214 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2455601214
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3525931391
Short name T931
Test name
Test status
Simulation time 68542493 ps
CPU time 0.83 seconds
Started Jul 14 05:50:01 PM PDT 24
Finished Jul 14 05:50:02 PM PDT 24
Peak memory 209152 kb
Host smart-bc784c2d-8a08-4cb0-9b81-b77a52f5c11f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525931391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3525931391
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2945995334
Short name T929
Test name
Test status
Simulation time 217338887 ps
CPU time 1.82 seconds
Started Jul 14 05:49:54 PM PDT 24
Finished Jul 14 05:49:57 PM PDT 24
Peak memory 209148 kb
Host smart-c888e96d-470d-4efe-b868-d8e708e0e292
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945995334 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2945995334
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.362960805
Short name T871
Test name
Test status
Simulation time 1296364184 ps
CPU time 6.59 seconds
Started Jul 14 05:49:53 PM PDT 24
Finished Jul 14 05:50:00 PM PDT 24
Peak memory 208920 kb
Host smart-43bcfba7-3e5c-42cf-aba8-c9e369c7a7b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362960805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.362960805
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1061956772
Short name T872
Test name
Test status
Simulation time 701225106 ps
CPU time 18.63 seconds
Started Jul 14 05:49:53 PM PDT 24
Finished Jul 14 05:50:12 PM PDT 24
Peak memory 208908 kb
Host smart-2e0d4e3e-1e55-4f65-8262-3654c66a8ddb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061956772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1061956772
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.374194571
Short name T873
Test name
Test status
Simulation time 47764943 ps
CPU time 1.63 seconds
Started Jul 14 05:49:51 PM PDT 24
Finished Jul 14 05:49:53 PM PDT 24
Peak memory 217424 kb
Host smart-7370d22a-3798-4644-ba75-2414697e5e33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374194571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.374194571
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1519108700
Short name T922
Test name
Test status
Simulation time 84968344 ps
CPU time 1.77 seconds
Started Jul 14 05:49:53 PM PDT 24
Finished Jul 14 05:49:56 PM PDT 24
Peak memory 217216 kb
Host smart-f6a4cc2b-16f9-4085-9235-ecfbbe087c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519108700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1519108700
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3142704053
Short name T218
Test name
Test status
Simulation time 40957411 ps
CPU time 1.4 seconds
Started Jul 14 05:49:52 PM PDT 24
Finished Jul 14 05:49:54 PM PDT 24
Peak memory 211312 kb
Host smart-d33ff8f2-c80c-46f7-acbc-27b1c62575c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142704053 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3142704053
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1283506980
Short name T947
Test name
Test status
Simulation time 37551429 ps
CPU time 1.64 seconds
Started Jul 14 05:50:01 PM PDT 24
Finished Jul 14 05:50:03 PM PDT 24
Peak memory 217480 kb
Host smart-58960a59-7b18-459a-b5bc-ee7ec2498912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283506980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1283506980
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4066481087
Short name T987
Test name
Test status
Simulation time 161982158 ps
CPU time 2.98 seconds
Started Jul 14 05:50:00 PM PDT 24
Finished Jul 14 05:50:04 PM PDT 24
Peak memory 217772 kb
Host smart-b87a2166-a136-4cce-8a1a-5ab3994b692a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066481087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4066481087
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4285202007
Short name T149
Test name
Test status
Simulation time 44364188 ps
CPU time 1.79 seconds
Started Jul 14 05:50:00 PM PDT 24
Finished Jul 14 05:50:02 PM PDT 24
Peak memory 221128 kb
Host smart-ed50407b-88db-42da-a5c9-e349f9d71514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285202007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4285202007
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2411335876
Short name T985
Test name
Test status
Simulation time 68758812 ps
CPU time 1.65 seconds
Started Jul 14 05:50:09 PM PDT 24
Finished Jul 14 05:50:11 PM PDT 24
Peak memory 222256 kb
Host smart-75149d6a-72b9-46d2-991b-98888249def1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411335876 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2411335876
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2410481547
Short name T220
Test name
Test status
Simulation time 47397275 ps
CPU time 0.97 seconds
Started Jul 14 05:50:08 PM PDT 24
Finished Jul 14 05:50:09 PM PDT 24
Peak memory 209508 kb
Host smart-a2584db3-3bd7-4afe-bf0a-1ba787786668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410481547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2410481547
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3909675715
Short name T949
Test name
Test status
Simulation time 305273671 ps
CPU time 1.38 seconds
Started Jul 14 05:50:08 PM PDT 24
Finished Jul 14 05:50:10 PM PDT 24
Peak memory 209088 kb
Host smart-1d80291f-703d-40ee-b4e7-f4f00d0bcf2e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909675715 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3909675715
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.35284392
Short name T976
Test name
Test status
Simulation time 3982728775 ps
CPU time 8.88 seconds
Started Jul 14 05:50:00 PM PDT 24
Finished Jul 14 05:50:10 PM PDT 24
Peak memory 209204 kb
Host smart-cbe5d7a2-0eae-486f-ad4d-ed10bc0e9ea2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35284392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.lc_ctrl_jtag_csr_aliasing.35284392
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1643169029
Short name T902
Test name
Test status
Simulation time 4075041378 ps
CPU time 10.31 seconds
Started Jul 14 05:49:59 PM PDT 24
Finished Jul 14 05:50:10 PM PDT 24
Peak memory 209196 kb
Host smart-e9835afb-2faa-450d-9f42-cac6a2b74be5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643169029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1643169029
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2298796099
Short name T967
Test name
Test status
Simulation time 935690954 ps
CPU time 4.38 seconds
Started Jul 14 05:49:59 PM PDT 24
Finished Jul 14 05:50:03 PM PDT 24
Peak memory 210896 kb
Host smart-ad4a09a5-27e8-4885-bf5c-d9614d50234f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298796099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2298796099
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4222921612
Short name T942
Test name
Test status
Simulation time 501897158 ps
CPU time 4.1 seconds
Started Jul 14 05:50:00 PM PDT 24
Finished Jul 14 05:50:04 PM PDT 24
Peak memory 218604 kb
Host smart-81e47de6-a359-4558-b8c9-316c400d0944
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422292
1612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4222921612
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.707948080
Short name T950
Test name
Test status
Simulation time 131035077 ps
CPU time 3.1 seconds
Started Jul 14 05:50:00 PM PDT 24
Finished Jul 14 05:50:03 PM PDT 24
Peak memory 209112 kb
Host smart-f22d74b7-481a-424c-9a59-b35801b8c83a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707948080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.707948080
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2050775319
Short name T903
Test name
Test status
Simulation time 22848572 ps
CPU time 1.31 seconds
Started Jul 14 05:49:59 PM PDT 24
Finished Jul 14 05:50:01 PM PDT 24
Peak memory 209300 kb
Host smart-cc3cb487-1578-46f9-a4c6-22f322a72e17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050775319 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2050775319
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1714603466
Short name T136
Test name
Test status
Simulation time 18369960 ps
CPU time 1.07 seconds
Started Jul 14 05:50:07 PM PDT 24
Finished Jul 14 05:50:09 PM PDT 24
Peak memory 209316 kb
Host smart-553bb3cd-7bff-4c34-a213-73a7c62266a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714603466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1714603466
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3044587387
Short name T127
Test name
Test status
Simulation time 89112305 ps
CPU time 1.52 seconds
Started Jul 14 05:50:07 PM PDT 24
Finished Jul 14 05:50:09 PM PDT 24
Peak memory 217952 kb
Host smart-7ad529ad-ae2f-494e-850c-a3efc33324c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044587387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3044587387
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2563207891
Short name T993
Test name
Test status
Simulation time 64883578 ps
CPU time 1.03 seconds
Started Jul 14 05:50:15 PM PDT 24
Finished Jul 14 05:50:16 PM PDT 24
Peak memory 217544 kb
Host smart-b1632933-d783-4c50-9e3e-634511ee12a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563207891 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2563207891
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3827740830
Short name T169
Test name
Test status
Simulation time 26400133 ps
CPU time 0.96 seconds
Started Jul 14 05:50:16 PM PDT 24
Finished Jul 14 05:50:17 PM PDT 24
Peak memory 209180 kb
Host smart-e4ff7ea5-9ae0-44b0-b249-5588855d67c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827740830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3827740830
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.768758395
Short name T980
Test name
Test status
Simulation time 36341155 ps
CPU time 1.56 seconds
Started Jul 14 05:50:08 PM PDT 24
Finished Jul 14 05:50:10 PM PDT 24
Peak memory 209156 kb
Host smart-d3c301af-6c19-4c4b-8b31-998ac0738199
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768758395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.768758395
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2876997687
Short name T876
Test name
Test status
Simulation time 1478921102 ps
CPU time 4.11 seconds
Started Jul 14 05:50:09 PM PDT 24
Finished Jul 14 05:50:13 PM PDT 24
Peak memory 216948 kb
Host smart-19b5b7e9-abff-49da-b0b4-cf7ea00741cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876997687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2876997687
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3583803035
Short name T135
Test name
Test status
Simulation time 1113337971 ps
CPU time 10.97 seconds
Started Jul 14 05:50:09 PM PDT 24
Finished Jul 14 05:50:20 PM PDT 24
Peak memory 208964 kb
Host smart-afe34b79-223f-474f-ab4f-1c27f65b3c98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583803035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3583803035
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3485100709
Short name T156
Test name
Test status
Simulation time 440735465 ps
CPU time 3.61 seconds
Started Jul 14 05:50:07 PM PDT 24
Finished Jul 14 05:50:11 PM PDT 24
Peak memory 210912 kb
Host smart-538b7247-fe49-4418-89a8-897c4a5f54e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485100709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3485100709
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2916841721
Short name T979
Test name
Test status
Simulation time 135301609 ps
CPU time 4.25 seconds
Started Jul 14 05:50:07 PM PDT 24
Finished Jul 14 05:50:11 PM PDT 24
Peak memory 218352 kb
Host smart-b6611d1a-9064-4f6e-872d-d836225c44f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291684
1721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2916841721
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2170095151
Short name T908
Test name
Test status
Simulation time 411380735 ps
CPU time 3.32 seconds
Started Jul 14 05:50:08 PM PDT 24
Finished Jul 14 05:50:12 PM PDT 24
Peak memory 217280 kb
Host smart-1b7dd1f9-fa26-4a64-89c2-42ecaa0e76c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170095151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2170095151
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3671868477
Short name T926
Test name
Test status
Simulation time 47600093 ps
CPU time 1.4 seconds
Started Jul 14 05:50:10 PM PDT 24
Finished Jul 14 05:50:12 PM PDT 24
Peak memory 209392 kb
Host smart-eb0a2239-b440-4ae7-a09f-8c7c79135586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671868477 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3671868477
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2094004304
Short name T894
Test name
Test status
Simulation time 17595971 ps
CPU time 1.06 seconds
Started Jul 14 05:50:14 PM PDT 24
Finished Jul 14 05:50:16 PM PDT 24
Peak memory 209256 kb
Host smart-94fef71c-d5a2-4cd6-a294-fe87d339eed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094004304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2094004304
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1643325003
Short name T146
Test name
Test status
Simulation time 76817776 ps
CPU time 2.45 seconds
Started Jul 14 05:50:05 PM PDT 24
Finished Jul 14 05:50:08 PM PDT 24
Peak memory 218520 kb
Host smart-60b561c6-cd55-4925-a7a0-e099b63ed561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643325003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1643325003
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3568057190
Short name T140
Test name
Test status
Simulation time 255061174 ps
CPU time 2.97 seconds
Started Jul 14 05:50:15 PM PDT 24
Finished Jul 14 05:50:18 PM PDT 24
Peak memory 221852 kb
Host smart-cca09eff-daea-4838-9eb3-d49c7835bc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568057190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3568057190
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1120799631
Short name T917
Test name
Test status
Simulation time 89188276 ps
CPU time 1.61 seconds
Started Jul 14 05:50:22 PM PDT 24
Finished Jul 14 05:50:24 PM PDT 24
Peak memory 217572 kb
Host smart-170ddd2f-6b47-4c43-8fc9-6ffc3abbbd05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120799631 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1120799631
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3112758622
Short name T912
Test name
Test status
Simulation time 13697328 ps
CPU time 0.84 seconds
Started Jul 14 05:50:13 PM PDT 24
Finished Jul 14 05:50:15 PM PDT 24
Peak memory 208844 kb
Host smart-d7ba933c-bdb7-4c85-9129-fb0607c244cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112758622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3112758622
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2710685464
Short name T869
Test name
Test status
Simulation time 40220394 ps
CPU time 1.16 seconds
Started Jul 14 05:50:13 PM PDT 24
Finished Jul 14 05:50:14 PM PDT 24
Peak memory 209140 kb
Host smart-3410ce92-a9eb-4c05-862f-b7fd8d4f3d62
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710685464 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2710685464
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3367914212
Short name T948
Test name
Test status
Simulation time 5192545141 ps
CPU time 7.94 seconds
Started Jul 14 05:50:14 PM PDT 24
Finished Jul 14 05:50:23 PM PDT 24
Peak memory 217292 kb
Host smart-d345968b-d338-44dd-a7bf-f264d0f588c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367914212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3367914212
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1937153809
Short name T952
Test name
Test status
Simulation time 488358256 ps
CPU time 5.84 seconds
Started Jul 14 05:50:13 PM PDT 24
Finished Jul 14 05:50:19 PM PDT 24
Peak memory 208964 kb
Host smart-eaa65cb2-8c29-4c6f-b7a0-c4f31882ef86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937153809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1937153809
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3213745676
Short name T911
Test name
Test status
Simulation time 194928331 ps
CPU time 1.87 seconds
Started Jul 14 05:50:16 PM PDT 24
Finished Jul 14 05:50:19 PM PDT 24
Peak memory 217396 kb
Host smart-0957ea21-229b-4641-8154-a1664f164fe7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213745676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3213745676
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.379179785
Short name T882
Test name
Test status
Simulation time 104261555 ps
CPU time 2.56 seconds
Started Jul 14 05:50:14 PM PDT 24
Finished Jul 14 05:50:17 PM PDT 24
Peak memory 217568 kb
Host smart-6b17a509-b2fc-46e9-8338-6a902509fc97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379179
785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.379179785
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3606144114
Short name T964
Test name
Test status
Simulation time 222421425 ps
CPU time 1.17 seconds
Started Jul 14 05:50:16 PM PDT 24
Finished Jul 14 05:50:18 PM PDT 24
Peak memory 209308 kb
Host smart-be56caca-3356-467d-9dbd-5d0afac1e41a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606144114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3606144114
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.631730471
Short name T934
Test name
Test status
Simulation time 39473708 ps
CPU time 1.22 seconds
Started Jul 14 05:50:14 PM PDT 24
Finished Jul 14 05:50:16 PM PDT 24
Peak memory 211416 kb
Host smart-29d14d1d-04cf-4b9e-8143-0c2fbc4e766e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631730471 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.631730471
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2257088604
Short name T961
Test name
Test status
Simulation time 68637153 ps
CPU time 1.31 seconds
Started Jul 14 05:50:23 PM PDT 24
Finished Jul 14 05:50:25 PM PDT 24
Peak memory 209296 kb
Host smart-c098922a-cf03-4b51-be0e-0c2dfd13694f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257088604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2257088604
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4023375838
Short name T896
Test name
Test status
Simulation time 194396428 ps
CPU time 2.71 seconds
Started Jul 14 05:50:14 PM PDT 24
Finished Jul 14 05:50:17 PM PDT 24
Peak memory 217448 kb
Host smart-1b143134-f47e-488b-98c4-256df76bf0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023375838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4023375838
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2574170671
Short name T143
Test name
Test status
Simulation time 131351207 ps
CPU time 2.81 seconds
Started Jul 14 05:50:15 PM PDT 24
Finished Jul 14 05:50:18 PM PDT 24
Peak memory 221812 kb
Host smart-bf39dc7b-4650-40fd-b9d9-61e26c6c996e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574170671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2574170671
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.4221579663
Short name T343
Test name
Test status
Simulation time 24691013 ps
CPU time 0.95 seconds
Started Jul 14 06:20:33 PM PDT 24
Finished Jul 14 06:20:35 PM PDT 24
Peak memory 208968 kb
Host smart-607bc55a-d92b-460b-a3f1-e0bf92f503e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221579663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.4221579663
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2390912990
Short name T580
Test name
Test status
Simulation time 1274181897 ps
CPU time 12.18 seconds
Started Jul 14 06:20:24 PM PDT 24
Finished Jul 14 06:20:36 PM PDT 24
Peak memory 218120 kb
Host smart-7e653b37-ee7d-4842-a5e6-a403a5bf7981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390912990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2390912990
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2970772133
Short name T487
Test name
Test status
Simulation time 481233830 ps
CPU time 3.57 seconds
Started Jul 14 06:20:23 PM PDT 24
Finished Jul 14 06:20:27 PM PDT 24
Peak memory 217280 kb
Host smart-a6d4e39f-a61f-4689-9799-2fb23b0b1961
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970772133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2970772133
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2497481254
Short name T541
Test name
Test status
Simulation time 10621665659 ps
CPU time 33.74 seconds
Started Jul 14 06:20:24 PM PDT 24
Finished Jul 14 06:20:58 PM PDT 24
Peak memory 218936 kb
Host smart-c04d058d-8499-43db-976b-77e93c2bc236
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497481254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2497481254
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2820294332
Short name T608
Test name
Test status
Simulation time 190289745 ps
CPU time 5.52 seconds
Started Jul 14 06:20:26 PM PDT 24
Finished Jul 14 06:20:32 PM PDT 24
Peak memory 217668 kb
Host smart-0c1d7b3b-f460-4d8d-8c11-47c247378386
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820294332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
820294332
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2746509720
Short name T747
Test name
Test status
Simulation time 555710574 ps
CPU time 7.17 seconds
Started Jul 14 06:20:23 PM PDT 24
Finished Jul 14 06:20:30 PM PDT 24
Peak memory 218232 kb
Host smart-5827fbd0-8a73-409a-aad7-6a77b1bdefeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746509720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2746509720
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3537665972
Short name T63
Test name
Test status
Simulation time 2050804475 ps
CPU time 28.17 seconds
Started Jul 14 06:20:22 PM PDT 24
Finished Jul 14 06:20:51 PM PDT 24
Peak memory 217684 kb
Host smart-cad3f898-e444-4ad8-af5c-d02566b197f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537665972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3537665972
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3562625585
Short name T688
Test name
Test status
Simulation time 233681840 ps
CPU time 2.62 seconds
Started Jul 14 06:20:25 PM PDT 24
Finished Jul 14 06:20:28 PM PDT 24
Peak memory 217812 kb
Host smart-8ab265d0-1b6e-47d6-8488-d76d79cfb1ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562625585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3562625585
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1681888762
Short name T321
Test name
Test status
Simulation time 1694528053 ps
CPU time 61.19 seconds
Started Jul 14 06:20:26 PM PDT 24
Finished Jul 14 06:21:27 PM PDT 24
Peak memory 268164 kb
Host smart-a6f97d79-88de-4979-a264-e3757d80d644
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681888762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1681888762
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.707063209
Short name T770
Test name
Test status
Simulation time 469098321 ps
CPU time 3.71 seconds
Started Jul 14 06:20:23 PM PDT 24
Finished Jul 14 06:20:27 PM PDT 24
Peak memory 222612 kb
Host smart-f974cb6d-2d7f-44b6-bed7-4c39c87b40e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707063209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.707063209
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3524452135
Short name T579
Test name
Test status
Simulation time 3517525943 ps
CPU time 14.18 seconds
Started Jul 14 06:20:27 PM PDT 24
Finished Jul 14 06:20:42 PM PDT 24
Peak memory 217732 kb
Host smart-b57c5a0a-280a-4d00-b59a-e1371b4f7a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524452135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3524452135
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1967590251
Short name T50
Test name
Test status
Simulation time 2972063424 ps
CPU time 37.32 seconds
Started Jul 14 06:20:33 PM PDT 24
Finished Jul 14 06:21:11 PM PDT 24
Peak memory 270156 kb
Host smart-ddb55177-9cd1-479a-af80-39855e85537a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967590251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1967590251
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2197861494
Short name T238
Test name
Test status
Simulation time 847139403 ps
CPU time 14.45 seconds
Started Jul 14 06:20:33 PM PDT 24
Finished Jul 14 06:20:48 PM PDT 24
Peak memory 226020 kb
Host smart-1f64f6fe-b7a0-4e11-ba43-2a1aef06f15d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197861494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2197861494
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2605211962
Short name T162
Test name
Test status
Simulation time 352034552 ps
CPU time 5.82 seconds
Started Jul 14 06:20:22 PM PDT 24
Finished Jul 14 06:20:28 PM PDT 24
Peak memory 218124 kb
Host smart-89962ac7-72b2-4a06-8c8d-e04fc9b9b8c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605211962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
605211962
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2757303691
Short name T571
Test name
Test status
Simulation time 1116835653 ps
CPU time 10.9 seconds
Started Jul 14 06:20:26 PM PDT 24
Finished Jul 14 06:20:37 PM PDT 24
Peak memory 218304 kb
Host smart-8e6eb437-2985-44b8-8ffe-5621fa5e5977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757303691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2757303691
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.648796767
Short name T867
Test name
Test status
Simulation time 74643904 ps
CPU time 2.55 seconds
Started Jul 14 06:20:24 PM PDT 24
Finished Jul 14 06:20:27 PM PDT 24
Peak memory 217676 kb
Host smart-9452e2f1-871e-4120-839f-df10140cb13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648796767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.648796767
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2665359918
Short name T389
Test name
Test status
Simulation time 1379329053 ps
CPU time 24.19 seconds
Started Jul 14 06:20:23 PM PDT 24
Finished Jul 14 06:20:47 PM PDT 24
Peak memory 250956 kb
Host smart-23f146d5-cc35-4c9d-806e-93dbccaa5acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665359918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2665359918
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1969179107
Short name T419
Test name
Test status
Simulation time 221677805 ps
CPU time 6.49 seconds
Started Jul 14 06:20:26 PM PDT 24
Finished Jul 14 06:20:33 PM PDT 24
Peak memory 246524 kb
Host smart-be1c817a-8399-4468-bb7e-5107edc38518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969179107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1969179107
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.670660771
Short name T292
Test name
Test status
Simulation time 66607060 ps
CPU time 0.93 seconds
Started Jul 14 06:20:24 PM PDT 24
Finished Jul 14 06:20:25 PM PDT 24
Peak memory 211872 kb
Host smart-d3162af2-09ea-4e52-97fd-fcb7bc9a6d9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670660771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.670660771
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2996675276
Short name T753
Test name
Test status
Simulation time 34300073 ps
CPU time 1.15 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:41 PM PDT 24
Peak memory 209068 kb
Host smart-ff251597-d62a-47e2-8535-7bf6a05cdf01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996675276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2996675276
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1950068383
Short name T116
Test name
Test status
Simulation time 565702787 ps
CPU time 11.78 seconds
Started Jul 14 06:20:33 PM PDT 24
Finished Jul 14 06:20:45 PM PDT 24
Peak memory 218208 kb
Host smart-34db5ce4-3497-43b6-8d8b-c065e5768484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950068383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1950068383
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3917897393
Short name T785
Test name
Test status
Simulation time 1786062365 ps
CPU time 2.64 seconds
Started Jul 14 06:20:35 PM PDT 24
Finished Jul 14 06:20:38 PM PDT 24
Peak memory 217328 kb
Host smart-606706f5-ec38-4d6c-be00-d473b726a5c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917897393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3917897393
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3210740834
Short name T842
Test name
Test status
Simulation time 13875351652 ps
CPU time 94.29 seconds
Started Jul 14 06:20:33 PM PDT 24
Finished Jul 14 06:22:07 PM PDT 24
Peak memory 226028 kb
Host smart-e8bb82a0-4d71-4730-9c22-1b184fe6185e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210740834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3210740834
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1607142959
Short name T514
Test name
Test status
Simulation time 368987147 ps
CPU time 2.66 seconds
Started Jul 14 06:20:32 PM PDT 24
Finished Jul 14 06:20:35 PM PDT 24
Peak memory 217796 kb
Host smart-6306bcb8-a2ff-4cc0-b74c-1341b68c6aa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607142959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
607142959
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.162304707
Short name T175
Test name
Test status
Simulation time 1496794906 ps
CPU time 14.86 seconds
Started Jul 14 06:20:32 PM PDT 24
Finished Jul 14 06:20:47 PM PDT 24
Peak memory 224392 kb
Host smart-98513e6a-ab05-4460-b09e-20a8e1574fd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162304707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.162304707
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1468822582
Short name T596
Test name
Test status
Simulation time 6177005714 ps
CPU time 35.73 seconds
Started Jul 14 06:20:46 PM PDT 24
Finished Jul 14 06:21:22 PM PDT 24
Peak memory 217660 kb
Host smart-4f9fa35a-b816-48cc-a17e-21fb7080d54c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468822582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1468822582
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3301658445
Short name T66
Test name
Test status
Simulation time 712713308 ps
CPU time 9.79 seconds
Started Jul 14 06:20:33 PM PDT 24
Finished Jul 14 06:20:43 PM PDT 24
Peak memory 217616 kb
Host smart-78fe3862-1005-4b21-8b6b-51d1833a6681
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301658445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3301658445
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1097683562
Short name T775
Test name
Test status
Simulation time 1894669325 ps
CPU time 73.98 seconds
Started Jul 14 06:20:34 PM PDT 24
Finished Jul 14 06:21:48 PM PDT 24
Peak memory 267276 kb
Host smart-2f55f37b-c126-475e-a996-277659557bee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097683562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1097683562
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3329032825
Short name T466
Test name
Test status
Simulation time 972956110 ps
CPU time 12.73 seconds
Started Jul 14 06:20:35 PM PDT 24
Finished Jul 14 06:20:48 PM PDT 24
Peak memory 250532 kb
Host smart-d19d09bb-817a-4b64-ba3e-80342ce0be8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329032825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3329032825
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.478206083
Short name T710
Test name
Test status
Simulation time 89742105 ps
CPU time 3.05 seconds
Started Jul 14 06:20:34 PM PDT 24
Finished Jul 14 06:20:37 PM PDT 24
Peak memory 218108 kb
Host smart-cb835bee-d64e-4c7a-9c47-4189640ff342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478206083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.478206083
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3652811750
Short name T838
Test name
Test status
Simulation time 390576478 ps
CPU time 20.61 seconds
Started Jul 14 06:20:33 PM PDT 24
Finished Jul 14 06:20:54 PM PDT 24
Peak memory 217732 kb
Host smart-3eace8b9-df57-45a2-9d85-6f6d2da3f1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652811750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3652811750
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.154560930
Short name T599
Test name
Test status
Simulation time 630032811 ps
CPU time 15.82 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:59 PM PDT 24
Peak memory 226036 kb
Host smart-01b5ea06-dff1-419b-bf14-e5ef95beb059
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154560930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.154560930
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.714174263
Short name T432
Test name
Test status
Simulation time 2648202194 ps
CPU time 11.8 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:53 PM PDT 24
Peak memory 226048 kb
Host smart-2d6d69ce-c32d-411b-a347-49b8fc8e3a6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714174263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.714174263
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2729891275
Short name T702
Test name
Test status
Simulation time 2226502080 ps
CPU time 11.75 seconds
Started Jul 14 06:20:43 PM PDT 24
Finished Jul 14 06:20:56 PM PDT 24
Peak memory 226048 kb
Host smart-d05620b8-72f8-493e-8bce-f79b1c9f490c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729891275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
729891275
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1222938856
Short name T452
Test name
Test status
Simulation time 3062037366 ps
CPU time 9.27 seconds
Started Jul 14 06:20:34 PM PDT 24
Finished Jul 14 06:20:44 PM PDT 24
Peak memory 218412 kb
Host smart-c5500b6b-3a18-4518-93f3-6fd1b8f43838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222938856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1222938856
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.473008514
Short name T689
Test name
Test status
Simulation time 143490958 ps
CPU time 2.7 seconds
Started Jul 14 06:20:35 PM PDT 24
Finished Jul 14 06:20:38 PM PDT 24
Peak memory 214572 kb
Host smart-c72ddf8e-b4b4-4dbc-aa5a-32c6152a49d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473008514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.473008514
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3787517378
Short name T458
Test name
Test status
Simulation time 1236721978 ps
CPU time 37.32 seconds
Started Jul 14 06:20:35 PM PDT 24
Finished Jul 14 06:21:13 PM PDT 24
Peak memory 250972 kb
Host smart-6de82736-0a1c-4b1a-9ed5-4bd06f87cf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787517378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3787517378
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3725492611
Short name T577
Test name
Test status
Simulation time 285742123 ps
CPU time 7.11 seconds
Started Jul 14 06:20:34 PM PDT 24
Finished Jul 14 06:20:42 PM PDT 24
Peak memory 250308 kb
Host smart-c84674e4-626c-4967-9adf-6566fd6be750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725492611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3725492611
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4100681217
Short name T711
Test name
Test status
Simulation time 6718167110 ps
CPU time 99.24 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:22:23 PM PDT 24
Peak memory 275480 kb
Host smart-ca175332-984b-42e2-9c9c-7ec44f7caa26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100681217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4100681217
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2985763961
Short name T357
Test name
Test status
Simulation time 183234695 ps
CPU time 0.95 seconds
Started Jul 14 06:20:32 PM PDT 24
Finished Jul 14 06:20:33 PM PDT 24
Peak memory 211988 kb
Host smart-db7ffe56-45d8-4bf8-8fd3-60dad065e75e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985763961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2985763961
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.82545203
Short name T372
Test name
Test status
Simulation time 43067980 ps
CPU time 1.09 seconds
Started Jul 14 06:21:30 PM PDT 24
Finished Jul 14 06:21:32 PM PDT 24
Peak memory 208980 kb
Host smart-e4e55cf9-fbd1-4cc0-8067-4fd621a32176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82545203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.82545203
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2546662308
Short name T474
Test name
Test status
Simulation time 5327244779 ps
CPU time 12.42 seconds
Started Jul 14 06:21:21 PM PDT 24
Finished Jul 14 06:21:34 PM PDT 24
Peak memory 218244 kb
Host smart-34846bf0-d54b-4ca2-9806-3c0776512b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546662308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2546662308
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1190294082
Short name T417
Test name
Test status
Simulation time 472944350 ps
CPU time 4.95 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:21:31 PM PDT 24
Peak memory 217068 kb
Host smart-7ca4e83f-a653-45a4-aeb2-9ee762a06416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190294082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1190294082
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3597869158
Short name T45
Test name
Test status
Simulation time 4824179070 ps
CPU time 59.45 seconds
Started Jul 14 06:21:22 PM PDT 24
Finished Jul 14 06:22:22 PM PDT 24
Peak memory 226024 kb
Host smart-5fc1ed1f-5b43-4f1c-ba03-314afdf4e375
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597869158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3597869158
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3709162871
Short name T191
Test name
Test status
Simulation time 350843886 ps
CPU time 11.36 seconds
Started Jul 14 06:21:22 PM PDT 24
Finished Jul 14 06:21:34 PM PDT 24
Peak memory 223252 kb
Host smart-94bb4e41-af9b-411b-8727-d9bbb9bae48c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709162871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3709162871
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3153438418
Short name T438
Test name
Test status
Simulation time 2255973480 ps
CPU time 7.3 seconds
Started Jul 14 06:21:21 PM PDT 24
Finished Jul 14 06:21:29 PM PDT 24
Peak memory 217684 kb
Host smart-7776f01b-9505-4b84-97c2-0a36af548e53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153438418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3153438418
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1944540929
Short name T400
Test name
Test status
Simulation time 6335616628 ps
CPU time 58.23 seconds
Started Jul 14 06:21:24 PM PDT 24
Finished Jul 14 06:22:23 PM PDT 24
Peak memory 274048 kb
Host smart-7a365594-a187-4368-85b8-d35f0413dec9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944540929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1944540929
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3522724770
Short name T854
Test name
Test status
Simulation time 2780832151 ps
CPU time 16.43 seconds
Started Jul 14 06:21:23 PM PDT 24
Finished Jul 14 06:21:40 PM PDT 24
Peak memory 251008 kb
Host smart-e1f2e0b4-4f0e-48aa-9bfb-f5f38db1f486
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522724770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3522724770
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1024203746
Short name T312
Test name
Test status
Simulation time 147715993 ps
CPU time 3.53 seconds
Started Jul 14 06:21:20 PM PDT 24
Finished Jul 14 06:21:24 PM PDT 24
Peak memory 218192 kb
Host smart-a1a4e83f-9de8-4b9c-a075-b1fdcbecd31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024203746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1024203746
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2526713990
Short name T723
Test name
Test status
Simulation time 1055253715 ps
CPU time 15.87 seconds
Started Jul 14 06:21:26 PM PDT 24
Finished Jul 14 06:21:43 PM PDT 24
Peak memory 226000 kb
Host smart-c273f20b-7704-48a9-a7dd-90679fa26557
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526713990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2526713990
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2369243357
Short name T728
Test name
Test status
Simulation time 711770829 ps
CPU time 8.96 seconds
Started Jul 14 06:21:28 PM PDT 24
Finished Jul 14 06:21:38 PM PDT 24
Peak memory 218344 kb
Host smart-dc09f8d1-5e8a-4701-aa6a-674b2493e8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369243357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2369243357
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.142198266
Short name T790
Test name
Test status
Simulation time 621017040 ps
CPU time 8.86 seconds
Started Jul 14 06:21:24 PM PDT 24
Finished Jul 14 06:21:34 PM PDT 24
Peak memory 218268 kb
Host smart-d1e49a8d-0314-4e0a-b223-e1bf93f122dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142198266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.142198266
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1384534881
Short name T555
Test name
Test status
Simulation time 332093287 ps
CPU time 3.4 seconds
Started Jul 14 06:21:23 PM PDT 24
Finished Jul 14 06:21:27 PM PDT 24
Peak memory 217628 kb
Host smart-4ae395c2-0590-4249-946a-d1f349c2c11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384534881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1384534881
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.4219793171
Short name T831
Test name
Test status
Simulation time 195298842 ps
CPU time 20.32 seconds
Started Jul 14 06:21:21 PM PDT 24
Finished Jul 14 06:21:42 PM PDT 24
Peak memory 250960 kb
Host smart-597e7a45-9bf4-4ec9-bd4b-719b2285c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219793171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4219793171
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.20059908
Short name T426
Test name
Test status
Simulation time 1369539257 ps
CPU time 7.18 seconds
Started Jul 14 06:21:21 PM PDT 24
Finished Jul 14 06:21:29 PM PDT 24
Peak memory 250488 kb
Host smart-18a7d72a-ee81-4bd0-897c-18a7bc2cb550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20059908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.20059908
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1492429520
Short name T641
Test name
Test status
Simulation time 3744052130 ps
CPU time 48.31 seconds
Started Jul 14 06:21:28 PM PDT 24
Finished Jul 14 06:22:17 PM PDT 24
Peak memory 267732 kb
Host smart-78a12f77-641a-4156-ace5-18764e60daf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492429520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1492429520
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2628737551
Short name T346
Test name
Test status
Simulation time 25343623 ps
CPU time 0.86 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:21:26 PM PDT 24
Peak memory 217684 kb
Host smart-b90fef6d-996f-4d20-9624-bb63372310ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628737551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2628737551
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.450747297
Short name T729
Test name
Test status
Simulation time 30646685 ps
CPU time 1.11 seconds
Started Jul 14 06:21:27 PM PDT 24
Finished Jul 14 06:21:29 PM PDT 24
Peak memory 208980 kb
Host smart-1dbc4440-9d9d-4016-900c-3af892f42183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450747297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.450747297
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.500585033
Short name T295
Test name
Test status
Simulation time 371021614 ps
CPU time 13.29 seconds
Started Jul 14 06:21:30 PM PDT 24
Finished Jul 14 06:21:44 PM PDT 24
Peak memory 218172 kb
Host smart-5cf92929-5320-4986-9863-911db2d0950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500585033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.500585033
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1396537227
Short name T28
Test name
Test status
Simulation time 1587651102 ps
CPU time 4.33 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:21:29 PM PDT 24
Peak memory 217432 kb
Host smart-70bceec5-76c6-45ff-b458-9d9c6f24ff65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396537227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1396537227
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1009652308
Short name T847
Test name
Test status
Simulation time 5207085465 ps
CPU time 63.88 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 218936 kb
Host smart-42e86d17-ac01-4942-aa16-3d962d0e69ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009652308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1009652308
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4059254377
Short name T94
Test name
Test status
Simulation time 725424748 ps
CPU time 6.11 seconds
Started Jul 14 06:21:26 PM PDT 24
Finished Jul 14 06:21:33 PM PDT 24
Peak memory 221796 kb
Host smart-d329b431-3ca0-45c0-bded-cedc1a2c69a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059254377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4059254377
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3096467497
Short name T502
Test name
Test status
Simulation time 304036334 ps
CPU time 3.85 seconds
Started Jul 14 06:21:28 PM PDT 24
Finished Jul 14 06:21:33 PM PDT 24
Peak memory 217640 kb
Host smart-a36a8a2d-fb21-441f-acf9-f712ef4ada17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096467497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3096467497
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3353553978
Short name T531
Test name
Test status
Simulation time 1221844944 ps
CPU time 44.79 seconds
Started Jul 14 06:21:26 PM PDT 24
Finished Jul 14 06:22:11 PM PDT 24
Peak memory 250896 kb
Host smart-0e70abd1-7913-4441-aed3-5cdee4c05045
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353553978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3353553978
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2779313856
Short name T299
Test name
Test status
Simulation time 1513219350 ps
CPU time 10.5 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:21:36 PM PDT 24
Peak memory 248800 kb
Host smart-cc29d780-943f-4753-b12d-dbce335a2297
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779313856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2779313856
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3650481771
Short name T773
Test name
Test status
Simulation time 50252386 ps
CPU time 2.98 seconds
Started Jul 14 06:21:28 PM PDT 24
Finished Jul 14 06:21:32 PM PDT 24
Peak memory 218220 kb
Host smart-126f17f5-d40c-4b96-8a95-33ed1971db7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650481771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3650481771
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1155013103
Short name T178
Test name
Test status
Simulation time 1559024790 ps
CPU time 10.94 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:21:37 PM PDT 24
Peak memory 226032 kb
Host smart-86ae837f-a66f-45f6-a90c-0e908ed18a07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155013103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1155013103
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.408605341
Short name T352
Test name
Test status
Simulation time 248442927 ps
CPU time 6.18 seconds
Started Jul 14 06:21:30 PM PDT 24
Finished Jul 14 06:21:37 PM PDT 24
Peak memory 226036 kb
Host smart-47e000f8-03fb-4cd5-b9ed-2c83583d6c70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408605341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.408605341
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3293488943
Short name T119
Test name
Test status
Simulation time 1082787529 ps
CPU time 8.21 seconds
Started Jul 14 06:21:28 PM PDT 24
Finished Jul 14 06:21:37 PM PDT 24
Peak memory 226036 kb
Host smart-08df59ce-ff30-42e4-9a4c-8e6aff168ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293488943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3293488943
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3425386906
Short name T529
Test name
Test status
Simulation time 59807408 ps
CPU time 2.06 seconds
Started Jul 14 06:21:27 PM PDT 24
Finished Jul 14 06:21:30 PM PDT 24
Peak memory 217616 kb
Host smart-69a3c75c-8cf3-48d4-ae7c-096f752a1569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425386906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3425386906
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4232943698
Short name T696
Test name
Test status
Simulation time 573240686 ps
CPU time 24.4 seconds
Started Jul 14 06:21:26 PM PDT 24
Finished Jul 14 06:21:52 PM PDT 24
Peak memory 251052 kb
Host smart-9191fa13-0879-44e3-a0a9-3704a34ead5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232943698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4232943698
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2567676625
Short name T324
Test name
Test status
Simulation time 99095908 ps
CPU time 7.15 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:21:33 PM PDT 24
Peak memory 250572 kb
Host smart-32ad2321-09b0-46a6-bf55-987c79b3c66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567676625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2567676625
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.551303202
Short name T64
Test name
Test status
Simulation time 12309845509 ps
CPU time 91.76 seconds
Started Jul 14 06:21:27 PM PDT 24
Finished Jul 14 06:23:00 PM PDT 24
Peak memory 217800 kb
Host smart-98a16907-436f-4150-ba6f-fed96f5a5f40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551303202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.551303202
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3744144551
Short name T296
Test name
Test status
Simulation time 116373359 ps
CPU time 0.81 seconds
Started Jul 14 06:21:26 PM PDT 24
Finished Jul 14 06:21:28 PM PDT 24
Peak memory 211848 kb
Host smart-0812f3c4-0c81-472d-b9c6-50f71cd45751
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744144551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3744144551
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.816562125
Short name T471
Test name
Test status
Simulation time 20826795 ps
CPU time 1.17 seconds
Started Jul 14 06:21:34 PM PDT 24
Finished Jul 14 06:21:37 PM PDT 24
Peak memory 208876 kb
Host smart-79369c11-0bd7-4e2b-bd04-5e9b80c3f84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816562125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.816562125
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3560921723
Short name T802
Test name
Test status
Simulation time 606500120 ps
CPU time 10.77 seconds
Started Jul 14 06:21:37 PM PDT 24
Finished Jul 14 06:21:49 PM PDT 24
Peak memory 226032 kb
Host smart-83418f50-523a-4ebe-8c0a-49732a6e0237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560921723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3560921723
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1843680631
Short name T107
Test name
Test status
Simulation time 1266684101 ps
CPU time 7.33 seconds
Started Jul 14 06:21:33 PM PDT 24
Finished Jul 14 06:21:41 PM PDT 24
Peak memory 217148 kb
Host smart-1436b61a-c7c8-4d23-bfe2-676077decf5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843680631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1843680631
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2178969612
Short name T165
Test name
Test status
Simulation time 1475863292 ps
CPU time 42.01 seconds
Started Jul 14 06:21:34 PM PDT 24
Finished Jul 14 06:22:17 PM PDT 24
Peak memory 218252 kb
Host smart-1543b652-7db6-49cf-a491-80fc54c186c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178969612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2178969612
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.171655051
Short name T866
Test name
Test status
Simulation time 468526135 ps
CPU time 8.91 seconds
Started Jul 14 06:21:34 PM PDT 24
Finished Jul 14 06:21:44 PM PDT 24
Peak memory 218248 kb
Host smart-76ce3490-5a11-4ea0-840e-403d00088fb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171655051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.171655051
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2910714368
Short name T336
Test name
Test status
Simulation time 1689493282 ps
CPU time 5.11 seconds
Started Jul 14 06:21:33 PM PDT 24
Finished Jul 14 06:21:39 PM PDT 24
Peak memory 217716 kb
Host smart-4d76fd0f-e3fb-4d9e-88bc-5cf8b6e05de6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910714368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2910714368
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3880018470
Short name T706
Test name
Test status
Simulation time 1157936223 ps
CPU time 30.03 seconds
Started Jul 14 06:21:34 PM PDT 24
Finished Jul 14 06:22:05 PM PDT 24
Peak memory 250960 kb
Host smart-19e6c99b-dcba-40df-96b6-3b61407248d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880018470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3880018470
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3907810452
Short name T664
Test name
Test status
Simulation time 401787273 ps
CPU time 15.11 seconds
Started Jul 14 06:21:37 PM PDT 24
Finished Jul 14 06:21:53 PM PDT 24
Peak memory 251000 kb
Host smart-dd128902-3def-4af8-b55a-d6b691246283
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907810452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3907810452
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.561863518
Short name T827
Test name
Test status
Simulation time 142590069 ps
CPU time 2.49 seconds
Started Jul 14 06:21:34 PM PDT 24
Finished Jul 14 06:21:38 PM PDT 24
Peak memory 218216 kb
Host smart-645c8233-65b5-4611-9d91-a05b07fb2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561863518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.561863518
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2789537803
Short name T37
Test name
Test status
Simulation time 2744986022 ps
CPU time 26.04 seconds
Started Jul 14 06:21:36 PM PDT 24
Finished Jul 14 06:22:03 PM PDT 24
Peak memory 226072 kb
Host smart-742782b1-a7e1-4876-af5e-7e6d80c20dbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789537803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2789537803
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3875826501
Short name T544
Test name
Test status
Simulation time 619354322 ps
CPU time 12.11 seconds
Started Jul 14 06:21:37 PM PDT 24
Finished Jul 14 06:21:50 PM PDT 24
Peak memory 226036 kb
Host smart-94da3c90-5858-4838-b093-971a993984af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875826501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3875826501
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1021560046
Short name T828
Test name
Test status
Simulation time 390116037 ps
CPU time 8.9 seconds
Started Jul 14 06:21:34 PM PDT 24
Finished Jul 14 06:21:44 PM PDT 24
Peak memory 218236 kb
Host smart-27200243-c6e4-4723-bda5-3c7e2f722624
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021560046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1021560046
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2606077878
Short name T68
Test name
Test status
Simulation time 36724268 ps
CPU time 1.71 seconds
Started Jul 14 06:21:30 PM PDT 24
Finished Jul 14 06:21:32 PM PDT 24
Peak memory 217672 kb
Host smart-69d7af15-ff7b-4d3c-b71e-50c980f105d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606077878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2606077878
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3568923601
Short name T769
Test name
Test status
Simulation time 305119114 ps
CPU time 27.61 seconds
Started Jul 14 06:21:26 PM PDT 24
Finished Jul 14 06:21:55 PM PDT 24
Peak memory 250968 kb
Host smart-06b884a7-b71e-4996-b832-5cfd0992b080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568923601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3568923601
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3490349591
Short name T823
Test name
Test status
Simulation time 57820892 ps
CPU time 10.19 seconds
Started Jul 14 06:21:34 PM PDT 24
Finished Jul 14 06:21:44 PM PDT 24
Peak memory 250984 kb
Host smart-591cadde-db9c-4742-9175-959d2e2b1efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490349591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3490349591
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2418207427
Short name T698
Test name
Test status
Simulation time 27756538 ps
CPU time 0.89 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:21:27 PM PDT 24
Peak memory 211996 kb
Host smart-e978aaa7-cee2-4582-9524-c53ebd9ec0f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418207427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2418207427
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.174919239
Short name T655
Test name
Test status
Simulation time 31455431 ps
CPU time 0.82 seconds
Started Jul 14 06:21:50 PM PDT 24
Finished Jul 14 06:21:52 PM PDT 24
Peak memory 208796 kb
Host smart-b7fd256c-a8d5-496d-bacc-bb75977798fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174919239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.174919239
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1868899112
Short name T340
Test name
Test status
Simulation time 1348639132 ps
CPU time 13.12 seconds
Started Jul 14 06:21:33 PM PDT 24
Finished Jul 14 06:21:47 PM PDT 24
Peak memory 218220 kb
Host smart-bc173fc4-8a33-48b5-88cb-175424c964fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868899112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1868899112
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1277976209
Short name T587
Test name
Test status
Simulation time 59424287 ps
CPU time 2.2 seconds
Started Jul 14 06:21:34 PM PDT 24
Finished Jul 14 06:21:37 PM PDT 24
Peak memory 217180 kb
Host smart-b0a8a266-a2b4-4fb8-b781-0a1c53865c96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277976209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1277976209
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1567668577
Short name T462
Test name
Test status
Simulation time 4435816655 ps
CPU time 122.41 seconds
Started Jul 14 06:21:37 PM PDT 24
Finished Jul 14 06:23:40 PM PDT 24
Peak memory 219500 kb
Host smart-adc28042-158d-4341-8b90-e409e32188c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567668577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1567668577
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.774939970
Short name T640
Test name
Test status
Simulation time 680730785 ps
CPU time 5.39 seconds
Started Jul 14 06:21:33 PM PDT 24
Finished Jul 14 06:21:38 PM PDT 24
Peak memory 222960 kb
Host smart-74d7a2fc-d4aa-4287-a3e4-60257a91b529
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774939970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.774939970
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3772134434
Short name T84
Test name
Test status
Simulation time 959801947 ps
CPU time 7.06 seconds
Started Jul 14 06:21:35 PM PDT 24
Finished Jul 14 06:21:43 PM PDT 24
Peak memory 217696 kb
Host smart-0065ea9b-371d-469f-8a54-d44ba9be8e80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772134434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3772134434
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2312612614
Short name T758
Test name
Test status
Simulation time 8853882790 ps
CPU time 55.17 seconds
Started Jul 14 06:21:36 PM PDT 24
Finished Jul 14 06:22:32 PM PDT 24
Peak memory 252684 kb
Host smart-26729608-0573-4e50-b91b-548c6d90fbb8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312612614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2312612614
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2592863300
Short name T534
Test name
Test status
Simulation time 1050551503 ps
CPU time 17.22 seconds
Started Jul 14 06:21:37 PM PDT 24
Finished Jul 14 06:21:55 PM PDT 24
Peak memory 226264 kb
Host smart-bdb276ab-6d24-4f1a-9e9b-7180e5387026
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592863300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2592863300
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2905359205
Short name T297
Test name
Test status
Simulation time 709650884 ps
CPU time 3.54 seconds
Started Jul 14 06:21:33 PM PDT 24
Finished Jul 14 06:21:37 PM PDT 24
Peak memory 218112 kb
Host smart-ae224021-64ef-429f-9fbd-a509a7b6e4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905359205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2905359205
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.455024024
Short name T598
Test name
Test status
Simulation time 655434344 ps
CPU time 18.19 seconds
Started Jul 14 06:21:36 PM PDT 24
Finished Jul 14 06:21:55 PM PDT 24
Peak memory 218456 kb
Host smart-a23ba2c7-d845-4cd7-8429-f759a98e2903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455024024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.455024024
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3497174308
Short name T841
Test name
Test status
Simulation time 368913482 ps
CPU time 15.25 seconds
Started Jul 14 06:21:35 PM PDT 24
Finished Jul 14 06:21:51 PM PDT 24
Peak memory 226016 kb
Host smart-f67f5694-1bb6-43c4-b594-5a2df63dd1ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497174308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3497174308
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.966382665
Short name T164
Test name
Test status
Simulation time 1088771097 ps
CPU time 12.89 seconds
Started Jul 14 06:21:37 PM PDT 24
Finished Jul 14 06:21:51 PM PDT 24
Peak memory 218204 kb
Host smart-88f76262-9df8-426c-b087-577f96aec99b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966382665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.966382665
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.208171744
Short name T633
Test name
Test status
Simulation time 281191093 ps
CPU time 7.23 seconds
Started Jul 14 06:21:37 PM PDT 24
Finished Jul 14 06:21:45 PM PDT 24
Peak memory 224232 kb
Host smart-f19591af-c29a-4033-92b7-907b29b10795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208171744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.208171744
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2690987640
Short name T681
Test name
Test status
Simulation time 581857029 ps
CPU time 2.13 seconds
Started Jul 14 06:21:36 PM PDT 24
Finished Jul 14 06:21:39 PM PDT 24
Peak memory 223312 kb
Host smart-8cd47058-c6ab-4750-9c6d-c25e060d37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690987640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2690987640
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3466214731
Short name T768
Test name
Test status
Simulation time 244118880 ps
CPU time 27.26 seconds
Started Jul 14 06:21:38 PM PDT 24
Finished Jul 14 06:22:06 PM PDT 24
Peak memory 250836 kb
Host smart-1c7ffe22-35e4-47b8-ba5e-91a93857b811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466214731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3466214731
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2212893303
Short name T365
Test name
Test status
Simulation time 100505583 ps
CPU time 7.27 seconds
Started Jul 14 06:21:35 PM PDT 24
Finished Jul 14 06:21:43 PM PDT 24
Peak memory 250908 kb
Host smart-e5998d1d-a6ce-4d9f-bb0e-002a3ca2d150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212893303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2212893303
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2618738904
Short name T195
Test name
Test status
Simulation time 89069440655 ps
CPU time 529.47 seconds
Started Jul 14 06:21:36 PM PDT 24
Finished Jul 14 06:30:26 PM PDT 24
Peak memory 275764 kb
Host smart-76c39272-8584-46f5-9fe4-b212ddd7b785
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618738904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2618738904
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3615431030
Short name T623
Test name
Test status
Simulation time 36690624 ps
CPU time 0.95 seconds
Started Jul 14 06:21:37 PM PDT 24
Finished Jul 14 06:21:38 PM PDT 24
Peak memory 211876 kb
Host smart-153e7bc8-c48a-4e67-a306-b5592c2301c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615431030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3615431030
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1416949575
Short name T71
Test name
Test status
Simulation time 47585754 ps
CPU time 0.9 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:21:46 PM PDT 24
Peak memory 208956 kb
Host smart-94066e9c-253b-4305-a71a-d55b51c4ea23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416949575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1416949575
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3097675573
Short name T496
Test name
Test status
Simulation time 344501417 ps
CPU time 11.46 seconds
Started Jul 14 06:21:50 PM PDT 24
Finished Jul 14 06:22:03 PM PDT 24
Peak memory 218172 kb
Host smart-4ca8b48c-7140-4e56-9440-5ac9ac8f32a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097675573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3097675573
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3115969327
Short name T399
Test name
Test status
Simulation time 941392885 ps
CPU time 5.86 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:21:51 PM PDT 24
Peak memory 217348 kb
Host smart-57a3f040-0740-4d24-8e10-3b20dd8f12c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115969327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3115969327
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3260291411
Short name T744
Test name
Test status
Simulation time 11071160000 ps
CPU time 52.42 seconds
Started Jul 14 06:21:38 PM PDT 24
Finished Jul 14 06:22:31 PM PDT 24
Peak memory 218864 kb
Host smart-254a5904-1b1d-4a30-a0b8-e39e271bcc34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260291411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3260291411
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2511366613
Short name T347
Test name
Test status
Simulation time 306295687 ps
CPU time 5.94 seconds
Started Jul 14 06:21:49 PM PDT 24
Finished Jul 14 06:21:56 PM PDT 24
Peak memory 218136 kb
Host smart-010b5e50-8fa7-481b-8c75-6c0f8d2241f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511366613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2511366613
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1533976852
Short name T792
Test name
Test status
Simulation time 667866194 ps
CPU time 4.64 seconds
Started Jul 14 06:21:40 PM PDT 24
Finished Jul 14 06:21:45 PM PDT 24
Peak memory 217900 kb
Host smart-f8482967-048b-4f2f-9430-9e52ffd47483
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533976852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1533976852
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.4280034848
Short name T93
Test name
Test status
Simulation time 6562070654 ps
CPU time 60.79 seconds
Started Jul 14 06:21:40 PM PDT 24
Finished Jul 14 06:22:41 PM PDT 24
Peak memory 275824 kb
Host smart-7aaf402a-3b2c-4021-be69-17fa2e8f79c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280034848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.4280034848
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1749546708
Short name T618
Test name
Test status
Simulation time 652795664 ps
CPU time 22.12 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:22:08 PM PDT 24
Peak memory 250888 kb
Host smart-e4c269ed-2bfd-4031-9ef4-2c0e5e2b9117
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749546708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1749546708
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3320968342
Short name T735
Test name
Test status
Simulation time 172251767 ps
CPU time 2.2 seconds
Started Jul 14 06:21:39 PM PDT 24
Finished Jul 14 06:21:42 PM PDT 24
Peak memory 218136 kb
Host smart-e2aeb51e-babb-44fe-afa3-e0cbee62b3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320968342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3320968342
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.61671129
Short name T745
Test name
Test status
Simulation time 548607244 ps
CPU time 15.52 seconds
Started Jul 14 06:21:47 PM PDT 24
Finished Jul 14 06:22:05 PM PDT 24
Peak memory 226004 kb
Host smart-1aad9583-8620-4051-9497-f94be8e59cf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61671129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.61671129
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4258563274
Short name T316
Test name
Test status
Simulation time 716129486 ps
CPU time 7.51 seconds
Started Jul 14 06:21:39 PM PDT 24
Finished Jul 14 06:21:47 PM PDT 24
Peak memory 226032 kb
Host smart-61b4016b-88fe-4bbb-84b3-e766202e2a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258563274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4258563274
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4264868313
Short name T482
Test name
Test status
Simulation time 687531913 ps
CPU time 7.99 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:21:54 PM PDT 24
Peak memory 226020 kb
Host smart-d6a8eedd-141d-4cdb-96a4-a9d992d7a4c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264868313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
4264868313
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3564613487
Short name T508
Test name
Test status
Simulation time 1085650847 ps
CPU time 9.36 seconds
Started Jul 14 06:21:49 PM PDT 24
Finished Jul 14 06:22:00 PM PDT 24
Peak memory 226068 kb
Host smart-b7d84fa2-29c1-44af-937f-3db205f298c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564613487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3564613487
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3190461740
Short name T807
Test name
Test status
Simulation time 22935604 ps
CPU time 1.38 seconds
Started Jul 14 06:21:48 PM PDT 24
Finished Jul 14 06:21:51 PM PDT 24
Peak memory 213628 kb
Host smart-b617134f-5d73-4c76-ab1b-b4d745e04655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190461740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3190461740
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2171077552
Short name T237
Test name
Test status
Simulation time 297233049 ps
CPU time 22.26 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:22:08 PM PDT 24
Peak memory 251084 kb
Host smart-eebf274d-0760-4d33-8dbb-9874e85bf426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171077552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2171077552
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.587055613
Short name T398
Test name
Test status
Simulation time 109246055 ps
CPU time 9.31 seconds
Started Jul 14 06:21:46 PM PDT 24
Finished Jul 14 06:21:57 PM PDT 24
Peak memory 250876 kb
Host smart-d5c29bf0-87dc-458e-a8f4-7422a86caf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587055613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.587055613
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2638957117
Short name T722
Test name
Test status
Simulation time 8339379816 ps
CPU time 127.14 seconds
Started Jul 14 06:21:46 PM PDT 24
Finished Jul 14 06:23:54 PM PDT 24
Peak memory 250980 kb
Host smart-8d2eb90f-8f1e-4104-926f-c4cdf9c92ddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638957117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2638957117
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3261648123
Short name T177
Test name
Test status
Simulation time 150550544227 ps
CPU time 773.1 seconds
Started Jul 14 06:21:44 PM PDT 24
Finished Jul 14 06:34:38 PM PDT 24
Peak memory 496852 kb
Host smart-6e3c3ca2-bcfd-40c4-8814-23ed38caec1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3261648123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3261648123
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.963993566
Short name T647
Test name
Test status
Simulation time 17766698 ps
CPU time 0.97 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:21:47 PM PDT 24
Peak memory 212980 kb
Host smart-eab3227b-9b88-4e94-a9e2-9ef7d50d9233
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963993566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.963993566
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1756269040
Short name T685
Test name
Test status
Simulation time 28515637 ps
CPU time 1.15 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:21:48 PM PDT 24
Peak memory 208936 kb
Host smart-8ff8ca7f-3a46-4dee-8319-f68cadef1e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756269040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1756269040
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3510797571
Short name T832
Test name
Test status
Simulation time 284728374 ps
CPU time 10.3 seconds
Started Jul 14 06:21:40 PM PDT 24
Finished Jul 14 06:21:51 PM PDT 24
Peak memory 218164 kb
Host smart-5e84904a-00e3-47c3-ab60-4cde071576fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510797571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3510797571
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1725971651
Short name T604
Test name
Test status
Simulation time 2522964984 ps
CPU time 11.9 seconds
Started Jul 14 06:21:47 PM PDT 24
Finished Jul 14 06:22:01 PM PDT 24
Peak memory 217536 kb
Host smart-72a04a81-4032-4091-b353-7146278effef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725971651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1725971651
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2324649230
Short name T378
Test name
Test status
Simulation time 14556706087 ps
CPU time 50.86 seconds
Started Jul 14 06:21:41 PM PDT 24
Finished Jul 14 06:22:32 PM PDT 24
Peak memory 226088 kb
Host smart-27b8a608-14fc-4b1d-98a5-c432cee44bb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324649230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2324649230
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3710943639
Short name T53
Test name
Test status
Simulation time 388631546 ps
CPU time 4.02 seconds
Started Jul 14 06:21:39 PM PDT 24
Finished Jul 14 06:21:44 PM PDT 24
Peak memory 222896 kb
Host smart-6ad1b3c6-0c18-4af1-8277-653e9e1fcfb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710943639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3710943639
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3950345775
Short name T367
Test name
Test status
Simulation time 903056123 ps
CPU time 6.48 seconds
Started Jul 14 06:21:38 PM PDT 24
Finished Jul 14 06:21:45 PM PDT 24
Peak memory 217688 kb
Host smart-3ac16550-f584-4af8-853b-caf790c09d8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950345775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3950345775
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.205832377
Short name T268
Test name
Test status
Simulation time 1197746575 ps
CPU time 33.54 seconds
Started Jul 14 06:21:40 PM PDT 24
Finished Jul 14 06:22:14 PM PDT 24
Peak memory 252564 kb
Host smart-53a421c3-d888-4c6a-9053-707ed03391ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205832377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.205832377
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2188364949
Short name T765
Test name
Test status
Simulation time 3489225712 ps
CPU time 11.69 seconds
Started Jul 14 06:21:39 PM PDT 24
Finished Jul 14 06:21:51 PM PDT 24
Peak memory 247920 kb
Host smart-a65d8385-090c-4c74-8529-cac50931c0e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188364949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2188364949
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3607279155
Short name T21
Test name
Test status
Simulation time 368569922 ps
CPU time 3.04 seconds
Started Jul 14 06:21:39 PM PDT 24
Finished Jul 14 06:21:43 PM PDT 24
Peak memory 218116 kb
Host smart-0fb4342c-00a1-4d7d-aa77-f9f84a37ac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607279155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3607279155
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3604858440
Short name T303
Test name
Test status
Simulation time 2674120927 ps
CPU time 14.88 seconds
Started Jul 14 06:21:41 PM PDT 24
Finished Jul 14 06:21:56 PM PDT 24
Peak memory 225996 kb
Host smart-46cd9eff-b7eb-4736-abba-9edba164d526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604858440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3604858440
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2117491398
Short name T652
Test name
Test status
Simulation time 586215209 ps
CPU time 16.39 seconds
Started Jul 14 06:21:49 PM PDT 24
Finished Jul 14 06:22:07 PM PDT 24
Peak memory 226048 kb
Host smart-0e4d788e-ac60-41fa-b08f-f5c56297144c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117491398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2117491398
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2461411796
Short name T554
Test name
Test status
Simulation time 502271478 ps
CPU time 13.75 seconds
Started Jul 14 06:21:38 PM PDT 24
Finished Jul 14 06:21:53 PM PDT 24
Peak memory 218248 kb
Host smart-9d2d178d-1bb6-45c0-8717-01d20eb9c743
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461411796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2461411796
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1580536807
Short name T276
Test name
Test status
Simulation time 2214154877 ps
CPU time 6.18 seconds
Started Jul 14 06:21:47 PM PDT 24
Finished Jul 14 06:21:55 PM PDT 24
Peak memory 218328 kb
Host smart-c2e7e6f2-f73d-47df-b112-64b8248aa3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580536807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1580536807
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.983325026
Short name T609
Test name
Test status
Simulation time 155533591 ps
CPU time 1.97 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:21:48 PM PDT 24
Peak memory 217728 kb
Host smart-556d788f-e402-44c2-bb1a-1fadb83d1262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983325026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.983325026
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.691976389
Short name T856
Test name
Test status
Simulation time 1936005653 ps
CPU time 24.32 seconds
Started Jul 14 06:21:48 PM PDT 24
Finished Jul 14 06:22:14 PM PDT 24
Peak memory 250876 kb
Host smart-19b04645-1650-4056-91f0-c8bc10886088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691976389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.691976389
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2411520023
Short name T569
Test name
Test status
Simulation time 271995702 ps
CPU time 8.16 seconds
Started Jul 14 06:21:49 PM PDT 24
Finished Jul 14 06:21:59 PM PDT 24
Peak memory 250912 kb
Host smart-208823c4-0cef-4c94-849d-ac8f9ed0a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411520023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2411520023
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3350214161
Short name T725
Test name
Test status
Simulation time 2307529357 ps
CPU time 79.57 seconds
Started Jul 14 06:21:46 PM PDT 24
Finished Jul 14 06:23:06 PM PDT 24
Peak memory 332960 kb
Host smart-16a27aac-3393-4617-a56b-83d3897800b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350214161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3350214161
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2250910228
Short name T74
Test name
Test status
Simulation time 164059579480 ps
CPU time 1044.81 seconds
Started Jul 14 06:21:47 PM PDT 24
Finished Jul 14 06:39:14 PM PDT 24
Peak memory 742680 kb
Host smart-11f531db-6bec-4e82-8a58-876e30b9aacb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2250910228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2250910228
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3005910505
Short name T166
Test name
Test status
Simulation time 15664121 ps
CPU time 1.03 seconds
Started Jul 14 06:21:39 PM PDT 24
Finished Jul 14 06:21:40 PM PDT 24
Peak memory 217720 kb
Host smart-ad9022e4-659e-4082-b16b-a902f77234d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005910505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3005910505
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2783502721
Short name T468
Test name
Test status
Simulation time 33089752 ps
CPU time 1.1 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:21:53 PM PDT 24
Peak memory 208964 kb
Host smart-aea83594-e3d9-4266-981d-0e35e6b71dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783502721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2783502721
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2754584052
Short name T741
Test name
Test status
Simulation time 1124386517 ps
CPU time 9.26 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:22:02 PM PDT 24
Peak memory 217404 kb
Host smart-616cd258-8af7-4b56-9765-4cce9161734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754584052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2754584052
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2772866807
Short name T382
Test name
Test status
Simulation time 1198648759 ps
CPU time 8.64 seconds
Started Jul 14 06:21:46 PM PDT 24
Finished Jul 14 06:21:55 PM PDT 24
Peak memory 217400 kb
Host smart-810467d4-bf62-4b42-970c-ad685bd24474
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772866807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2772866807
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2721580447
Short name T375
Test name
Test status
Simulation time 1333339664 ps
CPU time 42.36 seconds
Started Jul 14 06:21:55 PM PDT 24
Finished Jul 14 06:22:38 PM PDT 24
Peak memory 226016 kb
Host smart-b100279a-02d1-4fef-8060-1b580861a1e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721580447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2721580447
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2039313344
Short name T634
Test name
Test status
Simulation time 395730375 ps
CPU time 6.23 seconds
Started Jul 14 06:21:48 PM PDT 24
Finished Jul 14 06:21:56 PM PDT 24
Peak memory 218264 kb
Host smart-1331ec16-88d0-468c-9881-6fd3fe6d6ad7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039313344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2039313344
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3280666576
Short name T75
Test name
Test status
Simulation time 718076219 ps
CPU time 1.83 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:21:54 PM PDT 24
Peak memory 217724 kb
Host smart-75261792-084a-4e80-a9fe-e770c0cb385c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280666576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3280666576
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.843443966
Short name T86
Test name
Test status
Simulation time 3736844075 ps
CPU time 75.31 seconds
Started Jul 14 06:21:48 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 283820 kb
Host smart-8143c030-8c7a-4856-b10e-d38e205c1660
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843443966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.843443966
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3257844543
Short name T523
Test name
Test status
Simulation time 1059609121 ps
CPU time 19.95 seconds
Started Jul 14 06:21:48 PM PDT 24
Finished Jul 14 06:22:10 PM PDT 24
Peak memory 246912 kb
Host smart-c1a97113-f397-466e-8fcc-1665fa836b91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257844543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3257844543
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.365679535
Short name T173
Test name
Test status
Simulation time 130220008 ps
CPU time 3.37 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:21:48 PM PDT 24
Peak memory 218160 kb
Host smart-dbba64da-3e6d-48e0-83c3-23b59a3328f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365679535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.365679535
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1345214690
Short name T627
Test name
Test status
Simulation time 1700608232 ps
CPU time 17.99 seconds
Started Jul 14 06:21:46 PM PDT 24
Finished Jul 14 06:22:06 PM PDT 24
Peak memory 226024 kb
Host smart-fad65b5d-3af6-4991-8d36-f759ecebf09d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345214690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1345214690
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2700660828
Short name T547
Test name
Test status
Simulation time 2962774249 ps
CPU time 12.51 seconds
Started Jul 14 06:21:47 PM PDT 24
Finished Jul 14 06:22:01 PM PDT 24
Peak memory 226092 kb
Host smart-0f80b58d-cb25-4210-85a6-da860fffc169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700660828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2700660828
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3854327452
Short name T591
Test name
Test status
Simulation time 282270643 ps
CPU time 11.39 seconds
Started Jul 14 06:21:48 PM PDT 24
Finished Jul 14 06:22:01 PM PDT 24
Peak memory 226020 kb
Host smart-e1eea373-e514-4ef2-b0f3-7b3bdac48be8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854327452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3854327452
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.146324051
Short name T721
Test name
Test status
Simulation time 753934823 ps
CPU time 9.41 seconds
Started Jul 14 06:21:45 PM PDT 24
Finished Jul 14 06:21:56 PM PDT 24
Peak memory 225224 kb
Host smart-4e86c31c-da76-41a6-81a4-2d6a780dafc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146324051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.146324051
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3544642315
Short name T443
Test name
Test status
Simulation time 149695200 ps
CPU time 2.63 seconds
Started Jul 14 06:21:46 PM PDT 24
Finished Jul 14 06:21:50 PM PDT 24
Peak memory 214316 kb
Host smart-357cf6de-2524-4dd3-a208-ec44c658342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544642315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3544642315
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1405899863
Short name T835
Test name
Test status
Simulation time 167241361 ps
CPU time 22.05 seconds
Started Jul 14 06:21:55 PM PDT 24
Finished Jul 14 06:22:18 PM PDT 24
Peak memory 250944 kb
Host smart-ec8bf38a-39b2-4065-b976-9ce7dcac894d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405899863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1405899863
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1269117976
Short name T774
Test name
Test status
Simulation time 628624629 ps
CPU time 9.11 seconds
Started Jul 14 06:21:50 PM PDT 24
Finished Jul 14 06:22:00 PM PDT 24
Peak memory 250980 kb
Host smart-99cd45e5-e78b-4015-8841-c08900dfed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269117976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1269117976
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3839695524
Short name T422
Test name
Test status
Simulation time 4299274014 ps
CPU time 95.88 seconds
Started Jul 14 06:21:50 PM PDT 24
Finished Jul 14 06:23:27 PM PDT 24
Peak memory 283744 kb
Host smart-6b1c1568-9091-464d-aa07-bc90b2ce7285
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839695524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3839695524
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2148755977
Short name T44
Test name
Test status
Simulation time 70192165274 ps
CPU time 453.5 seconds
Started Jul 14 06:21:46 PM PDT 24
Finished Jul 14 06:29:21 PM PDT 24
Peak memory 438488 kb
Host smart-929ca9fb-6ae3-4f76-bdc1-b27f4309b7b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2148755977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2148755977
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2933076027
Short name T289
Test name
Test status
Simulation time 37736666 ps
CPU time 1.17 seconds
Started Jul 14 06:21:53 PM PDT 24
Finished Jul 14 06:21:55 PM PDT 24
Peak memory 208948 kb
Host smart-836487d7-4a40-455d-b559-4855e18bd262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933076027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2933076027
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2020513554
Short name T540
Test name
Test status
Simulation time 287433755 ps
CPU time 9.43 seconds
Started Jul 14 06:21:50 PM PDT 24
Finished Jul 14 06:22:01 PM PDT 24
Peak memory 226040 kb
Host smart-cfec0dfb-5c44-4976-91f0-92d9020795a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020513554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2020513554
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2790719959
Short name T572
Test name
Test status
Simulation time 913117352 ps
CPU time 5.24 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:21:58 PM PDT 24
Peak memory 217096 kb
Host smart-83dae419-d720-47a3-9364-54bbf541aa65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790719959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2790719959
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2111293637
Short name T559
Test name
Test status
Simulation time 2078631252 ps
CPU time 24.44 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:22:16 PM PDT 24
Peak memory 218240 kb
Host smart-7760cb21-baa3-4732-a98d-a77d46431c26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111293637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2111293637
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2024876528
Short name T818
Test name
Test status
Simulation time 1352092405 ps
CPU time 11.17 seconds
Started Jul 14 06:21:47 PM PDT 24
Finished Jul 14 06:22:00 PM PDT 24
Peak memory 218132 kb
Host smart-1984b60b-a072-4e68-97c5-07f33e0d35f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024876528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2024876528
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3867420397
Short name T79
Test name
Test status
Simulation time 155927736 ps
CPU time 4.55 seconds
Started Jul 14 06:21:43 PM PDT 24
Finished Jul 14 06:21:48 PM PDT 24
Peak memory 217664 kb
Host smart-d2877677-5261-4ad3-bc7d-b4e8e07df931
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867420397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3867420397
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1812357384
Short name T265
Test name
Test status
Simulation time 5865636270 ps
CPU time 51.32 seconds
Started Jul 14 06:21:48 PM PDT 24
Finished Jul 14 06:22:41 PM PDT 24
Peak memory 280332 kb
Host smart-825d9ad8-f7dd-4d61-97a8-9bbd9f1247d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812357384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1812357384
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3748569508
Short name T439
Test name
Test status
Simulation time 876142591 ps
CPU time 14.35 seconds
Started Jul 14 06:21:48 PM PDT 24
Finished Jul 14 06:22:05 PM PDT 24
Peak memory 222248 kb
Host smart-5a2ba9e1-e4a7-4f2b-9be6-2ab32d932c72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748569508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3748569508
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.548955892
Short name T449
Test name
Test status
Simulation time 96471357 ps
CPU time 2.51 seconds
Started Jul 14 06:21:47 PM PDT 24
Finished Jul 14 06:21:51 PM PDT 24
Peak memory 218200 kb
Host smart-c36e4e84-f2e6-4424-a7b5-499ceee959a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548955892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.548955892
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1251924974
Short name T250
Test name
Test status
Simulation time 756788412 ps
CPU time 14.98 seconds
Started Jul 14 06:21:53 PM PDT 24
Finished Jul 14 06:22:08 PM PDT 24
Peak memory 225988 kb
Host smart-e3c6e1c4-2ed6-4017-90ba-9559543e1736
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251924974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1251924974
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1531087253
Short name T782
Test name
Test status
Simulation time 1251842889 ps
CPU time 7.95 seconds
Started Jul 14 06:21:55 PM PDT 24
Finished Jul 14 06:22:04 PM PDT 24
Peak memory 226012 kb
Host smart-a7098ad4-2ab0-43e6-a3e7-314e1ec7697c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531087253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1531087253
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3680795349
Short name T306
Test name
Test status
Simulation time 1582958723 ps
CPU time 13.87 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:22:06 PM PDT 24
Peak memory 226036 kb
Host smart-ce8c4adc-33d1-4f78-a57a-8338377562b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680795349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3680795349
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.13313999
Short name T190
Test name
Test status
Simulation time 19655085 ps
CPU time 1.81 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:21:54 PM PDT 24
Peak memory 213376 kb
Host smart-81011e6f-d9ea-42db-82dd-4c967d836264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13313999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.13313999
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3815291266
Short name T246
Test name
Test status
Simulation time 295901203 ps
CPU time 30.89 seconds
Started Jul 14 06:21:50 PM PDT 24
Finished Jul 14 06:22:22 PM PDT 24
Peak memory 250952 kb
Host smart-981d19de-a5e5-48d9-a3bb-ad57ced12877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815291266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3815291266
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.456861867
Short name T730
Test name
Test status
Simulation time 59514952 ps
CPU time 8.89 seconds
Started Jul 14 06:21:55 PM PDT 24
Finished Jul 14 06:22:05 PM PDT 24
Peak memory 251072 kb
Host smart-0e5883d4-19bb-4c41-9891-fc7288867e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456861867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.456861867
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.465385545
Short name T839
Test name
Test status
Simulation time 673414339 ps
CPU time 17.57 seconds
Started Jul 14 06:21:55 PM PDT 24
Finished Jul 14 06:22:13 PM PDT 24
Peak memory 226016 kb
Host smart-1fe6aedb-27c0-43a7-a77f-bb7911fd4eb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465385545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.465385545
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2921660472
Short name T574
Test name
Test status
Simulation time 19526005 ps
CPU time 0.94 seconds
Started Jul 14 06:21:47 PM PDT 24
Finished Jul 14 06:21:50 PM PDT 24
Peak memory 211924 kb
Host smart-475ae24e-96d4-4ac7-af66-76114deba373
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921660472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2921660472
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1416901966
Short name T277
Test name
Test status
Simulation time 12897239 ps
CPU time 1.01 seconds
Started Jul 14 06:21:54 PM PDT 24
Finished Jul 14 06:21:57 PM PDT 24
Peak memory 208908 kb
Host smart-cb6fecda-ba14-40dd-94e4-27a6b3668f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416901966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1416901966
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3974637241
Short name T567
Test name
Test status
Simulation time 661173298 ps
CPU time 8.25 seconds
Started Jul 14 06:21:54 PM PDT 24
Finished Jul 14 06:22:04 PM PDT 24
Peak memory 218176 kb
Host smart-73606512-5894-478b-891a-e71eb74963b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974637241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3974637241
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1220412536
Short name T693
Test name
Test status
Simulation time 5419948497 ps
CPU time 16.39 seconds
Started Jul 14 06:21:55 PM PDT 24
Finished Jul 14 06:22:12 PM PDT 24
Peak memory 217944 kb
Host smart-721080c2-2084-46f1-860e-6f0f9755d290
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220412536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1220412536
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3120342128
Short name T263
Test name
Test status
Simulation time 8580810587 ps
CPU time 27.98 seconds
Started Jul 14 06:21:53 PM PDT 24
Finished Jul 14 06:22:22 PM PDT 24
Peak memory 218168 kb
Host smart-5d69df36-5220-4574-9d1f-c42f6dc2a68e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120342128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3120342128
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1101257702
Short name T323
Test name
Test status
Simulation time 1255325300 ps
CPU time 9.77 seconds
Started Jul 14 06:21:54 PM PDT 24
Finished Jul 14 06:22:05 PM PDT 24
Peak memory 218264 kb
Host smart-8886d79e-8551-4908-a303-6b56d0cd05e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101257702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1101257702
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.100796059
Short name T171
Test name
Test status
Simulation time 1296133331 ps
CPU time 3.93 seconds
Started Jul 14 06:21:56 PM PDT 24
Finished Jul 14 06:22:01 PM PDT 24
Peak memory 217596 kb
Host smart-46c1bc48-5b78-4a93-8cb1-baa8497bbb8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100796059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
100796059
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2874853020
Short name T808
Test name
Test status
Simulation time 9381598706 ps
CPU time 81.29 seconds
Started Jul 14 06:21:52 PM PDT 24
Finished Jul 14 06:23:14 PM PDT 24
Peak memory 279716 kb
Host smart-e05ae8ce-b895-4ec7-a34b-cee5edb65c2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874853020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2874853020
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2654350055
Short name T556
Test name
Test status
Simulation time 704295069 ps
CPU time 20.06 seconds
Started Jul 14 06:21:54 PM PDT 24
Finished Jul 14 06:22:15 PM PDT 24
Peak memory 250976 kb
Host smart-e5be50b6-5d98-4b6f-80c9-5972770d7976
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654350055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2654350055
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3204626188
Short name T715
Test name
Test status
Simulation time 64150253 ps
CPU time 2.7 seconds
Started Jul 14 06:21:55 PM PDT 24
Finished Jul 14 06:21:58 PM PDT 24
Peak memory 218228 kb
Host smart-fcb67ca8-a666-4d44-bd77-d69a0a738808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204626188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3204626188
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3881250202
Short name T812
Test name
Test status
Simulation time 1414461830 ps
CPU time 12.27 seconds
Started Jul 14 06:21:53 PM PDT 24
Finished Jul 14 06:22:06 PM PDT 24
Peak memory 226036 kb
Host smart-3dec693e-2e98-4570-88bd-6e2a352923b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881250202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3881250202
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.25584333
Short name T731
Test name
Test status
Simulation time 1742849002 ps
CPU time 11.15 seconds
Started Jul 14 06:21:53 PM PDT 24
Finished Jul 14 06:22:05 PM PDT 24
Peak memory 226004 kb
Host smart-750b61a5-8c8e-4b18-b634-6b2b8c04f011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25584333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_dig
est.25584333
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.658234503
Short name T401
Test name
Test status
Simulation time 416959347 ps
CPU time 9.56 seconds
Started Jul 14 06:21:58 PM PDT 24
Finished Jul 14 06:22:08 PM PDT 24
Peak memory 218132 kb
Host smart-cccd2796-f653-4b12-b8f7-75456c65c2a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658234503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.658234503
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.309105442
Short name T595
Test name
Test status
Simulation time 458908884 ps
CPU time 6.68 seconds
Started Jul 14 06:21:59 PM PDT 24
Finished Jul 14 06:22:06 PM PDT 24
Peak memory 218248 kb
Host smart-00f8db72-9c15-478d-a24b-d4ff78a421f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309105442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.309105442
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.339736040
Short name T733
Test name
Test status
Simulation time 656255171 ps
CPU time 5.39 seconds
Started Jul 14 06:21:53 PM PDT 24
Finished Jul 14 06:21:59 PM PDT 24
Peak memory 217716 kb
Host smart-c16b6d23-8f6b-402c-aec8-253fae93119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339736040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.339736040
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2293297914
Short name T270
Test name
Test status
Simulation time 825160956 ps
CPU time 18.86 seconds
Started Jul 14 06:21:53 PM PDT 24
Finished Jul 14 06:22:13 PM PDT 24
Peak memory 250976 kb
Host smart-329cf91d-f80f-426c-bb4b-27901c2d3118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293297914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2293297914
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.943475129
Short name T415
Test name
Test status
Simulation time 156844929 ps
CPU time 7.45 seconds
Started Jul 14 06:21:52 PM PDT 24
Finished Jul 14 06:22:00 PM PDT 24
Peak memory 247152 kb
Host smart-93ea035e-8952-462e-913d-b5e6c773e2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943475129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.943475129
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1504564665
Short name T803
Test name
Test status
Simulation time 9592912991 ps
CPU time 183.07 seconds
Started Jul 14 06:21:54 PM PDT 24
Finished Jul 14 06:24:59 PM PDT 24
Peak memory 281428 kb
Host smart-91dea0a2-fc06-4957-a4cc-a595ecaf7c95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504564665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1504564665
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3247325597
Short name T91
Test name
Test status
Simulation time 17390317261 ps
CPU time 211.2 seconds
Started Jul 14 06:21:52 PM PDT 24
Finished Jul 14 06:25:24 PM PDT 24
Peak memory 267460 kb
Host smart-0c34f7ac-a12b-4792-b371-a6af57d6d74d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3247325597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3247325597
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4176602402
Short name T380
Test name
Test status
Simulation time 32315868 ps
CPU time 0.89 seconds
Started Jul 14 06:21:50 PM PDT 24
Finished Jul 14 06:21:52 PM PDT 24
Peak memory 212932 kb
Host smart-61ab42b3-b9b1-4681-8545-3640726938a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176602402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4176602402
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3126624020
Short name T258
Test name
Test status
Simulation time 66201518 ps
CPU time 0.98 seconds
Started Jul 14 06:21:59 PM PDT 24
Finished Jul 14 06:22:01 PM PDT 24
Peak memory 208968 kb
Host smart-ad4ee2ff-f91e-4e52-a5c3-6065a846fc52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126624020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3126624020
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.210093543
Short name T108
Test name
Test status
Simulation time 690080306 ps
CPU time 11.42 seconds
Started Jul 14 06:22:00 PM PDT 24
Finished Jul 14 06:22:12 PM PDT 24
Peak memory 218100 kb
Host smart-40d75ee6-c32e-4ea3-8abf-bb0d70243091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210093543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.210093543
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3197728965
Short name T27
Test name
Test status
Simulation time 2164373978 ps
CPU time 4.09 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:15 PM PDT 24
Peak memory 216980 kb
Host smart-ba6c86ad-5a04-4488-a9fe-60546fa870ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197728965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3197728965
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.473581
Short name T40
Test name
Test status
Simulation time 2393447850 ps
CPU time 61.69 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:23:14 PM PDT 24
Peak memory 218284 kb
Host smart-ccd0e9ec-427b-4247-9a47-7305452a1232
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_
errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_errors.473581
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.162716278
Short name T491
Test name
Test status
Simulation time 1101097119 ps
CPU time 6.36 seconds
Started Jul 14 06:21:59 PM PDT 24
Finished Jul 14 06:22:06 PM PDT 24
Peak memory 218284 kb
Host smart-cc51f188-0f33-4ff0-8923-34c1d78351d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162716278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.162716278
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.743269603
Short name T80
Test name
Test status
Simulation time 1019285112 ps
CPU time 3.29 seconds
Started Jul 14 06:22:01 PM PDT 24
Finished Jul 14 06:22:05 PM PDT 24
Peak memory 217736 kb
Host smart-f3a31e82-8ce8-4ca7-b8d1-20c5c49c43b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743269603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
743269603
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2547636756
Short name T337
Test name
Test status
Simulation time 5336282201 ps
CPU time 46.55 seconds
Started Jul 14 06:22:01 PM PDT 24
Finished Jul 14 06:22:48 PM PDT 24
Peak memory 255924 kb
Host smart-33721b63-5279-418d-956f-0448bd56d13f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547636756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2547636756
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1697699687
Short name T293
Test name
Test status
Simulation time 2010464062 ps
CPU time 18.61 seconds
Started Jul 14 06:22:02 PM PDT 24
Finished Jul 14 06:22:22 PM PDT 24
Peak memory 247640 kb
Host smart-225e0b17-9a9d-46d2-828b-b68926b80a1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697699687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1697699687
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4026495019
Short name T253
Test name
Test status
Simulation time 86289627 ps
CPU time 3.28 seconds
Started Jul 14 06:21:59 PM PDT 24
Finished Jul 14 06:22:03 PM PDT 24
Peak memory 218176 kb
Host smart-2652afb0-8801-4764-a884-9a4b545258cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026495019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4026495019
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3692551837
Short name T418
Test name
Test status
Simulation time 452316660 ps
CPU time 10.56 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:23 PM PDT 24
Peak memory 218848 kb
Host smart-21d8c7aa-4068-466a-98ec-ba7da3c6ce46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692551837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3692551837
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2919714164
Short name T249
Test name
Test status
Simulation time 1572772140 ps
CPU time 11.57 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:23 PM PDT 24
Peak memory 225992 kb
Host smart-80acec1e-6215-422a-88ad-8b47fef39cc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919714164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2919714164
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1914406549
Short name T348
Test name
Test status
Simulation time 165290745 ps
CPU time 7.04 seconds
Started Jul 14 06:21:57 PM PDT 24
Finished Jul 14 06:22:05 PM PDT 24
Peak memory 224720 kb
Host smart-67baaf88-1d62-44f6-9b96-46dd81c5e33e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914406549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1914406549
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.122550482
Short name T762
Test name
Test status
Simulation time 568786785 ps
CPU time 11.76 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:24 PM PDT 24
Peak memory 225488 kb
Host smart-31d0d27a-970a-457a-a1f5-9a2c54264149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122550482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.122550482
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1445205112
Short name T448
Test name
Test status
Simulation time 368945462 ps
CPU time 2.88 seconds
Started Jul 14 06:21:53 PM PDT 24
Finished Jul 14 06:21:56 PM PDT 24
Peak memory 217676 kb
Host smart-800c4a92-dedf-4eb9-bf2d-5a858ca144ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445205112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1445205112
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3596671212
Short name T746
Test name
Test status
Simulation time 236472310 ps
CPU time 29.31 seconds
Started Jul 14 06:22:00 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 250836 kb
Host smart-1c5b09a4-b9bd-4071-898b-4f49ad272358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596671212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3596671212
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3231056293
Short name T100
Test name
Test status
Simulation time 98752077 ps
CPU time 2.86 seconds
Started Jul 14 06:21:59 PM PDT 24
Finished Jul 14 06:22:02 PM PDT 24
Peak memory 226292 kb
Host smart-1e7861e8-9376-48f9-80a2-41d32bb44f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231056293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3231056293
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1546038137
Short name T77
Test name
Test status
Simulation time 16599270512 ps
CPU time 230.84 seconds
Started Jul 14 06:21:59 PM PDT 24
Finished Jul 14 06:25:51 PM PDT 24
Peak memory 226036 kb
Host smart-1620cc13-64b3-4aed-a3e8-2a591db70e46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546038137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1546038137
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.477966610
Short name T254
Test name
Test status
Simulation time 13605849 ps
CPU time 1.02 seconds
Started Jul 14 06:21:51 PM PDT 24
Finished Jul 14 06:21:53 PM PDT 24
Peak memory 211808 kb
Host smart-898b83b0-c407-49d1-a9a7-5c837ce0b309
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477966610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.477966610
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.197724704
Short name T484
Test name
Test status
Simulation time 52581719 ps
CPU time 0.91 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:43 PM PDT 24
Peak memory 208956 kb
Host smart-71d0dc22-7acd-4702-9182-6d4fe0ba4cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197724704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.197724704
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1794886369
Short name T612
Test name
Test status
Simulation time 66502588 ps
CPU time 0.82 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:41 PM PDT 24
Peak memory 208980 kb
Host smart-b1c57ffb-bd86-4339-a049-9d10d1ab04f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794886369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1794886369
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1334254297
Short name T17
Test name
Test status
Simulation time 2441531008 ps
CPU time 15.9 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:56 PM PDT 24
Peak memory 218288 kb
Host smart-9f487eee-f957-4e11-b887-4b0fa29b627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334254297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1334254297
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2512088868
Short name T29
Test name
Test status
Simulation time 355829637 ps
CPU time 4.73 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:47 PM PDT 24
Peak memory 217284 kb
Host smart-1825ca6a-e72c-4879-b21f-55a49e1acb95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512088868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2512088868
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.901560542
Short name T403
Test name
Test status
Simulation time 3144230169 ps
CPU time 46.93 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:21:29 PM PDT 24
Peak memory 226088 kb
Host smart-ab088057-6007-440e-a9df-d5072acc2f87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901560542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.901560542
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2698694578
Short name T626
Test name
Test status
Simulation time 287118816 ps
CPU time 7.8 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:20:52 PM PDT 24
Peak memory 217720 kb
Host smart-208f0fd5-c29d-46c4-aa97-4ce17c5cba52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698694578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
698694578
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2367846476
Short name T568
Test name
Test status
Simulation time 1900586488 ps
CPU time 10.77 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:51 PM PDT 24
Peak memory 218144 kb
Host smart-5477e5c0-913e-4b1d-858d-635512e159e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367846476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2367846476
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.249157333
Short name T450
Test name
Test status
Simulation time 1650967350 ps
CPU time 18.36 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:21:02 PM PDT 24
Peak memory 217632 kb
Host smart-7148f683-3f4b-4a0e-ba85-d2cc1a5565be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249157333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.249157333
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3588705882
Short name T532
Test name
Test status
Simulation time 365517521 ps
CPU time 4.8 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:46 PM PDT 24
Peak memory 217708 kb
Host smart-c35d1076-1fcb-4155-a786-991f5c29b97c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588705882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3588705882
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3603549370
Short name T333
Test name
Test status
Simulation time 4075925673 ps
CPU time 29.07 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:21:13 PM PDT 24
Peak memory 267424 kb
Host smart-029a679a-1045-444a-9f44-970aa6777b40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603549370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3603549370
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2677980535
Short name T24
Test name
Test status
Simulation time 1443268140 ps
CPU time 11.12 seconds
Started Jul 14 06:20:44 PM PDT 24
Finished Jul 14 06:20:56 PM PDT 24
Peak memory 247664 kb
Host smart-954a4e21-334d-428c-bae6-9b450d00769b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677980535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2677980535
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.343977429
Short name T602
Test name
Test status
Simulation time 193377394 ps
CPU time 2.8 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:20:46 PM PDT 24
Peak memory 218228 kb
Host smart-ebdafabc-73d2-4a7a-bbb9-21f348aa223d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343977429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.343977429
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1858240389
Short name T548
Test name
Test status
Simulation time 1506878730 ps
CPU time 13.07 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:55 PM PDT 24
Peak memory 217664 kb
Host smart-071a3e8b-9a27-4946-919f-9f7f112521b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858240389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1858240389
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.824345665
Short name T89
Test name
Test status
Simulation time 485069319 ps
CPU time 21.39 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:21:04 PM PDT 24
Peak memory 281512 kb
Host smart-75496a18-9559-49fd-a5ba-70ca4ee17240
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824345665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.824345665
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3103318858
Short name T469
Test name
Test status
Simulation time 610136212 ps
CPU time 13.22 seconds
Started Jul 14 06:20:44 PM PDT 24
Finished Jul 14 06:20:58 PM PDT 24
Peak memory 226032 kb
Host smart-0c90b977-8d1d-4063-9eb1-c942b2f29177
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103318858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3103318858
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1850272272
Short name T256
Test name
Test status
Simulation time 4064876616 ps
CPU time 15.95 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:58 PM PDT 24
Peak memory 226108 kb
Host smart-0e29993b-ba51-4f04-ba3b-3737f6d89173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850272272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1850272272
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2030475983
Short name T799
Test name
Test status
Simulation time 246596110 ps
CPU time 9.32 seconds
Started Jul 14 06:20:44 PM PDT 24
Finished Jul 14 06:20:54 PM PDT 24
Peak memory 218224 kb
Host smart-9229f691-e395-407a-bd4f-ff9e92dc1f65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030475983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
030475983
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1434365239
Short name T47
Test name
Test status
Simulation time 2086556117 ps
CPU time 12.69 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:55 PM PDT 24
Peak memory 226036 kb
Host smart-4669fecb-01c7-4a17-b8e1-c438430d79bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434365239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1434365239
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.947696033
Short name T809
Test name
Test status
Simulation time 26442106 ps
CPU time 1.28 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:44 PM PDT 24
Peak memory 213636 kb
Host smart-6c4d983b-a31c-4b48-a037-9dd9404cf3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947696033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.947696033
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3985090947
Short name T578
Test name
Test status
Simulation time 3233284583 ps
CPU time 28.57 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:21:11 PM PDT 24
Peak memory 250968 kb
Host smart-e5fb163f-d776-429d-bc18-0ef7f66ad68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985090947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3985090947
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2312517889
Short name T648
Test name
Test status
Simulation time 99457191 ps
CPU time 8.86 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:20:52 PM PDT 24
Peak memory 250968 kb
Host smart-872cef37-cf89-468d-94f6-0c401b6a1ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312517889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2312517889
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1930538398
Short name T421
Test name
Test status
Simulation time 17422837254 ps
CPU time 162.44 seconds
Started Jul 14 06:20:46 PM PDT 24
Finished Jul 14 06:23:29 PM PDT 24
Peak memory 272244 kb
Host smart-18d14906-69a9-444a-8973-4b9e5663fb0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930538398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1930538398
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1906842683
Short name T329
Test name
Test status
Simulation time 23073219 ps
CPU time 0.96 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:41 PM PDT 24
Peak memory 212008 kb
Host smart-d3843b94-3a54-429f-a590-21371b3f99c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906842683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1906842683
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3953573958
Short name T11
Test name
Test status
Simulation time 57178141 ps
CPU time 1 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:14 PM PDT 24
Peak memory 208940 kb
Host smart-4814e482-1afd-46cc-8e61-5b63eeac3f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953573958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3953573958
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1173653742
Short name T861
Test name
Test status
Simulation time 1322588678 ps
CPU time 13.95 seconds
Started Jul 14 06:21:58 PM PDT 24
Finished Jul 14 06:22:12 PM PDT 24
Peak memory 218168 kb
Host smart-f77b8e14-b1de-4172-84ef-bbe0aa5fbc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173653742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1173653742
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1249207440
Short name T751
Test name
Test status
Simulation time 182634505 ps
CPU time 2.56 seconds
Started Jul 14 06:22:03 PM PDT 24
Finished Jul 14 06:22:06 PM PDT 24
Peak memory 217128 kb
Host smart-0ebe430d-3763-46b9-9ac0-e4deae0434e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249207440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1249207440
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1822137080
Short name T186
Test name
Test status
Simulation time 126484792 ps
CPU time 3.15 seconds
Started Jul 14 06:21:58 PM PDT 24
Finished Jul 14 06:22:02 PM PDT 24
Peak memory 222236 kb
Host smart-032eaa32-4faf-4f4c-8ba9-074ec7bb1ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822137080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1822137080
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2521895085
Short name T453
Test name
Test status
Simulation time 898514391 ps
CPU time 19.07 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 225980 kb
Host smart-28505bf0-93f1-489c-accb-4277cb7ff318
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521895085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2521895085
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2772947239
Short name T99
Test name
Test status
Simulation time 1756921551 ps
CPU time 12.79 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:28 PM PDT 24
Peak memory 225932 kb
Host smart-04f2c6de-1c1a-4419-9e62-35ab19956af3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772947239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2772947239
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1565094778
Short name T477
Test name
Test status
Simulation time 1008052247 ps
CPU time 6.7 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:19 PM PDT 24
Peak memory 218236 kb
Host smart-51d5e544-df89-4dd6-a403-e2e6c52b0089
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565094778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1565094778
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2049589666
Short name T716
Test name
Test status
Simulation time 1565618935 ps
CPU time 8.53 seconds
Started Jul 14 06:21:59 PM PDT 24
Finished Jul 14 06:22:08 PM PDT 24
Peak memory 224660 kb
Host smart-90a47b8c-f34e-43a1-ad34-559ae3720565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049589666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2049589666
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2624343308
Short name T605
Test name
Test status
Simulation time 37228565 ps
CPU time 2.6 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:13 PM PDT 24
Peak memory 214760 kb
Host smart-fac6c7df-262b-434c-8c7b-9d4b3494b0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624343308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2624343308
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3469924424
Short name T549
Test name
Test status
Simulation time 1098311529 ps
CPU time 21.28 seconds
Started Jul 14 06:21:59 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 250952 kb
Host smart-d0b263ef-9d52-4704-8810-26e9c3e56920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469924424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3469924424
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2426727921
Short name T500
Test name
Test status
Simulation time 57134742 ps
CPU time 2.58 seconds
Started Jul 14 06:22:01 PM PDT 24
Finished Jul 14 06:22:04 PM PDT 24
Peak memory 222152 kb
Host smart-f25d9004-1a22-45fa-988e-75e2ccbe5b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426727921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2426727921
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.337835498
Short name T662
Test name
Test status
Simulation time 2687506287 ps
CPU time 129.18 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:24:26 PM PDT 24
Peak memory 226288 kb
Host smart-be60bda4-c4d6-4bfd-bb2f-e9355af950ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337835498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.337835498
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2458672638
Short name T752
Test name
Test status
Simulation time 79060988633 ps
CPU time 614.56 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:32:28 PM PDT 24
Peak memory 340488 kb
Host smart-6c92bad1-0919-4a65-9b70-1d01a6ad30a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2458672638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2458672638
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1653101057
Short name T793
Test name
Test status
Simulation time 34457660 ps
CPU time 0.77 seconds
Started Jul 14 06:22:00 PM PDT 24
Finished Jul 14 06:22:01 PM PDT 24
Peak memory 207104 kb
Host smart-2d1af3a0-7482-4c72-89ec-c98ce113986a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653101057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1653101057
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3945747242
Short name T551
Test name
Test status
Simulation time 125649475 ps
CPU time 0.87 seconds
Started Jul 14 06:22:09 PM PDT 24
Finished Jul 14 06:22:11 PM PDT 24
Peak memory 208964 kb
Host smart-a524aaff-edaa-43d0-a5dc-634e32646c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945747242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3945747242
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4151161893
Short name T660
Test name
Test status
Simulation time 327194966 ps
CPU time 10.3 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 218156 kb
Host smart-b2006e46-40ba-461d-acb0-288879c53d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151161893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4151161893
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.412558586
Short name T26
Test name
Test status
Simulation time 481700774 ps
CPU time 5.36 seconds
Started Jul 14 06:22:12 PM PDT 24
Finished Jul 14 06:22:20 PM PDT 24
Peak memory 217304 kb
Host smart-504580bd-59bf-4617-ba46-614551747083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412558586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.412558586
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3109489843
Short name T291
Test name
Test status
Simulation time 51268676 ps
CPU time 3.15 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:17 PM PDT 24
Peak memory 218220 kb
Host smart-be8a04c6-b70b-44e7-980d-c367caa7f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109489843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3109489843
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1520490955
Short name T795
Test name
Test status
Simulation time 431898141 ps
CPU time 14.42 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:29 PM PDT 24
Peak memory 225688 kb
Host smart-52f6a68b-b846-4c32-a434-0eb310ab7c77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520490955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1520490955
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.714242669
Short name T757
Test name
Test status
Simulation time 1564263754 ps
CPU time 10.22 seconds
Started Jul 14 06:22:09 PM PDT 24
Finished Jul 14 06:22:20 PM PDT 24
Peak memory 225936 kb
Host smart-81250387-3e60-4e45-88b2-1129d64503af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714242669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.714242669
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4105575844
Short name T345
Test name
Test status
Simulation time 1023620117 ps
CPU time 9.4 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:22 PM PDT 24
Peak memory 218232 kb
Host smart-9b7178a1-06e2-43a8-bfa6-ab56015ac4f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105575844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4105575844
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3221213032
Short name T424
Test name
Test status
Simulation time 314880458 ps
CPU time 11.61 seconds
Started Jul 14 06:22:09 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 225984 kb
Host smart-65890212-15da-47f4-9fbd-e1a895564290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221213032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3221213032
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3657584715
Short name T83
Test name
Test status
Simulation time 17961910 ps
CPU time 1.17 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:15 PM PDT 24
Peak memory 212304 kb
Host smart-45f63e5e-0aed-417e-897b-1f250ffd6866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657584715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3657584715
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.499934733
Short name T241
Test name
Test status
Simulation time 285236343 ps
CPU time 31.46 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:47 PM PDT 24
Peak memory 250880 kb
Host smart-55fe1579-9edf-453b-8ecf-cc21b00ee19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499934733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.499934733
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1845966065
Short name T298
Test name
Test status
Simulation time 96386943 ps
CPU time 3.16 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:16 PM PDT 24
Peak memory 222664 kb
Host smart-507fb87b-1f5d-44ef-96cb-2c55c97bf4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845966065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1845966065
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2469577469
Short name T852
Test name
Test status
Simulation time 18219966235 ps
CPU time 147.25 seconds
Started Jul 14 06:22:09 PM PDT 24
Finished Jul 14 06:24:36 PM PDT 24
Peak memory 283688 kb
Host smart-6a020cac-bb95-47b1-b7c9-999bd30b533a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469577469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2469577469
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3163568607
Short name T157
Test name
Test status
Simulation time 63111969984 ps
CPU time 503.54 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:30:38 PM PDT 24
Peak memory 283908 kb
Host smart-b9765930-9a62-40e0-823f-b1f4d0e54f1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3163568607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3163568607
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2325088732
Short name T720
Test name
Test status
Simulation time 14198935 ps
CPU time 0.92 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:17 PM PDT 24
Peak memory 211800 kb
Host smart-ca2b556b-48b4-44b3-83fd-fcc3c1291095
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325088732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2325088732
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2722984316
Short name T447
Test name
Test status
Simulation time 23814442 ps
CPU time 1.28 seconds
Started Jul 14 06:22:16 PM PDT 24
Finished Jul 14 06:22:19 PM PDT 24
Peak memory 209004 kb
Host smart-8601a443-3889-4b0e-8289-97efe291dec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722984316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2722984316
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2193596555
Short name T646
Test name
Test status
Simulation time 358868287 ps
CPU time 9.94 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 218180 kb
Host smart-02839a19-4f7f-4b52-8aa2-59c66ad0df18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193596555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2193596555
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.82994198
Short name T189
Test name
Test status
Simulation time 115573887 ps
CPU time 2.38 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:16 PM PDT 24
Peak memory 217660 kb
Host smart-4c478de9-9af3-47dc-a0b4-4fce13367751
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82994198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.82994198
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.67440344
Short name T833
Test name
Test status
Simulation time 161343269 ps
CPU time 2.84 seconds
Started Jul 14 06:22:09 PM PDT 24
Finished Jul 14 06:22:12 PM PDT 24
Peak memory 218124 kb
Host smart-cc75a8f4-cf08-4632-ba23-35babaa19dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67440344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.67440344
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2843610697
Short name T331
Test name
Test status
Simulation time 970005496 ps
CPU time 10.86 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:25 PM PDT 24
Peak memory 218192 kb
Host smart-c1d518e4-40fb-4d5f-acdd-399d1558f834
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843610697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2843610697
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2585200752
Short name T657
Test name
Test status
Simulation time 905773275 ps
CPU time 8.68 seconds
Started Jul 14 06:22:14 PM PDT 24
Finished Jul 14 06:22:25 PM PDT 24
Peak memory 226032 kb
Host smart-44755ddd-daf1-48f5-bdf6-fd42809955eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585200752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2585200752
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1709256251
Short name T257
Test name
Test status
Simulation time 548518770 ps
CPU time 10.3 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:27 PM PDT 24
Peak memory 225988 kb
Host smart-3c90c45a-f9e0-4cf3-9075-dd7826422915
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709256251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1709256251
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.573699457
Short name T409
Test name
Test status
Simulation time 215184171 ps
CPU time 6.8 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:18 PM PDT 24
Peak memory 218248 kb
Host smart-df04e936-c7a3-46cc-815b-4b425102a3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573699457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.573699457
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1264788249
Short name T65
Test name
Test status
Simulation time 60967913 ps
CPU time 2.52 seconds
Started Jul 14 06:22:10 PM PDT 24
Finished Jul 14 06:22:13 PM PDT 24
Peak memory 214232 kb
Host smart-7cd3df9a-4c5b-48c0-95b7-f38fc26b23b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264788249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1264788249
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3199337999
Short name T236
Test name
Test status
Simulation time 1381240689 ps
CPU time 33.11 seconds
Started Jul 14 06:22:08 PM PDT 24
Finished Jul 14 06:22:42 PM PDT 24
Peak memory 250992 kb
Host smart-366c8c97-479e-4284-925d-009fb86ee17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199337999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3199337999
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1506357747
Short name T513
Test name
Test status
Simulation time 5073010346 ps
CPU time 69.69 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:23:26 PM PDT 24
Peak memory 251168 kb
Host smart-327dcd4e-a0d8-49af-8871-b4598a9e4b1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506357747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1506357747
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2994022760
Short name T187
Test name
Test status
Simulation time 51455808 ps
CPU time 0.84 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:14 PM PDT 24
Peak memory 211780 kb
Host smart-63030bd0-9b88-4ca6-90ce-a176e9a36d44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994022760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2994022760
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1452511879
Short name T740
Test name
Test status
Simulation time 48314263 ps
CPU time 0.82 seconds
Started Jul 14 06:22:15 PM PDT 24
Finished Jul 14 06:22:18 PM PDT 24
Peak memory 208924 kb
Host smart-f2454f0f-0a9a-467e-9378-9d9b0c4cef65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452511879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1452511879
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2620515275
Short name T485
Test name
Test status
Simulation time 1109298712 ps
CPU time 15.4 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 218168 kb
Host smart-9c244f40-6ed3-4065-8ff2-7e235e0f870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620515275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2620515275
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.917593433
Short name T31
Test name
Test status
Simulation time 406283886 ps
CPU time 8.26 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:24 PM PDT 24
Peak memory 217284 kb
Host smart-6278d74d-690b-49ad-a524-a20927d6b350
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917593433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.917593433
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.423590519
Short name T109
Test name
Test status
Simulation time 39384333 ps
CPU time 2.05 seconds
Started Jul 14 06:22:15 PM PDT 24
Finished Jul 14 06:22:19 PM PDT 24
Peak memory 222352 kb
Host smart-ab0ddb7c-0370-47ec-a5ed-885ffd226db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423590519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.423590519
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.396445796
Short name T52
Test name
Test status
Simulation time 533295193 ps
CPU time 13.18 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:33 PM PDT 24
Peak memory 219476 kb
Host smart-f65bade3-bed1-468e-b3d8-7e31771274fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396445796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.396445796
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.910105926
Short name T521
Test name
Test status
Simulation time 1284561233 ps
CPU time 17.22 seconds
Started Jul 14 06:22:12 PM PDT 24
Finished Jul 14 06:22:33 PM PDT 24
Peak memory 225960 kb
Host smart-89d1eb73-e160-4755-8345-6e8cb5dcff69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910105926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.910105926
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1890188776
Short name T545
Test name
Test status
Simulation time 1163946423 ps
CPU time 12.75 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:29 PM PDT 24
Peak memory 225992 kb
Host smart-f5d47a11-5370-49e1-b746-1ad3dc77bd7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890188776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1890188776
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1088666421
Short name T616
Test name
Test status
Simulation time 528719365 ps
CPU time 11.34 seconds
Started Jul 14 06:22:15 PM PDT 24
Finished Jul 14 06:22:28 PM PDT 24
Peak memory 226048 kb
Host smart-751fdbbd-2bd6-41c6-84c0-769f30bead27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088666421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1088666421
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.238381636
Short name T454
Test name
Test status
Simulation time 50094829 ps
CPU time 0.95 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:16 PM PDT 24
Peak memory 211988 kb
Host smart-3e20abac-2c27-4558-a858-b5f7901a0e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238381636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.238381636
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1492600655
Short name T339
Test name
Test status
Simulation time 1214079185 ps
CPU time 31.34 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:51 PM PDT 24
Peak memory 250096 kb
Host smart-d9c037e3-2b69-41dd-8962-f2757b1deffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492600655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1492600655
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1182551940
Short name T865
Test name
Test status
Simulation time 1030251274 ps
CPU time 7.49 seconds
Started Jul 14 06:22:15 PM PDT 24
Finished Jul 14 06:22:24 PM PDT 24
Peak memory 248536 kb
Host smart-9ec8090b-e40e-4d0f-997d-9af908be8dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182551940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1182551940
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.866810682
Short name T561
Test name
Test status
Simulation time 10198567157 ps
CPU time 64.3 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:23:20 PM PDT 24
Peak memory 251240 kb
Host smart-20ff8e7e-7d1d-4a00-86bf-3f328d9209f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866810682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.866810682
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2476432974
Short name T97
Test name
Test status
Simulation time 269781201526 ps
CPU time 1478.43 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:46:53 PM PDT 24
Peak memory 497036 kb
Host smart-5afb5d35-c8de-4d62-836c-827f1e8cbdd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2476432974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2476432974
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1992408076
Short name T573
Test name
Test status
Simulation time 64857915 ps
CPU time 0.95 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:20 PM PDT 24
Peak memory 211616 kb
Host smart-e703c154-4a4c-46e7-bab3-c63766148add
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992408076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1992408076
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2165218421
Short name T446
Test name
Test status
Simulation time 18463991 ps
CPU time 0.92 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 209040 kb
Host smart-20882f82-9228-479b-b2e3-72a1e8c2c2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165218421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2165218421
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1290720680
Short name T115
Test name
Test status
Simulation time 207836234 ps
CPU time 10.22 seconds
Started Jul 14 06:22:12 PM PDT 24
Finished Jul 14 06:22:25 PM PDT 24
Peak memory 226032 kb
Host smart-e8037c52-2e6e-42d5-a2ed-47f519c09abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290720680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1290720680
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1730849216
Short name T749
Test name
Test status
Simulation time 170267658 ps
CPU time 4.77 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:20 PM PDT 24
Peak memory 217692 kb
Host smart-527bc63d-1aed-46d5-8227-7e1e449cc8b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730849216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1730849216
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3749060557
Short name T465
Test name
Test status
Simulation time 689362918 ps
CPU time 4.32 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 218196 kb
Host smart-2541ae38-b487-46c6-83e8-c43defbdcc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749060557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3749060557
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2565502597
Short name T377
Test name
Test status
Simulation time 264276269 ps
CPU time 13.76 seconds
Started Jul 14 06:22:13 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 226024 kb
Host smart-1db15062-fb30-440c-b8d4-8873393be872
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565502597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2565502597
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1020101042
Short name T441
Test name
Test status
Simulation time 1050347173 ps
CPU time 12.27 seconds
Started Jul 14 06:22:19 PM PDT 24
Finished Jul 14 06:22:33 PM PDT 24
Peak memory 226008 kb
Host smart-3b59906c-f10c-4d44-a31b-5138a929ddf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020101042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1020101042
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1676033361
Short name T280
Test name
Test status
Simulation time 1056486807 ps
CPU time 8.58 seconds
Started Jul 14 06:22:11 PM PDT 24
Finished Jul 14 06:22:23 PM PDT 24
Peak memory 218252 kb
Host smart-b53bf2d6-6413-4275-ad5a-34e8cf866a84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676033361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1676033361
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.144237482
Short name T51
Test name
Test status
Simulation time 395796052 ps
CPU time 13.87 seconds
Started Jul 14 06:22:15 PM PDT 24
Finished Jul 14 06:22:31 PM PDT 24
Peak memory 218252 kb
Host smart-dc691872-d4f2-4bd5-ac1d-f98616a009fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144237482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.144237482
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3639280192
Short name T524
Test name
Test status
Simulation time 184534271 ps
CPU time 3.4 seconds
Started Jul 14 06:22:15 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 217620 kb
Host smart-8eb3f9bc-1552-4a2b-a390-42d035ae4e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639280192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3639280192
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3644132308
Short name T679
Test name
Test status
Simulation time 318683918 ps
CPU time 29.65 seconds
Started Jul 14 06:22:12 PM PDT 24
Finished Jul 14 06:22:44 PM PDT 24
Peak memory 247268 kb
Host smart-4401e97f-ca7b-4b9e-8f8a-196aa645904f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644132308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3644132308
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1528955665
Short name T611
Test name
Test status
Simulation time 377118274 ps
CPU time 10.84 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 250476 kb
Host smart-85e3e505-8e31-470f-966a-9838342d9979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528955665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1528955665
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1751412559
Short name T472
Test name
Test status
Simulation time 10537956998 ps
CPU time 114.13 seconds
Started Jul 14 06:22:16 PM PDT 24
Finished Jul 14 06:24:12 PM PDT 24
Peak memory 256136 kb
Host smart-103d9500-b8bb-435e-b98c-3bde9b19217e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751412559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1751412559
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2308655728
Short name T509
Test name
Test status
Simulation time 15126142 ps
CPU time 0.87 seconds
Started Jul 14 06:22:16 PM PDT 24
Finished Jul 14 06:22:19 PM PDT 24
Peak memory 211880 kb
Host smart-82d6d80d-1cdf-4790-9db5-6b375d45a47f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308655728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2308655728
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.142860641
Short name T528
Test name
Test status
Simulation time 72704213 ps
CPU time 0.84 seconds
Started Jul 14 06:22:21 PM PDT 24
Finished Jul 14 06:22:22 PM PDT 24
Peak memory 208936 kb
Host smart-ee836876-7ef1-415b-8022-8229f2677698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142860641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.142860641
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1245703527
Short name T481
Test name
Test status
Simulation time 1674043448 ps
CPU time 10.6 seconds
Started Jul 14 06:22:22 PM PDT 24
Finished Jul 14 06:22:33 PM PDT 24
Peak memory 218108 kb
Host smart-b220c9f4-1ec8-42e4-a8b1-5437eafc072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245703527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1245703527
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2587666086
Short name T690
Test name
Test status
Simulation time 483432678 ps
CPU time 5.49 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:25 PM PDT 24
Peak memory 217180 kb
Host smart-e42cd8b1-04ef-4efe-bbd2-1a325005e1d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587666086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2587666086
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1611000224
Short name T338
Test name
Test status
Simulation time 114219565 ps
CPU time 2.85 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:23 PM PDT 24
Peak memory 218248 kb
Host smart-5233827f-ac40-4972-aec9-6a16c4f976ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611000224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1611000224
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.4024590627
Short name T106
Test name
Test status
Simulation time 582457825 ps
CPU time 7.97 seconds
Started Jul 14 06:22:19 PM PDT 24
Finished Jul 14 06:22:29 PM PDT 24
Peak memory 226044 kb
Host smart-4ec57866-1db2-4b2e-b09c-3d2953f1731c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024590627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.4024590627
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3797704873
Short name T262
Test name
Test status
Simulation time 298248373 ps
CPU time 8.53 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:29 PM PDT 24
Peak memory 225644 kb
Host smart-de315a3c-f89a-48ba-b0fe-f0909adf1a8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797704873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3797704873
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.234231035
Short name T714
Test name
Test status
Simulation time 651628397 ps
CPU time 12.37 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 226032 kb
Host smart-b816ce8f-ca17-457d-b204-7b628b61b8e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234231035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.234231035
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1931893034
Short name T294
Test name
Test status
Simulation time 39761149 ps
CPU time 0.95 seconds
Started Jul 14 06:22:16 PM PDT 24
Finished Jul 14 06:22:19 PM PDT 24
Peak memory 217628 kb
Host smart-4d116e2b-c1e3-463f-826f-d79a5cb8869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931893034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1931893034
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2154400966
Short name T325
Test name
Test status
Simulation time 1023673170 ps
CPU time 21.17 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:41 PM PDT 24
Peak memory 250988 kb
Host smart-89560d2b-f975-4782-8429-0ee3193123b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154400966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2154400966
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1275515867
Short name T95
Test name
Test status
Simulation time 62428026 ps
CPU time 8.16 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:28 PM PDT 24
Peak memory 250972 kb
Host smart-0918c9a4-98e4-42fb-aff1-184bcad0ea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275515867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1275515867
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.4206028524
Short name T637
Test name
Test status
Simulation time 14840705910 ps
CPU time 236.2 seconds
Started Jul 14 06:22:19 PM PDT 24
Finished Jul 14 06:26:17 PM PDT 24
Peak memory 273892 kb
Host smart-f0275b90-d95c-4de5-b012-70b6ca8e4e63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206028524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.4206028524
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3737773467
Short name T518
Test name
Test status
Simulation time 47713366 ps
CPU time 0.91 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 211752 kb
Host smart-5b5c97c8-9840-44cd-8fd1-858ca773ef9a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737773467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3737773467
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1283262641
Short name T351
Test name
Test status
Simulation time 106904225 ps
CPU time 0.99 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:20 PM PDT 24
Peak memory 208992 kb
Host smart-7e7236a7-1daa-4b9e-9497-7a7d1dcc3151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283262641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1283262641
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3454834682
Short name T112
Test name
Test status
Simulation time 676680401 ps
CPU time 8.95 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:28 PM PDT 24
Peak memory 218260 kb
Host smart-ea0ad639-cad0-415b-be4c-83240f0ddbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454834682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3454834682
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1685445586
Short name T625
Test name
Test status
Simulation time 141428804 ps
CPU time 2.22 seconds
Started Jul 14 06:22:22 PM PDT 24
Finished Jul 14 06:22:25 PM PDT 24
Peak memory 217268 kb
Host smart-e89cd9fd-373e-4704-9cf6-5e55369c920c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685445586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1685445586
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.163069379
Short name T434
Test name
Test status
Simulation time 65372836 ps
CPU time 2.62 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:23 PM PDT 24
Peak memory 222344 kb
Host smart-96baaee6-f40e-4de7-b4dc-22f429eb344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163069379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.163069379
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2116997317
Short name T713
Test name
Test status
Simulation time 219148377 ps
CPU time 8.33 seconds
Started Jul 14 06:22:22 PM PDT 24
Finished Jul 14 06:22:31 PM PDT 24
Peak memory 226016 kb
Host smart-5ba49145-9419-4c22-8f85-6d4e6c5f4de6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116997317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2116997317
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1725053080
Short name T271
Test name
Test status
Simulation time 378128399 ps
CPU time 11.88 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:32 PM PDT 24
Peak memory 225932 kb
Host smart-baf238f1-ab30-4a8e-87bb-9523becfab60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725053080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1725053080
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.927793840
Short name T697
Test name
Test status
Simulation time 586958016 ps
CPU time 7.95 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:27 PM PDT 24
Peak memory 218216 kb
Host smart-d779c89b-b849-43c3-8446-5be50147e80a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927793840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.927793840
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1247037991
Short name T661
Test name
Test status
Simulation time 277706907 ps
CPU time 6.72 seconds
Started Jul 14 06:22:23 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 218300 kb
Host smart-4fd9db2c-a068-48ce-a109-388d68d9596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247037991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1247037991
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3621730773
Short name T621
Test name
Test status
Simulation time 80201744 ps
CPU time 2.23 seconds
Started Jul 14 06:22:17 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 214204 kb
Host smart-d95350a8-ffbd-4763-b716-25dc14a67cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621730773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3621730773
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.145996115
Short name T244
Test name
Test status
Simulation time 398799184 ps
CPU time 18.58 seconds
Started Jul 14 06:22:22 PM PDT 24
Finished Jul 14 06:22:41 PM PDT 24
Peak memory 250940 kb
Host smart-909cfb20-0e09-41bf-a69a-dd6a736fbcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145996115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.145996115
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1967994620
Short name T328
Test name
Test status
Simulation time 272771598 ps
CPU time 7.33 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:27 PM PDT 24
Peak memory 250536 kb
Host smart-77f3d052-95ff-4ac0-aa6a-5197a9a6f336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967994620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1967994620
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1210944000
Short name T184
Test name
Test status
Simulation time 18972939697 ps
CPU time 208.04 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:25:48 PM PDT 24
Peak memory 422004 kb
Host smart-6d2040f7-8ed2-4c4d-93c9-f484b90823e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210944000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1210944000
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.809781367
Short name T546
Test name
Test status
Simulation time 80329877117 ps
CPU time 396.34 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:28:57 PM PDT 24
Peak memory 283912 kb
Host smart-7442685e-8333-4b08-a15a-135c4ecde122
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=809781367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.809781367
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4146257299
Short name T406
Test name
Test status
Simulation time 19000112 ps
CPU time 0.82 seconds
Started Jul 14 06:22:18 PM PDT 24
Finished Jul 14 06:22:21 PM PDT 24
Peak memory 211880 kb
Host smart-91814223-28d8-4f5d-87d7-5cbba02081cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146257299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4146257299
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2342290057
Short name T72
Test name
Test status
Simulation time 75661220 ps
CPU time 1.05 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:34 PM PDT 24
Peak memory 209036 kb
Host smart-ef2f28f6-cf14-4e6d-950a-d89512a1be07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342290057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2342290057
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1053833571
Short name T245
Test name
Test status
Simulation time 307321188 ps
CPU time 13.61 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:46 PM PDT 24
Peak memory 225948 kb
Host smart-86642e84-6a79-4a35-91c5-ced30d669046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053833571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1053833571
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2478806827
Short name T198
Test name
Test status
Simulation time 368016344 ps
CPU time 4.77 seconds
Started Jul 14 06:22:25 PM PDT 24
Finished Jul 14 06:22:31 PM PDT 24
Peak memory 217352 kb
Host smart-83f21852-23c1-4633-af69-226005bbd4f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478806827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2478806827
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2718299570
Short name T259
Test name
Test status
Simulation time 63801162 ps
CPU time 3.49 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:35 PM PDT 24
Peak memory 218216 kb
Host smart-05fc20c9-34ad-4c33-a617-0e143c5c4753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718299570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2718299570
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2421182614
Short name T404
Test name
Test status
Simulation time 2492566124 ps
CPU time 16.6 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:49 PM PDT 24
Peak memory 226080 kb
Host smart-298bc006-f24d-46ce-b53a-46bf05375c53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421182614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2421182614
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3303475547
Short name T444
Test name
Test status
Simulation time 7777068971 ps
CPU time 15.18 seconds
Started Jul 14 06:22:24 PM PDT 24
Finished Jul 14 06:22:40 PM PDT 24
Peak memory 226096 kb
Host smart-c6e38ab5-2326-4e90-a21c-b4bbe350c4fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303475547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3303475547
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.797951312
Short name T356
Test name
Test status
Simulation time 580065083 ps
CPU time 9.56 seconds
Started Jul 14 06:22:26 PM PDT 24
Finished Jul 14 06:22:36 PM PDT 24
Peak memory 218212 kb
Host smart-457cd719-76d4-4fb7-826a-20594d112b6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797951312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.797951312
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3521072580
Short name T390
Test name
Test status
Simulation time 620662759 ps
CPU time 19.96 seconds
Started Jul 14 06:22:23 PM PDT 24
Finished Jul 14 06:22:44 PM PDT 24
Peak memory 225992 kb
Host smart-9bfe5d72-36dd-4b18-ac7d-dc0a0e3193f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521072580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3521072580
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2922209614
Short name T461
Test name
Test status
Simulation time 47150096 ps
CPU time 1.65 seconds
Started Jul 14 06:22:25 PM PDT 24
Finished Jul 14 06:22:27 PM PDT 24
Peak memory 217712 kb
Host smart-7a632685-452c-496f-b685-01319479b0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922209614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2922209614
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2858659274
Short name T267
Test name
Test status
Simulation time 281997971 ps
CPU time 25.34 seconds
Started Jul 14 06:22:24 PM PDT 24
Finished Jul 14 06:22:50 PM PDT 24
Peak memory 250880 kb
Host smart-72398066-a77a-4911-a97d-ecab9cae1749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858659274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2858659274
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1422982818
Short name T387
Test name
Test status
Simulation time 370692743 ps
CPU time 3.72 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:37 PM PDT 24
Peak memory 218148 kb
Host smart-28830079-7996-4950-bd49-73a07f2f53a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422982818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1422982818
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2119642037
Short name T776
Test name
Test status
Simulation time 15742614 ps
CPU time 0.98 seconds
Started Jul 14 06:22:26 PM PDT 24
Finished Jul 14 06:22:28 PM PDT 24
Peak memory 211816 kb
Host smart-e8bb4246-727a-4aa2-ad8d-d99e47529898
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119642037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2119642037
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1927477998
Short name T819
Test name
Test status
Simulation time 21691868 ps
CPU time 1.17 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:33 PM PDT 24
Peak memory 208984 kb
Host smart-32026d11-86cb-497e-925e-c24f45439d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927477998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1927477998
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1216578989
Short name T694
Test name
Test status
Simulation time 400045403 ps
CPU time 18.16 seconds
Started Jul 14 06:22:26 PM PDT 24
Finished Jul 14 06:22:45 PM PDT 24
Peak memory 218264 kb
Host smart-5aebb749-c60d-4f94-8463-777bc1c38cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216578989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1216578989
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1834167950
Short name T813
Test name
Test status
Simulation time 1427016285 ps
CPU time 9.17 seconds
Started Jul 14 06:22:25 PM PDT 24
Finished Jul 14 06:22:35 PM PDT 24
Peak memory 217100 kb
Host smart-88f60f4e-49d3-43b3-a425-369ffd8c455a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834167950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1834167950
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1072958305
Short name T359
Test name
Test status
Simulation time 197331727 ps
CPU time 2.79 seconds
Started Jul 14 06:22:24 PM PDT 24
Finished Jul 14 06:22:28 PM PDT 24
Peak memory 222368 kb
Host smart-fa30db70-aaaa-480b-9f2a-a2a96d35f0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072958305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1072958305
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1534027012
Short name T379
Test name
Test status
Simulation time 1085881238 ps
CPU time 13.61 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:44 PM PDT 24
Peak memory 225984 kb
Host smart-9bd221fc-1835-4e2f-bf02-2703a0032370
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534027012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1534027012
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.163992070
Short name T118
Test name
Test status
Simulation time 790138116 ps
CPU time 9.51 seconds
Started Jul 14 06:22:27 PM PDT 24
Finished Jul 14 06:22:37 PM PDT 24
Peak memory 225976 kb
Host smart-f514064f-a6fc-4d1e-a4a5-bd7329077ce5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163992070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.163992070
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1817030514
Short name T62
Test name
Test status
Simulation time 724589171 ps
CPU time 13.05 seconds
Started Jul 14 06:22:23 PM PDT 24
Finished Jul 14 06:22:37 PM PDT 24
Peak memory 218204 kb
Host smart-2720ddad-7776-41e1-946f-f7c3ffc2e384
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817030514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1817030514
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2489664352
Short name T739
Test name
Test status
Simulation time 829833277 ps
CPU time 9.78 seconds
Started Jul 14 06:22:25 PM PDT 24
Finished Jul 14 06:22:36 PM PDT 24
Peak memory 226336 kb
Host smart-1c659104-d57d-4a6b-b74e-5acdd782bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489664352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2489664352
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2437583907
Short name T837
Test name
Test status
Simulation time 115567585 ps
CPU time 1.3 seconds
Started Jul 14 06:22:25 PM PDT 24
Finished Jul 14 06:22:27 PM PDT 24
Peak memory 217404 kb
Host smart-26fd0c3b-c4f2-4260-b72a-48c81791bdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437583907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2437583907
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.430692460
Short name T457
Test name
Test status
Simulation time 924566802 ps
CPU time 20.54 seconds
Started Jul 14 06:22:26 PM PDT 24
Finished Jul 14 06:22:47 PM PDT 24
Peak memory 250972 kb
Host smart-382aeb6c-b875-4083-b0f7-cc2db3d0901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430692460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.430692460
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2148988025
Short name T304
Test name
Test status
Simulation time 81924641 ps
CPU time 3.82 seconds
Started Jul 14 06:22:24 PM PDT 24
Finished Jul 14 06:22:28 PM PDT 24
Peak memory 222484 kb
Host smart-a7b257aa-84c7-4773-8c19-756b5aaad382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148988025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2148988025
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.351348039
Short name T76
Test name
Test status
Simulation time 13660319989 ps
CPU time 427.14 seconds
Started Jul 14 06:22:25 PM PDT 24
Finished Jul 14 06:29:33 PM PDT 24
Peak memory 267412 kb
Host smart-54add4fa-df40-4a7c-857a-907ac10b0e9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351348039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.351348039
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3625437422
Short name T622
Test name
Test status
Simulation time 24536941 ps
CPU time 0.87 seconds
Started Jul 14 06:22:22 PM PDT 24
Finished Jul 14 06:22:24 PM PDT 24
Peak memory 211884 kb
Host smart-0d488d32-4a40-4ca4-b8e4-bec774fbbf45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625437422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3625437422
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.996197779
Short name T613
Test name
Test status
Simulation time 20728656 ps
CPU time 0.82 seconds
Started Jul 14 06:22:29 PM PDT 24
Finished Jul 14 06:22:30 PM PDT 24
Peak memory 209020 kb
Host smart-6b4c0315-8592-4754-a9a3-87d89850b39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996197779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.996197779
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3838933083
Short name T19
Test name
Test status
Simulation time 1572621601 ps
CPU time 12.15 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:45 PM PDT 24
Peak memory 218144 kb
Host smart-4f5de53b-d515-4648-a6ad-6ddc6692a139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838933083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3838933083
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.7193114
Short name T826
Test name
Test status
Simulation time 1312224714 ps
CPU time 7.92 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:39 PM PDT 24
Peak memory 217280 kb
Host smart-11ce8af0-c666-4d21-9f1b-6629003767a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7193114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.7193114
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1458869668
Short name T110
Test name
Test status
Simulation time 82235505 ps
CPU time 3.76 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:36 PM PDT 24
Peak memory 218196 kb
Host smart-c9971d32-b471-4ffa-8b9c-83d150e39c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458869668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1458869668
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3920945508
Short name T413
Test name
Test status
Simulation time 1980839934 ps
CPU time 16.91 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:48 PM PDT 24
Peak memory 226020 kb
Host smart-9569b465-fdd9-4561-95db-d7eb63366a94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920945508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3920945508
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1231347504
Short name T416
Test name
Test status
Simulation time 469205822 ps
CPU time 17.7 seconds
Started Jul 14 06:22:32 PM PDT 24
Finished Jul 14 06:22:52 PM PDT 24
Peak memory 225940 kb
Host smart-ac08ca22-d7e1-4aec-bf87-603fbad29367
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231347504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1231347504
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.586295174
Short name T476
Test name
Test status
Simulation time 1075298007 ps
CPU time 7.18 seconds
Started Jul 14 06:22:32 PM PDT 24
Finished Jul 14 06:22:41 PM PDT 24
Peak memory 225352 kb
Host smart-f15679be-2ef2-44a6-a00c-2e96b4c4e9dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586295174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.586295174
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2053281943
Short name T414
Test name
Test status
Simulation time 1791704291 ps
CPU time 11.65 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:44 PM PDT 24
Peak memory 225988 kb
Host smart-dcb9d51d-e024-4f3a-902b-203289af14ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053281943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2053281943
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2056447742
Short name T467
Test name
Test status
Simulation time 17337979 ps
CPU time 1.3 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:34 PM PDT 24
Peak memory 217704 kb
Host smart-d2578b2f-a5fc-4f7c-a00d-c6dd14578f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056447742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2056447742
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2779379393
Short name T493
Test name
Test status
Simulation time 693645634 ps
CPU time 18.08 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:50 PM PDT 24
Peak memory 250960 kb
Host smart-2844cc45-bbda-4a5a-8348-52a5849df3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779379393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2779379393
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2840524301
Short name T117
Test name
Test status
Simulation time 59639780 ps
CPU time 10.47 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:43 PM PDT 24
Peak memory 250976 kb
Host smart-109185a9-cdb7-492c-b502-73b0ba7be168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840524301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2840524301
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4091787631
Short name T649
Test name
Test status
Simulation time 2988952879 ps
CPU time 25.51 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:59 PM PDT 24
Peak memory 250956 kb
Host smart-fcd57fa9-d098-40a9-8020-e6a8681e7c80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091787631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4091787631
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3241001369
Short name T313
Test name
Test status
Simulation time 10462739 ps
CPU time 1.01 seconds
Started Jul 14 06:22:32 PM PDT 24
Finished Jul 14 06:22:35 PM PDT 24
Peak memory 211860 kb
Host smart-127eae30-d62d-47c4-9d33-9737767c0896
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241001369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3241001369
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3488197617
Short name T407
Test name
Test status
Simulation time 27247654 ps
CPU time 1.02 seconds
Started Jul 14 06:20:54 PM PDT 24
Finished Jul 14 06:20:57 PM PDT 24
Peak memory 208952 kb
Host smart-e2be7b24-f740-4aee-8125-0d170643d5c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488197617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3488197617
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1427722080
Short name T364
Test name
Test status
Simulation time 12345586 ps
CPU time 0.82 seconds
Started Jul 14 06:20:42 PM PDT 24
Finished Jul 14 06:20:45 PM PDT 24
Peak memory 208976 kb
Host smart-b031ed50-9f83-405d-affa-b8a19922a148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427722080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1427722080
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3653381852
Short name T431
Test name
Test status
Simulation time 67950876 ps
CPU time 2.36 seconds
Started Jul 14 06:20:49 PM PDT 24
Finished Jul 14 06:20:52 PM PDT 24
Peak memory 216968 kb
Host smart-d214e475-376b-4b5f-8e07-525c7e8007f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653381852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3653381852
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1681840558
Short name T172
Test name
Test status
Simulation time 17897375613 ps
CPU time 51.76 seconds
Started Jul 14 06:20:50 PM PDT 24
Finished Jul 14 06:21:43 PM PDT 24
Peak memory 218932 kb
Host smart-80266d61-8034-4372-841f-210198befbde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681840558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1681840558
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3443112801
Short name T67
Test name
Test status
Simulation time 2180570840 ps
CPU time 2.06 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:20:56 PM PDT 24
Peak memory 217856 kb
Host smart-7804889c-ec98-4d48-b842-6636bea836a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443112801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
443112801
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.498427085
Short name T335
Test name
Test status
Simulation time 207777308 ps
CPU time 2.76 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:20:55 PM PDT 24
Peak memory 221692 kb
Host smart-04da5b8a-6f8b-46e8-afda-031d295ded7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498427085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.498427085
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.624093639
Short name T862
Test name
Test status
Simulation time 2797727166 ps
CPU time 9.75 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:21:03 PM PDT 24
Peak memory 217836 kb
Host smart-302a1ce3-cf16-448a-9e41-78da19543690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624093639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.624093639
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3591740668
Short name T825
Test name
Test status
Simulation time 1421781691 ps
CPU time 10.06 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:21:03 PM PDT 24
Peak memory 217780 kb
Host smart-9c7c9928-8237-4321-ac65-fa1afd28dcce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591740668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3591740668
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.602628759
Short name T846
Test name
Test status
Simulation time 8489838456 ps
CPU time 49.88 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:21:44 PM PDT 24
Peak memory 279000 kb
Host smart-1ad2b464-a064-42b6-afac-92691b8a0c71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602628759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.602628759
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.93910899
Short name T727
Test name
Test status
Simulation time 612682524 ps
CPU time 22.94 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:21:14 PM PDT 24
Peak memory 250872 kb
Host smart-de2160c8-340b-41bb-b72d-ff4ae224a8bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93910899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_state_post_trans.93910899
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4047911061
Short name T787
Test name
Test status
Simulation time 46596148 ps
CPU time 2.06 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:44 PM PDT 24
Peak memory 222024 kb
Host smart-09abc74f-62ae-4f43-9134-528e9be19d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047911061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4047911061
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.519309713
Short name T57
Test name
Test status
Simulation time 1413178508 ps
CPU time 8.81 seconds
Started Jul 14 06:20:43 PM PDT 24
Finished Jul 14 06:20:53 PM PDT 24
Peak memory 214652 kb
Host smart-27e170e4-4a38-49ce-b5a9-1cae2f32d92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519309713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.519309713
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2819610145
Short name T113
Test name
Test status
Simulation time 115631766 ps
CPU time 23.95 seconds
Started Jul 14 06:20:54 PM PDT 24
Finished Jul 14 06:21:20 PM PDT 24
Peak memory 268428 kb
Host smart-da5d0296-c333-4074-b359-b6440f9e22f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819610145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2819610145
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2260787865
Short name T520
Test name
Test status
Simulation time 340119293 ps
CPU time 13.86 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:21:06 PM PDT 24
Peak memory 226044 kb
Host smart-bf123b98-929f-45cb-aeaf-d4f47321c998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260787865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2260787865
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.142277674
Short name T239
Test name
Test status
Simulation time 1010429730 ps
CPU time 7.47 seconds
Started Jul 14 06:20:49 PM PDT 24
Finished Jul 14 06:20:57 PM PDT 24
Peak memory 226044 kb
Host smart-91bd32ce-6842-4316-87c1-d699a8b4423b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142277674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.142277674
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.927117333
Short name T586
Test name
Test status
Simulation time 1601876218 ps
CPU time 6.81 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:20:58 PM PDT 24
Peak memory 218228 kb
Host smart-9df3bd46-989c-4ced-b148-eefe82020853
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927117333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.927117333
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2824974749
Short name T537
Test name
Test status
Simulation time 380694283 ps
CPU time 8.05 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:51 PM PDT 24
Peak memory 224980 kb
Host smart-c1a0be6d-b6fc-4b2e-ac37-a9b04e86d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824974749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2824974749
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1230833112
Short name T479
Test name
Test status
Simulation time 43053811 ps
CPU time 1.29 seconds
Started Jul 14 06:20:41 PM PDT 24
Finished Jul 14 06:20:43 PM PDT 24
Peak memory 217684 kb
Host smart-dd23d1b7-4289-4e93-9ea0-bb58e8827b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230833112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1230833112
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.480744573
Short name T360
Test name
Test status
Simulation time 516347165 ps
CPU time 24.96 seconds
Started Jul 14 06:20:45 PM PDT 24
Finished Jul 14 06:21:10 PM PDT 24
Peak memory 250872 kb
Host smart-dda84cf2-1b89-4565-8885-bd96454d1ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480744573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.480744573
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.134444444
Short name T750
Test name
Test status
Simulation time 514283983 ps
CPU time 3.36 seconds
Started Jul 14 06:20:45 PM PDT 24
Finished Jul 14 06:20:49 PM PDT 24
Peak memory 226400 kb
Host smart-7db3c190-477a-4ffd-91bf-80380f999564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134444444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.134444444
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1655763800
Short name T456
Test name
Test status
Simulation time 4410949680 ps
CPU time 81.58 seconds
Started Jul 14 06:20:50 PM PDT 24
Finished Jul 14 06:22:12 PM PDT 24
Peak memory 234600 kb
Host smart-6b7edffe-2c14-46a2-be98-25e8a8a74491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655763800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1655763800
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1493823451
Short name T478
Test name
Test status
Simulation time 12147513 ps
CPU time 1 seconds
Started Jul 14 06:20:40 PM PDT 24
Finished Jul 14 06:20:43 PM PDT 24
Peak memory 211920 kb
Host smart-7b89b596-0dd5-4fed-935a-64e3a9c77589
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493823451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1493823451
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1124716456
Short name T459
Test name
Test status
Simulation time 15669212 ps
CPU time 1.1 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:34 PM PDT 24
Peak memory 208884 kb
Host smart-d35daf97-662e-497a-be04-a8cfdb3a6c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124716456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1124716456
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3662423846
Short name T232
Test name
Test status
Simulation time 814545877 ps
CPU time 11.73 seconds
Started Jul 14 06:22:32 PM PDT 24
Finished Jul 14 06:22:45 PM PDT 24
Peak memory 226020 kb
Host smart-a5182192-9a16-4450-b399-b7b117089804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662423846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3662423846
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2297360502
Short name T585
Test name
Test status
Simulation time 310342806 ps
CPU time 4.72 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:38 PM PDT 24
Peak memory 217396 kb
Host smart-af6d22ec-2cb2-4a5e-8542-7b125e42f1b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297360502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2297360502
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1295743078
Short name T464
Test name
Test status
Simulation time 45952747 ps
CPU time 2.75 seconds
Started Jul 14 06:22:40 PM PDT 24
Finished Jul 14 06:22:43 PM PDT 24
Peak memory 218180 kb
Host smart-32082225-13b6-4edf-806b-c65c6835a508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295743078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1295743078
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1378609171
Short name T38
Test name
Test status
Simulation time 1467987144 ps
CPU time 14.83 seconds
Started Jul 14 06:22:32 PM PDT 24
Finished Jul 14 06:22:49 PM PDT 24
Peak memory 218880 kb
Host smart-fc34d054-4b07-4e0e-b26a-9fcbc6ab9e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378609171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1378609171
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.305382394
Short name T104
Test name
Test status
Simulation time 4819076779 ps
CPU time 9.14 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:43 PM PDT 24
Peak memory 226108 kb
Host smart-398af35f-5435-40e5-8285-ad7b00cfcdaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305382394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.305382394
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.417253038
Short name T363
Test name
Test status
Simulation time 1038157331 ps
CPU time 10.19 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:43 PM PDT 24
Peak memory 224772 kb
Host smart-f4958cb2-4f36-4d42-aba0-817ecc212541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417253038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.417253038
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1309795489
Short name T423
Test name
Test status
Simulation time 20140650 ps
CPU time 1.38 seconds
Started Jul 14 06:22:33 PM PDT 24
Finished Jul 14 06:22:35 PM PDT 24
Peak memory 217676 kb
Host smart-ea370e3b-c687-4c08-aeba-acadac11ccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309795489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1309795489
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3926741724
Short name T530
Test name
Test status
Simulation time 776568653 ps
CPU time 22.17 seconds
Started Jul 14 06:22:36 PM PDT 24
Finished Jul 14 06:22:59 PM PDT 24
Peak memory 250936 kb
Host smart-f239b93a-7e25-41be-a1c8-044d6fddb669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926741724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3926741724
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1350750068
Short name T522
Test name
Test status
Simulation time 54821891 ps
CPU time 8.25 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:41 PM PDT 24
Peak memory 250968 kb
Host smart-4494a2e0-7d3e-482a-bd51-80e909b9d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350750068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1350750068
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3230913432
Short name T308
Test name
Test status
Simulation time 7361657994 ps
CPU time 177.37 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:25:31 PM PDT 24
Peak memory 251044 kb
Host smart-6e8eaad7-6983-45ec-93b7-a3bee83241d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230913432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3230913432
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3396930112
Short name T275
Test name
Test status
Simulation time 12865490 ps
CPU time 1.04 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:34 PM PDT 24
Peak memory 211840 kb
Host smart-55cf0639-5598-4796-8cad-9adf62d935e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396930112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3396930112
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1797815251
Short name T269
Test name
Test status
Simulation time 1557802621 ps
CPU time 13.96 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:46 PM PDT 24
Peak memory 218260 kb
Host smart-81ed999f-caaf-4a4b-8f80-12e535638dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797815251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1797815251
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1113831754
Short name T455
Test name
Test status
Simulation time 203545244 ps
CPU time 5.54 seconds
Started Jul 14 06:22:32 PM PDT 24
Finished Jul 14 06:22:39 PM PDT 24
Peak memory 217040 kb
Host smart-cfd0351b-7f44-408e-ac6d-b31eeb0c239e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113831754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1113831754
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3211157727
Short name T82
Test name
Test status
Simulation time 18530014 ps
CPU time 1.73 seconds
Started Jul 14 06:22:33 PM PDT 24
Finished Jul 14 06:22:36 PM PDT 24
Peak memory 218072 kb
Host smart-bbd42b17-5fd4-425a-aeea-584cbed0ac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211157727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3211157727
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2723315755
Short name T624
Test name
Test status
Simulation time 281885823 ps
CPU time 13.44 seconds
Started Jul 14 06:22:39 PM PDT 24
Finished Jul 14 06:22:53 PM PDT 24
Peak memory 218876 kb
Host smart-ec88e778-6251-43ec-bef6-8cc8658fd7e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723315755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2723315755
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.817808678
Short name T759
Test name
Test status
Simulation time 358862105 ps
CPU time 9.26 seconds
Started Jul 14 06:22:37 PM PDT 24
Finished Jul 14 06:22:47 PM PDT 24
Peak memory 226020 kb
Host smart-66f66a74-3dba-41c9-8a89-92b7b71ad5ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817808678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.817808678
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1926241725
Short name T319
Test name
Test status
Simulation time 638060010 ps
CPU time 19.39 seconds
Started Jul 14 06:22:38 PM PDT 24
Finished Jul 14 06:22:58 PM PDT 24
Peak memory 218140 kb
Host smart-27bbbdce-c4f4-44e1-ba1f-5144865724a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926241725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1926241725
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.4281011753
Short name T588
Test name
Test status
Simulation time 830573103 ps
CPU time 7.71 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:51 PM PDT 24
Peak memory 225996 kb
Host smart-f8083c6a-899d-4f60-99e2-a923fc3558b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281011753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.4281011753
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.24779275
Short name T70
Test name
Test status
Simulation time 194204317 ps
CPU time 2.84 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:47 PM PDT 24
Peak memory 214748 kb
Host smart-dae07e0e-3129-4b56-9cb1-882965d15d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24779275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.24779275
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1172045236
Short name T801
Test name
Test status
Simulation time 1258953810 ps
CPU time 20.29 seconds
Started Jul 14 06:22:31 PM PDT 24
Finished Jul 14 06:22:53 PM PDT 24
Peak memory 250984 kb
Host smart-b7562a8c-3421-4aba-9bf4-5fe8f6299294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172045236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1172045236
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3847444020
Short name T290
Test name
Test status
Simulation time 117946099 ps
CPU time 6.66 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:50 PM PDT 24
Peak memory 250372 kb
Host smart-3a8ba9e1-96b0-4673-846d-1d022323fbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847444020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3847444020
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.4011971211
Short name T492
Test name
Test status
Simulation time 16368378881 ps
CPU time 194.16 seconds
Started Jul 14 06:22:39 PM PDT 24
Finished Jul 14 06:25:54 PM PDT 24
Peak memory 283816 kb
Host smart-807f809a-7336-49e5-a688-23a2e0743dc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011971211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.4011971211
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1196302004
Short name T167
Test name
Test status
Simulation time 37988692106 ps
CPU time 1219.45 seconds
Started Jul 14 06:22:37 PM PDT 24
Finished Jul 14 06:42:57 PM PDT 24
Peak memory 316680 kb
Host smart-80841aa0-a5f9-4114-bb09-6c96a080c10f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1196302004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1196302004
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2804428851
Short name T526
Test name
Test status
Simulation time 56422128 ps
CPU time 0.91 seconds
Started Jul 14 06:22:30 PM PDT 24
Finished Jul 14 06:22:32 PM PDT 24
Peak memory 217732 kb
Host smart-96d2e270-9532-414a-b43c-63e6a6f36452
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804428851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2804428851
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1667205355
Short name T366
Test name
Test status
Simulation time 37338512 ps
CPU time 1.16 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:45 PM PDT 24
Peak memory 209036 kb
Host smart-fc312acc-35c8-4b80-bdd5-b4f5e4e95e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667205355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1667205355
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1447524966
Short name T650
Test name
Test status
Simulation time 181352579 ps
CPU time 9.76 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:54 PM PDT 24
Peak memory 218224 kb
Host smart-a26aeaf9-31d1-4378-ba88-494c324cf606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447524966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1447524966
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2835362495
Short name T425
Test name
Test status
Simulation time 240898987 ps
CPU time 2.14 seconds
Started Jul 14 06:22:36 PM PDT 24
Finished Jul 14 06:22:39 PM PDT 24
Peak memory 217052 kb
Host smart-28fb0607-f77e-49ee-bf8c-2e2610a621d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835362495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2835362495
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2994895217
Short name T342
Test name
Test status
Simulation time 80630529 ps
CPU time 3.75 seconds
Started Jul 14 06:22:38 PM PDT 24
Finished Jul 14 06:22:42 PM PDT 24
Peak memory 222404 kb
Host smart-e359aaf3-8863-4edb-9b23-788794d68e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994895217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2994895217
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.761827506
Short name T853
Test name
Test status
Simulation time 777807931 ps
CPU time 7.89 seconds
Started Jul 14 06:22:38 PM PDT 24
Finished Jul 14 06:22:47 PM PDT 24
Peak memory 225992 kb
Host smart-e84b1ec1-357a-4db7-8d95-e196096c6a0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761827506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.761827506
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2973158426
Short name T180
Test name
Test status
Simulation time 1802995151 ps
CPU time 9.99 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:52 PM PDT 24
Peak memory 226040 kb
Host smart-e319e5b6-7159-471f-8069-bdf639de148c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973158426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2973158426
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3093309410
Short name T597
Test name
Test status
Simulation time 1584018248 ps
CPU time 10.11 seconds
Started Jul 14 06:22:40 PM PDT 24
Finished Jul 14 06:22:51 PM PDT 24
Peak memory 218220 kb
Host smart-f448a6d8-dba9-46da-a843-4bace91eecde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093309410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3093309410
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1576117840
Short name T557
Test name
Test status
Simulation time 442148556 ps
CPU time 16.57 seconds
Started Jul 14 06:22:38 PM PDT 24
Finished Jul 14 06:22:55 PM PDT 24
Peak memory 225928 kb
Host smart-f51e277a-dbc4-47de-89a4-8ffa237e9674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576117840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1576117840
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4139693565
Short name T393
Test name
Test status
Simulation time 18334523 ps
CPU time 1.58 seconds
Started Jul 14 06:22:38 PM PDT 24
Finished Jul 14 06:22:40 PM PDT 24
Peak memory 213788 kb
Host smart-0983b06c-9161-4620-96fe-d5406678f8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139693565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4139693565
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.4005643155
Short name T543
Test name
Test status
Simulation time 286290910 ps
CPU time 29.2 seconds
Started Jul 14 06:22:40 PM PDT 24
Finished Jul 14 06:23:10 PM PDT 24
Peak memory 250912 kb
Host smart-4961398f-3e19-4388-899c-6723846b012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005643155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4005643155
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.760924389
Short name T499
Test name
Test status
Simulation time 58646966 ps
CPU time 6.8 seconds
Started Jul 14 06:22:40 PM PDT 24
Finished Jul 14 06:22:47 PM PDT 24
Peak memory 246116 kb
Host smart-57028c33-5fb8-495f-944b-ca16b6580933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760924389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.760924389
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1544069768
Short name T632
Test name
Test status
Simulation time 7791519620 ps
CPU time 274 seconds
Started Jul 14 06:22:43 PM PDT 24
Finished Jul 14 06:27:18 PM PDT 24
Peak memory 277284 kb
Host smart-72c11933-8e37-4f2d-92bc-e3f3416aec95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544069768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1544069768
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.815945889
Short name T158
Test name
Test status
Simulation time 19864301192 ps
CPU time 463.67 seconds
Started Jul 14 06:22:38 PM PDT 24
Finished Jul 14 06:30:23 PM PDT 24
Peak memory 267564 kb
Host smart-4a6a1679-c6a7-4ddd-beb4-238cd168aec3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=815945889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.815945889
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3811282844
Short name T282
Test name
Test status
Simulation time 23307956 ps
CPU time 0.99 seconds
Started Jul 14 06:22:38 PM PDT 24
Finished Jul 14 06:22:40 PM PDT 24
Peak memory 211772 kb
Host smart-cda0997e-5d32-40a2-bafc-20de363c3c26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811282844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3811282844
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.693866717
Short name T606
Test name
Test status
Simulation time 46843101 ps
CPU time 0.95 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:45 PM PDT 24
Peak memory 209008 kb
Host smart-f51ccfed-1ba9-40c9-8ef1-9d5062bf0823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693866717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.693866717
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2779690530
Short name T427
Test name
Test status
Simulation time 1195670274 ps
CPU time 11.07 seconds
Started Jul 14 06:22:46 PM PDT 24
Finished Jul 14 06:22:57 PM PDT 24
Peak memory 226000 kb
Host smart-f31cb577-3970-49ff-8057-19eb85eeccb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779690530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2779690530
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2809743873
Short name T683
Test name
Test status
Simulation time 1124572651 ps
CPU time 5.93 seconds
Started Jul 14 06:22:47 PM PDT 24
Finished Jul 14 06:22:53 PM PDT 24
Peak memory 217136 kb
Host smart-dd9bc054-cae4-48c5-a54c-68f19c5b5184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809743873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2809743873
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2865239768
Short name T791
Test name
Test status
Simulation time 100261587 ps
CPU time 4.33 seconds
Started Jul 14 06:22:37 PM PDT 24
Finished Jul 14 06:22:41 PM PDT 24
Peak memory 218176 kb
Host smart-464c19f2-217e-49d2-a019-167c1353ab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865239768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2865239768
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.502922173
Short name T858
Test name
Test status
Simulation time 976980310 ps
CPU time 13.01 seconds
Started Jul 14 06:22:47 PM PDT 24
Finished Jul 14 06:23:00 PM PDT 24
Peak memory 225932 kb
Host smart-08cd00f9-fc14-4b83-8550-b06dc4b54e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502922173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.502922173
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3375067231
Short name T642
Test name
Test status
Simulation time 3457265079 ps
CPU time 8.32 seconds
Started Jul 14 06:22:48 PM PDT 24
Finished Jul 14 06:22:56 PM PDT 24
Peak memory 218216 kb
Host smart-b495348d-2daf-45fb-a40c-83eecb295d30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375067231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3375067231
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3088478949
Short name T663
Test name
Test status
Simulation time 998320251 ps
CPU time 11.12 seconds
Started Jul 14 06:22:45 PM PDT 24
Finished Jul 14 06:22:57 PM PDT 24
Peak memory 218192 kb
Host smart-fa31fc95-cb14-4d05-9e3d-58c32f8da5f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088478949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3088478949
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1557759161
Short name T315
Test name
Test status
Simulation time 280716535 ps
CPU time 7.62 seconds
Started Jul 14 06:22:45 PM PDT 24
Finished Jul 14 06:22:53 PM PDT 24
Peak memory 226052 kb
Host smart-085d91c1-4a7b-4745-87ef-b93d85c88b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557759161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1557759161
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4151196008
Short name T639
Test name
Test status
Simulation time 37137087 ps
CPU time 1.77 seconds
Started Jul 14 06:22:40 PM PDT 24
Finished Jul 14 06:22:43 PM PDT 24
Peak memory 213916 kb
Host smart-cde46de4-c79b-4b2f-b5f3-e9e397fc0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151196008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4151196008
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1762304957
Short name T789
Test name
Test status
Simulation time 245302102 ps
CPU time 30.68 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:23:15 PM PDT 24
Peak memory 250940 kb
Host smart-184d6b8d-f5bb-4b5b-8dc6-987025cb5506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762304957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1762304957
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2834820506
Short name T645
Test name
Test status
Simulation time 264750149 ps
CPU time 6.76 seconds
Started Jul 14 06:22:37 PM PDT 24
Finished Jul 14 06:22:45 PM PDT 24
Peak memory 250868 kb
Host smart-8ae0eef8-6e20-4f7c-9719-08cee7ee91df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834820506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2834820506
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4246368182
Short name T821
Test name
Test status
Simulation time 6316043227 ps
CPU time 167.51 seconds
Started Jul 14 06:22:43 PM PDT 24
Finished Jul 14 06:25:32 PM PDT 24
Peak memory 283068 kb
Host smart-63714b8e-65c4-423c-b17e-12edd280507a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246368182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4246368182
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2933446997
Short name T763
Test name
Test status
Simulation time 40547609 ps
CPU time 1 seconds
Started Jul 14 06:22:38 PM PDT 24
Finished Jul 14 06:22:39 PM PDT 24
Peak memory 211848 kb
Host smart-cd6f7a97-4353-4b75-9afa-643315a92863
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933446997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2933446997
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2723280419
Short name T820
Test name
Test status
Simulation time 32902713 ps
CPU time 1.14 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:44 PM PDT 24
Peak memory 208976 kb
Host smart-833c03cf-8e7a-4533-84dc-1b096960107b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723280419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2723280419
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.4098489832
Short name T330
Test name
Test status
Simulation time 488212918 ps
CPU time 9.46 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:53 PM PDT 24
Peak memory 218188 kb
Host smart-1f1730fb-da5d-482a-8451-a4b74e9aead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098489832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.4098489832
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4210943301
Short name T420
Test name
Test status
Simulation time 1589396279 ps
CPU time 20.16 seconds
Started Jul 14 06:22:44 PM PDT 24
Finished Jul 14 06:23:06 PM PDT 24
Peak memory 217480 kb
Host smart-86002bdc-5c7d-4c97-b04e-955a01904ac9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210943301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4210943301
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2821172654
Short name T562
Test name
Test status
Simulation time 238744228 ps
CPU time 3.61 seconds
Started Jul 14 06:22:45 PM PDT 24
Finished Jul 14 06:22:50 PM PDT 24
Peak memory 218224 kb
Host smart-6d26714f-f7ab-49b2-bf2f-b48f031aa39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821172654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2821172654
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.958818083
Short name T601
Test name
Test status
Simulation time 1473809242 ps
CPU time 14.62 seconds
Started Jul 14 06:22:45 PM PDT 24
Finished Jul 14 06:23:01 PM PDT 24
Peak memory 226008 kb
Host smart-b1345d9f-38e5-47f3-b194-ca47214c0fc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958818083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.958818083
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.316543853
Short name T392
Test name
Test status
Simulation time 824538456 ps
CPU time 17.85 seconds
Started Jul 14 06:22:44 PM PDT 24
Finished Jul 14 06:23:03 PM PDT 24
Peak memory 225976 kb
Host smart-09e041b3-b1f7-43fe-bab8-d62dc3298c86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316543853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.316543853
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2142198883
Short name T814
Test name
Test status
Simulation time 283582856 ps
CPU time 7.86 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:50 PM PDT 24
Peak memory 218192 kb
Host smart-47eb4bb9-99ee-482d-925f-48c96efc3a7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142198883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2142198883
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4135862464
Short name T707
Test name
Test status
Simulation time 283075708 ps
CPU time 7.75 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:51 PM PDT 24
Peak memory 224196 kb
Host smart-7fcdd5d0-4906-4bac-8c26-afa9fb0aa82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135862464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4135862464
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3155419950
Short name T755
Test name
Test status
Simulation time 94844619 ps
CPU time 2.41 seconds
Started Jul 14 06:22:43 PM PDT 24
Finished Jul 14 06:22:47 PM PDT 24
Peak memory 217660 kb
Host smart-cdfd3b1a-d9ad-44ce-81ef-11b9291c65ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155419950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3155419950
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3615044715
Short name T376
Test name
Test status
Simulation time 1197947913 ps
CPU time 33.54 seconds
Started Jul 14 06:22:43 PM PDT 24
Finished Jul 14 06:23:18 PM PDT 24
Peak memory 250948 kb
Host smart-6ea0ea0b-5b3e-4923-ab2c-a16387c117ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615044715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3615044715
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2540102238
Short name T302
Test name
Test status
Simulation time 98752627 ps
CPU time 6.84 seconds
Started Jul 14 06:22:45 PM PDT 24
Finished Jul 14 06:22:53 PM PDT 24
Peak memory 250868 kb
Host smart-8b47bff7-5209-47c5-9f9e-2fab0ccb11dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540102238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2540102238
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2229485107
Short name T98
Test name
Test status
Simulation time 616816538 ps
CPU time 49.59 seconds
Started Jul 14 06:22:44 PM PDT 24
Finished Jul 14 06:23:35 PM PDT 24
Peak memory 249864 kb
Host smart-5316cf7a-bfb2-4c99-83b0-7d52de01b459
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229485107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2229485107
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3111886313
Short name T283
Test name
Test status
Simulation time 16872984 ps
CPU time 0.97 seconds
Started Jul 14 06:22:42 PM PDT 24
Finished Jul 14 06:22:44 PM PDT 24
Peak memory 211852 kb
Host smart-efadc691-6de3-47fb-876e-4ed9854deb8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111886313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3111886313
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1553085077
Short name T674
Test name
Test status
Simulation time 33146434 ps
CPU time 1.08 seconds
Started Jul 14 06:23:04 PM PDT 24
Finished Jul 14 06:23:06 PM PDT 24
Peak memory 208904 kb
Host smart-3754ecd7-b0e2-4dc7-8841-ecfa824235a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553085077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1553085077
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3802692767
Short name T849
Test name
Test status
Simulation time 709784823 ps
CPU time 15.19 seconds
Started Jul 14 06:22:47 PM PDT 24
Finished Jul 14 06:23:03 PM PDT 24
Peak memory 218200 kb
Host smart-f79c7021-843c-4f67-b5b6-4605591d15a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802692767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3802692767
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1085954461
Short name T767
Test name
Test status
Simulation time 64797178 ps
CPU time 2.83 seconds
Started Jul 14 06:22:43 PM PDT 24
Finished Jul 14 06:22:48 PM PDT 24
Peak memory 222432 kb
Host smart-e3f5ebc9-a02f-48f6-9931-7ecb4b1fad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085954461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1085954461
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.762989184
Short name T385
Test name
Test status
Simulation time 362440965 ps
CPU time 14.64 seconds
Started Jul 14 06:22:49 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 226036 kb
Host smart-72691fa7-317a-44ef-8163-4d4d26f7d82a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762989184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.762989184
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.875033524
Short name T708
Test name
Test status
Simulation time 391323136 ps
CPU time 13.66 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:24 PM PDT 24
Peak memory 225964 kb
Host smart-c62dbd3a-4d22-459b-a7b8-039cc5c46d4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875033524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.875033524
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.715780644
Short name T489
Test name
Test status
Simulation time 407537175 ps
CPU time 8.45 seconds
Started Jul 14 06:22:53 PM PDT 24
Finished Jul 14 06:23:03 PM PDT 24
Peak memory 218244 kb
Host smart-2e39bb63-cb06-451f-922c-38951d7b1711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715780644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.715780644
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1852349668
Short name T850
Test name
Test status
Simulation time 608718911 ps
CPU time 11.35 seconds
Started Jul 14 06:22:44 PM PDT 24
Finished Jul 14 06:22:57 PM PDT 24
Peak memory 224576 kb
Host smart-59891d99-dbae-4364-b4ca-b7585a73fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852349668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1852349668
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.59893952
Short name T692
Test name
Test status
Simulation time 257956488 ps
CPU time 2.56 seconds
Started Jul 14 06:22:47 PM PDT 24
Finished Jul 14 06:22:50 PM PDT 24
Peak memory 217620 kb
Host smart-4439ea5d-daf1-4031-a2eb-10e81dd358ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59893952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.59893952
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.669523246
Short name T318
Test name
Test status
Simulation time 335866664 ps
CPU time 30.4 seconds
Started Jul 14 06:22:43 PM PDT 24
Finished Jul 14 06:23:15 PM PDT 24
Peak memory 250912 kb
Host smart-040db3f6-3ca3-408f-ad80-c0b2cc67bb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669523246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.669523246
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2783850136
Short name T772
Test name
Test status
Simulation time 121008799 ps
CPU time 7.15 seconds
Started Jul 14 06:22:43 PM PDT 24
Finished Jul 14 06:22:52 PM PDT 24
Peak memory 247136 kb
Host smart-5c0973b2-d017-4bed-9cd8-422d5902144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783850136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2783850136
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2452554493
Short name T59
Test name
Test status
Simulation time 2377093371 ps
CPU time 42.68 seconds
Started Jul 14 06:22:51 PM PDT 24
Finished Jul 14 06:23:34 PM PDT 24
Peak memory 249784 kb
Host smart-cd1167a3-f59f-42a0-8e97-34d8440eabbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452554493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2452554493
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3437084587
Short name T170
Test name
Test status
Simulation time 52914377 ps
CPU time 0.99 seconds
Started Jul 14 06:22:43 PM PDT 24
Finished Jul 14 06:22:46 PM PDT 24
Peak memory 211840 kb
Host smart-e8e5dcc4-f3a9-440c-adad-976277a2dd95
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437084587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3437084587
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1191159138
Short name T248
Test name
Test status
Simulation time 47040767 ps
CPU time 0.99 seconds
Started Jul 14 06:22:49 PM PDT 24
Finished Jul 14 06:22:51 PM PDT 24
Peak memory 208992 kb
Host smart-8029a9d3-78e8-487f-9ae2-dc981f2f4c15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191159138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1191159138
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1826041221
Short name T274
Test name
Test status
Simulation time 2431580298 ps
CPU time 12.15 seconds
Started Jul 14 06:23:06 PM PDT 24
Finished Jul 14 06:23:19 PM PDT 24
Peak memory 226028 kb
Host smart-0b55b216-465c-45c8-acc2-62c307bc7a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826041221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1826041221
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3211115312
Short name T501
Test name
Test status
Simulation time 326028284 ps
CPU time 4.54 seconds
Started Jul 14 06:22:49 PM PDT 24
Finished Jul 14 06:22:54 PM PDT 24
Peak memory 217456 kb
Host smart-1154874d-1a6e-4c6b-a1c4-de333947b8d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211115312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3211115312
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1632614015
Short name T600
Test name
Test status
Simulation time 189808591 ps
CPU time 2.46 seconds
Started Jul 14 06:22:53 PM PDT 24
Finished Jul 14 06:22:56 PM PDT 24
Peak memory 218164 kb
Host smart-5fa7d230-2fab-4006-ada4-43ada315c54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632614015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1632614015
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2260828550
Short name T181
Test name
Test status
Simulation time 739400001 ps
CPU time 15.29 seconds
Started Jul 14 06:22:52 PM PDT 24
Finished Jul 14 06:23:08 PM PDT 24
Peak memory 218796 kb
Host smart-395b6971-3880-4600-aec7-97061a88d1d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260828550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2260828550
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3312932297
Short name T766
Test name
Test status
Simulation time 247912128 ps
CPU time 10.19 seconds
Started Jul 14 06:22:53 PM PDT 24
Finished Jul 14 06:23:04 PM PDT 24
Peak memory 226016 kb
Host smart-6b258e42-fa78-4a61-8ab8-089708eb4064
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312932297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3312932297
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2385867461
Short name T445
Test name
Test status
Simulation time 1644875743 ps
CPU time 6.7 seconds
Started Jul 14 06:22:51 PM PDT 24
Finished Jul 14 06:22:58 PM PDT 24
Peak memory 218232 kb
Host smart-b6d13f1a-590b-46d1-a564-ebbc94b5089d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385867461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2385867461
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2347217667
Short name T788
Test name
Test status
Simulation time 1048497865 ps
CPU time 9.94 seconds
Started Jul 14 06:22:53 PM PDT 24
Finished Jul 14 06:23:04 PM PDT 24
Peak memory 226044 kb
Host smart-878c1691-8f91-4446-ad21-15d28c3e0e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347217667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2347217667
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3263109129
Short name T194
Test name
Test status
Simulation time 68016580 ps
CPU time 2.65 seconds
Started Jul 14 06:22:49 PM PDT 24
Finished Jul 14 06:22:53 PM PDT 24
Peak memory 214860 kb
Host smart-cc95ec70-0eb3-4f98-ad31-419df6951021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263109129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3263109129
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.4203386861
Short name T584
Test name
Test status
Simulation time 442676546 ps
CPU time 21.51 seconds
Started Jul 14 06:22:51 PM PDT 24
Finished Jul 14 06:23:13 PM PDT 24
Peak memory 250952 kb
Host smart-71f4da07-c1b0-49c6-a90e-5622ae1a3a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203386861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.4203386861
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2489193146
Short name T673
Test name
Test status
Simulation time 148473691 ps
CPU time 8.63 seconds
Started Jul 14 06:22:50 PM PDT 24
Finished Jul 14 06:22:59 PM PDT 24
Peak memory 247864 kb
Host smart-b90d95df-f037-4efc-b104-1b55de3cf4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489193146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2489193146
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1999707010
Short name T334
Test name
Test status
Simulation time 328476273 ps
CPU time 26.77 seconds
Started Jul 14 06:22:48 PM PDT 24
Finished Jul 14 06:23:15 PM PDT 24
Peak memory 250884 kb
Host smart-41064428-f53d-4d66-92a1-083db15a08fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999707010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1999707010
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.244505611
Short name T281
Test name
Test status
Simulation time 32444598 ps
CPU time 0.97 seconds
Started Jul 14 06:22:50 PM PDT 24
Finished Jul 14 06:22:51 PM PDT 24
Peak memory 211912 kb
Host smart-e2e6c122-63ce-4490-ba75-480c721b668f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244505611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.244505611
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.177782190
Short name T436
Test name
Test status
Simulation time 86585420 ps
CPU time 0.93 seconds
Started Jul 14 06:22:58 PM PDT 24
Finished Jul 14 06:23:00 PM PDT 24
Peak memory 208944 kb
Host smart-3a5b66de-10ad-457e-8a52-20fd5a961b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177782190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.177782190
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2878564057
Short name T388
Test name
Test status
Simulation time 532009018 ps
CPU time 17.35 seconds
Started Jul 14 06:22:51 PM PDT 24
Finished Jul 14 06:23:08 PM PDT 24
Peak memory 218160 kb
Host smart-1445cfdf-01cc-4415-9b81-c678303b9aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878564057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2878564057
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3426560454
Short name T734
Test name
Test status
Simulation time 549198415 ps
CPU time 14.11 seconds
Started Jul 14 06:22:49 PM PDT 24
Finished Jul 14 06:23:04 PM PDT 24
Peak memory 217420 kb
Host smart-a4c89b54-99fe-4f63-b46e-f9cb27a3c882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426560454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3426560454
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1503778643
Short name T234
Test name
Test status
Simulation time 41175891 ps
CPU time 2.24 seconds
Started Jul 14 06:22:49 PM PDT 24
Finished Jul 14 06:22:52 PM PDT 24
Peak memory 218112 kb
Host smart-93b69dc0-ca77-4bbc-85b8-261804e49b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503778643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1503778643
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3208178895
Short name T247
Test name
Test status
Simulation time 2929987688 ps
CPU time 10.3 seconds
Started Jul 14 06:22:54 PM PDT 24
Finished Jul 14 06:23:06 PM PDT 24
Peak memory 226016 kb
Host smart-cac924e5-745c-40c9-b3ce-96aff4312853
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208178895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3208178895
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.4020998694
Short name T743
Test name
Test status
Simulation time 745359693 ps
CPU time 9.66 seconds
Started Jul 14 06:22:53 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 218152 kb
Host smart-3734a5e0-8657-4256-8e4d-6ead705f9f9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020998694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
4020998694
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.709613210
Short name T658
Test name
Test status
Simulation time 799368288 ps
CPU time 8.51 seconds
Started Jul 14 06:22:51 PM PDT 24
Finished Jul 14 06:23:00 PM PDT 24
Peak memory 218200 kb
Host smart-44de7641-d6be-4d95-a148-c6a4b68097a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709613210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.709613210
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1842251028
Short name T161
Test name
Test status
Simulation time 232587704 ps
CPU time 2.55 seconds
Started Jul 14 06:22:50 PM PDT 24
Finished Jul 14 06:22:53 PM PDT 24
Peak memory 214704 kb
Host smart-74debf2d-ed60-460b-b5e4-e4255ad17aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842251028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1842251028
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2232111839
Short name T868
Test name
Test status
Simulation time 2801636708 ps
CPU time 29.27 seconds
Started Jul 14 06:22:49 PM PDT 24
Finished Jul 14 06:23:19 PM PDT 24
Peak memory 251048 kb
Host smart-673c49ce-fae5-457c-b4ef-2de9e0e35165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232111839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2232111839
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.307852499
Short name T16
Test name
Test status
Simulation time 63180152 ps
CPU time 5.91 seconds
Started Jul 14 06:22:54 PM PDT 24
Finished Jul 14 06:23:02 PM PDT 24
Peak memory 246852 kb
Host smart-4fb2a9f8-67fe-4e27-b2da-95d77083f798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307852499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.307852499
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.695129599
Short name T512
Test name
Test status
Simulation time 15640033163 ps
CPU time 95.7 seconds
Started Jul 14 06:22:55 PM PDT 24
Finished Jul 14 06:24:32 PM PDT 24
Peak memory 269092 kb
Host smart-fd8cfd2c-49c6-49f9-82ca-acdf09e31c5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695129599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.695129599
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3534671704
Short name T845
Test name
Test status
Simulation time 25043923474 ps
CPU time 787.53 seconds
Started Jul 14 06:22:58 PM PDT 24
Finished Jul 14 06:36:06 PM PDT 24
Peak memory 333096 kb
Host smart-80ba0e9a-4d4e-4f5b-9c92-c67af63591a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3534671704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3534671704
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3518235625
Short name T712
Test name
Test status
Simulation time 32096286 ps
CPU time 0.98 seconds
Started Jul 14 06:22:49 PM PDT 24
Finished Jul 14 06:22:51 PM PDT 24
Peak memory 212004 kb
Host smart-93fadbca-50db-4d56-930b-940d90c72306
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518235625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3518235625
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2989926297
Short name T160
Test name
Test status
Simulation time 16276594 ps
CPU time 0.86 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 208804 kb
Host smart-c69dcbbc-4c0d-44e1-8848-c2d7c2bf72ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989926297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2989926297
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2119648065
Short name T326
Test name
Test status
Simulation time 435040505 ps
CPU time 14.3 seconds
Started Jul 14 06:22:54 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 218096 kb
Host smart-7fa94538-057e-4dc2-9cb1-83e63c95b3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119648065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2119648065
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1720232128
Short name T23
Test name
Test status
Simulation time 74128022 ps
CPU time 1.6 seconds
Started Jul 14 06:22:59 PM PDT 24
Finished Jul 14 06:23:01 PM PDT 24
Peak memory 217064 kb
Host smart-31509e63-ee9e-433f-bc2a-36dc8a72f808
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720232128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1720232128
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2571202723
Short name T780
Test name
Test status
Simulation time 78535573 ps
CPU time 1.93 seconds
Started Jul 14 06:22:54 PM PDT 24
Finished Jul 14 06:22:58 PM PDT 24
Peak memory 218244 kb
Host smart-e5cee903-89a3-42f5-8e28-e659c3fc888f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571202723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2571202723
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3827263076
Short name T564
Test name
Test status
Simulation time 1614179826 ps
CPU time 8.35 seconds
Started Jul 14 06:22:57 PM PDT 24
Finished Jul 14 06:23:06 PM PDT 24
Peak memory 218132 kb
Host smart-8621ae7b-0c29-45e5-ba0b-c99c89096531
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827263076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3827263076
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.999173820
Short name T815
Test name
Test status
Simulation time 779673700 ps
CPU time 16.71 seconds
Started Jul 14 06:22:58 PM PDT 24
Finished Jul 14 06:23:16 PM PDT 24
Peak memory 226048 kb
Host smart-3830d79e-1a1f-4e54-9d57-db9edc1a63d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999173820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.999173820
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2754952422
Short name T794
Test name
Test status
Simulation time 1471023514 ps
CPU time 16.57 seconds
Started Jul 14 06:22:54 PM PDT 24
Finished Jul 14 06:23:13 PM PDT 24
Peak memory 225520 kb
Host smart-8e356454-5e04-49af-90d8-cb1cdbe5824e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754952422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2754952422
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.371182354
Short name T700
Test name
Test status
Simulation time 352646008 ps
CPU time 7.87 seconds
Started Jul 14 06:22:53 PM PDT 24
Finished Jul 14 06:23:03 PM PDT 24
Peak memory 218376 kb
Host smart-8bcd117d-ff05-497b-ba44-213f22cb2639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371182354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.371182354
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.332102770
Short name T397
Test name
Test status
Simulation time 134630158 ps
CPU time 2.78 seconds
Started Jul 14 06:22:56 PM PDT 24
Finished Jul 14 06:23:00 PM PDT 24
Peak memory 217776 kb
Host smart-0f289038-90cf-4fd4-ac4d-541098ed421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332102770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.332102770
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.4023135824
Short name T764
Test name
Test status
Simulation time 1510366518 ps
CPU time 34.67 seconds
Started Jul 14 06:22:57 PM PDT 24
Finished Jul 14 06:23:33 PM PDT 24
Peak memory 250976 kb
Host smart-d4b97e86-73d4-4363-9c29-b1f711e2af63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023135824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.4023135824
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3851141740
Short name T678
Test name
Test status
Simulation time 94104365 ps
CPU time 6.75 seconds
Started Jul 14 06:22:55 PM PDT 24
Finished Jul 14 06:23:03 PM PDT 24
Peak memory 250976 kb
Host smart-9ab67bfb-f0f3-4510-abb4-a2916a02b67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851141740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3851141740
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3049563513
Short name T778
Test name
Test status
Simulation time 2342840151 ps
CPU time 72.39 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:24:23 PM PDT 24
Peak memory 250608 kb
Host smart-86b81ffb-a259-447f-832e-49402af0df04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049563513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3049563513
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1208930586
Short name T628
Test name
Test status
Simulation time 93023541 ps
CPU time 0.83 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 211628 kb
Host smart-9fafd295-7063-4cf1-9a35-459d59f6d7f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208930586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1208930586
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3788700579
Short name T582
Test name
Test status
Simulation time 77564548 ps
CPU time 1.23 seconds
Started Jul 14 06:23:03 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 209004 kb
Host smart-4845e98a-b664-457c-a1cf-dd4b98a95e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788700579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3788700579
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2186234998
Short name T42
Test name
Test status
Simulation time 290158674 ps
CPU time 9.02 seconds
Started Jul 14 06:22:54 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 218188 kb
Host smart-b0f8b7e6-fd22-4723-95e5-9bfef230b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186234998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2186234998
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.244248457
Short name T533
Test name
Test status
Simulation time 952013522 ps
CPU time 2.48 seconds
Started Jul 14 06:22:55 PM PDT 24
Finished Jul 14 06:22:59 PM PDT 24
Peak memory 217140 kb
Host smart-c4e68255-a9ee-4189-9d5d-4a58fa3fb6da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244248457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.244248457
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3565997256
Short name T111
Test name
Test status
Simulation time 79307499 ps
CPU time 3.78 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:14 PM PDT 24
Peak memory 218132 kb
Host smart-46368f94-384f-4adf-9f28-714d09b92793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565997256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3565997256
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1376195236
Short name T353
Test name
Test status
Simulation time 1038778110 ps
CPU time 11.2 seconds
Started Jul 14 06:22:58 PM PDT 24
Finished Jul 14 06:23:10 PM PDT 24
Peak memory 218248 kb
Host smart-b29e66a6-86d9-4f9a-a79e-5abb860a98a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376195236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1376195236
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2986257597
Short name T320
Test name
Test status
Simulation time 1691257684 ps
CPU time 15.78 seconds
Started Jul 14 06:22:55 PM PDT 24
Finished Jul 14 06:23:13 PM PDT 24
Peak memory 225936 kb
Host smart-2c563587-8517-4c95-8c3a-660f69b5721d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986257597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2986257597
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2590150063
Short name T252
Test name
Test status
Simulation time 214664812 ps
CPU time 8.96 seconds
Started Jul 14 06:22:53 PM PDT 24
Finished Jul 14 06:23:02 PM PDT 24
Peak memory 218212 kb
Host smart-d542cf9f-b261-4ed4-adc8-e02db5d63b24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590150063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2590150063
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2661249221
Short name T386
Test name
Test status
Simulation time 2559436044 ps
CPU time 10.38 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:21 PM PDT 24
Peak memory 226004 kb
Host smart-d80d8d13-699c-4718-9c03-ae0eea25577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661249221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2661249221
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.634769536
Short name T381
Test name
Test status
Simulation time 12993791 ps
CPU time 1.18 seconds
Started Jul 14 06:22:55 PM PDT 24
Finished Jul 14 06:22:58 PM PDT 24
Peak memory 212052 kb
Host smart-557660ff-201d-4807-abad-f3fe03b9fb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634769536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.634769536
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1992156242
Short name T373
Test name
Test status
Simulation time 311725825 ps
CPU time 37.38 seconds
Started Jul 14 06:22:58 PM PDT 24
Finished Jul 14 06:23:37 PM PDT 24
Peak memory 250880 kb
Host smart-052e97d4-076a-4cf9-8517-173bbebf41a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992156242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1992156242
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1902841765
Short name T857
Test name
Test status
Simulation time 225538710 ps
CPU time 7.83 seconds
Started Jul 14 06:22:57 PM PDT 24
Finished Jul 14 06:23:06 PM PDT 24
Peak memory 250992 kb
Host smart-ae5549ef-e694-4488-983d-6310284cad07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902841765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1902841765
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4084945796
Short name T505
Test name
Test status
Simulation time 1460280628 ps
CPU time 30.5 seconds
Started Jul 14 06:22:58 PM PDT 24
Finished Jul 14 06:23:30 PM PDT 24
Peak memory 226404 kb
Host smart-683f9c09-4b93-44a0-9ee6-eaba874737b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084945796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4084945796
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1017107462
Short name T848
Test name
Test status
Simulation time 18446157146 ps
CPU time 347.44 seconds
Started Jul 14 06:22:54 PM PDT 24
Finished Jul 14 06:28:44 PM PDT 24
Peak memory 280756 kb
Host smart-89be6f2a-971b-49dc-b1c4-7226342c67fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1017107462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1017107462
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3021181909
Short name T301
Test name
Test status
Simulation time 40733298 ps
CPU time 0.91 seconds
Started Jul 14 06:22:54 PM PDT 24
Finished Jul 14 06:22:57 PM PDT 24
Peak memory 217748 kb
Host smart-ff9bbfab-894a-4b0e-95c0-db26f294bd9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021181909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3021181909
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3459079395
Short name T760
Test name
Test status
Simulation time 52099187 ps
CPU time 0.97 seconds
Started Jul 14 06:20:53 PM PDT 24
Finished Jul 14 06:20:56 PM PDT 24
Peak memory 208996 kb
Host smart-86bdf7db-d98b-4ab3-aa75-d87cfa7ba33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459079395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3459079395
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2387785534
Short name T806
Test name
Test status
Simulation time 38307005 ps
CPU time 0.88 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:20:55 PM PDT 24
Peak memory 209084 kb
Host smart-57492946-86f9-427a-83c4-8a467b68f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387785534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2387785534
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1635526480
Short name T589
Test name
Test status
Simulation time 51360424 ps
CPU time 2.13 seconds
Started Jul 14 06:20:53 PM PDT 24
Finished Jul 14 06:20:58 PM PDT 24
Peak memory 217064 kb
Host smart-d7774235-8552-4d20-bfe8-239fed85da59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635526480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1635526480
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.194827412
Short name T279
Test name
Test status
Simulation time 7756661788 ps
CPU time 51.33 seconds
Started Jul 14 06:20:55 PM PDT 24
Finished Jul 14 06:21:48 PM PDT 24
Peak memory 219004 kb
Host smart-d4e2b85a-94cc-4b48-8873-a2d7d2c5feb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194827412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.194827412
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2724968493
Short name T671
Test name
Test status
Simulation time 665610615 ps
CPU time 15.87 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:21:10 PM PDT 24
Peak memory 217724 kb
Host smart-64bf7c6d-1235-4e27-9441-be1f79d30d8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724968493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
724968493
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4108474707
Short name T699
Test name
Test status
Simulation time 3630401447 ps
CPU time 12.15 seconds
Started Jul 14 06:20:55 PM PDT 24
Finished Jul 14 06:21:09 PM PDT 24
Peak memory 218244 kb
Host smart-f79df646-7c0b-429e-99d5-e5eceede02da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108474707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4108474707
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1373618285
Short name T659
Test name
Test status
Simulation time 1851102008 ps
CPU time 27.49 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:21:22 PM PDT 24
Peak memory 217708 kb
Host smart-dbe586a4-c5d2-46ca-a4eb-873e16da8dec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373618285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1373618285
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.163391962
Short name T374
Test name
Test status
Simulation time 1249348743 ps
CPU time 6.8 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:21:00 PM PDT 24
Peak memory 217708 kb
Host smart-c1460c62-f7ee-445c-b657-4004f09b4d7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163391962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.163391962
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2699783783
Short name T405
Test name
Test status
Simulation time 1185319006 ps
CPU time 37.57 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:21:30 PM PDT 24
Peak memory 267364 kb
Host smart-5d8805a4-4f78-4e7d-87c4-65190244b6c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699783783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2699783783
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1426159731
Short name T592
Test name
Test status
Simulation time 1892735858 ps
CPU time 14.87 seconds
Started Jul 14 06:20:53 PM PDT 24
Finished Jul 14 06:21:10 PM PDT 24
Peak memory 250924 kb
Host smart-cb8a7244-bc06-4df5-bac0-7dca3575b051
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426159731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1426159731
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3860685917
Short name T102
Test name
Test status
Simulation time 193397056 ps
CPU time 4.41 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:20:58 PM PDT 24
Peak memory 222628 kb
Host smart-5489e447-d544-4031-bf69-e5b0c0352f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860685917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3860685917
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3977028526
Short name T196
Test name
Test status
Simulation time 4113288552 ps
CPU time 8.91 seconds
Started Jul 14 06:20:53 PM PDT 24
Finished Jul 14 06:21:04 PM PDT 24
Peak memory 215532 kb
Host smart-4cd17085-74e2-4e13-aa56-0391e12ec508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977028526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3977028526
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2547491140
Short name T796
Test name
Test status
Simulation time 474099591 ps
CPU time 8.77 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:21:00 PM PDT 24
Peak memory 218136 kb
Host smart-b792585a-d1f2-49b3-9e3d-a72d8ba37e80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547491140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2547491140
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1474164053
Short name T288
Test name
Test status
Simulation time 203473336 ps
CPU time 8.24 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:21:02 PM PDT 24
Peak memory 226028 kb
Host smart-99355611-6f4c-4d25-a197-19b5f516315a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474164053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1474164053
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3771731244
Short name T327
Test name
Test status
Simulation time 899362784 ps
CPU time 15.06 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:21:06 PM PDT 24
Peak memory 225704 kb
Host smart-47596a82-0e8b-4e76-9164-ad3eaa1b50de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771731244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
771731244
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2714544537
Short name T539
Test name
Test status
Simulation time 179842543 ps
CPU time 2.58 seconds
Started Jul 14 06:20:53 PM PDT 24
Finished Jul 14 06:20:58 PM PDT 24
Peak memory 217728 kb
Host smart-2d3154cd-baeb-45fd-aacc-4c591f320f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714544537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2714544537
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1251508825
Short name T264
Test name
Test status
Simulation time 381147503 ps
CPU time 26.69 seconds
Started Jul 14 06:20:53 PM PDT 24
Finished Jul 14 06:21:22 PM PDT 24
Peak memory 250832 kb
Host smart-ae393069-4a86-450f-bf18-15b48a2051bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251508825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1251508825
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2762667577
Short name T800
Test name
Test status
Simulation time 446890649 ps
CPU time 7.36 seconds
Started Jul 14 06:20:51 PM PDT 24
Finished Jul 14 06:21:00 PM PDT 24
Peak memory 250440 kb
Host smart-f992eae8-4145-44b9-b692-d265834bea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762667577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2762667577
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4109464738
Short name T396
Test name
Test status
Simulation time 18415599405 ps
CPU time 452.18 seconds
Started Jul 14 06:20:50 PM PDT 24
Finished Jul 14 06:28:23 PM PDT 24
Peak memory 272384 kb
Host smart-717da060-ce52-45fe-85ad-e664c6288a9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109464738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4109464738
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4198778004
Short name T811
Test name
Test status
Simulation time 14114500 ps
CPU time 0.84 seconds
Started Jul 14 06:20:50 PM PDT 24
Finished Jul 14 06:20:51 PM PDT 24
Peak memory 212012 kb
Host smart-a50bc54f-6e6d-4f35-97be-eace8ccafa16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198778004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4198778004
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1530665003
Short name T777
Test name
Test status
Simulation time 57396744 ps
CPU time 1.13 seconds
Started Jul 14 06:23:03 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 209000 kb
Host smart-eaf661fe-f969-47b6-8264-607196289349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530665003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1530665003
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2920428575
Short name T677
Test name
Test status
Simulation time 769914929 ps
CPU time 12.89 seconds
Started Jul 14 06:23:03 PM PDT 24
Finished Jul 14 06:23:17 PM PDT 24
Peak memory 226044 kb
Host smart-e5565385-2851-4f5d-8293-0cac82822433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920428575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2920428575
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2214099394
Short name T629
Test name
Test status
Simulation time 155994984 ps
CPU time 1.67 seconds
Started Jul 14 06:23:01 PM PDT 24
Finished Jul 14 06:23:04 PM PDT 24
Peak memory 217688 kb
Host smart-d7dc0d4f-d256-4e32-bd1b-cf4ea9cdaf2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214099394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2214099394
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2811891024
Short name T322
Test name
Test status
Simulation time 24083437 ps
CPU time 1.72 seconds
Started Jul 14 06:23:02 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 218268 kb
Host smart-b2eb1bdf-1612-4734-b449-936d1ce788bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811891024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2811891024
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1594866868
Short name T341
Test name
Test status
Simulation time 1623280516 ps
CPU time 9.65 seconds
Started Jul 14 06:23:01 PM PDT 24
Finished Jul 14 06:23:12 PM PDT 24
Peak memory 226044 kb
Host smart-92004728-795f-4b3c-8421-01130f7a1ffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594866868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1594866868
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2511550240
Short name T516
Test name
Test status
Simulation time 1175464056 ps
CPU time 9.63 seconds
Started Jul 14 06:23:01 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 226056 kb
Host smart-37584b16-988c-4b68-9b44-6217983a1530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511550240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2511550240
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3492074588
Short name T565
Test name
Test status
Simulation time 1573150576 ps
CPU time 9.37 seconds
Started Jul 14 06:23:01 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 218228 kb
Host smart-d0c7d192-0ad2-4cb0-82a0-7ff43212ab08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492074588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3492074588
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3659144145
Short name T230
Test name
Test status
Simulation time 1534586283 ps
CPU time 14.43 seconds
Started Jul 14 06:23:02 PM PDT 24
Finished Jul 14 06:23:18 PM PDT 24
Peak memory 226016 kb
Host smart-c277ed82-bd28-4937-b465-21af583a3cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659144145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3659144145
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.48078153
Short name T863
Test name
Test status
Simulation time 829407724 ps
CPU time 2.39 seconds
Started Jul 14 06:23:01 PM PDT 24
Finished Jul 14 06:23:04 PM PDT 24
Peak memory 214620 kb
Host smart-ee62772c-4b08-43ff-bc03-c5999ef580a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48078153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.48078153
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3047571668
Short name T527
Test name
Test status
Simulation time 976975935 ps
CPU time 26.21 seconds
Started Jul 14 06:23:04 PM PDT 24
Finished Jul 14 06:23:31 PM PDT 24
Peak memory 250956 kb
Host smart-7f6ca540-cb87-48c8-850d-a5e65c3d19ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047571668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3047571668
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.473188681
Short name T830
Test name
Test status
Simulation time 84850724 ps
CPU time 7.76 seconds
Started Jul 14 06:23:02 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 250464 kb
Host smart-b0ceef0f-3fc9-4757-ac1e-4b516d28a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473188681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.473188681
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2135315592
Short name T182
Test name
Test status
Simulation time 15617196286 ps
CPU time 137.6 seconds
Started Jul 14 06:23:02 PM PDT 24
Finished Jul 14 06:25:20 PM PDT 24
Peak memory 251040 kb
Host smart-3f2fccf1-0a3b-4208-a3ed-390cf4b41752
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135315592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2135315592
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.266589886
Short name T92
Test name
Test status
Simulation time 33252034306 ps
CPU time 294.13 seconds
Started Jul 14 06:23:03 PM PDT 24
Finished Jul 14 06:27:58 PM PDT 24
Peak memory 283904 kb
Host smart-6ba5ed81-06b2-4568-bdb4-e7170b6ce085
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=266589886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.266589886
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2136520014
Short name T754
Test name
Test status
Simulation time 24558993 ps
CPU time 0.99 seconds
Started Jul 14 06:23:01 PM PDT 24
Finished Jul 14 06:23:03 PM PDT 24
Peak memory 211752 kb
Host smart-ef158603-b55f-470e-b7bc-f80e84b4979d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136520014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2136520014
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3645926580
Short name T90
Test name
Test status
Simulation time 19669246 ps
CPU time 0.97 seconds
Started Jul 14 06:23:03 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 208976 kb
Host smart-1b780eb1-b1bd-4298-b92a-5e9fbcb25370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645926580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3645926580
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.809396704
Short name T718
Test name
Test status
Simulation time 431061593 ps
CPU time 11.89 seconds
Started Jul 14 06:23:00 PM PDT 24
Finished Jul 14 06:23:13 PM PDT 24
Peak memory 226020 kb
Host smart-04510f54-0af3-4a61-9003-57ab3ae85f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809396704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.809396704
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1068039451
Short name T581
Test name
Test status
Simulation time 717453937 ps
CPU time 16.82 seconds
Started Jul 14 06:23:01 PM PDT 24
Finished Jul 14 06:23:19 PM PDT 24
Peak memory 217252 kb
Host smart-9e9491cf-ba8b-45cb-b4a8-bb508315c265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068039451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1068039451
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.35432832
Short name T8
Test name
Test status
Simulation time 88511042 ps
CPU time 3.33 seconds
Started Jul 14 06:23:02 PM PDT 24
Finished Jul 14 06:23:07 PM PDT 24
Peak memory 218244 kb
Host smart-2fc4fdba-71c1-4c01-b596-66b6bb85f819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35432832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.35432832
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3686587263
Short name T309
Test name
Test status
Simulation time 517626747 ps
CPU time 13.02 seconds
Started Jul 14 06:23:00 PM PDT 24
Finished Jul 14 06:23:14 PM PDT 24
Peak memory 218180 kb
Host smart-c8bb21cb-0695-424b-8826-f3346527782b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686587263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3686587263
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1715150028
Short name T2
Test name
Test status
Simulation time 205619437 ps
CPU time 7 seconds
Started Jul 14 06:23:03 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 225992 kb
Host smart-cc200eb0-5324-4c6c-8917-56fbae972eef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715150028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1715150028
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1559686137
Short name T620
Test name
Test status
Simulation time 650855760 ps
CPU time 13.27 seconds
Started Jul 14 06:23:00 PM PDT 24
Finished Jul 14 06:23:15 PM PDT 24
Peak memory 218132 kb
Host smart-2965184d-ec1b-4a90-945b-3fbfb1f34482
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559686137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1559686137
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.709272176
Short name T558
Test name
Test status
Simulation time 279271485 ps
CPU time 11.29 seconds
Started Jul 14 06:23:00 PM PDT 24
Finished Jul 14 06:23:12 PM PDT 24
Peak memory 218248 kb
Host smart-0b1711f2-03b9-43dd-b90f-94aaf9761acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709272176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.709272176
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1320594931
Short name T494
Test name
Test status
Simulation time 115944813 ps
CPU time 2.53 seconds
Started Jul 14 06:23:06 PM PDT 24
Finished Jul 14 06:23:09 PM PDT 24
Peak memory 214368 kb
Host smart-2bd47fc2-5685-4ce6-9d2b-e77aa6178e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320594931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1320594931
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2119113178
Short name T840
Test name
Test status
Simulation time 672957245 ps
CPU time 22.67 seconds
Started Jul 14 06:23:01 PM PDT 24
Finished Jul 14 06:23:25 PM PDT 24
Peak memory 250904 kb
Host smart-d67ef150-7f13-4f79-bf7a-c42459b352ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119113178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2119113178
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3451091703
Short name T272
Test name
Test status
Simulation time 199986742 ps
CPU time 8.84 seconds
Started Jul 14 06:23:03 PM PDT 24
Finished Jul 14 06:23:13 PM PDT 24
Peak memory 250432 kb
Host smart-5887c87d-2cac-4f9f-82e9-267706b8fa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451091703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3451091703
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1530276201
Short name T88
Test name
Test status
Simulation time 10116997829 ps
CPU time 95.06 seconds
Started Jul 14 06:23:03 PM PDT 24
Finished Jul 14 06:24:39 PM PDT 24
Peak memory 275608 kb
Host smart-83a3cbb8-cf25-4bff-aa32-045a5ff3b93d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530276201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1530276201
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3253826200
Short name T779
Test name
Test status
Simulation time 19256863 ps
CPU time 0.97 seconds
Started Jul 14 06:23:00 PM PDT 24
Finished Jul 14 06:23:02 PM PDT 24
Peak memory 211868 kb
Host smart-c05a81bc-8bf9-4835-bf8e-8029d7a41276
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253826200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3253826200
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.225002766
Short name T550
Test name
Test status
Simulation time 25613402 ps
CPU time 1.12 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 209044 kb
Host smart-22daedf2-9ace-459f-9bd6-ee44eafccc9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225002766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.225002766
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2976422054
Short name T738
Test name
Test status
Simulation time 3613510412 ps
CPU time 22.76 seconds
Started Jul 14 06:23:07 PM PDT 24
Finished Jul 14 06:23:31 PM PDT 24
Peak memory 218268 kb
Host smart-b12c9be8-fb19-49c0-8fff-2511c82521e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976422054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2976422054
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.516410146
Short name T5
Test name
Test status
Simulation time 161744251 ps
CPU time 2.32 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:13 PM PDT 24
Peak memory 217172 kb
Host smart-83beaf5b-1262-45f0-96a0-e7d4edacb6f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516410146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.516410146
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.714189736
Short name T240
Test name
Test status
Simulation time 85724078 ps
CPU time 1.75 seconds
Started Jul 14 06:23:07 PM PDT 24
Finished Jul 14 06:23:09 PM PDT 24
Peak memory 221936 kb
Host smart-bc724e44-6e88-4786-993d-cabb53792cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714189736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.714189736
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2052152277
Short name T442
Test name
Test status
Simulation time 1466158198 ps
CPU time 11.3 seconds
Started Jul 14 06:23:14 PM PDT 24
Finished Jul 14 06:23:26 PM PDT 24
Peak memory 218920 kb
Host smart-bedc3c3b-241c-408c-93d9-9e09c8c15b16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052152277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2052152277
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.58530409
Short name T726
Test name
Test status
Simulation time 204017164 ps
CPU time 9.11 seconds
Started Jul 14 06:23:07 PM PDT 24
Finished Jul 14 06:23:17 PM PDT 24
Peak memory 226032 kb
Host smart-63ad64ba-1fba-4684-b330-69883e65076e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58530409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_dig
est.58530409
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.831837656
Short name T553
Test name
Test status
Simulation time 1349841572 ps
CPU time 8.9 seconds
Started Jul 14 06:23:10 PM PDT 24
Finished Jul 14 06:23:20 PM PDT 24
Peak memory 218264 kb
Host smart-a2946eb2-5795-4d3b-aace-36c15add61c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831837656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.831837656
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1670819200
Short name T824
Test name
Test status
Simulation time 10913148421 ps
CPU time 16.92 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:28 PM PDT 24
Peak memory 226040 kb
Host smart-69925f7d-f4c4-4d4d-9399-33f87a56cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670819200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1670819200
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.38552621
Short name T631
Test name
Test status
Simulation time 75140014 ps
CPU time 1.53 seconds
Started Jul 14 06:23:02 PM PDT 24
Finished Jul 14 06:23:05 PM PDT 24
Peak memory 217720 kb
Host smart-9f5a7122-2614-442e-8049-7819ef37d407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38552621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.38552621
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.439067749
Short name T638
Test name
Test status
Simulation time 253113285 ps
CPU time 19.39 seconds
Started Jul 14 06:23:08 PM PDT 24
Finished Jul 14 06:23:29 PM PDT 24
Peak memory 250884 kb
Host smart-5a8c373b-2343-4dc2-8ad0-5d5d6a3d9db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439067749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.439067749
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3363924268
Short name T810
Test name
Test status
Simulation time 73526338 ps
CPU time 6.39 seconds
Started Jul 14 06:23:10 PM PDT 24
Finished Jul 14 06:23:18 PM PDT 24
Peak memory 250872 kb
Host smart-2d7e25b5-d45b-4ff8-819d-0560df5b0b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363924268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3363924268
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3642421966
Short name T36
Test name
Test status
Simulation time 17291318718 ps
CPU time 66.01 seconds
Started Jul 14 06:23:06 PM PDT 24
Finished Jul 14 06:24:13 PM PDT 24
Peak memory 267376 kb
Host smart-a1651c92-92a2-4834-9be5-d007ce351717
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642421966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3642421966
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3022856236
Short name T121
Test name
Test status
Simulation time 50085597454 ps
CPU time 511.67 seconds
Started Jul 14 06:23:07 PM PDT 24
Finished Jul 14 06:31:39 PM PDT 24
Peak memory 283172 kb
Host smart-b11920f7-d12d-493c-9804-4f10beb31808
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3022856236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3022856236
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4240144009
Short name T498
Test name
Test status
Simulation time 32349392 ps
CPU time 0.91 seconds
Started Jul 14 06:23:12 PM PDT 24
Finished Jul 14 06:23:13 PM PDT 24
Peak memory 211796 kb
Host smart-f8384a7f-f95b-4034-adeb-0cdda801589b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240144009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4240144009
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.937627253
Short name T383
Test name
Test status
Simulation time 16970502 ps
CPU time 1.15 seconds
Started Jul 14 06:23:08 PM PDT 24
Finished Jul 14 06:23:09 PM PDT 24
Peak memory 209008 kb
Host smart-5450d6ee-6bfe-49eb-8cbe-7de434c6711a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937627253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.937627253
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3400847835
Short name T55
Test name
Test status
Simulation time 990407540 ps
CPU time 12.53 seconds
Started Jul 14 06:23:07 PM PDT 24
Finished Jul 14 06:23:20 PM PDT 24
Peak memory 218216 kb
Host smart-c0dfb5f0-bb53-4ba7-bafe-53dc67f231f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400847835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3400847835
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3174912997
Short name T30
Test name
Test status
Simulation time 652547840 ps
CPU time 15.16 seconds
Started Jul 14 06:23:12 PM PDT 24
Finished Jul 14 06:23:28 PM PDT 24
Peak memory 217468 kb
Host smart-2fe804d7-159c-47b0-ae19-2008b4ffe471
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174912997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3174912997
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1740404671
Short name T307
Test name
Test status
Simulation time 92142543 ps
CPU time 4.21 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:15 PM PDT 24
Peak memory 218108 kb
Host smart-a987e3e5-6568-476c-a2a9-e319c5c65fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740404671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1740404671
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1124072767
Short name T475
Test name
Test status
Simulation time 1015921262 ps
CPU time 10.81 seconds
Started Jul 14 06:23:14 PM PDT 24
Finished Jul 14 06:23:25 PM PDT 24
Peak memory 226072 kb
Host smart-b8fcff8b-0df8-40fd-8170-84135fab10f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124072767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1124072767
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.760980631
Short name T430
Test name
Test status
Simulation time 342503923 ps
CPU time 12.03 seconds
Started Jul 14 06:23:06 PM PDT 24
Finished Jul 14 06:23:19 PM PDT 24
Peak memory 226036 kb
Host smart-8d1b9721-9bf0-4da2-b65d-08a0ff2ac6a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760980631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.760980631
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.538293312
Short name T229
Test name
Test status
Simulation time 2161242279 ps
CPU time 8.7 seconds
Started Jul 14 06:23:08 PM PDT 24
Finished Jul 14 06:23:17 PM PDT 24
Peak memory 226096 kb
Host smart-bad369af-1710-4fe1-8f56-04b0c1a038b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538293312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.538293312
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1291203657
Short name T310
Test name
Test status
Simulation time 41031504 ps
CPU time 0.98 seconds
Started Jul 14 06:23:06 PM PDT 24
Finished Jul 14 06:23:08 PM PDT 24
Peak memory 212052 kb
Host smart-f8f6a7db-0d89-45c2-99e0-3b43e9b404f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291203657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1291203657
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.317999011
Short name T273
Test name
Test status
Simulation time 1052036253 ps
CPU time 15.83 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:26 PM PDT 24
Peak memory 250920 kb
Host smart-6ddb362e-5690-4aac-a9d8-3e08c8b9b22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317999011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.317999011
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2486001859
Short name T724
Test name
Test status
Simulation time 61554117 ps
CPU time 6.36 seconds
Started Jul 14 06:23:08 PM PDT 24
Finished Jul 14 06:23:14 PM PDT 24
Peak memory 250544 kb
Host smart-4646fe6f-25cf-4323-87fa-13b3d714e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486001859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2486001859
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.329667683
Short name T39
Test name
Test status
Simulation time 70932987021 ps
CPU time 285.96 seconds
Started Jul 14 06:23:10 PM PDT 24
Finished Jul 14 06:27:58 PM PDT 24
Peak memory 283840 kb
Host smart-cb10805a-3e9b-4dec-bbae-537af0a66c9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329667683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.329667683
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1389827836
Short name T344
Test name
Test status
Simulation time 17778251 ps
CPU time 0.97 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 212828 kb
Host smart-f3d92c85-2e7d-405a-8365-7217a9b2a6ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389827836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1389827836
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4239590021
Short name T192
Test name
Test status
Simulation time 80023138 ps
CPU time 0.96 seconds
Started Jul 14 06:23:13 PM PDT 24
Finished Jul 14 06:23:15 PM PDT 24
Peak memory 208976 kb
Host smart-64914fca-e27d-4fad-8bee-151b6cc21d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239590021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4239590021
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1807140075
Short name T384
Test name
Test status
Simulation time 870902920 ps
CPU time 11.91 seconds
Started Jul 14 06:23:14 PM PDT 24
Finished Jul 14 06:23:27 PM PDT 24
Peak memory 226052 kb
Host smart-6d2afafe-fabc-4407-84ae-59caa08dc488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807140075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1807140075
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3447480756
Short name T525
Test name
Test status
Simulation time 1050305216 ps
CPU time 6.23 seconds
Started Jul 14 06:23:12 PM PDT 24
Finished Jul 14 06:23:19 PM PDT 24
Peak memory 217540 kb
Host smart-290f97e8-3110-4931-b363-273b4e850b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447480756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3447480756
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3296054221
Short name T781
Test name
Test status
Simulation time 109587668 ps
CPU time 2.62 seconds
Started Jul 14 06:23:07 PM PDT 24
Finished Jul 14 06:23:10 PM PDT 24
Peak memory 222420 kb
Host smart-d7d6b941-55de-4623-9534-3f67411ccf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296054221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3296054221
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1591562378
Short name T709
Test name
Test status
Simulation time 1727458016 ps
CPU time 18.42 seconds
Started Jul 14 06:23:19 PM PDT 24
Finished Jul 14 06:23:38 PM PDT 24
Peak memory 225964 kb
Host smart-1c7429e7-70d0-4a01-8243-3ee1359dd505
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591562378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1591562378
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2415851046
Short name T506
Test name
Test status
Simulation time 200470160 ps
CPU time 10.16 seconds
Started Jul 14 06:23:13 PM PDT 24
Finished Jul 14 06:23:24 PM PDT 24
Peak memory 226196 kb
Host smart-3f81c375-f4a7-4ff9-a403-6f393afb9896
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415851046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2415851046
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.889725505
Short name T61
Test name
Test status
Simulation time 341836153 ps
CPU time 6.08 seconds
Started Jul 14 06:23:14 PM PDT 24
Finished Jul 14 06:23:21 PM PDT 24
Peak memory 218168 kb
Host smart-8f61c141-89ec-46de-926c-d883b21e80ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889725505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.889725505
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.510957953
Short name T370
Test name
Test status
Simulation time 428426309 ps
CPU time 9.1 seconds
Started Jul 14 06:23:08 PM PDT 24
Finished Jul 14 06:23:18 PM PDT 24
Peak memory 218264 kb
Host smart-575f6705-438a-40b1-9384-89e487914524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510957953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.510957953
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.581737903
Short name T603
Test name
Test status
Simulation time 65969740 ps
CPU time 2.76 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:14 PM PDT 24
Peak memory 217792 kb
Host smart-5056c65d-4eae-47b3-ae25-42016f7631a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581737903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.581737903
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3246716481
Short name T630
Test name
Test status
Simulation time 253769057 ps
CPU time 30.56 seconds
Started Jul 14 06:23:10 PM PDT 24
Finished Jul 14 06:23:42 PM PDT 24
Peak memory 250976 kb
Host smart-86851c56-18b3-49d9-9af4-a337ed2b0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246716481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3246716481
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3280932877
Short name T87
Test name
Test status
Simulation time 895930498 ps
CPU time 8.28 seconds
Started Jul 14 06:23:10 PM PDT 24
Finished Jul 14 06:23:20 PM PDT 24
Peak memory 250988 kb
Host smart-c73dd3b4-72d4-4e9d-a604-18c9e47332b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280932877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3280932877
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3680689328
Short name T41
Test name
Test status
Simulation time 48744606747 ps
CPU time 62.41 seconds
Started Jul 14 06:23:14 PM PDT 24
Finished Jul 14 06:24:17 PM PDT 24
Peak memory 280220 kb
Host smart-4c45ed12-851d-4fd1-b102-b07c4c0bf19b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680689328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3680689328
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3744221788
Short name T429
Test name
Test status
Simulation time 19297821 ps
CPU time 0.74 seconds
Started Jul 14 06:23:09 PM PDT 24
Finished Jul 14 06:23:11 PM PDT 24
Peak memory 207068 kb
Host smart-a51ade2d-b35c-49c8-84dd-5830ba7d1168
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744221788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3744221788
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3354302514
Short name T10
Test name
Test status
Simulation time 97218937 ps
CPU time 1.09 seconds
Started Jul 14 06:23:13 PM PDT 24
Finished Jul 14 06:23:15 PM PDT 24
Peak memory 209000 kb
Host smart-3a48b72e-ce00-4d46-ae79-4d523956f96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354302514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3354302514
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.692242142
Short name T463
Test name
Test status
Simulation time 213565792 ps
CPU time 10.32 seconds
Started Jul 14 06:23:12 PM PDT 24
Finished Jul 14 06:23:23 PM PDT 24
Peak memory 226000 kb
Host smart-b8bcd0c4-76eb-471e-b9c2-c8813a83086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692242142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.692242142
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1997539883
Short name T96
Test name
Test status
Simulation time 441928337 ps
CPU time 6.97 seconds
Started Jul 14 06:23:14 PM PDT 24
Finished Jul 14 06:23:22 PM PDT 24
Peak memory 217380 kb
Host smart-b0e1e7e5-a55a-4065-8fff-4ef05f163c57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997539883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1997539883
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3404154965
Short name T251
Test name
Test status
Simulation time 32341674 ps
CPU time 2.14 seconds
Started Jul 14 06:23:15 PM PDT 24
Finished Jul 14 06:23:18 PM PDT 24
Peak memory 218200 kb
Host smart-19741b21-2652-492e-8397-35e7e7d8bc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404154965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3404154965
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1915796429
Short name T836
Test name
Test status
Simulation time 223060305 ps
CPU time 11.56 seconds
Started Jul 14 06:23:16 PM PDT 24
Finished Jul 14 06:23:28 PM PDT 24
Peak memory 225936 kb
Host smart-0763c23b-adca-43da-9bdc-0ef345d78a02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915796429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1915796429
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.4290359104
Short name T411
Test name
Test status
Simulation time 3759147320 ps
CPU time 15.68 seconds
Started Jul 14 06:23:12 PM PDT 24
Finished Jul 14 06:23:29 PM PDT 24
Peak memory 226080 kb
Host smart-3ab4b42a-c3db-4152-85da-cfa94d35c0f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290359104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.4290359104
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3273420352
Short name T619
Test name
Test status
Simulation time 1876193086 ps
CPU time 10.01 seconds
Started Jul 14 06:23:15 PM PDT 24
Finished Jul 14 06:23:26 PM PDT 24
Peak memory 226036 kb
Host smart-a60af342-66af-4791-99b9-bf8b1227e841
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273420352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3273420352
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3223087524
Short name T361
Test name
Test status
Simulation time 436584982 ps
CPU time 10.17 seconds
Started Jul 14 06:23:15 PM PDT 24
Finished Jul 14 06:23:26 PM PDT 24
Peak memory 218316 kb
Host smart-ac764fcf-09e8-4555-b120-30c5254a1d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223087524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3223087524
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2905462652
Short name T317
Test name
Test status
Simulation time 124888465 ps
CPU time 7.16 seconds
Started Jul 14 06:23:13 PM PDT 24
Finished Jul 14 06:23:21 PM PDT 24
Peak memory 217716 kb
Host smart-9e9e2762-6434-4a24-9978-382ae919f217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905462652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2905462652
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3669116964
Short name T233
Test name
Test status
Simulation time 211211975 ps
CPU time 23.87 seconds
Started Jul 14 06:23:13 PM PDT 24
Finished Jul 14 06:23:38 PM PDT 24
Peak memory 250888 kb
Host smart-66aa56e1-c614-47cf-b3be-9aa6300b85bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669116964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3669116964
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4201990551
Short name T593
Test name
Test status
Simulation time 211006137 ps
CPU time 6.99 seconds
Started Jul 14 06:23:14 PM PDT 24
Finished Jul 14 06:23:22 PM PDT 24
Peak memory 250856 kb
Host smart-60a5daed-41f5-49cc-afc4-c51923d7dcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201990551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4201990551
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2221636426
Short name T798
Test name
Test status
Simulation time 11978015351 ps
CPU time 129.34 seconds
Started Jul 14 06:23:13 PM PDT 24
Finished Jul 14 06:25:23 PM PDT 24
Peak memory 277736 kb
Host smart-dfc0a3c7-dc8e-47d9-82c9-ab1240912307
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221636426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2221636426
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2013785001
Short name T676
Test name
Test status
Simulation time 34924454 ps
CPU time 0.89 seconds
Started Jul 14 06:23:15 PM PDT 24
Finished Jul 14 06:23:17 PM PDT 24
Peak memory 211864 kb
Host smart-0f6e1e84-d671-4b9d-8e40-cdb69cd47575
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013785001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2013785001
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1126071340
Short name T590
Test name
Test status
Simulation time 16989101 ps
CPU time 0.83 seconds
Started Jul 14 06:23:20 PM PDT 24
Finished Jul 14 06:23:22 PM PDT 24
Peak memory 208984 kb
Host smart-6c3dd92f-bf18-4704-bd99-10e3c93a176c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126071340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1126071340
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.4150990013
Short name T408
Test name
Test status
Simulation time 1074350984 ps
CPU time 9.15 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:32 PM PDT 24
Peak memory 218176 kb
Host smart-a367850a-dadf-45e6-8188-399a8480a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150990013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.4150990013
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2364414961
Short name T615
Test name
Test status
Simulation time 80934153 ps
CPU time 2.67 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:26 PM PDT 24
Peak memory 217024 kb
Host smart-d3bdd011-6b0f-4868-945b-6819ac7c4156
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364414961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2364414961
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4159834297
Short name T163
Test name
Test status
Simulation time 58736358 ps
CPU time 3.12 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:26 PM PDT 24
Peak memory 222292 kb
Host smart-c1d1bab9-b94a-4a19-a031-fe6f31faa000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159834297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4159834297
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1821987234
Short name T394
Test name
Test status
Simulation time 1241968869 ps
CPU time 12.61 seconds
Started Jul 14 06:23:18 PM PDT 24
Finished Jul 14 06:23:32 PM PDT 24
Peak memory 218132 kb
Host smart-670e2bf5-a670-463d-9bc8-ded0ebde5efa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821987234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1821987234
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3412516272
Short name T675
Test name
Test status
Simulation time 761965955 ps
CPU time 14.38 seconds
Started Jul 14 06:23:20 PM PDT 24
Finished Jul 14 06:23:35 PM PDT 24
Peak memory 226016 kb
Host smart-de4a8928-f550-4fdc-980a-ee6d1727f055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412516272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3412516272
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3022723864
Short name T354
Test name
Test status
Simulation time 942470423 ps
CPU time 6.11 seconds
Started Jul 14 06:23:20 PM PDT 24
Finished Jul 14 06:23:27 PM PDT 24
Peak memory 218188 kb
Host smart-61e3c0f6-9e5f-4517-874e-dcfe9c85fa71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022723864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3022723864
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3857854394
Short name T535
Test name
Test status
Simulation time 228161715 ps
CPU time 6.52 seconds
Started Jul 14 06:23:20 PM PDT 24
Finished Jul 14 06:23:28 PM PDT 24
Peak memory 218228 kb
Host smart-06c7c16b-44fe-43c9-b49b-958594eba277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857854394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3857854394
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1255826166
Short name T654
Test name
Test status
Simulation time 18507377 ps
CPU time 1.41 seconds
Started Jul 14 06:23:12 PM PDT 24
Finished Jul 14 06:23:15 PM PDT 24
Peak memory 217616 kb
Host smart-93a5199d-8005-404d-95a4-c842c1660d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255826166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1255826166
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.4153808460
Short name T510
Test name
Test status
Simulation time 3183978803 ps
CPU time 28.65 seconds
Started Jul 14 06:23:13 PM PDT 24
Finished Jul 14 06:23:43 PM PDT 24
Peak memory 251040 kb
Host smart-1be41d08-5706-48f2-977d-39f98d3d03d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153808460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4153808460
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2452917559
Short name T784
Test name
Test status
Simulation time 218374286 ps
CPU time 8.59 seconds
Started Jul 14 06:23:13 PM PDT 24
Finished Jul 14 06:23:22 PM PDT 24
Peak memory 250452 kb
Host smart-fca317af-9d1a-422d-a449-956f0c589194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452917559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2452917559
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2707278592
Short name T197
Test name
Test status
Simulation time 8184848750 ps
CPU time 263.3 seconds
Started Jul 14 06:23:19 PM PDT 24
Finished Jul 14 06:27:43 PM PDT 24
Peak memory 300160 kb
Host smart-06a8acc3-3cdd-41e3-8f75-141136493c43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707278592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2707278592
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1076183745
Short name T704
Test name
Test status
Simulation time 39205445 ps
CPU time 0.97 seconds
Started Jul 14 06:23:15 PM PDT 24
Finished Jul 14 06:23:17 PM PDT 24
Peak memory 211880 kb
Host smart-5565fd87-da39-4c60-a880-6d7e5f2cd51f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076183745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1076183745
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1184306583
Short name T451
Test name
Test status
Simulation time 81029246 ps
CPU time 0.89 seconds
Started Jul 14 06:23:19 PM PDT 24
Finished Jul 14 06:23:21 PM PDT 24
Peak memory 208836 kb
Host smart-cbecc9b4-ec7b-4576-9055-0056204a9a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184306583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1184306583
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.4113993462
Short name T651
Test name
Test status
Simulation time 3615966283 ps
CPU time 11.52 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:34 PM PDT 24
Peak memory 219020 kb
Host smart-51b58de3-d6cc-49bb-be4e-96bdab19e54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113993462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.4113993462
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3904580042
Short name T368
Test name
Test status
Simulation time 614892806 ps
CPU time 3.96 seconds
Started Jul 14 06:23:19 PM PDT 24
Finished Jul 14 06:23:24 PM PDT 24
Peak memory 217252 kb
Host smart-824fa7d7-d1c3-4fb1-8e28-6ae5e91a10c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904580042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3904580042
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.940281016
Short name T286
Test name
Test status
Simulation time 41814366 ps
CPU time 2.53 seconds
Started Jul 14 06:23:22 PM PDT 24
Finished Jul 14 06:23:26 PM PDT 24
Peak memory 222132 kb
Host smart-76b19f52-491a-4e50-9579-d4c3c5dfcc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940281016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.940281016
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1761123874
Short name T188
Test name
Test status
Simulation time 660421538 ps
CPU time 9.39 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:32 PM PDT 24
Peak memory 225908 kb
Host smart-c941cc00-5c2a-43af-89c8-839d8ebccf7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761123874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1761123874
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1419581292
Short name T719
Test name
Test status
Simulation time 324228632 ps
CPU time 10.81 seconds
Started Jul 14 06:23:22 PM PDT 24
Finished Jul 14 06:23:34 PM PDT 24
Peak memory 218184 kb
Host smart-24d0e65d-02f4-4757-b931-70b7a6762ead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419581292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1419581292
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1535267494
Short name T486
Test name
Test status
Simulation time 872672950 ps
CPU time 15.52 seconds
Started Jul 14 06:23:20 PM PDT 24
Finished Jul 14 06:23:37 PM PDT 24
Peak memory 225932 kb
Host smart-e87bd4da-ca9e-4730-be0f-c2fee2b6b650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535267494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1535267494
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1758818519
Short name T60
Test name
Test status
Simulation time 113630690 ps
CPU time 2.44 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:25 PM PDT 24
Peak memory 214388 kb
Host smart-93001936-c0eb-4387-998a-2dc6b3752893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758818519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1758818519
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.325807363
Short name T703
Test name
Test status
Simulation time 1281188532 ps
CPU time 22.4 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:45 PM PDT 24
Peak memory 250984 kb
Host smart-7af99c65-9e4c-4bd7-938e-334e5a4b71d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325807363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.325807363
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3656604207
Short name T261
Test name
Test status
Simulation time 219380565 ps
CPU time 3.08 seconds
Started Jul 14 06:23:20 PM PDT 24
Finished Jul 14 06:23:25 PM PDT 24
Peak memory 222224 kb
Host smart-80a6404f-e9f4-47ee-a1ae-bc2cb2713b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656604207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3656604207
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1481156679
Short name T15
Test name
Test status
Simulation time 20755095819 ps
CPU time 319.75 seconds
Started Jul 14 06:23:18 PM PDT 24
Finished Jul 14 06:28:39 PM PDT 24
Peak memory 283656 kb
Host smart-d2834240-fe86-42ed-b99b-3be4fe0111f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481156679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1481156679
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1662871925
Short name T470
Test name
Test status
Simulation time 42914686849 ps
CPU time 421 seconds
Started Jul 14 06:23:18 PM PDT 24
Finished Jul 14 06:30:20 PM PDT 24
Peak memory 372324 kb
Host smart-f38ce181-614c-496c-9a39-8df6f566c378
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1662871925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1662871925
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.633103480
Short name T542
Test name
Test status
Simulation time 20546406 ps
CPU time 0.92 seconds
Started Jul 14 06:23:18 PM PDT 24
Finished Jul 14 06:23:20 PM PDT 24
Peak memory 211960 kb
Host smart-8830e7cb-42ab-4bb6-a29b-fb40db05e4b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633103480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.633103480
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4286673019
Short name T570
Test name
Test status
Simulation time 31684436 ps
CPU time 0.9 seconds
Started Jul 14 06:23:31 PM PDT 24
Finished Jul 14 06:23:33 PM PDT 24
Peak memory 208996 kb
Host smart-3b78854b-9f6f-474b-8dde-c1b870486f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286673019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4286673019
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.4061058812
Short name T488
Test name
Test status
Simulation time 355123579 ps
CPU time 17 seconds
Started Jul 14 06:23:20 PM PDT 24
Finished Jul 14 06:23:38 PM PDT 24
Peak memory 218168 kb
Host smart-502dec5d-381c-41d5-b42d-ead7f2af5811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061058812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4061058812
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1842738340
Short name T672
Test name
Test status
Simulation time 2856536115 ps
CPU time 7.41 seconds
Started Jul 14 06:23:31 PM PDT 24
Finished Jul 14 06:23:39 PM PDT 24
Peak memory 217788 kb
Host smart-e5449b05-22ae-4572-9e48-a7b6a125f40c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842738340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1842738340
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1559766054
Short name T594
Test name
Test status
Simulation time 101056089 ps
CPU time 2.85 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:25 PM PDT 24
Peak memory 218192 kb
Host smart-cd34c57b-b49a-455b-9d73-70b7253b6c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559766054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1559766054
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2116151559
Short name T440
Test name
Test status
Simulation time 1146845203 ps
CPU time 14.88 seconds
Started Jul 14 06:23:26 PM PDT 24
Finished Jul 14 06:23:42 PM PDT 24
Peak memory 226012 kb
Host smart-040a24fe-d309-47a5-8bba-23eda48ea9d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116151559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2116151559
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1910804315
Short name T610
Test name
Test status
Simulation time 3734800070 ps
CPU time 17.98 seconds
Started Jul 14 06:23:31 PM PDT 24
Finished Jul 14 06:23:49 PM PDT 24
Peak memory 226112 kb
Host smart-70d0522c-e8db-48ae-b0a6-6d05ac12c2ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910804315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1910804315
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2763548376
Short name T480
Test name
Test status
Simulation time 489341050 ps
CPU time 10.89 seconds
Started Jul 14 06:23:31 PM PDT 24
Finished Jul 14 06:23:43 PM PDT 24
Peak memory 226108 kb
Host smart-7f79c044-582b-4a22-b81d-dd21a33550be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763548376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2763548376
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1025413412
Short name T691
Test name
Test status
Simulation time 1173919633 ps
CPU time 10.23 seconds
Started Jul 14 06:23:18 PM PDT 24
Finished Jul 14 06:23:29 PM PDT 24
Peak memory 226120 kb
Host smart-c67d6105-836c-4030-a496-c1bfef25c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025413412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1025413412
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.4008827184
Short name T495
Test name
Test status
Simulation time 15277600 ps
CPU time 1.31 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:24 PM PDT 24
Peak memory 217680 kb
Host smart-664e68e8-6a9d-4d5b-9446-57630d0db4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008827184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4008827184
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2015052204
Short name T829
Test name
Test status
Simulation time 252715861 ps
CPU time 23.25 seconds
Started Jul 14 06:23:20 PM PDT 24
Finished Jul 14 06:23:44 PM PDT 24
Peak memory 251164 kb
Host smart-f01378c1-808b-4ab9-a5e9-e4d9122a306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015052204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2015052204
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3740354479
Short name T174
Test name
Test status
Simulation time 98244121 ps
CPU time 7.77 seconds
Started Jul 14 06:23:21 PM PDT 24
Finished Jul 14 06:23:31 PM PDT 24
Peak memory 250380 kb
Host smart-72fff0dc-3865-407a-b8c4-957bfa2cfc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740354479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3740354479
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2648678719
Short name T851
Test name
Test status
Simulation time 5522714454 ps
CPU time 24.23 seconds
Started Jul 14 06:23:24 PM PDT 24
Finished Jul 14 06:23:49 PM PDT 24
Peak memory 226068 kb
Host smart-549a54db-4b11-491a-a278-402ebbc4a3c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648678719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2648678719
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1031999680
Short name T159
Test name
Test status
Simulation time 9226031175 ps
CPU time 365.47 seconds
Started Jul 14 06:23:25 PM PDT 24
Finished Jul 14 06:29:32 PM PDT 24
Peak memory 496916 kb
Host smart-912af7c4-dfbe-4e82-83a1-e9ce3d3d1830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1031999680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1031999680
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3181237105
Short name T183
Test name
Test status
Simulation time 46847717 ps
CPU time 0.93 seconds
Started Jul 14 06:23:19 PM PDT 24
Finished Jul 14 06:23:21 PM PDT 24
Peak memory 211876 kb
Host smart-47ee8c55-121f-4c38-be38-52a172d73def
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181237105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3181237105
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.903972590
Short name T73
Test name
Test status
Simulation time 157830960 ps
CPU time 1.66 seconds
Started Jul 14 06:23:26 PM PDT 24
Finished Jul 14 06:23:28 PM PDT 24
Peak memory 208980 kb
Host smart-3f1f2f54-bf11-44bb-9e6f-e11019edfc06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903972590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.903972590
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.4224328738
Short name T35
Test name
Test status
Simulation time 872870698 ps
CPU time 12.06 seconds
Started Jul 14 06:23:25 PM PDT 24
Finished Jul 14 06:23:38 PM PDT 24
Peak memory 218180 kb
Host smart-5c4a7307-b48c-4aec-b447-d3189fb9deac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224328738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4224328738
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3850340173
Short name T575
Test name
Test status
Simulation time 1416801229 ps
CPU time 15.71 seconds
Started Jul 14 06:23:23 PM PDT 24
Finished Jul 14 06:23:40 PM PDT 24
Peak memory 217484 kb
Host smart-130da873-8af4-40a3-a5bf-1f0d9e265c31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850340173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3850340173
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3448566172
Short name T284
Test name
Test status
Simulation time 370453647 ps
CPU time 2.7 seconds
Started Jul 14 06:23:31 PM PDT 24
Finished Jul 14 06:23:34 PM PDT 24
Peak memory 218228 kb
Host smart-65f4fcc6-0d8c-4bd0-9bb5-d6cc92734900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448566172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3448566172
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.24953651
Short name T583
Test name
Test status
Simulation time 295223630 ps
CPU time 13.72 seconds
Started Jul 14 06:23:27 PM PDT 24
Finished Jul 14 06:23:41 PM PDT 24
Peak memory 218876 kb
Host smart-8ba7ca59-56c2-4a02-99d9-4e51572c6d54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24953651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.24953651
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.315156203
Short name T864
Test name
Test status
Simulation time 586632284 ps
CPU time 13.78 seconds
Started Jul 14 06:23:25 PM PDT 24
Finished Jul 14 06:23:40 PM PDT 24
Peak memory 226020 kb
Host smart-68c41b8f-8536-4aad-8a0b-7cd34bb50c2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315156203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.315156203
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1375098005
Short name T684
Test name
Test status
Simulation time 1428507294 ps
CPU time 8.65 seconds
Started Jul 14 06:23:25 PM PDT 24
Finished Jul 14 06:23:35 PM PDT 24
Peak memory 225924 kb
Host smart-16a0782c-a2ea-4ea5-b78c-b113fe488358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375098005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1375098005
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2314090163
Short name T576
Test name
Test status
Simulation time 444982980 ps
CPU time 7.06 seconds
Started Jul 14 06:23:31 PM PDT 24
Finished Jul 14 06:23:39 PM PDT 24
Peak memory 218364 kb
Host smart-631b98cb-3ba6-400e-bb38-68fb0d5e17e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314090163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2314090163
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.349643119
Short name T636
Test name
Test status
Simulation time 160343528 ps
CPU time 2.96 seconds
Started Jul 14 06:23:26 PM PDT 24
Finished Jul 14 06:23:30 PM PDT 24
Peak memory 214952 kb
Host smart-c7323e45-9063-44e7-8bc0-12af223b1ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349643119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.349643119
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2576941303
Short name T483
Test name
Test status
Simulation time 329652304 ps
CPU time 28.68 seconds
Started Jul 14 06:23:24 PM PDT 24
Finished Jul 14 06:23:53 PM PDT 24
Peak memory 250932 kb
Host smart-0e8d7652-a484-46f5-863e-8f5746d2edeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576941303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2576941303
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3853924843
Short name T566
Test name
Test status
Simulation time 98820735 ps
CPU time 7.41 seconds
Started Jul 14 06:23:25 PM PDT 24
Finished Jul 14 06:23:33 PM PDT 24
Peak memory 250880 kb
Host smart-53ce1e40-3eab-498e-9185-0bb304040eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853924843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3853924843
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2939684079
Short name T412
Test name
Test status
Simulation time 9077754269 ps
CPU time 208.06 seconds
Started Jul 14 06:23:23 PM PDT 24
Finished Jul 14 06:26:52 PM PDT 24
Peak memory 267368 kb
Host smart-3e92a76c-5e74-4b17-a327-e99fcb5edafd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939684079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2939684079
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1261337570
Short name T804
Test name
Test status
Simulation time 37032755 ps
CPU time 0.91 seconds
Started Jul 14 06:23:24 PM PDT 24
Finished Jul 14 06:23:25 PM PDT 24
Peak memory 211812 kb
Host smart-98043866-50bb-4f60-855e-89513ad49559
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261337570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1261337570
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.801536270
Short name T34
Test name
Test status
Simulation time 70235400 ps
CPU time 1.1 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:02 PM PDT 24
Peak memory 208960 kb
Host smart-2b559d8f-a484-40c8-83c2-b133283056de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801536270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.801536270
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.574017554
Short name T225
Test name
Test status
Simulation time 13823555 ps
CPU time 0.84 seconds
Started Jul 14 06:20:57 PM PDT 24
Finished Jul 14 06:20:59 PM PDT 24
Peak memory 208828 kb
Host smart-8360583b-7e43-40d8-8cae-7ddf9aeff093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574017554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.574017554
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1308437914
Short name T643
Test name
Test status
Simulation time 1262470067 ps
CPU time 10.71 seconds
Started Jul 14 06:20:55 PM PDT 24
Finished Jul 14 06:21:07 PM PDT 24
Peak memory 226096 kb
Host smart-0a1c45bb-5240-4792-9ab5-7eebadcdd4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308437914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1308437914
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3197252833
Short name T101
Test name
Test status
Simulation time 152767480 ps
CPU time 2.08 seconds
Started Jul 14 06:20:58 PM PDT 24
Finished Jul 14 06:21:01 PM PDT 24
Peak memory 217068 kb
Host smart-d7cd5159-cc47-4166-8c5e-5878ef6796a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197252833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3197252833
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2610358574
Short name T687
Test name
Test status
Simulation time 12916853553 ps
CPU time 42.56 seconds
Started Jul 14 06:20:58 PM PDT 24
Finished Jul 14 06:21:42 PM PDT 24
Peak memory 226080 kb
Host smart-6fecd64f-a4d7-4b14-b34c-4e6c2578e8d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610358574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2610358574
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.961289245
Short name T665
Test name
Test status
Simulation time 535022787 ps
CPU time 4.1 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:04 PM PDT 24
Peak memory 217712 kb
Host smart-f3eafb47-18a7-4d93-83d7-1bc4133feb9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961289245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.961289245
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1592104934
Short name T428
Test name
Test status
Simulation time 163334791 ps
CPU time 3.86 seconds
Started Jul 14 06:21:01 PM PDT 24
Finished Jul 14 06:21:06 PM PDT 24
Peak memory 218148 kb
Host smart-da31e5d1-1ef0-4fc2-8a82-012993fe6916
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592104934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1592104934
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1128267106
Short name T859
Test name
Test status
Simulation time 1582850025 ps
CPU time 43.87 seconds
Started Jul 14 06:21:02 PM PDT 24
Finished Jul 14 06:21:47 PM PDT 24
Peak memory 217640 kb
Host smart-96a69937-5537-4d44-991e-6579121f6d17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128267106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1128267106
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3284000869
Short name T617
Test name
Test status
Simulation time 50383520 ps
CPU time 2.23 seconds
Started Jul 14 06:21:00 PM PDT 24
Finished Jul 14 06:21:04 PM PDT 24
Peak memory 217732 kb
Host smart-96fdb31f-a1f4-47f9-b5ac-3550eef78ffc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284000869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3284000869
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3649772569
Short name T497
Test name
Test status
Simulation time 2332440094 ps
CPU time 82.53 seconds
Started Jul 14 06:20:58 PM PDT 24
Finished Jul 14 06:22:22 PM PDT 24
Peak memory 277796 kb
Host smart-9572f4f0-b275-4501-bf59-141d9e368578
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649772569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3649772569
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1802777272
Short name T242
Test name
Test status
Simulation time 1109691768 ps
CPU time 6.26 seconds
Started Jul 14 06:20:56 PM PDT 24
Finished Jul 14 06:21:03 PM PDT 24
Peak memory 221924 kb
Host smart-e5c9c735-595c-453e-b8d3-87eae6d1c854
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802777272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1802777272
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.925965716
Short name T460
Test name
Test status
Simulation time 150089740 ps
CPU time 2.83 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:20:56 PM PDT 24
Peak memory 222388 kb
Host smart-ba13a8cc-b930-48db-af20-a8abd53ef263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925965716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.925965716
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.615199371
Short name T223
Test name
Test status
Simulation time 804024167 ps
CPU time 5.91 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:07 PM PDT 24
Peak memory 214620 kb
Host smart-75616718-ea94-4fdc-b8b9-45da0c821a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615199371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.615199371
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.4252151860
Short name T391
Test name
Test status
Simulation time 1105596030 ps
CPU time 12.84 seconds
Started Jul 14 06:20:57 PM PDT 24
Finished Jul 14 06:21:10 PM PDT 24
Peak memory 226020 kb
Host smart-c382248d-a2ea-41e8-ac46-12be41c3a321
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252151860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4252151860
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1563756434
Short name T362
Test name
Test status
Simulation time 412262495 ps
CPU time 16.06 seconds
Started Jul 14 06:21:00 PM PDT 24
Finished Jul 14 06:21:18 PM PDT 24
Peak memory 225940 kb
Host smart-814dc166-4b85-4414-aafe-0621ef31e279
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563756434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1563756434
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1646152759
Short name T860
Test name
Test status
Simulation time 1161521456 ps
CPU time 9.05 seconds
Started Jul 14 06:21:01 PM PDT 24
Finished Jul 14 06:21:11 PM PDT 24
Peak memory 218228 kb
Host smart-fe1c2981-9731-4b6a-9de5-50fc1df49856
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646152759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
646152759
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.383743207
Short name T761
Test name
Test status
Simulation time 229318019 ps
CPU time 6.46 seconds
Started Jul 14 06:21:00 PM PDT 24
Finished Jul 14 06:21:08 PM PDT 24
Peak memory 224880 kb
Host smart-d40cee03-ae53-48e6-a975-5c1b41011dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383743207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.383743207
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2173536024
Short name T669
Test name
Test status
Simulation time 268398870 ps
CPU time 4.11 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:20:58 PM PDT 24
Peak memory 217728 kb
Host smart-c45c67dd-850b-4619-a081-18eb50007241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173536024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2173536024
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3016923014
Short name T22
Test name
Test status
Simulation time 1027930776 ps
CPU time 26.53 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:21:21 PM PDT 24
Peak memory 250948 kb
Host smart-a4f865c0-d1e3-4e64-8981-1ec3717b97e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016923014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3016923014
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4035336059
Short name T680
Test name
Test status
Simulation time 368629939 ps
CPU time 8.26 seconds
Started Jul 14 06:20:52 PM PDT 24
Finished Jul 14 06:21:02 PM PDT 24
Peak memory 251160 kb
Host smart-b4d47dae-2de8-41ac-ae23-42209f62b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035336059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4035336059
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1575475241
Short name T56
Test name
Test status
Simulation time 10287413036 ps
CPU time 157.27 seconds
Started Jul 14 06:21:01 PM PDT 24
Finished Jul 14 06:23:40 PM PDT 24
Peak memory 275084 kb
Host smart-d6acf447-ca1d-4b28-8c67-2972dba47406
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575475241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1575475241
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1656845874
Short name T33
Test name
Test status
Simulation time 114809616 ps
CPU time 0.76 seconds
Started Jul 14 06:20:53 PM PDT 24
Finished Jul 14 06:20:56 PM PDT 24
Peak memory 208120 kb
Host smart-afc46a1d-2179-4c51-9d34-8224076fb621
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656845874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1656845874
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.4129248618
Short name T607
Test name
Test status
Simulation time 17173447 ps
CPU time 0.97 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:02 PM PDT 24
Peak memory 208984 kb
Host smart-689ae448-aa5c-48ca-9e10-6a00694afa45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129248618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4129248618
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3679132566
Short name T834
Test name
Test status
Simulation time 35275445 ps
CPU time 0.8 seconds
Started Jul 14 06:21:04 PM PDT 24
Finished Jul 14 06:21:05 PM PDT 24
Peak memory 208856 kb
Host smart-187505a5-9b85-4b96-b83b-8e2271f73e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679132566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3679132566
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1653287788
Short name T305
Test name
Test status
Simulation time 1942924355 ps
CPU time 21.35 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:22 PM PDT 24
Peak memory 225996 kb
Host smart-d1cd6ec4-9673-49df-9911-05511ddb2a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653287788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1653287788
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2465883903
Short name T32
Test name
Test status
Simulation time 1766249548 ps
CPU time 8.05 seconds
Started Jul 14 06:21:03 PM PDT 24
Finished Jul 14 06:21:12 PM PDT 24
Peak memory 217248 kb
Host smart-e1882213-da4e-4a34-9634-c8398cdcc352
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465883903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2465883903
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1023809731
Short name T670
Test name
Test status
Simulation time 2599142364 ps
CPU time 21.59 seconds
Started Jul 14 06:21:03 PM PDT 24
Finished Jul 14 06:21:25 PM PDT 24
Peak memory 218844 kb
Host smart-030612fc-b65e-4b0b-8328-222141e44967
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023809731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1023809731
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.557131962
Short name T358
Test name
Test status
Simulation time 7472411612 ps
CPU time 44.59 seconds
Started Jul 14 06:21:02 PM PDT 24
Finished Jul 14 06:21:48 PM PDT 24
Peak memory 217780 kb
Host smart-f69cf972-de50-4eba-9215-970a96bc3836
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557131962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.557131962
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1816654002
Short name T402
Test name
Test status
Simulation time 296800071 ps
CPU time 6.43 seconds
Started Jul 14 06:20:58 PM PDT 24
Finished Jul 14 06:21:05 PM PDT 24
Peak memory 218216 kb
Host smart-cfefe008-5dd4-4b97-9623-392fdf633f98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816654002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1816654002
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1936684305
Short name T701
Test name
Test status
Simulation time 865364514 ps
CPU time 12.95 seconds
Started Jul 14 06:21:02 PM PDT 24
Finished Jul 14 06:21:16 PM PDT 24
Peak memory 217644 kb
Host smart-30feb64e-1df9-4caa-9fac-ce483452b497
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936684305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1936684305
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.221986843
Short name T504
Test name
Test status
Simulation time 3699110085 ps
CPU time 6.16 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:07 PM PDT 24
Peak memory 217784 kb
Host smart-c99bda47-edae-4e0c-9d67-eb8edcd185be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221986843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.221986843
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1461896941
Short name T311
Test name
Test status
Simulation time 9719743534 ps
CPU time 36.68 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:37 PM PDT 24
Peak memory 251040 kb
Host smart-e2819168-633c-4d2b-84aa-192ce98e7d61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461896941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1461896941
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1436935225
Short name T410
Test name
Test status
Simulation time 491258461 ps
CPU time 11.6 seconds
Started Jul 14 06:21:01 PM PDT 24
Finished Jul 14 06:21:14 PM PDT 24
Peak memory 247604 kb
Host smart-a4435634-0ec8-4f56-b19e-39409d362b0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436935225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1436935225
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2320234250
Short name T797
Test name
Test status
Simulation time 71910916 ps
CPU time 2.51 seconds
Started Jul 14 06:21:03 PM PDT 24
Finished Jul 14 06:21:06 PM PDT 24
Peak memory 218052 kb
Host smart-c4e6b03a-97c2-45e0-847d-f890e4fcf590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320234250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2320234250
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1044040821
Short name T78
Test name
Test status
Simulation time 277551602 ps
CPU time 15.81 seconds
Started Jul 14 06:21:02 PM PDT 24
Finished Jul 14 06:21:19 PM PDT 24
Peak memory 214836 kb
Host smart-191da279-b6f3-4c4d-9838-57fe023647a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044040821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1044040821
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1173693259
Short name T695
Test name
Test status
Simulation time 319809928 ps
CPU time 10.08 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:11 PM PDT 24
Peak memory 226028 kb
Host smart-0eebf514-1fa4-492f-9b52-30064fe11b85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173693259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1173693259
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.688391051
Short name T736
Test name
Test status
Simulation time 922235075 ps
CPU time 8.22 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:09 PM PDT 24
Peak memory 226044 kb
Host smart-f9145d0d-aebc-4a2e-bf0c-aafd6d5c537d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688391051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.688391051
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1734091639
Short name T686
Test name
Test status
Simulation time 556949117 ps
CPU time 13.68 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:14 PM PDT 24
Peak memory 218216 kb
Host smart-ca5f9753-c39e-4d06-a15a-f314e3aa511e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734091639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
734091639
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3117738003
Short name T786
Test name
Test status
Simulation time 220208692 ps
CPU time 9.32 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:10 PM PDT 24
Peak memory 224816 kb
Host smart-3f415eae-eeee-4211-8a14-265ad1a0a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117738003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3117738003
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2385207772
Short name T653
Test name
Test status
Simulation time 404460760 ps
CPU time 3.26 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:04 PM PDT 24
Peak memory 217732 kb
Host smart-bc5714fb-560e-4076-92dc-410880bb2aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385207772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2385207772
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1669549885
Short name T668
Test name
Test status
Simulation time 878154289 ps
CPU time 21.41 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:21 PM PDT 24
Peak memory 250976 kb
Host smart-97bd39be-978f-4793-ba0a-5a10bf509fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669549885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1669549885
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2066818644
Short name T844
Test name
Test status
Simulation time 51227509 ps
CPU time 8.07 seconds
Started Jul 14 06:21:01 PM PDT 24
Finished Jul 14 06:21:10 PM PDT 24
Peak memory 250968 kb
Host smart-842182f8-19e4-4e0e-9e89-07af22f55feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066818644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2066818644
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2295117596
Short name T285
Test name
Test status
Simulation time 2744573634 ps
CPU time 48.77 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:49 PM PDT 24
Peak memory 251004 kb
Host smart-fd2ceb43-79ee-4f8c-8608-9f621f9874d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295117596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2295117596
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3787615361
Short name T536
Test name
Test status
Simulation time 11188103 ps
CPU time 1 seconds
Started Jul 14 06:20:58 PM PDT 24
Finished Jul 14 06:20:59 PM PDT 24
Peak memory 211844 kb
Host smart-76b0e746-0c2a-4d5f-8fd8-2eee082aee2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787615361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3787615361
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1947873497
Short name T717
Test name
Test status
Simulation time 57576923 ps
CPU time 0.96 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:08 PM PDT 24
Peak memory 208944 kb
Host smart-2e4dd1d3-3c9b-40e9-9d61-5f372b8c4834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947873497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1947873497
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2248110673
Short name T517
Test name
Test status
Simulation time 12315618 ps
CPU time 0.83 seconds
Started Jul 14 06:21:05 PM PDT 24
Finished Jul 14 06:21:06 PM PDT 24
Peak memory 208776 kb
Host smart-02473843-1fd3-45d4-9d3f-7e95ff4a9cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248110673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2248110673
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3913975556
Short name T278
Test name
Test status
Simulation time 191635551 ps
CPU time 9.88 seconds
Started Jul 14 06:21:01 PM PDT 24
Finished Jul 14 06:21:12 PM PDT 24
Peak memory 218160 kb
Host smart-e00444f3-8fb5-4d28-ac34-ce7597979fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913975556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3913975556
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1081119689
Short name T7
Test name
Test status
Simulation time 775924036 ps
CPU time 10.47 seconds
Started Jul 14 06:21:09 PM PDT 24
Finished Jul 14 06:21:20 PM PDT 24
Peak memory 217404 kb
Host smart-2e92efa0-df1e-448b-8624-508d94f145e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081119689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1081119689
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2285556257
Short name T14
Test name
Test status
Simulation time 3954809239 ps
CPU time 54.18 seconds
Started Jul 14 06:21:04 PM PDT 24
Finished Jul 14 06:21:59 PM PDT 24
Peak memory 219952 kb
Host smart-117fdc0e-5204-4d72-ada9-8273cbd20af7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285556257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2285556257
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3571265980
Short name T515
Test name
Test status
Simulation time 222277451 ps
CPU time 4.69 seconds
Started Jul 14 06:21:05 PM PDT 24
Finished Jul 14 06:21:11 PM PDT 24
Peak memory 217748 kb
Host smart-d45b609b-08db-4ee9-9ee9-956edcda4e8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571265980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
571265980
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3741216188
Short name T490
Test name
Test status
Simulation time 621629498 ps
CPU time 5.42 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:13 PM PDT 24
Peak memory 218256 kb
Host smart-727e60d4-b154-45a9-8b52-3d341d8aeb42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741216188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3741216188
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2584990808
Short name T300
Test name
Test status
Simulation time 5569375465 ps
CPU time 26.83 seconds
Started Jul 14 06:21:07 PM PDT 24
Finished Jul 14 06:21:35 PM PDT 24
Peak memory 217680 kb
Host smart-1e16eb2b-9c05-42af-b07f-67c243a8f6d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584990808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2584990808
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2700887872
Short name T805
Test name
Test status
Simulation time 702467968 ps
CPU time 5.43 seconds
Started Jul 14 06:21:05 PM PDT 24
Finished Jul 14 06:21:11 PM PDT 24
Peak memory 217680 kb
Host smart-ea4ba986-ed97-444b-8d4e-9e12e2d06cff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700887872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2700887872
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1004411182
Short name T1
Test name
Test status
Simulation time 1937413089 ps
CPU time 44.51 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:59 PM PDT 24
Peak memory 267440 kb
Host smart-9fce8c42-6c32-4f50-a844-42b1153ef580
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004411182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1004411182
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2950790388
Short name T538
Test name
Test status
Simulation time 3895180464 ps
CPU time 14.78 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:22 PM PDT 24
Peak memory 226104 kb
Host smart-a6415a27-8772-4650-b70c-820f53e9da55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950790388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2950790388
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.4191095701
Short name T666
Test name
Test status
Simulation time 246799656 ps
CPU time 3.8 seconds
Started Jul 14 06:21:00 PM PDT 24
Finished Jul 14 06:21:06 PM PDT 24
Peak memory 218160 kb
Host smart-3f47c603-2ddc-4ab9-9555-26b96daa4530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191095701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.4191095701
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3305986099
Short name T552
Test name
Test status
Simulation time 1440516701 ps
CPU time 20 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:28 PM PDT 24
Peak memory 217688 kb
Host smart-a2e54bf5-551d-4c0c-9759-3427115ab03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305986099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3305986099
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3384162983
Short name T519
Test name
Test status
Simulation time 1154970513 ps
CPU time 11.98 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:26 PM PDT 24
Peak memory 226000 kb
Host smart-d639f66d-c0ed-4741-98b9-0df56e21fcf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384162983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3384162983
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2896459132
Short name T255
Test name
Test status
Simulation time 677474957 ps
CPU time 15.91 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:24 PM PDT 24
Peak memory 226040 kb
Host smart-db215834-21ee-46b8-a3fd-c7b4e143b1c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896459132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2896459132
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1515335660
Short name T369
Test name
Test status
Simulation time 517393336 ps
CPU time 6.66 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:21 PM PDT 24
Peak memory 218244 kb
Host smart-eb21e040-aeb1-4367-a04b-152287d854bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515335660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
515335660
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2518398683
Short name T46
Test name
Test status
Simulation time 2439038465 ps
CPU time 9.2 seconds
Started Jul 14 06:21:00 PM PDT 24
Finished Jul 14 06:21:11 PM PDT 24
Peak memory 226152 kb
Host smart-ce6b9715-3a33-4aae-9537-9473d1901358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518398683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2518398683
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.4035663415
Short name T756
Test name
Test status
Simulation time 627169362 ps
CPU time 2.55 seconds
Started Jul 14 06:21:01 PM PDT 24
Finished Jul 14 06:21:05 PM PDT 24
Peak memory 214672 kb
Host smart-d64c0cfb-05ec-4e0a-b8ce-af87bc01bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035663415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.4035663415
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1616435910
Short name T123
Test name
Test status
Simulation time 191146390 ps
CPU time 24.27 seconds
Started Jul 14 06:20:58 PM PDT 24
Finished Jul 14 06:21:23 PM PDT 24
Peak memory 250912 kb
Host smart-a7d3f189-0780-4b4b-a6e6-79ab574130e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616435910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1616435910
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1445039685
Short name T855
Test name
Test status
Simulation time 136994472 ps
CPU time 6.81 seconds
Started Jul 14 06:20:59 PM PDT 24
Finished Jul 14 06:21:07 PM PDT 24
Peak memory 242780 kb
Host smart-4f697276-8d28-4f4a-8f2c-a37e0c669673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445039685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1445039685
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.158629493
Short name T349
Test name
Test status
Simulation time 70718880849 ps
CPU time 455.51 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:28:43 PM PDT 24
Peak memory 283760 kb
Host smart-9188dbb2-c9b9-43c1-818b-7426e26e2fa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158629493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.158629493
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4028902464
Short name T435
Test name
Test status
Simulation time 10941159 ps
CPU time 1 seconds
Started Jul 14 06:21:02 PM PDT 24
Finished Jul 14 06:21:04 PM PDT 24
Peak memory 211848 kb
Host smart-de38c981-16a2-4bda-9e15-2c5017f10ea1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028902464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.4028902464
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3935966217
Short name T193
Test name
Test status
Simulation time 29198385 ps
CPU time 0.87 seconds
Started Jul 14 06:21:15 PM PDT 24
Finished Jul 14 06:21:16 PM PDT 24
Peak memory 208932 kb
Host smart-434a730a-1bd5-412b-8612-7f3b06be5f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935966217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3935966217
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.810990736
Short name T226
Test name
Test status
Simulation time 35309445 ps
CPU time 0.83 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:08 PM PDT 24
Peak memory 208928 kb
Host smart-8fe813d0-c4fd-45cf-8947-504a54d96ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810990736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.810990736
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3972506497
Short name T355
Test name
Test status
Simulation time 1556151300 ps
CPU time 22.89 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:31 PM PDT 24
Peak memory 218412 kb
Host smart-a4a6bb1d-8044-4290-8b74-3ba9ee90d348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972506497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3972506497
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.327446298
Short name T371
Test name
Test status
Simulation time 284301847 ps
CPU time 3.99 seconds
Started Jul 14 06:21:17 PM PDT 24
Finished Jul 14 06:21:21 PM PDT 24
Peak memory 217060 kb
Host smart-4ef777ab-f781-4ea1-837b-54a7baca8332
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327446298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.327446298
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.383477051
Short name T732
Test name
Test status
Simulation time 2725412694 ps
CPU time 40.14 seconds
Started Jul 14 06:21:15 PM PDT 24
Finished Jul 14 06:21:55 PM PDT 24
Peak memory 218828 kb
Host smart-096350a4-f128-4e31-a320-669ac928dc8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383477051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.383477051
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2936215537
Short name T507
Test name
Test status
Simulation time 1083450416 ps
CPU time 24.49 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:39 PM PDT 24
Peak memory 217776 kb
Host smart-2efaf4ab-7556-4229-ba8d-b219ce661266
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936215537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
936215537
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.85458354
Short name T771
Test name
Test status
Simulation time 2604639135 ps
CPU time 6.78 seconds
Started Jul 14 06:21:07 PM PDT 24
Finished Jul 14 06:21:15 PM PDT 24
Peak memory 218244 kb
Host smart-082a5526-8e98-4c3b-928e-0cb9ae88efb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85458354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_p
rog_failure.85458354
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4204651880
Short name T817
Test name
Test status
Simulation time 2857185699 ps
CPU time 27.27 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:41 PM PDT 24
Peak memory 217704 kb
Host smart-64bcc5ca-8655-44e6-94df-3fff8a22859b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204651880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4204651880
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.182197136
Short name T350
Test name
Test status
Simulation time 144588308 ps
CPU time 2.96 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:11 PM PDT 24
Peak memory 217608 kb
Host smart-9b40f6a2-184f-47af-84a6-8e70bc57d837
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182197136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.182197136
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.391881004
Short name T314
Test name
Test status
Simulation time 12717226874 ps
CPU time 77.83 seconds
Started Jul 14 06:21:05 PM PDT 24
Finished Jul 14 06:22:24 PM PDT 24
Peak memory 283724 kb
Host smart-f4a1ccaf-bb48-411c-af9d-69bd0eaa0976
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391881004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.391881004
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1399230705
Short name T437
Test name
Test status
Simulation time 590452140 ps
CPU time 17.62 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:32 PM PDT 24
Peak memory 218260 kb
Host smart-14d4ef99-03c7-44c3-94ba-8df51a40958f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399230705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1399230705
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2027122591
Short name T260
Test name
Test status
Simulation time 325951357 ps
CPU time 3.19 seconds
Started Jul 14 06:21:05 PM PDT 24
Finished Jul 14 06:21:09 PM PDT 24
Peak memory 222316 kb
Host smart-87e4449c-92af-469c-852d-9bf2cb20864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027122591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2027122591
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2118382735
Short name T395
Test name
Test status
Simulation time 1332014091 ps
CPU time 12.13 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:27 PM PDT 24
Peak memory 217724 kb
Host smart-49f860eb-894a-4fbb-ac48-932b48262b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118382735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2118382735
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2291615449
Short name T503
Test name
Test status
Simulation time 2287683882 ps
CPU time 17.77 seconds
Started Jul 14 06:21:16 PM PDT 24
Finished Jul 14 06:21:34 PM PDT 24
Peak memory 225988 kb
Host smart-0bb3b4d5-ece2-417e-bd30-102f0503b7ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291615449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2291615449
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2369724883
Short name T656
Test name
Test status
Simulation time 562699238 ps
CPU time 7.83 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:21 PM PDT 24
Peak memory 218168 kb
Host smart-a969bbf9-a3d1-47c8-94a6-82cfba90e532
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369724883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
369724883
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3439283604
Short name T614
Test name
Test status
Simulation time 1850378174 ps
CPU time 10.34 seconds
Started Jul 14 06:21:05 PM PDT 24
Finished Jul 14 06:21:16 PM PDT 24
Peak memory 225828 kb
Host smart-87c655ce-2e5e-4e44-a251-94d6b732fcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439283604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3439283604
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3419055521
Short name T81
Test name
Test status
Simulation time 23887566 ps
CPU time 1.82 seconds
Started Jul 14 06:21:05 PM PDT 24
Finished Jul 14 06:21:07 PM PDT 24
Peak memory 214132 kb
Host smart-d8e7d809-464c-4f56-94d4-bc66b0b5e1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419055521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3419055521
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.456474571
Short name T179
Test name
Test status
Simulation time 136936794 ps
CPU time 18.92 seconds
Started Jul 14 06:21:07 PM PDT 24
Finished Jul 14 06:21:27 PM PDT 24
Peak memory 251236 kb
Host smart-15750340-fa45-45f5-b7cc-6653530d12f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456474571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.456474571
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.4045166297
Short name T473
Test name
Test status
Simulation time 458221719 ps
CPU time 8.47 seconds
Started Jul 14 06:21:06 PM PDT 24
Finished Jul 14 06:21:16 PM PDT 24
Peak memory 250984 kb
Host smart-39fddd9b-31c7-478f-87e6-be40e3e5355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045166297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4045166297
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2964983610
Short name T682
Test name
Test status
Simulation time 790385274 ps
CPU time 6.79 seconds
Started Jul 14 06:21:15 PM PDT 24
Finished Jul 14 06:21:23 PM PDT 24
Peak memory 217812 kb
Host smart-b9817f9f-fff7-4411-989a-25c2e4c07b77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964983610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2964983610
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4260321424
Short name T176
Test name
Test status
Simulation time 47347295680 ps
CPU time 281.58 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:25:56 PM PDT 24
Peak memory 281852 kb
Host smart-e908ef8f-caa8-4098-83e5-6d21c7ebe31c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4260321424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.4260321424
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1554008980
Short name T635
Test name
Test status
Simulation time 41707538 ps
CPU time 1 seconds
Started Jul 14 06:21:07 PM PDT 24
Finished Jul 14 06:21:09 PM PDT 24
Peak memory 211872 kb
Host smart-024b0ed8-64fc-4a95-ad30-f052d285583b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554008980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1554008980
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2100378537
Short name T737
Test name
Test status
Simulation time 134812112 ps
CPU time 1.14 seconds
Started Jul 14 06:21:20 PM PDT 24
Finished Jul 14 06:21:22 PM PDT 24
Peak memory 208860 kb
Host smart-e1cbc1ca-bec7-40e6-8f04-d162d03e861b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100378537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2100378537
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3756710212
Short name T705
Test name
Test status
Simulation time 862748859 ps
CPU time 13.37 seconds
Started Jul 14 06:21:20 PM PDT 24
Finished Jul 14 06:21:34 PM PDT 24
Peak memory 218124 kb
Host smart-0bbc40b3-d623-499a-9a99-13f6c1601a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756710212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3756710212
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2458814744
Short name T560
Test name
Test status
Simulation time 1661453205 ps
CPU time 5.58 seconds
Started Jul 14 06:21:20 PM PDT 24
Finished Jul 14 06:21:26 PM PDT 24
Peak memory 217164 kb
Host smart-d05704f8-ede5-4e2f-ad1c-df222a37bd09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458814744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2458814744
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.473726993
Short name T816
Test name
Test status
Simulation time 12160099281 ps
CPU time 77.13 seconds
Started Jul 14 06:21:25 PM PDT 24
Finished Jul 14 06:22:43 PM PDT 24
Peak memory 218540 kb
Host smart-4b5cb2f4-35b4-420c-b748-f5d70408b5fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473726993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.473726993
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1668452447
Short name T243
Test name
Test status
Simulation time 72696937 ps
CPU time 1.76 seconds
Started Jul 14 06:21:20 PM PDT 24
Finished Jul 14 06:21:23 PM PDT 24
Peak memory 217724 kb
Host smart-9972c6b2-6cee-498d-9f14-8482e60f91cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668452447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
668452447
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3944008051
Short name T231
Test name
Test status
Simulation time 291846957 ps
CPU time 9.35 seconds
Started Jul 14 06:21:22 PM PDT 24
Finished Jul 14 06:21:32 PM PDT 24
Peak memory 218124 kb
Host smart-8f48bd34-1db8-493c-bbbb-6e33b1ec7ff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944008051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3944008051
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.634100539
Short name T667
Test name
Test status
Simulation time 2504402945 ps
CPU time 35.27 seconds
Started Jul 14 06:21:21 PM PDT 24
Finished Jul 14 06:21:57 PM PDT 24
Peak memory 217752 kb
Host smart-7b5b8e78-715f-42a5-9b0e-607e7cc3244a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634100539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.634100539
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2618319628
Short name T783
Test name
Test status
Simulation time 2735059231 ps
CPU time 6.41 seconds
Started Jul 14 06:21:23 PM PDT 24
Finished Jul 14 06:21:30 PM PDT 24
Peak memory 217672 kb
Host smart-0c4559f8-db44-4847-93da-fa57b66fd1d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618319628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2618319628
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3958470825
Short name T563
Test name
Test status
Simulation time 1213021532 ps
CPU time 52.7 seconds
Started Jul 14 06:21:20 PM PDT 24
Finished Jul 14 06:22:13 PM PDT 24
Peak memory 252736 kb
Host smart-01a9007f-01c8-46e5-9ba2-e6414d25c0fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958470825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3958470825
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3778593817
Short name T843
Test name
Test status
Simulation time 737309495 ps
CPU time 11.59 seconds
Started Jul 14 06:21:23 PM PDT 24
Finished Jul 14 06:21:35 PM PDT 24
Peak memory 250948 kb
Host smart-fa8b8125-c541-4894-98a9-02aa4070dde5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778593817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3778593817
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.848349109
Short name T742
Test name
Test status
Simulation time 124938885 ps
CPU time 2.08 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:16 PM PDT 24
Peak memory 218172 kb
Host smart-de003869-d12b-4813-997e-8a9086023050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848349109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.848349109
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.402952250
Short name T748
Test name
Test status
Simulation time 1524461791 ps
CPU time 18.91 seconds
Started Jul 14 06:21:20 PM PDT 24
Finished Jul 14 06:21:40 PM PDT 24
Peak memory 217748 kb
Host smart-2f0deefa-9041-457d-b718-650242c91b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402952250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.402952250
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.746806862
Short name T433
Test name
Test status
Simulation time 959052923 ps
CPU time 10.42 seconds
Started Jul 14 06:21:20 PM PDT 24
Finished Jul 14 06:21:31 PM PDT 24
Peak memory 226044 kb
Host smart-431d870d-4880-4b2d-9be6-b47be4ef353f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746806862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.746806862
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1717730264
Short name T511
Test name
Test status
Simulation time 649240952 ps
CPU time 14.65 seconds
Started Jul 14 06:21:23 PM PDT 24
Finished Jul 14 06:21:38 PM PDT 24
Peak memory 225936 kb
Host smart-b0b27f1a-462e-4fdd-b430-c8a3a436b7f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717730264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1717730264
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2844946659
Short name T287
Test name
Test status
Simulation time 505930993 ps
CPU time 13.06 seconds
Started Jul 14 06:21:22 PM PDT 24
Finished Jul 14 06:21:36 PM PDT 24
Peak memory 218224 kb
Host smart-1dd5882d-43ac-46e0-9815-8c0aa160b1ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844946659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
844946659
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.882331385
Short name T48
Test name
Test status
Simulation time 455279622 ps
CPU time 9.52 seconds
Started Jul 14 06:21:21 PM PDT 24
Finished Jul 14 06:21:31 PM PDT 24
Peak memory 218276 kb
Host smart-73750738-e239-4c82-9092-6e5fbd6a60ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882331385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.882331385
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.474333076
Short name T822
Test name
Test status
Simulation time 88890950 ps
CPU time 2.31 seconds
Started Jul 14 06:21:13 PM PDT 24
Finished Jul 14 06:21:16 PM PDT 24
Peak memory 217900 kb
Host smart-9aee61cc-879a-4572-a064-10d4592de272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474333076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.474333076
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3368975128
Short name T266
Test name
Test status
Simulation time 1024767450 ps
CPU time 21.63 seconds
Started Jul 14 06:21:15 PM PDT 24
Finished Jul 14 06:21:37 PM PDT 24
Peak memory 250956 kb
Host smart-91400fb5-9b66-4b26-ae40-c4d15b7cd494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368975128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3368975128
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1661444054
Short name T332
Test name
Test status
Simulation time 63731001 ps
CPU time 6.84 seconds
Started Jul 14 06:21:14 PM PDT 24
Finished Jul 14 06:21:22 PM PDT 24
Peak memory 250432 kb
Host smart-de1adad8-e3a6-4e0f-b205-c144b2f17430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661444054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1661444054
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1395712114
Short name T122
Test name
Test status
Simulation time 23927975314 ps
CPU time 192.39 seconds
Started Jul 14 06:21:22 PM PDT 24
Finished Jul 14 06:24:35 PM PDT 24
Peak memory 269740 kb
Host smart-5e7e60f9-0d2a-480a-8d0e-489934b07cb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395712114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1395712114
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3299755645
Short name T168
Test name
Test status
Simulation time 33500832251 ps
CPU time 4462 seconds
Started Jul 14 06:21:21 PM PDT 24
Finished Jul 14 07:35:44 PM PDT 24
Peak memory 955716 kb
Host smart-6642b7c1-e6db-44b9-a63f-f35bc7d7e37b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3299755645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3299755645
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.464172769
Short name T228
Test name
Test status
Simulation time 17057300 ps
CPU time 0.9 seconds
Started Jul 14 06:21:16 PM PDT 24
Finished Jul 14 06:21:17 PM PDT 24
Peak memory 211892 kb
Host smart-aa264d82-71c8-410a-be4f-351a14519418
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464172769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.464172769
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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