Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113511441

1

T1

22623

T2

1418

T3

1083

auto[1]

1473224

1

T2

99

T4

98

T5

2871

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113528379

1

T1

22623

T2

1418

T3

1083

auto[1]

1456286

1

T2

99

T4

98

T5

3663

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7586402	1			T1	112		T2	262		T3	88
auto[IdleSt]	22121222	1			T1	22511		T2	863		T3	55
auto[ClkMuxSt]	36989	1			T2	2		T3	1		T4	2
auto[CntIncrSt]	36654	1			T2	2		T3	1		T4	2
auto[CntProgSt]	1675298	1			T2	4		T3	2		T4	23
auto[TransCheckSt]	28624	1			T3	1		T10	1		T6	79
auto[TokenHashSt]	50670386	1			T3	10		T10	10		T6	2171
auto[FlashRmaSt]	37312	1			T6	75		T11	12		T12	45
auto[TokenCheck0St]	13336	1			T6	25		T11	12		T12	20
auto[TokenCheck1St]	9993	1			T6	16		T11	8		T12	20
auto[TransProgSt]	433359	1			T6	4039		T11	12		T12	89
auto[PostTransSt]	13912028	1			T2	142		T3	925		T4	874
auto[ScrapSt]	147968	1			T23	3		T13	1126		T35	85
auto[EscalateSt]	7016141	1			T2	242		T4	721		T5	8183
auto[InvalidSt]	11256713	1			T5	4770		T22	1530		T13	130665

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2240	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11256713	1			T5	4770		T22	1530		T13	130665
EscalateSt	7016141	1			T2	242		T4	721		T5	8183
ScrapSt	147968	1			T23	3		T13	1126		T35	85
PostTransSt	13912028	1			T2	142		T3	925		T4	874
TransProgSt	433359	1			T6	4039		T11	12		T12	89
TokenCheck1St	9993	1			T6	16		T11	8		T12	20
TokenCheck0St	13336	1			T6	25		T11	12		T12	20
FlashRmaSt	37312	1			T6	75		T11	12		T12	45
TokenHashSt	50670386	1			T3	10		T10	10		T6	2171
TransCheckSt	28624	1			T3	1		T10	1		T6	79
CntProgSt	1675298	1			T2	4		T3	2		T4	23
CntIncrSt	36654	1			T2	2		T3	1		T4	2
ClkMuxSt	36989	1			T2	2		T3	1		T4	2
IdleSt	22121222	1			T1	22511		T2	863		T3	55
ResetSt	7586402	1			T1	112		T2	262		T3	88
arcs[ResetSt=>IdleSt]	57487	1			T1	1		T2	3		T3	1
arcs[IdleSt=>ScrapSt]	300	1			T23	1		T13	3		T35	2
arcs[IdleSt=>ClkMuxSt]	36724	1			T2	2		T3	1		T4	2
arcs[ClkMuxSt=>CntIncrSt]	36654	1			T2	2		T3	1		T4	2
arcs[CntIncrSt=>PostTransSt]	2046	1			T6	7		T11	10		T13	47
arcs[CntIncrSt=>CntProgSt]	34555	1			T2	2		T3	1		T4	2
arcs[CntProgSt=>PostTransSt]	4731	1			T2	2		T4	2		T6	11
arcs[CntProgSt=>TransCheckSt]	28624	1			T3	1		T10	1		T6	79
arcs[TransCheckSt=>PostTransSt]	3920	1			T6	13		T11	8		T13	53
arcs[TransCheckSt=>TokenHashSt]	24648	1			T3	1		T10	1		T6	66
arcs[TokenHashSt=>PostTransSt]	10667	1			T3	1		T10	1		T6	41
arcs[TokenHashSt=>FlashRmaSt]	13428	1			T6	25		T11	12		T12	21
arcs[FlashRmaSt=>TokenCheck0St]	13336	1			T6	25		T11	12		T12	20
arcs[TokenCheck0St=>PostTransSt]	3323	1			T6	9		T11	4		T22	7
arcs[TokenCheck0St=>TokenCheck1St]	9993	1			T6	16		T11	8		T12	20
arcs[TokenCheck1St=>PostTransSt]	638	1			T6	1		T11	2		T13	2
arcs[TransProgSt=>PostTransSt]	8377	1			T6	15		T11	6		T12	1
arcs[IdleSt=>EscalateSt]	209	1			T23	5		T45	4		T42	8
arcs[ClkMuxSt=>EscalateSt]	70	1			T42	1		T43	1		T44	1
arcs[CntIncrSt=>EscalateSt]	53	1			T23	2		T45	1		T42	2
arcs[CntProgSt=>EscalateSt]	1200	1			T12	27		T23	28		T45	6
arcs[TransCheckSt=>EscalateSt]	56	1			T45	4		T47	5		T53	2
arcs[TokenHashSt=>EscalateSt]	553	1			T12	7		T23	5		T13	3
arcs[FlashRmaSt=>EscalateSt]	92	1			T12	1		T23	1		T42	1
arcs[TokenCheck0St=>EscalateSt]	20	1			T44	1		T51	1		T52	1
arcs[TokenCheck1St=>EscalateSt]	152	1			T12	3		T23	1		T45	4
arcs[TransProgSt=>EscalateSt]	826	1			T12	16		T23	23		T45	5
arcs[PostTransSt=>EscalateSt]	4896	1			T2	2		T4	2		T6	11
arcs[InvalidSt=>EscalateSt]	15700	1			T5	66		T22	8		T13	78

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7586236	1			T1	112		T2	262		T3	88
auto[0]	auto[IdleSt]	22121087	1			T1	22511		T2	863		T3	55
auto[0]	auto[ClkMuxSt]	36941	1			T2	2		T3	1		T4	2
auto[0]	auto[CntIncrSt]	36613	1			T2	2		T3	1		T4	2
auto[0]	auto[CntProgSt]	1674490	1			T2	4		T3	2		T4	23
auto[0]	auto[TransCheckSt]	28590	1			T3	1		T10	1		T6	79
auto[0]	auto[TokenHashSt]	50670028	1			T3	10		T10	10		T6	2171
auto[0]	auto[FlashRmaSt]	37247	1			T6	75		T11	12		T12	44
auto[0]	auto[TokenCheck0St]	13321	1			T6	25		T11	12		T12	20
auto[0]	auto[TokenCheck1St]	9897	1			T6	16		T11	8		T12	19
auto[0]	auto[TransProgSt]	432807	1			T6	4039		T11	12		T12	78
auto[0]	auto[PostTransSt]	13909543	1			T2	141		T3	925		T4	873
auto[0]	auto[ScrapSt]	147939	1			T23	2		T13	1126		T35	85
auto[0]	auto[EscalateSt]	5555640	1			T2	144		T4	624		T5	5341
auto[0]	auto[InvalidSt]	11248822	1			T5	4741		T22	1526		T13	130625
auto[1]	auto[ResetSt]	166	1			T12	2		T23	1		T45	2
auto[1]	auto[IdleSt]	135	1			T23	5		T45	2		T42	4
auto[1]	auto[ClkMuxSt]	48	1			T42	1		T44	1		T46	3
auto[1]	auto[CntIncrSt]	41	1			T23	1		T42	2		T43	2
auto[1]	auto[CntProgSt]	808	1			T12	19		T23	18		T45	3
auto[1]	auto[TransCheckSt]	34	1			T45	3		T47	3		T53	2
auto[1]	auto[TokenHashSt]	358	1			T12	4		T23	3		T13	3
auto[1]	auto[FlashRmaSt]	65	1			T12	1		T42	1		T46	2
auto[1]	auto[TokenCheck0St]	15	1			T44	1		T51	1		T52	1
auto[1]	auto[TokenCheck1St]	96	1			T12	1		T23	1		T45	3
auto[1]	auto[TransProgSt]	552	1			T12	11		T23	19		T45	4
auto[1]	auto[PostTransSt]	2485	1			T2	1		T4	1		T6	5
auto[1]	auto[ScrapSt]	29	1			T23	1		T47	2		T166	1
auto[1]	auto[EscalateSt]	1460501	1			T2	98		T4	97		T5	2842
auto[1]	auto[InvalidSt]	7891	1			T5	29		T22	4		T13	40

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7586239	1			T1	112		T2	262		T3	88
auto[0]	auto[IdleSt]	22121072	1			T1	22511		T2	863		T3	55
auto[0]	auto[ClkMuxSt]	36938	1			T2	2		T3	1		T4	2
auto[0]	auto[CntIncrSt]	36619	1			T2	2		T3	1		T4	2
auto[0]	auto[CntProgSt]	1674505	1			T2	4		T3	2		T4	23
auto[0]	auto[TransCheckSt]	28586	1			T3	1		T10	1		T6	79
auto[0]	auto[TokenHashSt]	50670032	1			T3	10		T10	10		T6	2171
auto[0]	auto[FlashRmaSt]	37257	1			T6	75		T11	12		T12	44
auto[0]	auto[TokenCheck0St]	13324	1			T6	25		T11	12		T12	20
auto[0]	auto[TokenCheck1St]	9894	1			T6	16		T11	8		T12	17
auto[0]	auto[TransProgSt]	432826	1			T6	4039		T11	12		T12	77
auto[0]	auto[PostTransSt]	13909573	1			T2	141		T3	925		T4	873
auto[0]	auto[ScrapSt]	147935	1			T23	2		T13	1126		T35	85
auto[0]	auto[EscalateSt]	5572435	1			T2	144		T4	624		T5	4557
auto[0]	auto[InvalidSt]	11248904	1			T5	4733		T22	1526		T13	130627
auto[1]	auto[ResetSt]	163	1			T12	2		T23	2		T45	2
auto[1]	auto[IdleSt]	150	1			T23	3		T45	3		T42	5
auto[1]	auto[ClkMuxSt]	51	1			T42	1		T43	1		T44	1
auto[1]	auto[CntIncrSt]	35	1			T23	2		T45	1		T42	1
auto[1]	auto[CntProgSt]	793	1			T12	16		T23	17		T45	5
auto[1]	auto[TransCheckSt]	38	1			T45	2		T47	3		T53	2
auto[1]	auto[TokenHashSt]	354	1			T12	4		T23	4		T45	9
auto[1]	auto[FlashRmaSt]	55	1			T12	1		T23	1		T43	1
auto[1]	auto[TokenCheck0St]	12	1			T51	1		T208	1		T209	1
auto[1]	auto[TokenCheck1St]	99	1			T12	3		T45	2		T42	2
auto[1]	auto[TransProgSt]	533	1			T12	12		T23	12		T45	3
auto[1]	auto[PostTransSt]	2455	1			T2	1		T4	1		T6	6
auto[1]	auto[ScrapSt]	33	1			T23	1		T46	1		T47	1
auto[1]	auto[EscalateSt]	1443706	1			T2	98		T4	97		T5	3626
auto[1]	auto[InvalidSt]	7809	1			T5	37		T22	4		T13	38