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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.78 97.92 95.56 93.40 97.62 98.52 98.51 95.94


Total test records in report: 996
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T805 /workspace/coverage/default/34.lc_ctrl_errors.90934438 Jul 18 06:57:32 PM PDT 24 Jul 18 06:57:52 PM PDT 24 289861236 ps
T806 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.564092328 Jul 18 06:57:45 PM PDT 24 Jul 18 06:57:58 PM PDT 24 655606734 ps
T807 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3125722226 Jul 18 06:57:15 PM PDT 24 Jul 18 06:57:38 PM PDT 24 423061426 ps
T808 /workspace/coverage/default/23.lc_ctrl_state_failure.2473488127 Jul 18 06:56:52 PM PDT 24 Jul 18 06:57:28 PM PDT 24 712586473 ps
T809 /workspace/coverage/default/27.lc_ctrl_smoke.2300697352 Jul 18 06:57:00 PM PDT 24 Jul 18 06:57:07 PM PDT 24 28265002 ps
T810 /workspace/coverage/default/19.lc_ctrl_stress_all.1886581529 Jul 18 06:56:42 PM PDT 24 Jul 18 06:59:33 PM PDT 24 7468117420 ps
T811 /workspace/coverage/default/4.lc_ctrl_errors.2976809356 Jul 18 06:55:30 PM PDT 24 Jul 18 06:55:45 PM PDT 24 366344222 ps
T812 /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2004742208 Jul 18 06:56:05 PM PDT 24 Jul 18 07:11:48 PM PDT 24 407627337138 ps
T813 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.691606379 Jul 18 06:55:59 PM PDT 24 Jul 18 06:56:09 PM PDT 24 28000281 ps
T814 /workspace/coverage/default/16.lc_ctrl_stress_all.4152927561 Jul 18 06:56:21 PM PDT 24 Jul 18 07:04:40 PM PDT 24 45601597062 ps
T815 /workspace/coverage/default/28.lc_ctrl_prog_failure.1409351699 Jul 18 06:57:10 PM PDT 24 Jul 18 06:57:18 PM PDT 24 81684224 ps
T816 /workspace/coverage/default/13.lc_ctrl_errors.1824627637 Jul 18 06:56:03 PM PDT 24 Jul 18 06:56:25 PM PDT 24 822442261 ps
T817 /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3202090092 Jul 18 06:57:08 PM PDT 24 Jul 18 06:57:12 PM PDT 24 13002304 ps
T818 /workspace/coverage/default/27.lc_ctrl_sec_mubi.173105081 Jul 18 06:56:54 PM PDT 24 Jul 18 06:57:13 PM PDT 24 482044794 ps
T819 /workspace/coverage/default/22.lc_ctrl_smoke.2083898127 Jul 18 06:56:39 PM PDT 24 Jul 18 06:56:46 PM PDT 24 28757629 ps
T820 /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3595675882 Jul 18 06:56:36 PM PDT 24 Jul 18 06:56:45 PM PDT 24 320951930 ps
T82 /workspace/coverage/default/49.lc_ctrl_smoke.321257425 Jul 18 06:58:06 PM PDT 24 Jul 18 06:58:14 PM PDT 24 545170952 ps
T821 /workspace/coverage/default/40.lc_ctrl_stress_all.1197486088 Jul 18 06:57:45 PM PDT 24 Jul 18 07:07:45 PM PDT 24 76059939042 ps
T822 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.118070617 Jul 18 06:56:37 PM PDT 24 Jul 18 06:56:42 PM PDT 24 359696772 ps
T823 /workspace/coverage/default/15.lc_ctrl_security_escalation.2308394092 Jul 18 06:56:21 PM PDT 24 Jul 18 06:56:37 PM PDT 24 997373226 ps
T92 /workspace/coverage/default/0.lc_ctrl_sec_cm.1984075598 Jul 18 06:55:14 PM PDT 24 Jul 18 06:55:50 PM PDT 24 210803659 ps
T824 /workspace/coverage/default/35.lc_ctrl_stress_all.1890914929 Jul 18 06:57:32 PM PDT 24 Jul 18 06:58:49 PM PDT 24 3118863079 ps
T825 /workspace/coverage/default/35.lc_ctrl_security_escalation.3710704000 Jul 18 06:57:27 PM PDT 24 Jul 18 06:57:40 PM PDT 24 1115884516 ps
T826 /workspace/coverage/default/18.lc_ctrl_state_failure.1612463420 Jul 18 06:56:38 PM PDT 24 Jul 18 06:57:16 PM PDT 24 978589447 ps
T827 /workspace/coverage/default/43.lc_ctrl_state_post_trans.3876969209 Jul 18 06:57:46 PM PDT 24 Jul 18 06:57:59 PM PDT 24 176021232 ps
T828 /workspace/coverage/default/34.lc_ctrl_sec_mubi.1435264138 Jul 18 06:57:30 PM PDT 24 Jul 18 06:57:49 PM PDT 24 1925352096 ps
T829 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.626893637 Jul 18 06:55:55 PM PDT 24 Jul 18 06:56:03 PM PDT 24 34976737 ps
T830 /workspace/coverage/default/28.lc_ctrl_stress_all.2345467689 Jul 18 06:57:06 PM PDT 24 Jul 18 06:59:41 PM PDT 24 22827918559 ps
T831 /workspace/coverage/default/5.lc_ctrl_state_post_trans.514504671 Jul 18 06:55:34 PM PDT 24 Jul 18 06:55:47 PM PDT 24 828622458 ps
T832 /workspace/coverage/default/37.lc_ctrl_alert_test.676804519 Jul 18 06:57:33 PM PDT 24 Jul 18 06:57:39 PM PDT 24 31601463 ps
T833 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2985224381 Jul 18 06:56:57 PM PDT 24 Jul 18 06:57:14 PM PDT 24 519223321 ps
T834 /workspace/coverage/default/48.lc_ctrl_smoke.376661843 Jul 18 06:58:00 PM PDT 24 Jul 18 06:58:09 PM PDT 24 377101608 ps
T835 /workspace/coverage/default/40.lc_ctrl_sec_mubi.378319800 Jul 18 06:57:43 PM PDT 24 Jul 18 06:58:04 PM PDT 24 668373900 ps
T836 /workspace/coverage/default/14.lc_ctrl_prog_failure.2011877935 Jul 18 06:56:12 PM PDT 24 Jul 18 06:56:22 PM PDT 24 360407465 ps
T837 /workspace/coverage/default/6.lc_ctrl_jtag_priority.3984463142 Jul 18 06:55:46 PM PDT 24 Jul 18 06:55:53 PM PDT 24 83022394 ps
T838 /workspace/coverage/default/45.lc_ctrl_alert_test.397090851 Jul 18 06:58:03 PM PDT 24 Jul 18 06:58:09 PM PDT 24 62897516 ps
T839 /workspace/coverage/default/31.lc_ctrl_sec_mubi.955326703 Jul 18 06:57:13 PM PDT 24 Jul 18 06:57:31 PM PDT 24 1098624713 ps
T840 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.769605367 Jul 18 06:56:57 PM PDT 24 Jul 18 06:57:15 PM PDT 24 1996479073 ps
T841 /workspace/coverage/default/24.lc_ctrl_errors.726037004 Jul 18 06:57:00 PM PDT 24 Jul 18 06:57:20 PM PDT 24 489616685 ps
T842 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3669477552 Jul 18 06:57:15 PM PDT 24 Jul 18 06:57:33 PM PDT 24 1389101078 ps
T843 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2454831979 Jul 18 06:55:16 PM PDT 24 Jul 18 06:55:32 PM PDT 24 751136401 ps
T844 /workspace/coverage/default/4.lc_ctrl_security_escalation.2026425597 Jul 18 06:55:29 PM PDT 24 Jul 18 06:55:40 PM PDT 24 1132092356 ps
T845 /workspace/coverage/default/2.lc_ctrl_alert_test.2066106888 Jul 18 06:55:30 PM PDT 24 Jul 18 06:55:35 PM PDT 24 79547021 ps
T846 /workspace/coverage/default/8.lc_ctrl_alert_test.3352595154 Jul 18 06:55:59 PM PDT 24 Jul 18 06:56:09 PM PDT 24 34544679 ps
T847 /workspace/coverage/default/13.lc_ctrl_alert_test.3691638382 Jul 18 06:56:08 PM PDT 24 Jul 18 06:56:18 PM PDT 24 23047162 ps
T848 /workspace/coverage/default/3.lc_ctrl_security_escalation.1738953303 Jul 18 06:55:28 PM PDT 24 Jul 18 06:55:38 PM PDT 24 340366622 ps
T849 /workspace/coverage/default/42.lc_ctrl_stress_all.1986255289 Jul 18 06:57:46 PM PDT 24 Jul 18 06:58:55 PM PDT 24 1702264953 ps
T850 /workspace/coverage/default/39.lc_ctrl_sec_mubi.1075181624 Jul 18 06:57:41 PM PDT 24 Jul 18 06:57:58 PM PDT 24 3747457051 ps
T851 /workspace/coverage/default/46.lc_ctrl_state_failure.2061223759 Jul 18 06:58:02 PM PDT 24 Jul 18 06:58:27 PM PDT 24 538909556 ps
T852 /workspace/coverage/default/33.lc_ctrl_state_post_trans.1642978273 Jul 18 06:57:14 PM PDT 24 Jul 18 06:57:27 PM PDT 24 81737230 ps
T853 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.4169545549 Jul 18 06:55:47 PM PDT 24 Jul 18 06:56:09 PM PDT 24 801026594 ps
T854 /workspace/coverage/default/17.lc_ctrl_errors.1128887731 Jul 18 06:56:21 PM PDT 24 Jul 18 06:56:46 PM PDT 24 1301525445 ps
T855 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1380201411 Jul 18 06:57:46 PM PDT 24 Jul 18 06:58:00 PM PDT 24 228105704 ps
T856 /workspace/coverage/default/2.lc_ctrl_state_failure.2230461223 Jul 18 06:55:14 PM PDT 24 Jul 18 06:55:44 PM PDT 24 333410540 ps
T857 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4253672645 Jul 18 06:56:42 PM PDT 24 Jul 18 06:56:56 PM PDT 24 499566267 ps
T858 /workspace/coverage/default/6.lc_ctrl_jtag_errors.3945570307 Jul 18 06:55:48 PM PDT 24 Jul 18 06:56:45 PM PDT 24 3356525032 ps
T859 /workspace/coverage/default/0.lc_ctrl_smoke.159348559 Jul 18 06:54:57 PM PDT 24 Jul 18 06:55:08 PM PDT 24 34347372 ps
T860 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.4082534498 Jul 18 06:56:06 PM PDT 24 Jul 18 06:56:24 PM PDT 24 6718604167 ps
T861 /workspace/coverage/default/5.lc_ctrl_jtag_errors.1464519009 Jul 18 06:55:34 PM PDT 24 Jul 18 06:56:02 PM PDT 24 6253887915 ps
T862 /workspace/coverage/default/22.lc_ctrl_security_escalation.2210241563 Jul 18 06:56:40 PM PDT 24 Jul 18 06:57:00 PM PDT 24 379622226 ps
T863 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1573464786 Jul 18 06:55:55 PM PDT 24 Jul 18 06:56:48 PM PDT 24 8555648483 ps
T111 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.857530425 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:36 PM PDT 24 15502559 ps
T112 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1875327472 Jul 18 06:46:43 PM PDT 24 Jul 18 06:46:48 PM PDT 24 36003122 ps
T106 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3288077222 Jul 18 06:46:51 PM PDT 24 Jul 18 06:46:56 PM PDT 24 113065906 ps
T145 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3053202931 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:32 PM PDT 24 27033697 ps
T136 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1239003980 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:53 PM PDT 24 75588657 ps
T107 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3926516803 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:34 PM PDT 24 109017497 ps
T864 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1851343557 Jul 18 06:46:55 PM PDT 24 Jul 18 06:46:58 PM PDT 24 40103051 ps
T137 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3499731922 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:28 PM PDT 24 166745391 ps
T108 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3866068446 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:37 PM PDT 24 155939463 ps
T196 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.707009300 Jul 18 06:46:51 PM PDT 24 Jul 18 06:46:55 PM PDT 24 22087698 ps
T110 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2594212749 Jul 18 06:46:51 PM PDT 24 Jul 18 06:46:56 PM PDT 24 77307531 ps
T197 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.8815019 Jul 18 06:46:21 PM PDT 24 Jul 18 06:46:26 PM PDT 24 32730138 ps
T146 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.108435801 Jul 18 06:46:44 PM PDT 24 Jul 18 06:46:48 PM PDT 24 70808481 ps
T109 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3402466913 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:37 PM PDT 24 315223330 ps
T184 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3902842750 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:36 PM PDT 24 26360319 ps
T130 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2733087312 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:53 PM PDT 24 64177184 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3188757969 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:47 PM PDT 24 4848405847 ps
T114 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2313358696 Jul 18 06:46:55 PM PDT 24 Jul 18 06:46:58 PM PDT 24 128497531 ps
T115 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2418537627 Jul 18 06:46:42 PM PDT 24 Jul 18 06:46:47 PM PDT 24 27368990 ps
T185 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4105007367 Jul 18 06:46:30 PM PDT 24 Jul 18 06:46:40 PM PDT 24 57247388 ps
T865 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3205204998 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:32 PM PDT 24 66421706 ps
T122 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3954507901 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:38 PM PDT 24 1205598641 ps
T120 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3790293622 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:40 PM PDT 24 184020598 ps
T121 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1606301710 Jul 18 06:46:48 PM PDT 24 Jul 18 06:46:54 PM PDT 24 175629052 ps
T866 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1523971435 Jul 18 06:46:56 PM PDT 24 Jul 18 06:47:02 PM PDT 24 112915947 ps
T198 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1637873420 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:27 PM PDT 24 43168323 ps
T867 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1524151730 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:37 PM PDT 24 21061406 ps
T868 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4198490129 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:39 PM PDT 24 95898747 ps
T869 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1767554455 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:33 PM PDT 24 192064851 ps
T134 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3837025818 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:37 PM PDT 24 187747703 ps
T870 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.795156794 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:30 PM PDT 24 476857089 ps
T199 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3795384391 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:52 PM PDT 24 415438470 ps
T135 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4091618345 Jul 18 06:46:33 PM PDT 24 Jul 18 06:46:43 PM PDT 24 392379199 ps
T871 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1678567504 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:41 PM PDT 24 129964451 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2869732112 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:42 PM PDT 24 1626071800 ps
T873 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1464126262 Jul 18 06:46:39 PM PDT 24 Jul 18 06:46:44 PM PDT 24 30183173 ps
T200 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3251744140 Jul 18 06:46:51 PM PDT 24 Jul 18 06:46:54 PM PDT 24 85619054 ps
T874 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1953488519 Jul 18 06:46:21 PM PDT 24 Jul 18 06:46:27 PM PDT 24 91173506 ps
T875 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4206221265 Jul 18 06:46:56 PM PDT 24 Jul 18 06:46:59 PM PDT 24 38890493 ps
T201 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3236773781 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:36 PM PDT 24 72916176 ps
T126 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3849849049 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:34 PM PDT 24 194932993 ps
T876 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3645038050 Jul 18 06:46:43 PM PDT 24 Jul 18 06:46:49 PM PDT 24 86449489 ps
T877 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1264696476 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:35 PM PDT 24 276970401 ps
T202 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4171216385 Jul 18 06:46:55 PM PDT 24 Jul 18 06:46:58 PM PDT 24 124059477 ps
T878 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1583540850 Jul 18 06:46:56 PM PDT 24 Jul 18 06:47:02 PM PDT 24 92337804 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.334872349 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:36 PM PDT 24 27300260 ps
T880 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4230420314 Jul 18 06:46:42 PM PDT 24 Jul 18 06:46:47 PM PDT 24 27417780 ps
T881 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3413691436 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:52 PM PDT 24 150837858 ps
T193 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.839716806 Jul 18 06:46:30 PM PDT 24 Jul 18 06:46:41 PM PDT 24 200673462 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2861549401 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:42 PM PDT 24 581862382 ps
T186 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3362234439 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:36 PM PDT 24 49492898 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2004191498 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:34 PM PDT 24 23293700 ps
T884 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3583941288 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:40 PM PDT 24 33875327 ps
T885 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1748761192 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:27 PM PDT 24 56629409 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.900520985 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:29 PM PDT 24 30476851 ps
T887 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1085591430 Jul 18 06:46:44 PM PDT 24 Jul 18 06:46:48 PM PDT 24 27644371 ps
T888 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2888433255 Jul 18 06:46:52 PM PDT 24 Jul 18 06:46:55 PM PDT 24 89841314 ps
T889 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2196237728 Jul 18 06:46:56 PM PDT 24 Jul 18 06:47:00 PM PDT 24 147330644 ps
T890 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3056640411 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:37 PM PDT 24 20784767 ps
T891 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2730705297 Jul 18 06:46:48 PM PDT 24 Jul 18 06:46:55 PM PDT 24 130379070 ps
T892 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3395238688 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:44 PM PDT 24 2698719163 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.405787202 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:39 PM PDT 24 424424874 ps
T894 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.756838805 Jul 18 06:46:25 PM PDT 24 Jul 18 06:46:34 PM PDT 24 26310388 ps
T124 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3287398961 Jul 18 06:46:56 PM PDT 24 Jul 18 06:47:00 PM PDT 24 81913580 ps
T895 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.626199465 Jul 18 06:46:56 PM PDT 24 Jul 18 06:46:59 PM PDT 24 13074025 ps
T123 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3564153093 Jul 18 06:46:48 PM PDT 24 Jul 18 06:46:55 PM PDT 24 112285862 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1138176268 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:53 PM PDT 24 332410817 ps
T897 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3564767076 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:52 PM PDT 24 113864250 ps
T898 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1000054422 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:33 PM PDT 24 36252348 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2435085490 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:28 PM PDT 24 54123973 ps
T116 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1687150119 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:36 PM PDT 24 773550684 ps
T900 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.447863614 Jul 18 06:46:51 PM PDT 24 Jul 18 06:46:55 PM PDT 24 192812874 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3776766913 Jul 18 06:46:45 PM PDT 24 Jul 18 06:46:50 PM PDT 24 45082576 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2282074005 Jul 18 06:46:39 PM PDT 24 Jul 18 06:46:55 PM PDT 24 2057435730 ps
T119 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2855459237 Jul 18 06:46:46 PM PDT 24 Jul 18 06:46:53 PM PDT 24 39817301 ps
T903 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1410709061 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:35 PM PDT 24 57453085 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2437388114 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:39 PM PDT 24 60292148 ps
T187 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3928260763 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:32 PM PDT 24 18020305 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.429429658 Jul 18 06:46:24 PM PDT 24 Jul 18 06:46:37 PM PDT 24 705220263 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.520927818 Jul 18 06:46:55 PM PDT 24 Jul 18 06:47:00 PM PDT 24 134461912 ps
T907 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.695981249 Jul 18 06:46:53 PM PDT 24 Jul 18 06:46:56 PM PDT 24 322950223 ps
T908 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1505791194 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:37 PM PDT 24 18795175 ps
T909 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.490678120 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:37 PM PDT 24 67676448 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2348429189 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:39 PM PDT 24 13152776 ps
T911 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3804596005 Jul 18 06:46:56 PM PDT 24 Jul 18 06:47:00 PM PDT 24 415144888 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1911028190 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:38 PM PDT 24 356230920 ps
T913 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1593426918 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:47 PM PDT 24 4274528610 ps
T914 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3740708235 Jul 18 06:46:52 PM PDT 24 Jul 18 06:46:56 PM PDT 24 199731580 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.475580675 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:40 PM PDT 24 163377737 ps
T916 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.949481675 Jul 18 06:46:46 PM PDT 24 Jul 18 06:46:51 PM PDT 24 235982784 ps
T917 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.951918598 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:33 PM PDT 24 985385242 ps
T918 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.581189104 Jul 18 06:46:57 PM PDT 24 Jul 18 06:47:07 PM PDT 24 695813621 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1758301886 Jul 18 06:46:21 PM PDT 24 Jul 18 06:46:26 PM PDT 24 308878126 ps
T920 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3140900376 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:38 PM PDT 24 246222663 ps
T921 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3572433129 Jul 18 06:46:55 PM PDT 24 Jul 18 06:46:58 PM PDT 24 111880891 ps
T188 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1865883754 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:52 PM PDT 24 15708540 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1815415553 Jul 18 06:46:40 PM PDT 24 Jul 18 06:46:46 PM PDT 24 264183329 ps
T923 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3673884734 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:32 PM PDT 24 24663554 ps
T924 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2060288130 Jul 18 06:46:38 PM PDT 24 Jul 18 06:46:44 PM PDT 24 24744045 ps
T925 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.823181039 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:38 PM PDT 24 87658704 ps
T926 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1733127835 Jul 18 06:46:40 PM PDT 24 Jul 18 06:46:44 PM PDT 24 103758277 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.314295230 Jul 18 06:46:28 PM PDT 24 Jul 18 06:46:38 PM PDT 24 30269184 ps
T117 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2179845738 Jul 18 06:46:56 PM PDT 24 Jul 18 06:47:01 PM PDT 24 438081479 ps
T928 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4189238651 Jul 18 06:46:46 PM PDT 24 Jul 18 06:46:51 PM PDT 24 342793672 ps
T929 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1159800754 Jul 18 06:46:48 PM PDT 24 Jul 18 06:46:52 PM PDT 24 19985725 ps
T118 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1133176745 Jul 18 06:46:53 PM PDT 24 Jul 18 06:46:58 PM PDT 24 163178487 ps
T930 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1066752674 Jul 18 06:46:48 PM PDT 24 Jul 18 06:46:52 PM PDT 24 13668832 ps
T931 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3050213867 Jul 18 06:46:56 PM PDT 24 Jul 18 06:46:59 PM PDT 24 166190109 ps
T932 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4238232028 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:37 PM PDT 24 276700161 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.601883293 Jul 18 06:46:38 PM PDT 24 Jul 18 06:46:43 PM PDT 24 81394650 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.205582350 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:31 PM PDT 24 62992965 ps
T129 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1292661377 Jul 18 06:46:39 PM PDT 24 Jul 18 06:46:44 PM PDT 24 181284860 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1944363864 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:37 PM PDT 24 44389629 ps
T132 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1261168072 Jul 18 06:46:38 PM PDT 24 Jul 18 06:46:44 PM PDT 24 239573623 ps
T189 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3679379981 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:51 PM PDT 24 137880170 ps
T936 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1504296390 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:39 PM PDT 24 215957223 ps
T190 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2731631159 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:35 PM PDT 24 22796686 ps
T937 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3777386821 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:32 PM PDT 24 17810973 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.690868051 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:37 PM PDT 24 158883433 ps
T939 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.498478154 Jul 18 06:46:30 PM PDT 24 Jul 18 06:46:46 PM PDT 24 1534643687 ps
T940 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2824611797 Jul 18 06:46:41 PM PDT 24 Jul 18 06:46:45 PM PDT 24 98232955 ps
T941 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3160492636 Jul 18 06:46:27 PM PDT 24 Jul 18 06:47:03 PM PDT 24 4417109232 ps
T942 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2619422671 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:51 PM PDT 24 19440609 ps
T943 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.25990828 Jul 18 06:46:21 PM PDT 24 Jul 18 06:46:27 PM PDT 24 255102165 ps
T944 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3799092590 Jul 18 06:46:46 PM PDT 24 Jul 18 06:46:53 PM PDT 24 410297899 ps
T945 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3593285066 Jul 18 06:46:46 PM PDT 24 Jul 18 06:46:52 PM PDT 24 27351783 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2246550949 Jul 18 06:46:41 PM PDT 24 Jul 18 06:46:49 PM PDT 24 371967367 ps
T947 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3324231620 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:40 PM PDT 24 371147901 ps
T948 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4170180360 Jul 18 06:46:21 PM PDT 24 Jul 18 06:46:26 PM PDT 24 45849873 ps
T949 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4174114863 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:37 PM PDT 24 16263202 ps
T950 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.647480741 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:37 PM PDT 24 28422953 ps
T951 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1301563377 Jul 18 06:46:25 PM PDT 24 Jul 18 06:46:35 PM PDT 24 335682294 ps
T131 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.827758536 Jul 18 06:46:51 PM PDT 24 Jul 18 06:46:56 PM PDT 24 68654374 ps
T952 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3568271516 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:37 PM PDT 24 215956165 ps
T953 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1351057964 Jul 18 06:46:55 PM PDT 24 Jul 18 06:47:01 PM PDT 24 218199973 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2233958706 Jul 18 06:46:39 PM PDT 24 Jul 18 06:46:43 PM PDT 24 27334302 ps
T955 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4268069169 Jul 18 06:46:40 PM PDT 24 Jul 18 06:46:44 PM PDT 24 57532704 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.710675646 Jul 18 06:46:43 PM PDT 24 Jul 18 06:46:48 PM PDT 24 143963663 ps
T957 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4026875377 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:39 PM PDT 24 56097591 ps
T958 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2931307551 Jul 18 06:46:56 PM PDT 24 Jul 18 06:47:00 PM PDT 24 50691684 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1588135872 Jul 18 06:46:42 PM PDT 24 Jul 18 06:46:46 PM PDT 24 14921479 ps
T960 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2403511578 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:36 PM PDT 24 113443871 ps
T961 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3938497405 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:39 PM PDT 24 60692014 ps
T962 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.942235520 Jul 18 06:46:25 PM PDT 24 Jul 18 06:46:36 PM PDT 24 228618168 ps
T191 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2639969676 Jul 18 06:46:48 PM PDT 24 Jul 18 06:46:53 PM PDT 24 16585142 ps
T963 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2525016438 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:53 PM PDT 24 43950523 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.842706859 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:33 PM PDT 24 165073316 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.306929052 Jul 18 06:46:25 PM PDT 24 Jul 18 06:46:36 PM PDT 24 296000753 ps
T966 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2104297510 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:26 PM PDT 24 76445985 ps
T967 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3078267493 Jul 18 06:46:55 PM PDT 24 Jul 18 06:46:57 PM PDT 24 93565209 ps
T968 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2419169641 Jul 18 06:46:42 PM PDT 24 Jul 18 06:46:48 PM PDT 24 33542886 ps
T969 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3753598348 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:52 PM PDT 24 264316334 ps
T970 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1492819227 Jul 18 06:46:52 PM PDT 24 Jul 18 06:46:57 PM PDT 24 126250392 ps
T971 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1951322597 Jul 18 06:46:25 PM PDT 24 Jul 18 06:46:35 PM PDT 24 15901714 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4202675175 Jul 18 06:46:44 PM PDT 24 Jul 18 06:46:48 PM PDT 24 53329458 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3872405325 Jul 18 06:46:30 PM PDT 24 Jul 18 06:46:45 PM PDT 24 4528460006 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.812202580 Jul 18 06:46:25 PM PDT 24 Jul 18 06:46:46 PM PDT 24 2013500469 ps
T192 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2758508467 Jul 18 06:46:21 PM PDT 24 Jul 18 06:46:25 PM PDT 24 99104923 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2235884315 Jul 18 06:46:22 PM PDT 24 Jul 18 06:46:28 PM PDT 24 31833060 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3121319633 Jul 18 06:46:20 PM PDT 24 Jul 18 06:46:29 PM PDT 24 189600805 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1641098716 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:40 PM PDT 24 83875767 ps
T978 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3465439014 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:32 PM PDT 24 1011749256 ps
T979 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.601981945 Jul 18 06:46:48 PM PDT 24 Jul 18 06:46:53 PM PDT 24 27225734 ps
T128 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1644179122 Jul 18 06:46:25 PM PDT 24 Jul 18 06:46:35 PM PDT 24 65041513 ps
T980 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1493817430 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:42 PM PDT 24 720603973 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.79003659 Jul 18 06:46:56 PM PDT 24 Jul 18 06:46:59 PM PDT 24 12674337 ps
T982 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2964077087 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:37 PM PDT 24 100755438 ps
T983 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1025338836 Jul 18 06:46:39 PM PDT 24 Jul 18 06:46:51 PM PDT 24 1041876828 ps
T984 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.257257451 Jul 18 06:46:55 PM PDT 24 Jul 18 06:46:57 PM PDT 24 15980390 ps
T985 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2186013044 Jul 18 06:46:42 PM PDT 24 Jul 18 06:47:05 PM PDT 24 835824004 ps
T986 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.55561127 Jul 18 06:46:47 PM PDT 24 Jul 18 06:46:53 PM PDT 24 68885395 ps
T987 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2514966274 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:36 PM PDT 24 139323645 ps
T194 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1204263870 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:37 PM PDT 24 35048073 ps
T988 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1054991621 Jul 18 06:46:43 PM PDT 24 Jul 18 06:46:47 PM PDT 24 11356858 ps
T989 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1738903214 Jul 18 06:46:23 PM PDT 24 Jul 18 06:46:38 PM PDT 24 1511180157 ps
T125 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3290645757 Jul 18 06:46:40 PM PDT 24 Jul 18 06:46:45 PM PDT 24 636938940 ps
T990 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3175360721 Jul 18 06:46:51 PM PDT 24 Jul 18 06:46:55 PM PDT 24 55822052 ps
T991 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1807071499 Jul 18 06:46:43 PM PDT 24 Jul 18 06:46:49 PM PDT 24 73852794 ps
T992 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.269110863 Jul 18 06:46:27 PM PDT 24 Jul 18 06:46:38 PM PDT 24 20499105 ps
T993 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1786188578 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:39 PM PDT 24 27857515 ps
T994 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2973866899 Jul 18 06:46:52 PM PDT 24 Jul 18 06:46:57 PM PDT 24 107553131 ps
T195 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1083474355 Jul 18 06:46:43 PM PDT 24 Jul 18 06:46:47 PM PDT 24 53739177 ps
T127 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.700093916 Jul 18 06:46:51 PM PDT 24 Jul 18 06:46:55 PM PDT 24 455612461 ps
T995 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2749125805 Jul 18 06:46:29 PM PDT 24 Jul 18 06:46:43 PM PDT 24 415268306 ps
T996 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3588185091 Jul 18 06:46:26 PM PDT 24 Jul 18 06:46:38 PM PDT 24 163498855 ps

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.604358862
Short name T12
Test name
Test status
Simulation time 792381975 ps
CPU time 8.62 seconds
Started Jul 18 06:57:31 PM PDT 24
Finished Jul 18 06:57:46 PM PDT 24
Peak memory 218436 kb
Host smart-a435c656-ecc2-481f-b11e-7474b85a01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604358862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.604358862
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1190065324
Short name T13
Test name
Test status
Simulation time 38677732724 ps
CPU time 287.88 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 07:01:14 PM PDT 24
Peak memory 292708 kb
Host smart-18dc070b-b33f-4bb2-b3dd-c6bca94e1c5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1190065324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1190065324
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.462640975
Short name T328
Test name
Test status
Simulation time 980080555 ps
CPU time 10.38 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:14 PM PDT 24
Peak memory 225656 kb
Host smart-1373f5b7-1efc-472c-b7cf-6b79161f1167
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462640975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.462640975
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4085403509
Short name T51
Test name
Test status
Simulation time 2284530363 ps
CPU time 12.01 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 225348 kb
Host smart-0c727003-6aaa-4dad-baa0-4528057f1d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085403509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4085403509
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1743656092
Short name T40
Test name
Test status
Simulation time 212777300952 ps
CPU time 2150.68 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 07:33:13 PM PDT 24
Peak memory 960412 kb
Host smart-35ebbdde-a678-4d94-a488-d7da0683aa77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1743656092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1743656092
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.359425921
Short name T23
Test name
Test status
Simulation time 1541941060 ps
CPU time 14.25 seconds
Started Jul 18 06:56:07 PM PDT 24
Finished Jul 18 06:56:31 PM PDT 24
Peak memory 226172 kb
Host smart-84364ad9-3d26-4c67-a061-50c11be5cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359425921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.359425921
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3866068446
Short name T108
Test name
Test status
Simulation time 155939463 ps
CPU time 2.13 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 219580 kb
Host smart-8634184c-85f1-4fbe-9bf8-025e43ad8cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386606
8446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3866068446
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1984075598
Short name T92
Test name
Test status
Simulation time 210803659 ps
CPU time 34.43 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:50 PM PDT 24
Peak memory 270848 kb
Host smart-8b60f631-cfa5-4be9-83b1-f3493eb2e25f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984075598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1984075598
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3911193594
Short name T62
Test name
Test status
Simulation time 246963481 ps
CPU time 6.89 seconds
Started Jul 18 06:55:54 PM PDT 24
Finished Jul 18 06:56:08 PM PDT 24
Peak memory 218300 kb
Host smart-bf9516d5-0253-407a-b945-92450ac3793a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911193594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
911193594
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3288077222
Short name T106
Test name
Test status
Simulation time 113065906 ps
CPU time 2.78 seconds
Started Jul 18 06:46:51 PM PDT 24
Finished Jul 18 06:46:56 PM PDT 24
Peak memory 222380 kb
Host smart-03e7b440-4981-4835-86d6-9e0a0416d453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288077222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3288077222
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3940259004
Short name T7
Test name
Test status
Simulation time 402774813 ps
CPU time 5.53 seconds
Started Jul 18 06:57:00 PM PDT 24
Finished Jul 18 06:57:11 PM PDT 24
Peak memory 217472 kb
Host smart-9923b728-1884-46d9-b2af-5dcbaa6c9e7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940259004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3940259004
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3294307836
Short name T9
Test name
Test status
Simulation time 19391502 ps
CPU time 0.91 seconds
Started Jul 18 06:58:07 PM PDT 24
Finished Jul 18 06:58:14 PM PDT 24
Peak memory 208924 kb
Host smart-47a55a56-f17c-48f0-8b09-b9d5a9b1dea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294307836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3294307836
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3928260763
Short name T187
Test name
Test status
Simulation time 18020305 ps
CPU time 1.17 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:32 PM PDT 24
Peak memory 217868 kb
Host smart-f1161554-d9ad-4d18-b643-932d9795a4bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928260763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3928260763
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1606301710
Short name T121
Test name
Test status
Simulation time 175629052 ps
CPU time 3.07 seconds
Started Jul 18 06:46:48 PM PDT 24
Finished Jul 18 06:46:54 PM PDT 24
Peak memory 217844 kb
Host smart-7dc4eba4-ad86-45d6-8482-a9a4a0f4293e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606301710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1606301710
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3564153093
Short name T123
Test name
Test status
Simulation time 112285862 ps
CPU time 3.97 seconds
Started Jul 18 06:46:48 PM PDT 24
Finished Jul 18 06:46:55 PM PDT 24
Peak memory 217816 kb
Host smart-86a4b6b9-725f-468c-81e1-4a6fc1f066c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564153093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3564153093
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.4284627726
Short name T6
Test name
Test status
Simulation time 5412918764 ps
CPU time 49.89 seconds
Started Jul 18 06:56:12 PM PDT 24
Finished Jul 18 06:57:09 PM PDT 24
Peak memory 219256 kb
Host smart-6306335b-0637-42b8-b560-65b9459301b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284627726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.4284627726
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3290645757
Short name T125
Test name
Test status
Simulation time 636938940 ps
CPU time 1.91 seconds
Started Jul 18 06:46:40 PM PDT 24
Finished Jul 18 06:46:45 PM PDT 24
Peak memory 222112 kb
Host smart-ca837135-9585-4126-943e-04f66e2fda9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290645757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3290645757
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1037489979
Short name T57
Test name
Test status
Simulation time 16870089838 ps
CPU time 195.58 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:58:32 PM PDT 24
Peak memory 270176 kb
Host smart-b502e3bb-4415-4733-98a4-5f6cc2867881
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037489979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1037489979
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2869732112
Short name T872
Test name
Test status
Simulation time 1626071800 ps
CPU time 10.37 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:42 PM PDT 24
Peak memory 209396 kb
Host smart-38034633-a4a5-40b6-887e-927f924542a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869732112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2869732112
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1133176745
Short name T118
Test name
Test status
Simulation time 163178487 ps
CPU time 3.36 seconds
Started Jul 18 06:46:53 PM PDT 24
Finished Jul 18 06:46:58 PM PDT 24
Peak memory 217836 kb
Host smart-a8f1ea43-6569-476f-8ee9-8fce6466c3a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133176745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1133176745
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.8815019
Short name T197
Test name
Test status
Simulation time 32730138 ps
CPU time 1.16 seconds
Started Jul 18 06:46:21 PM PDT 24
Finished Jul 18 06:46:26 PM PDT 24
Peak memory 209684 kb
Host smart-7c574aa8-3f8d-4888-bf7d-07453584e136
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8815019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sa
me_csr_outstanding.8815019
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.59716626
Short name T3
Test name
Test status
Simulation time 20865998 ps
CPU time 1.05 seconds
Started Jul 18 06:56:22 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 211888 kb
Host smart-5929cf34-ebf4-4ad9-a207-c80c156be0f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59716626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_volatile_unlock_smoke.59716626
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4053239652
Short name T45
Test name
Test status
Simulation time 1193229977 ps
CPU time 7.18 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:22 PM PDT 24
Peak memory 225216 kb
Host smart-5ac2d31b-af6a-4e2f-9c10-5cfca5a61fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053239652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4053239652
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2179845738
Short name T117
Test name
Test status
Simulation time 438081479 ps
CPU time 3.36 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:47:01 PM PDT 24
Peak memory 222920 kb
Host smart-4e18dc4e-5fa9-4844-a019-93c61a4de8f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179845738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2179845738
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2340219229
Short name T207
Test name
Test status
Simulation time 19343988 ps
CPU time 0.77 seconds
Started Jul 18 06:55:04 PM PDT 24
Finished Jul 18 06:55:09 PM PDT 24
Peak memory 209124 kb
Host smart-73ddb4bd-36aa-4565-9434-faa5dd91faaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340219229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2340219229
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.782574276
Short name T205
Test name
Test status
Simulation time 28215821 ps
CPU time 0.93 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:55:55 PM PDT 24
Peak memory 208832 kb
Host smart-bfcf6b32-ac4a-4451-82f1-c4acaa485074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782574276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.782574276
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3614702619
Short name T22
Test name
Test status
Simulation time 1319674582 ps
CPU time 9.81 seconds
Started Jul 18 06:57:10 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 226164 kb
Host smart-b5b45721-6593-4c91-9f20-15502aeb034c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614702619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3614702619
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1644179122
Short name T128
Test name
Test status
Simulation time 65041513 ps
CPU time 2.02 seconds
Started Jul 18 06:46:25 PM PDT 24
Finished Jul 18 06:46:35 PM PDT 24
Peak memory 222384 kb
Host smart-9fb353c9-9e02-413c-aa8c-a846fdb91162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644179122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1644179122
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3287398961
Short name T124
Test name
Test status
Simulation time 81913580 ps
CPU time 2.68 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:47:00 PM PDT 24
Peak memory 217952 kb
Host smart-3bc583bd-8836-4099-8ba1-79bf9ecccc3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287398961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3287398961
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.700093916
Short name T127
Test name
Test status
Simulation time 455612461 ps
CPU time 2.03 seconds
Started Jul 18 06:46:51 PM PDT 24
Finished Jul 18 06:46:55 PM PDT 24
Peak memory 222260 kb
Host smart-453c17dc-0806-4eea-9f1a-d65cd05670eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700093916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.700093916
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.827758536
Short name T131
Test name
Test status
Simulation time 68654374 ps
CPU time 2.59 seconds
Started Jul 18 06:46:51 PM PDT 24
Finished Jul 18 06:46:56 PM PDT 24
Peak memory 217816 kb
Host smart-734fc111-ebf1-4c23-a38d-814a4e3e7a33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827758536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.827758536
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2855459237
Short name T119
Test name
Test status
Simulation time 39817301 ps
CPU time 2.36 seconds
Started Jul 18 06:46:46 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 217524 kb
Host smart-05cfddf9-4cec-4953-8e1a-1a4a5215b816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855459237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2855459237
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3849849049
Short name T126
Test name
Test status
Simulation time 194932993 ps
CPU time 1.71 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:34 PM PDT 24
Peak memory 222340 kb
Host smart-09c8ff84-835e-4818-af2f-218f1584f556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849849049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3849849049
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3954507901
Short name T122
Test name
Test status
Simulation time 1205598641 ps
CPU time 2.83 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 222456 kb
Host smart-bc07e794-3f5d-47d7-a33b-a468a758be0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954507901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3954507901
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1292661377
Short name T129
Test name
Test status
Simulation time 181284860 ps
CPU time 2.08 seconds
Started Jul 18 06:46:39 PM PDT 24
Finished Jul 18 06:46:44 PM PDT 24
Peak memory 217816 kb
Host smart-39cf4cb9-1d3e-4fde-bdae-62bfb94d8671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292661377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1292661377
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1178977256
Short name T41
Test name
Test status
Simulation time 10018577839 ps
CPU time 207.09 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:59:40 PM PDT 24
Peak memory 283980 kb
Host smart-00e49ac1-7000-4c59-84fc-92e328b6c057
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1178977256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.1178977256
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2762167220
Short name T87
Test name
Test status
Simulation time 259201429 ps
CPU time 30.39 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:56:08 PM PDT 24
Peak memory 250996 kb
Host smart-2f22653d-0360-49f5-a0da-bf216897f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762167220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2762167220
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1873450078
Short name T26
Test name
Test status
Simulation time 2563338904 ps
CPU time 74.4 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:57:54 PM PDT 24
Peak memory 218616 kb
Host smart-3354823e-0254-4d43-8c92-79ec64704f7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873450078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1873450078
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.25990828
Short name T943
Test name
Test status
Simulation time 255102165 ps
CPU time 2.49 seconds
Started Jul 18 06:46:21 PM PDT 24
Finished Jul 18 06:46:27 PM PDT 24
Peak memory 209436 kb
Host smart-385e64fb-1b63-4ffb-b395-fafaa58b5635
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25990828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash.25990828
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1524151730
Short name T867
Test name
Test status
Simulation time 21061406 ps
CPU time 1.02 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 210388 kb
Host smart-2e72085f-ed6d-4b66-a651-04464e1930e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524151730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1524151730
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2403511578
Short name T960
Test name
Test status
Simulation time 113443871 ps
CPU time 1.33 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 219836 kb
Host smart-9a8891e1-33d2-482e-82ae-16c9f4723689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403511578 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2403511578
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2758508467
Short name T192
Test name
Test status
Simulation time 99104923 ps
CPU time 0.95 seconds
Started Jul 18 06:46:21 PM PDT 24
Finished Jul 18 06:46:25 PM PDT 24
Peak memory 209624 kb
Host smart-f1b6e316-4c54-4316-9220-2ea7777a04bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758508467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2758508467
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3568271516
Short name T952
Test name
Test status
Simulation time 215956165 ps
CPU time 2.14 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 209496 kb
Host smart-2c6845ac-b43f-474e-a7d9-2af46c1bc2ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568271516 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3568271516
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3121319633
Short name T976
Test name
Test status
Simulation time 189600805 ps
CPU time 5.45 seconds
Started Jul 18 06:46:20 PM PDT 24
Finished Jul 18 06:46:29 PM PDT 24
Peak memory 209544 kb
Host smart-6b02c72f-9828-408c-95f3-b23fe76199bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121319633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3121319633
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1911028190
Short name T912
Test name
Test status
Simulation time 356230920 ps
CPU time 9.06 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 209308 kb
Host smart-401db3aa-56ed-41f4-a78c-b43fe0cf3191
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911028190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1911028190
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1264696476
Short name T877
Test name
Test status
Simulation time 276970401 ps
CPU time 2.33 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:35 PM PDT 24
Peak memory 211148 kb
Host smart-9779a092-6f52-46de-a94a-4dad87cd932b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264696476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1264696476
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1953488519
Short name T874
Test name
Test status
Simulation time 91173506 ps
CPU time 2.01 seconds
Started Jul 18 06:46:21 PM PDT 24
Finished Jul 18 06:46:27 PM PDT 24
Peak memory 217896 kb
Host smart-243e654d-5c02-48ee-a851-d5552a438f29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195348
8519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1953488519
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1410709061
Short name T903
Test name
Test status
Simulation time 57453085 ps
CPU time 2.14 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:35 PM PDT 24
Peak memory 209812 kb
Host smart-1cd647f6-eb7c-464b-a89f-4f6acb1caa0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410709061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1410709061
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.205582350
Short name T934
Test name
Test status
Simulation time 62992965 ps
CPU time 1 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:31 PM PDT 24
Peak memory 209488 kb
Host smart-d365aede-d093-45c9-bc7e-34e2553174ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205582350 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.205582350
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2435085490
Short name T899
Test name
Test status
Simulation time 54123973 ps
CPU time 1.75 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:28 PM PDT 24
Peak memory 217832 kb
Host smart-4b78222c-f953-4870-a6df-9b20e6c0352b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435085490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2435085490
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2235884315
Short name T975
Test name
Test status
Simulation time 31833060 ps
CPU time 1.21 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:28 PM PDT 24
Peak memory 209096 kb
Host smart-f17da6ca-fe73-4b5c-986c-1d59edcf886b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235884315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2235884315
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.900520985
Short name T886
Test name
Test status
Simulation time 30476851 ps
CPU time 1.14 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:29 PM PDT 24
Peak memory 209580 kb
Host smart-7c6a6708-0c63-481c-a60f-44d299894938
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900520985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.900520985
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2104297510
Short name T966
Test name
Test status
Simulation time 76445985 ps
CPU time 1.03 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:26 PM PDT 24
Peak memory 210356 kb
Host smart-c01e0d0f-e0a0-4988-8580-f10de9663214
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104297510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2104297510
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2004191498
Short name T883
Test name
Test status
Simulation time 23293700 ps
CPU time 1.52 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:34 PM PDT 24
Peak memory 224836 kb
Host smart-d108fe4b-c3c8-47b5-a11e-210c25c031e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004191498 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2004191498
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1637873420
Short name T198
Test name
Test status
Simulation time 43168323 ps
CPU time 1 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:27 PM PDT 24
Peak memory 209640 kb
Host smart-1e88da7b-5238-45aa-863e-5ca2cfd81529
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637873420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1637873420
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.795156794
Short name T870
Test name
Test status
Simulation time 476857089 ps
CPU time 1.58 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:30 PM PDT 24
Peak memory 209468 kb
Host smart-94b8eb13-af23-4e9c-bc8a-66850b709a6b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795156794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.795156794
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.812202580
Short name T974
Test name
Test status
Simulation time 2013500469 ps
CPU time 12.42 seconds
Started Jul 18 06:46:25 PM PDT 24
Finished Jul 18 06:46:46 PM PDT 24
Peak memory 208988 kb
Host smart-fb3b98bd-19f5-4b3f-891a-6d5735b92098
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812202580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.812202580
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.842706859
Short name T964
Test name
Test status
Simulation time 165073316 ps
CPU time 2.55 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:33 PM PDT 24
Peak memory 211036 kb
Host smart-66afdb95-b941-403f-a125-a8199e177dd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842706859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.842706859
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3465439014
Short name T978
Test name
Test status
Simulation time 1011749256 ps
CPU time 3.13 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:32 PM PDT 24
Peak memory 218900 kb
Host smart-31fa8efc-91d0-431f-8356-a72342f8fc7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346543
9014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3465439014
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1748761192
Short name T885
Test name
Test status
Simulation time 56629409 ps
CPU time 1.93 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:27 PM PDT 24
Peak memory 209592 kb
Host smart-7de88d18-092a-49cf-9ffe-3dcf9f539060
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748761192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1748761192
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3777386821
Short name T937
Test name
Test status
Simulation time 17810973 ps
CPU time 1.14 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:32 PM PDT 24
Peak memory 209748 kb
Host smart-7e36a480-c0e0-45c2-94dc-f99645b52984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777386821 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3777386821
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4170180360
Short name T948
Test name
Test status
Simulation time 45849873 ps
CPU time 1.39 seconds
Started Jul 18 06:46:21 PM PDT 24
Finished Jul 18 06:46:26 PM PDT 24
Peak memory 217940 kb
Host smart-2a4577b2-2128-484f-850c-aec40b5c29f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170180360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.4170180360
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1301563377
Short name T951
Test name
Test status
Simulation time 335682294 ps
CPU time 1.92 seconds
Started Jul 18 06:46:25 PM PDT 24
Finished Jul 18 06:46:35 PM PDT 24
Peak memory 217756 kb
Host smart-19bec5d0-2c1c-4491-b6ae-883b34a84374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301563377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1301563377
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1687150119
Short name T116
Test name
Test status
Simulation time 773550684 ps
CPU time 3.94 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 217808 kb
Host smart-d7974103-4bb0-45cb-b9b6-05b0f2ae7fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687150119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1687150119
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4206221265
Short name T875
Test name
Test status
Simulation time 38890493 ps
CPU time 1.41 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:46:59 PM PDT 24
Peak memory 218100 kb
Host smart-885b87a0-4698-42d3-8f39-8987076f46dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206221265 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4206221265
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1066752674
Short name T930
Test name
Test status
Simulation time 13668832 ps
CPU time 0.85 seconds
Started Jul 18 06:46:48 PM PDT 24
Finished Jul 18 06:46:52 PM PDT 24
Peak memory 209620 kb
Host smart-495829e9-eb11-4be6-94eb-6cfdc0bf7792
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066752674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1066752674
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4268069169
Short name T955
Test name
Test status
Simulation time 57532704 ps
CPU time 1.17 seconds
Started Jul 18 06:46:40 PM PDT 24
Finished Jul 18 06:46:44 PM PDT 24
Peak memory 209608 kb
Host smart-85e0de4c-17f9-4fdc-94f6-7a35f193f7e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268069169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.4268069169
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3740708235
Short name T914
Test name
Test status
Simulation time 199731580 ps
CPU time 2.05 seconds
Started Jul 18 06:46:52 PM PDT 24
Finished Jul 18 06:46:56 PM PDT 24
Peak memory 217848 kb
Host smart-9517beef-3f92-4013-a3ca-a20a86ef801f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740708235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3740708235
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1261168072
Short name T132
Test name
Test status
Simulation time 239573623 ps
CPU time 2.28 seconds
Started Jul 18 06:46:38 PM PDT 24
Finished Jul 18 06:46:44 PM PDT 24
Peak memory 217828 kb
Host smart-9828b436-3a00-49ce-8c39-9495206ef2c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261168072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1261168072
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3572433129
Short name T921
Test name
Test status
Simulation time 111880891 ps
CPU time 1.38 seconds
Started Jul 18 06:46:55 PM PDT 24
Finished Jul 18 06:46:58 PM PDT 24
Peak memory 217904 kb
Host smart-256a2421-c91a-43ba-9986-d78c8f7fec02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572433129 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3572433129
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1865883754
Short name T188
Test name
Test status
Simulation time 15708540 ps
CPU time 1.05 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:52 PM PDT 24
Peak memory 209632 kb
Host smart-3fb87856-cec0-42a0-b5da-dbdd2a6dfaa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865883754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1865883754
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3251744140
Short name T200
Test name
Test status
Simulation time 85619054 ps
CPU time 1.03 seconds
Started Jul 18 06:46:51 PM PDT 24
Finished Jul 18 06:46:54 PM PDT 24
Peak memory 209712 kb
Host smart-f8ac2b0a-7370-4ad1-9baa-a38044972a88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251744140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3251744140
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2313358696
Short name T114
Test name
Test status
Simulation time 128497531 ps
CPU time 2.04 seconds
Started Jul 18 06:46:55 PM PDT 24
Finished Jul 18 06:46:58 PM PDT 24
Peak memory 217848 kb
Host smart-9173ea56-876f-4c82-b04a-f019a46a7380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313358696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2313358696
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1159800754
Short name T929
Test name
Test status
Simulation time 19985725 ps
CPU time 1.25 seconds
Started Jul 18 06:46:48 PM PDT 24
Finished Jul 18 06:46:52 PM PDT 24
Peak memory 219992 kb
Host smart-039aa177-7d80-4378-8fd2-9313b18cdfab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159800754 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1159800754
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1851343557
Short name T864
Test name
Test status
Simulation time 40103051 ps
CPU time 0.79 seconds
Started Jul 18 06:46:55 PM PDT 24
Finished Jul 18 06:46:58 PM PDT 24
Peak memory 209708 kb
Host smart-f4d5e760-3838-418e-b805-683b81aa20c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851343557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1851343557
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1085591430
Short name T887
Test name
Test status
Simulation time 27644371 ps
CPU time 1.42 seconds
Started Jul 18 06:46:44 PM PDT 24
Finished Jul 18 06:46:48 PM PDT 24
Peak memory 209740 kb
Host smart-7600e5be-c810-48cb-9893-19d5036f01b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085591430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1085591430
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1464126262
Short name T873
Test name
Test status
Simulation time 30183173 ps
CPU time 1.71 seconds
Started Jul 18 06:46:39 PM PDT 24
Finished Jul 18 06:46:44 PM PDT 24
Peak memory 217828 kb
Host smart-ccd44598-447f-4ff2-a403-45110027036f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464126262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1464126262
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.695981249
Short name T907
Test name
Test status
Simulation time 322950223 ps
CPU time 1.38 seconds
Started Jul 18 06:46:53 PM PDT 24
Finished Jul 18 06:46:56 PM PDT 24
Peak memory 217900 kb
Host smart-a4344f6a-e61e-46a9-8b2d-b7968abcbb24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695981249 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.695981249
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.108435801
Short name T146
Test name
Test status
Simulation time 70808481 ps
CPU time 0.89 seconds
Started Jul 18 06:46:44 PM PDT 24
Finished Jul 18 06:46:48 PM PDT 24
Peak memory 209616 kb
Host smart-bbd8ba35-7119-465e-9abe-2da0bcea21f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108435801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.108435801
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4230420314
Short name T880
Test name
Test status
Simulation time 27417780 ps
CPU time 1.37 seconds
Started Jul 18 06:46:42 PM PDT 24
Finished Jul 18 06:46:47 PM PDT 24
Peak memory 209636 kb
Host smart-7999c763-6cd4-41b7-9952-167f7d5f7bcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230420314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.4230420314
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2525016438
Short name T963
Test name
Test status
Simulation time 43950523 ps
CPU time 1.69 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 217952 kb
Host smart-8ae01388-54f2-41bc-8920-27e448a25211
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525016438 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2525016438
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3050213867
Short name T931
Test name
Test status
Simulation time 166190109 ps
CPU time 1.08 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:46:59 PM PDT 24
Peak memory 209684 kb
Host smart-a8337810-33c1-45d1-b332-cc492707a1bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050213867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3050213867
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3753598348
Short name T969
Test name
Test status
Simulation time 264316334 ps
CPU time 0.97 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:52 PM PDT 24
Peak memory 209620 kb
Host smart-96a17f7e-79ba-405f-aa5e-87960041ea12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753598348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3753598348
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1523971435
Short name T866
Test name
Test status
Simulation time 112915947 ps
CPU time 4.4 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 217916 kb
Host smart-7122f5c9-2ef3-4e9c-871e-429203dfb951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523971435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1523971435
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.601981945
Short name T979
Test name
Test status
Simulation time 27225734 ps
CPU time 2.09 seconds
Started Jul 18 06:46:48 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 219048 kb
Host smart-6cf306f0-6df6-4eb6-9e5a-941d0835910c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601981945 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.601981945
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2639969676
Short name T191
Test name
Test status
Simulation time 16585142 ps
CPU time 1.11 seconds
Started Jul 18 06:46:48 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 209620 kb
Host smart-ce4fd354-85de-4587-811e-2ff9915abfd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639969676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2639969676
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3564767076
Short name T897
Test name
Test status
Simulation time 113864250 ps
CPU time 1.38 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:52 PM PDT 24
Peak memory 209640 kb
Host smart-bb5cf447-1ac3-407d-b499-a6af02318df9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564767076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3564767076
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2730705297
Short name T891
Test name
Test status
Simulation time 130379070 ps
CPU time 3.67 seconds
Started Jul 18 06:46:48 PM PDT 24
Finished Jul 18 06:46:55 PM PDT 24
Peak memory 218004 kb
Host smart-4a696829-2dda-497c-95e4-c9dd11bf6c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730705297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2730705297
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2060288130
Short name T924
Test name
Test status
Simulation time 24744045 ps
CPU time 1.52 seconds
Started Jul 18 06:46:38 PM PDT 24
Finished Jul 18 06:46:44 PM PDT 24
Peak memory 219820 kb
Host smart-9ce7d011-4223-4dad-b2f1-c03b66f393f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060288130 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2060288130
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3679379981
Short name T189
Test name
Test status
Simulation time 137880170 ps
CPU time 0.92 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:51 PM PDT 24
Peak memory 209628 kb
Host smart-2440e330-9019-4cc8-8062-b50a72a2d4c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679379981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3679379981
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3795384391
Short name T199
Test name
Test status
Simulation time 415438470 ps
CPU time 1.11 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:52 PM PDT 24
Peak memory 209632 kb
Host smart-49cbade8-4991-4620-aa5d-4065857283a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795384391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3795384391
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3804596005
Short name T911
Test name
Test status
Simulation time 415144888 ps
CPU time 2.22 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:47:00 PM PDT 24
Peak memory 218064 kb
Host smart-b4f5db11-766f-4e30-9819-f75efc63d850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804596005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3804596005
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2824611797
Short name T940
Test name
Test status
Simulation time 98232955 ps
CPU time 1.57 seconds
Started Jul 18 06:46:41 PM PDT 24
Finished Jul 18 06:46:45 PM PDT 24
Peak memory 219032 kb
Host smart-da572531-4278-4ca7-9fbd-b34328232f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824611797 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2824611797
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.626199465
Short name T895
Test name
Test status
Simulation time 13074025 ps
CPU time 0.89 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:46:59 PM PDT 24
Peak memory 209776 kb
Host smart-94f93a61-2ca3-45e8-82fb-6584116254a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626199465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.626199465
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3593285066
Short name T945
Test name
Test status
Simulation time 27351783 ps
CPU time 1.49 seconds
Started Jul 18 06:46:46 PM PDT 24
Finished Jul 18 06:46:52 PM PDT 24
Peak memory 209384 kb
Host smart-845a8ee4-fca1-4743-bcb7-cf13eea57ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593285066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3593285066
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2196237728
Short name T889
Test name
Test status
Simulation time 147330644 ps
CPU time 1.89 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:47:00 PM PDT 24
Peak memory 217980 kb
Host smart-a5d50533-4ab3-4858-a220-3fe7fed58e46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196237728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2196237728
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2419169641
Short name T968
Test name
Test status
Simulation time 33542886 ps
CPU time 1.82 seconds
Started Jul 18 06:46:42 PM PDT 24
Finished Jul 18 06:46:48 PM PDT 24
Peak memory 218104 kb
Host smart-df81fba8-1943-467b-b72c-fcbd65a597cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419169641 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2419169641
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2619422671
Short name T942
Test name
Test status
Simulation time 19440609 ps
CPU time 0.84 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:51 PM PDT 24
Peak memory 209276 kb
Host smart-a3f941a2-d404-413b-8dbd-a4b34fefc346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619422671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2619422671
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4189238651
Short name T928
Test name
Test status
Simulation time 342793672 ps
CPU time 1.24 seconds
Started Jul 18 06:46:46 PM PDT 24
Finished Jul 18 06:46:51 PM PDT 24
Peak memory 217832 kb
Host smart-3a4fa222-ef5d-466b-b249-e0d9920d9202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189238651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.4189238651
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3645038050
Short name T876
Test name
Test status
Simulation time 86449489 ps
CPU time 2.76 seconds
Started Jul 18 06:46:43 PM PDT 24
Finished Jul 18 06:46:49 PM PDT 24
Peak memory 217860 kb
Host smart-6c9ee0f5-b714-4bea-997e-b8fb34c15574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645038050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3645038050
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.55561127
Short name T986
Test name
Test status
Simulation time 68885395 ps
CPU time 2 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 222120 kb
Host smart-cd21d650-dc10-421d-9fc5-ed74f470a962
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55561127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_e
rr.55561127
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.949481675
Short name T916
Test name
Test status
Simulation time 235982784 ps
CPU time 1.32 seconds
Started Jul 18 06:46:46 PM PDT 24
Finished Jul 18 06:46:51 PM PDT 24
Peak memory 218960 kb
Host smart-8e7d95ce-e15f-44fa-ba45-fffd9aac95eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949481675 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.949481675
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1083474355
Short name T195
Test name
Test status
Simulation time 53739177 ps
CPU time 0.89 seconds
Started Jul 18 06:46:43 PM PDT 24
Finished Jul 18 06:46:47 PM PDT 24
Peak memory 209384 kb
Host smart-f263a95d-f8a4-4ec3-8bcf-c072a28fdde2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083474355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1083474355
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1733127835
Short name T926
Test name
Test status
Simulation time 103758277 ps
CPU time 1.06 seconds
Started Jul 18 06:46:40 PM PDT 24
Finished Jul 18 06:46:44 PM PDT 24
Peak memory 209620 kb
Host smart-a391dfcd-441c-4fe0-89c4-b031fb7cd761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733127835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1733127835
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3799092590
Short name T944
Test name
Test status
Simulation time 410297899 ps
CPU time 4.34 seconds
Started Jul 18 06:46:46 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 217828 kb
Host smart-905e3d47-035f-4642-9d3a-b67453e709d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799092590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3799092590
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2733087312
Short name T130
Test name
Test status
Simulation time 64177184 ps
CPU time 2.62 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 217752 kb
Host smart-48916fae-eb56-47b8-aac0-9b3d568883dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733087312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2733087312
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1000054422
Short name T898
Test name
Test status
Simulation time 36252348 ps
CPU time 1.02 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:33 PM PDT 24
Peak memory 209664 kb
Host smart-248f4747-3d3a-4d11-a228-9127ac127df6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000054422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1000054422
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3205204998
Short name T865
Test name
Test status
Simulation time 66421706 ps
CPU time 1.28 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:32 PM PDT 24
Peak memory 209676 kb
Host smart-e064d0ab-80cd-4c3e-8e64-82a886f58fa7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205204998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3205204998
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.269110863
Short name T992
Test name
Test status
Simulation time 20499105 ps
CPU time 1.24 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 211804 kb
Host smart-64c258bb-5992-481b-beaf-c2a66f622936
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269110863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.269110863
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3673884734
Short name T923
Test name
Test status
Simulation time 24663554 ps
CPU time 1.16 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:32 PM PDT 24
Peak memory 217944 kb
Host smart-18a62354-d943-4aee-97f5-3d5fd65b0f30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673884734 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3673884734
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2348429189
Short name T910
Test name
Test status
Simulation time 13152776 ps
CPU time 0.86 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:39 PM PDT 24
Peak memory 209528 kb
Host smart-b816db88-9383-4fa9-8625-bf8f3ba118ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348429189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2348429189
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4238232028
Short name T932
Test name
Test status
Simulation time 276700161 ps
CPU time 2.39 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 208212 kb
Host smart-f1756b88-dc1a-41fe-9960-453d8a7b62d4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238232028 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4238232028
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1767554455
Short name T869
Test name
Test status
Simulation time 192064851 ps
CPU time 2.79 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:33 PM PDT 24
Peak memory 208808 kb
Host smart-11eea79c-abd4-422d-82f0-c703b77a3567
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767554455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1767554455
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1738903214
Short name T989
Test name
Test status
Simulation time 1511180157 ps
CPU time 8.47 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 209352 kb
Host smart-b4c18ae4-83b0-4a63-af51-ee72b342deed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738903214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1738903214
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.951918598
Short name T917
Test name
Test status
Simulation time 985385242 ps
CPU time 4.1 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:33 PM PDT 24
Peak memory 211216 kb
Host smart-de841ed9-8406-4fdb-86b4-b329af4401d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951918598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.951918598
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.429429658
Short name T905
Test name
Test status
Simulation time 705220263 ps
CPU time 5.26 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 218552 kb
Host smart-eeb174c9-5ad8-4864-8ed5-15d9cf6d172c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429429
658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.429429658
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3499731922
Short name T137
Test name
Test status
Simulation time 166745391 ps
CPU time 1.2 seconds
Started Jul 18 06:46:22 PM PDT 24
Finished Jul 18 06:46:28 PM PDT 24
Peak memory 209548 kb
Host smart-d5951a5f-b8bf-48ef-8da3-f1490561f0bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499731922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3499731922
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1951322597
Short name T971
Test name
Test status
Simulation time 15901714 ps
CPU time 1.14 seconds
Started Jul 18 06:46:25 PM PDT 24
Finished Jul 18 06:46:35 PM PDT 24
Peak memory 209652 kb
Host smart-52ff90e5-0c48-4bff-8447-5c6c57839acd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951322597 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1951322597
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1504296390
Short name T936
Test name
Test status
Simulation time 215957223 ps
CPU time 1 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:39 PM PDT 24
Peak memory 209692 kb
Host smart-62256402-a496-42ee-b52a-da7a416b6ba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504296390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1504296390
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1758301886
Short name T919
Test name
Test status
Simulation time 308878126 ps
CPU time 2.96 seconds
Started Jul 18 06:46:21 PM PDT 24
Finished Jul 18 06:46:26 PM PDT 24
Peak memory 218396 kb
Host smart-629ca0f0-d6c1-40b2-b7d4-e7694b97c1d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758301886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1758301886
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4105007367
Short name T185
Test name
Test status
Simulation time 57247388 ps
CPU time 1.11 seconds
Started Jul 18 06:46:30 PM PDT 24
Finished Jul 18 06:46:40 PM PDT 24
Peak memory 209736 kb
Host smart-657b902e-0cb7-4ea8-b01a-d05cae39e578
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105007367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4105007367
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.839716806
Short name T193
Test name
Test status
Simulation time 200673462 ps
CPU time 2.23 seconds
Started Jul 18 06:46:30 PM PDT 24
Finished Jul 18 06:46:41 PM PDT 24
Peak memory 209560 kb
Host smart-25cbcb0f-02d9-4c74-b42b-91bb9368ca82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839716806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.839716806
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3362234439
Short name T186
Test name
Test status
Simulation time 49492898 ps
CPU time 1.04 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 210196 kb
Host smart-01ce285f-2704-4e3f-8633-f84cbb70675e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362234439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3362234439
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.334872349
Short name T879
Test name
Test status
Simulation time 27300260 ps
CPU time 1.19 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 219896 kb
Host smart-e44b207f-6a08-4b70-b791-0b280a57e7b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334872349 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.334872349
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3902842750
Short name T184
Test name
Test status
Simulation time 26360319 ps
CPU time 0.92 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 217524 kb
Host smart-23c3ef84-cac5-4f35-aac9-4fff5693f2b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902842750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3902842750
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.647480741
Short name T950
Test name
Test status
Simulation time 28422953 ps
CPU time 1.07 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 209456 kb
Host smart-5b4b56dc-d343-462d-b9c8-fc7b61cdccca
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647480741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.647480741
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3188757969
Short name T133
Test name
Test status
Simulation time 4848405847 ps
CPU time 11.67 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:47 PM PDT 24
Peak memory 209560 kb
Host smart-a0df8086-bc51-47f9-8c1a-e5ff0e2dc660
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188757969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3188757969
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1593426918
Short name T913
Test name
Test status
Simulation time 4274528610 ps
CPU time 8.38 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:47 PM PDT 24
Peak memory 209648 kb
Host smart-2233e2d0-d0a4-4b37-a6b9-db40a34a9ee8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593426918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1593426918
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.475580675
Short name T915
Test name
Test status
Simulation time 163377737 ps
CPU time 4.21 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:40 PM PDT 24
Peak memory 211256 kb
Host smart-fb34d5eb-cfe6-4bbb-b380-70cc670688a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475580675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.475580675
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3837025818
Short name T134
Test name
Test status
Simulation time 187747703 ps
CPU time 1.94 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 218860 kb
Host smart-4d40527b-b35c-40f7-8c8b-476a5a754296
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383702
5818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3837025818
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.405787202
Short name T893
Test name
Test status
Simulation time 424424874 ps
CPU time 1.09 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:39 PM PDT 24
Peak memory 209576 kb
Host smart-247eb474-4126-4088-93a1-338d3b91b3b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405787202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.405787202
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3776766913
Short name T901
Test name
Test status
Simulation time 45082576 ps
CPU time 1.27 seconds
Started Jul 18 06:46:45 PM PDT 24
Finished Jul 18 06:46:50 PM PDT 24
Peak memory 209820 kb
Host smart-3e7f8ccc-4290-494f-b937-ee191538747e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776766913 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3776766913
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2437388114
Short name T904
Test name
Test status
Simulation time 60292148 ps
CPU time 0.99 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:39 PM PDT 24
Peak memory 209628 kb
Host smart-d6038d31-bec0-40e6-bcb9-0049c21d74de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437388114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2437388114
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3588185091
Short name T996
Test name
Test status
Simulation time 163498855 ps
CPU time 3.09 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 217904 kb
Host smart-feba67be-305d-4cd3-9b50-6bbbc41e7351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588185091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3588185091
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3402466913
Short name T109
Test name
Test status
Simulation time 315223330 ps
CPU time 1.94 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 221856 kb
Host smart-5f0eb60c-28ab-4d25-b38a-eeef8655fe12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402466913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3402466913
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1786188578
Short name T993
Test name
Test status
Simulation time 27857515 ps
CPU time 1.11 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:39 PM PDT 24
Peak memory 209592 kb
Host smart-8fe216bf-796b-492c-8b6c-023b5730239b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786188578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1786188578
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.306929052
Short name T965
Test name
Test status
Simulation time 296000753 ps
CPU time 2.52 seconds
Started Jul 18 06:46:25 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 209568 kb
Host smart-38ae4b25-382b-4d0f-91cd-224af6c4504f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306929052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.306929052
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3938497405
Short name T961
Test name
Test status
Simulation time 60692014 ps
CPU time 1.05 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:39 PM PDT 24
Peak memory 209788 kb
Host smart-0d57bb0a-ca2a-4f05-8a9c-646b99c7fbe0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938497405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3938497405
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4174114863
Short name T949
Test name
Test status
Simulation time 16263202 ps
CPU time 1.21 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 219944 kb
Host smart-85072ee8-d3dc-4d32-adae-8041873eb1c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174114863 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.4174114863
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2731631159
Short name T190
Test name
Test status
Simulation time 22796686 ps
CPU time 0.86 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:35 PM PDT 24
Peak memory 209604 kb
Host smart-fed71059-bd4e-4a46-994b-f5217d8aab87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731631159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2731631159
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3583941288
Short name T884
Test name
Test status
Simulation time 33875327 ps
CPU time 1.54 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:40 PM PDT 24
Peak memory 209472 kb
Host smart-fa429a7e-f320-4e0f-a5f7-5f64fa36f3eb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583941288 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3583941288
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.498478154
Short name T939
Test name
Test status
Simulation time 1534643687 ps
CPU time 6.46 seconds
Started Jul 18 06:46:30 PM PDT 24
Finished Jul 18 06:46:46 PM PDT 24
Peak memory 209364 kb
Host smart-185d398e-6846-43c3-aaf0-e7ff0287f0a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498478154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.498478154
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3872405325
Short name T973
Test name
Test status
Simulation time 4528460006 ps
CPU time 5.48 seconds
Started Jul 18 06:46:30 PM PDT 24
Finished Jul 18 06:46:45 PM PDT 24
Peak memory 209604 kb
Host smart-54c3a5b5-f4dc-4b27-9175-110ddf98eabd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872405325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3872405325
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3140900376
Short name T920
Test name
Test status
Simulation time 246222663 ps
CPU time 3 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 211156 kb
Host smart-b7d20c17-dad1-465d-b288-921351ff590b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140900376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3140900376
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1493817430
Short name T980
Test name
Test status
Simulation time 720603973 ps
CPU time 3.68 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:42 PM PDT 24
Peak memory 218468 kb
Host smart-e1e5d0e8-121f-454d-998b-d8a21d9b351c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149381
7430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1493817430
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1641098716
Short name T977
Test name
Test status
Simulation time 83875767 ps
CPU time 1.8 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:40 PM PDT 24
Peak memory 209536 kb
Host smart-6345b3fd-9f25-41b3-9bf2-8d6e33481b1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641098716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1641098716
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.314295230
Short name T927
Test name
Test status
Simulation time 30269184 ps
CPU time 1.11 seconds
Started Jul 18 06:46:28 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 209640 kb
Host smart-8e00781e-7f51-4c12-8e4c-c31a9e2feccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314295230 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.314295230
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3236773781
Short name T201
Test name
Test status
Simulation time 72916176 ps
CPU time 1.35 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 211792 kb
Host smart-b12d7523-40ce-4786-b1c8-5c44b34bbf43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236773781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3236773781
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1678567504
Short name T871
Test name
Test status
Simulation time 129964451 ps
CPU time 2.78 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:41 PM PDT 24
Peak memory 217836 kb
Host smart-d288ed5d-43ab-4fc5-8ad9-6324b23c4c31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678567504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1678567504
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4198490129
Short name T868
Test name
Test status
Simulation time 95898747 ps
CPU time 2 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:39 PM PDT 24
Peak memory 220072 kb
Host smart-2c53595f-1ab1-48c3-b877-e105e87b8fb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198490129 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4198490129
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1204263870
Short name T194
Test name
Test status
Simulation time 35048073 ps
CPU time 0.8 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 209552 kb
Host smart-34254764-e4ae-4de0-b2f6-112ba078f275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204263870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1204263870
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.756838805
Short name T894
Test name
Test status
Simulation time 26310388 ps
CPU time 0.94 seconds
Started Jul 18 06:46:25 PM PDT 24
Finished Jul 18 06:46:34 PM PDT 24
Peak memory 209448 kb
Host smart-a7d46d5e-c1bc-4f0e-a845-4a9c2f9308f1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756838805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.756838805
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.942235520
Short name T962
Test name
Test status
Simulation time 228618168 ps
CPU time 2.61 seconds
Started Jul 18 06:46:25 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 209376 kb
Host smart-729e3828-3169-42a6-b7cd-2ed7b75f8156
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942235520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.942235520
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3395238688
Short name T892
Test name
Test status
Simulation time 2698719163 ps
CPU time 8.71 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:44 PM PDT 24
Peak memory 208924 kb
Host smart-7da90884-0c4d-4f4d-8e8f-e4600c3f696b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395238688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3395238688
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2861549401
Short name T882
Test name
Test status
Simulation time 581862382 ps
CPU time 4.09 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:42 PM PDT 24
Peak memory 210756 kb
Host smart-76cbd057-81c2-4247-abdc-94ed87973da2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861549401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2861549401
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4026875377
Short name T957
Test name
Test status
Simulation time 56097591 ps
CPU time 1.13 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:39 PM PDT 24
Peak memory 209516 kb
Host smart-58c4e72b-6c2f-41c2-81ae-75bef279f7f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026875377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4026875377
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2964077087
Short name T982
Test name
Test status
Simulation time 100755438 ps
CPU time 1.27 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 209692 kb
Host smart-755418a0-97d9-4efc-8417-16d7da0c8347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964077087 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2964077087
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2514966274
Short name T987
Test name
Test status
Simulation time 139323645 ps
CPU time 1.36 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 209280 kb
Host smart-1eade9f1-3e28-44ba-8af8-77ae706abafb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514966274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2514966274
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3790293622
Short name T120
Test name
Test status
Simulation time 184020598 ps
CPU time 5.06 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:40 PM PDT 24
Peak memory 217836 kb
Host smart-38c159c2-4841-41b8-b393-7151b9083d67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790293622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3790293622
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1944363864
Short name T935
Test name
Test status
Simulation time 44389629 ps
CPU time 1.9 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 221816 kb
Host smart-406de287-2a22-4d24-bdc0-148804b71177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944363864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1944363864
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1505791194
Short name T908
Test name
Test status
Simulation time 18795175 ps
CPU time 1.45 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 217840 kb
Host smart-9fcba540-3be5-4da5-905d-94190c21782f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505791194 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1505791194
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3056640411
Short name T890
Test name
Test status
Simulation time 20784767 ps
CPU time 0.96 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 209596 kb
Host smart-b2bbf00d-3051-4348-a9e5-deab721cd369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056640411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3056640411
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.690868051
Short name T938
Test name
Test status
Simulation time 158883433 ps
CPU time 1.43 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 209544 kb
Host smart-40b96f13-e50d-465d-a804-d244620eaf0c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690868051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.690868051
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2749125805
Short name T995
Test name
Test status
Simulation time 415268306 ps
CPU time 4.59 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:43 PM PDT 24
Peak memory 209376 kb
Host smart-30f7bcfd-e714-4a0f-bb4a-f324404d3244
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749125805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2749125805
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3160492636
Short name T941
Test name
Test status
Simulation time 4417109232 ps
CPU time 27.46 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:47:03 PM PDT 24
Peak memory 209648 kb
Host smart-5b110d8e-7714-467a-8f6a-5725aa2390d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160492636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3160492636
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.490678120
Short name T909
Test name
Test status
Simulation time 67676448 ps
CPU time 1.34 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 210972 kb
Host smart-4e994e99-9354-42da-8d1a-1ce6cbe0b8a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490678120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.490678120
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4091618345
Short name T135
Test name
Test status
Simulation time 392379199 ps
CPU time 1.86 seconds
Started Jul 18 06:46:33 PM PDT 24
Finished Jul 18 06:46:43 PM PDT 24
Peak memory 219336 kb
Host smart-d1759b5a-57d9-4f03-ba56-ff724d4ada57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409161
8345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4091618345
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3324231620
Short name T947
Test name
Test status
Simulation time 371147901 ps
CPU time 1.45 seconds
Started Jul 18 06:46:29 PM PDT 24
Finished Jul 18 06:46:40 PM PDT 24
Peak memory 209520 kb
Host smart-65804c12-0879-445b-93d6-30d9aa5652d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324231620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3324231620
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3053202931
Short name T145
Test name
Test status
Simulation time 27033697 ps
CPU time 1.44 seconds
Started Jul 18 06:46:23 PM PDT 24
Finished Jul 18 06:46:32 PM PDT 24
Peak memory 209208 kb
Host smart-b668be04-bea0-45cc-b3b3-167f27266147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053202931 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3053202931
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.857530425
Short name T111
Test name
Test status
Simulation time 15502559 ps
CPU time 0.96 seconds
Started Jul 18 06:46:26 PM PDT 24
Finished Jul 18 06:46:36 PM PDT 24
Peak memory 209596 kb
Host smart-8635dc13-237d-41f6-8ca1-0bf7e9fc7e80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857530425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.857530425
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.823181039
Short name T925
Test name
Test status
Simulation time 87658704 ps
CPU time 1.79 seconds
Started Jul 18 06:46:27 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 217888 kb
Host smart-476e0f48-3938-479c-9875-bb9a25b414e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823181039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.823181039
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3926516803
Short name T107
Test name
Test status
Simulation time 109017497 ps
CPU time 1.89 seconds
Started Jul 18 06:46:24 PM PDT 24
Finished Jul 18 06:46:34 PM PDT 24
Peak memory 222164 kb
Host smart-5770ef25-9714-4810-89ca-0a47b9ebb10a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926516803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3926516803
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.447863614
Short name T900
Test name
Test status
Simulation time 192812874 ps
CPU time 1.43 seconds
Started Jul 18 06:46:51 PM PDT 24
Finished Jul 18 06:46:55 PM PDT 24
Peak memory 217784 kb
Host smart-5e63ff1c-40bd-4579-82b1-d62850664091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447863614 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.447863614
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.79003659
Short name T981
Test name
Test status
Simulation time 12674337 ps
CPU time 0.84 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:46:59 PM PDT 24
Peak memory 209712 kb
Host smart-31337002-b25d-4362-8e58-02ace69dfde9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79003659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.79003659
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1588135872
Short name T959
Test name
Test status
Simulation time 14921479 ps
CPU time 1.11 seconds
Started Jul 18 06:46:42 PM PDT 24
Finished Jul 18 06:46:46 PM PDT 24
Peak memory 208220 kb
Host smart-85393eb7-6730-4e20-b066-f69b567b485c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588135872 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1588135872
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2246550949
Short name T946
Test name
Test status
Simulation time 371967367 ps
CPU time 5.59 seconds
Started Jul 18 06:46:41 PM PDT 24
Finished Jul 18 06:46:49 PM PDT 24
Peak memory 209364 kb
Host smart-251a3815-6dfc-4c77-b3c0-595f33f5c628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246550949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2246550949
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.581189104
Short name T918
Test name
Test status
Simulation time 695813621 ps
CPU time 8.07 seconds
Started Jul 18 06:46:57 PM PDT 24
Finished Jul 18 06:47:07 PM PDT 24
Peak memory 209664 kb
Host smart-43f2445a-766b-4a54-ad59-be322a2011ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581189104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.581189104
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1583540850
Short name T878
Test name
Test status
Simulation time 92337804 ps
CPU time 3.07 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 211432 kb
Host smart-45e9a366-6c35-442c-abed-cc1c0f98dbbd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583540850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1583540850
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1807071499
Short name T991
Test name
Test status
Simulation time 73852794 ps
CPU time 2.61 seconds
Started Jul 18 06:46:43 PM PDT 24
Finished Jul 18 06:46:49 PM PDT 24
Peak memory 217972 kb
Host smart-6f1b1982-82bf-45de-a5ed-384cd46f1e01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180707
1499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1807071499
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3175360721
Short name T990
Test name
Test status
Simulation time 55822052 ps
CPU time 1.56 seconds
Started Jul 18 06:46:51 PM PDT 24
Finished Jul 18 06:46:55 PM PDT 24
Peak memory 208576 kb
Host smart-7d504ece-8152-4b39-b3fd-403d8e9bee24
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175360721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3175360721
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2233958706
Short name T954
Test name
Test status
Simulation time 27334302 ps
CPU time 1.02 seconds
Started Jul 18 06:46:39 PM PDT 24
Finished Jul 18 06:46:43 PM PDT 24
Peak memory 209176 kb
Host smart-a7b770a8-56c2-460d-b940-a33f764d626f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233958706 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2233958706
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3413691436
Short name T881
Test name
Test status
Simulation time 150837858 ps
CPU time 1.3 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:52 PM PDT 24
Peak memory 211720 kb
Host smart-cc51765c-9a03-4984-a348-c481e27e916f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413691436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3413691436
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.520927818
Short name T906
Test name
Test status
Simulation time 134461912 ps
CPU time 2.48 seconds
Started Jul 18 06:46:55 PM PDT 24
Finished Jul 18 06:47:00 PM PDT 24
Peak memory 217892 kb
Host smart-7c20b212-44ee-457e-824a-a04804ec229b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520927818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.520927818
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2418537627
Short name T115
Test name
Test status
Simulation time 27368990 ps
CPU time 1.86 seconds
Started Jul 18 06:46:42 PM PDT 24
Finished Jul 18 06:46:47 PM PDT 24
Peak memory 223492 kb
Host smart-f3c522e0-8f1f-4003-b937-4a9c8aaf2484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418537627 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2418537627
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1054991621
Short name T988
Test name
Test status
Simulation time 11356858 ps
CPU time 0.99 seconds
Started Jul 18 06:46:43 PM PDT 24
Finished Jul 18 06:46:47 PM PDT 24
Peak memory 209368 kb
Host smart-aa2742d8-39cb-44dd-a707-53eb9e821ccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054991621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1054991621
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1138176268
Short name T896
Test name
Test status
Simulation time 332410817 ps
CPU time 2.53 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 209332 kb
Host smart-a9aadece-cc9f-4bc6-9fa9-1378f294fcd1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138176268 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1138176268
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2282074005
Short name T902
Test name
Test status
Simulation time 2057435730 ps
CPU time 12.96 seconds
Started Jul 18 06:46:39 PM PDT 24
Finished Jul 18 06:46:55 PM PDT 24
Peak memory 209376 kb
Host smart-24097cda-3d19-4936-be85-165054149fdd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282074005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2282074005
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1025338836
Short name T983
Test name
Test status
Simulation time 1041876828 ps
CPU time 8.58 seconds
Started Jul 18 06:46:39 PM PDT 24
Finished Jul 18 06:46:51 PM PDT 24
Peak memory 208804 kb
Host smart-93fd7d45-2770-4abb-a733-9f179d25c4a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025338836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1025338836
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2973866899
Short name T994
Test name
Test status
Simulation time 107553131 ps
CPU time 3.22 seconds
Started Jul 18 06:46:52 PM PDT 24
Finished Jul 18 06:46:57 PM PDT 24
Peak memory 211276 kb
Host smart-4afa086f-e6be-4571-b752-a484504ec885
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973866899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2973866899
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1239003980
Short name T136
Test name
Test status
Simulation time 75588657 ps
CPU time 2.61 seconds
Started Jul 18 06:46:47 PM PDT 24
Finished Jul 18 06:46:53 PM PDT 24
Peak memory 218000 kb
Host smart-ef3700e6-d498-4af2-80a6-bbc7214bfc3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123900
3980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1239003980
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3078267493
Short name T967
Test name
Test status
Simulation time 93565209 ps
CPU time 1.57 seconds
Started Jul 18 06:46:55 PM PDT 24
Finished Jul 18 06:46:57 PM PDT 24
Peak memory 209536 kb
Host smart-afe1b221-a711-431c-b045-fe0945604e9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078267493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3078267493
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.707009300
Short name T196
Test name
Test status
Simulation time 22087698 ps
CPU time 1.47 seconds
Started Jul 18 06:46:51 PM PDT 24
Finished Jul 18 06:46:55 PM PDT 24
Peak memory 211596 kb
Host smart-d8958487-d1ba-43dc-8c64-cdfe4ffa3f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707009300 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.707009300
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4171216385
Short name T202
Test name
Test status
Simulation time 124059477 ps
CPU time 1.43 seconds
Started Jul 18 06:46:55 PM PDT 24
Finished Jul 18 06:46:58 PM PDT 24
Peak memory 209624 kb
Host smart-8c584d13-7f91-4a6b-9288-de5bd30d686f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171216385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4171216385
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2594212749
Short name T110
Test name
Test status
Simulation time 77307531 ps
CPU time 2.1 seconds
Started Jul 18 06:46:51 PM PDT 24
Finished Jul 18 06:46:56 PM PDT 24
Peak memory 217952 kb
Host smart-96974fe3-7cd4-4f9e-9e0a-3602ad009f28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594212749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2594212749
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.601883293
Short name T933
Test name
Test status
Simulation time 81394650 ps
CPU time 1.42 seconds
Started Jul 18 06:46:38 PM PDT 24
Finished Jul 18 06:46:43 PM PDT 24
Peak memory 219868 kb
Host smart-e4aa5bbc-8c76-41f1-80bb-57424d5d81dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601883293 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.601883293
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.257257451
Short name T984
Test name
Test status
Simulation time 15980390 ps
CPU time 0.82 seconds
Started Jul 18 06:46:55 PM PDT 24
Finished Jul 18 06:46:57 PM PDT 24
Peak memory 209056 kb
Host smart-f613adbb-9abc-4e07-b8fe-564c2170a754
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257257451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.257257451
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2888433255
Short name T888
Test name
Test status
Simulation time 89841314 ps
CPU time 1.19 seconds
Started Jul 18 06:46:52 PM PDT 24
Finished Jul 18 06:46:55 PM PDT 24
Peak memory 208260 kb
Host smart-4e3d1f07-bdf7-4fbe-9ca0-fa2ef78c85cc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888433255 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2888433255
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1815415553
Short name T922
Test name
Test status
Simulation time 264183329 ps
CPU time 3.56 seconds
Started Jul 18 06:46:40 PM PDT 24
Finished Jul 18 06:46:46 PM PDT 24
Peak memory 209516 kb
Host smart-397c98d6-2615-40d8-87c1-4ab2b3deedb9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815415553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1815415553
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2186013044
Short name T985
Test name
Test status
Simulation time 835824004 ps
CPU time 19.49 seconds
Started Jul 18 06:46:42 PM PDT 24
Finished Jul 18 06:47:05 PM PDT 24
Peak memory 208988 kb
Host smart-5c518072-72f1-4b80-8bd5-da4639493990
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186013044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2186013044
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1492819227
Short name T970
Test name
Test status
Simulation time 126250392 ps
CPU time 3.47 seconds
Started Jul 18 06:46:52 PM PDT 24
Finished Jul 18 06:46:57 PM PDT 24
Peak memory 211272 kb
Host smart-e6025982-7045-45fd-841e-6ccbc3f7a146
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492819227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1492819227
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4202675175
Short name T972
Test name
Test status
Simulation time 53329458 ps
CPU time 1.47 seconds
Started Jul 18 06:46:44 PM PDT 24
Finished Jul 18 06:46:48 PM PDT 24
Peak memory 218952 kb
Host smart-fd3f31f6-b455-4238-bce5-0f7fff5a75b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420267
5175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4202675175
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.710675646
Short name T956
Test name
Test status
Simulation time 143963663 ps
CPU time 1.46 seconds
Started Jul 18 06:46:43 PM PDT 24
Finished Jul 18 06:46:48 PM PDT 24
Peak memory 209644 kb
Host smart-7e27437b-3350-45cf-af66-a96fa50f6174
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710675646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.710675646
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1875327472
Short name T112
Test name
Test status
Simulation time 36003122 ps
CPU time 1.68 seconds
Started Jul 18 06:46:43 PM PDT 24
Finished Jul 18 06:46:48 PM PDT 24
Peak memory 209700 kb
Host smart-de44561a-d7fc-4230-adf9-a284472b9cd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875327472 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1875327472
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2931307551
Short name T958
Test name
Test status
Simulation time 50691684 ps
CPU time 2.06 seconds
Started Jul 18 06:46:56 PM PDT 24
Finished Jul 18 06:47:00 PM PDT 24
Peak memory 209640 kb
Host smart-4d210bb3-6be0-4f66-b681-f991d5524df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931307551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2931307551
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1351057964
Short name T953
Test name
Test status
Simulation time 218199973 ps
CPU time 4.39 seconds
Started Jul 18 06:46:55 PM PDT 24
Finished Jul 18 06:47:01 PM PDT 24
Peak memory 217848 kb
Host smart-11fc1683-9150-4f41-aee6-c4bc27621e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351057964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1351057964
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.143220209
Short name T344
Test name
Test status
Simulation time 62346607 ps
CPU time 1.08 seconds
Started Jul 18 06:55:13 PM PDT 24
Finished Jul 18 06:55:15 PM PDT 24
Peak memory 209044 kb
Host smart-e83861b1-4b62-450c-8eec-49b781117bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143220209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.143220209
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2378208836
Short name T473
Test name
Test status
Simulation time 313116254 ps
CPU time 13.66 seconds
Started Jul 18 06:55:04 PM PDT 24
Finished Jul 18 06:55:22 PM PDT 24
Peak memory 226180 kb
Host smart-fed47473-f00d-4e32-a817-48d0548dd251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378208836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2378208836
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.443356505
Short name T641
Test name
Test status
Simulation time 447687491 ps
CPU time 3.68 seconds
Started Jul 18 06:54:56 PM PDT 24
Finished Jul 18 06:55:09 PM PDT 24
Peak memory 217764 kb
Host smart-22362378-c11a-4457-95a1-f563e17ffbda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443356505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.443356505
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1782028872
Short name T721
Test name
Test status
Simulation time 2104814432 ps
CPU time 63.02 seconds
Started Jul 18 06:54:56 PM PDT 24
Finished Jul 18 06:56:08 PM PDT 24
Peak memory 218340 kb
Host smart-bc866d0e-0a3a-4e9b-ae77-8033973ea7f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782028872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1782028872
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1058080515
Short name T309
Test name
Test status
Simulation time 1346819843 ps
CPU time 12.16 seconds
Started Jul 18 06:54:57 PM PDT 24
Finished Jul 18 06:55:18 PM PDT 24
Peak memory 217840 kb
Host smart-bbde2cc5-f3df-4b1d-9f55-22f03c23e769
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058080515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
058080515
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1334126480
Short name T251
Test name
Test status
Simulation time 376333206 ps
CPU time 11.26 seconds
Started Jul 18 06:54:57 PM PDT 24
Finished Jul 18 06:55:18 PM PDT 24
Peak memory 218380 kb
Host smart-43ffc547-5623-4391-ba99-9e6b83dea84f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334126480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1334126480
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.692629818
Short name T670
Test name
Test status
Simulation time 1493042656 ps
CPU time 18.99 seconds
Started Jul 18 06:55:11 PM PDT 24
Finished Jul 18 06:55:31 PM PDT 24
Peak memory 217704 kb
Host smart-b925bf92-9127-42e5-a9a0-f1c69fcaeb4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692629818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.692629818
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1497209033
Short name T693
Test name
Test status
Simulation time 123063193 ps
CPU time 2.51 seconds
Started Jul 18 06:54:56 PM PDT 24
Finished Jul 18 06:55:08 PM PDT 24
Peak memory 217704 kb
Host smart-78e0124a-3d1f-4e6b-a122-3df189637526
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497209033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1497209033
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1935190211
Short name T229
Test name
Test status
Simulation time 5973843107 ps
CPU time 45.6 seconds
Started Jul 18 06:55:04 PM PDT 24
Finished Jul 18 06:55:54 PM PDT 24
Peak memory 275724 kb
Host smart-86d33c9d-074e-404e-b8ee-52abb236da17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935190211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1935190211
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.856635229
Short name T455
Test name
Test status
Simulation time 4623725967 ps
CPU time 19.24 seconds
Started Jul 18 06:54:59 PM PDT 24
Finished Jul 18 06:55:26 PM PDT 24
Peak memory 226540 kb
Host smart-d69310c0-71f9-4c6e-b643-f256f82a72d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856635229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.856635229
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2743627862
Short name T731
Test name
Test status
Simulation time 28052565 ps
CPU time 2.08 seconds
Started Jul 18 06:54:57 PM PDT 24
Finished Jul 18 06:55:08 PM PDT 24
Peak memory 218544 kb
Host smart-d6365f75-5566-4034-b23b-4ee1dc79f106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743627862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2743627862
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2340728668
Short name T562
Test name
Test status
Simulation time 762836052 ps
CPU time 11.37 seconds
Started Jul 18 06:54:54 PM PDT 24
Finished Jul 18 06:55:15 PM PDT 24
Peak memory 214644 kb
Host smart-ad5c1877-2404-4c4c-a319-a611ff346079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340728668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2340728668
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1163433540
Short name T615
Test name
Test status
Simulation time 370675587 ps
CPU time 10.74 seconds
Started Jul 18 06:55:15 PM PDT 24
Finished Jul 18 06:55:28 PM PDT 24
Peak memory 219024 kb
Host smart-53fe54fa-1262-4229-b7f9-13d578b49152
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163433540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1163433540
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4034520346
Short name T598
Test name
Test status
Simulation time 971191262 ps
CPU time 12.55 seconds
Started Jul 18 06:55:13 PM PDT 24
Finished Jul 18 06:55:26 PM PDT 24
Peak memory 218280 kb
Host smart-937760b1-4a72-434d-a2eb-b6e77f8f1233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034520346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.4034520346
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.764757085
Short name T637
Test name
Test status
Simulation time 1216265417 ps
CPU time 6.36 seconds
Started Jul 18 06:55:12 PM PDT 24
Finished Jul 18 06:55:20 PM PDT 24
Peak memory 218308 kb
Host smart-345fac77-292e-4c5e-95af-2d42375619bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764757085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.764757085
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.762457388
Short name T614
Test name
Test status
Simulation time 984533549 ps
CPU time 16.6 seconds
Started Jul 18 06:54:56 PM PDT 24
Finished Jul 18 06:55:22 PM PDT 24
Peak memory 226312 kb
Host smart-c5b381ef-f5a9-4897-905b-518624f75294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762457388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.762457388
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.159348559
Short name T859
Test name
Test status
Simulation time 34347372 ps
CPU time 2.28 seconds
Started Jul 18 06:54:57 PM PDT 24
Finished Jul 18 06:55:08 PM PDT 24
Peak memory 214420 kb
Host smart-d98a590e-b673-4c0b-92e9-5fae6fc5c2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159348559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.159348559
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3717701520
Short name T639
Test name
Test status
Simulation time 441494119 ps
CPU time 17.36 seconds
Started Jul 18 06:55:03 PM PDT 24
Finished Jul 18 06:55:25 PM PDT 24
Peak memory 251120 kb
Host smart-1f930eb8-d498-4897-806c-6a651b62a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717701520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3717701520
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.4040907274
Short name T741
Test name
Test status
Simulation time 91012566 ps
CPU time 7.19 seconds
Started Jul 18 06:54:56 PM PDT 24
Finished Jul 18 06:55:12 PM PDT 24
Peak memory 251188 kb
Host smart-08b9d7a6-9a96-4f93-bd5a-1a77b1644348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040907274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.4040907274
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2470876082
Short name T318
Test name
Test status
Simulation time 1619997529 ps
CPU time 57.22 seconds
Started Jul 18 06:55:12 PM PDT 24
Finished Jul 18 06:56:11 PM PDT 24
Peak memory 251128 kb
Host smart-a87640ec-b295-4025-98e1-4f0e7deeca28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470876082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2470876082
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1962160363
Short name T405
Test name
Test status
Simulation time 51062608 ps
CPU time 0.81 seconds
Started Jul 18 06:54:56 PM PDT 24
Finished Jul 18 06:55:06 PM PDT 24
Peak memory 211940 kb
Host smart-210da5be-f62d-4fef-b0dd-a1605b09a6a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962160363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1962160363
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2064883414
Short name T687
Test name
Test status
Simulation time 20985160 ps
CPU time 0.95 seconds
Started Jul 18 06:55:12 PM PDT 24
Finished Jul 18 06:55:14 PM PDT 24
Peak memory 208960 kb
Host smart-aa1dfd98-f9f5-4014-ac86-4a7d74e020c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064883414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2064883414
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2234342130
Short name T633
Test name
Test status
Simulation time 20698330 ps
CPU time 0.83 seconds
Started Jul 18 06:55:16 PM PDT 24
Finished Jul 18 06:55:20 PM PDT 24
Peak memory 209100 kb
Host smart-9eafeca0-c32b-43d6-a18f-cf6d09c21203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234342130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2234342130
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3384461822
Short name T573
Test name
Test status
Simulation time 2490294314 ps
CPU time 23.35 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:39 PM PDT 24
Peak memory 219096 kb
Host smart-1322ebdc-2e6f-4aab-814d-fb497ae4f9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384461822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3384461822
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2345150281
Short name T522
Test name
Test status
Simulation time 68901649 ps
CPU time 2.75 seconds
Started Jul 18 06:55:16 PM PDT 24
Finished Jul 18 06:55:22 PM PDT 24
Peak memory 217156 kb
Host smart-4c801bef-a3e7-430a-81f3-cbc8958a6db0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345150281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2345150281
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.9676177
Short name T501
Test name
Test status
Simulation time 2951458775 ps
CPU time 80.14 seconds
Started Jul 18 06:55:09 PM PDT 24
Finished Jul 18 06:56:31 PM PDT 24
Peak memory 218372 kb
Host smart-c9b72d01-c63b-4988-bb08-fca747f7dd9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9676177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_error
s.9676177
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3706068849
Short name T24
Test name
Test status
Simulation time 820032980 ps
CPU time 5.42 seconds
Started Jul 18 06:55:13 PM PDT 24
Finished Jul 18 06:55:20 PM PDT 24
Peak memory 217844 kb
Host smart-2ac0fc9b-1c69-414d-a7d3-55250066b9cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706068849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
706068849
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3800106148
Short name T4
Test name
Test status
Simulation time 253146635 ps
CPU time 2.94 seconds
Started Jul 18 06:55:09 PM PDT 24
Finished Jul 18 06:55:13 PM PDT 24
Peak memory 218308 kb
Host smart-2407c49c-128f-4705-b125-004dba8fbe1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800106148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3800106148
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1325025442
Short name T516
Test name
Test status
Simulation time 976886723 ps
CPU time 27.63 seconds
Started Jul 18 06:55:09 PM PDT 24
Finished Jul 18 06:55:38 PM PDT 24
Peak memory 217612 kb
Host smart-7cf43e7d-ae7b-44e5-ae54-14c932400b86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325025442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1325025442
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2100148752
Short name T278
Test name
Test status
Simulation time 441809925 ps
CPU time 2.17 seconds
Started Jul 18 06:55:12 PM PDT 24
Finished Jul 18 06:55:15 PM PDT 24
Peak memory 217688 kb
Host smart-92b6f5b8-12e2-4f44-9aad-28b98da02188
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100148752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2100148752
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.282397956
Short name T25
Test name
Test status
Simulation time 1563670083 ps
CPU time 66.51 seconds
Started Jul 18 06:55:11 PM PDT 24
Finished Jul 18 06:56:19 PM PDT 24
Peak memory 275716 kb
Host smart-1c3d256b-1509-4001-8b7b-3aba4420521f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282397956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.282397956
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2428862549
Short name T728
Test name
Test status
Simulation time 1495628073 ps
CPU time 12.15 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:27 PM PDT 24
Peak memory 223156 kb
Host smart-df8871eb-8a57-47a2-bed7-c4ae3a18b994
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428862549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2428862549
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.995814441
Short name T487
Test name
Test status
Simulation time 39702040 ps
CPU time 2.03 seconds
Started Jul 18 06:55:10 PM PDT 24
Finished Jul 18 06:55:13 PM PDT 24
Peak memory 218440 kb
Host smart-2e143f21-5760-4ebf-a901-ce1ec6df0c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995814441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.995814441
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.706378358
Short name T678
Test name
Test status
Simulation time 1510099306 ps
CPU time 11.5 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:28 PM PDT 24
Peak memory 214780 kb
Host smart-4a71a521-0ed2-46ed-b182-a5134cb542f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706378358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.706378358
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.543028169
Short name T50
Test name
Test status
Simulation time 245119715 ps
CPU time 23.14 seconds
Started Jul 18 06:55:10 PM PDT 24
Finished Jul 18 06:55:34 PM PDT 24
Peak memory 269460 kb
Host smart-d27bcbf5-1784-427a-b180-5ca999bab41f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543028169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.543028169
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4136673024
Short name T259
Test name
Test status
Simulation time 4833955147 ps
CPU time 9.96 seconds
Started Jul 18 06:55:16 PM PDT 24
Finished Jul 18 06:55:29 PM PDT 24
Peak memory 219476 kb
Host smart-b8c800e6-4556-4af9-b325-5b72cfe2ac52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136673024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4136673024
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2454831979
Short name T843
Test name
Test status
Simulation time 751136401 ps
CPU time 13.98 seconds
Started Jul 18 06:55:16 PM PDT 24
Finished Jul 18 06:55:32 PM PDT 24
Peak memory 226100 kb
Host smart-4d7e5e4a-5437-4ccd-b3bb-da651ff4f524
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454831979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2454831979
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.13197354
Short name T337
Test name
Test status
Simulation time 580702110 ps
CPU time 8.48 seconds
Started Jul 18 06:55:12 PM PDT 24
Finished Jul 18 06:55:22 PM PDT 24
Peak memory 218320 kb
Host smart-10b9e1bd-339a-49bc-91fc-0def411221c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.13197354
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2418717643
Short name T552
Test name
Test status
Simulation time 843542876 ps
CPU time 9.38 seconds
Started Jul 18 06:55:11 PM PDT 24
Finished Jul 18 06:55:21 PM PDT 24
Peak memory 225276 kb
Host smart-91be4c33-c63d-4070-904f-72a22d73cc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418717643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2418717643
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.964941279
Short name T740
Test name
Test status
Simulation time 50424163 ps
CPU time 3.02 seconds
Started Jul 18 06:55:12 PM PDT 24
Finished Jul 18 06:55:17 PM PDT 24
Peak memory 214800 kb
Host smart-0c9b80cb-1e4b-4350-9fef-7698bbdfbaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964941279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.964941279
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1049050757
Short name T260
Test name
Test status
Simulation time 697184057 ps
CPU time 21.21 seconds
Started Jul 18 06:55:12 PM PDT 24
Finished Jul 18 06:55:35 PM PDT 24
Peak memory 246108 kb
Host smart-3913ff46-746b-4d0a-9b74-c8545c5c0efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049050757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1049050757
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1917946108
Short name T595
Test name
Test status
Simulation time 57888099 ps
CPU time 7.09 seconds
Started Jul 18 06:55:10 PM PDT 24
Finished Jul 18 06:55:18 PM PDT 24
Peak memory 246716 kb
Host smart-2dc64bac-3fe7-468d-872a-5501aefdae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917946108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1917946108
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2317507624
Short name T162
Test name
Test status
Simulation time 43192688213 ps
CPU time 230.83 seconds
Started Jul 18 06:55:11 PM PDT 24
Finished Jul 18 06:59:03 PM PDT 24
Peak memory 283960 kb
Host smart-a2e6d8b4-95b6-41e2-a755-eea126bb5e1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2317507624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2317507624
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2241403612
Short name T803
Test name
Test status
Simulation time 16229208 ps
CPU time 0.97 seconds
Started Jul 18 06:55:16 PM PDT 24
Finished Jul 18 06:55:19 PM PDT 24
Peak memory 217764 kb
Host smart-1856f581-491a-400f-ad1b-e1615c051849
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241403612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2241403612
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.205722585
Short name T340
Test name
Test status
Simulation time 57742748 ps
CPU time 1.06 seconds
Started Jul 18 06:55:55 PM PDT 24
Finished Jul 18 06:56:03 PM PDT 24
Peak memory 209088 kb
Host smart-787ee469-a9fd-4adb-9dee-e1386b0e1868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205722585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.205722585
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.4007650965
Short name T725
Test name
Test status
Simulation time 701089034 ps
CPU time 9.39 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:06 PM PDT 24
Peak memory 226084 kb
Host smart-216a4bc8-edd0-48f9-9766-941f9cd8daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007650965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.4007650965
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3886043509
Short name T159
Test name
Test status
Simulation time 350145819 ps
CPU time 4.71 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:56:00 PM PDT 24
Peak memory 217164 kb
Host smart-33218b92-c9ac-422c-a40a-e305cf49ce51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886043509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3886043509
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1947590339
Short name T408
Test name
Test status
Simulation time 3665212805 ps
CPU time 50.2 seconds
Started Jul 18 06:55:46 PM PDT 24
Finished Jul 18 06:56:41 PM PDT 24
Peak memory 218368 kb
Host smart-dd9e9757-157f-496f-9e1c-2c88f5c8afe9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947590339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1947590339
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2206936450
Short name T542
Test name
Test status
Simulation time 211062859 ps
CPU time 3.44 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:55:58 PM PDT 24
Peak memory 218296 kb
Host smart-78e24f06-03c1-4ef1-ba3d-9e87f7b64f7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206936450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2206936450
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2920671764
Short name T797
Test name
Test status
Simulation time 261597285 ps
CPU time 1.85 seconds
Started Jul 18 06:55:46 PM PDT 24
Finished Jul 18 06:55:53 PM PDT 24
Peak memory 217776 kb
Host smart-f5c32e0c-a276-4dc7-83b8-e170ee123365
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920671764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2920671764
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1326760235
Short name T170
Test name
Test status
Simulation time 41562190465 ps
CPU time 99.12 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:57:32 PM PDT 24
Peak memory 279084 kb
Host smart-5168ccbf-f69f-4936-a350-65c38890f5e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326760235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1326760235
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2630216389
Short name T638
Test name
Test status
Simulation time 346606906 ps
CPU time 16.09 seconds
Started Jul 18 06:55:51 PM PDT 24
Finished Jul 18 06:56:14 PM PDT 24
Peak memory 242872 kb
Host smart-629ac37b-36d4-4ee9-a72a-4f075aeaff34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630216389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2630216389
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2413739071
Short name T767
Test name
Test status
Simulation time 29629605 ps
CPU time 1.63 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:55:55 PM PDT 24
Peak memory 218372 kb
Host smart-f1a8a2d8-efab-4c51-84fe-30bfb8d949dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413739071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2413739071
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1376576409
Short name T468
Test name
Test status
Simulation time 633170190 ps
CPU time 8.71 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:56:10 PM PDT 24
Peak memory 226052 kb
Host smart-44fe8fc2-3074-4cc9-8e68-ad3dfdea7be9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376576409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1376576409
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2027559862
Short name T395
Test name
Test status
Simulation time 1067618387 ps
CPU time 11.6 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:09 PM PDT 24
Peak memory 226188 kb
Host smart-9bbfac2a-8bd7-460f-a352-c524f5bdea06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027559862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2027559862
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1245470641
Short name T642
Test name
Test status
Simulation time 293856776 ps
CPU time 8.47 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:55:59 PM PDT 24
Peak memory 218596 kb
Host smart-d1f990a5-cb35-4e81-b63b-cd2c50231fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245470641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1245470641
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.948417928
Short name T80
Test name
Test status
Simulation time 62375601 ps
CPU time 2.9 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:55:58 PM PDT 24
Peak memory 215112 kb
Host smart-246f5f80-4be8-48ed-adaa-2f2779717588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948417928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.948417928
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1487813580
Short name T394
Test name
Test status
Simulation time 253413555 ps
CPU time 32.43 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:56:33 PM PDT 24
Peak memory 251068 kb
Host smart-05034a18-7b8f-46e0-a013-862306d5bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487813580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1487813580
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1213882672
Short name T584
Test name
Test status
Simulation time 403899890 ps
CPU time 7.41 seconds
Started Jul 18 06:55:49 PM PDT 24
Finished Jul 18 06:56:02 PM PDT 24
Peak memory 251112 kb
Host smart-c7332d7c-22b6-4a87-9533-cddffbe7d9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213882672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1213882672
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2151813075
Short name T404
Test name
Test status
Simulation time 8968620365 ps
CPU time 138.87 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 277924 kb
Host smart-338e311a-b033-4b18-97c9-b80d1a53ed46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151813075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2151813075
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3815422403
Short name T381
Test name
Test status
Simulation time 17318610 ps
CPU time 0.93 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:55:50 PM PDT 24
Peak memory 211976 kb
Host smart-def8b9a8-0068-4ae8-8797-7ba257734600
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815422403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3815422403
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.476368052
Short name T332
Test name
Test status
Simulation time 18179115 ps
CPU time 1.14 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:56:14 PM PDT 24
Peak memory 208980 kb
Host smart-89231a92-dc71-4fb7-84d9-7eb4589cba7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476368052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.476368052
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3112552706
Short name T566
Test name
Test status
Simulation time 3828247478 ps
CPU time 12.12 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:28 PM PDT 24
Peak memory 219092 kb
Host smart-ed3b29f2-6f8a-4092-8951-ad444aed484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112552706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3112552706
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3128759669
Short name T764
Test name
Test status
Simulation time 288666115 ps
CPU time 5.58 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:56:19 PM PDT 24
Peak memory 217696 kb
Host smart-e50492fc-deef-41cd-abc7-aec62a2b8273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128759669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3128759669
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1270190454
Short name T307
Test name
Test status
Simulation time 855748412 ps
CPU time 4.1 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 222980 kb
Host smart-71e0d1c2-1b96-4d71-bcdc-5535ea32109d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270190454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1270190454
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.112554762
Short name T94
Test name
Test status
Simulation time 2044436959 ps
CPU time 8.22 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:24 PM PDT 24
Peak memory 217712 kb
Host smart-ae813eab-7e73-440d-91ee-58066b94bf6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112554762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
112554762
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2626488950
Short name T245
Test name
Test status
Simulation time 6167403070 ps
CPU time 73.42 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:57:29 PM PDT 24
Peak memory 277664 kb
Host smart-16cdce77-2a1d-42f7-ac48-9c83704148ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626488950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2626488950
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3428080738
Short name T748
Test name
Test status
Simulation time 462616562 ps
CPU time 7.36 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:23 PM PDT 24
Peak memory 224064 kb
Host smart-1f90cf51-2f6c-445e-bd18-906451168363
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428080738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3428080738
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2181763386
Short name T19
Test name
Test status
Simulation time 990678457 ps
CPU time 3.32 seconds
Started Jul 18 06:56:05 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 222752 kb
Host smart-d4eb4ccb-3ed8-44db-b5ae-c9f6d50cd69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181763386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2181763386
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3191432579
Short name T465
Test name
Test status
Simulation time 2155844830 ps
CPU time 13.07 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 226228 kb
Host smart-34b2d971-9c14-4e33-8576-c0976cbc3da2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191432579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3191432579
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2963795616
Short name T56
Test name
Test status
Simulation time 810508866 ps
CPU time 10.89 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:25 PM PDT 24
Peak memory 226092 kb
Host smart-e25ca160-3f45-4e14-b77e-5439b085e9bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963795616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2963795616
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3335239186
Short name T576
Test name
Test status
Simulation time 288452532 ps
CPU time 10.19 seconds
Started Jul 18 06:56:01 PM PDT 24
Finished Jul 18 06:56:21 PM PDT 24
Peak memory 226104 kb
Host smart-73eb153a-c4a2-4dc5-a214-28b9f67e70dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335239186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3335239186
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3968900904
Short name T46
Test name
Test status
Simulation time 603615399 ps
CPU time 14.68 seconds
Started Jul 18 06:56:09 PM PDT 24
Finished Jul 18 06:56:32 PM PDT 24
Peak memory 226180 kb
Host smart-2aac38b2-647a-4ec0-b40b-d6f3437f411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968900904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3968900904
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.159561691
Short name T529
Test name
Test status
Simulation time 1017754099 ps
CPU time 3.06 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:56:04 PM PDT 24
Peak memory 217780 kb
Host smart-bfc5f2bf-32f0-4c36-bf5c-60f3a122f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159561691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.159561691
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4007068576
Short name T247
Test name
Test status
Simulation time 1231453684 ps
CPU time 23.29 seconds
Started Jul 18 06:55:59 PM PDT 24
Finished Jul 18 06:56:31 PM PDT 24
Peak memory 251088 kb
Host smart-05c0c125-b4ec-41f6-87fa-1d7c20ebb15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007068576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4007068576
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3519104116
Short name T397
Test name
Test status
Simulation time 419304620 ps
CPU time 7.69 seconds
Started Jul 18 06:56:07 PM PDT 24
Finished Jul 18 06:56:24 PM PDT 24
Peak memory 251116 kb
Host smart-114fe68b-3bd0-4d59-84fb-04c973578ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519104116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3519104116
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3909840314
Short name T657
Test name
Test status
Simulation time 4856030785 ps
CPU time 198.59 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:59:32 PM PDT 24
Peak memory 250940 kb
Host smart-cb0a4106-e282-4822-badc-4ffd302b7c5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909840314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3909840314
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.626893637
Short name T829
Test name
Test status
Simulation time 34976737 ps
CPU time 0.91 seconds
Started Jul 18 06:55:55 PM PDT 24
Finished Jul 18 06:56:03 PM PDT 24
Peak memory 211920 kb
Host smart-7ef8bfa1-a38e-47f2-9042-56c8c6f96458
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626893637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.626893637
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.345985644
Short name T548
Test name
Test status
Simulation time 20594166 ps
CPU time 1.1 seconds
Started Jul 18 06:56:13 PM PDT 24
Finished Jul 18 06:56:21 PM PDT 24
Peak memory 208992 kb
Host smart-79d2fa1e-4c78-4438-b59a-013494504fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345985644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.345985644
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1975990376
Short name T459
Test name
Test status
Simulation time 466434133 ps
CPU time 13.76 seconds
Started Jul 18 06:56:01 PM PDT 24
Finished Jul 18 06:56:25 PM PDT 24
Peak memory 218376 kb
Host smart-d59acf13-6854-4741-9627-25b3672d2d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975990376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1975990376
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.319712148
Short name T494
Test name
Test status
Simulation time 322229920 ps
CPU time 8.48 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:25 PM PDT 24
Peak memory 217316 kb
Host smart-eb7939fa-5c77-462f-987c-c8edb879d1c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319712148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.319712148
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4016843501
Short name T403
Test name
Test status
Simulation time 981084456 ps
CPU time 31.37 seconds
Started Jul 18 06:56:13 PM PDT 24
Finished Jul 18 06:56:51 PM PDT 24
Peak memory 218296 kb
Host smart-f3ca085e-a13d-450f-a62e-383c9b89a436
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016843501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4016843501
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3870407771
Short name T317
Test name
Test status
Simulation time 284318325 ps
CPU time 9.65 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:24 PM PDT 24
Peak memory 218200 kb
Host smart-1da0a2a8-5e03-4732-b100-94e3a958baab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870407771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3870407771
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.604597375
Short name T295
Test name
Test status
Simulation time 194549861 ps
CPU time 4.55 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 217644 kb
Host smart-a156028d-472b-477e-bb38-beec725c559d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604597375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
604597375
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3045579830
Short name T226
Test name
Test status
Simulation time 5491557263 ps
CPU time 38.53 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:52 PM PDT 24
Peak memory 271716 kb
Host smart-add4e7aa-616e-4c5b-9307-e34a74add40e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045579830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3045579830
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2813173647
Short name T308
Test name
Test status
Simulation time 1061661424 ps
CPU time 33.75 seconds
Started Jul 18 06:56:07 PM PDT 24
Finished Jul 18 06:56:50 PM PDT 24
Peak memory 251068 kb
Host smart-175a2bd9-9aa8-43f1-ab3c-09a028bf4171
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813173647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2813173647
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2457034623
Short name T705
Test name
Test status
Simulation time 60615597 ps
CPU time 3.42 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:17 PM PDT 24
Peak memory 218384 kb
Host smart-4d62022f-c679-40db-a673-c064da003edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457034623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2457034623
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2140520094
Short name T64
Test name
Test status
Simulation time 1729740596 ps
CPU time 8.78 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:56:22 PM PDT 24
Peak memory 219020 kb
Host smart-b94b6daa-ab4c-4289-b633-7c37e0c99a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140520094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2140520094
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.4126583034
Short name T234
Test name
Test status
Simulation time 525245861 ps
CPU time 7.39 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:56:20 PM PDT 24
Peak memory 226152 kb
Host smart-240d30c8-d435-4123-b770-fdf56e5702ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126583034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.4126583034
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.565305802
Short name T310
Test name
Test status
Simulation time 407195636 ps
CPU time 11.15 seconds
Started Jul 18 06:56:02 PM PDT 24
Finished Jul 18 06:56:23 PM PDT 24
Peak memory 226112 kb
Host smart-d3e13c97-e7a7-42f5-b17e-773e8797b7dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565305802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.565305802
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3105633743
Short name T791
Test name
Test status
Simulation time 751553543 ps
CPU time 9.19 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:22 PM PDT 24
Peak memory 226172 kb
Host smart-2f8f4881-7cdc-42d9-a50b-8b4b3ad2a930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105633743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3105633743
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.148492342
Short name T65
Test name
Test status
Simulation time 31964315 ps
CPU time 2.21 seconds
Started Jul 18 06:56:02 PM PDT 24
Finished Jul 18 06:56:14 PM PDT 24
Peak memory 214956 kb
Host smart-a05b4ce9-1daf-4bbc-9a90-7ccba35fc9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148492342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.148492342
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.379151237
Short name T161
Test name
Test status
Simulation time 2470902526 ps
CPU time 24.69 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:41 PM PDT 24
Peak memory 251140 kb
Host smart-1ecb04ab-9ee8-4789-a711-13acdfda2aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379151237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.379151237
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.649427176
Short name T388
Test name
Test status
Simulation time 183613537 ps
CPU time 8.4 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:24 PM PDT 24
Peak memory 245144 kb
Host smart-0c24b56d-734b-45c6-9063-47a6130716a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649427176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.649427176
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2051363167
Short name T180
Test name
Test status
Simulation time 3482019934 ps
CPU time 33.12 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 217704 kb
Host smart-576d7eaa-220c-4a1e-bbae-267f2c36a05c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051363167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2051363167
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2004742208
Short name T812
Test name
Test status
Simulation time 407627337138 ps
CPU time 932.74 seconds
Started Jul 18 06:56:05 PM PDT 24
Finished Jul 18 07:11:48 PM PDT 24
Peak memory 373152 kb
Host smart-889e171d-4291-4368-adcc-01e69f931f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2004742208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2004742208
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.63693880
Short name T370
Test name
Test status
Simulation time 13829469 ps
CPU time 1.09 seconds
Started Jul 18 06:56:02 PM PDT 24
Finished Jul 18 06:56:13 PM PDT 24
Peak memory 211936 kb
Host smart-eb69e212-dd26-418c-94ef-04fc1d20e784
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63693880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_volatile_unlock_smoke.63693880
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3691638382
Short name T847
Test name
Test status
Simulation time 23047162 ps
CPU time 0.96 seconds
Started Jul 18 06:56:08 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 209040 kb
Host smart-681c8c82-3b9a-49b3-bd62-56da247a6528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691638382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3691638382
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1824627637
Short name T816
Test name
Test status
Simulation time 822442261 ps
CPU time 12.09 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:56:25 PM PDT 24
Peak memory 218552 kb
Host smart-56484da0-f145-4da3-b95e-129c451bbaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824627637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1824627637
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4194966492
Short name T795
Test name
Test status
Simulation time 2601475756 ps
CPU time 4.77 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 217588 kb
Host smart-fc0b09a6-444c-4839-9e64-e6de387235df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194966492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4194966492
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.70376730
Short name T605
Test name
Test status
Simulation time 3139192652 ps
CPU time 51.97 seconds
Started Jul 18 06:56:08 PM PDT 24
Finished Jul 18 06:57:09 PM PDT 24
Peak memory 218312 kb
Host smart-05921c29-adda-47f4-8f7b-446a295d022f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70376730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_err
ors.70376730
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2579457183
Short name T97
Test name
Test status
Simulation time 1763298572 ps
CPU time 7.92 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:21 PM PDT 24
Peak memory 224364 kb
Host smart-9d04619e-a0a0-4c78-bf4b-80a98ba2483c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579457183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2579457183
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2701757147
Short name T76
Test name
Test status
Simulation time 383283558 ps
CPU time 10.07 seconds
Started Jul 18 06:56:05 PM PDT 24
Finished Jul 18 06:56:25 PM PDT 24
Peak memory 217720 kb
Host smart-d9e856fe-88da-4acd-a4e2-4acfc3c62a1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701757147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2701757147
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.204204750
Short name T402
Test name
Test status
Simulation time 782924843 ps
CPU time 42.63 seconds
Started Jul 18 06:56:08 PM PDT 24
Finished Jul 18 06:57:00 PM PDT 24
Peak memory 251064 kb
Host smart-8635cb90-67f1-440c-9de3-878166c5d8c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204204750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.204204750
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.4082534498
Short name T860
Test name
Test status
Simulation time 6718604167 ps
CPU time 7.89 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:24 PM PDT 24
Peak memory 225488 kb
Host smart-a2be25b8-da87-4bde-ab6e-31ee99eb2672
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082534498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.4082534498
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3815400743
Short name T419
Test name
Test status
Simulation time 60516980 ps
CPU time 2.59 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 222464 kb
Host smart-08799605-5333-4d05-bd0d-4dedf40d401a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815400743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3815400743
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1747222368
Short name T622
Test name
Test status
Simulation time 431735325 ps
CPU time 10.12 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:26 PM PDT 24
Peak memory 226104 kb
Host smart-7ea1fe53-4a12-4540-9d15-6c36555b839b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747222368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1747222368
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3910758272
Short name T237
Test name
Test status
Simulation time 485840488 ps
CPU time 9.67 seconds
Started Jul 18 06:56:03 PM PDT 24
Finished Jul 18 06:56:23 PM PDT 24
Peak memory 218320 kb
Host smart-b3d3a260-341b-46af-bffd-896536dd05f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910758272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3910758272
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.658358594
Short name T644
Test name
Test status
Simulation time 63094071 ps
CPU time 2.45 seconds
Started Jul 18 06:56:00 PM PDT 24
Finished Jul 18 06:56:12 PM PDT 24
Peak memory 214476 kb
Host smart-2a83a5f2-2843-45e5-9663-d9cbb13d4575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658358594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.658358594
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1762217124
Short name T335
Test name
Test status
Simulation time 447266650 ps
CPU time 25.78 seconds
Started Jul 18 06:56:12 PM PDT 24
Finished Jul 18 06:56:45 PM PDT 24
Peak memory 251100 kb
Host smart-6e47ac11-8e62-4f54-8323-c9295fb6f11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762217124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1762217124
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.414163281
Short name T664
Test name
Test status
Simulation time 69665041 ps
CPU time 8.14 seconds
Started Jul 18 06:56:05 PM PDT 24
Finished Jul 18 06:56:24 PM PDT 24
Peak memory 251116 kb
Host smart-881bf1e1-5da7-49f0-a922-af4e09de7471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414163281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.414163281
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.60678419
Short name T422
Test name
Test status
Simulation time 1762532660 ps
CPU time 62.02 seconds
Started Jul 18 06:56:05 PM PDT 24
Finished Jul 18 06:57:16 PM PDT 24
Peak memory 251592 kb
Host smart-febfbe5a-9ed9-4bf8-8c4d-e224742a43c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60678419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.lc_ctrl_stress_all.60678419
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3863795993
Short name T756
Test name
Test status
Simulation time 15527999669 ps
CPU time 497.39 seconds
Started Jul 18 06:56:08 PM PDT 24
Finished Jul 18 07:04:34 PM PDT 24
Peak memory 267700 kb
Host smart-659d731e-21f0-4ccc-8485-0deda66f2c08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3863795993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3863795993
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2789862043
Short name T173
Test name
Test status
Simulation time 121315361 ps
CPU time 0.86 seconds
Started Jul 18 06:56:12 PM PDT 24
Finished Jul 18 06:56:19 PM PDT 24
Peak memory 211936 kb
Host smart-fc17fa8d-852a-4d72-9b07-79662d863b33
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789862043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2789862043
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.925828990
Short name T515
Test name
Test status
Simulation time 39707599 ps
CPU time 1.02 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:26 PM PDT 24
Peak memory 208960 kb
Host smart-aff99388-f803-4b44-bf85-5472c7562e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925828990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.925828990
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1341843366
Short name T674
Test name
Test status
Simulation time 339177940 ps
CPU time 10.86 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:27 PM PDT 24
Peak memory 218372 kb
Host smart-c4b21f14-bc9f-47c2-9533-9bd7962b6e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341843366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1341843366
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1351346686
Short name T182
Test name
Test status
Simulation time 839955998 ps
CPU time 12.07 seconds
Started Jul 18 07:04:21 PM PDT 24
Finished Jul 18 07:04:38 PM PDT 24
Peak memory 217608 kb
Host smart-a0cdb919-f4db-4037-ad7a-c6f79b8461a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351346686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1351346686
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1359533736
Short name T620
Test name
Test status
Simulation time 1284548786 ps
CPU time 40.95 seconds
Started Jul 18 06:56:18 PM PDT 24
Finished Jul 18 06:57:05 PM PDT 24
Peak memory 218392 kb
Host smart-7575fe53-415f-411b-a9fe-0db2e022ab61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359533736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1359533736
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3593951541
Short name T498
Test name
Test status
Simulation time 754604044 ps
CPU time 3.9 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 218304 kb
Host smart-123f69d6-9fb5-4940-bcec-1e38f40697ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593951541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3593951541
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1537406107
Short name T453
Test name
Test status
Simulation time 389900597 ps
CPU time 4.47 seconds
Started Jul 18 06:56:04 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 217804 kb
Host smart-4cc2ae57-1ea9-4d82-ba6a-1b22fbd757e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537406107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1537406107
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1213522477
Short name T95
Test name
Test status
Simulation time 7432104851 ps
CPU time 25.66 seconds
Started Jul 18 06:56:01 PM PDT 24
Finished Jul 18 06:56:37 PM PDT 24
Peak memory 251108 kb
Host smart-e9d7f609-17e9-4be8-a429-b8fe5e61003e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213522477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1213522477
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.356966298
Short name T570
Test name
Test status
Simulation time 541129638 ps
CPU time 10.01 seconds
Started Jul 18 06:56:17 PM PDT 24
Finished Jul 18 06:56:32 PM PDT 24
Peak memory 224348 kb
Host smart-2b3f1764-f585-43c1-8069-b93fdab40bb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356966298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.356966298
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2011877935
Short name T836
Test name
Test status
Simulation time 360407465 ps
CPU time 3.6 seconds
Started Jul 18 06:56:12 PM PDT 24
Finished Jul 18 06:56:22 PM PDT 24
Peak memory 222800 kb
Host smart-bd9abbb6-9932-4e74-80fe-994c1df11849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011877935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2011877935
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1591242243
Short name T482
Test name
Test status
Simulation time 599489671 ps
CPU time 15.72 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:44 PM PDT 24
Peak memory 219056 kb
Host smart-11593b48-2d72-435d-b854-596ad11a506a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591242243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1591242243
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3571548604
Short name T561
Test name
Test status
Simulation time 299920929 ps
CPU time 12.56 seconds
Started Jul 18 06:56:18 PM PDT 24
Finished Jul 18 06:56:36 PM PDT 24
Peak memory 226172 kb
Host smart-c69f5e01-4a4f-484c-bf0b-ef10a26fddbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571548604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3571548604
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.545488594
Short name T20
Test name
Test status
Simulation time 591510757 ps
CPU time 7.75 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:36 PM PDT 24
Peak memory 217936 kb
Host smart-d05f8cf6-f882-4ec6-bdf3-454dc30f1058
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545488594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.545488594
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1309537375
Short name T789
Test name
Test status
Simulation time 221409978 ps
CPU time 9.85 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:25 PM PDT 24
Peak memory 226180 kb
Host smart-d5aaeef9-ef5a-43d5-b0f3-23c62a792aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309537375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1309537375
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2230385112
Short name T263
Test name
Test status
Simulation time 370126641 ps
CPU time 1.85 seconds
Started Jul 18 06:56:05 PM PDT 24
Finished Jul 18 06:56:17 PM PDT 24
Peak memory 214508 kb
Host smart-410aadee-94b6-46d0-aee8-5ae4922dee21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230385112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2230385112
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2964595348
Short name T248
Test name
Test status
Simulation time 805897899 ps
CPU time 22.09 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:38 PM PDT 24
Peak memory 251192 kb
Host smart-16f9618f-0862-4817-8438-bad1cf0aaaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964595348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2964595348
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.534024152
Short name T692
Test name
Test status
Simulation time 335185182 ps
CPU time 6.79 seconds
Started Jul 18 06:56:05 PM PDT 24
Finished Jul 18 06:56:22 PM PDT 24
Peak memory 247452 kb
Host smart-866346d9-c139-457a-ae1a-1f8f31827ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534024152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.534024152
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3010641496
Short name T294
Test name
Test status
Simulation time 42559616096 ps
CPU time 294.14 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 07:01:22 PM PDT 24
Peak memory 282872 kb
Host smart-5b1cce70-7854-4ede-8ca1-7daa113d7ad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010641496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3010641496
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3533384872
Short name T708
Test name
Test status
Simulation time 36321823 ps
CPU time 0.98 seconds
Started Jul 18 06:56:06 PM PDT 24
Finished Jul 18 06:56:17 PM PDT 24
Peak memory 212040 kb
Host smart-615a859e-e1dc-4a23-9c20-bf9b8c511482
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533384872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3533384872
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2480848528
Short name T775
Test name
Test status
Simulation time 42355310 ps
CPU time 1.17 seconds
Started Jul 18 06:56:18 PM PDT 24
Finished Jul 18 06:56:25 PM PDT 24
Peak memory 209140 kb
Host smart-d8bf141c-6dfb-47a4-8528-6183489db286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480848528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2480848528
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.4006509119
Short name T171
Test name
Test status
Simulation time 438653430 ps
CPU time 11.6 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:39 PM PDT 24
Peak memory 218424 kb
Host smart-6b8281c7-1bc6-41b4-b57b-9dd7440057b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006509119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4006509119
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2945663327
Short name T98
Test name
Test status
Simulation time 1313248973 ps
CPU time 7.79 seconds
Started Jul 18 06:56:18 PM PDT 24
Finished Jul 18 06:56:32 PM PDT 24
Peak memory 217316 kb
Host smart-64f9ac43-a4cc-4ccc-a320-2e96d3377a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945663327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2945663327
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2153044697
Short name T172
Test name
Test status
Simulation time 5592464356 ps
CPU time 24.19 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:51 PM PDT 24
Peak memory 219008 kb
Host smart-9fd2dbdc-2bdd-474c-bfbe-99ef977f4cd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153044697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2153044697
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1315636057
Short name T489
Test name
Test status
Simulation time 108317582 ps
CPU time 2.7 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 221860 kb
Host smart-58a26d2e-736e-4e4a-b916-f2b0e6edda32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315636057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1315636057
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2512125519
Short name T782
Test name
Test status
Simulation time 1505975095 ps
CPU time 3.59 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 217720 kb
Host smart-8420192a-6784-4f34-b471-1e433acd3064
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512125519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2512125519
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3229242107
Short name T451
Test name
Test status
Simulation time 17551658561 ps
CPU time 41.45 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:57:07 PM PDT 24
Peak memory 267504 kb
Host smart-5bc1da23-eeff-42a7-87f4-0b965ab8eec0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229242107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3229242107
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3121993205
Short name T300
Test name
Test status
Simulation time 523262156 ps
CPU time 14.16 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:42 PM PDT 24
Peak memory 251036 kb
Host smart-bf6bef58-e1f2-438f-a45c-3f80b7f34fd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121993205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3121993205
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2218086572
Short name T270
Test name
Test status
Simulation time 113062143 ps
CPU time 3.02 seconds
Started Jul 18 06:56:23 PM PDT 24
Finished Jul 18 06:56:32 PM PDT 24
Peak memory 218372 kb
Host smart-239ad4ab-3f53-4e83-b583-cf640bef0b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218086572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2218086572
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2387995480
Short name T358
Test name
Test status
Simulation time 413451095 ps
CPU time 17.23 seconds
Started Jul 18 06:56:18 PM PDT 24
Finished Jul 18 06:56:41 PM PDT 24
Peak memory 226076 kb
Host smart-b46162aa-74ce-4ae8-b015-59b4f7d33f13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387995480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2387995480
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1225684537
Short name T743
Test name
Test status
Simulation time 487530496 ps
CPU time 8.16 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:33 PM PDT 24
Peak memory 226052 kb
Host smart-3482577f-6ac1-4c35-adba-17a66c7e24f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225684537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1225684537
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.483243922
Short name T293
Test name
Test status
Simulation time 2058170101 ps
CPU time 17.31 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:44 PM PDT 24
Peak memory 218208 kb
Host smart-a7d13ce2-b8b8-476c-aa17-a486ddb0c4ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483243922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.483243922
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2308394092
Short name T823
Test name
Test status
Simulation time 997373226 ps
CPU time 9.91 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:37 PM PDT 24
Peak memory 218436 kb
Host smart-45550d66-b08f-45e3-bfa3-6cee4a427349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308394092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2308394092
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3861480005
Short name T421
Test name
Test status
Simulation time 28287085 ps
CPU time 2.11 seconds
Started Jul 18 06:56:22 PM PDT 24
Finished Jul 18 06:56:30 PM PDT 24
Peak memory 214180 kb
Host smart-f1db6dec-10fd-4251-add0-7243d23d2827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861480005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3861480005
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3851090588
Short name T512
Test name
Test status
Simulation time 1298454359 ps
CPU time 32.41 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:58 PM PDT 24
Peak memory 251116 kb
Host smart-db731ffc-26a4-4548-8551-c02d11a05e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851090588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3851090588
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1687842261
Short name T659
Test name
Test status
Simulation time 255330511 ps
CPU time 6.74 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:34 PM PDT 24
Peak memory 247204 kb
Host smart-1f042c94-5069-4325-9c45-7734c1694bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687842261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1687842261
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1542832519
Short name T618
Test name
Test status
Simulation time 17078804604 ps
CPU time 515.05 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 07:05:02 PM PDT 24
Peak memory 279024 kb
Host smart-7d455bc6-9f37-41b0-896d-e15cbfb3037f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542832519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1542832519
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1171179494
Short name T463
Test name
Test status
Simulation time 23599397 ps
CPU time 1.01 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:28 PM PDT 24
Peak memory 212072 kb
Host smart-45985820-05bd-44e1-a423-dd7c4389a54d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171179494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1171179494
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2339346897
Short name T754
Test name
Test status
Simulation time 172255901 ps
CPU time 1.03 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 208768 kb
Host smart-58c30949-2cfe-4697-b404-75ef2f0c726a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339346897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2339346897
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.704417855
Short name T783
Test name
Test status
Simulation time 303905037 ps
CPU time 14.84 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:42 PM PDT 24
Peak memory 218376 kb
Host smart-23da839d-3cde-4513-abe7-b67f900779a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704417855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.704417855
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.792274136
Short name T33
Test name
Test status
Simulation time 4440456543 ps
CPU time 10.95 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:38 PM PDT 24
Peak memory 217808 kb
Host smart-05fc1cf6-4cf5-43c5-bdef-d7e3a9c55358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792274136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.792274136
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1703142831
Short name T504
Test name
Test status
Simulation time 9115088295 ps
CPU time 41.63 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:57:07 PM PDT 24
Peak memory 218368 kb
Host smart-7b0b6876-051a-45fe-a857-d6ce8951b589
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703142831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1703142831
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.384512113
Short name T600
Test name
Test status
Simulation time 1606986430 ps
CPU time 8.73 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:33 PM PDT 24
Peak memory 224316 kb
Host smart-74d42528-9fd1-43c1-86c9-92c81f91b347
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384512113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.384512113
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1631664318
Short name T751
Test name
Test status
Simulation time 221610211 ps
CPU time 5.88 seconds
Started Jul 18 06:56:24 PM PDT 24
Finished Jul 18 06:56:36 PM PDT 24
Peak memory 217732 kb
Host smart-20911c58-a394-4b81-9ec4-c42ffb80c05c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631664318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1631664318
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.340599060
Short name T437
Test name
Test status
Simulation time 17347276019 ps
CPU time 54.76 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:57:22 PM PDT 24
Peak memory 283048 kb
Host smart-8af87428-ad7e-4363-af66-6d529a3dff2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340599060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.340599060
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3906089953
Short name T679
Test name
Test status
Simulation time 651722843 ps
CPU time 11.57 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:39 PM PDT 24
Peak memory 223284 kb
Host smart-3313b6e8-8eb1-4f99-820f-b5494412e791
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906089953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3906089953
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2373272062
Short name T617
Test name
Test status
Simulation time 156920459 ps
CPU time 2.37 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 218360 kb
Host smart-1b8e0233-4e0c-4af1-bfb1-629623f425dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373272062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2373272062
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.4235001494
Short name T351
Test name
Test status
Simulation time 770603497 ps
CPU time 12.72 seconds
Started Jul 18 06:56:22 PM PDT 24
Finished Jul 18 06:56:41 PM PDT 24
Peak memory 226108 kb
Host smart-49945a2e-0b14-4d3f-be01-3fc7f59ba67b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235001494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.4235001494
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1190705443
Short name T321
Test name
Test status
Simulation time 2440864528 ps
CPU time 8.24 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:36 PM PDT 24
Peak memory 226268 kb
Host smart-27e4a863-4859-418c-ad24-67dcc0ad60e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190705443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1190705443
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3511381532
Short name T744
Test name
Test status
Simulation time 3534584621 ps
CPU time 10.35 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:36 PM PDT 24
Peak memory 226364 kb
Host smart-87f4a56b-7f61-4a8e-8cfd-523de032727f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511381532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3511381532
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.73703137
Short name T349
Test name
Test status
Simulation time 31430738 ps
CPU time 2.43 seconds
Started Jul 18 06:56:18 PM PDT 24
Finished Jul 18 06:56:25 PM PDT 24
Peak memory 214536 kb
Host smart-14be8be6-3fb6-4ca0-aca0-a11cf65bf779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73703137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.73703137
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1249145866
Short name T100
Test name
Test status
Simulation time 936436063 ps
CPU time 21.2 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:48 PM PDT 24
Peak memory 251116 kb
Host smart-2dc4ab51-29d5-4f5f-b5d7-a24271b5cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249145866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1249145866
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.611648622
Short name T691
Test name
Test status
Simulation time 135103150 ps
CPU time 3.02 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:29 PM PDT 24
Peak memory 224360 kb
Host smart-d421ac6b-a42d-4bd2-86ba-37ce01a4b9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611648622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.611648622
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.4152927561
Short name T814
Test name
Test status
Simulation time 45601597062 ps
CPU time 493.12 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 07:04:40 PM PDT 24
Peak memory 283888 kb
Host smart-c102c941-ffc0-4960-a6c6-0872c035c1f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152927561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.4152927561
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3208096742
Short name T138
Test name
Test status
Simulation time 148466016179 ps
CPU time 853.88 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 07:10:40 PM PDT 24
Peak memory 284140 kb
Host smart-e2399fae-4f27-4e6c-a10b-6900aecfae06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3208096742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3208096742
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.216641698
Short name T547
Test name
Test status
Simulation time 25124643 ps
CPU time 0.98 seconds
Started Jul 18 06:56:19 PM PDT 24
Finished Jul 18 06:56:26 PM PDT 24
Peak memory 213016 kb
Host smart-fd1c35d3-1157-470e-99db-71e43030d41a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216641698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.216641698
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1782614953
Short name T436
Test name
Test status
Simulation time 21823297 ps
CPU time 1.03 seconds
Started Jul 18 06:56:38 PM PDT 24
Finished Jul 18 06:56:42 PM PDT 24
Peak memory 209048 kb
Host smart-27ca8d3c-2027-41b5-a9c6-b799e923ef1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782614953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1782614953
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1128887731
Short name T854
Test name
Test status
Simulation time 1301525445 ps
CPU time 18.29 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:46 PM PDT 24
Peak memory 218380 kb
Host smart-ca22f663-9c9a-4a03-8dd5-a24d8c3e8c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128887731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1128887731
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2412586596
Short name T363
Test name
Test status
Simulation time 215091273 ps
CPU time 2.1 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:42 PM PDT 24
Peak memory 217124 kb
Host smart-af601295-e7e8-46b3-987f-1a43e947d88b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412586596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2412586596
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3834262402
Short name T800
Test name
Test status
Simulation time 4243076432 ps
CPU time 36.69 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:57:16 PM PDT 24
Peak memory 218448 kb
Host smart-547bd6cf-819b-4e03-8bad-cb52795f44b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834262402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3834262402
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4078909868
Short name T793
Test name
Test status
Simulation time 396306618 ps
CPU time 6.3 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:56:53 PM PDT 24
Peak memory 218308 kb
Host smart-cdfe3b3f-56d9-43cc-b8c1-b02846306b5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078909868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4078909868
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.533806678
Short name T84
Test name
Test status
Simulation time 2009441036 ps
CPU time 7.9 seconds
Started Jul 18 06:56:22 PM PDT 24
Finished Jul 18 06:56:36 PM PDT 24
Peak memory 217704 kb
Host smart-48c3c0fd-19f9-4b9d-a0ce-81132c3ad36e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533806678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
533806678
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2537320613
Short name T407
Test name
Test status
Simulation time 1303871773 ps
CPU time 63.31 seconds
Started Jul 18 06:56:23 PM PDT 24
Finished Jul 18 06:57:33 PM PDT 24
Peak memory 267436 kb
Host smart-ad1345c8-721e-485e-89f8-354b41c60b37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537320613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2537320613
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1348142951
Short name T420
Test name
Test status
Simulation time 1138456966 ps
CPU time 22.79 seconds
Started Jul 18 06:56:20 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 251000 kb
Host smart-2f6ab369-80f3-45e7-b016-2213159a6f34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348142951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1348142951
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.864638140
Short name T684
Test name
Test status
Simulation time 144195604 ps
CPU time 3.12 seconds
Started Jul 18 06:56:23 PM PDT 24
Finished Jul 18 06:56:32 PM PDT 24
Peak memory 218360 kb
Host smart-0a02bf81-9515-4b8c-8840-df437f997dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864638140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.864638140
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1044177105
Short name T716
Test name
Test status
Simulation time 1941651804 ps
CPU time 19.25 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:59 PM PDT 24
Peak memory 226080 kb
Host smart-38eabbb8-118a-4a30-adb1-e104b36bf4c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044177105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1044177105
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3928735894
Short name T433
Test name
Test status
Simulation time 2229256169 ps
CPU time 15.42 seconds
Started Jul 18 06:56:38 PM PDT 24
Finished Jul 18 06:56:57 PM PDT 24
Peak memory 226180 kb
Host smart-5316050a-7ecf-4d37-b804-c2fa066a618c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928735894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3928735894
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2804721531
Short name T519
Test name
Test status
Simulation time 422026895 ps
CPU time 9.1 seconds
Started Jul 18 06:56:36 PM PDT 24
Finished Jul 18 06:56:48 PM PDT 24
Peak memory 218316 kb
Host smart-13075962-84e6-4091-8a19-2e7730352cf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804721531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2804721531
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3965054264
Short name T634
Test name
Test status
Simulation time 597818913 ps
CPU time 11.44 seconds
Started Jul 18 06:56:23 PM PDT 24
Finished Jul 18 06:56:41 PM PDT 24
Peak memory 218448 kb
Host smart-b314d0dc-1470-4e76-8cfb-2fcab650ca2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965054264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3965054264
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.700688983
Short name T371
Test name
Test status
Simulation time 48099638 ps
CPU time 3.08 seconds
Started Jul 18 06:56:22 PM PDT 24
Finished Jul 18 06:56:32 PM PDT 24
Peak memory 214536 kb
Host smart-3021c68c-5116-4580-b474-b7eb7417d9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700688983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.700688983
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2677540400
Short name T265
Test name
Test status
Simulation time 422578086 ps
CPU time 26.29 seconds
Started Jul 18 06:56:22 PM PDT 24
Finished Jul 18 06:56:55 PM PDT 24
Peak memory 251080 kb
Host smart-1375dae4-dd6b-43e3-bb32-683b28448be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677540400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2677540400
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2884838563
Short name T590
Test name
Test status
Simulation time 88965697 ps
CPU time 3.24 seconds
Started Jul 18 06:56:21 PM PDT 24
Finished Jul 18 06:56:31 PM PDT 24
Peak memory 218368 kb
Host smart-b55c419c-35a2-432f-b964-74f1388c046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884838563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2884838563
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2445915158
Short name T415
Test name
Test status
Simulation time 17017233308 ps
CPU time 358.99 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 07:02:42 PM PDT 24
Peak memory 267628 kb
Host smart-cce1b6eb-11aa-4536-be61-ddb0de02b9fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445915158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2445915158
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2966078120
Short name T717
Test name
Test status
Simulation time 53045406695 ps
CPU time 470.97 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 07:04:35 PM PDT 24
Peak memory 327620 kb
Host smart-50bc105d-4f79-4276-bf21-52948346c68b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2966078120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2966078120
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3550591493
Short name T580
Test name
Test status
Simulation time 49122796 ps
CPU time 1.01 seconds
Started Jul 18 06:56:36 PM PDT 24
Finished Jul 18 06:56:40 PM PDT 24
Peak memory 208968 kb
Host smart-5982cdfc-600c-48cb-af7f-6ab176e9eb87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550591493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3550591493
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3726510113
Short name T788
Test name
Test status
Simulation time 473722886 ps
CPU time 13.32 seconds
Started Jul 18 06:56:35 PM PDT 24
Finished Jul 18 06:56:51 PM PDT 24
Peak memory 218420 kb
Host smart-ca00ad87-5606-443d-a8d2-5d2386af4eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726510113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3726510113
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.471757573
Short name T611
Test name
Test status
Simulation time 284494960 ps
CPU time 3.52 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:43 PM PDT 24
Peak memory 217276 kb
Host smart-cf859cea-933e-4530-84d2-923d487d4284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471757573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.471757573
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3415574708
Short name T628
Test name
Test status
Simulation time 266165163 ps
CPU time 5.07 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:45 PM PDT 24
Peak memory 221884 kb
Host smart-38b5e6f4-ca37-4a95-9d00-d46cfdc1324a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415574708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3415574708
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.118070617
Short name T822
Test name
Test status
Simulation time 359696772 ps
CPU time 2.2 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:42 PM PDT 24
Peak memory 217724 kb
Host smart-418b09d5-b0f1-4a10-9e0e-85dab2cf7b68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118070617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
118070617
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.565056030
Short name T353
Test name
Test status
Simulation time 7412470263 ps
CPU time 35.34 seconds
Started Jul 18 06:56:36 PM PDT 24
Finished Jul 18 06:57:14 PM PDT 24
Peak memory 268836 kb
Host smart-43acde79-eaf9-468f-9078-f6e48ea8fc3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565056030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.565056030
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2680507714
Short name T379
Test name
Test status
Simulation time 1586964319 ps
CPU time 15.83 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:57:02 PM PDT 24
Peak memory 246792 kb
Host smart-e7f494a6-8be1-40bd-9caf-454aa47549d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680507714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2680507714
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.4204697560
Short name T750
Test name
Test status
Simulation time 48424902 ps
CPU time 2.56 seconds
Started Jul 18 06:56:41 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 218448 kb
Host smart-6df6c5a9-f752-45a1-b83f-b3bf4ece5a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204697560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.4204697560
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1850326665
Short name T608
Test name
Test status
Simulation time 329724600 ps
CPU time 8.94 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 218412 kb
Host smart-05e987f6-a606-43c1-b113-159184f7afcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850326665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1850326665
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.4261374546
Short name T230
Test name
Test status
Simulation time 1459490346 ps
CPU time 11.3 seconds
Started Jul 18 06:56:38 PM PDT 24
Finished Jul 18 06:56:53 PM PDT 24
Peak memory 226100 kb
Host smart-35e8e8da-694c-4e4f-9969-ca062bf26ff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261374546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.4261374546
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1100552829
Short name T514
Test name
Test status
Simulation time 284769933 ps
CPU time 10.56 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:50 PM PDT 24
Peak memory 226088 kb
Host smart-13b84e73-9b1e-4f24-ba86-2289420eb788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100552829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1100552829
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2033700813
Short name T273
Test name
Test status
Simulation time 251995236 ps
CPU time 7.96 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:48 PM PDT 24
Peak memory 225452 kb
Host smart-2feb39bf-a904-4199-a94e-c13ec11ec3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033700813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2033700813
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.465156275
Short name T581
Test name
Test status
Simulation time 94210649 ps
CPU time 1.86 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:56:41 PM PDT 24
Peak memory 214240 kb
Host smart-a3ae388b-3c7c-4cb5-a753-d00b9b787de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465156275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.465156275
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1612463420
Short name T826
Test name
Test status
Simulation time 978589447 ps
CPU time 34.2 seconds
Started Jul 18 06:56:38 PM PDT 24
Finished Jul 18 06:57:16 PM PDT 24
Peak memory 251180 kb
Host smart-96285e3b-68c4-48cc-ad93-e0d572f14a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612463420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1612463420
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2868056596
Short name T702
Test name
Test status
Simulation time 47043127 ps
CPU time 6.12 seconds
Started Jul 18 06:56:36 PM PDT 24
Finished Jul 18 06:56:45 PM PDT 24
Peak memory 242852 kb
Host smart-b2c5ecd3-4fd3-4c18-b1a3-3a92edebf6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868056596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2868056596
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3927239518
Short name T380
Test name
Test status
Simulation time 11626490126 ps
CPU time 94.03 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:58:19 PM PDT 24
Peak memory 272672 kb
Host smart-400d25a1-4f59-4f41-afee-409e78d7ec69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927239518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3927239518
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3894293522
Short name T105
Test name
Test status
Simulation time 29590446440 ps
CPU time 797.31 seconds
Started Jul 18 06:56:34 PM PDT 24
Finished Jul 18 07:09:54 PM PDT 24
Peak memory 497056 kb
Host smart-4f3b2129-a7b8-44fc-9d53-536c1b008560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3894293522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3894293522
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3698785260
Short name T86
Test name
Test status
Simulation time 13430406 ps
CPU time 0.87 seconds
Started Jul 18 06:56:38 PM PDT 24
Finished Jul 18 06:56:43 PM PDT 24
Peak memory 212028 kb
Host smart-86e5b876-c398-4fbc-a1c3-03af4f057648
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698785260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3698785260
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.402881809
Short name T69
Test name
Test status
Simulation time 15119138 ps
CPU time 0.91 seconds
Started Jul 18 06:56:42 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 208904 kb
Host smart-40b33eec-eb78-4592-ab5b-1b6380b4caeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402881809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.402881809
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2709067521
Short name T272
Test name
Test status
Simulation time 983706675 ps
CPU time 10.17 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:54 PM PDT 24
Peak memory 218376 kb
Host smart-74d733fc-0925-4aa4-9c8c-c2a27d4359b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709067521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2709067521
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3053353093
Short name T446
Test name
Test status
Simulation time 657081892 ps
CPU time 8.86 seconds
Started Jul 18 06:56:38 PM PDT 24
Finished Jul 18 06:56:51 PM PDT 24
Peak memory 217424 kb
Host smart-a2eaeae0-d64c-4260-abd0-59825bf87c60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053353093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3053353093
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2963512694
Short name T472
Test name
Test status
Simulation time 3606069919 ps
CPU time 100.28 seconds
Started Jul 18 06:56:37 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 219012 kb
Host smart-8c8e7031-8d60-405e-9249-240fe7792c45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963512694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2963512694
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3595675882
Short name T820
Test name
Test status
Simulation time 320951930 ps
CPU time 6.65 seconds
Started Jul 18 06:56:36 PM PDT 24
Finished Jul 18 06:56:45 PM PDT 24
Peak memory 218312 kb
Host smart-858ef685-ae1f-4a86-85d2-66c11713050f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595675882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3595675882
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1199201054
Short name T724
Test name
Test status
Simulation time 1416632387 ps
CPU time 9.54 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:53 PM PDT 24
Peak memory 217844 kb
Host smart-a8e50249-dad1-416b-9c15-13d83c40435b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199201054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1199201054
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.952976445
Short name T485
Test name
Test status
Simulation time 4461734215 ps
CPU time 54.28 seconds
Started Jul 18 06:56:34 PM PDT 24
Finished Jul 18 06:57:30 PM PDT 24
Peak memory 283516 kb
Host smart-36bd98ee-a6f1-4af7-b727-7d93adf0f91a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952976445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.952976445
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2321790918
Short name T474
Test name
Test status
Simulation time 3121742547 ps
CPU time 14.21 seconds
Started Jul 18 06:56:38 PM PDT 24
Finished Jul 18 06:56:57 PM PDT 24
Peak memory 251128 kb
Host smart-040c9144-6d07-4496-91f6-f39f941ec616
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321790918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2321790918
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.796531993
Short name T732
Test name
Test status
Simulation time 52281089 ps
CPU time 2.11 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:56:47 PM PDT 24
Peak memory 218372 kb
Host smart-11e1cfcc-c807-4216-84f3-cb5665c8193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796531993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.796531993
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3644803726
Short name T225
Test name
Test status
Simulation time 3697714067 ps
CPU time 9.36 seconds
Started Jul 18 06:56:42 PM PDT 24
Finished Jul 18 06:56:58 PM PDT 24
Peak memory 226168 kb
Host smart-0dcc9c58-e438-4235-a707-5e29e79a7ff6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644803726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3644803726
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1461184953
Short name T16
Test name
Test status
Simulation time 1118242976 ps
CPU time 9.52 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:53 PM PDT 24
Peak memory 218396 kb
Host smart-816397b3-277c-4394-b56b-c624b9230eef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461184953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1461184953
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2737322668
Short name T99
Test name
Test status
Simulation time 1439212706 ps
CPU time 10.83 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:56 PM PDT 24
Peak memory 226176 kb
Host smart-de3ee956-18ef-4577-92b0-0afe7ff79960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737322668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2737322668
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3197802325
Short name T231
Test name
Test status
Simulation time 13280077 ps
CPU time 1.06 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:44 PM PDT 24
Peak memory 217852 kb
Host smart-67e16d5e-8a50-4cef-82f3-c57b338b90e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197802325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3197802325
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2667711412
Short name T167
Test name
Test status
Simulation time 280220601 ps
CPU time 26.26 seconds
Started Jul 18 06:56:36 PM PDT 24
Finished Jul 18 06:57:05 PM PDT 24
Peak memory 251116 kb
Host smart-4c0f018b-db3a-4bc1-b43b-f56fd0623114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667711412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2667711412
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3097335833
Short name T72
Test name
Test status
Simulation time 108518331 ps
CPU time 6.96 seconds
Started Jul 18 06:56:35 PM PDT 24
Finished Jul 18 06:56:45 PM PDT 24
Peak memory 246576 kb
Host smart-fec6769a-04a8-4a1d-bd30-e1037bcfffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097335833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3097335833
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1886581529
Short name T810
Test name
Test status
Simulation time 7468117420 ps
CPU time 164.32 seconds
Started Jul 18 06:56:42 PM PDT 24
Finished Jul 18 06:59:33 PM PDT 24
Peak memory 283928 kb
Host smart-a1846572-a9f2-43ee-9fa6-b7c1f3e3d74a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886581529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1886581529
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3523908157
Short name T602
Test name
Test status
Simulation time 81037681162 ps
CPU time 530.72 seconds
Started Jul 18 06:56:41 PM PDT 24
Finished Jul 18 07:05:38 PM PDT 24
Peak memory 284020 kb
Host smart-0b3652ad-34e2-439e-8265-104651733f8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3523908157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3523908157
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2263762272
Short name T158
Test name
Test status
Simulation time 34517961 ps
CPU time 0.95 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:56:46 PM PDT 24
Peak memory 208268 kb
Host smart-89c7d099-529f-42c9-8a9f-2658d591b86d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263762272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2263762272
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2066106888
Short name T845
Test name
Test status
Simulation time 79547021 ps
CPU time 1.13 seconds
Started Jul 18 06:55:30 PM PDT 24
Finished Jul 18 06:55:35 PM PDT 24
Peak memory 209040 kb
Host smart-4f2353de-6bd4-4d7a-9ae6-ebeaf9a1f3c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066106888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2066106888
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1402217492
Short name T258
Test name
Test status
Simulation time 26458630 ps
CPU time 0.79 seconds
Started Jul 18 06:55:17 PM PDT 24
Finished Jul 18 06:55:20 PM PDT 24
Peak memory 209136 kb
Host smart-58eaf765-1252-4bd9-95e3-d6a94dca0427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402217492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1402217492
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2804009833
Short name T14
Test name
Test status
Simulation time 754152862 ps
CPU time 15.8 seconds
Started Jul 18 06:55:15 PM PDT 24
Finished Jul 18 06:55:33 PM PDT 24
Peak memory 218312 kb
Host smart-9cd7f1a3-70f2-42ac-93e8-6e29bc91f0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804009833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2804009833
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2212796093
Short name T710
Test name
Test status
Simulation time 435935690 ps
CPU time 11.07 seconds
Started Jul 18 06:55:10 PM PDT 24
Finished Jul 18 06:55:22 PM PDT 24
Peak memory 217748 kb
Host smart-bbe98814-0eb6-431f-9305-1490229a87a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212796093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2212796093
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1923941040
Short name T250
Test name
Test status
Simulation time 3809541887 ps
CPU time 48.75 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:56:05 PM PDT 24
Peak memory 220396 kb
Host smart-3a97b6b8-f64e-43de-8870-8ec436cc0620
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923941040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1923941040
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2932139231
Short name T550
Test name
Test status
Simulation time 101153678 ps
CPU time 3.21 seconds
Started Jul 18 06:55:12 PM PDT 24
Finished Jul 18 06:55:17 PM PDT 24
Peak memory 217536 kb
Host smart-4cb46c08-7804-498f-91dd-33b3567e6d23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932139231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
932139231
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1803295486
Short name T594
Test name
Test status
Simulation time 940350398 ps
CPU time 13.15 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:30 PM PDT 24
Peak memory 218320 kb
Host smart-ec8a88d4-d030-463d-adbc-1a2d79f6ed89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803295486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1803295486
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.614092395
Short name T777
Test name
Test status
Simulation time 1313315605 ps
CPU time 19.83 seconds
Started Jul 18 06:55:09 PM PDT 24
Finished Jul 18 06:55:30 PM PDT 24
Peak memory 217676 kb
Host smart-ab30e048-aa08-4fa9-9edb-54c0c45f2226
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614092395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.614092395
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.930232034
Short name T505
Test name
Test status
Simulation time 329306492 ps
CPU time 3.1 seconds
Started Jul 18 06:55:15 PM PDT 24
Finished Jul 18 06:55:20 PM PDT 24
Peak memory 217724 kb
Host smart-b1de9031-8d42-4bd1-a004-416448796f0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930232034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.930232034
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2480766976
Short name T545
Test name
Test status
Simulation time 2778519412 ps
CPU time 33.37 seconds
Started Jul 18 06:55:17 PM PDT 24
Finished Jul 18 06:55:53 PM PDT 24
Peak memory 251876 kb
Host smart-3bd0800a-ad95-41c0-ad6c-701f41ef24c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480766976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2480766976
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2775387392
Short name T796
Test name
Test status
Simulation time 3279064179 ps
CPU time 26.09 seconds
Started Jul 18 06:55:15 PM PDT 24
Finished Jul 18 06:55:44 PM PDT 24
Peak memory 226552 kb
Host smart-2e0ff001-cd39-48e3-9233-cc91e6a5409a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775387392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2775387392
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2678591760
Short name T651
Test name
Test status
Simulation time 107944904 ps
CPU time 3.4 seconds
Started Jul 18 06:55:17 PM PDT 24
Finished Jul 18 06:55:23 PM PDT 24
Peak memory 218360 kb
Host smart-e92b2ff0-33e6-4503-aa4a-4c0258836a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678591760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2678591760
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2354009277
Short name T78
Test name
Test status
Simulation time 861633763 ps
CPU time 24.09 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 217792 kb
Host smart-cc6a84b3-e9fa-49d5-ac0b-a420237e36b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354009277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2354009277
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2612935710
Short name T91
Test name
Test status
Simulation time 967885152 ps
CPU time 38.04 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:56:11 PM PDT 24
Peak memory 269660 kb
Host smart-7de9d7f5-104b-40a8-a1b2-06eafb1ad977
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612935710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2612935710
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2761756307
Short name T365
Test name
Test status
Simulation time 617394709 ps
CPU time 13.59 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:29 PM PDT 24
Peak memory 226176 kb
Host smart-c8608675-d6d8-46f5-9553-5b73ce69576b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761756307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2761756307
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3584144079
Short name T630
Test name
Test status
Simulation time 1088130097 ps
CPU time 13.07 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 226096 kb
Host smart-7c4dee5d-70e2-406a-8079-216ca9b816cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584144079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3584144079
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2318804824
Short name T492
Test name
Test status
Simulation time 414732744 ps
CPU time 10.15 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:42 PM PDT 24
Peak memory 218392 kb
Host smart-c8833716-06f8-4768-9f08-705f87db45ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318804824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
318804824
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2245675286
Short name T374
Test name
Test status
Simulation time 2861233197 ps
CPU time 6.73 seconds
Started Jul 18 06:55:17 PM PDT 24
Finished Jul 18 06:55:26 PM PDT 24
Peak memory 225588 kb
Host smart-07ceae14-89a4-45ce-b37c-c3e928637662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245675286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2245675286
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3502852189
Short name T21
Test name
Test status
Simulation time 87319656 ps
CPU time 3.36 seconds
Started Jul 18 06:55:17 PM PDT 24
Finished Jul 18 06:55:23 PM PDT 24
Peak memory 217816 kb
Host smart-a38cf1ff-2ff2-4749-bde6-03df5b54a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502852189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3502852189
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2230461223
Short name T856
Test name
Test status
Simulation time 333410540 ps
CPU time 29.29 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:44 PM PDT 24
Peak memory 251072 kb
Host smart-ff31b4d9-568b-4faa-a14e-d237f6ee58bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230461223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2230461223
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.492414940
Short name T579
Test name
Test status
Simulation time 682136511 ps
CPU time 3.62 seconds
Started Jul 18 06:55:14 PM PDT 24
Finished Jul 18 06:55:20 PM PDT 24
Peak memory 218364 kb
Host smart-d2c32988-240d-45c3-ae2c-ec9d477a4eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492414940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.492414940
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.4313694
Short name T647
Test name
Test status
Simulation time 38656596155 ps
CPU time 136 seconds
Started Jul 18 06:55:28 PM PDT 24
Finished Jul 18 06:57:46 PM PDT 24
Peak memory 251188 kb
Host smart-f4c76c1b-c91d-4d1c-b303-1143a3f81abb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4313694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
lc_ctrl_stress_all.4313694
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2265434651
Short name T218
Test name
Test status
Simulation time 29673801 ps
CPU time 1.26 seconds
Started Jul 18 06:55:13 PM PDT 24
Finished Jul 18 06:55:15 PM PDT 24
Peak memory 213104 kb
Host smart-4bcf8610-626c-4f5a-810c-875fb7f455c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265434651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2265434651
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2249364905
Short name T768
Test name
Test status
Simulation time 19641723 ps
CPU time 1 seconds
Started Jul 18 06:56:44 PM PDT 24
Finished Jul 18 06:56:51 PM PDT 24
Peak memory 208984 kb
Host smart-c67da7b0-d413-4aaa-aecc-7495549588f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249364905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2249364905
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.60057749
Short name T291
Test name
Test status
Simulation time 257370074 ps
CPU time 10.92 seconds
Started Jul 18 06:56:42 PM PDT 24
Finished Jul 18 06:56:59 PM PDT 24
Peak memory 218376 kb
Host smart-fe9fade1-5faa-427d-961b-f54fc9681b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60057749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.60057749
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.677285065
Short name T67
Test name
Test status
Simulation time 189353363 ps
CPU time 4.89 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 217164 kb
Host smart-08ba9ff5-a6fc-4c19-bdfb-91eee14c6f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677285065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.677285065
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2089285021
Short name T483
Test name
Test status
Simulation time 142457947 ps
CPU time 1.89 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:56:47 PM PDT 24
Peak memory 218444 kb
Host smart-3a0e7639-020f-4332-95cc-3ca8436fd78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089285021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2089285021
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3238719977
Short name T530
Test name
Test status
Simulation time 6908485838 ps
CPU time 18.09 seconds
Started Jul 18 06:56:43 PM PDT 24
Finished Jul 18 06:57:07 PM PDT 24
Peak memory 226160 kb
Host smart-ba888bc0-f89d-415d-b344-905c63f37361
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238719977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3238719977
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1615477577
Short name T253
Test name
Test status
Simulation time 2027586662 ps
CPU time 10.87 seconds
Started Jul 18 06:56:43 PM PDT 24
Finished Jul 18 06:57:00 PM PDT 24
Peak memory 218112 kb
Host smart-8d1cc868-f816-49b5-87c1-70f0f9ddaedb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615477577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1615477577
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3860184563
Short name T428
Test name
Test status
Simulation time 226330844 ps
CPU time 9.54 seconds
Started Jul 18 06:56:43 PM PDT 24
Finished Jul 18 06:56:59 PM PDT 24
Peak memory 218240 kb
Host smart-2e74f7d9-31da-4626-9949-c305c0383d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860184563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3860184563
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1012087252
Short name T275
Test name
Test status
Simulation time 410612936 ps
CPU time 5.41 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:56:51 PM PDT 24
Peak memory 217792 kb
Host smart-da931c7c-5a37-4d8b-9022-d40655ce0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012087252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1012087252
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2128966471
Short name T88
Test name
Test status
Simulation time 709665838 ps
CPU time 22.24 seconds
Started Jul 18 06:56:41 PM PDT 24
Finished Jul 18 06:57:10 PM PDT 24
Peak memory 251120 kb
Host smart-b3882ec3-a419-4be1-9720-b6262bb46d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128966471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2128966471
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3756260437
Short name T93
Test name
Test status
Simulation time 765314507 ps
CPU time 6.15 seconds
Started Jul 18 06:56:42 PM PDT 24
Finished Jul 18 06:56:54 PM PDT 24
Peak memory 242776 kb
Host smart-655e5d59-268f-4969-a705-df07426140ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756260437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3756260437
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.599241712
Short name T271
Test name
Test status
Simulation time 274728699 ps
CPU time 6.97 seconds
Started Jul 18 06:56:43 PM PDT 24
Finished Jul 18 06:56:56 PM PDT 24
Peak memory 217824 kb
Host smart-39ea45b0-1870-4646-8a8c-b45aa337cd9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599241712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.599241712
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3942253683
Short name T305
Test name
Test status
Simulation time 17914420 ps
CPU time 1 seconds
Started Jul 18 06:56:42 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 211924 kb
Host smart-0128bca1-7c58-4bc2-85c6-cd880d93e530
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942253683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3942253683
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.4187830961
Short name T606
Test name
Test status
Simulation time 29112067 ps
CPU time 0.87 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:45 PM PDT 24
Peak memory 208908 kb
Host smart-df528cb2-6e03-4aae-a0f9-d089b990262c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187830961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.4187830961
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1507276884
Short name T569
Test name
Test status
Simulation time 1023453679 ps
CPU time 12.7 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:56 PM PDT 24
Peak memory 218356 kb
Host smart-f3e396ea-3d49-4090-ab9b-ed8500bbde3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507276884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1507276884
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1567897824
Short name T470
Test name
Test status
Simulation time 739870532 ps
CPU time 17.28 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:57:03 PM PDT 24
Peak memory 217244 kb
Host smart-2068d62d-27ba-42eb-b86c-29fa333e2a56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567897824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1567897824
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.376609161
Short name T471
Test name
Test status
Simulation time 415789564 ps
CPU time 3.85 seconds
Started Jul 18 06:56:42 PM PDT 24
Finished Jul 18 06:56:52 PM PDT 24
Peak memory 218360 kb
Host smart-14d5ced0-abee-42f2-8446-de70b5b5fda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376609161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.376609161
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1739923417
Short name T38
Test name
Test status
Simulation time 2840420062 ps
CPU time 18.61 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:57:05 PM PDT 24
Peak memory 219144 kb
Host smart-752b5958-c027-4248-9a17-c7c46339d17e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739923417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1739923417
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2396662051
Short name T444
Test name
Test status
Simulation time 677176059 ps
CPU time 16.31 seconds
Started Jul 18 06:56:44 PM PDT 24
Finished Jul 18 06:57:07 PM PDT 24
Peak memory 226116 kb
Host smart-eb3896cc-eb93-4929-b48a-702d67cbb9f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396662051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2396662051
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4253672645
Short name T857
Test name
Test status
Simulation time 499566267 ps
CPU time 8.48 seconds
Started Jul 18 06:56:42 PM PDT 24
Finished Jul 18 06:56:56 PM PDT 24
Peak memory 218332 kb
Host smart-9a877d6a-095e-43c8-968f-bd98cb418829
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253672645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4253672645
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3740614046
Short name T166
Test name
Test status
Simulation time 790428754 ps
CPU time 9.56 seconds
Started Jul 18 06:56:41 PM PDT 24
Finished Jul 18 06:56:57 PM PDT 24
Peak memory 226180 kb
Host smart-6e9ff4c7-7d36-4a45-b3f9-9f80fafd8217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740614046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3740614046
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1407848668
Short name T770
Test name
Test status
Simulation time 49712643 ps
CPU time 3.1 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:56:50 PM PDT 24
Peak memory 217792 kb
Host smart-260c18a2-7580-4063-8704-18c96f178d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407848668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1407848668
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.664715060
Short name T629
Test name
Test status
Simulation time 619905224 ps
CPU time 18.69 seconds
Started Jul 18 06:56:44 PM PDT 24
Finished Jul 18 06:57:09 PM PDT 24
Peak memory 251120 kb
Host smart-97ce2021-6686-40bd-87fd-51585693c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664715060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.664715060
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2881691488
Short name T667
Test name
Test status
Simulation time 113329090 ps
CPU time 8.32 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:56:54 PM PDT 24
Peak memory 247224 kb
Host smart-c1c78ad8-fced-4374-b640-0551501fbb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881691488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2881691488
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1392921515
Short name T585
Test name
Test status
Simulation time 2338115817 ps
CPU time 138.64 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:59:02 PM PDT 24
Peak memory 251180 kb
Host smart-89a18ab1-fe65-4a58-b71c-fffd9331f980
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392921515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1392921515
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1628380274
Short name T499
Test name
Test status
Simulation time 6526890984 ps
CPU time 202.28 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 07:00:07 PM PDT 24
Peak memory 276788 kb
Host smart-5eee1a45-b986-4875-b4b1-d3207c628768
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1628380274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1628380274
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2697702895
Short name T497
Test name
Test status
Simulation time 44784402 ps
CPU time 0.9 seconds
Started Jul 18 06:56:44 PM PDT 24
Finished Jul 18 06:56:51 PM PDT 24
Peak memory 211984 kb
Host smart-998b33b9-ba62-4c83-9458-3253b0deb0e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697702895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2697702895
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1840710942
Short name T688
Test name
Test status
Simulation time 55928822 ps
CPU time 0.85 seconds
Started Jul 18 06:56:56 PM PDT 24
Finished Jul 18 06:57:03 PM PDT 24
Peak memory 208916 kb
Host smart-50735a94-37eb-424d-be6f-3938b9a8be76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840710942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1840710942
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.629990236
Short name T773
Test name
Test status
Simulation time 1929636846 ps
CPU time 12.69 seconds
Started Jul 18 06:57:16 PM PDT 24
Finished Jul 18 06:57:35 PM PDT 24
Peak memory 218488 kb
Host smart-b9fc9fad-d266-4af6-9871-689c911a41d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629990236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.629990236
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.364245569
Short name T524
Test name
Test status
Simulation time 701924437 ps
CPU time 1.83 seconds
Started Jul 18 06:56:41 PM PDT 24
Finished Jul 18 06:56:49 PM PDT 24
Peak memory 217148 kb
Host smart-54d211bb-70ba-4fba-917e-fa8558c48363
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364245569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.364245569
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1103495089
Short name T326
Test name
Test status
Simulation time 49655760 ps
CPU time 1.91 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:56:47 PM PDT 24
Peak memory 218328 kb
Host smart-5e674a64-aac1-4843-82da-773c9e9feee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103495089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1103495089
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.296799888
Short name T658
Test name
Test status
Simulation time 370256552 ps
CPU time 13.18 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:13 PM PDT 24
Peak memory 226172 kb
Host smart-0770641a-7ea3-4bfa-a6ec-c4b902ecd2b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296799888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.296799888
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2160896386
Short name T241
Test name
Test status
Simulation time 261512303 ps
CPU time 8.38 seconds
Started Jul 18 06:56:52 PM PDT 24
Finished Jul 18 06:57:05 PM PDT 24
Peak memory 226120 kb
Host smart-d1016138-06ca-4afc-bf31-461a85e668fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160896386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2160896386
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.733087441
Short name T612
Test name
Test status
Simulation time 320342442 ps
CPU time 10.53 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:11 PM PDT 24
Peak memory 218308 kb
Host smart-9b6bf6b8-922e-44ff-8948-d7ab58fab4a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733087441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.733087441
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2210241563
Short name T862
Test name
Test status
Simulation time 379622226 ps
CPU time 14.35 seconds
Started Jul 18 06:56:40 PM PDT 24
Finished Jul 18 06:57:00 PM PDT 24
Peak memory 226180 kb
Host smart-8c3fab4b-3755-4cac-9623-6651f2dac0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210241563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2210241563
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2083898127
Short name T819
Test name
Test status
Simulation time 28757629 ps
CPU time 1.48 seconds
Started Jul 18 06:56:39 PM PDT 24
Finished Jul 18 06:56:46 PM PDT 24
Peak memory 213996 kb
Host smart-ced84d9c-050a-4a7f-9e9e-23e67f945780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083898127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2083898127
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3484215969
Short name T34
Test name
Test status
Simulation time 288611980 ps
CPU time 28.13 seconds
Started Jul 18 06:56:38 PM PDT 24
Finished Jul 18 06:57:09 PM PDT 24
Peak memory 251260 kb
Host smart-77d2e77c-fda1-4474-8661-804926e706e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484215969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3484215969
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.54573534
Short name T227
Test name
Test status
Simulation time 73583372 ps
CPU time 4.01 seconds
Started Jul 18 06:56:36 PM PDT 24
Finished Jul 18 06:56:43 PM PDT 24
Peak memory 218368 kb
Host smart-7cb42b6e-5e66-410e-9fa3-212d2933b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54573534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.54573534
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3621296103
Short name T752
Test name
Test status
Simulation time 20097257724 ps
CPU time 158.89 seconds
Started Jul 18 06:56:52 PM PDT 24
Finished Jul 18 06:59:37 PM PDT 24
Peak memory 263328 kb
Host smart-3524a76d-aced-4e91-a70b-9a3f0237ceb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621296103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3621296103
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2473636222
Short name T490
Test name
Test status
Simulation time 17487225 ps
CPU time 0.88 seconds
Started Jul 18 06:56:36 PM PDT 24
Finished Jul 18 06:56:40 PM PDT 24
Peak memory 212156 kb
Host smart-7ada63b9-e32e-41c0-8adc-dd9ec66f3cb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473636222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2473636222
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2190250736
Short name T445
Test name
Test status
Simulation time 16615377 ps
CPU time 1.13 seconds
Started Jul 18 06:56:53 PM PDT 24
Finished Jul 18 06:56:59 PM PDT 24
Peak memory 208976 kb
Host smart-71a01f2f-8b02-4b56-898f-01d73bf21945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190250736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2190250736
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.26129988
Short name T244
Test name
Test status
Simulation time 330642349 ps
CPU time 11.57 seconds
Started Jul 18 06:56:58 PM PDT 24
Finished Jul 18 06:57:16 PM PDT 24
Peak memory 226328 kb
Host smart-f772c5d5-ed78-4e9a-ab87-1f583f1e3954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26129988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.26129988
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.4178616665
Short name T8
Test name
Test status
Simulation time 1407986750 ps
CPU time 13.94 seconds
Started Jul 18 06:56:52 PM PDT 24
Finished Jul 18 06:57:10 PM PDT 24
Peak memory 217400 kb
Host smart-20f77a9d-0f75-43da-aca8-2de3fd75d935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178616665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.4178616665
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3936627542
Short name T224
Test name
Test status
Simulation time 174289930 ps
CPU time 2.45 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:03 PM PDT 24
Peak memory 218344 kb
Host smart-dd63e28f-e223-451a-b799-1f82a83d5120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936627542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3936627542
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2539793735
Short name T432
Test name
Test status
Simulation time 884315914 ps
CPU time 15.69 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:17 PM PDT 24
Peak memory 218992 kb
Host smart-0c309e97-2ad3-4c62-b7bd-59b78567e44f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539793735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2539793735
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2051300965
Short name T718
Test name
Test status
Simulation time 1415242369 ps
CPU time 15.59 seconds
Started Jul 18 06:56:53 PM PDT 24
Finished Jul 18 06:57:14 PM PDT 24
Peak memory 226100 kb
Host smart-781f1c34-cc3d-4dd5-a7fb-6bd52a0f7e78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051300965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2051300965
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.4178401860
Short name T619
Test name
Test status
Simulation time 489968277 ps
CPU time 12.11 seconds
Started Jul 18 06:56:59 PM PDT 24
Finished Jul 18 06:57:17 PM PDT 24
Peak memory 218324 kb
Host smart-44dddcf7-8d5b-4d36-b6d3-c1e580c3684e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178401860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
4178401860
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3505274978
Short name T52
Test name
Test status
Simulation time 990707772 ps
CPU time 10.44 seconds
Started Jul 18 06:56:56 PM PDT 24
Finished Jul 18 06:57:13 PM PDT 24
Peak memory 218460 kb
Host smart-1e4b37ab-1fb2-4736-9c43-1904edce44a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505274978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3505274978
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3272941982
Short name T802
Test name
Test status
Simulation time 92065643 ps
CPU time 2.83 seconds
Started Jul 18 06:56:56 PM PDT 24
Finished Jul 18 06:57:05 PM PDT 24
Peak memory 217800 kb
Host smart-76ce2665-ba56-4a29-bc87-41ef3e6f34c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272941982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3272941982
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2473488127
Short name T808
Test name
Test status
Simulation time 712586473 ps
CPU time 31.03 seconds
Started Jul 18 06:56:52 PM PDT 24
Finished Jul 18 06:57:28 PM PDT 24
Peak memory 251100 kb
Host smart-b02323a7-582d-4dba-8063-d5f457cdac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473488127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2473488127
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2200494234
Short name T496
Test name
Test status
Simulation time 275657817 ps
CPU time 7.36 seconds
Started Jul 18 06:56:53 PM PDT 24
Finished Jul 18 06:57:06 PM PDT 24
Peak memory 251120 kb
Host smart-802c61a2-878b-4da5-8309-95c2340827ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200494234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2200494234
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3582359124
Short name T410
Test name
Test status
Simulation time 8324424215 ps
CPU time 214.04 seconds
Started Jul 18 06:56:59 PM PDT 24
Finished Jul 18 07:00:40 PM PDT 24
Peak memory 250944 kb
Host smart-6b47c36c-5807-4f15-93bd-9ea38be3ef63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582359124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3582359124
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.227528190
Short name T174
Test name
Test status
Simulation time 105088203 ps
CPU time 1.15 seconds
Started Jul 18 06:56:56 PM PDT 24
Finished Jul 18 06:57:04 PM PDT 24
Peak memory 213036 kb
Host smart-1402bcf8-a333-47cc-8e11-ad0b0e9fd5e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227528190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.227528190
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.427712517
Short name T491
Test name
Test status
Simulation time 30161296 ps
CPU time 1.08 seconds
Started Jul 18 06:57:01 PM PDT 24
Finished Jul 18 06:57:07 PM PDT 24
Peak memory 209088 kb
Host smart-c779d00b-1ced-4038-858d-c38ea739c7a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427712517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.427712517
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.726037004
Short name T841
Test name
Test status
Simulation time 489616685 ps
CPU time 14.84 seconds
Started Jul 18 06:57:00 PM PDT 24
Finished Jul 18 06:57:20 PM PDT 24
Peak memory 225860 kb
Host smart-c62670ca-f1cf-493e-aa9d-8af87f7745b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726037004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.726037004
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2517310939
Short name T350
Test name
Test status
Simulation time 541896125 ps
CPU time 13.67 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:15 PM PDT 24
Peak memory 217488 kb
Host smart-a8560589-e07e-41a4-af7e-d411f602de58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517310939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2517310939
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.311669003
Short name T722
Test name
Test status
Simulation time 115736249 ps
CPU time 1.84 seconds
Started Jul 18 06:56:59 PM PDT 24
Finished Jul 18 06:57:07 PM PDT 24
Peak memory 218372 kb
Host smart-0fd203bd-8101-4413-9714-aa3c0506dcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311669003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.311669003
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1606898142
Short name T266
Test name
Test status
Simulation time 669904309 ps
CPU time 13.79 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:17 PM PDT 24
Peak memory 226092 kb
Host smart-9007765a-2641-4f36-be8a-0802baa21ccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606898142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1606898142
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2985224381
Short name T833
Test name
Test status
Simulation time 519223321 ps
CPU time 10.69 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:14 PM PDT 24
Peak memory 218384 kb
Host smart-094eef66-389f-4c11-9450-53b9c2df00ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985224381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2985224381
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3352490505
Short name T372
Test name
Test status
Simulation time 305473898 ps
CPU time 12.87 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:17 PM PDT 24
Peak memory 218604 kb
Host smart-5eaf5359-989a-4a12-a558-5bd3bd53289e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352490505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3352490505
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.837042625
Short name T663
Test name
Test status
Simulation time 82105080 ps
CPU time 1.22 seconds
Started Jul 18 06:56:51 PM PDT 24
Finished Jul 18 06:56:57 PM PDT 24
Peak memory 217760 kb
Host smart-15569d1d-67c6-4cb0-bcf5-aaf04bab593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837042625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.837042625
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2810635233
Short name T5
Test name
Test status
Simulation time 897811299 ps
CPU time 27.58 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:32 PM PDT 24
Peak memory 251064 kb
Host smart-a8d4fbe5-63fe-4673-aeb9-146a8af48a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810635233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2810635233
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2482962762
Short name T632
Test name
Test status
Simulation time 82513634 ps
CPU time 7.15 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:11 PM PDT 24
Peak memory 251172 kb
Host smart-e5ab4fad-c989-4e96-a2c4-5e99a70c93dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482962762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2482962762
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2536118578
Short name T183
Test name
Test status
Simulation time 52420170143 ps
CPU time 354.15 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 07:02:54 PM PDT 24
Peak memory 278792 kb
Host smart-ee2da1ba-f01b-43fe-9198-809b9bce1750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536118578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2536118578
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.2240215389
Short name T140
Test name
Test status
Simulation time 79661553456 ps
CPU time 375.83 seconds
Started Jul 18 06:56:53 PM PDT 24
Finished Jul 18 07:03:15 PM PDT 24
Peak memory 284048 kb
Host smart-b8e1d43b-9cc1-4878-a7ca-dd54c34058f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2240215389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.2240215389
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3561476533
Short name T686
Test name
Test status
Simulation time 12300239 ps
CPU time 1.07 seconds
Started Jul 18 06:56:58 PM PDT 24
Finished Jul 18 06:57:06 PM PDT 24
Peak memory 211996 kb
Host smart-a4d416c5-8bb5-43c5-a671-f79a7196dd29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561476533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3561476533
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1850897726
Short name T68
Test name
Test status
Simulation time 31925953 ps
CPU time 1.1 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:01 PM PDT 24
Peak memory 208996 kb
Host smart-5aac8b0e-605d-413c-9250-2f8cf1503be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850897726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1850897726
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3578803179
Short name T213
Test name
Test status
Simulation time 281310292 ps
CPU time 11.64 seconds
Started Jul 18 06:56:59 PM PDT 24
Finished Jul 18 06:57:17 PM PDT 24
Peak memory 218376 kb
Host smart-ed534ab3-1a2b-4a0d-a092-62c80e159f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578803179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3578803179
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.750523583
Short name T643
Test name
Test status
Simulation time 2936873647 ps
CPU time 7.8 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:08 PM PDT 24
Peak memory 217632 kb
Host smart-a7cbfac9-55d7-43ba-98e6-35213bb45a40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750523583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.750523583
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.683023940
Short name T671
Test name
Test status
Simulation time 99426136 ps
CPU time 3.8 seconds
Started Jul 18 06:56:58 PM PDT 24
Finished Jul 18 06:57:08 PM PDT 24
Peak memory 222884 kb
Host smart-d7523ac5-a338-48c0-864e-dfc41ca4e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683023940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.683023940
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1504077910
Short name T517
Test name
Test status
Simulation time 756214452 ps
CPU time 16.17 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:20 PM PDT 24
Peak memory 226252 kb
Host smart-ba486509-f816-4909-a2a9-dedcc78f9b0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504077910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1504077910
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.769605367
Short name T840
Test name
Test status
Simulation time 1996479073 ps
CPU time 11.88 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:15 PM PDT 24
Peak memory 226052 kb
Host smart-0662c1ac-4b2d-4ad8-a740-e844173fcb0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769605367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.769605367
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1794540080
Short name T325
Test name
Test status
Simulation time 250174882 ps
CPU time 9.43 seconds
Started Jul 18 06:56:52 PM PDT 24
Finished Jul 18 06:57:06 PM PDT 24
Peak memory 226112 kb
Host smart-8c2e1c0b-13fe-45d4-ba53-9ee97b8250ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794540080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1794540080
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3989328097
Short name T636
Test name
Test status
Simulation time 391112239 ps
CPU time 9.68 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:10 PM PDT 24
Peak memory 226152 kb
Host smart-2db27659-77d4-44c4-bc9b-af8950032882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989328097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3989328097
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1394888368
Short name T409
Test name
Test status
Simulation time 80200140 ps
CPU time 3.32 seconds
Started Jul 18 06:56:55 PM PDT 24
Finished Jul 18 06:57:04 PM PDT 24
Peak memory 214688 kb
Host smart-5384ca30-bfc2-4c0e-837a-4967d009c8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394888368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1394888368
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.4002403188
Short name T96
Test name
Test status
Simulation time 188739309 ps
CPU time 29.44 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:30 PM PDT 24
Peak memory 251120 kb
Host smart-b66531bb-d7a8-43b8-a6e5-8d70fa7324e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002403188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.4002403188
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.64006312
Short name T175
Test name
Test status
Simulation time 154257872 ps
CPU time 6.83 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:11 PM PDT 24
Peak memory 250960 kb
Host smart-c74ddfe9-5e16-4823-a989-d84fca831a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64006312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.64006312
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2905896137
Short name T75
Test name
Test status
Simulation time 1946256648 ps
CPU time 46.76 seconds
Started Jul 18 06:56:56 PM PDT 24
Finished Jul 18 06:57:49 PM PDT 24
Peak memory 251120 kb
Host smart-88fafa6a-db0f-4298-b255-92a14a296526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905896137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2905896137
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3043198910
Short name T85
Test name
Test status
Simulation time 7338976431 ps
CPU time 305.07 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 07:02:09 PM PDT 24
Peak memory 300472 kb
Host smart-05ab8675-b4e0-4a8b-8898-a9883de59a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3043198910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3043198910
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3151931541
Short name T425
Test name
Test status
Simulation time 63539012 ps
CPU time 1.03 seconds
Started Jul 18 06:56:52 PM PDT 24
Finished Jul 18 06:56:58 PM PDT 24
Peak memory 212000 kb
Host smart-8836540e-0002-464f-a402-2dbd54498e18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151931541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3151931541
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.4058409587
Short name T338
Test name
Test status
Simulation time 38357477 ps
CPU time 0.9 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:04 PM PDT 24
Peak memory 208920 kb
Host smart-79f5de07-e5b5-4edb-877d-65ff3487d491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058409587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.4058409587
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4288907056
Short name T648
Test name
Test status
Simulation time 4865266898 ps
CPU time 9.7 seconds
Started Jul 18 06:56:56 PM PDT 24
Finished Jul 18 06:57:12 PM PDT 24
Peak memory 226224 kb
Host smart-353b247f-6b8f-499a-bec5-f8b987fc40c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288907056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4288907056
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.246242356
Short name T274
Test name
Test status
Simulation time 117825205 ps
CPU time 3.21 seconds
Started Jul 18 06:56:55 PM PDT 24
Finished Jul 18 06:57:04 PM PDT 24
Peak memory 218264 kb
Host smart-8d2af4aa-8a65-4f0b-81f8-9a0f9113fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246242356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.246242356
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3539521581
Short name T510
Test name
Test status
Simulation time 501568374 ps
CPU time 11.88 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:15 PM PDT 24
Peak memory 226236 kb
Host smart-8a2beafb-7259-4531-90b2-f420b9450265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539521581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3539521581
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2811742228
Short name T779
Test name
Test status
Simulation time 2309422800 ps
CPU time 12.46 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:16 PM PDT 24
Peak memory 226176 kb
Host smart-1074731e-59b8-42c0-8814-ced5cd11d838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811742228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2811742228
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3207175953
Short name T762
Test name
Test status
Simulation time 1052575679 ps
CPU time 9.37 seconds
Started Jul 18 06:57:01 PM PDT 24
Finished Jul 18 06:57:16 PM PDT 24
Peak memory 218324 kb
Host smart-43c7e170-160e-459c-91e7-1799baae5cee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207175953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3207175953
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3569376264
Short name T646
Test name
Test status
Simulation time 232523986 ps
CPU time 8.48 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:12 PM PDT 24
Peak memory 225092 kb
Host smart-0896b2f8-2cec-4f83-ace7-5714d37003ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569376264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3569376264
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1712346366
Short name T178
Test name
Test status
Simulation time 109250141 ps
CPU time 2.45 seconds
Started Jul 18 06:56:53 PM PDT 24
Finished Jul 18 06:57:01 PM PDT 24
Peak memory 214264 kb
Host smart-14d0fb77-ce94-4ab7-b7d8-8c3b8d7279b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712346366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1712346366
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.906581058
Short name T429
Test name
Test status
Simulation time 1256221362 ps
CPU time 29.51 seconds
Started Jul 18 06:56:52 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 251112 kb
Host smart-ec011a45-0fa8-4a78-870d-639a186d1aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906581058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.906581058
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1403165223
Short name T549
Test name
Test status
Simulation time 68079979 ps
CPU time 7.22 seconds
Started Jul 18 06:56:56 PM PDT 24
Finished Jul 18 06:57:09 PM PDT 24
Peak memory 242932 kb
Host smart-cc462129-8868-49f6-8081-eee5ae606fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403165223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1403165223
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1192226781
Short name T715
Test name
Test status
Simulation time 5432143269 ps
CPU time 187.71 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 07:00:11 PM PDT 24
Peak memory 282268 kb
Host smart-0b259564-5c96-4085-928c-25054033a6ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192226781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1192226781
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3611800081
Short name T163
Test name
Test status
Simulation time 149701089420 ps
CPU time 382.63 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 07:03:26 PM PDT 24
Peak memory 295524 kb
Host smart-72129924-578f-47e2-be6a-4b6cbf588115
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3611800081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3611800081
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1122773869
Short name T264
Test name
Test status
Simulation time 50100828 ps
CPU time 0.8 seconds
Started Jul 18 06:56:59 PM PDT 24
Finished Jul 18 06:57:06 PM PDT 24
Peak memory 211952 kb
Host smart-ab5ada5f-e6f6-45e8-bb83-a0ce7bbca7e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122773869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1122773869
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.980206773
Short name T222
Test name
Test status
Simulation time 27335003 ps
CPU time 0.87 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:57:12 PM PDT 24
Peak memory 208792 kb
Host smart-d4989a23-4dc4-4deb-a86f-a31f25aa5148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980206773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.980206773
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2378666834
Short name T277
Test name
Test status
Simulation time 1409645317 ps
CPU time 17.81 seconds
Started Jul 18 06:57:00 PM PDT 24
Finished Jul 18 06:57:24 PM PDT 24
Peak memory 218364 kb
Host smart-3b8b53cf-b4cd-4732-baaf-ecf09bffc1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378666834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2378666834
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.901474442
Short name T583
Test name
Test status
Simulation time 203500255 ps
CPU time 4.1 seconds
Started Jul 18 06:56:53 PM PDT 24
Finished Jul 18 06:57:03 PM PDT 24
Peak memory 217212 kb
Host smart-fa161e0f-6da6-41ae-8292-41048d7a5101
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901474442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.901474442
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2157307207
Short name T785
Test name
Test status
Simulation time 140539852 ps
CPU time 2.64 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:06 PM PDT 24
Peak memory 222440 kb
Host smart-446cdd64-4680-4dd7-9121-496558e0a431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157307207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2157307207
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.173105081
Short name T818
Test name
Test status
Simulation time 482044794 ps
CPU time 13.04 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:13 PM PDT 24
Peak memory 226172 kb
Host smart-c7b04c2b-dec8-46a9-add6-0c45ade86199
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173105081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.173105081
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2155579696
Short name T467
Test name
Test status
Simulation time 695520424 ps
CPU time 15 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:35 PM PDT 24
Peak memory 226184 kb
Host smart-6710adc3-7d2a-41e1-b082-583a2a3630ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155579696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2155579696
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1862548475
Short name T346
Test name
Test status
Simulation time 2327732991 ps
CPU time 9.73 seconds
Started Jul 18 06:56:54 PM PDT 24
Finished Jul 18 06:57:10 PM PDT 24
Peak memory 218396 kb
Host smart-a1e2883c-7847-441e-a5d0-fd0eaebe112f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862548475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1862548475
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3693994863
Short name T44
Test name
Test status
Simulation time 1320325644 ps
CPU time 8.18 seconds
Started Jul 18 06:57:00 PM PDT 24
Finished Jul 18 06:57:14 PM PDT 24
Peak memory 225348 kb
Host smart-8a54c023-99ed-4158-9746-ba19dd8b89fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693994863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3693994863
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2300697352
Short name T809
Test name
Test status
Simulation time 28265002 ps
CPU time 1.02 seconds
Started Jul 18 06:57:00 PM PDT 24
Finished Jul 18 06:57:07 PM PDT 24
Peak memory 217780 kb
Host smart-6285213c-7a91-4353-af8e-632b97a34a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300697352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2300697352
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1330874331
Short name T707
Test name
Test status
Simulation time 353473638 ps
CPU time 31.98 seconds
Started Jul 18 06:56:52 PM PDT 24
Finished Jul 18 06:57:29 PM PDT 24
Peak memory 251084 kb
Host smart-af8c6223-4873-472d-bef1-036fc74b0992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330874331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1330874331
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3171921574
Short name T391
Test name
Test status
Simulation time 386754312 ps
CPU time 7.05 seconds
Started Jul 18 06:56:56 PM PDT 24
Finished Jul 18 06:57:10 PM PDT 24
Peak memory 251040 kb
Host smart-9e66ecf1-d9b1-449b-9672-c09b923f0ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171921574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3171921574
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3175304869
Short name T399
Test name
Test status
Simulation time 2765815657 ps
CPU time 61.31 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:58:12 PM PDT 24
Peak memory 217868 kb
Host smart-f35b0f5a-5f79-44ac-8266-0e0f2a369407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175304869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3175304869
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2655034075
Short name T386
Test name
Test status
Simulation time 19374426 ps
CPU time 0.94 seconds
Started Jul 18 06:56:57 PM PDT 24
Finished Jul 18 06:57:05 PM PDT 24
Peak memory 212088 kb
Host smart-c73c5266-b9d9-4420-9fd1-869c9200019c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655034075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2655034075
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2083102229
Short name T554
Test name
Test status
Simulation time 31130186 ps
CPU time 1.06 seconds
Started Jul 18 06:57:10 PM PDT 24
Finished Jul 18 06:57:16 PM PDT 24
Peak memory 209140 kb
Host smart-61e37b84-2961-43cc-b295-af7eb91e599e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083102229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2083102229
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3626713780
Short name T500
Test name
Test status
Simulation time 184202356 ps
CPU time 7.5 seconds
Started Jul 18 06:57:12 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 226188 kb
Host smart-60806b52-630f-4b20-8fcf-b80e1132f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626713780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3626713780
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1364796753
Short name T1
Test name
Test status
Simulation time 226254812 ps
CPU time 6.29 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:57:19 PM PDT 24
Peak memory 217168 kb
Host smart-80b9445d-b974-4e53-9158-a7cf2407a18a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364796753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1364796753
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1409351699
Short name T815
Test name
Test status
Simulation time 81684224 ps
CPU time 2.54 seconds
Started Jul 18 06:57:10 PM PDT 24
Finished Jul 18 06:57:18 PM PDT 24
Peak memory 218452 kb
Host smart-b5a10511-acbe-42d8-a162-3df7f07b0135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409351699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1409351699
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2883777268
Short name T799
Test name
Test status
Simulation time 1465847783 ps
CPU time 12.01 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 06:57:22 PM PDT 24
Peak memory 226108 kb
Host smart-195f3b18-637b-49ba-9bfa-465ca8ba6042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883777268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2883777268
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.943836144
Short name T553
Test name
Test status
Simulation time 1172612561 ps
CPU time 13.07 seconds
Started Jul 18 06:57:10 PM PDT 24
Finished Jul 18 06:57:29 PM PDT 24
Peak memory 226208 kb
Host smart-0b09eac0-71e0-44ac-917f-a85267aa53a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943836144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.943836144
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2410766104
Short name T521
Test name
Test status
Simulation time 1047722623 ps
CPU time 7.59 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 06:57:18 PM PDT 24
Peak memory 226152 kb
Host smart-f31c3d99-7e20-4fa4-a995-2840e0f0d365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410766104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2410766104
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2409327333
Short name T456
Test name
Test status
Simulation time 549485150 ps
CPU time 5.83 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:25 PM PDT 24
Peak memory 217804 kb
Host smart-2c6c33c2-ca6d-4542-b1c3-77b22efd0c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409327333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2409327333
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.4165400773
Short name T262
Test name
Test status
Simulation time 354779645 ps
CPU time 21.23 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 06:57:31 PM PDT 24
Peak memory 251108 kb
Host smart-eea53ad3-4b15-485d-85f5-45d0c8d30772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165400773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.4165400773
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.757868548
Short name T462
Test name
Test status
Simulation time 78781858 ps
CPU time 7.65 seconds
Started Jul 18 06:57:12 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 247512 kb
Host smart-4978fad1-0f99-4913-982a-2eb41770b906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757868548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.757868548
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2345467689
Short name T830
Test name
Test status
Simulation time 22827918559 ps
CPU time 151.49 seconds
Started Jul 18 06:57:06 PM PDT 24
Finished Jul 18 06:59:41 PM PDT 24
Peak memory 267572 kb
Host smart-3fecc1ff-002b-4a48-bfcb-5cc9315077e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345467689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2345467689
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3202090092
Short name T817
Test name
Test status
Simulation time 13002304 ps
CPU time 0.77 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:57:12 PM PDT 24
Peak memory 208524 kb
Host smart-d21d2351-505f-40dd-9129-80aadff3f5e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202090092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3202090092
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.184369679
Short name T560
Test name
Test status
Simulation time 51721233 ps
CPU time 0.83 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:20 PM PDT 24
Peak memory 208812 kb
Host smart-40e7aee7-e563-4dc6-b8ac-965d0cd41fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184369679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.184369679
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.412259770
Short name T221
Test name
Test status
Simulation time 312053402 ps
CPU time 13.26 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 218368 kb
Host smart-75f07c72-c0b4-4068-b70a-d2e3c5dd9e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412259770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.412259770
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2653892276
Short name T660
Test name
Test status
Simulation time 781173724 ps
CPU time 5.63 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 06:57:15 PM PDT 24
Peak memory 217408 kb
Host smart-0ceac7b2-3dbd-4aa6-ac04-7c21c6fa83c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653892276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2653892276
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2816603809
Short name T703
Test name
Test status
Simulation time 61165159 ps
CPU time 2.2 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:15 PM PDT 24
Peak memory 218332 kb
Host smart-58529b43-c728-466d-8621-9c4f2c61f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816603809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2816603809
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.767065700
Short name T212
Test name
Test status
Simulation time 471808074 ps
CPU time 9.15 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:23 PM PDT 24
Peak memory 226244 kb
Host smart-96258e6f-8f32-4989-a928-96148905ab3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767065700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.767065700
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2687222371
Short name T601
Test name
Test status
Simulation time 1419992331 ps
CPU time 17.89 seconds
Started Jul 18 06:57:11 PM PDT 24
Finished Jul 18 06:57:35 PM PDT 24
Peak memory 226100 kb
Host smart-33f96d45-5c54-4181-b788-f340a2d09889
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687222371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2687222371
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3753778931
Short name T348
Test name
Test status
Simulation time 246822589 ps
CPU time 9.34 seconds
Started Jul 18 06:57:11 PM PDT 24
Finished Jul 18 06:57:27 PM PDT 24
Peak memory 226116 kb
Host smart-51f3389b-a1c0-4140-8771-00e994b41f65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753778931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3753778931
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2369775302
Short name T77
Test name
Test status
Simulation time 33498012 ps
CPU time 1.81 seconds
Started Jul 18 06:57:10 PM PDT 24
Finished Jul 18 06:57:18 PM PDT 24
Peak memory 214404 kb
Host smart-75ee3d59-84df-46f0-947c-b12c7231b501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369775302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2369775302
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.375710749
Short name T233
Test name
Test status
Simulation time 677942780 ps
CPU time 27.36 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:46 PM PDT 24
Peak memory 245464 kb
Host smart-9ed60e97-314a-49a5-8f81-fe1c3c350b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375710749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.375710749
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2946919757
Short name T645
Test name
Test status
Simulation time 47769399 ps
CPU time 6.98 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:28 PM PDT 24
Peak memory 250920 kb
Host smart-41179af6-d42d-4259-8f98-51d8f8865cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946919757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2946919757
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1553128453
Short name T698
Test name
Test status
Simulation time 15431532649 ps
CPU time 139.77 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:59:32 PM PDT 24
Peak memory 251296 kb
Host smart-00ec8ad1-c24f-4667-a1c3-e9c683d1960a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553128453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1553128453
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3328460520
Short name T142
Test name
Test status
Simulation time 29076335069 ps
CPU time 1070 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 07:15:00 PM PDT 24
Peak memory 422248 kb
Host smart-ef21db45-427e-4d34-b973-adefc2f3a14b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3328460520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3328460520
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3734447958
Short name T571
Test name
Test status
Simulation time 19064520 ps
CPU time 0.99 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:14 PM PDT 24
Peak memory 211924 kb
Host smart-46210d6c-fb65-4de0-8378-7e0a1bfc120d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734447958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3734447958
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.494683305
Short name T90
Test name
Test status
Simulation time 23322705 ps
CPU time 1.02 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:33 PM PDT 24
Peak memory 209028 kb
Host smart-000bcc23-70a3-4721-8bde-8ab93c5bf052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494683305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.494683305
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2481269924
Short name T520
Test name
Test status
Simulation time 11015815 ps
CPU time 0.93 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:37 PM PDT 24
Peak memory 208880 kb
Host smart-87c0dd5f-a132-40f4-8867-5f536545346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481269924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2481269924
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1922487687
Short name T418
Test name
Test status
Simulation time 3550971734 ps
CPU time 15.08 seconds
Started Jul 18 06:55:27 PM PDT 24
Finished Jul 18 06:55:43 PM PDT 24
Peak memory 219096 kb
Host smart-06b60c37-d798-445c-a5ef-bf31000a0e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922487687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1922487687
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4266206250
Short name T790
Test name
Test status
Simulation time 590603294 ps
CPU time 4.25 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:55:42 PM PDT 24
Peak memory 217160 kb
Host smart-2ea2ccb0-1324-404f-a9b0-cabb93e9da52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266206250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4266206250
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2115017725
Short name T312
Test name
Test status
Simulation time 7153950900 ps
CPU time 33.05 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:56:05 PM PDT 24
Peak memory 219040 kb
Host smart-d673ea0b-9a05-4ab7-b9c7-427704d950fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115017725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2115017725
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1547400144
Short name T613
Test name
Test status
Simulation time 204913926 ps
CPU time 2.94 seconds
Started Jul 18 06:55:27 PM PDT 24
Finished Jul 18 06:55:32 PM PDT 24
Peak memory 217804 kb
Host smart-389294e5-e20b-40f3-89c5-a69f06de3ebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547400144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
547400144
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3929605314
Short name T763
Test name
Test status
Simulation time 1752537456 ps
CPU time 10.6 seconds
Started Jul 18 06:55:26 PM PDT 24
Finished Jul 18 06:55:38 PM PDT 24
Peak memory 223052 kb
Host smart-fac858f8-6a60-4a80-a26b-8ff3e34f9304
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929605314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3929605314
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1048237932
Short name T609
Test name
Test status
Simulation time 1887866248 ps
CPU time 29.3 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:56:05 PM PDT 24
Peak memory 217712 kb
Host smart-ae3a723e-cb5d-47cb-b465-f163ed7b6e72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048237932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1048237932
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.768978614
Short name T79
Test name
Test status
Simulation time 1285167457 ps
CPU time 5.28 seconds
Started Jul 18 06:55:28 PM PDT 24
Finished Jul 18 06:55:36 PM PDT 24
Peak memory 217724 kb
Host smart-1987f331-3db7-438c-abf4-dfd240c8cddc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768978614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.768978614
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1848168852
Short name T727
Test name
Test status
Simulation time 1932472588 ps
CPU time 76.81 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:56:54 PM PDT 24
Peak memory 283820 kb
Host smart-8d5cd46f-b277-4c35-a24a-41077f903d17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848168852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1848168852
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.905170523
Short name T475
Test name
Test status
Simulation time 504266678 ps
CPU time 11.63 seconds
Started Jul 18 06:55:30 PM PDT 24
Finished Jul 18 06:55:46 PM PDT 24
Peak memory 250996 kb
Host smart-3c113dd0-c1a1-4d28-a58c-a774fd833141
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905170523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.905170523
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1164073757
Short name T616
Test name
Test status
Simulation time 81702291 ps
CPU time 1.69 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:35 PM PDT 24
Peak memory 218360 kb
Host smart-2764d06e-51ed-4152-b4c3-9cf18ede98a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164073757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1164073757
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1782754483
Short name T681
Test name
Test status
Simulation time 260779416 ps
CPU time 7.61 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 217824 kb
Host smart-f0881615-fcea-4bed-ab53-7403f182d539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782754483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1782754483
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.767327645
Short name T48
Test name
Test status
Simulation time 142826547 ps
CPU time 23.71 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:56:01 PM PDT 24
Peak memory 269644 kb
Host smart-c56e5067-b9aa-4e09-a5dd-2ff737e501ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767327645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.767327645
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2579753452
Short name T479
Test name
Test status
Simulation time 553439163 ps
CPU time 12.91 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:50 PM PDT 24
Peak memory 226100 kb
Host smart-f94912e8-fec6-448f-9317-f4a5ec9e9768
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579753452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2579753452
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3222639548
Short name T481
Test name
Test status
Simulation time 224758897 ps
CPU time 7.76 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:40 PM PDT 24
Peak memory 218292 kb
Host smart-a89e5070-757c-4a31-8218-c5fd5ffae2f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222639548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
222639548
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1738953303
Short name T848
Test name
Test status
Simulation time 340366622 ps
CPU time 8.09 seconds
Started Jul 18 06:55:28 PM PDT 24
Finished Jul 18 06:55:38 PM PDT 24
Peak memory 226252 kb
Host smart-55a6445a-4834-4a7a-af67-ce11abe99a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738953303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1738953303
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4198670914
Short name T164
Test name
Test status
Simulation time 63977002 ps
CPU time 2.14 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:38 PM PDT 24
Peak memory 214304 kb
Host smart-7f8a3f15-c389-4a80-aafc-f8ce6986febf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198670914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4198670914
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1585226639
Short name T469
Test name
Test status
Simulation time 537542534 ps
CPU time 25.88 seconds
Started Jul 18 06:55:27 PM PDT 24
Finished Jul 18 06:55:55 PM PDT 24
Peak memory 251112 kb
Host smart-1eba228a-5599-4f8b-a331-affee42065b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585226639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1585226639
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2228167895
Short name T288
Test name
Test status
Simulation time 109603354 ps
CPU time 9.02 seconds
Started Jul 18 06:55:30 PM PDT 24
Finished Jul 18 06:55:43 PM PDT 24
Peak memory 251112 kb
Host smart-bb0e7c62-5ea7-443b-89ff-7bec04ed3b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228167895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2228167895
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1461726110
Short name T103
Test name
Test status
Simulation time 5081449190 ps
CPU time 83.26 seconds
Started Jul 18 06:55:27 PM PDT 24
Finished Jul 18 06:56:51 PM PDT 24
Peak memory 267632 kb
Host smart-f7970de1-b4e8-4ccf-9b33-33b3030fb1f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461726110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1461726110
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.505166553
Short name T101
Test name
Test status
Simulation time 21600339024 ps
CPU time 767.61 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 07:08:19 PM PDT 24
Peak memory 497056 kb
Host smart-fa5237e3-973b-4c92-bcbd-b8c78105f9b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=505166553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.505166553
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3213417895
Short name T412
Test name
Test status
Simulation time 111229762 ps
CPU time 0.86 seconds
Started Jul 18 06:55:27 PM PDT 24
Finished Jul 18 06:55:30 PM PDT 24
Peak memory 217784 kb
Host smart-8454cfec-d886-464a-a918-35f30c58051b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213417895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3213417895
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.4212833029
Short name T269
Test name
Test status
Simulation time 33482911 ps
CPU time 0.93 seconds
Started Jul 18 06:57:12 PM PDT 24
Finished Jul 18 06:57:20 PM PDT 24
Peak memory 208920 kb
Host smart-565aa082-8198-4871-92dd-02fe9da8590d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212833029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.4212833029
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1604565219
Short name T285
Test name
Test status
Simulation time 1347849404 ps
CPU time 13.36 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 06:57:24 PM PDT 24
Peak memory 218372 kb
Host smart-5b87185d-4f25-45a5-9b5f-657030717635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604565219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1604565219
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3759299575
Short name T452
Test name
Test status
Simulation time 1895924445 ps
CPU time 12.28 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 06:57:22 PM PDT 24
Peak memory 217640 kb
Host smart-aba93296-1b01-4de3-8753-5b37238594b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759299575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3759299575
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2658804940
Short name T526
Test name
Test status
Simulation time 329489325 ps
CPU time 4.19 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:23 PM PDT 24
Peak memory 222900 kb
Host smart-e58429f3-fb3b-4b40-964e-61f5257f046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658804940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2658804940
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.356811144
Short name T368
Test name
Test status
Simulation time 489137458 ps
CPU time 11.43 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:57:23 PM PDT 24
Peak memory 226168 kb
Host smart-761e7f35-0565-42a3-bbaa-3a9267a3d54e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356811144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.356811144
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1997109884
Short name T804
Test name
Test status
Simulation time 1555803949 ps
CPU time 12.52 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 06:57:22 PM PDT 24
Peak memory 226108 kb
Host smart-012ec610-10a8-4744-9eef-2fa519706ea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997109884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1997109884
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1955242333
Short name T156
Test name
Test status
Simulation time 410922107 ps
CPU time 6.24 seconds
Started Jul 18 06:57:11 PM PDT 24
Finished Jul 18 06:57:23 PM PDT 24
Peak memory 226104 kb
Host smart-6965561e-eb03-4322-8f27-1924a3af6bd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955242333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1955242333
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3887914641
Short name T541
Test name
Test status
Simulation time 20779622 ps
CPU time 1.21 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:15 PM PDT 24
Peak memory 213864 kb
Host smart-54d6e242-3801-4491-bf82-ebe89c918dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887914641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3887914641
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.819777946
Short name T427
Test name
Test status
Simulation time 758638297 ps
CPU time 32.66 seconds
Started Jul 18 06:57:12 PM PDT 24
Finished Jul 18 06:57:52 PM PDT 24
Peak memory 251196 kb
Host smart-4ec5e660-2f6f-4195-a041-a94da28e5cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819777946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.819777946
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.861933122
Short name T242
Test name
Test status
Simulation time 57156596 ps
CPU time 6.1 seconds
Started Jul 18 06:57:10 PM PDT 24
Finished Jul 18 06:57:21 PM PDT 24
Peak memory 250688 kb
Host smart-63f2d235-168a-4d4f-b2b7-7f3627546ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861933122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.861933122
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1654684817
Short name T254
Test name
Test status
Simulation time 1957229116 ps
CPU time 34.26 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 226164 kb
Host smart-19aaedac-156c-42ba-997c-0d795449441b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654684817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1654684817
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3707813049
Short name T268
Test name
Test status
Simulation time 12603364 ps
CPU time 1.13 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:20 PM PDT 24
Peak memory 212028 kb
Host smart-9f4be7f7-3423-4311-9bd2-d32295fe25ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707813049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3707813049
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3618714143
Short name T458
Test name
Test status
Simulation time 31064302 ps
CPU time 0.9 seconds
Started Jul 18 06:57:12 PM PDT 24
Finished Jul 18 06:57:20 PM PDT 24
Peak memory 208908 kb
Host smart-f57c62a8-3063-49f1-9782-0c4747009545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618714143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3618714143
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3052380022
Short name T712
Test name
Test status
Simulation time 208449334 ps
CPU time 9.94 seconds
Started Jul 18 06:57:07 PM PDT 24
Finished Jul 18 06:57:20 PM PDT 24
Peak memory 218380 kb
Host smart-b1265204-125a-4ba4-8d1f-60ace5ffd60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052380022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3052380022
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.4207903291
Short name T32
Test name
Test status
Simulation time 1083196831 ps
CPU time 9.49 seconds
Started Jul 18 06:57:11 PM PDT 24
Finished Jul 18 06:57:27 PM PDT 24
Peak memory 217192 kb
Host smart-5f382e82-d8c3-4ee7-b7d2-cefb3b349171
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207903291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.4207903291
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.824745031
Short name T375
Test name
Test status
Simulation time 292221564 ps
CPU time 3.7 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:25 PM PDT 24
Peak memory 218320 kb
Host smart-db7c3cfb-2f39-4288-8a9a-fb54cf1270ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824745031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.824745031
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.955326703
Short name T839
Test name
Test status
Simulation time 1098624713 ps
CPU time 11.23 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:31 PM PDT 24
Peak memory 226172 kb
Host smart-343ce2ed-1109-4e31-9fe4-293fb20a305d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955326703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.955326703
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3029381004
Short name T672
Test name
Test status
Simulation time 2017241563 ps
CPU time 14.63 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:35 PM PDT 24
Peak memory 226044 kb
Host smart-cc916e60-57ad-4a8a-95dd-049c9872e284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029381004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3029381004
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3669477552
Short name T842
Test name
Test status
Simulation time 1389101078 ps
CPU time 11.55 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:33 PM PDT 24
Peak memory 226112 kb
Host smart-60d5a0ee-60cb-403e-a03e-6b298fe45df1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669477552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3669477552
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2945437826
Short name T695
Test name
Test status
Simulation time 572223555 ps
CPU time 13.09 seconds
Started Jul 18 06:57:11 PM PDT 24
Finished Jul 18 06:57:29 PM PDT 24
Peak memory 218428 kb
Host smart-effe6117-68ef-4ee2-b170-8985b87f143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945437826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2945437826
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3609484233
Short name T81
Test name
Test status
Simulation time 21870905 ps
CPU time 1.5 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:23 PM PDT 24
Peak memory 217768 kb
Host smart-b7a5d9cf-e041-47cd-aec6-e5825d8944a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609484233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3609484233
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2019134754
Short name T607
Test name
Test status
Simulation time 632121338 ps
CPU time 25.73 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 246384 kb
Host smart-09131bbf-369b-45c3-b67e-b0fa75cdb75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019134754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2019134754
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2989750371
Short name T759
Test name
Test status
Simulation time 379526406 ps
CPU time 9.89 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:24 PM PDT 24
Peak memory 251116 kb
Host smart-6bc79530-302d-4f0e-b9e6-74704f7d0bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989750371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2989750371
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.878329430
Short name T417
Test name
Test status
Simulation time 7257865817 ps
CPU time 74.75 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:58:34 PM PDT 24
Peak memory 239044 kb
Host smart-bbb7a68a-a9b9-4285-a474-f549e86387a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878329430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.878329430
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.617156849
Short name T439
Test name
Test status
Simulation time 52400614 ps
CPU time 0.92 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:15 PM PDT 24
Peak memory 211940 kb
Host smart-4433d525-7348-4855-b98a-aefac7486cfb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617156849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.617156849
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1535299552
Short name T736
Test name
Test status
Simulation time 30960221 ps
CPU time 0.93 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:57:14 PM PDT 24
Peak memory 209092 kb
Host smart-f7c7adbb-fa27-45c7-aee2-54f2cea2dc8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535299552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1535299552
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3138429067
Short name T219
Test name
Test status
Simulation time 336235739 ps
CPU time 9.02 seconds
Started Jul 18 06:57:11 PM PDT 24
Finished Jul 18 06:57:26 PM PDT 24
Peak memory 218376 kb
Host smart-4c7fa1a0-de3a-4e0f-9e73-1f6b74b8453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138429067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3138429067
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3826896267
Short name T31
Test name
Test status
Simulation time 329826780 ps
CPU time 5 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:27 PM PDT 24
Peak memory 217484 kb
Host smart-39d98389-2c47-495b-b88e-eb9e203ac5bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826896267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3826896267
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3013972121
Short name T287
Test name
Test status
Simulation time 142572359 ps
CPU time 2.02 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:23 PM PDT 24
Peak memory 218380 kb
Host smart-22d96421-767e-443b-ae78-adc4a2060429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013972121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3013972121
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3125722226
Short name T807
Test name
Test status
Simulation time 423061426 ps
CPU time 16.27 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 226104 kb
Host smart-29233c45-8c73-4701-8dc5-5254a1309dbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125722226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3125722226
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1198897011
Short name T327
Test name
Test status
Simulation time 3290920795 ps
CPU time 15.38 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:30 PM PDT 24
Peak memory 218384 kb
Host smart-709befd7-a84d-40bd-b72b-51eb0b9849ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198897011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1198897011
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1825864919
Short name T564
Test name
Test status
Simulation time 1076097908 ps
CPU time 8.65 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:28 PM PDT 24
Peak memory 225376 kb
Host smart-4b634208-e7e2-4318-8b80-499831bc6f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825864919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1825864919
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.554901553
Short name T267
Test name
Test status
Simulation time 105095647 ps
CPU time 1.71 seconds
Started Jul 18 06:57:09 PM PDT 24
Finished Jul 18 06:57:16 PM PDT 24
Peak memory 214172 kb
Host smart-e0d7e547-090f-4626-95f1-1635534d565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554901553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.554901553
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2645373450
Short name T709
Test name
Test status
Simulation time 286450713 ps
CPU time 27.38 seconds
Started Jul 18 06:57:11 PM PDT 24
Finished Jul 18 06:57:44 PM PDT 24
Peak memory 250892 kb
Host smart-0070e28f-794a-458d-a817-caf1a89fcb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645373450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2645373450
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.870701902
Short name T507
Test name
Test status
Simulation time 521861825 ps
CPU time 8.1 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:30 PM PDT 24
Peak memory 250956 kb
Host smart-7a8be681-7e3f-4476-827d-f77b71019628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870701902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.870701902
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2793050781
Short name T384
Test name
Test status
Simulation time 23597761396 ps
CPU time 111.94 seconds
Started Jul 18 06:57:14 PM PDT 24
Finished Jul 18 06:59:13 PM PDT 24
Peak memory 276400 kb
Host smart-04aa9a8b-dda0-421a-9af2-e43483c502cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793050781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2793050781
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1773264693
Short name T143
Test name
Test status
Simulation time 236747397068 ps
CPU time 2284.62 seconds
Started Jul 18 06:57:14 PM PDT 24
Finished Jul 18 07:35:25 PM PDT 24
Peak memory 946268 kb
Host smart-5e738b2a-ebf5-4263-a9fc-ae0436583f1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1773264693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1773264693
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2465710643
Short name T655
Test name
Test status
Simulation time 13811688 ps
CPU time 1.02 seconds
Started Jul 18 06:57:08 PM PDT 24
Finished Jul 18 06:57:13 PM PDT 24
Peak memory 211920 kb
Host smart-46677b74-2595-4047-9ca0-bd417c802b99
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465710643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2465710643
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1336558214
Short name T776
Test name
Test status
Simulation time 28894870 ps
CPU time 1.31 seconds
Started Jul 18 06:57:26 PM PDT 24
Finished Jul 18 06:57:33 PM PDT 24
Peak memory 209148 kb
Host smart-b61b1bd4-6797-4eff-abb9-5bdb2008a381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336558214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1336558214
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1712337929
Short name T690
Test name
Test status
Simulation time 1689856565 ps
CPU time 16.93 seconds
Started Jul 18 06:57:26 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 218368 kb
Host smart-3c93c4fa-765b-46bc-b5e6-26c1e6b77e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712337929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1712337929
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1603064094
Short name T177
Test name
Test status
Simulation time 33050644 ps
CPU time 1.29 seconds
Started Jul 18 06:57:31 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 217212 kb
Host smart-2022b563-ac5b-406a-bfdd-46812de95c31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603064094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1603064094
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.4273584434
Short name T733
Test name
Test status
Simulation time 137236860 ps
CPU time 3.91 seconds
Started Jul 18 06:57:28 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 218364 kb
Host smart-7b6189c0-0d07-4303-8d73-3cff03353229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273584434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.4273584434
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4255587251
Short name T15
Test name
Test status
Simulation time 615135496 ps
CPU time 23.43 seconds
Started Jul 18 06:57:25 PM PDT 24
Finished Jul 18 06:57:54 PM PDT 24
Peak memory 226176 kb
Host smart-c849691b-4a0f-4196-8c7f-68c1fbf713c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255587251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4255587251
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2620304095
Short name T625
Test name
Test status
Simulation time 824988053 ps
CPU time 6.66 seconds
Started Jul 18 06:57:27 PM PDT 24
Finished Jul 18 06:57:39 PM PDT 24
Peak memory 218236 kb
Host smart-04115c84-12c4-427a-b43e-b0472d98d690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620304095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2620304095
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1742640140
Short name T685
Test name
Test status
Simulation time 641922619 ps
CPU time 10.02 seconds
Started Jul 18 06:57:24 PM PDT 24
Finished Jul 18 06:57:40 PM PDT 24
Peak memory 226172 kb
Host smart-9971c535-5618-44d2-9d95-cc8a82ebb368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742640140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1742640140
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2403597931
Short name T354
Test name
Test status
Simulation time 171554125 ps
CPU time 3.62 seconds
Started Jul 18 06:57:13 PM PDT 24
Finished Jul 18 06:57:23 PM PDT 24
Peak memory 215484 kb
Host smart-2f320449-d466-4b55-86ca-7fdb47a85445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403597931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2403597931
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2302082962
Short name T603
Test name
Test status
Simulation time 1033494939 ps
CPU time 24.56 seconds
Started Jul 18 06:57:15 PM PDT 24
Finished Jul 18 06:57:46 PM PDT 24
Peak memory 246244 kb
Host smart-ec9c9a64-659f-4c63-bd35-9bba27a4c4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302082962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2302082962
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1642978273
Short name T852
Test name
Test status
Simulation time 81737230 ps
CPU time 7.22 seconds
Started Jul 18 06:57:14 PM PDT 24
Finished Jul 18 06:57:27 PM PDT 24
Peak memory 251292 kb
Host smart-8e87ec24-3b70-4b6d-8610-9bdaec7a33c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642978273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1642978273
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2850626342
Short name T502
Test name
Test status
Simulation time 2947469271 ps
CPU time 47 seconds
Started Jul 18 06:57:24 PM PDT 24
Finished Jul 18 06:58:17 PM PDT 24
Peak memory 251160 kb
Host smart-24801dc6-6d40-464c-9492-daec2876a1b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850626342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2850626342
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2378321299
Short name T74
Test name
Test status
Simulation time 49146927292 ps
CPU time 779.64 seconds
Started Jul 18 06:57:25 PM PDT 24
Finished Jul 18 07:10:30 PM PDT 24
Peak memory 497032 kb
Host smart-96729004-cf72-4eea-868c-e06a1a29a4d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2378321299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2378321299
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1545125325
Short name T292
Test name
Test status
Simulation time 13445481 ps
CPU time 0.98 seconds
Started Jul 18 06:57:14 PM PDT 24
Finished Jul 18 06:57:21 PM PDT 24
Peak memory 212204 kb
Host smart-59a3d93f-e06a-41c3-8dfe-a37b9e27f36d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545125325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1545125325
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.985379816
Short name T682
Test name
Test status
Simulation time 19037214 ps
CPU time 0.99 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 06:57:37 PM PDT 24
Peak memory 208916 kb
Host smart-f65b47e1-cd7d-4841-8d48-65697c0c74ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985379816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.985379816
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.90934438
Short name T805
Test name
Test status
Simulation time 289861236 ps
CPU time 15.03 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:57:52 PM PDT 24
Peak memory 218364 kb
Host smart-f83b1cc3-a41e-4f9b-9704-033e30b4c701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90934438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.90934438
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4251627673
Short name T531
Test name
Test status
Simulation time 4067927654 ps
CPU time 12.08 seconds
Started Jul 18 06:57:26 PM PDT 24
Finished Jul 18 06:57:44 PM PDT 24
Peak memory 217852 kb
Host smart-080451ec-e3f1-4734-ad8f-59ba81b85477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251627673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4251627673
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1315394009
Short name T396
Test name
Test status
Simulation time 23468914 ps
CPU time 1.93 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:57:37 PM PDT 24
Peak memory 218364 kb
Host smart-2a16087e-54f2-4b57-b977-15b6ca72f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315394009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1315394009
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1435264138
Short name T828
Test name
Test status
Simulation time 1925352096 ps
CPU time 12.87 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 06:57:49 PM PDT 24
Peak memory 226176 kb
Host smart-cf18312f-819d-49cc-9952-1e867089bbb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435264138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1435264138
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.231584656
Short name T426
Test name
Test status
Simulation time 380348883 ps
CPU time 6.6 seconds
Started Jul 18 06:57:28 PM PDT 24
Finished Jul 18 06:57:41 PM PDT 24
Peak memory 225648 kb
Host smart-da00709b-e87a-42a4-a1bd-4dfc30e29e51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231584656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.231584656
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3820972206
Short name T766
Test name
Test status
Simulation time 895172679 ps
CPU time 10.09 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:57:45 PM PDT 24
Peak memory 218376 kb
Host smart-c2cae125-ba35-48f4-ab96-3289bbce4246
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820972206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3820972206
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2131271497
Short name T154
Test name
Test status
Simulation time 471889455 ps
CPU time 16.3 seconds
Started Jul 18 06:57:23 PM PDT 24
Finished Jul 18 06:57:45 PM PDT 24
Peak memory 218448 kb
Host smart-1aed45a9-ca91-489f-b8c4-59bdb59a184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131271497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2131271497
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.479564297
Short name T320
Test name
Test status
Simulation time 65226370 ps
CPU time 2.59 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:57:37 PM PDT 24
Peak memory 214444 kb
Host smart-4056efad-781d-4a8a-9e93-e1052533d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479564297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.479564297
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2024820292
Short name T393
Test name
Test status
Simulation time 652894873 ps
CPU time 30.8 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:58:08 PM PDT 24
Peak memory 248572 kb
Host smart-ed4a7b65-ea52-43b6-9a6e-57bedda2cfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024820292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2024820292
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1732722470
Short name T745
Test name
Test status
Simulation time 434257013 ps
CPU time 7.7 seconds
Started Jul 18 06:57:25 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 251096 kb
Host smart-42d14230-18ae-45bf-b5e6-71bc97a7ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732722470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1732722470
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2410671846
Short name T102
Test name
Test status
Simulation time 78487860172 ps
CPU time 116.28 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:59:34 PM PDT 24
Peak memory 267700 kb
Host smart-f99f9036-3b9e-41dd-aaef-b1e96fe27f0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410671846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2410671846
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.4062371555
Short name T680
Test name
Test status
Simulation time 6249635413 ps
CPU time 227.39 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 07:01:23 PM PDT 24
Peak memory 282040 kb
Host smart-f3a92c56-cfed-40e6-9966-1d3e2378ad97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4062371555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.4062371555
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3104004061
Short name T577
Test name
Test status
Simulation time 25296278 ps
CPU time 0.83 seconds
Started Jul 18 06:57:26 PM PDT 24
Finished Jul 18 06:57:33 PM PDT 24
Peak memory 211928 kb
Host smart-5b69805f-e67c-4071-ae11-abae03c28bfa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104004061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3104004061
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.744052458
Short name T176
Test name
Test status
Simulation time 42069493 ps
CPU time 0.95 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:57:36 PM PDT 24
Peak memory 208980 kb
Host smart-4b919f39-ddcb-4830-8bec-fd6b11790aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744052458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.744052458
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2067656471
Short name T36
Test name
Test status
Simulation time 1798521645 ps
CPU time 15.47 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:57:50 PM PDT 24
Peak memory 226268 kb
Host smart-c4c6d745-3f08-46b4-9e3e-c218f0c564ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067656471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2067656471
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1379782570
Short name T447
Test name
Test status
Simulation time 2272668463 ps
CPU time 14.4 seconds
Started Jul 18 06:57:27 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 217596 kb
Host smart-71fad857-2f09-44c1-922a-be1bab98b502
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379782570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1379782570
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4065948076
Short name T239
Test name
Test status
Simulation time 23427010 ps
CPU time 2.08 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:57:37 PM PDT 24
Peak memory 218376 kb
Host smart-99504061-7d58-46af-b2b7-fcc1f5da4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065948076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4065948076
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1614264925
Short name T753
Test name
Test status
Simulation time 1132966185 ps
CPU time 14.12 seconds
Started Jul 18 06:57:26 PM PDT 24
Finished Jul 18 06:57:46 PM PDT 24
Peak memory 226164 kb
Host smart-ea555510-a8a6-4422-bee2-b20b252d2259
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614264925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1614264925
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.301317473
Short name T559
Test name
Test status
Simulation time 581632635 ps
CPU time 13.32 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 226088 kb
Host smart-7e47c1b3-36dc-4d7f-9477-8cf387d03a3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301317473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.301317473
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4091333512
Short name T771
Test name
Test status
Simulation time 1658519907 ps
CPU time 11.83 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 218384 kb
Host smart-a0341c5f-eab4-4a79-90c4-4429bdd5101b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091333512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4091333512
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3710704000
Short name T825
Test name
Test status
Simulation time 1115884516 ps
CPU time 7.79 seconds
Started Jul 18 06:57:27 PM PDT 24
Finished Jul 18 06:57:40 PM PDT 24
Peak memory 226172 kb
Host smart-0ac7ac3b-c2dd-4fe8-b898-1f50803a27ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710704000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3710704000
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3822241329
Short name T457
Test name
Test status
Simulation time 306611530 ps
CPU time 2.21 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 214376 kb
Host smart-dc772b3a-83b6-494b-a19f-18ac0b10be56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822241329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3822241329
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3561956118
Short name T296
Test name
Test status
Simulation time 377044188 ps
CPU time 19.16 seconds
Started Jul 18 06:57:28 PM PDT 24
Finished Jul 18 06:57:53 PM PDT 24
Peak memory 251196 kb
Host smart-209dca04-86ad-47de-9694-c5b8ee4b30f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561956118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3561956118
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3983624057
Short name T706
Test name
Test status
Simulation time 301701797 ps
CPU time 6.96 seconds
Started Jul 18 06:57:27 PM PDT 24
Finished Jul 18 06:57:40 PM PDT 24
Peak memory 247576 kb
Host smart-401fcb07-b9d0-4ad7-9b04-2b388f32a2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983624057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3983624057
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1890914929
Short name T824
Test name
Test status
Simulation time 3118863079 ps
CPU time 71.46 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:58:49 PM PDT 24
Peak memory 274552 kb
Host smart-1b12dd59-286b-42b0-ab25-12222441c4a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890914929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1890914929
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1476509123
Short name T587
Test name
Test status
Simulation time 11329720 ps
CPU time 0.88 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 212032 kb
Host smart-28501ecd-7b6f-492f-937b-5d02fd34747a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476509123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1476509123
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.4035171780
Short name T319
Test name
Test status
Simulation time 19535381 ps
CPU time 0.91 seconds
Started Jul 18 06:57:33 PM PDT 24
Finished Jul 18 06:57:39 PM PDT 24
Peak memory 208904 kb
Host smart-638f1413-238e-428e-bbcd-042423044e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035171780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.4035171780
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3734564637
Short name T257
Test name
Test status
Simulation time 1566623180 ps
CPU time 16.11 seconds
Started Jul 18 07:04:34 PM PDT 24
Finished Jul 18 07:04:52 PM PDT 24
Peak memory 218380 kb
Host smart-d771ab57-d69b-4315-afac-490a3501c289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734564637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3734564637
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.645589654
Short name T694
Test name
Test status
Simulation time 558303117 ps
CPU time 7.62 seconds
Started Jul 18 06:57:33 PM PDT 24
Finished Jul 18 06:57:46 PM PDT 24
Peak memory 217300 kb
Host smart-36832eef-4b03-4ae7-a52a-79cad43d5f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645589654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.645589654
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2985288947
Short name T360
Test name
Test status
Simulation time 138172698 ps
CPU time 1.86 seconds
Started Jul 18 06:57:31 PM PDT 24
Finished Jul 18 06:57:39 PM PDT 24
Peak memory 218372 kb
Host smart-90159a4d-f3e1-4c3e-84c8-13ad5beb1bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985288947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2985288947
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3381785832
Short name T508
Test name
Test status
Simulation time 9125519898 ps
CPU time 25.17 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:58:03 PM PDT 24
Peak memory 226172 kb
Host smart-77ab9dea-a61e-4296-ac6c-6bfece356ab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381785832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3381785832
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.873211460
Short name T769
Test name
Test status
Simulation time 1634315774 ps
CPU time 14.43 seconds
Started Jul 18 06:57:28 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 226112 kb
Host smart-8960141d-fc8d-4d88-a216-63b62434a9e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873211460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.873211460
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3608164675
Short name T431
Test name
Test status
Simulation time 49298791 ps
CPU time 1.47 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:57:39 PM PDT 24
Peak memory 213944 kb
Host smart-2ed9eb09-5bfc-4c95-81c7-4de4a84a02e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608164675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3608164675
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.963611406
Short name T228
Test name
Test status
Simulation time 991280645 ps
CPU time 22.16 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 06:57:58 PM PDT 24
Peak memory 251116 kb
Host smart-983b8c04-3fdf-4eb1-a4e3-952fd6e5ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963611406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.963611406
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3311695646
Short name T761
Test name
Test status
Simulation time 71196797 ps
CPU time 8.39 seconds
Started Jul 18 06:57:34 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 251080 kb
Host smart-270b0ff4-cebb-4787-9656-80680023dd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311695646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3311695646
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.976437783
Short name T390
Test name
Test status
Simulation time 9592015733 ps
CPU time 81.28 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:58:57 PM PDT 24
Peak memory 251180 kb
Host smart-be2b100f-8b6b-4ebc-b122-912e80cea2c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976437783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.976437783
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2897009475
Short name T204
Test name
Test status
Simulation time 201953667039 ps
CPU time 913.44 seconds
Started Jul 18 06:57:33 PM PDT 24
Finished Jul 18 07:12:52 PM PDT 24
Peak memory 529948 kb
Host smart-278eef78-f8b2-49ea-bcb9-5d42be35446e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2897009475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2897009475
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2205474101
Short name T574
Test name
Test status
Simulation time 14709179 ps
CPU time 0.9 seconds
Started Jul 18 06:57:31 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 211940 kb
Host smart-f52ebfac-e123-4493-9e35-9ce488aedaa2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205474101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2205474101
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.676804519
Short name T832
Test name
Test status
Simulation time 31601463 ps
CPU time 0.96 seconds
Started Jul 18 06:57:33 PM PDT 24
Finished Jul 18 06:57:39 PM PDT 24
Peak memory 209256 kb
Host smart-65a80d13-f155-4653-9871-d93963bcab8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676804519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.676804519
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2213286639
Short name T235
Test name
Test status
Simulation time 2151558554 ps
CPU time 19.21 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 06:57:55 PM PDT 24
Peak memory 226224 kb
Host smart-28dab9ed-5901-4b68-9e26-bb06aee61329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213286639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2213286639
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.4158380174
Short name T699
Test name
Test status
Simulation time 111690341 ps
CPU time 3.61 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:57:41 PM PDT 24
Peak memory 217152 kb
Host smart-fbf207f3-9787-44cd-b127-c9b93de45945
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158380174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.4158380174
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3724580861
Short name T760
Test name
Test status
Simulation time 300462802 ps
CPU time 4.09 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:57:41 PM PDT 24
Peak memory 218332 kb
Host smart-9a040a69-017f-4403-83f7-dd1513e99d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724580861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3724580861
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.4238311685
Short name T794
Test name
Test status
Simulation time 474951501 ps
CPU time 15.04 seconds
Started Jul 18 06:57:34 PM PDT 24
Finished Jul 18 06:57:54 PM PDT 24
Peak memory 226276 kb
Host smart-50615d01-5fcb-43a7-8abb-93c39414f15d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238311685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.4238311685
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1404190520
Short name T342
Test name
Test status
Simulation time 3777077420 ps
CPU time 11.12 seconds
Started Jul 18 06:57:31 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 226172 kb
Host smart-62861a31-662c-4f89-bd57-3179a7019313
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404190520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1404190520
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3927237755
Short name T400
Test name
Test status
Simulation time 3765106966 ps
CPU time 8.35 seconds
Started Jul 18 06:57:34 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 218480 kb
Host smart-1d93a377-9a35-44cd-9adb-7a9b805267ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927237755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3927237755
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.358344844
Short name T528
Test name
Test status
Simulation time 2201438086 ps
CPU time 10.94 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 226220 kb
Host smart-f1db2b1c-b9fe-48fe-bbcc-447a5e2edb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358344844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.358344844
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2695830719
Short name T631
Test name
Test status
Simulation time 144053848 ps
CPU time 2.69 seconds
Started Jul 18 06:57:33 PM PDT 24
Finished Jul 18 06:57:41 PM PDT 24
Peak memory 214916 kb
Host smart-ae3a7b62-a30f-45c1-afc0-de813663f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695830719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2695830719
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.930556128
Short name T330
Test name
Test status
Simulation time 1017655396 ps
CPU time 25.17 seconds
Started Jul 18 06:57:33 PM PDT 24
Finished Jul 18 06:58:04 PM PDT 24
Peak memory 251280 kb
Host smart-0d1f2425-d651-4a8a-ada4-f860aa75eef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930556128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.930556128
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2663402861
Short name T149
Test name
Test status
Simulation time 63979623 ps
CPU time 7.98 seconds
Started Jul 18 06:57:27 PM PDT 24
Finished Jul 18 06:57:40 PM PDT 24
Peak memory 251132 kb
Host smart-c413f756-082d-4914-aa44-2cca3bd599f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663402861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2663402861
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2229795035
Short name T532
Test name
Test status
Simulation time 34029765714 ps
CPU time 330.47 seconds
Started Jul 18 06:57:34 PM PDT 24
Finished Jul 18 07:03:09 PM PDT 24
Peak memory 251216 kb
Host smart-1a1ed945-2766-4e99-b751-d8056eb86f45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229795035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2229795035
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1743188221
Short name T58
Test name
Test status
Simulation time 17406660999 ps
CPU time 685.19 seconds
Started Jul 18 06:57:30 PM PDT 24
Finished Jul 18 07:09:01 PM PDT 24
Peak memory 422236 kb
Host smart-483301af-62e1-44ca-b703-55af3244bb79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1743188221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1743188221
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2945040038
Short name T668
Test name
Test status
Simulation time 13532111 ps
CPU time 0.9 seconds
Started Jul 18 06:57:32 PM PDT 24
Finished Jul 18 06:57:38 PM PDT 24
Peak memory 211956 kb
Host smart-d7594863-0bfc-4a52-87c1-6bb98b9a346b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945040038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2945040038
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.4253841010
Short name T89
Test name
Test status
Simulation time 31279404 ps
CPU time 1.04 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:53 PM PDT 24
Peak memory 209084 kb
Host smart-27ba1789-78bb-4235-be4e-e07a7b6180f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253841010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.4253841010
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.325324461
Short name T11
Test name
Test status
Simulation time 273412078 ps
CPU time 9.41 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:58:02 PM PDT 24
Peak memory 217864 kb
Host smart-ca250e59-8949-4a5e-8a24-4fb1da70837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325324461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.325324461
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3426227400
Short name T440
Test name
Test status
Simulation time 1019971131 ps
CPU time 2.99 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 217228 kb
Host smart-03844ca3-3a00-4764-b199-21da96ca6b5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426227400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3426227400
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3116666843
Short name T236
Test name
Test status
Simulation time 96111470 ps
CPU time 1.94 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 222148 kb
Host smart-7d317b6e-bfb2-41c4-84b6-2ef10a1a9822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116666843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3116666843
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1226892449
Short name T649
Test name
Test status
Simulation time 2410742776 ps
CPU time 10.7 seconds
Started Jul 18 06:57:48 PM PDT 24
Finished Jul 18 06:58:05 PM PDT 24
Peak memory 226172 kb
Host smart-66db60e1-d95e-45f8-b1db-1257ed030e0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226892449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1226892449
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.564092328
Short name T806
Test name
Test status
Simulation time 655606734 ps
CPU time 10.42 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:57:58 PM PDT 24
Peak memory 218316 kb
Host smart-1acc7a16-d80e-421b-9a9f-0eed0b628aeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564092328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.564092328
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.290289363
Short name T43
Test name
Test status
Simulation time 399374974 ps
CPU time 13.16 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:59 PM PDT 24
Peak memory 225820 kb
Host smart-cc962f43-7718-40f5-b325-7cfb4908cee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290289363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.290289363
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2109797523
Short name T749
Test name
Test status
Simulation time 253511799 ps
CPU time 2.33 seconds
Started Jul 18 06:57:29 PM PDT 24
Finished Jul 18 06:57:37 PM PDT 24
Peak memory 214464 kb
Host smart-a17e360f-c0b0-4bf8-80b2-3682909281fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109797523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2109797523
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2378695790
Short name T179
Test name
Test status
Simulation time 273971419 ps
CPU time 27.32 seconds
Started Jul 18 06:57:27 PM PDT 24
Finished Jul 18 06:58:00 PM PDT 24
Peak memory 251112 kb
Host smart-a3e799d4-fd69-4fa1-b4f4-50851eed403e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378695790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2378695790
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.257845107
Short name T232
Test name
Test status
Simulation time 166991085 ps
CPU time 3.59 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:49 PM PDT 24
Peak memory 226668 kb
Host smart-1258dde6-bbfe-4932-8911-f48008dd3d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257845107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.257845107
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1605723597
Short name T477
Test name
Test status
Simulation time 18899864194 ps
CPU time 194.52 seconds
Started Jul 18 06:57:47 PM PDT 24
Finished Jul 18 07:01:09 PM PDT 24
Peak memory 267484 kb
Host smart-2e5f8854-f496-410f-90ea-bb136507bebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605723597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1605723597
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.334223003
Short name T572
Test name
Test status
Simulation time 30467325 ps
CPU time 1.02 seconds
Started Jul 18 06:57:34 PM PDT 24
Finished Jul 18 06:57:40 PM PDT 24
Peak memory 212108 kb
Host smart-16a60247-f459-49e5-8e1b-f1557f7d832d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334223003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.334223003
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2133177244
Short name T539
Test name
Test status
Simulation time 368071591 ps
CPU time 1.02 seconds
Started Jul 18 06:57:48 PM PDT 24
Finished Jul 18 06:57:56 PM PDT 24
Peak memory 209040 kb
Host smart-d7d6a577-933b-4d5a-bfa1-c6e0b06be842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133177244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2133177244
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2573268127
Short name T168
Test name
Test status
Simulation time 3360588254 ps
CPU time 18.9 seconds
Started Jul 18 06:57:43 PM PDT 24
Finished Jul 18 06:58:03 PM PDT 24
Peak memory 219224 kb
Host smart-f479d49a-d53c-4449-a133-dde9dc8618b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573268127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2573268127
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1396269212
Short name T27
Test name
Test status
Simulation time 243644773 ps
CPU time 7.29 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:58:00 PM PDT 24
Peak memory 217220 kb
Host smart-0c02efce-a92d-4121-a3af-a9507d828b77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396269212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1396269212
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1059997018
Short name T157
Test name
Test status
Simulation time 77419635 ps
CPU time 2.75 seconds
Started Jul 18 06:57:43 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 222552 kb
Host smart-ae65ed1d-cf8b-4b7e-9dc8-92507c025975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059997018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1059997018
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1075181624
Short name T850
Test name
Test status
Simulation time 3747457051 ps
CPU time 16.03 seconds
Started Jul 18 06:57:41 PM PDT 24
Finished Jul 18 06:57:58 PM PDT 24
Peak memory 226240 kb
Host smart-a1fc30b1-ad16-4c89-af64-29964b2dbf5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075181624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1075181624
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1380201411
Short name T855
Test name
Test status
Simulation time 228105704 ps
CPU time 8.3 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:58:00 PM PDT 24
Peak memory 226108 kb
Host smart-99278e4d-9a29-4ff6-ae6f-3a2e5e889a96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380201411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1380201411
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2194221648
Short name T311
Test name
Test status
Simulation time 337605630 ps
CPU time 13.4 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:58:04 PM PDT 24
Peak memory 218388 kb
Host smart-1936f31f-4c2b-4872-908a-c04bdeb87cca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194221648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2194221648
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3226806784
Short name T208
Test name
Test status
Simulation time 1094024300 ps
CPU time 7.05 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:57:57 PM PDT 24
Peak memory 225080 kb
Host smart-803cc9d9-e76b-4faf-922c-e867f7bb626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226806784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3226806784
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1968403655
Short name T563
Test name
Test status
Simulation time 39358391 ps
CPU time 2.97 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:57:51 PM PDT 24
Peak memory 214368 kb
Host smart-8c86db8f-4397-48ef-be00-169f0529a4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968403655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1968403655
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.371700023
Short name T450
Test name
Test status
Simulation time 487646128 ps
CPU time 21.64 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:58:15 PM PDT 24
Peak memory 251120 kb
Host smart-af3378d3-f475-41df-bd9a-999f516a9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371700023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.371700023
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1471518211
Short name T486
Test name
Test status
Simulation time 285195264 ps
CPU time 6.22 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:57:57 PM PDT 24
Peak memory 246660 kb
Host smart-ad8b71eb-9fa7-48b0-8243-06a9c752f4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471518211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1471518211
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4064103900
Short name T369
Test name
Test status
Simulation time 4450111848 ps
CPU time 97.21 seconds
Started Jul 18 06:57:42 PM PDT 24
Finished Jul 18 06:59:20 PM PDT 24
Peak memory 251208 kb
Host smart-ecd70645-1336-497b-9e90-73318149962f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064103900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4064103900
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3702493803
Short name T665
Test name
Test status
Simulation time 41543930339 ps
CPU time 2556.07 seconds
Started Jul 18 06:57:48 PM PDT 24
Finished Jul 18 07:40:31 PM PDT 24
Peak memory 1538616 kb
Host smart-1206c43d-f34c-4fbf-b04e-c58e0c18080c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3702493803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3702493803
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3387687470
Short name T214
Test name
Test status
Simulation time 41883723 ps
CPU time 0.92 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 211940 kb
Host smart-7e7cdd36-dbe0-4ac3-91e8-41019e8f80b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387687470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3387687470
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.472713821
Short name T324
Test name
Test status
Simulation time 115521954 ps
CPU time 1.31 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:38 PM PDT 24
Peak memory 209088 kb
Host smart-2e645e1d-6a9a-4faf-aec0-fc8d29716635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472713821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.472713821
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4078612542
Short name T534
Test name
Test status
Simulation time 21277552 ps
CPU time 1 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:40 PM PDT 24
Peak memory 208892 kb
Host smart-e6a022e7-4967-44f2-979f-e090274f94bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078612542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.4078612542
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2976809356
Short name T811
Test name
Test status
Simulation time 366344222 ps
CPU time 11.63 seconds
Started Jul 18 06:55:30 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 218304 kb
Host smart-ccaaadbf-1002-4780-9a38-71a84d1eb8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976809356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2976809356
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3801227092
Short name T435
Test name
Test status
Simulation time 272552990 ps
CPU time 3.17 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:40 PM PDT 24
Peak memory 217240 kb
Host smart-6bd39a69-e56f-45a9-b54e-e83cc816d59a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801227092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3801227092
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.626455518
Short name T243
Test name
Test status
Simulation time 1197422879 ps
CPU time 21.1 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:53 PM PDT 24
Peak memory 218444 kb
Host smart-9b67006d-e51d-4f30-80cd-c4a15057b8ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626455518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.626455518
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2124412951
Short name T697
Test name
Test status
Simulation time 504303999 ps
CPU time 3.77 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 217416 kb
Host smart-c3fcd676-c569-44fc-8f40-0e2246b52b90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124412951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
124412951
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2907129313
Short name T416
Test name
Test status
Simulation time 109531125 ps
CPU time 4.34 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:44 PM PDT 24
Peak memory 218256 kb
Host smart-fb58c13b-f458-48dc-8335-83b81ada9f3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907129313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2907129313
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3528786129
Short name T589
Test name
Test status
Simulation time 4095729354 ps
CPU time 12.23 seconds
Started Jul 18 06:55:28 PM PDT 24
Finished Jul 18 06:55:43 PM PDT 24
Peak memory 217972 kb
Host smart-5abac0a7-326a-479b-ad3c-c0001558f1cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528786129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3528786129
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.944924829
Short name T424
Test name
Test status
Simulation time 569632022 ps
CPU time 7.79 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 217716 kb
Host smart-b58c4538-6f83-4538-acd6-b04d93b92cac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944924829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.944924829
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2162582361
Short name T389
Test name
Test status
Simulation time 963482953 ps
CPU time 41.63 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:56:17 PM PDT 24
Peak memory 251064 kb
Host smart-f57e1848-736f-4edf-8d61-05a87345abd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162582361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2162582361
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2619327377
Short name T586
Test name
Test status
Simulation time 1684424327 ps
CPU time 18.11 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:57 PM PDT 24
Peak memory 251072 kb
Host smart-5467f4ff-b54f-4cb5-bd7f-052b0608e8cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619327377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2619327377
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2785619920
Short name T357
Test name
Test status
Simulation time 249190004 ps
CPU time 5.31 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:42 PM PDT 24
Peak memory 218328 kb
Host smart-c03bb1ef-103e-450a-8de7-c896d6cd4b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785619920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2785619920
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1375733497
Short name T689
Test name
Test status
Simulation time 958500157 ps
CPU time 5.86 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:37 PM PDT 24
Peak memory 214656 kb
Host smart-7b39e647-b0a6-47b8-8acb-9d9651ae9b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375733497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1375733497
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3398588060
Short name T49
Test name
Test status
Simulation time 226049859 ps
CPU time 36.53 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:56:15 PM PDT 24
Peak memory 270360 kb
Host smart-26f3ed67-2030-482d-be99-b601bfdbf3ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398588060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3398588060
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2892839554
Short name T347
Test name
Test status
Simulation time 729973739 ps
CPU time 12.98 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 226152 kb
Host smart-ac220b1d-0fd5-424c-8656-0230bbc378e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892839554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2892839554
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2758324674
Short name T246
Test name
Test status
Simulation time 564451947 ps
CPU time 8.53 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:44 PM PDT 24
Peak memory 226096 kb
Host smart-20c1d336-d3ce-49da-8b0d-bc4a5dcfdc16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758324674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2758324674
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2153737102
Short name T787
Test name
Test status
Simulation time 312889051 ps
CPU time 10.42 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:47 PM PDT 24
Peak memory 218316 kb
Host smart-b0ab7543-2e46-40b2-96d1-d621be61d850
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153737102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
153737102
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2026425597
Short name T844
Test name
Test status
Simulation time 1132092356 ps
CPU time 7.42 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:40 PM PDT 24
Peak memory 226332 kb
Host smart-06399048-37e7-491e-b64f-1ff3e411af09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026425597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2026425597
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.291376592
Short name T558
Test name
Test status
Simulation time 70102740 ps
CPU time 1.3 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:34 PM PDT 24
Peak memory 213756 kb
Host smart-36dcd916-f0c8-45a7-b81e-a6fcf3d9a705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291376592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.291376592
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2999058762
Short name T653
Test name
Test status
Simulation time 41408788 ps
CPU time 2.88 seconds
Started Jul 18 06:55:28 PM PDT 24
Finished Jul 18 06:55:34 PM PDT 24
Peak memory 218372 kb
Host smart-3564428a-0d9a-4c62-8db5-742cef1b63ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999058762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2999058762
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2482740567
Short name T169
Test name
Test status
Simulation time 3308777249 ps
CPU time 104.57 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:57:24 PM PDT 24
Peak memory 249620 kb
Host smart-be0ac7bf-c2a8-4bbb-8b52-eb18c5e46876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482740567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2482740567
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.851043571
Short name T73
Test name
Test status
Simulation time 13695596 ps
CPU time 1.13 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:37 PM PDT 24
Peak memory 217800 kb
Host smart-4bc9644c-26cb-4ce1-abae-2a0d1af81079
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851043571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.851043571
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.4228999256
Short name T503
Test name
Test status
Simulation time 14237959 ps
CPU time 1.05 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:54 PM PDT 24
Peak memory 208924 kb
Host smart-acf99ea8-efcf-4200-a35d-920fc9a22a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228999256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.4228999256
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2232970210
Short name T165
Test name
Test status
Simulation time 933028634 ps
CPU time 9.86 seconds
Started Jul 18 06:57:42 PM PDT 24
Finished Jul 18 06:57:53 PM PDT 24
Peak memory 226164 kb
Host smart-b47f24d1-c544-43db-a455-6829b5dccbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232970210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2232970210
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2247890578
Short name T290
Test name
Test status
Simulation time 1565562104 ps
CPU time 10.35 seconds
Started Jul 18 06:57:42 PM PDT 24
Finished Jul 18 06:57:53 PM PDT 24
Peak memory 217560 kb
Host smart-2e23a3f7-f0b3-4532-81bb-0ae05979ba94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247890578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2247890578
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.973073195
Short name T460
Test name
Test status
Simulation time 48658265 ps
CPU time 1.91 seconds
Started Jul 18 06:57:49 PM PDT 24
Finished Jul 18 06:57:57 PM PDT 24
Peak memory 218352 kb
Host smart-b5235a36-e69c-43ed-bccf-1c0da1054f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973073195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.973073195
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.378319800
Short name T835
Test name
Test status
Simulation time 668373900 ps
CPU time 19.89 seconds
Started Jul 18 06:57:43 PM PDT 24
Finished Jul 18 06:58:04 PM PDT 24
Peak memory 218532 kb
Host smart-524e3ad0-c44a-41f4-a642-a79c6117038e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378319800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.378319800
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2663211973
Short name T220
Test name
Test status
Simulation time 2367816454 ps
CPU time 9.79 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:58:03 PM PDT 24
Peak memory 226164 kb
Host smart-4a538d19-e21d-4ff2-8f5e-942b7f7045cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663211973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2663211973
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3119711307
Short name T63
Test name
Test status
Simulation time 2634348074 ps
CPU time 8.37 seconds
Started Jul 18 06:57:43 PM PDT 24
Finished Jul 18 06:57:53 PM PDT 24
Peak memory 218380 kb
Host smart-6a8e1611-9946-4f26-bfd8-0d1b9608a779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119711307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3119711307
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1264985025
Short name T495
Test name
Test status
Simulation time 724578879 ps
CPU time 9.41 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:58:03 PM PDT 24
Peak memory 226172 kb
Host smart-18ce4c2d-5907-4708-a830-541f9c461a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264985025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1264985025
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.108196437
Short name T59
Test name
Test status
Simulation time 64035127 ps
CPU time 2.29 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:56 PM PDT 24
Peak memory 214704 kb
Host smart-5fe4317a-31e7-4b13-b8ef-fc26608141f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108196437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.108196437
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1774957950
Short name T343
Test name
Test status
Simulation time 272829395 ps
CPU time 25.33 seconds
Started Jul 18 06:57:48 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 251116 kb
Host smart-31211700-5b13-4360-aa0f-e328d8f364b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774957950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1774957950
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3632382959
Short name T555
Test name
Test status
Simulation time 354268200 ps
CPU time 9.93 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:56 PM PDT 24
Peak memory 251120 kb
Host smart-dbafc04b-8c3b-4372-8b83-819408618dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632382959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3632382959
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1197486088
Short name T821
Test name
Test status
Simulation time 76059939042 ps
CPU time 595.34 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 07:07:45 PM PDT 24
Peak memory 228476 kb
Host smart-eaeacab6-ae81-4618-93ca-717f351e9e2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197486088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1197486088
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2573183340
Short name T316
Test name
Test status
Simulation time 12546115 ps
CPU time 1.04 seconds
Started Jul 18 06:57:47 PM PDT 24
Finished Jul 18 06:57:54 PM PDT 24
Peak memory 211952 kb
Host smart-23588582-8da4-4943-a336-afb3e9940888
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573183340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2573183340
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.469385890
Short name T438
Test name
Test status
Simulation time 15977854 ps
CPU time 1.07 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:54 PM PDT 24
Peak memory 208972 kb
Host smart-791752de-620a-4413-af75-89eabb25f67d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469385890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.469385890
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.598487222
Short name T746
Test name
Test status
Simulation time 999902491 ps
CPU time 10.8 seconds
Started Jul 18 06:57:43 PM PDT 24
Finished Jul 18 06:57:55 PM PDT 24
Peak memory 218456 kb
Host smart-27b79eff-b5e8-481a-bd0c-ec079a9d42c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598487222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.598487222
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2288345671
Short name T322
Test name
Test status
Simulation time 671455577 ps
CPU time 6.76 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:53 PM PDT 24
Peak memory 217840 kb
Host smart-dfd33a05-decd-456b-8885-c51623b01c8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288345671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2288345671
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1133125277
Short name T249
Test name
Test status
Simulation time 129842504 ps
CPU time 3.66 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:57 PM PDT 24
Peak memory 222856 kb
Host smart-3d3fe619-82f9-4e57-92d5-1d69fe9d85f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133125277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1133125277
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3917563710
Short name T398
Test name
Test status
Simulation time 253287904 ps
CPU time 10.28 seconds
Started Jul 18 06:57:47 PM PDT 24
Finished Jul 18 06:58:05 PM PDT 24
Peak memory 226084 kb
Host smart-6b421d24-0ae3-4e03-998a-e5a2de2c1a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917563710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3917563710
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3617240033
Short name T538
Test name
Test status
Simulation time 1233790300 ps
CPU time 16.96 seconds
Started Jul 18 06:57:47 PM PDT 24
Finished Jul 18 06:58:10 PM PDT 24
Peak memory 226104 kb
Host smart-00e079f7-b7fc-4eaf-bd9c-32165c409265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617240033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3617240033
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.232140074
Short name T298
Test name
Test status
Simulation time 1159978867 ps
CPU time 8.62 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:57:58 PM PDT 24
Peak memory 218312 kb
Host smart-145788de-09bb-4500-9992-d820963dd2bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232140074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.232140074
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2173854679
Short name T209
Test name
Test status
Simulation time 1945105267 ps
CPU time 11.28 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:58:04 PM PDT 24
Peak memory 226180 kb
Host smart-33b5ef4f-e929-41ef-96f0-9a12e59d7a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173854679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2173854679
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.267974797
Short name T223
Test name
Test status
Simulation time 41817177 ps
CPU time 1.1 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:53 PM PDT 24
Peak memory 213716 kb
Host smart-7cf07530-161f-4ad8-a137-2a4b093718eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267974797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.267974797
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2514105560
Short name T55
Test name
Test status
Simulation time 3764571121 ps
CPU time 27.95 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:58:16 PM PDT 24
Peak memory 251168 kb
Host smart-78478642-824a-4348-8edc-0cd3994ae7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514105560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2514105560
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3896946536
Short name T677
Test name
Test status
Simulation time 1378569170 ps
CPU time 4.28 seconds
Started Jul 18 06:57:42 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 226536 kb
Host smart-ea6a070b-dbd2-49c5-9f3d-c9b168a2b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896946536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3896946536
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3388615480
Short name T739
Test name
Test status
Simulation time 20859742154 ps
CPU time 219 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 07:01:27 PM PDT 24
Peak memory 280008 kb
Host smart-596cfa67-c8fd-474f-9943-87cadb995f35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388615480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3388615480
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2792126902
Short name T535
Test name
Test status
Simulation time 43158392 ps
CPU time 0.98 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:53 PM PDT 24
Peak memory 211992 kb
Host smart-f371d864-7c77-459d-9811-e4dc2f49c031
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792126902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2792126902
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.544813030
Short name T282
Test name
Test status
Simulation time 36255182 ps
CPU time 0.81 seconds
Started Jul 18 06:57:47 PM PDT 24
Finished Jul 18 06:57:54 PM PDT 24
Peak memory 208796 kb
Host smart-295c6269-d292-4cc9-a118-ecb6ff53e105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544813030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.544813030
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2390949594
Short name T480
Test name
Test status
Simulation time 1248091974 ps
CPU time 13.16 seconds
Started Jul 18 06:57:49 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 218304 kb
Host smart-ae7a9c99-37a4-409d-94de-ad34738d1dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390949594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2390949594
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.298282047
Short name T624
Test name
Test status
Simulation time 77550320 ps
CPU time 1.25 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:57:52 PM PDT 24
Peak memory 217244 kb
Host smart-694b42f3-9567-4c5a-8aa3-4d5fc495e4f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298282047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.298282047
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.4007743935
Short name T18
Test name
Test status
Simulation time 83035525 ps
CPU time 3.05 seconds
Started Jul 18 06:57:49 PM PDT 24
Finished Jul 18 06:57:59 PM PDT 24
Peak memory 218360 kb
Host smart-226a578e-d947-4846-8f2d-aac54a0d5244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007743935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.4007743935
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3033567513
Short name T730
Test name
Test status
Simulation time 325713427 ps
CPU time 10.14 seconds
Started Jul 18 06:57:47 PM PDT 24
Finished Jul 18 06:58:05 PM PDT 24
Peak memory 218384 kb
Host smart-792d11ae-710d-4904-bc4e-877847db07d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033567513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3033567513
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3285015372
Short name T329
Test name
Test status
Simulation time 208829704 ps
CPU time 10.05 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:56 PM PDT 24
Peak memory 226108 kb
Host smart-3386802a-d53b-4648-a5f4-17f0b9479aef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285015372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3285015372
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1889481303
Short name T801
Test name
Test status
Simulation time 2151722259 ps
CPU time 9.28 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:57:56 PM PDT 24
Peak memory 218376 kb
Host smart-faef87d7-a388-43f9-9fd8-ee6f2ef6449e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889481303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1889481303
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3011392062
Short name T464
Test name
Test status
Simulation time 1599979999 ps
CPU time 6.1 seconds
Started Jul 18 06:57:49 PM PDT 24
Finished Jul 18 06:58:02 PM PDT 24
Peak memory 225188 kb
Host smart-535b601a-3b81-41ed-8485-fc55dbead5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011392062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3011392062
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.555807599
Short name T355
Test name
Test status
Simulation time 91366771 ps
CPU time 1.53 seconds
Started Jul 18 06:57:49 PM PDT 24
Finished Jul 18 06:57:57 PM PDT 24
Peak memory 213916 kb
Host smart-4c58a7a4-3ef5-483c-addc-4badc40ea698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555807599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.555807599
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3148310097
Short name T546
Test name
Test status
Simulation time 2896970223 ps
CPU time 26 seconds
Started Jul 18 06:57:48 PM PDT 24
Finished Jul 18 06:58:21 PM PDT 24
Peak memory 251180 kb
Host smart-3c101535-4b0a-4791-a5eb-b5f8f1d62d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148310097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3148310097
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3770892723
Short name T299
Test name
Test status
Simulation time 157028853 ps
CPU time 2.94 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:56 PM PDT 24
Peak memory 222348 kb
Host smart-df7dab5e-2d55-4ba7-a9f0-93a5b70dae97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770892723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3770892723
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1986255289
Short name T849
Test name
Test status
Simulation time 1702264953 ps
CPU time 63.22 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:58:55 PM PDT 24
Peak memory 226128 kb
Host smart-5f31e5dc-02b7-41d4-8e64-0119d6815eba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986255289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1986255289
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1048595344
Short name T383
Test name
Test status
Simulation time 14798702 ps
CPU time 1.04 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:57:48 PM PDT 24
Peak memory 211900 kb
Host smart-1249b34f-ef76-4d36-a684-5a5c1bf0c7ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048595344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1048595344
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.4085468615
Short name T284
Test name
Test status
Simulation time 25845270 ps
CPU time 0.87 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:54 PM PDT 24
Peak memory 208808 kb
Host smart-7421e4a5-2af0-45aa-875d-93a1e2e8034b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085468615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4085468615
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2677067890
Short name T621
Test name
Test status
Simulation time 2846763115 ps
CPU time 10.6 seconds
Started Jul 18 06:57:50 PM PDT 24
Finished Jul 18 06:58:07 PM PDT 24
Peak memory 218432 kb
Host smart-36922ed1-33d9-49ac-9184-1966e3318420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677067890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2677067890
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2843062786
Short name T153
Test name
Test status
Simulation time 135938505 ps
CPU time 2.26 seconds
Started Jul 18 06:57:44 PM PDT 24
Finished Jul 18 06:57:47 PM PDT 24
Peak memory 217148 kb
Host smart-7745375b-4ac0-42d0-a99a-bc1f2789fa9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843062786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2843062786
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.358725823
Short name T217
Test name
Test status
Simulation time 756819746 ps
CPU time 2.49 seconds
Started Jul 18 06:57:50 PM PDT 24
Finished Jul 18 06:57:59 PM PDT 24
Peak memory 218440 kb
Host smart-5f9b4168-1dbd-4066-82fc-279be703caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358725823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.358725823
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1233795404
Short name T255
Test name
Test status
Simulation time 771099455 ps
CPU time 14.89 seconds
Started Jul 18 06:57:49 PM PDT 24
Finished Jul 18 06:58:10 PM PDT 24
Peak memory 226004 kb
Host smart-763b279c-8475-4fdd-ad68-5472519a88d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233795404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1233795404
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.879650917
Short name T537
Test name
Test status
Simulation time 188747163 ps
CPU time 6.42 seconds
Started Jul 18 06:57:48 PM PDT 24
Finished Jul 18 06:58:02 PM PDT 24
Peak memory 218308 kb
Host smart-439fd201-23ca-4ac1-a822-fd19888ee0ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879650917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.879650917
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2664017932
Short name T676
Test name
Test status
Simulation time 665896593 ps
CPU time 7.66 seconds
Started Jul 18 06:57:49 PM PDT 24
Finished Jul 18 06:58:03 PM PDT 24
Peak memory 226076 kb
Host smart-059081fd-183c-4de2-b03b-14a560322271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664017932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2664017932
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2978541651
Short name T215
Test name
Test status
Simulation time 16396994 ps
CPU time 1.06 seconds
Started Jul 18 06:57:50 PM PDT 24
Finished Jul 18 06:57:57 PM PDT 24
Peak memory 212044 kb
Host smart-0b94ff14-ab94-4dd2-a2e7-8046c32416d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978541651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2978541651
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.148836592
Short name T511
Test name
Test status
Simulation time 1308039890 ps
CPU time 31.83 seconds
Started Jul 18 06:57:45 PM PDT 24
Finished Jul 18 06:58:23 PM PDT 24
Peak memory 250888 kb
Host smart-58d23bd7-433b-4573-a631-9de89bef2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148836592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.148836592
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3876969209
Short name T827
Test name
Test status
Simulation time 176021232 ps
CPU time 6.55 seconds
Started Jul 18 06:57:46 PM PDT 24
Finished Jul 18 06:57:59 PM PDT 24
Peak memory 248196 kb
Host smart-b7e992ba-8df1-4c3b-89e2-cccb231ef1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876969209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3876969209
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3614203213
Short name T701
Test name
Test status
Simulation time 624601897 ps
CPU time 18.41 seconds
Started Jul 18 06:57:48 PM PDT 24
Finished Jul 18 06:58:13 PM PDT 24
Peak memory 226176 kb
Host smart-a2df532c-540a-4c1a-8855-485ec371cf22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614203213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3614203213
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.33401994
Short name T714
Test name
Test status
Simulation time 11116304 ps
CPU time 1.01 seconds
Started Jul 18 06:57:50 PM PDT 24
Finished Jul 18 06:57:57 PM PDT 24
Peak memory 211904 kb
Host smart-0e5a3f83-6cb7-4948-af8c-707dd467394a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33401994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctr
l_volatile_unlock_smoke.33401994
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1491091471
Short name T155
Test name
Test status
Simulation time 46273441 ps
CPU time 0.98 seconds
Started Jul 18 06:57:58 PM PDT 24
Finished Jul 18 06:58:01 PM PDT 24
Peak memory 209004 kb
Host smart-2dc5e8d2-bb1d-4151-baae-6762df6af521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491091471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1491091471
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.4001626995
Short name T540
Test name
Test status
Simulation time 1148438150 ps
CPU time 12.95 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 226024 kb
Host smart-b467519e-9c9f-4a86-abce-0fcf10a4d989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001626995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.4001626995
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.397599844
Short name T29
Test name
Test status
Simulation time 2334943735 ps
CPU time 14.55 seconds
Started Jul 18 06:58:10 PM PDT 24
Finished Jul 18 06:58:30 PM PDT 24
Peak memory 217404 kb
Host smart-8efdd32d-bd56-4414-9832-4a50a004467d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397599844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.397599844
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2085467104
Short name T723
Test name
Test status
Simulation time 140341978 ps
CPU time 2.45 seconds
Started Jul 18 06:58:00 PM PDT 24
Finished Jul 18 06:58:04 PM PDT 24
Peak memory 222264 kb
Host smart-0a4e1d4b-7682-46c2-b402-061ac2d32868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085467104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2085467104
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2853226696
Short name T588
Test name
Test status
Simulation time 887019439 ps
CPU time 12.13 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:19 PM PDT 24
Peak memory 225936 kb
Host smart-de2fb6dc-2e10-415a-b6d6-a67b395d60b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853226696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2853226696
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3960892837
Short name T593
Test name
Test status
Simulation time 3451068750 ps
CPU time 13.01 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 06:58:23 PM PDT 24
Peak memory 226072 kb
Host smart-c71beaba-de97-4d1c-918a-8089435dfaf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960892837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3960892837
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.579414849
Short name T774
Test name
Test status
Simulation time 219103400 ps
CPU time 6.24 seconds
Started Jul 18 06:57:58 PM PDT 24
Finished Jul 18 06:58:06 PM PDT 24
Peak memory 225276 kb
Host smart-1839dc09-0d43-43f3-b0c1-64b25c12f563
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579414849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.579414849
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.140232934
Short name T367
Test name
Test status
Simulation time 2432517265 ps
CPU time 9.88 seconds
Started Jul 18 06:58:03 PM PDT 24
Finished Jul 18 06:58:18 PM PDT 24
Peak memory 226312 kb
Host smart-a4d62880-50bb-405a-ad9d-1886dde1753e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140232934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.140232934
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3041741435
Short name T735
Test name
Test status
Simulation time 116808282 ps
CPU time 3.4 seconds
Started Jul 18 06:57:53 PM PDT 24
Finished Jul 18 06:58:01 PM PDT 24
Peak memory 217796 kb
Host smart-5be485a0-b7c0-4caf-bcb8-890080fd2e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041741435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3041741435
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.164769242
Short name T747
Test name
Test status
Simulation time 2681439646 ps
CPU time 29.2 seconds
Started Jul 18 06:57:47 PM PDT 24
Finished Jul 18 06:58:24 PM PDT 24
Peak memory 251172 kb
Host smart-8cb7e60a-ea97-4cad-82df-907d193dd2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164769242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.164769242
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.120457835
Short name T151
Test name
Test status
Simulation time 2944543325 ps
CPU time 11.54 seconds
Started Jul 18 06:57:49 PM PDT 24
Finished Jul 18 06:58:07 PM PDT 24
Peak memory 251088 kb
Host smart-edcbfb02-cd10-49dd-a776-97500eda1b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120457835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.120457835
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3831621910
Short name T323
Test name
Test status
Simulation time 13288597633 ps
CPU time 124.83 seconds
Started Jul 18 06:58:04 PM PDT 24
Finished Jul 18 07:00:15 PM PDT 24
Peak memory 275496 kb
Host smart-46c0be3e-c432-4a17-9325-5c057c0aa94d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831621910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3831621910
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1980602381
Short name T640
Test name
Test status
Simulation time 11670420101 ps
CPU time 258.68 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 07:02:24 PM PDT 24
Peak memory 284096 kb
Host smart-cc2a1cc8-406a-41f4-b8ae-7b3a797921ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1980602381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.1980602381
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2005100964
Short name T742
Test name
Test status
Simulation time 78168473 ps
CPU time 1.09 seconds
Started Jul 18 06:57:53 PM PDT 24
Finished Jul 18 06:57:59 PM PDT 24
Peak memory 213136 kb
Host smart-f2ea741d-df93-4053-83ee-ff2dee6cabf4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005100964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2005100964
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.397090851
Short name T838
Test name
Test status
Simulation time 62897516 ps
CPU time 0.93 seconds
Started Jul 18 06:58:03 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 208892 kb
Host smart-a2d1cb36-7d5d-45b0-99c8-6bcea968516b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397090851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.397090851
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2607698973
Short name T441
Test name
Test status
Simulation time 582759018 ps
CPU time 17.95 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:23 PM PDT 24
Peak memory 226172 kb
Host smart-31866861-3666-4881-a193-306df2739eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607698973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2607698973
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.477711770
Short name T28
Test name
Test status
Simulation time 256392325 ps
CPU time 2.94 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:10 PM PDT 24
Peak memory 217256 kb
Host smart-369a3d7b-aae7-4aad-ad35-6fcdf6a3216f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477711770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.477711770
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2602504721
Short name T449
Test name
Test status
Simulation time 385200887 ps
CPU time 3.13 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 218404 kb
Host smart-a18584fb-9046-4508-909b-98db59205b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602504721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2602504721
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.339009767
Short name T430
Test name
Test status
Simulation time 1715235871 ps
CPU time 14.19 seconds
Started Jul 18 07:04:37 PM PDT 24
Finished Jul 18 07:04:52 PM PDT 24
Peak memory 219028 kb
Host smart-f3c68b8e-3983-4a6e-8285-4e9b759e97f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339009767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.339009767
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.4140671073
Short name T283
Test name
Test status
Simulation time 336282990 ps
CPU time 8.79 seconds
Started Jul 18 06:58:00 PM PDT 24
Finished Jul 18 06:58:12 PM PDT 24
Peak memory 226092 kb
Host smart-211e428d-cedb-4d6d-8918-dd72233b6811
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140671073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.4140671073
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4251065659
Short name T635
Test name
Test status
Simulation time 197236044 ps
CPU time 6.27 seconds
Started Jul 18 06:58:00 PM PDT 24
Finished Jul 18 06:58:10 PM PDT 24
Peak memory 218316 kb
Host smart-593b9699-832f-405a-8ad0-1f1d8c99bc0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251065659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4251065659
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3755472718
Short name T786
Test name
Test status
Simulation time 484026456 ps
CPU time 16.64 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:24 PM PDT 24
Peak memory 218424 kb
Host smart-166993a3-4c13-4319-8926-638906cd47da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755472718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3755472718
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3059552083
Short name T83
Test name
Test status
Simulation time 158178290 ps
CPU time 2.93 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:08 PM PDT 24
Peak memory 217792 kb
Host smart-9b9967b2-8111-4206-9c81-e4c9d053f2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059552083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3059552083
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1036985623
Short name T597
Test name
Test status
Simulation time 2076591400 ps
CPU time 33.51 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:38 PM PDT 24
Peak memory 251100 kb
Host smart-02bced80-b748-4378-a1b2-e1812a5e7f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036985623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1036985623
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.742567866
Short name T476
Test name
Test status
Simulation time 50513649 ps
CPU time 5.85 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:10 PM PDT 24
Peak memory 250680 kb
Host smart-1dce4d2d-0b17-40f8-bec3-8bb181f2ea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742567866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.742567866
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.4080620773
Short name T345
Test name
Test status
Simulation time 6101789815 ps
CPU time 136.54 seconds
Started Jul 18 06:58:03 PM PDT 24
Finished Jul 18 07:00:24 PM PDT 24
Peak memory 305352 kb
Host smart-b73cd4d4-9d00-48c7-8799-c0645e6fcba1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080620773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.4080620773
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.514601253
Short name T711
Test name
Test status
Simulation time 73593216135 ps
CPU time 314.6 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 07:03:21 PM PDT 24
Peak memory 370984 kb
Host smart-7bb0ad8d-747f-4a70-ac3d-e7d0da429800
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=514601253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.514601253
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.80955096
Short name T216
Test name
Test status
Simulation time 12284731 ps
CPU time 0.98 seconds
Started Jul 18 06:58:04 PM PDT 24
Finished Jul 18 06:58:11 PM PDT 24
Peak memory 211936 kb
Host smart-063bf91c-2a4c-4232-a816-eb01e7a42686
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80955096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctr
l_volatile_unlock_smoke.80955096
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3651696249
Short name T315
Test name
Test status
Simulation time 46032196 ps
CPU time 0.86 seconds
Started Jul 18 06:58:00 PM PDT 24
Finished Jul 18 06:58:04 PM PDT 24
Peak memory 208828 kb
Host smart-fa24e484-61ac-45f9-83de-7e9f90be5d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651696249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3651696249
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.486244272
Short name T778
Test name
Test status
Simulation time 1529358525 ps
CPU time 16.24 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 06:58:27 PM PDT 24
Peak memory 218548 kb
Host smart-d934d2c8-c7f0-4f4b-9f75-e6f4aacb35b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486244272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.486244272
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1778918723
Short name T276
Test name
Test status
Simulation time 291232419 ps
CPU time 2.37 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:08 PM PDT 24
Peak memory 217244 kb
Host smart-c8135fcb-a21c-451a-a11c-c9b7b0ab7960
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778918723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1778918723
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3963732519
Short name T582
Test name
Test status
Simulation time 95723378 ps
CPU time 3.23 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 06:58:14 PM PDT 24
Peak memory 218380 kb
Host smart-248256f8-45c2-4be4-8160-3714609e8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963732519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3963732519
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3383084343
Short name T150
Test name
Test status
Simulation time 270843090 ps
CPU time 12.31 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 225700 kb
Host smart-67a06c41-aa1e-49a6-a04a-eacf89e16f5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383084343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3383084343
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2540445654
Short name T729
Test name
Test status
Simulation time 1731188122 ps
CPU time 12.44 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:17 PM PDT 24
Peak memory 226112 kb
Host smart-1cd89502-bfe7-4acb-971e-1dd89bedb876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540445654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2540445654
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2882951818
Short name T627
Test name
Test status
Simulation time 2743267260 ps
CPU time 15.99 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 218564 kb
Host smart-88e37b86-34d6-4145-a73e-61c3e476fd2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882951818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2882951818
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3652746030
Short name T47
Test name
Test status
Simulation time 303952095 ps
CPU time 12.12 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:17 PM PDT 24
Peak memory 226168 kb
Host smart-764e9030-557b-4303-92d9-7d103849efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652746030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3652746030
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.336418896
Short name T656
Test name
Test status
Simulation time 143321310 ps
CPU time 1.97 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 214056 kb
Host smart-3663c369-c1ba-421e-9ea0-3f4bf842b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336418896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.336418896
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2061223759
Short name T851
Test name
Test status
Simulation time 538909556 ps
CPU time 19.59 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:27 PM PDT 24
Peak memory 251104 kb
Host smart-498b8317-7514-4e23-b35d-0146bae8f35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061223759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2061223759
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3667771634
Short name T513
Test name
Test status
Simulation time 78039946 ps
CPU time 7.2 seconds
Started Jul 18 06:58:06 PM PDT 24
Finished Jul 18 06:58:19 PM PDT 24
Peak memory 247048 kb
Host smart-3c32007d-614f-4ada-971a-e44422eaf346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667771634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3667771634
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3296937527
Short name T596
Test name
Test status
Simulation time 42893754297 ps
CPU time 175.02 seconds
Started Jul 18 06:58:04 PM PDT 24
Finished Jul 18 07:01:05 PM PDT 24
Peak memory 251076 kb
Host smart-bbcbae5d-8c3a-4cd4-9765-435841330173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296937527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3296937527
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4076062300
Short name T461
Test name
Test status
Simulation time 11394260 ps
CPU time 0.87 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:08 PM PDT 24
Peak memory 211988 kb
Host smart-fd3be4ea-c039-47be-8fac-29e819a3f04d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076062300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4076062300
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.531768760
Short name T256
Test name
Test status
Simulation time 23460149 ps
CPU time 1.28 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 209116 kb
Host smart-b6b215a2-9595-4763-9c51-70dc7ffe1524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531768760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.531768760
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.4027591961
Short name T304
Test name
Test status
Simulation time 284073318 ps
CPU time 12.63 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 06:58:23 PM PDT 24
Peak memory 226184 kb
Host smart-b758670f-4980-430e-8787-c0ced50b0239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027591961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.4027591961
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1660120354
Short name T352
Test name
Test status
Simulation time 342258154 ps
CPU time 3.73 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:11 PM PDT 24
Peak memory 217260 kb
Host smart-ea366de1-a11e-4d1e-801a-dff6130af53d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660120354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1660120354
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2390878803
Short name T509
Test name
Test status
Simulation time 159104838 ps
CPU time 3.86 seconds
Started Jul 18 06:57:59 PM PDT 24
Finished Jul 18 06:58:05 PM PDT 24
Peak memory 218364 kb
Host smart-b5f76d33-62c9-4e31-9d81-1f934ccfb442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390878803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2390878803
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1742147601
Short name T591
Test name
Test status
Simulation time 369678508 ps
CPU time 17.15 seconds
Started Jul 18 06:58:04 PM PDT 24
Finished Jul 18 06:58:26 PM PDT 24
Peak memory 226112 kb
Host smart-06dc0545-1b3e-4e2f-8309-60bb7b3566cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742147601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1742147601
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.621912609
Short name T411
Test name
Test status
Simulation time 366427988 ps
CPU time 15.93 seconds
Started Jul 18 06:58:10 PM PDT 24
Finished Jul 18 06:58:31 PM PDT 24
Peak memory 226104 kb
Host smart-8c204f39-35ee-4377-a6cc-38932e61479f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621912609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.621912609
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1909138271
Short name T720
Test name
Test status
Simulation time 339749481 ps
CPU time 7.26 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:12 PM PDT 24
Peak memory 218312 kb
Host smart-c4695a6d-ef1d-448a-9e1f-8fea4e7b2b6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909138271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1909138271
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3248025437
Short name T661
Test name
Test status
Simulation time 282113085 ps
CPU time 9.64 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:15 PM PDT 24
Peak memory 226176 kb
Host smart-79190423-f83e-4054-9781-9476d614724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248025437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3248025437
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.967398919
Short name T551
Test name
Test status
Simulation time 31392844 ps
CPU time 1.8 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 217864 kb
Host smart-bf07fac3-b8d0-4ed3-b656-7005dc20759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967398919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.967398919
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.459189196
Short name T413
Test name
Test status
Simulation time 271268627 ps
CPU time 29.37 seconds
Started Jul 18 06:58:00 PM PDT 24
Finished Jul 18 06:58:31 PM PDT 24
Peak memory 251184 kb
Host smart-8be8e5e6-849e-4cda-ae09-f096756f54ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459189196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.459189196
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2436831294
Short name T392
Test name
Test status
Simulation time 989830149 ps
CPU time 7.88 seconds
Started Jul 18 06:58:00 PM PDT 24
Finished Jul 18 06:58:12 PM PDT 24
Peak memory 247436 kb
Host smart-22328e63-8172-40a9-a694-dfebbed93015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436831294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2436831294
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3194154836
Short name T734
Test name
Test status
Simulation time 3783708216 ps
CPU time 33.49 seconds
Started Jul 18 06:58:03 PM PDT 24
Finished Jul 18 06:58:42 PM PDT 24
Peak memory 268076 kb
Host smart-8b48fc6b-7663-4e9c-9f54-eef3e6740252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194154836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3194154836
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1305099944
Short name T104
Test name
Test status
Simulation time 45983087282 ps
CPU time 2980.93 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 07:47:52 PM PDT 24
Peak memory 932088 kb
Host smart-9811b317-7719-4f0f-8b9c-c6677cdf65ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1305099944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1305099944
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.896685908
Short name T673
Test name
Test status
Simulation time 30968723 ps
CPU time 0.73 seconds
Started Jul 18 06:57:58 PM PDT 24
Finished Jul 18 06:58:01 PM PDT 24
Peak memory 207504 kb
Host smart-01c75d6d-201e-438a-811c-3eddd73ba114
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896685908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.896685908
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1994833053
Short name T302
Test name
Test status
Simulation time 1095623439 ps
CPU time 21.04 seconds
Started Jul 18 06:58:04 PM PDT 24
Finished Jul 18 06:58:30 PM PDT 24
Peak memory 218400 kb
Host smart-afd59e86-8236-4a13-b400-9e80771de492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994833053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1994833053
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.502775021
Short name T454
Test name
Test status
Simulation time 1165755609 ps
CPU time 6.14 seconds
Started Jul 18 06:58:06 PM PDT 24
Finished Jul 18 06:58:18 PM PDT 24
Peak memory 217472 kb
Host smart-5fbe3691-0313-48f9-804a-537f0c909e91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502775021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.502775021
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2961601101
Short name T2
Test name
Test status
Simulation time 79952417 ps
CPU time 1.54 seconds
Started Jul 18 06:58:13 PM PDT 24
Finished Jul 18 06:58:18 PM PDT 24
Peak memory 218352 kb
Host smart-26598fab-d652-4d0c-9a4f-7a3b73ae57c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961601101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2961601101
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3267352688
Short name T281
Test name
Test status
Simulation time 252815338 ps
CPU time 12.31 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:19 PM PDT 24
Peak memory 226168 kb
Host smart-f469fc5f-99da-4083-90f1-28339b16d1a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267352688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3267352688
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2561043370
Short name T567
Test name
Test status
Simulation time 2023714589 ps
CPU time 14.09 seconds
Started Jul 18 06:58:06 PM PDT 24
Finished Jul 18 06:58:26 PM PDT 24
Peak memory 226108 kb
Host smart-e24cf2b8-c0b1-4954-93a1-d39ff25ce327
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561043370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2561043370
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.600348410
Short name T738
Test name
Test status
Simulation time 348548581 ps
CPU time 8.81 seconds
Started Jul 18 06:58:07 PM PDT 24
Finished Jul 18 06:58:21 PM PDT 24
Peak memory 218372 kb
Host smart-2d646b3a-3cb7-4272-bc12-f5dfe6cc5ff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600348410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.600348410
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2377880511
Short name T42
Test name
Test status
Simulation time 487286394 ps
CPU time 9.7 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 225652 kb
Host smart-0299d2f7-c019-4c79-9cc8-d8eaa35e51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377880511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2377880511
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.376661843
Short name T834
Test name
Test status
Simulation time 377101608 ps
CPU time 5.18 seconds
Started Jul 18 06:58:00 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 217796 kb
Host smart-9d6d893b-1d3e-41d5-9140-1ab1708b01a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376661843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.376661843
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2300610585
Short name T314
Test name
Test status
Simulation time 253386418 ps
CPU time 23.34 seconds
Started Jul 18 06:58:03 PM PDT 24
Finished Jul 18 06:58:32 PM PDT 24
Peak memory 246656 kb
Host smart-10117bf1-dc02-467b-b901-53a390f14d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300610585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2300610585
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3304785377
Short name T478
Test name
Test status
Simulation time 123636594 ps
CPU time 3.56 seconds
Started Jul 18 06:58:03 PM PDT 24
Finished Jul 18 06:58:12 PM PDT 24
Peak memory 218300 kb
Host smart-95fafc29-0148-4072-a6da-b554033ffb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304785377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3304785377
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2059053119
Short name T61
Test name
Test status
Simulation time 82174388685 ps
CPU time 245.64 seconds
Started Jul 18 06:58:07 PM PDT 24
Finished Jul 18 07:02:18 PM PDT 24
Peak memory 283864 kb
Host smart-2d8f52df-c35c-41eb-a6a4-77d95d1b2eb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059053119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2059053119
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1300385051
Short name T139
Test name
Test status
Simulation time 26225842465 ps
CPU time 125.53 seconds
Started Jul 18 06:58:07 PM PDT 24
Finished Jul 18 07:00:18 PM PDT 24
Peak memory 267400 kb
Host smart-647270e2-1e1e-4500-960b-dc47635c4587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1300385051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1300385051
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2071360224
Short name T654
Test name
Test status
Simulation time 12918677 ps
CPU time 0.99 seconds
Started Jul 18 06:58:10 PM PDT 24
Finished Jul 18 06:58:16 PM PDT 24
Peak memory 211988 kb
Host smart-7077c7fa-b1f1-46f5-925e-901628deb2a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071360224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2071360224
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3097667571
Short name T442
Test name
Test status
Simulation time 48864286 ps
CPU time 0.86 seconds
Started Jul 18 06:58:03 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 208824 kb
Host smart-263018fe-2070-47db-a80d-d35d47928eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097667571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3097667571
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2588273345
Short name T434
Test name
Test status
Simulation time 1140829313 ps
CPU time 11.66 seconds
Started Jul 18 06:58:09 PM PDT 24
Finished Jul 18 06:58:26 PM PDT 24
Peak memory 218384 kb
Host smart-11ed10de-0e89-4dc1-95f9-578178ae2bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588273345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2588273345
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.300295814
Short name T334
Test name
Test status
Simulation time 127687643 ps
CPU time 3.84 seconds
Started Jul 18 06:58:06 PM PDT 24
Finished Jul 18 06:58:16 PM PDT 24
Peak memory 217224 kb
Host smart-14a832d3-badb-4658-b9c7-9542254fe176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300295814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.300295814
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2228534613
Short name T356
Test name
Test status
Simulation time 26704493 ps
CPU time 2.03 seconds
Started Jul 18 06:58:02 PM PDT 24
Finished Jul 18 06:58:09 PM PDT 24
Peak memory 218292 kb
Host smart-04b00b40-ce97-4c38-bf88-3f7366b9e1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228534613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2228534613
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1845667682
Short name T443
Test name
Test status
Simulation time 303464831 ps
CPU time 12.39 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 06:58:23 PM PDT 24
Peak memory 226164 kb
Host smart-574b54d5-6d3e-4804-b6a4-959e78630882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845667682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1845667682
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2774947281
Short name T610
Test name
Test status
Simulation time 2197218633 ps
CPU time 15.23 seconds
Started Jul 18 06:58:01 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 226172 kb
Host smart-6bc69bd1-eadc-429c-96d5-59ecc82de72c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774947281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2774947281
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.742347915
Short name T506
Test name
Test status
Simulation time 795969352 ps
CPU time 5.95 seconds
Started Jul 18 06:58:09 PM PDT 24
Finished Jul 18 06:58:20 PM PDT 24
Peak memory 218312 kb
Host smart-da30cf57-d924-4009-865b-f582908cc940
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742347915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.742347915
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3034771215
Short name T578
Test name
Test status
Simulation time 665829896 ps
CPU time 10.34 seconds
Started Jul 18 06:58:03 PM PDT 24
Finished Jul 18 06:58:19 PM PDT 24
Peak memory 226168 kb
Host smart-31df2a03-3254-46a2-a3bd-e85777e012b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034771215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3034771215
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.321257425
Short name T82
Test name
Test status
Simulation time 545170952 ps
CPU time 1.89 seconds
Started Jul 18 06:58:06 PM PDT 24
Finished Jul 18 06:58:14 PM PDT 24
Peak memory 217860 kb
Host smart-aa258c16-5946-4802-b573-60b797d1a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321257425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.321257425
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.383414309
Short name T523
Test name
Test status
Simulation time 1945042220 ps
CPU time 24.24 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 06:58:35 PM PDT 24
Peak memory 244868 kb
Host smart-fd31eacb-c60e-49a2-bbf4-2bf8cc92c41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383414309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.383414309
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1179410757
Short name T726
Test name
Test status
Simulation time 271858729 ps
CPU time 7.43 seconds
Started Jul 18 06:58:08 PM PDT 24
Finished Jul 18 06:58:21 PM PDT 24
Peak memory 250936 kb
Host smart-acd3ccae-5d1c-44fa-8ab7-71c8a97958e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179410757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1179410757
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3440843069
Short name T306
Test name
Test status
Simulation time 2276622649 ps
CPU time 107.74 seconds
Started Jul 18 06:58:09 PM PDT 24
Finished Jul 18 07:00:02 PM PDT 24
Peak memory 252196 kb
Host smart-f592527c-db66-400f-93a4-52578a35df6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440843069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3440843069
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.1647768360
Short name T141
Test name
Test status
Simulation time 13425612185 ps
CPU time 538.38 seconds
Started Jul 18 06:58:05 PM PDT 24
Finished Jul 18 07:07:09 PM PDT 24
Peak memory 333208 kb
Host smart-475306e1-7ff3-46b8-9ef7-c46a68f1e46f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1647768360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.1647768360
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4259918633
Short name T10
Test name
Test status
Simulation time 12662242 ps
CPU time 1.08 seconds
Started Jul 18 06:58:06 PM PDT 24
Finished Jul 18 06:58:13 PM PDT 24
Peak memory 211748 kb
Host smart-936dae1b-6815-4b25-bf70-552b7976f55f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259918633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.4259918633
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.433352929
Short name T313
Test name
Test status
Simulation time 40597545 ps
CPU time 0.98 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:40 PM PDT 24
Peak memory 208968 kb
Host smart-ff1e37a1-fbf1-41ca-938e-5f38303788a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433352929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.433352929
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.4270454404
Short name T206
Test name
Test status
Simulation time 41855664 ps
CPU time 0.78 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:40 PM PDT 24
Peak memory 209088 kb
Host smart-fb0635f3-ba20-4f74-831c-5097dcda36d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270454404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.4270454404
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4010503430
Short name T543
Test name
Test status
Simulation time 1042439227 ps
CPU time 12.57 seconds
Started Jul 18 06:55:37 PM PDT 24
Finished Jul 18 06:55:54 PM PDT 24
Peak memory 218368 kb
Host smart-689c32e7-e26c-4a42-ac03-598b49f72059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010503430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4010503430
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2280448206
Short name T758
Test name
Test status
Simulation time 1888869702 ps
CPU time 7 seconds
Started Jul 18 06:55:35 PM PDT 24
Finished Jul 18 06:55:48 PM PDT 24
Peak memory 217504 kb
Host smart-41ccadb7-2c94-4228-856f-8b7aec609cca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280448206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2280448206
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1464519009
Short name T861
Test name
Test status
Simulation time 6253887915 ps
CPU time 23.12 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:56:02 PM PDT 24
Peak memory 218980 kb
Host smart-75ed068f-ab42-4d58-b431-62c5b98bb2c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464519009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1464519009
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2601713291
Short name T364
Test name
Test status
Simulation time 844561484 ps
CPU time 2.08 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 217916 kb
Host smart-b6075107-93b3-46cc-82c4-2e706459fb58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601713291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
601713291
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2645730632
Short name T781
Test name
Test status
Simulation time 230022024 ps
CPU time 2.58 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 218312 kb
Host smart-e9fba8db-a5d6-4dd5-8b82-a061def7375c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645730632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2645730632
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2954484627
Short name T406
Test name
Test status
Simulation time 1249397888 ps
CPU time 19.96 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:55:58 PM PDT 24
Peak memory 217724 kb
Host smart-68bc46ca-d4f6-4b79-b331-023973be7699
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954484627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2954484627
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3665338671
Short name T765
Test name
Test status
Simulation time 333258413 ps
CPU time 2.56 seconds
Started Jul 18 06:55:35 PM PDT 24
Finished Jul 18 06:55:43 PM PDT 24
Peak memory 217728 kb
Host smart-ca74bebe-075a-4fed-9d0c-b0b7f6213c4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665338671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3665338671
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3628607144
Short name T575
Test name
Test status
Simulation time 737543704 ps
CPU time 23.28 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:56:01 PM PDT 24
Peak memory 251048 kb
Host smart-26802054-bdfa-4d6b-bc74-5801e4d0b06c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628607144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3628607144
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2010536921
Short name T704
Test name
Test status
Simulation time 389606135 ps
CPU time 11.11 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:50 PM PDT 24
Peak memory 250612 kb
Host smart-e9761d9b-edd0-49dc-86c9-0f6d890364ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010536921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2010536921
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.994221693
Short name T592
Test name
Test status
Simulation time 174772169 ps
CPU time 2.27 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:55:40 PM PDT 24
Peak memory 218368 kb
Host smart-9f8dca97-7aaa-4bcf-8241-290a6cc9b616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994221693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.994221693
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.220564951
Short name T181
Test name
Test status
Simulation time 584532589 ps
CPU time 11.23 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:50 PM PDT 24
Peak memory 217800 kb
Host smart-e64a47f4-f87c-4def-923f-6eff779f5d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220564951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.220564951
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1362189831
Short name T488
Test name
Test status
Simulation time 466394407 ps
CPU time 12.13 seconds
Started Jul 18 06:55:29 PM PDT 24
Finished Jul 18 06:55:44 PM PDT 24
Peak memory 226196 kb
Host smart-8a9b65cb-406d-4160-9553-910ce080d6f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362189831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1362189831
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3017869760
Short name T556
Test name
Test status
Simulation time 285397213 ps
CPU time 8.68 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:55:47 PM PDT 24
Peak memory 226008 kb
Host smart-a9db5775-ad82-407a-91ae-bcc5a0f4fcfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017869760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3017869760
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3415041273
Short name T113
Test name
Test status
Simulation time 935864868 ps
CPU time 8.22 seconds
Started Jul 18 06:55:31 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 226112 kb
Host smart-e32518ee-a536-4971-961d-9bef211eb163
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415041273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
415041273
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1649749830
Short name T700
Test name
Test status
Simulation time 803340761 ps
CPU time 8.36 seconds
Started Jul 18 06:55:36 PM PDT 24
Finished Jul 18 06:55:49 PM PDT 24
Peak memory 226180 kb
Host smart-18f769b0-d149-4a69-9475-6d53617f54b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649749830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1649749830
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1205167325
Short name T604
Test name
Test status
Simulation time 160309144 ps
CPU time 2.26 seconds
Started Jul 18 06:55:37 PM PDT 24
Finished Jul 18 06:55:44 PM PDT 24
Peak memory 214600 kb
Host smart-1597e45c-9c4c-419c-8a80-97c9d5c7e993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205167325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1205167325
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3698781546
Short name T382
Test name
Test status
Simulation time 307818060 ps
CPU time 23.49 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:56:01 PM PDT 24
Peak memory 251112 kb
Host smart-daca2d87-55e9-4c5f-a865-a7a9d422a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698781546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3698781546
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.514504671
Short name T831
Test name
Test status
Simulation time 828622458 ps
CPU time 7.09 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:47 PM PDT 24
Peak memory 251112 kb
Host smart-a92d8170-599a-419e-abfe-1e5c8b2e6eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514504671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.514504671
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3738767603
Short name T286
Test name
Test status
Simulation time 7386001584 ps
CPU time 69.96 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:56:48 PM PDT 24
Peak memory 259180 kb
Host smart-f0cecf24-fc27-46ad-8534-17c119e4aae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738767603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3738767603
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3010869845
Short name T144
Test name
Test status
Simulation time 22163136836 ps
CPU time 794.78 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 07:08:55 PM PDT 24
Peak memory 333212 kb
Host smart-18bbc51b-84ea-444d-a241-4cb3634f70be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3010869845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3010869845
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.233866401
Short name T536
Test name
Test status
Simulation time 34548031 ps
CPU time 0.99 seconds
Started Jul 18 06:55:32 PM PDT 24
Finished Jul 18 06:55:39 PM PDT 24
Peak memory 213048 kb
Host smart-59371fbe-d8c9-4f6a-b40c-3d9a3747798a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233866401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.233866401
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3357920815
Short name T147
Test name
Test status
Simulation time 17325202 ps
CPU time 0.91 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:55:51 PM PDT 24
Peak memory 208920 kb
Host smart-d0e9ee88-5cfe-4547-94a5-bd382d50cde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357920815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3357920815
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2798552965
Short name T784
Test name
Test status
Simulation time 13086939 ps
CPU time 0.88 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 208776 kb
Host smart-a9df6da4-cc63-4acd-98c9-081a678ea322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798552965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2798552965
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2201657713
Short name T339
Test name
Test status
Simulation time 230577127 ps
CPU time 12.05 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:52 PM PDT 24
Peak memory 218372 kb
Host smart-8fc8fca8-1789-4d93-baa7-17af154b0e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201657713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2201657713
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1328837186
Short name T30
Test name
Test status
Simulation time 572334745 ps
CPU time 2.31 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:55:57 PM PDT 24
Peak memory 217200 kb
Host smart-92022639-54b3-46d2-a9c7-a51594aa4620
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328837186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1328837186
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3945570307
Short name T858
Test name
Test status
Simulation time 3356525032 ps
CPU time 50.51 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:56:45 PM PDT 24
Peak memory 218436 kb
Host smart-780a1437-b998-4672-a7c9-8e6ef652c15e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945570307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3945570307
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3984463142
Short name T837
Test name
Test status
Simulation time 83022394 ps
CPU time 1.74 seconds
Started Jul 18 06:55:46 PM PDT 24
Finished Jul 18 06:55:53 PM PDT 24
Peak memory 217848 kb
Host smart-1ce38f8a-7138-4e90-9654-d3f4ab7ae251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984463142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
984463142
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1116274704
Short name T152
Test name
Test status
Simulation time 1202235907 ps
CPU time 5.62 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:55:58 PM PDT 24
Peak memory 218296 kb
Host smart-09dd1f41-061f-4981-9af7-0a8332a1176a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116274704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1116274704
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2735889465
Short name T70
Test name
Test status
Simulation time 626931049 ps
CPU time 16.31 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:56:08 PM PDT 24
Peak memory 217704 kb
Host smart-979efd29-e9a6-46a4-92c4-03bb1241e266
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735889465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2735889465
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2854575075
Short name T719
Test name
Test status
Simulation time 306800702 ps
CPU time 4.44 seconds
Started Jul 18 06:55:35 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 217704 kb
Host smart-8db72079-ec9b-49be-bf2b-e23f9a472329
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854575075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2854575075
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2557078328
Short name T414
Test name
Test status
Simulation time 4924042822 ps
CPU time 41.94 seconds
Started Jul 18 06:55:46 PM PDT 24
Finished Jul 18 06:56:32 PM PDT 24
Peak memory 275712 kb
Host smart-ed9479ee-1e93-4e44-863b-dc457ab5edd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557078328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2557078328
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.4169545549
Short name T853
Test name
Test status
Simulation time 801026594 ps
CPU time 17.19 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:56:09 PM PDT 24
Peak memory 251012 kb
Host smart-2dacb5c1-244b-466c-9e4a-0b806c94b19f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169545549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.4169545549
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1490079650
Short name T599
Test name
Test status
Simulation time 90892227 ps
CPU time 4.51 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 218224 kb
Host smart-1202bc0e-c372-4410-8161-978914b660e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490079650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1490079650
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3894636800
Short name T385
Test name
Test status
Simulation time 691174275 ps
CPU time 9.86 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:50 PM PDT 24
Peak memory 214888 kb
Host smart-7334e195-027c-4a65-aa5b-2d41185713ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894636800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3894636800
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1497402433
Short name T261
Test name
Test status
Simulation time 1737913697 ps
CPU time 9.64 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:55:59 PM PDT 24
Peak memory 226100 kb
Host smart-41dd80c6-c8de-4225-9314-a299c378f46a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497402433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1497402433
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1003345872
Short name T737
Test name
Test status
Simulation time 2561016609 ps
CPU time 8.64 seconds
Started Jul 18 06:55:44 PM PDT 24
Finished Jul 18 06:55:56 PM PDT 24
Peak memory 218452 kb
Host smart-d62e5a26-3f33-45e2-a07e-07c243a8e247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003345872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
003345872
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3230669965
Short name T362
Test name
Test status
Simulation time 255350311 ps
CPU time 10.48 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:51 PM PDT 24
Peak memory 225412 kb
Host smart-0a90200b-3e8e-456a-ab41-6f59fa7c8669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230669965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3230669965
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3176120332
Short name T713
Test name
Test status
Simulation time 120325676 ps
CPU time 2.36 seconds
Started Jul 18 06:55:33 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 223984 kb
Host smart-14789637-f37b-4583-8751-5ba6c82498ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176120332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3176120332
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1058689867
Short name T792
Test name
Test status
Simulation time 241998112 ps
CPU time 18.44 seconds
Started Jul 18 06:55:35 PM PDT 24
Finished Jul 18 06:55:59 PM PDT 24
Peak memory 245188 kb
Host smart-27315601-530d-4f90-9c5f-ec4ef241920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058689867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1058689867
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.607179207
Short name T210
Test name
Test status
Simulation time 83214582 ps
CPU time 7.36 seconds
Started Jul 18 06:55:34 PM PDT 24
Finished Jul 18 06:55:47 PM PDT 24
Peak memory 251108 kb
Host smart-93b5873c-aad5-4f5c-a92b-29092df3dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607179207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.607179207
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2519732567
Short name T301
Test name
Test status
Simulation time 5816305910 ps
CPU time 59.61 seconds
Started Jul 18 06:55:44 PM PDT 24
Finished Jul 18 06:56:48 PM PDT 24
Peak memory 226232 kb
Host smart-66f725b2-df05-413c-9610-11ddbc645434
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519732567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2519732567
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1095930596
Short name T359
Test name
Test status
Simulation time 53021022 ps
CPU time 0.89 seconds
Started Jul 18 06:55:35 PM PDT 24
Finished Jul 18 06:55:41 PM PDT 24
Peak memory 212996 kb
Host smart-45f28b3f-22ca-4494-8fb0-15e6435ea898
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095930596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1095930596
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2666256166
Short name T757
Test name
Test status
Simulation time 89428818 ps
CPU time 1.24 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:55:54 PM PDT 24
Peak memory 209100 kb
Host smart-ab1074b1-6f66-4a66-9beb-7d2b5655773a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666256166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2666256166
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.4069792282
Short name T378
Test name
Test status
Simulation time 633894195 ps
CPU time 17.99 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:56:10 PM PDT 24
Peak memory 217648 kb
Host smart-3a2e482b-2474-4cc6-9f0f-4e4576a9d9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069792282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.4069792282
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.582518137
Short name T366
Test name
Test status
Simulation time 317165374 ps
CPU time 2.9 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:55:57 PM PDT 24
Peak memory 217252 kb
Host smart-24c7c8f9-bce6-4b8a-84b7-4f364e32dc9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582518137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.582518137
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3495365737
Short name T376
Test name
Test status
Simulation time 4902278316 ps
CPU time 33.77 seconds
Started Jul 18 06:55:46 PM PDT 24
Finished Jul 18 06:56:24 PM PDT 24
Peak memory 218412 kb
Host smart-1ede710d-a9b2-4539-a65d-af1703242568
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495365737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3495365737
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2399518822
Short name T493
Test name
Test status
Simulation time 604398996 ps
CPU time 8.74 seconds
Started Jul 18 06:55:44 PM PDT 24
Finished Jul 18 06:55:57 PM PDT 24
Peak memory 218024 kb
Host smart-a6446371-c4f9-4de5-9990-9e6349a56719
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399518822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
399518822
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1677361785
Short name T772
Test name
Test status
Simulation time 139536997 ps
CPU time 3.29 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:55:55 PM PDT 24
Peak memory 218304 kb
Host smart-3b0ec50b-b651-41e1-9044-d01cdc4f1a63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677361785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1677361785
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1133341211
Short name T544
Test name
Test status
Simulation time 1374046467 ps
CPU time 17.63 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:14 PM PDT 24
Peak memory 217736 kb
Host smart-d2fefe6a-3c9d-42e0-8cef-8621d7a7f1d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133341211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1133341211
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.6510512
Short name T798
Test name
Test status
Simulation time 970604984 ps
CPU time 4.55 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:55:53 PM PDT 24
Peak memory 217756 kb
Host smart-df442cab-7517-4b99-a778-daadc945901b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6510512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.6510512
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3358124331
Short name T252
Test name
Test status
Simulation time 1237730743 ps
CPU time 47.5 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:44 PM PDT 24
Peak memory 267980 kb
Host smart-39a444f1-e56d-4681-89ea-e3bdf8d2b4bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358124331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3358124331
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.4056036249
Short name T675
Test name
Test status
Simulation time 1822332912 ps
CPU time 21.67 seconds
Started Jul 18 06:55:44 PM PDT 24
Finished Jul 18 06:56:09 PM PDT 24
Peak memory 251044 kb
Host smart-b6b8f0ba-bfbf-429e-a06b-531695f411b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056036249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.4056036249
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1821944499
Short name T525
Test name
Test status
Simulation time 319697673 ps
CPU time 2.93 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:55:55 PM PDT 24
Peak memory 222388 kb
Host smart-9c1b2d93-ca9e-4293-9815-d06d8eedf968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821944499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1821944499
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1944109792
Short name T66
Test name
Test status
Simulation time 2075822724 ps
CPU time 10.79 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:08 PM PDT 24
Peak memory 214744 kb
Host smart-c534b767-ea30-4eae-8ae1-51eb5566766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944109792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1944109792
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2080515172
Short name T211
Test name
Test status
Simulation time 2174610747 ps
CPU time 20.27 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:56:09 PM PDT 24
Peak memory 219092 kb
Host smart-35f4dc81-5086-41d6-b961-f4ed1173b10b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080515172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2080515172
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3137962224
Short name T527
Test name
Test status
Simulation time 972602120 ps
CPU time 10.53 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:56:05 PM PDT 24
Peak memory 226096 kb
Host smart-2be2f823-0c21-44bd-920d-699928947ee1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137962224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3137962224
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3391005032
Short name T303
Test name
Test status
Simulation time 1089869531 ps
CPU time 7.64 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:55:57 PM PDT 24
Peak memory 218312 kb
Host smart-ece27647-92cc-4858-9b08-bee78feb55db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391005032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
391005032
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3962413085
Short name T53
Test name
Test status
Simulation time 225327172 ps
CPU time 10.07 seconds
Started Jul 18 06:55:44 PM PDT 24
Finished Jul 18 06:55:57 PM PDT 24
Peak memory 226180 kb
Host smart-03d728fd-a4b7-4fcd-8c8e-76ffcb3d34a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962413085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3962413085
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3227972982
Short name T35
Test name
Test status
Simulation time 147014080 ps
CPU time 2.74 seconds
Started Jul 18 06:55:46 PM PDT 24
Finished Jul 18 06:55:53 PM PDT 24
Peak memory 217796 kb
Host smart-c67cfc27-fe26-469d-86fa-bd70b414bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227972982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3227972982
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1634531912
Short name T331
Test name
Test status
Simulation time 1076655174 ps
CPU time 20.78 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:56:13 PM PDT 24
Peak memory 251108 kb
Host smart-e28a3fed-7ffc-4b24-a94d-45474a36a03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634531912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1634531912
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.346809565
Short name T518
Test name
Test status
Simulation time 81547178 ps
CPU time 8.07 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:56:01 PM PDT 24
Peak memory 251100 kb
Host smart-60c951b5-29f1-4b3a-92d2-eb751910c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346809565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.346809565
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.949338319
Short name T37
Test name
Test status
Simulation time 5882904807 ps
CPU time 40.24 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:56:30 PM PDT 24
Peak memory 251268 kb
Host smart-d7b167c4-47d4-46f6-a03e-1564ba2a2b23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949338319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.949338319
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4165808122
Short name T377
Test name
Test status
Simulation time 34354705 ps
CPU time 0.93 seconds
Started Jul 18 06:55:46 PM PDT 24
Finished Jul 18 06:55:51 PM PDT 24
Peak memory 211952 kb
Host smart-364d619e-f77a-449c-9cca-915f2e20d572
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165808122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.4165808122
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3352595154
Short name T846
Test name
Test status
Simulation time 34544679 ps
CPU time 1.05 seconds
Started Jul 18 06:55:59 PM PDT 24
Finished Jul 18 06:56:09 PM PDT 24
Peak memory 208960 kb
Host smart-c6f5fc62-3c63-4f43-8a4a-3afe676977d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352595154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3352595154
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1424228094
Short name T387
Test name
Test status
Simulation time 48730727 ps
CPU time 0.9 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:55:58 PM PDT 24
Peak memory 208744 kb
Host smart-2a9c481c-2a1c-4e8d-9e5e-81d91dba64ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424228094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1424228094
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1376409691
Short name T361
Test name
Test status
Simulation time 1484108556 ps
CPU time 14.45 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:56:08 PM PDT 24
Peak memory 226172 kb
Host smart-6be1389f-a5f4-455e-921e-8400c22b9255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376409691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1376409691
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.329796053
Short name T650
Test name
Test status
Simulation time 1462712316 ps
CPU time 5.34 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:55:58 PM PDT 24
Peak memory 217328 kb
Host smart-ed00096b-432f-4793-8690-ab622f374d25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329796053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.329796053
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3735201645
Short name T336
Test name
Test status
Simulation time 14746220018 ps
CPU time 49.93 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:46 PM PDT 24
Peak memory 220052 kb
Host smart-2e2531d1-315e-4249-8c44-a90d2317ff68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735201645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3735201645
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2772201290
Short name T203
Test name
Test status
Simulation time 181709906 ps
CPU time 1.85 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:56:03 PM PDT 24
Peak memory 217732 kb
Host smart-9587a710-2f34-4365-bd8c-44a78c0dea46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772201290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
772201290
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3687798610
Short name T669
Test name
Test status
Simulation time 664384611 ps
CPU time 17.04 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:14 PM PDT 24
Peak memory 218384 kb
Host smart-b62e9dcb-e5ab-4e38-9a2c-8557196f67da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687798610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3687798610
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1124081001
Short name T557
Test name
Test status
Simulation time 942775080 ps
CPU time 14.43 seconds
Started Jul 18 06:55:55 PM PDT 24
Finished Jul 18 06:56:17 PM PDT 24
Peak memory 217728 kb
Host smart-455303ac-b932-4125-ba87-09df3e714b78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124081001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1124081001
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2201867820
Short name T533
Test name
Test status
Simulation time 252840520 ps
CPU time 7.75 seconds
Started Jul 18 06:55:51 PM PDT 24
Finished Jul 18 06:56:06 PM PDT 24
Peak memory 217712 kb
Host smart-65c33fa5-d1fb-416a-b600-d7f4b472734d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201867820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2201867820
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.4150230809
Short name T289
Test name
Test status
Simulation time 1212397679 ps
CPU time 51.02 seconds
Started Jul 18 06:55:46 PM PDT 24
Finished Jul 18 06:56:42 PM PDT 24
Peak memory 251076 kb
Host smart-49ae2b41-24db-4883-9da9-1548dca5c534
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150230809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.4150230809
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2560636297
Short name T484
Test name
Test status
Simulation time 2382829956 ps
CPU time 40.46 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:56:35 PM PDT 24
Peak memory 251128 kb
Host smart-36452af4-eac8-4f62-9b67-f25af442ac98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560636297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2560636297
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3075905504
Short name T54
Test name
Test status
Simulation time 201566917 ps
CPU time 2.34 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:55:59 PM PDT 24
Peak memory 222340 kb
Host smart-d43c48cd-5bc7-4435-a216-5d7a31b374f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075905504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3075905504
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.413755355
Short name T341
Test name
Test status
Simulation time 2623725864 ps
CPU time 17.96 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:56:13 PM PDT 24
Peak memory 214880 kb
Host smart-d3174c7a-8e3f-4a5d-aeef-352a288f7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413755355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.413755355
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3512523726
Short name T297
Test name
Test status
Simulation time 417407681 ps
CPU time 12.54 seconds
Started Jul 18 06:55:51 PM PDT 24
Finished Jul 18 06:56:11 PM PDT 24
Peak memory 226172 kb
Host smart-79e0a788-f17f-46db-b250-9dd9a11ec5d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512523726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3512523726
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1793769444
Short name T683
Test name
Test status
Simulation time 1871227935 ps
CPU time 18.5 seconds
Started Jul 18 06:55:54 PM PDT 24
Finished Jul 18 06:56:20 PM PDT 24
Peak memory 226088 kb
Host smart-d927941d-0830-4ce5-93ad-7d966ace1213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793769444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1793769444
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1228446062
Short name T423
Test name
Test status
Simulation time 647551789 ps
CPU time 8.96 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:06 PM PDT 24
Peak memory 226252 kb
Host smart-9401513e-12ca-4f1b-9639-59a21cf82ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228446062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1228446062
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2849975638
Short name T71
Test name
Test status
Simulation time 717087047 ps
CPU time 9.4 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:56:06 PM PDT 24
Peak memory 217812 kb
Host smart-4300e1a0-1fd1-4720-af4f-38b350cd934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849975638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2849975638
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3726789571
Short name T148
Test name
Test status
Simulation time 712435524 ps
CPU time 32.97 seconds
Started Jul 18 06:55:48 PM PDT 24
Finished Jul 18 06:56:28 PM PDT 24
Peak memory 251008 kb
Host smart-9541b0c7-a831-4eb3-9519-cca43f923870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726789571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3726789571
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.360257088
Short name T333
Test name
Test status
Simulation time 322643698 ps
CPU time 2.95 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 06:55:55 PM PDT 24
Peak memory 225624 kb
Host smart-4811dbd0-932d-4b0a-9665-62070f88a9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360257088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.360257088
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1092525445
Short name T39
Test name
Test status
Simulation time 53968461247 ps
CPU time 193.32 seconds
Started Jul 18 06:55:50 PM PDT 24
Finished Jul 18 06:59:10 PM PDT 24
Peak memory 274972 kb
Host smart-d49ce2b9-32b3-4f0e-b715-7b31aa2a58d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092525445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1092525445
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3142065520
Short name T626
Test name
Test status
Simulation time 15284458 ps
CPU time 1.16 seconds
Started Jul 18 06:55:45 PM PDT 24
Finished Jul 18 06:55:51 PM PDT 24
Peak memory 217792 kb
Host smart-39e91c7d-2140-49bb-8d30-ddbd8c67832d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142065520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3142065520
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.4182019183
Short name T401
Test name
Test status
Simulation time 20343409 ps
CPU time 0.95 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:56:02 PM PDT 24
Peak memory 208900 kb
Host smart-d68a95c4-097c-45d3-a3d5-71038d2fb656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182019183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.4182019183
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2795866211
Short name T160
Test name
Test status
Simulation time 20037068 ps
CPU time 0.97 seconds
Started Jul 18 06:55:51 PM PDT 24
Finished Jul 18 06:55:59 PM PDT 24
Peak memory 208916 kb
Host smart-79add954-1f3a-44a5-b259-927073e4eb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795866211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2795866211
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1026347480
Short name T240
Test name
Test status
Simulation time 2579150671 ps
CPU time 15.68 seconds
Started Jul 18 06:55:59 PM PDT 24
Finished Jul 18 06:56:24 PM PDT 24
Peak memory 218372 kb
Host smart-df01c885-5e37-4e2c-8080-955da5a5ddae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026347480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1026347480
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.553389515
Short name T652
Test name
Test status
Simulation time 1509680462 ps
CPU time 7.36 seconds
Started Jul 18 06:55:54 PM PDT 24
Finished Jul 18 06:56:09 PM PDT 24
Peak memory 217320 kb
Host smart-d8df342f-30f6-4c9a-97cd-c0a5e405e48f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553389515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.553389515
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3259577729
Short name T238
Test name
Test status
Simulation time 8650954254 ps
CPU time 60.14 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:57:01 PM PDT 24
Peak memory 218456 kb
Host smart-ac2ae8f3-480d-45d3-a18c-5748375b3a05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259577729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3259577729
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1225083401
Short name T662
Test name
Test status
Simulation time 3945321953 ps
CPU time 25.92 seconds
Started Jul 18 06:55:56 PM PDT 24
Finished Jul 18 06:56:30 PM PDT 24
Peak memory 217904 kb
Host smart-856c5426-f33a-4fbb-ac67-51fcc82180ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225083401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
225083401
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1525679497
Short name T17
Test name
Test status
Simulation time 318056395 ps
CPU time 5.79 seconds
Started Jul 18 06:55:57 PM PDT 24
Finished Jul 18 06:56:11 PM PDT 24
Peak memory 218308 kb
Host smart-bf1d254f-2d2c-4903-a0ce-2d5419679da8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525679497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1525679497
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1777648594
Short name T448
Test name
Test status
Simulation time 3449362702 ps
CPU time 21.34 seconds
Started Jul 18 06:55:54 PM PDT 24
Finished Jul 18 06:56:22 PM PDT 24
Peak memory 217764 kb
Host smart-94e8dc6e-2518-410f-923b-97201c0af489
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777648594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1777648594
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.4078978904
Short name T755
Test name
Test status
Simulation time 109971785 ps
CPU time 3.38 seconds
Started Jul 18 06:55:55 PM PDT 24
Finished Jul 18 06:56:06 PM PDT 24
Peak memory 217716 kb
Host smart-5ed59034-2a8f-400e-b598-4f2916966c5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078978904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
4078978904
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1573464786
Short name T863
Test name
Test status
Simulation time 8555648483 ps
CPU time 44.63 seconds
Started Jul 18 06:55:55 PM PDT 24
Finished Jul 18 06:56:48 PM PDT 24
Peak memory 251112 kb
Host smart-b4da0f9b-5017-4233-bb03-e7cce588c0ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573464786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1573464786
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1707065605
Short name T568
Test name
Test status
Simulation time 1577968196 ps
CPU time 7.74 seconds
Started Jul 18 06:55:57 PM PDT 24
Finished Jul 18 06:56:13 PM PDT 24
Peak memory 223204 kb
Host smart-bee71605-9462-42c2-99b7-4f4025badc85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707065605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1707065605
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3392173996
Short name T466
Test name
Test status
Simulation time 18395208 ps
CPU time 1.57 seconds
Started Jul 18 06:55:57 PM PDT 24
Finished Jul 18 06:56:06 PM PDT 24
Peak memory 218336 kb
Host smart-dd996688-5034-4be1-a0f8-346a2038dd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392173996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3392173996
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3905587113
Short name T279
Test name
Test status
Simulation time 419982133 ps
CPU time 8.28 seconds
Started Jul 18 06:55:51 PM PDT 24
Finished Jul 18 06:56:07 PM PDT 24
Peak memory 214692 kb
Host smart-87feda92-8ee8-4a5d-b74d-3f93103ccd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905587113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3905587113
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.4132198597
Short name T666
Test name
Test status
Simulation time 1791032276 ps
CPU time 17.96 seconds
Started Jul 18 06:55:56 PM PDT 24
Finished Jul 18 06:56:21 PM PDT 24
Peak memory 226176 kb
Host smart-407a93e0-34d4-4ac9-8e0a-f024a7c30a84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132198597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.4132198597
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.4047476350
Short name T280
Test name
Test status
Simulation time 1223432166 ps
CPU time 11.35 seconds
Started Jul 18 06:55:56 PM PDT 24
Finished Jul 18 06:56:15 PM PDT 24
Peak memory 226084 kb
Host smart-6a39f428-107d-408c-8394-a5677492fd94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047476350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.4047476350
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.763715941
Short name T565
Test name
Test status
Simulation time 968727985 ps
CPU time 16.79 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:56:18 PM PDT 24
Peak memory 226056 kb
Host smart-e5df9e17-81e9-4a86-b230-ea3006b04f03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763715941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.763715941
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.147863937
Short name T373
Test name
Test status
Simulation time 1123138672 ps
CPU time 8.86 seconds
Started Jul 18 06:55:56 PM PDT 24
Finished Jul 18 06:56:13 PM PDT 24
Peak memory 226172 kb
Host smart-71172a81-ce54-41a4-8704-9104bc02c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147863937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.147863937
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.178483220
Short name T60
Test name
Test status
Simulation time 447364354 ps
CPU time 6.79 seconds
Started Jul 18 06:55:53 PM PDT 24
Finished Jul 18 06:56:08 PM PDT 24
Peak memory 217796 kb
Host smart-51a7c039-c24c-4133-be40-867ada5585d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178483220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.178483220
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.4103494702
Short name T623
Test name
Test status
Simulation time 302350932 ps
CPU time 27.47 seconds
Started Jul 18 06:55:59 PM PDT 24
Finished Jul 18 06:56:35 PM PDT 24
Peak memory 251056 kb
Host smart-625aa4c4-675b-4a89-9fde-e480f935a49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103494702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4103494702
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1774024754
Short name T780
Test name
Test status
Simulation time 224610269 ps
CPU time 6.26 seconds
Started Jul 18 06:55:59 PM PDT 24
Finished Jul 18 06:56:14 PM PDT 24
Peak memory 247252 kb
Host smart-ea4dd24f-8349-4fc9-9255-bd604e35875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774024754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1774024754
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3782384025
Short name T696
Test name
Test status
Simulation time 54978294971 ps
CPU time 276.51 seconds
Started Jul 18 06:55:47 PM PDT 24
Finished Jul 18 07:00:30 PM PDT 24
Peak memory 278484 kb
Host smart-56ae4e23-36a9-42d2-8d19-f0d310bd84c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782384025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3782384025
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.691606379
Short name T813
Test name
Test status
Simulation time 28000281 ps
CPU time 0.95 seconds
Started Jul 18 06:55:59 PM PDT 24
Finished Jul 18 06:56:09 PM PDT 24
Peak memory 211904 kb
Host smart-d202353f-7011-45e3-9e05-709e811b2a7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691606379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.691606379
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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