Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100620010

1

T1

18515

T2

39431

T3

31805

auto[1]

1368150

1

T2

297

T3

1188

T16

1980

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100623604

1

T1

18515

T2

39134

T3

31112

auto[1]

1364556

1

T2

594

T3

1881

T16

1980

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6966275	1			T1	111		T2	8226		T3	6603
auto[IdleSt]	20313818	1			T1	18404		T2	7923		T3	5417
auto[ClkMuxSt]	34317	1			T2	92		T3	51		T4	59
auto[CntIncrSt]	34038	1			T2	92		T3	51		T4	59
auto[CntProgSt]	1617742	1			T2	918		T3	1417		T4	2396
auto[TransCheckSt]	26577	1			T2	69		T3	37		T4	59
auto[TokenHashSt]	43724953	1			T2	5795		T3	2630		T4	729
auto[FlashRmaSt]	33217	1			T2	49		T3	118		T4	44
auto[TokenCheck0St]	11949	1			T2	18		T3	30		T4	26
auto[TokenCheck1St]	9018	1			T2	6		T3	26		T4	13
auto[TransProgSt]	476042	1			T2	80		T3	1108		T14	18
auto[PostTransSt]	11795939	1			T2	15286		T3	8109		T4	9103
auto[ScrapSt]	350465	1			T20	6		T10	1165		T15	1131
auto[EscalateSt]	6318690	1			T2	1174		T3	4264		T16	5055
auto[InvalidSt]	10273210	1			T3	3132		T16	1258		T10	40024

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1910	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10273210	1			T3	3132		T16	1258		T10	40024
EscalateSt	6318690	1			T2	1174		T3	4264		T16	5055
ScrapSt	350465	1			T20	6		T10	1165		T15	1131
PostTransSt	11795939	1			T2	15286		T3	8109		T4	9103
TransProgSt	476042	1			T2	80		T3	1108		T14	18
TokenCheck1St	9018	1			T2	6		T3	26		T4	13
TokenCheck0St	11949	1			T2	18		T3	30		T4	26
FlashRmaSt	33217	1			T2	49		T3	118		T4	44
TokenHashSt	43724953	1			T2	5795		T3	2630		T4	729
TransCheckSt	26577	1			T2	69		T3	37		T4	59
CntProgSt	1617742	1			T2	918		T3	1417		T4	2396
CntIncrSt	34038	1			T2	92		T3	51		T4	59
ClkMuxSt	34317	1			T2	92		T3	51		T4	59
IdleSt	20313818	1			T1	18404		T2	7923		T3	5417
ResetSt	6966275	1			T1	111		T2	8226		T3	6603
arcs[ResetSt=>IdleSt]	51880	1			T1	1		T2	93		T3	69
arcs[IdleSt=>ScrapSt]	288	1			T20	2		T10	2		T15	7
arcs[IdleSt=>ClkMuxSt]	34117	1			T2	92		T3	51		T4	59
arcs[ClkMuxSt=>CntIncrSt]	34038	1			T2	92		T3	51		T4	59
arcs[CntIncrSt=>PostTransSt]	1771	1			T2	14		T9	11		T10	16
arcs[CntIncrSt=>CntProgSt]	32195	1			T2	78		T3	51		T4	59
arcs[CntProgSt=>PostTransSt]	4600	1			T2	9		T3	14		T16	24
arcs[CntProgSt=>TransCheckSt]	26577	1			T2	69		T3	37		T4	59
arcs[TransCheckSt=>PostTransSt]	3636	1			T2	8		T4	26		T12	51
arcs[TransCheckSt=>TokenHashSt]	22802	1			T2	61		T3	37		T4	33
arcs[TokenHashSt=>PostTransSt]	10026	1			T2	43		T3	7		T4	7
arcs[TokenHashSt=>FlashRmaSt]	12034	1			T2	18		T3	30		T4	26
arcs[FlashRmaSt=>TokenCheck0St]	11949	1			T2	18		T3	30		T4	26
arcs[TokenCheck0St=>PostTransSt]	2902	1			T2	12		T3	4		T4	13
arcs[TokenCheck0St=>TokenCheck1St]	9018	1			T2	6		T3	26		T4	13
arcs[TokenCheck1St=>PostTransSt]	581	1			T2	1		T4	13		T12	8
arcs[TransProgSt=>PostTransSt]	7604	1			T2	5		T3	26		T14	9
arcs[IdleSt=>EscalateSt]	215	1			T19	11		T40	14		T41	4
arcs[ClkMuxSt=>EscalateSt]	79	1			T20	4		T19	1		T40	1
arcs[CntIncrSt=>EscalateSt]	72	1			T20	1		T40	2		T41	1
arcs[CntProgSt=>EscalateSt]	1018	1			T20	33		T19	9		T40	35
arcs[TransCheckSt=>EscalateSt]	139	1			T20	1		T19	8		T41	9
arcs[TokenHashSt=>EscalateSt]	742	1			T20	7		T19	27		T40	12
arcs[FlashRmaSt=>EscalateSt]	85	1			T19	1		T40	3		T42	2
arcs[TokenCheck0St=>EscalateSt]	29	1			T20	2		T19	1		T41	1
arcs[TokenCheck1St=>EscalateSt]	147	1			T20	3		T19	2		T40	4
arcs[TransProgSt=>EscalateSt]	686	1			T20	20		T19	8		T40	14
arcs[PostTransSt=>EscalateSt]	4888	1			T2	9		T3	14		T16	24
arcs[InvalidSt=>EscalateSt]	13388	1			T3	17		T16	16		T10	66

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6966084	1			T1	111		T2	8226		T3	6603
auto[0]	auto[IdleSt]	20313688	1			T1	18404		T2	7923		T3	5417
auto[0]	auto[ClkMuxSt]	34262	1			T2	92		T3	51		T4	59
auto[0]	auto[CntIncrSt]	33983	1			T2	92		T3	51		T4	59
auto[0]	auto[CntProgSt]	1617074	1			T2	918		T3	1417		T4	2396
auto[0]	auto[TransCheckSt]	26475	1			T2	69		T3	37		T4	59
auto[0]	auto[TokenHashSt]	43724460	1			T2	5795		T3	2630		T4	729
auto[0]	auto[FlashRmaSt]	33158	1			T2	49		T3	118		T4	44
auto[0]	auto[TokenCheck0St]	11926	1			T2	18		T3	30		T4	26
auto[0]	auto[TokenCheck1St]	8923	1			T2	6		T3	26		T4	13
auto[0]	auto[TransProgSt]	475599	1			T2	80		T3	1108		T14	18
auto[0]	auto[PostTransSt]	11793421	1			T2	15283		T3	8103		T4	9103
auto[0]	auto[ScrapSt]	350422	1			T20	4		T10	1165		T15	1131
auto[0]	auto[EscalateSt]	4962103	1			T2	880		T3	3088		T16	3095
auto[0]	auto[InvalidSt]	10266522	1			T3	3126		T16	1249		T10	39997
auto[1]	auto[ResetSt]	191	1			T20	4		T19	6		T40	7
auto[1]	auto[IdleSt]	130	1			T19	7		T40	8		T41	2
auto[1]	auto[ClkMuxSt]	55	1			T20	3		T19	1		T41	1
auto[1]	auto[CntIncrSt]	55	1			T20	1		T40	2		T91	1
auto[1]	auto[CntProgSt]	668	1			T20	24		T19	8		T40	17
auto[1]	auto[TransCheckSt]	102	1			T20	1		T19	6		T41	6
auto[1]	auto[TokenHashSt]	493	1			T20	5		T19	21		T40	7
auto[1]	auto[FlashRmaSt]	59	1			T19	1		T40	3		T42	1
auto[1]	auto[TokenCheck0St]	23	1			T20	2		T19	1		T41	1
auto[1]	auto[TokenCheck1St]	95	1			T20	2		T19	2		T40	4
auto[1]	auto[TransProgSt]	443	1			T20	12		T19	5		T40	11
auto[1]	auto[PostTransSt]	2518	1			T2	3		T3	6		T16	11
auto[1]	auto[ScrapSt]	43	1			T20	2		T19	1		T40	1
auto[1]	auto[EscalateSt]	1356587	1			T2	294		T3	1176		T16	1960
auto[1]	auto[InvalidSt]	6688	1			T3	6		T16	9		T10	27

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6966094	1			T1	111		T2	8226		T3	6603
auto[0]	auto[IdleSt]	20313674	1			T1	18404		T2	7923		T3	5417
auto[0]	auto[ClkMuxSt]	34266	1			T2	92		T3	51		T4	59
auto[0]	auto[CntIncrSt]	33988	1			T2	92		T3	51		T4	59
auto[0]	auto[CntProgSt]	1617051	1			T2	918		T3	1417		T4	2396
auto[0]	auto[TransCheckSt]	26490	1			T2	69		T3	37		T4	59
auto[0]	auto[TokenHashSt]	43724469	1			T2	5795		T3	2630		T4	729
auto[0]	auto[FlashRmaSt]	33158	1			T2	49		T3	118		T4	44
auto[0]	auto[TokenCheck0St]	11928	1			T2	18		T3	30		T4	26
auto[0]	auto[TokenCheck1St]	8924	1			T2	6		T3	26		T4	13
auto[0]	auto[TransProgSt]	475577	1			T2	80		T3	1108		T14	18
auto[0]	auto[PostTransSt]	11793484	1			T2	15280		T3	8101		T4	9103
auto[0]	auto[ScrapSt]	350421	1			T20	5		T10	1165		T15	1131
auto[0]	auto[EscalateSt]	4965660	1			T2	586		T3	2402		T16	3095
auto[0]	auto[InvalidSt]	10266510	1			T3	3121		T16	1251		T10	39985
auto[1]	auto[ResetSt]	181	1			T20	2		T19	4		T40	3
auto[1]	auto[IdleSt]	144	1			T19	9		T40	9		T41	2
auto[1]	auto[ClkMuxSt]	51	1			T20	3		T19	1		T40	1
auto[1]	auto[CntIncrSt]	50	1			T40	1		T41	1		T42	1
auto[1]	auto[CntProgSt]	691	1			T20	23		T19	4		T40	27
auto[1]	auto[TransCheckSt]	87	1			T19	4		T41	7		T196	2
auto[1]	auto[TokenHashSt]	484	1			T20	6		T19	18		T40	9
auto[1]	auto[FlashRmaSt]	59	1			T19	1		T40	2		T42	1
auto[1]	auto[TokenCheck0St]	21	1			T20	1		T19	1		T41	1
auto[1]	auto[TokenCheck1St]	94	1			T20	1		T19	2		T40	2
auto[1]	auto[TransProgSt]	465	1			T20	16		T19	4		T40	7
auto[1]	auto[PostTransSt]	2455	1			T2	6		T3	8		T16	13
auto[1]	auto[ScrapSt]	44	1			T20	1		T19	3		T42	1
auto[1]	auto[EscalateSt]	1353030	1			T2	588		T3	1862		T16	1960
auto[1]	auto[InvalidSt]	6700	1			T3	11		T16	7		T10	39