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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.79 97.92 95.47 93.40 97.62 98.52 98.51 96.11


Total test records in report: 990
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T814 /workspace/coverage/default/6.lc_ctrl_state_post_trans.629251280 Jul 19 05:43:14 PM PDT 24 Jul 19 05:43:24 PM PDT 24 77654967 ps
T815 /workspace/coverage/default/38.lc_ctrl_alert_test.4041262420 Jul 19 05:45:26 PM PDT 24 Jul 19 05:45:30 PM PDT 24 54686887 ps
T816 /workspace/coverage/default/23.lc_ctrl_errors.2517416687 Jul 19 05:44:39 PM PDT 24 Jul 19 05:44:49 PM PDT 24 194633741 ps
T817 /workspace/coverage/default/13.lc_ctrl_smoke.381459879 Jul 19 05:43:53 PM PDT 24 Jul 19 05:43:59 PM PDT 24 57748920 ps
T818 /workspace/coverage/default/32.lc_ctrl_state_post_trans.1743970104 Jul 19 05:45:11 PM PDT 24 Jul 19 05:45:18 PM PDT 24 49130811 ps
T819 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.444514465 Jul 19 05:45:01 PM PDT 24 Jul 19 05:45:11 PM PDT 24 1115367971 ps
T820 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3274026950 Jul 19 05:44:41 PM PDT 24 Jul 19 05:44:44 PM PDT 24 13237488 ps
T821 /workspace/coverage/default/24.lc_ctrl_errors.3218957269 Jul 19 05:44:37 PM PDT 24 Jul 19 05:44:47 PM PDT 24 538238154 ps
T822 /workspace/coverage/default/12.lc_ctrl_state_post_trans.3620866833 Jul 19 05:43:43 PM PDT 24 Jul 19 05:43:53 PM PDT 24 187726612 ps
T823 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1652767100 Jul 19 05:44:58 PM PDT 24 Jul 19 05:45:09 PM PDT 24 814020484 ps
T824 /workspace/coverage/default/0.lc_ctrl_prog_failure.1004373231 Jul 19 05:42:42 PM PDT 24 Jul 19 05:42:48 PM PDT 24 450501864 ps
T825 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1768083706 Jul 19 05:45:44 PM PDT 24 Jul 19 05:45:57 PM PDT 24 459704486 ps
T826 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.4262890810 Jul 19 05:44:04 PM PDT 24 Jul 19 05:44:11 PM PDT 24 406797533 ps
T827 /workspace/coverage/default/4.lc_ctrl_jtag_priority.3201130096 Jul 19 05:43:06 PM PDT 24 Jul 19 05:43:11 PM PDT 24 2828975199 ps
T828 /workspace/coverage/default/1.lc_ctrl_alert_test.1808882407 Jul 19 05:42:49 PM PDT 24 Jul 19 05:42:51 PM PDT 24 13918026 ps
T829 /workspace/coverage/default/11.lc_ctrl_alert_test.829606986 Jul 19 05:43:44 PM PDT 24 Jul 19 05:43:48 PM PDT 24 92965944 ps
T830 /workspace/coverage/default/15.lc_ctrl_jtag_access.311640154 Jul 19 05:44:06 PM PDT 24 Jul 19 05:44:13 PM PDT 24 425518759 ps
T831 /workspace/coverage/default/45.lc_ctrl_state_failure.96412660 Jul 19 05:45:55 PM PDT 24 Jul 19 05:46:20 PM PDT 24 165643283 ps
T832 /workspace/coverage/default/30.lc_ctrl_alert_test.2234220601 Jul 19 05:45:04 PM PDT 24 Jul 19 05:45:06 PM PDT 24 41773739 ps
T833 /workspace/coverage/default/18.lc_ctrl_jtag_errors.2584200045 Jul 19 05:44:23 PM PDT 24 Jul 19 05:44:51 PM PDT 24 1718540853 ps
T834 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3357348923 Jul 19 05:45:51 PM PDT 24 Jul 19 05:46:01 PM PDT 24 474608044 ps
T60 /workspace/coverage/default/9.lc_ctrl_stress_all.3549671566 Jul 19 05:43:37 PM PDT 24 Jul 19 05:44:34 PM PDT 24 1413907998 ps
T193 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3984500377 Jul 19 05:43:19 PM PDT 24 Jul 19 05:43:21 PM PDT 24 10369769 ps
T835 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1965024959 Jul 19 05:43:49 PM PDT 24 Jul 19 05:43:56 PM PDT 24 659294897 ps
T836 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2868233894 Jul 19 05:45:31 PM PDT 24 Jul 19 05:45:32 PM PDT 24 11659352 ps
T837 /workspace/coverage/default/36.lc_ctrl_security_escalation.1406116576 Jul 19 05:45:23 PM PDT 24 Jul 19 05:45:34 PM PDT 24 208874875 ps
T838 /workspace/coverage/default/7.lc_ctrl_jtag_errors.4032112680 Jul 19 05:43:22 PM PDT 24 Jul 19 05:44:11 PM PDT 24 3355960967 ps
T839 /workspace/coverage/default/22.lc_ctrl_state_failure.3122973221 Jul 19 05:44:37 PM PDT 24 Jul 19 05:45:02 PM PDT 24 240375272 ps
T840 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1210314600 Jul 19 05:45:45 PM PDT 24 Jul 19 05:45:48 PM PDT 24 11768184 ps
T841 /workspace/coverage/default/3.lc_ctrl_stress_all.768223620 Jul 19 05:43:04 PM PDT 24 Jul 19 05:45:09 PM PDT 24 2678335381 ps
T842 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2904428437 Jul 19 05:43:53 PM PDT 24 Jul 19 05:44:06 PM PDT 24 263852211 ps
T843 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.583762992 Jul 19 05:43:45 PM PDT 24 Jul 19 05:43:55 PM PDT 24 463655719 ps
T844 /workspace/coverage/default/22.lc_ctrl_smoke.382582073 Jul 19 05:44:39 PM PDT 24 Jul 19 05:44:44 PM PDT 24 50726145 ps
T845 /workspace/coverage/default/45.lc_ctrl_errors.608785908 Jul 19 05:45:53 PM PDT 24 Jul 19 05:46:09 PM PDT 24 1234250813 ps
T846 /workspace/coverage/default/9.lc_ctrl_jtag_access.2328700987 Jul 19 05:43:38 PM PDT 24 Jul 19 05:43:46 PM PDT 24 601595768 ps
T847 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.904117020 Jul 19 05:43:04 PM PDT 24 Jul 19 05:43:13 PM PDT 24 924468020 ps
T848 /workspace/coverage/default/1.lc_ctrl_prog_failure.576701478 Jul 19 05:42:41 PM PDT 24 Jul 19 05:42:45 PM PDT 24 95329204 ps
T849 /workspace/coverage/default/38.lc_ctrl_errors.2821980281 Jul 19 05:45:25 PM PDT 24 Jul 19 05:45:55 PM PDT 24 994598379 ps
T850 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1196855908 Jul 19 05:43:49 PM PDT 24 Jul 19 05:44:01 PM PDT 24 2384268391 ps
T851 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2029248672 Jul 19 05:44:55 PM PDT 24 Jul 19 05:45:08 PM PDT 24 319309665 ps
T852 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3618365683 Jul 19 05:44:23 PM PDT 24 Jul 19 05:45:16 PM PDT 24 5234829908 ps
T853 /workspace/coverage/default/31.lc_ctrl_security_escalation.943479877 Jul 19 05:45:02 PM PDT 24 Jul 19 05:45:14 PM PDT 24 984593074 ps
T854 /workspace/coverage/default/7.lc_ctrl_stress_all.3050619039 Jul 19 05:43:27 PM PDT 24 Jul 19 05:48:01 PM PDT 24 15687571255 ps
T855 /workspace/coverage/default/1.lc_ctrl_state_failure.3531535587 Jul 19 05:42:42 PM PDT 24 Jul 19 05:43:11 PM PDT 24 207244756 ps
T856 /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.661096792 Jul 19 05:45:27 PM PDT 24 Jul 19 05:48:56 PM PDT 24 9805501604 ps
T857 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2409624359 Jul 19 05:43:26 PM PDT 24 Jul 19 05:43:36 PM PDT 24 1339946183 ps
T858 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1046481437 Jul 19 05:42:49 PM PDT 24 Jul 19 05:43:03 PM PDT 24 382881624 ps
T859 /workspace/coverage/default/24.lc_ctrl_state_failure.622297982 Jul 19 05:44:38 PM PDT 24 Jul 19 05:45:09 PM PDT 24 1831599323 ps
T860 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3387639498 Jul 19 05:43:36 PM PDT 24 Jul 19 05:44:07 PM PDT 24 771233115 ps
T861 /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3097029242 Jul 19 05:44:32 PM PDT 24 Jul 19 05:44:33 PM PDT 24 20230625 ps
T862 /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.484210513 Jul 19 05:42:40 PM PDT 24 Jul 19 05:52:33 PM PDT 24 83189006953 ps
T863 /workspace/coverage/default/29.lc_ctrl_alert_test.2942199968 Jul 19 05:44:55 PM PDT 24 Jul 19 05:44:57 PM PDT 24 20081730 ps
T864 /workspace/coverage/default/43.lc_ctrl_prog_failure.3867581758 Jul 19 05:45:42 PM PDT 24 Jul 19 05:45:47 PM PDT 24 120210591 ps
T865 /workspace/coverage/default/26.lc_ctrl_prog_failure.3551556454 Jul 19 05:44:56 PM PDT 24 Jul 19 05:45:00 PM PDT 24 38041866 ps
T140 /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3859643301 Jul 19 05:45:42 PM PDT 24 Jul 19 06:16:39 PM PDT 24 208939945435 ps
T94 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2391448481 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:19 PM PDT 24 26003457 ps
T112 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4005450091 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:07 PM PDT 24 420037303 ps
T104 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.478769804 Jul 19 04:47:15 PM PDT 24 Jul 19 04:47:31 PM PDT 24 27571712 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2327915063 Jul 19 04:46:59 PM PDT 24 Jul 19 04:47:11 PM PDT 24 129404683 ps
T105 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1816248432 Jul 19 04:46:39 PM PDT 24 Jul 19 04:46:56 PM PDT 24 1612949068 ps
T106 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.654943934 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:03 PM PDT 24 16816507 ps
T98 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.39537440 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:17 PM PDT 24 63475111 ps
T182 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3573838117 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:18 PM PDT 24 127815924 ps
T126 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4058067203 Jul 19 04:46:48 PM PDT 24 Jul 19 04:46:58 PM PDT 24 178450672 ps
T130 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4028650694 Jul 19 04:46:43 PM PDT 24 Jul 19 04:46:51 PM PDT 24 210266736 ps
T95 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2455589405 Jul 19 04:47:12 PM PDT 24 Jul 19 04:47:27 PM PDT 24 39533865 ps
T96 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3820582456 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:17 PM PDT 24 324509522 ps
T100 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4245616261 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:18 PM PDT 24 1317456237 ps
T183 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1139379476 Jul 19 04:47:13 PM PDT 24 Jul 19 04:47:30 PM PDT 24 110174554 ps
T866 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2721091444 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:56 PM PDT 24 78985172 ps
T171 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3415555185 Jul 19 04:46:48 PM PDT 24 Jul 19 04:46:56 PM PDT 24 42538137 ps
T155 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1037581950 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:17 PM PDT 24 31275257 ps
T129 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3436016052 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:06 PM PDT 24 162502102 ps
T128 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1365006964 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:24 PM PDT 24 765696815 ps
T867 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3352021462 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:04 PM PDT 24 307584860 ps
T868 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3010820792 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:16 PM PDT 24 47330669 ps
T99 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1638419209 Jul 19 04:47:06 PM PDT 24 Jul 19 04:47:21 PM PDT 24 99522545 ps
T168 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.703047941 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:20 PM PDT 24 30665830 ps
T101 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1282123547 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:21 PM PDT 24 76688503 ps
T102 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1651872427 Jul 19 04:47:15 PM PDT 24 Jul 19 04:47:34 PM PDT 24 411287679 ps
T869 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4259730302 Jul 19 04:47:07 PM PDT 24 Jul 19 04:47:21 PM PDT 24 55053070 ps
T870 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1389613173 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:57 PM PDT 24 164115865 ps
T871 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1761177274 Jul 19 04:46:42 PM PDT 24 Jul 19 04:46:59 PM PDT 24 970282592 ps
T872 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.701692495 Jul 19 04:47:06 PM PDT 24 Jul 19 04:47:20 PM PDT 24 14905453 ps
T116 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1059484309 Jul 19 04:47:11 PM PDT 24 Jul 19 04:47:25 PM PDT 24 47692106 ps
T873 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1755878232 Jul 19 04:47:04 PM PDT 24 Jul 19 04:47:17 PM PDT 24 15021981 ps
T141 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.361507647 Jul 19 04:47:09 PM PDT 24 Jul 19 04:47:22 PM PDT 24 19954706 ps
T103 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2657376118 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:18 PM PDT 24 1107694722 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.262795297 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:55 PM PDT 24 90406819 ps
T142 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.861551515 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:16 PM PDT 24 92280909 ps
T184 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3057821933 Jul 19 04:47:07 PM PDT 24 Jul 19 04:47:20 PM PDT 24 38960968 ps
T185 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2991178381 Jul 19 04:46:48 PM PDT 24 Jul 19 04:46:57 PM PDT 24 50376165 ps
T875 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3543361002 Jul 19 04:46:57 PM PDT 24 Jul 19 04:47:26 PM PDT 24 689940567 ps
T107 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1642189255 Jul 19 04:46:57 PM PDT 24 Jul 19 04:47:08 PM PDT 24 24409377 ps
T119 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2366975383 Jul 19 04:47:07 PM PDT 24 Jul 19 04:47:22 PM PDT 24 114505016 ps
T876 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.107746989 Jul 19 04:46:58 PM PDT 24 Jul 19 04:47:09 PM PDT 24 189364871 ps
T186 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2157066161 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:14 PM PDT 24 26444995 ps
T187 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3230220524 Jul 19 04:46:39 PM PDT 24 Jul 19 04:46:47 PM PDT 24 39428176 ps
T877 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3729704385 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:07 PM PDT 24 551774441 ps
T878 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2792368016 Jul 19 04:47:10 PM PDT 24 Jul 19 04:47:24 PM PDT 24 77613896 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1972992025 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:08 PM PDT 24 74110607 ps
T880 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4018948649 Jul 19 04:47:08 PM PDT 24 Jul 19 04:47:22 PM PDT 24 41263350 ps
T881 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.888530106 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:03 PM PDT 24 33651977 ps
T882 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4183229004 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:19 PM PDT 24 61249202 ps
T883 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3859258980 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:14 PM PDT 24 17381127697 ps
T188 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2696095371 Jul 19 04:46:57 PM PDT 24 Jul 19 04:47:08 PM PDT 24 67795751 ps
T189 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2270953804 Jul 19 04:47:04 PM PDT 24 Jul 19 04:47:19 PM PDT 24 69525416 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.407756128 Jul 19 04:46:52 PM PDT 24 Jul 19 04:47:01 PM PDT 24 354533137 ps
T885 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3766715474 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:03 PM PDT 24 43475199 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.286626204 Jul 19 04:46:48 PM PDT 24 Jul 19 04:46:57 PM PDT 24 37991277 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.278734852 Jul 19 04:46:42 PM PDT 24 Jul 19 04:46:51 PM PDT 24 212376662 ps
T888 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3494834615 Jul 19 04:46:46 PM PDT 24 Jul 19 04:47:12 PM PDT 24 1656838969 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3213041785 Jul 19 04:46:45 PM PDT 24 Jul 19 04:46:53 PM PDT 24 38948880 ps
T890 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2174874026 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:18 PM PDT 24 12976044 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.272478324 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:20 PM PDT 24 417700578 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3910797608 Jul 19 04:46:45 PM PDT 24 Jul 19 04:46:55 PM PDT 24 907825961 ps
T893 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4000243295 Jul 19 04:46:57 PM PDT 24 Jul 19 04:47:08 PM PDT 24 598833185 ps
T108 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3165937897 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:22 PM PDT 24 168302096 ps
T109 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2108532464 Jul 19 04:46:48 PM PDT 24 Jul 19 04:46:57 PM PDT 24 168710062 ps
T114 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.162589598 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:15 PM PDT 24 195628362 ps
T894 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3034837120 Jul 19 04:47:07 PM PDT 24 Jul 19 04:47:21 PM PDT 24 24083302 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2889529892 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:06 PM PDT 24 105328054 ps
T896 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2819808123 Jul 19 04:46:57 PM PDT 24 Jul 19 04:47:08 PM PDT 24 131961417 ps
T172 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1745085964 Jul 19 04:46:41 PM PDT 24 Jul 19 04:46:49 PM PDT 24 42121729 ps
T897 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2999917174 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:03 PM PDT 24 27668385 ps
T110 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1947479808 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:04 PM PDT 24 142928117 ps
T898 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2280076203 Jul 19 04:47:13 PM PDT 24 Jul 19 04:47:31 PM PDT 24 138240774 ps
T195 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.223143208 Jul 19 04:47:13 PM PDT 24 Jul 19 04:47:30 PM PDT 24 279852230 ps
T899 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.793207338 Jul 19 04:47:09 PM PDT 24 Jul 19 04:47:23 PM PDT 24 121570191 ps
T900 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1463052468 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:15 PM PDT 24 91510908 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1576155421 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:05 PM PDT 24 103681509 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.448172459 Jul 19 04:46:37 PM PDT 24 Jul 19 04:46:47 PM PDT 24 59980184 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3853477743 Jul 19 04:47:01 PM PDT 24 Jul 19 04:47:14 PM PDT 24 36225501 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1805935106 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:18 PM PDT 24 1026630215 ps
T904 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2992316513 Jul 19 04:46:49 PM PDT 24 Jul 19 04:46:58 PM PDT 24 553247786 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3828379312 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:03 PM PDT 24 15837612 ps
T906 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.679661723 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:20 PM PDT 24 57292486 ps
T173 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.867401258 Jul 19 04:47:13 PM PDT 24 Jul 19 04:47:29 PM PDT 24 56242153 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1889109641 Jul 19 04:46:46 PM PDT 24 Jul 19 04:46:54 PM PDT 24 239087579 ps
T120 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1316401413 Jul 19 04:47:04 PM PDT 24 Jul 19 04:47:20 PM PDT 24 147241079 ps
T908 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.634789543 Jul 19 04:47:06 PM PDT 24 Jul 19 04:48:15 PM PDT 24 40747395418 ps
T909 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.147824281 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:20 PM PDT 24 387652484 ps
T910 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2312733425 Jul 19 04:46:52 PM PDT 24 Jul 19 04:47:01 PM PDT 24 38821861 ps
T911 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.287865860 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:05 PM PDT 24 463499542 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2569233284 Jul 19 04:46:42 PM PDT 24 Jul 19 04:46:52 PM PDT 24 83091484 ps
T913 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4106914507 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:09 PM PDT 24 1378422185 ps
T914 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1327996500 Jul 19 04:47:11 PM PDT 24 Jul 19 04:47:25 PM PDT 24 329190821 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3590896221 Jul 19 04:46:52 PM PDT 24 Jul 19 04:47:17 PM PDT 24 12072380206 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.107887393 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:55 PM PDT 24 146238502 ps
T917 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.953303661 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:22 PM PDT 24 921425932 ps
T918 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2989775045 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:04 PM PDT 24 29043151 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1035892625 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:45 PM PDT 24 5086696849 ps
T174 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1236682528 Jul 19 04:47:13 PM PDT 24 Jul 19 04:47:29 PM PDT 24 12272372 ps
T175 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2204774306 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:03 PM PDT 24 17280059 ps
T920 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1313275426 Jul 19 04:46:58 PM PDT 24 Jul 19 04:47:13 PM PDT 24 566753105 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2309383131 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:10 PM PDT 24 123384641 ps
T922 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3500397394 Jul 19 04:46:57 PM PDT 24 Jul 19 04:47:09 PM PDT 24 793563438 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3864261070 Jul 19 04:46:41 PM PDT 24 Jul 19 04:46:51 PM PDT 24 74574903 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1126945301 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:07 PM PDT 24 27908379 ps
T925 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.656667733 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:03 PM PDT 24 189209874 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.398230363 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:05 PM PDT 24 317255922 ps
T927 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3278328002 Jul 19 04:46:46 PM PDT 24 Jul 19 04:46:54 PM PDT 24 64065220 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.908379782 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:55 PM PDT 24 16677227 ps
T929 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.492713787 Jul 19 04:47:09 PM PDT 24 Jul 19 04:47:23 PM PDT 24 62693095 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.161966769 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:07 PM PDT 24 158831837 ps
T931 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3192947615 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:15 PM PDT 24 316984748 ps
T932 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.787269803 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:16 PM PDT 24 75751341 ps
T933 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3015652135 Jul 19 04:47:12 PM PDT 24 Jul 19 04:47:28 PM PDT 24 89111725 ps
T934 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1159101519 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:11 PM PDT 24 1057257546 ps
T935 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.901399609 Jul 19 04:46:45 PM PDT 24 Jul 19 04:46:52 PM PDT 24 28057682 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4132099660 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:07 PM PDT 24 2166505343 ps
T937 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3621565928 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:19 PM PDT 24 23163670 ps
T938 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.43801708 Jul 19 04:46:45 PM PDT 24 Jul 19 04:47:03 PM PDT 24 1796962016 ps
T176 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.151486323 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:55 PM PDT 24 19079030 ps
T177 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3858724455 Jul 19 04:46:49 PM PDT 24 Jul 19 04:46:58 PM PDT 24 18187772 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.910130817 Jul 19 04:46:48 PM PDT 24 Jul 19 04:47:01 PM PDT 24 1609460688 ps
T122 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2968581343 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:57 PM PDT 24 119227058 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.900669537 Jul 19 04:46:46 PM PDT 24 Jul 19 04:46:55 PM PDT 24 49532976 ps
T941 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2950958796 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:15 PM PDT 24 51974413 ps
T942 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1088939958 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:07 PM PDT 24 1148457893 ps
T943 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3719846278 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:56 PM PDT 24 48408738 ps
T944 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2395509204 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:14 PM PDT 24 189281222 ps
T945 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2608415582 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:20 PM PDT 24 447842528 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1899558871 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:06 PM PDT 24 29831595 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1395695307 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:17 PM PDT 24 47855957 ps
T948 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1689580575 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:04 PM PDT 24 95478459 ps
T949 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1985917895 Jul 19 04:46:46 PM PDT 24 Jul 19 04:46:53 PM PDT 24 459510730 ps
T950 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1244426017 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:55 PM PDT 24 929903615 ps
T951 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3026848920 Jul 19 04:47:11 PM PDT 24 Jul 19 04:47:25 PM PDT 24 26079400 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4078819171 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:05 PM PDT 24 51232000 ps
T953 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2992044415 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:06 PM PDT 24 22341654 ps
T178 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3323763511 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:03 PM PDT 24 17931800 ps
T954 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3288438898 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:16 PM PDT 24 57551917 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.480007794 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:54 PM PDT 24 37144782 ps
T956 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1082067587 Jul 19 04:47:16 PM PDT 24 Jul 19 04:47:32 PM PDT 24 148519513 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.683720054 Jul 19 04:47:10 PM PDT 24 Jul 19 04:47:24 PM PDT 24 175311701 ps
T958 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.643831027 Jul 19 04:47:12 PM PDT 24 Jul 19 04:47:27 PM PDT 24 17973281 ps
T117 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.931007250 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:22 PM PDT 24 389445273 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2378232412 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:07 PM PDT 24 437998677 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1122137879 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:15 PM PDT 24 160771127 ps
T961 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4060292136 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:20 PM PDT 24 56186544 ps
T962 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1240193663 Jul 19 04:46:49 PM PDT 24 Jul 19 04:46:59 PM PDT 24 761529467 ps
T111 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2556999927 Jul 19 04:47:12 PM PDT 24 Jul 19 04:47:27 PM PDT 24 156845955 ps
T963 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1459533027 Jul 19 04:46:59 PM PDT 24 Jul 19 04:47:14 PM PDT 24 132881769 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1857569483 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:05 PM PDT 24 59196296 ps
T965 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2534284828 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:04 PM PDT 24 154384247 ps
T966 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3517959892 Jul 19 04:47:08 PM PDT 24 Jul 19 04:47:23 PM PDT 24 109969755 ps
T967 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2258565086 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:19 PM PDT 24 20919089 ps
T118 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3288275970 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:20 PM PDT 24 218767458 ps
T121 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.917884002 Jul 19 04:46:46 PM PDT 24 Jul 19 04:46:57 PM PDT 24 143510301 ps
T968 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.334302764 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:16 PM PDT 24 38673593 ps
T969 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3104560282 Jul 19 04:47:08 PM PDT 24 Jul 19 04:47:25 PM PDT 24 478099193 ps
T115 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1827517305 Jul 19 04:47:05 PM PDT 24 Jul 19 04:47:20 PM PDT 24 63414375 ps
T970 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1906883963 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:29 PM PDT 24 663043608 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2357321222 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:06 PM PDT 24 612236899 ps
T113 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.135644386 Jul 19 04:47:09 PM PDT 24 Jul 19 04:47:24 PM PDT 24 472416265 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4010013197 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:04 PM PDT 24 89707988 ps
T973 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2453183087 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:58 PM PDT 24 278794444 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.518186730 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:03 PM PDT 24 29789731 ps
T975 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.29878244 Jul 19 04:47:04 PM PDT 24 Jul 19 04:47:18 PM PDT 24 49562468 ps
T976 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4107729130 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:08 PM PDT 24 135894524 ps
T123 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3649982880 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:09 PM PDT 24 1025575936 ps
T179 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1365904725 Jul 19 04:46:53 PM PDT 24 Jul 19 04:47:03 PM PDT 24 113159041 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3834139714 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:08 PM PDT 24 94746068 ps
T978 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.366802975 Jul 19 04:47:12 PM PDT 24 Jul 19 04:47:29 PM PDT 24 26147849 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3300158195 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:06 PM PDT 24 411123435 ps
T180 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3766408765 Jul 19 04:47:10 PM PDT 24 Jul 19 04:47:23 PM PDT 24 15126574 ps
T980 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3306167046 Jul 19 04:47:09 PM PDT 24 Jul 19 04:47:23 PM PDT 24 32505778 ps
T981 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1667211911 Jul 19 04:46:58 PM PDT 24 Jul 19 04:47:10 PM PDT 24 203307399 ps
T982 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1134508416 Jul 19 04:46:37 PM PDT 24 Jul 19 04:46:47 PM PDT 24 472182984 ps
T125 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1411587108 Jul 19 04:46:54 PM PDT 24 Jul 19 04:47:05 PM PDT 24 73051325 ps
T983 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2853702066 Jul 19 04:47:13 PM PDT 24 Jul 19 04:47:30 PM PDT 24 137606250 ps
T984 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545354510 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:18 PM PDT 24 1053810880 ps
T985 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1386731171 Jul 19 04:46:48 PM PDT 24 Jul 19 04:46:57 PM PDT 24 61217704 ps
T986 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1217286056 Jul 19 04:46:47 PM PDT 24 Jul 19 04:46:56 PM PDT 24 178551278 ps
T987 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2868497347 Jul 19 04:47:03 PM PDT 24 Jul 19 04:47:18 PM PDT 24 218570414 ps
T181 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.563407099 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:06 PM PDT 24 62889926 ps
T988 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1877411149 Jul 19 04:47:02 PM PDT 24 Jul 19 04:47:16 PM PDT 24 131645075 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.861143852 Jul 19 04:46:55 PM PDT 24 Jul 19 04:47:08 PM PDT 24 522165667 ps
T990 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.332400263 Jul 19 04:46:56 PM PDT 24 Jul 19 04:47:07 PM PDT 24 32698346 ps

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.4039528020
Short name T3
Test name
Test status
Simulation time 1374777320 ps
CPU time 10.79 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:45:07 PM PDT 24
Peak memory 226164 kb
Host smart-620c35ad-2277-4d26-a15f-66e8ca26b8c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039528020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.4039528020
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3735106772
Short name T15
Test name
Test status
Simulation time 29045391342 ps
CPU time 980.02 seconds
Started Jul 19 05:43:19 PM PDT 24
Finished Jul 19 05:59:41 PM PDT 24
Peak memory 300384 kb
Host smart-71168958-c697-4f61-a69b-d6887eea3ae5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3735106772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3735106772
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2181011744
Short name T19
Test name
Test status
Simulation time 4879565293 ps
CPU time 11.85 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:44:12 PM PDT 24
Peak memory 226244 kb
Host smart-7a8d1b96-022f-4835-852e-84000fd76818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181011744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2181011744
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2455589405
Short name T95
Test name
Test status
Simulation time 39533865 ps
CPU time 1.41 seconds
Started Jul 19 04:47:12 PM PDT 24
Finished Jul 19 04:47:27 PM PDT 24
Peak memory 219512 kb
Host smart-24dff5c8-fb34-4aa3-92c2-5ca29ed18ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455589405 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2455589405
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.391173023
Short name T20
Test name
Test status
Simulation time 298404635 ps
CPU time 7.97 seconds
Started Jul 19 05:42:46 PM PDT 24
Finished Jul 19 05:42:55 PM PDT 24
Peak memory 224708 kb
Host smart-27a07168-9d4b-4792-af92-36277b0b7726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391173023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.391173023
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1923666106
Short name T4
Test name
Test status
Simulation time 406695564 ps
CPU time 8.87 seconds
Started Jul 19 05:46:06 PM PDT 24
Finished Jul 19 05:46:16 PM PDT 24
Peak memory 226156 kb
Host smart-eaca7dae-9d59-445a-a736-0edee2b9d178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923666106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1923666106
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.4225377988
Short name T46
Test name
Test status
Simulation time 29906367931 ps
CPU time 1070.33 seconds
Started Jul 19 05:44:15 PM PDT 24
Finished Jul 19 06:02:07 PM PDT 24
Peak memory 333176 kb
Host smart-789dda39-433f-4c3c-b01c-e66f824e3659
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4225377988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.4225377988
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1448944341
Short name T150
Test name
Test status
Simulation time 89834962200 ps
CPU time 455.27 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:52:16 PM PDT 24
Peak memory 283784 kb
Host smart-8908e6dc-317f-408b-abdd-94eb9c057525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448944341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1448944341
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1312817227
Short name T139
Test name
Test status
Simulation time 17302509834 ps
CPU time 195.47 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:48:43 PM PDT 24
Peak memory 267668 kb
Host smart-96a7e1bf-faa3-4a44-b507-9920f4468ca8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1312817227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1312817227
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2458769480
Short name T7
Test name
Test status
Simulation time 693010902 ps
CPU time 13.69 seconds
Started Jul 19 05:43:18 PM PDT 24
Finished Jul 19 05:43:34 PM PDT 24
Peak memory 217528 kb
Host smart-e0d01a6a-24c6-4d30-9bd6-66fb64cfb1df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458769480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2458769480
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.685998759
Short name T76
Test name
Test status
Simulation time 124464414 ps
CPU time 21.46 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:43:05 PM PDT 24
Peak memory 282972 kb
Host smart-2f881442-77ff-4878-9f5a-43de092e1850
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685998759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.685998759
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1595556823
Short name T11
Test name
Test status
Simulation time 27008091 ps
CPU time 1.06 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:41 PM PDT 24
Peak memory 209032 kb
Host smart-1127e781-b42c-453c-86cf-aa3e4dd12928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595556823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1595556823
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1316401413
Short name T120
Test name
Test status
Simulation time 147241079 ps
CPU time 3.2 seconds
Started Jul 19 04:47:04 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 222136 kb
Host smart-2e0a6075-c995-432d-852a-999f369ed1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316401413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1316401413
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4245616261
Short name T100
Test name
Test status
Simulation time 1317456237 ps
CPU time 3.88 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 218124 kb
Host smart-e410762a-74af-407c-a468-687649363035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424561
6261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4245616261
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3858724455
Short name T177
Test name
Test status
Simulation time 18187772 ps
CPU time 1.39 seconds
Started Jul 19 04:46:49 PM PDT 24
Finished Jul 19 04:46:58 PM PDT 24
Peak memory 209484 kb
Host smart-6d5a88e3-8ae1-43c1-be56-05fa47e8fe15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858724455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3858724455
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3189269124
Short name T23
Test name
Test status
Simulation time 15610841340 ps
CPU time 563.44 seconds
Started Jul 19 05:45:59 PM PDT 24
Finished Jul 19 05:55:26 PM PDT 24
Peak memory 282844 kb
Host smart-0586d11c-9275-4332-8eb2-a9b21f3fdc74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189269124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3189269124
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.931007250
Short name T117
Test name
Test status
Simulation time 389445273 ps
CPU time 2.84 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:22 PM PDT 24
Peak memory 222556 kb
Host smart-d86fc7e0-aefd-4690-bce3-d3f6d05ad392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931007250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.931007250
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2842252144
Short name T310
Test name
Test status
Simulation time 1303709192 ps
CPU time 14.73 seconds
Started Jul 19 05:42:41 PM PDT 24
Finished Jul 19 05:42:57 PM PDT 24
Peak memory 218376 kb
Host smart-5d7e050c-0ab7-4383-84c8-a9746a6fb31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842252144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2842252144
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.154247874
Short name T10
Test name
Test status
Simulation time 2945168143 ps
CPU time 117.17 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:47:26 PM PDT 24
Peak memory 278196 kb
Host smart-97b3a49a-d467-449b-94c2-8f126865c40b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=154247874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.154247874
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3864261070
Short name T923
Test name
Test status
Simulation time 74574903 ps
CPU time 3 seconds
Started Jul 19 04:46:41 PM PDT 24
Finished Jul 19 04:46:51 PM PDT 24
Peak memory 217804 kb
Host smart-31cc4bbf-819f-473a-a2ef-9c9a630cf5fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864261070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3864261070
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2556999927
Short name T111
Test name
Test status
Simulation time 156845955 ps
CPU time 1.83 seconds
Started Jul 19 04:47:12 PM PDT 24
Finished Jul 19 04:47:27 PM PDT 24
Peak memory 222312 kb
Host smart-8e7d74e9-b700-4167-8812-c1277d324701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556999927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2556999927
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.861551515
Short name T142
Test name
Test status
Simulation time 92280909 ps
CPU time 1.39 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:16 PM PDT 24
Peak memory 209512 kb
Host smart-0b78a8d8-21b8-4741-a850-ade4a8810ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861551515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.861551515
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3577374262
Short name T92
Test name
Test status
Simulation time 59966477782 ps
CPU time 289.61 seconds
Started Jul 19 05:44:13 PM PDT 24
Finished Jul 19 05:49:05 PM PDT 24
Peak memory 283924 kb
Host smart-ad6a351e-463e-4ba4-848d-4146bf776bba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577374262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3577374262
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.541292284
Short name T16
Test name
Test status
Simulation time 2963338105 ps
CPU time 14.37 seconds
Started Jul 19 05:44:37 PM PDT 24
Finished Jul 19 05:44:52 PM PDT 24
Peak memory 226172 kb
Host smart-693ee413-9b39-4323-a224-3bd15df1baff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541292284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.541292284
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.56190125
Short name T136
Test name
Test status
Simulation time 14650763 ps
CPU time 0.9 seconds
Started Jul 19 05:44:15 PM PDT 24
Finished Jul 19 05:44:17 PM PDT 24
Peak memory 211928 kb
Host smart-72f35b62-18ea-452f-8d23-274ab8114691
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56190125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_volatile_unlock_smoke.56190125
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.917884002
Short name T121
Test name
Test status
Simulation time 143510301 ps
CPU time 4.73 seconds
Started Jul 19 04:46:46 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 217804 kb
Host smart-fe0924a0-76c1-4b3f-8380-f05973f4f70b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917884002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.917884002
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3288275970
Short name T118
Test name
Test status
Simulation time 218767458 ps
CPU time 1.96 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 222464 kb
Host smart-940af518-2c3d-479c-a277-60f6318d6693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288275970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3288275970
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2968581343
Short name T122
Test name
Test status
Simulation time 119227058 ps
CPU time 2.92 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 222604 kb
Host smart-40fb45ad-fa5b-4cf4-93e8-6b1cf4689d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968581343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2968581343
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2366975383
Short name T119
Test name
Test status
Simulation time 114505016 ps
CPU time 2.58 seconds
Started Jul 19 04:47:07 PM PDT 24
Finished Jul 19 04:47:22 PM PDT 24
Peak memory 217912 kb
Host smart-e91fbb1f-4006-4901-a8a8-f591e2fb2e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366975383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2366975383
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.447039298
Short name T194
Test name
Test status
Simulation time 11409960 ps
CPU time 0.81 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:42:44 PM PDT 24
Peak memory 209024 kb
Host smart-8bf45f61-4fec-4105-ace4-3b49ee381832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447039298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.447039298
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1439510118
Short name T190
Test name
Test status
Simulation time 25310924 ps
CPU time 0.83 seconds
Started Jul 19 05:42:41 PM PDT 24
Finished Jul 19 05:42:44 PM PDT 24
Peak memory 209060 kb
Host smart-b16cf682-a1f2-417e-a716-e12354d51ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439510118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1439510118
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3984500377
Short name T193
Test name
Test status
Simulation time 10369769 ps
CPU time 0.81 seconds
Started Jul 19 05:43:19 PM PDT 24
Finished Jul 19 05:43:21 PM PDT 24
Peak memory 208716 kb
Host smart-3ed59aa7-1bf8-42f7-a279-b2100a94108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984500377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3984500377
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2657376118
Short name T103
Test name
Test status
Simulation time 1107694722 ps
CPU time 1.89 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 222384 kb
Host smart-ac09a584-d643-4158-82d6-022c4fd9e273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657376118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2657376118
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.135644386
Short name T113
Test name
Test status
Simulation time 472416265 ps
CPU time 3.09 seconds
Started Jul 19 04:47:09 PM PDT 24
Finished Jul 19 04:47:24 PM PDT 24
Peak memory 213364 kb
Host smart-02c317b7-0e3a-4f91-b983-749e5714d5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135644386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.135644386
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1947479808
Short name T110
Test name
Test status
Simulation time 142928117 ps
CPU time 1.82 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:04 PM PDT 24
Peak memory 222220 kb
Host smart-2d787f23-feb9-456a-a3d7-f6e3d484bac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947479808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1947479808
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3649982880
Short name T123
Test name
Test status
Simulation time 1025575936 ps
CPU time 3.35 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:09 PM PDT 24
Peak memory 217668 kb
Host smart-1d8410f5-d7bf-4ca9-8e01-9d046dc56261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649982880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3649982880
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1827517305
Short name T115
Test name
Test status
Simulation time 63414375 ps
CPU time 2.13 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 222016 kb
Host smart-c883bcc6-2e83-41cd-8f05-b6509b5a3a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827517305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1827517305
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4205212518
Short name T38
Test name
Test status
Simulation time 1174691152 ps
CPU time 12.85 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:15 PM PDT 24
Peak memory 218316 kb
Host smart-351a5c3d-b4c9-4566-a6ab-751ede2b0617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205212518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4205212518
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.48508005
Short name T9
Test name
Test status
Simulation time 28425654872 ps
CPU time 142.96 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:45:03 PM PDT 24
Peak memory 220240 kb
Host smart-b6076cf6-03c7-4389-b368-689d26ea3009
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48508005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_erro
rs.48508005
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2312733425
Short name T910
Test name
Test status
Simulation time 38821861 ps
CPU time 1.31 seconds
Started Jul 19 04:46:52 PM PDT 24
Finished Jul 19 04:47:01 PM PDT 24
Peak memory 209604 kb
Host smart-510da1f6-2dbc-40a7-869d-33a5e006c1aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312733425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2312733425
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1745085964
Short name T172
Test name
Test status
Simulation time 42121729 ps
CPU time 1.31 seconds
Started Jul 19 04:46:41 PM PDT 24
Finished Jul 19 04:46:49 PM PDT 24
Peak memory 211632 kb
Host smart-f739bf96-d96f-49e1-bb3e-f3f993492d0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745085964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1745085964
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.407756128
Short name T884
Test name
Test status
Simulation time 354533137 ps
CPU time 1.33 seconds
Started Jul 19 04:46:52 PM PDT 24
Finished Jul 19 04:47:01 PM PDT 24
Peak memory 218048 kb
Host smart-ce0bafe1-61d1-4e0a-a300-1ae4eb1ca433
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407756128 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.407756128
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.480007794
Short name T955
Test name
Test status
Simulation time 37144782 ps
CPU time 0.83 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:54 PM PDT 24
Peak memory 209524 kb
Host smart-f618bb57-7212-444d-841c-af9460432902
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480007794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.480007794
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4028650694
Short name T130
Test name
Test status
Simulation time 210266736 ps
CPU time 1.84 seconds
Started Jul 19 04:46:43 PM PDT 24
Finished Jul 19 04:46:51 PM PDT 24
Peak memory 209448 kb
Host smart-5f1b7847-ddb0-4f79-a15a-dfef8fd5ac29
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028650694 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.4028650694
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1816248432
Short name T105
Test name
Test status
Simulation time 1612949068 ps
CPU time 10.07 seconds
Started Jul 19 04:46:39 PM PDT 24
Finished Jul 19 04:46:56 PM PDT 24
Peak memory 209448 kb
Host smart-206564f3-0515-41ac-998b-ce9be8e2464f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816248432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1816248432
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1761177274
Short name T871
Test name
Test status
Simulation time 970282592 ps
CPU time 11.28 seconds
Started Jul 19 04:46:42 PM PDT 24
Finished Jul 19 04:46:59 PM PDT 24
Peak memory 209384 kb
Host smart-2bb1474b-391f-4619-ba4a-14b7b95fa883
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761177274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1761177274
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2569233284
Short name T912
Test name
Test status
Simulation time 83091484 ps
CPU time 2.89 seconds
Started Jul 19 04:46:42 PM PDT 24
Finished Jul 19 04:46:52 PM PDT 24
Peak memory 211388 kb
Host smart-59b8036c-7033-4674-a5dd-ddf826365e4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569233284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2569233284
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1134508416
Short name T982
Test name
Test status
Simulation time 472182984 ps
CPU time 2.68 seconds
Started Jul 19 04:46:37 PM PDT 24
Finished Jul 19 04:46:47 PM PDT 24
Peak memory 217968 kb
Host smart-1dee29f8-63e8-4b9a-8b05-4c9982eb9a15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113450
8416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1134508416
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.278734852
Short name T887
Test name
Test status
Simulation time 212376662 ps
CPU time 1.99 seconds
Started Jul 19 04:46:42 PM PDT 24
Finished Jul 19 04:46:51 PM PDT 24
Peak memory 209552 kb
Host smart-53c99185-6138-47db-ac58-291190000a15
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278734852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.278734852
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3230220524
Short name T187
Test name
Test status
Simulation time 39428176 ps
CPU time 1.23 seconds
Started Jul 19 04:46:39 PM PDT 24
Finished Jul 19 04:46:47 PM PDT 24
Peak memory 209244 kb
Host smart-9abcff2a-9678-420f-98ac-b359096f3e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230220524 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3230220524
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.286626204
Short name T886
Test name
Test status
Simulation time 37991277 ps
CPU time 1.35 seconds
Started Jul 19 04:46:48 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 209540 kb
Host smart-c4c7bdd4-d9bd-4dc6-a0ec-783fa0478bc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286626204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.286626204
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.448172459
Short name T124
Test name
Test status
Simulation time 59980184 ps
CPU time 2.73 seconds
Started Jul 19 04:46:37 PM PDT 24
Finished Jul 19 04:46:47 PM PDT 24
Peak memory 217736 kb
Host smart-90f6459c-7647-412d-b569-913eb20049d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448172459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.448172459
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3213041785
Short name T889
Test name
Test status
Simulation time 38948880 ps
CPU time 1.23 seconds
Started Jul 19 04:46:45 PM PDT 24
Finished Jul 19 04:46:53 PM PDT 24
Peak memory 209496 kb
Host smart-4dbb5db1-3d39-411c-bd7d-6746a7eba58a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213041785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3213041785
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2721091444
Short name T866
Test name
Test status
Simulation time 78985172 ps
CPU time 1.77 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:56 PM PDT 24
Peak memory 209656 kb
Host smart-609161c1-f9a7-4125-be8e-8a31622cd9ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721091444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2721091444
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.908379782
Short name T928
Test name
Test status
Simulation time 16677227 ps
CPU time 0.94 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:55 PM PDT 24
Peak memory 209796 kb
Host smart-801d3cda-b91b-4f15-ab58-63e6230fb438
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908379782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.908379782
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.901399609
Short name T935
Test name
Test status
Simulation time 28057682 ps
CPU time 1.11 seconds
Started Jul 19 04:46:45 PM PDT 24
Finished Jul 19 04:46:52 PM PDT 24
Peak memory 217872 kb
Host smart-37f16a63-4363-4922-89c4-4923e4c6cd28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901399609 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.901399609
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3415555185
Short name T171
Test name
Test status
Simulation time 42538137 ps
CPU time 0.91 seconds
Started Jul 19 04:46:48 PM PDT 24
Finished Jul 19 04:46:56 PM PDT 24
Peak memory 209500 kb
Host smart-35f71463-9b6c-429f-9f9e-07978f0c95de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415555185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3415555185
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.107887393
Short name T916
Test name
Test status
Simulation time 146238502 ps
CPU time 1.59 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:55 PM PDT 24
Peak memory 208112 kb
Host smart-d0b0c2c9-15ad-4ec6-a27c-fb554c00b9a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107887393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.107887393
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.910130817
Short name T939
Test name
Test status
Simulation time 1609460688 ps
CPU time 6.31 seconds
Started Jul 19 04:46:48 PM PDT 24
Finished Jul 19 04:47:01 PM PDT 24
Peak memory 209400 kb
Host smart-d02f76b3-b621-46ac-aa0c-54567ff470d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910130817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.910130817
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3590896221
Short name T915
Test name
Test status
Simulation time 12072380206 ps
CPU time 16.77 seconds
Started Jul 19 04:46:52 PM PDT 24
Finished Jul 19 04:47:17 PM PDT 24
Peak memory 208604 kb
Host smart-c4826f9b-122b-41cb-9d2d-920e38ead5fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590896221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3590896221
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1240193663
Short name T962
Test name
Test status
Simulation time 761529467 ps
CPU time 3.06 seconds
Started Jul 19 04:46:49 PM PDT 24
Finished Jul 19 04:46:59 PM PDT 24
Peak memory 211088 kb
Host smart-b520f592-c701-41b6-b02b-d5e16fac9d36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240193663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1240193663
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1244426017
Short name T950
Test name
Test status
Simulation time 929903615 ps
CPU time 1.93 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:55 PM PDT 24
Peak memory 218512 kb
Host smart-147e8654-8422-4488-818f-7274b72feda3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124442
6017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1244426017
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1389613173
Short name T870
Test name
Test status
Simulation time 164115865 ps
CPU time 2.72 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 209488 kb
Host smart-536b52c2-3f0f-4df0-a4f7-ff62c0646e18
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389613173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1389613173
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2991178381
Short name T185
Test name
Test status
Simulation time 50376165 ps
CPU time 0.98 seconds
Started Jul 19 04:46:48 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 209564 kb
Host smart-61d80709-0818-4241-85f4-b2296f23bb78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991178381 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2991178381
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1386731171
Short name T985
Test name
Test status
Simulation time 61217704 ps
CPU time 1.42 seconds
Started Jul 19 04:46:48 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 209548 kb
Host smart-28b1701e-69f7-4f2c-8591-da6367fbc53d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386731171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1386731171
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1217286056
Short name T986
Test name
Test status
Simulation time 178551278 ps
CPU time 2.71 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:56 PM PDT 24
Peak memory 217696 kb
Host smart-e4b2ff22-f357-4122-aded-d40906d563ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217286056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1217286056
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1463052468
Short name T900
Test name
Test status
Simulation time 91510908 ps
CPU time 1.63 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:15 PM PDT 24
Peak memory 219704 kb
Host smart-a4a57bda-f7f2-4c44-b3cd-881d5bdacd65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463052468 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1463052468
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1755878232
Short name T873
Test name
Test status
Simulation time 15021981 ps
CPU time 0.89 seconds
Started Jul 19 04:47:04 PM PDT 24
Finished Jul 19 04:47:17 PM PDT 24
Peak memory 209504 kb
Host smart-b8b0a9ff-4004-487c-875a-1e990d775d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755878232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1755878232
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3306167046
Short name T980
Test name
Test status
Simulation time 32505778 ps
CPU time 1.58 seconds
Started Jul 19 04:47:09 PM PDT 24
Finished Jul 19 04:47:23 PM PDT 24
Peak memory 209452 kb
Host smart-9a589dbf-c3b6-4845-9852-1c317a84dc38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306167046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3306167046
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2608415582
Short name T945
Test name
Test status
Simulation time 447842528 ps
CPU time 4.32 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 217772 kb
Host smart-a417ca9b-20e2-41e0-87bb-dd1b581ecdbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608415582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2608415582
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.334302764
Short name T968
Test name
Test status
Simulation time 38673593 ps
CPU time 1.44 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:16 PM PDT 24
Peak memory 217940 kb
Host smart-15dad70f-4a8b-4939-8592-b94883626f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334302764 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.334302764
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2174874026
Short name T890
Test name
Test status
Simulation time 12976044 ps
CPU time 1.03 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 209240 kb
Host smart-8cbe5ce4-63af-4501-862a-d52d5e677363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174874026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2174874026
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.787269803
Short name T932
Test name
Test status
Simulation time 75751341 ps
CPU time 1.85 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:16 PM PDT 24
Peak memory 209532 kb
Host smart-cba8079c-f225-4d97-8541-bfcb6479b7ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787269803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.787269803
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1638419209
Short name T99
Test name
Test status
Simulation time 99522545 ps
CPU time 2.01 seconds
Started Jul 19 04:47:06 PM PDT 24
Finished Jul 19 04:47:21 PM PDT 24
Peak memory 217952 kb
Host smart-c0f5bba1-ec89-4d93-a1f7-00c058b4c1fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638419209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1638419209
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1037581950
Short name T155
Test name
Test status
Simulation time 31275257 ps
CPU time 1.21 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:17 PM PDT 24
Peak memory 217804 kb
Host smart-d361d586-5e86-4573-91dd-caeff769b14f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037581950 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1037581950
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.701692495
Short name T872
Test name
Test status
Simulation time 14905453 ps
CPU time 1.19 seconds
Started Jul 19 04:47:06 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 209324 kb
Host smart-0bd24de0-0404-45f0-8518-b70b03e2f2b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701692495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.701692495
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3621565928
Short name T937
Test name
Test status
Simulation time 23163670 ps
CPU time 1.29 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:19 PM PDT 24
Peak memory 211688 kb
Host smart-29a791ed-715f-4f87-8b64-6b229682e344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621565928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3621565928
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2868497347
Short name T987
Test name
Test status
Simulation time 218570414 ps
CPU time 1.84 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 217808 kb
Host smart-6cbe6c9b-a4c0-4531-91e4-310dc1d29e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868497347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2868497347
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2391448481
Short name T94
Test name
Test status
Simulation time 26003457 ps
CPU time 1.3 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:19 PM PDT 24
Peak memory 222144 kb
Host smart-1d418bec-7f82-45bd-ae65-adee218079c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391448481 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2391448481
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4183229004
Short name T882
Test name
Test status
Simulation time 61249202 ps
CPU time 0.86 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:19 PM PDT 24
Peak memory 209496 kb
Host smart-c7798b62-326a-43d2-ab31-c5a3d484d888
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183229004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4183229004
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.29878244
Short name T975
Test name
Test status
Simulation time 49562468 ps
CPU time 0.94 seconds
Started Jul 19 04:47:04 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 209532 kb
Host smart-a441de48-5daa-4c6a-b0c3-02154e046b96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
same_csr_outstanding.29878244
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3820582456
Short name T96
Test name
Test status
Simulation time 324509522 ps
CPU time 2.07 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:17 PM PDT 24
Peak memory 217904 kb
Host smart-3c81913f-a657-41df-b7fb-58d742cc9600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820582456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3820582456
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.793207338
Short name T899
Test name
Test status
Simulation time 121570191 ps
CPU time 2.03 seconds
Started Jul 19 04:47:09 PM PDT 24
Finished Jul 19 04:47:23 PM PDT 24
Peak memory 222324 kb
Host smart-93df9623-fd0b-4a51-a6cb-c9369e01a8ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793207338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.793207338
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.679661723
Short name T906
Test name
Test status
Simulation time 57292486 ps
CPU time 2.04 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 223180 kb
Host smart-a981ad4e-0969-4f59-8617-d9f7e985fc05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679661723 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.679661723
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4018948649
Short name T880
Test name
Test status
Simulation time 41263350 ps
CPU time 0.84 seconds
Started Jul 19 04:47:08 PM PDT 24
Finished Jul 19 04:47:22 PM PDT 24
Peak memory 209380 kb
Host smart-f4c73a7c-b1d9-4072-bef5-0cb234da97cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018948649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4018948649
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4060292136
Short name T961
Test name
Test status
Simulation time 56186544 ps
CPU time 2.43 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 217792 kb
Host smart-95e48e90-57ca-4c71-ba7b-8489b9fd9bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060292136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4060292136
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2258565086
Short name T967
Test name
Test status
Simulation time 20919089 ps
CPU time 1.35 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:19 PM PDT 24
Peak memory 217808 kb
Host smart-439f8f13-f087-4293-9742-40b108495d7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258565086 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2258565086
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2950958796
Short name T941
Test name
Test status
Simulation time 51974413 ps
CPU time 1.06 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:15 PM PDT 24
Peak memory 209404 kb
Host smart-1a334f8f-88c8-44fa-860e-d2a5140776b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950958796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2950958796
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3034837120
Short name T894
Test name
Test status
Simulation time 24083302 ps
CPU time 1.42 seconds
Started Jul 19 04:47:07 PM PDT 24
Finished Jul 19 04:47:21 PM PDT 24
Peak memory 209176 kb
Host smart-6a969cf2-04dc-4e64-9eaf-be346ab9dd46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034837120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3034837120
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.953303661
Short name T917
Test name
Test status
Simulation time 921425932 ps
CPU time 4.22 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:22 PM PDT 24
Peak memory 217724 kb
Host smart-8205d8b4-70b2-4886-9045-565d25d3620f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953303661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.953303661
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.492713787
Short name T929
Test name
Test status
Simulation time 62693095 ps
CPU time 1.36 seconds
Started Jul 19 04:47:09 PM PDT 24
Finished Jul 19 04:47:23 PM PDT 24
Peak memory 217732 kb
Host smart-192b6c1e-e5c3-4eb6-8fa5-5a15956bfadb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492713787 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.492713787
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1236682528
Short name T174
Test name
Test status
Simulation time 12272372 ps
CPU time 0.99 seconds
Started Jul 19 04:47:13 PM PDT 24
Finished Jul 19 04:47:29 PM PDT 24
Peak memory 209520 kb
Host smart-022f371d-6785-43e3-98bb-57b41949e1ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236682528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1236682528
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1139379476
Short name T183
Test name
Test status
Simulation time 110174554 ps
CPU time 1.15 seconds
Started Jul 19 04:47:13 PM PDT 24
Finished Jul 19 04:47:30 PM PDT 24
Peak memory 209604 kb
Host smart-c125f3a8-3cae-4669-a017-99190e3a3234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139379476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1139379476
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1059484309
Short name T116
Test name
Test status
Simulation time 47692106 ps
CPU time 2.05 seconds
Started Jul 19 04:47:11 PM PDT 24
Finished Jul 19 04:47:25 PM PDT 24
Peak memory 218264 kb
Host smart-ef314d45-f46e-4634-a2b3-08fc2798378e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059484309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1059484309
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1651872427
Short name T102
Test name
Test status
Simulation time 411287679 ps
CPU time 3.9 seconds
Started Jul 19 04:47:15 PM PDT 24
Finished Jul 19 04:47:34 PM PDT 24
Peak memory 217804 kb
Host smart-51bdaed5-3e26-4ecb-9e29-091a1099443c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651872427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1651872427
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.478769804
Short name T104
Test name
Test status
Simulation time 27571712 ps
CPU time 0.87 seconds
Started Jul 19 04:47:15 PM PDT 24
Finished Jul 19 04:47:31 PM PDT 24
Peak memory 209444 kb
Host smart-23ef86c8-ce5f-4346-9100-d908236e3a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478769804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.478769804
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3026848920
Short name T951
Test name
Test status
Simulation time 26079400 ps
CPU time 1.25 seconds
Started Jul 19 04:47:11 PM PDT 24
Finished Jul 19 04:47:25 PM PDT 24
Peak memory 209592 kb
Host smart-839c6878-2c0c-40b7-b230-77adc0f9eef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026848920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3026848920
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.366802975
Short name T978
Test name
Test status
Simulation time 26147849 ps
CPU time 1.81 seconds
Started Jul 19 04:47:12 PM PDT 24
Finished Jul 19 04:47:29 PM PDT 24
Peak memory 217772 kb
Host smart-cd470e3b-5f85-4a0c-b2ea-3701070a813b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366802975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.366802975
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1082067587
Short name T956
Test name
Test status
Simulation time 148519513 ps
CPU time 1.6 seconds
Started Jul 19 04:47:16 PM PDT 24
Finished Jul 19 04:47:32 PM PDT 24
Peak memory 218916 kb
Host smart-022b5b98-12e8-4cde-b494-52e3971ef957
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082067587 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1082067587
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3766408765
Short name T180
Test name
Test status
Simulation time 15126574 ps
CPU time 0.82 seconds
Started Jul 19 04:47:10 PM PDT 24
Finished Jul 19 04:47:23 PM PDT 24
Peak memory 209100 kb
Host smart-72ff1aaf-6cff-4898-836c-ed089f62492d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766408765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3766408765
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3015652135
Short name T933
Test name
Test status
Simulation time 89111725 ps
CPU time 1.02 seconds
Started Jul 19 04:47:12 PM PDT 24
Finished Jul 19 04:47:28 PM PDT 24
Peak memory 209540 kb
Host smart-a851ec10-cf8a-41d2-a74c-d7cdf266304e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015652135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3015652135
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2853702066
Short name T983
Test name
Test status
Simulation time 137606250 ps
CPU time 1.87 seconds
Started Jul 19 04:47:13 PM PDT 24
Finished Jul 19 04:47:30 PM PDT 24
Peak memory 217792 kb
Host smart-1936ed5d-6943-449b-8c69-00354621871c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853702066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2853702066
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2792368016
Short name T878
Test name
Test status
Simulation time 77613896 ps
CPU time 1.72 seconds
Started Jul 19 04:47:10 PM PDT 24
Finished Jul 19 04:47:24 PM PDT 24
Peak memory 222264 kb
Host smart-963c8bf3-0f1f-46d9-8624-ed320974b94d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792368016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2792368016
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.643831027
Short name T958
Test name
Test status
Simulation time 17973281 ps
CPU time 1.1 seconds
Started Jul 19 04:47:12 PM PDT 24
Finished Jul 19 04:47:27 PM PDT 24
Peak memory 218884 kb
Host smart-0a025ca6-f8bf-4393-858d-0e912c8fad28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643831027 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.643831027
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.867401258
Short name T173
Test name
Test status
Simulation time 56242153 ps
CPU time 0.91 seconds
Started Jul 19 04:47:13 PM PDT 24
Finished Jul 19 04:47:29 PM PDT 24
Peak memory 209208 kb
Host smart-fe207548-d2ec-42cd-833f-314fde240f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867401258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.867401258
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1327996500
Short name T914
Test name
Test status
Simulation time 329190821 ps
CPU time 1.8 seconds
Started Jul 19 04:47:11 PM PDT 24
Finished Jul 19 04:47:25 PM PDT 24
Peak memory 217688 kb
Host smart-e5c21111-8c3b-4400-9bee-510418e884c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327996500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1327996500
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2280076203
Short name T898
Test name
Test status
Simulation time 138240774 ps
CPU time 2.88 seconds
Started Jul 19 04:47:13 PM PDT 24
Finished Jul 19 04:47:31 PM PDT 24
Peak memory 218152 kb
Host smart-8525e794-9f63-4889-bab1-eba1b8ed4f65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280076203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2280076203
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.223143208
Short name T195
Test name
Test status
Simulation time 279852230 ps
CPU time 1.94 seconds
Started Jul 19 04:47:13 PM PDT 24
Finished Jul 19 04:47:30 PM PDT 24
Peak memory 221828 kb
Host smart-6cf3a49f-d0c7-474b-9816-905149f64169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223143208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.223143208
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.151486323
Short name T176
Test name
Test status
Simulation time 19079030 ps
CPU time 1.38 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:55 PM PDT 24
Peak memory 209724 kb
Host smart-4c8646b1-628b-4e6d-af26-953757a7062c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151486323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.151486323
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.656667733
Short name T925
Test name
Test status
Simulation time 189209874 ps
CPU time 1.48 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 209608 kb
Host smart-82ad6f8d-4139-40c5-8e8e-e002c2901b00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656667733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.656667733
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1365904725
Short name T179
Test name
Test status
Simulation time 113159041 ps
CPU time 1.18 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 211772 kb
Host smart-6d9e9753-8bcc-496e-9bed-b855133874cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365904725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1365904725
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3278328002
Short name T927
Test name
Test status
Simulation time 64065220 ps
CPU time 1.03 seconds
Started Jul 19 04:46:46 PM PDT 24
Finished Jul 19 04:46:54 PM PDT 24
Peak memory 219368 kb
Host smart-287868eb-ee79-45a4-b2d0-f15168e1b4cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278328002 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3278328002
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.654943934
Short name T106
Test name
Test status
Simulation time 16816507 ps
CPU time 0.92 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 209224 kb
Host smart-5edf465e-30e0-44ef-8f09-69cf699cd227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654943934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.654943934
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.900669537
Short name T940
Test name
Test status
Simulation time 49532976 ps
CPU time 1.59 seconds
Started Jul 19 04:46:46 PM PDT 24
Finished Jul 19 04:46:55 PM PDT 24
Peak memory 209368 kb
Host smart-e00b9c51-e8e6-42eb-8a18-caeee69dcea8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900669537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.900669537
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3910797608
Short name T892
Test name
Test status
Simulation time 907825961 ps
CPU time 3.09 seconds
Started Jul 19 04:46:45 PM PDT 24
Finished Jul 19 04:46:55 PM PDT 24
Peak memory 208228 kb
Host smart-1a1ae42e-ab79-427f-8efb-b1416438d41b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910797608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3910797608
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3494834615
Short name T888
Test name
Test status
Simulation time 1656838969 ps
CPU time 19.05 seconds
Started Jul 19 04:46:46 PM PDT 24
Finished Jul 19 04:47:12 PM PDT 24
Peak memory 209444 kb
Host smart-513418ba-8d4b-495a-bcde-1a2ff8860a8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494834615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3494834615
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2992316513
Short name T904
Test name
Test status
Simulation time 553247786 ps
CPU time 1.36 seconds
Started Jul 19 04:46:49 PM PDT 24
Finished Jul 19 04:46:58 PM PDT 24
Peak memory 209472 kb
Host smart-5065d6fa-f360-49a5-bd9e-66646033f6fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992316513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2992316513
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2453183087
Short name T973
Test name
Test status
Simulation time 278794444 ps
CPU time 4.03 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:58 PM PDT 24
Peak memory 222844 kb
Host smart-d4ffdf63-a189-4aa4-bf8d-d7aff252f714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245318
3087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2453183087
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1889109641
Short name T907
Test name
Test status
Simulation time 239087579 ps
CPU time 1.44 seconds
Started Jul 19 04:46:46 PM PDT 24
Finished Jul 19 04:46:54 PM PDT 24
Peak memory 209504 kb
Host smart-b81acc33-025e-4a8f-b340-bfbef6481696
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889109641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1889109641
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3719846278
Short name T943
Test name
Test status
Simulation time 48408738 ps
CPU time 1.33 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:56 PM PDT 24
Peak memory 209596 kb
Host smart-88217be9-9cf7-4cd5-9215-ab9413a28aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719846278 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3719846278
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4058067203
Short name T126
Test name
Test status
Simulation time 178450672 ps
CPU time 1.83 seconds
Started Jul 19 04:46:48 PM PDT 24
Finished Jul 19 04:46:58 PM PDT 24
Peak memory 209564 kb
Host smart-2e7dcadf-d5d1-4f61-a8dd-108af5e73daa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058067203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.4058067203
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2108532464
Short name T109
Test name
Test status
Simulation time 168710062 ps
CPU time 1.58 seconds
Started Jul 19 04:46:48 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 218772 kb
Host smart-81d78781-50d9-4ded-a84e-858e8dd54a27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108532464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2108532464
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.518186730
Short name T974
Test name
Test status
Simulation time 29789731 ps
CPU time 1.49 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 209584 kb
Host smart-5ea9fbcf-5746-4169-b44c-2eb7ccb811f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518186730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.518186730
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2327915063
Short name T127
Test name
Test status
Simulation time 129404683 ps
CPU time 1.78 seconds
Started Jul 19 04:46:59 PM PDT 24
Finished Jul 19 04:47:11 PM PDT 24
Peak memory 209452 kb
Host smart-34e2cca1-5c1d-490e-8011-583ed110a78b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327915063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2327915063
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1667211911
Short name T981
Test name
Test status
Simulation time 203307399 ps
CPU time 1.2 seconds
Started Jul 19 04:46:58 PM PDT 24
Finished Jul 19 04:47:10 PM PDT 24
Peak memory 211796 kb
Host smart-feefdf23-1fac-4f09-be2c-1f6fd099415f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667211911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1667211911
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1126945301
Short name T924
Test name
Test status
Simulation time 27908379 ps
CPU time 1.57 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:07 PM PDT 24
Peak memory 222296 kb
Host smart-d51ea58e-e431-482d-b5be-e25df373a806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126945301 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1126945301
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2204774306
Short name T175
Test name
Test status
Simulation time 17280059 ps
CPU time 1.15 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 209476 kb
Host smart-d5cb2b14-d254-4a22-96e4-a5265e88f3d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204774306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2204774306
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.107746989
Short name T876
Test name
Test status
Simulation time 189364871 ps
CPU time 1.13 seconds
Started Jul 19 04:46:58 PM PDT 24
Finished Jul 19 04:47:09 PM PDT 24
Peak memory 208020 kb
Host smart-6e61848b-a8cb-4c7f-827c-6c001c5ffb3b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107746989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.107746989
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4132099660
Short name T936
Test name
Test status
Simulation time 2166505343 ps
CPU time 6.05 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:07 PM PDT 24
Peak memory 209444 kb
Host smart-f7c77744-3ac3-4f6f-b953-ead60e06e62a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132099660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4132099660
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.43801708
Short name T938
Test name
Test status
Simulation time 1796962016 ps
CPU time 11.01 seconds
Started Jul 19 04:46:45 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 209428 kb
Host smart-6cef4b48-5974-4c22-b917-d1524de1bbd0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43801708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.43801708
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1985917895
Short name T949
Test name
Test status
Simulation time 459510730 ps
CPU time 1.23 seconds
Started Jul 19 04:46:46 PM PDT 24
Finished Jul 19 04:46:53 PM PDT 24
Peak memory 210868 kb
Host smart-c1162c6f-3bb4-422c-b9d9-625bd120c5f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985917895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1985917895
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1972992025
Short name T879
Test name
Test status
Simulation time 74110607 ps
CPU time 2.49 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 218816 kb
Host smart-6aebf3eb-cd69-4665-a911-330519f9bcf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197299
2025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1972992025
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.262795297
Short name T874
Test name
Test status
Simulation time 90406819 ps
CPU time 1.74 seconds
Started Jul 19 04:46:47 PM PDT 24
Finished Jul 19 04:46:55 PM PDT 24
Peak memory 209496 kb
Host smart-06dc71e7-32ef-4a17-8c30-c7bc659b8cf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262795297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.262795297
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1857569483
Short name T964
Test name
Test status
Simulation time 59196296 ps
CPU time 1.19 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:05 PM PDT 24
Peak memory 209672 kb
Host smart-792fb394-8f25-4f39-bf14-2a1e98f0fac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857569483 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1857569483
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1689580575
Short name T948
Test name
Test status
Simulation time 95478459 ps
CPU time 1.07 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:04 PM PDT 24
Peak memory 209592 kb
Host smart-96e253cb-e80f-4b61-92d5-849199f3c4a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689580575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1689580575
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4107729130
Short name T976
Test name
Test status
Simulation time 135894524 ps
CPU time 2.51 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 217808 kb
Host smart-468eaedd-ebe4-42cf-aa1f-9c6b668cbb15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107729130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4107729130
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3300158195
Short name T979
Test name
Test status
Simulation time 411123435 ps
CPU time 3.02 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:06 PM PDT 24
Peak memory 222704 kb
Host smart-e7f7f3df-dc65-46f5-88b7-be49db8b1c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300158195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3300158195
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3323763511
Short name T178
Test name
Test status
Simulation time 17931800 ps
CPU time 1.32 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 209524 kb
Host smart-ed5fe0fe-4d1d-4787-b41b-760b0ca565d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323763511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3323763511
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3834139714
Short name T977
Test name
Test status
Simulation time 94746068 ps
CPU time 1.86 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 209440 kb
Host smart-ec2d7130-d00d-4f20-8c4a-cceab121f23c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834139714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3834139714
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.563407099
Short name T181
Test name
Test status
Simulation time 62889926 ps
CPU time 1.2 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:06 PM PDT 24
Peak memory 211808 kb
Host smart-b6d10ad4-2fb5-4302-87f6-dca12afbc37f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563407099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.563407099
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1576155421
Short name T901
Test name
Test status
Simulation time 103681509 ps
CPU time 1.23 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:05 PM PDT 24
Peak memory 217792 kb
Host smart-6c1e32f6-78d3-4ee1-af16-218659f1c1b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576155421 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1576155421
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3828379312
Short name T905
Test name
Test status
Simulation time 15837612 ps
CPU time 1.11 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 209548 kb
Host smart-838fdf11-efb8-47c6-8fda-e71765c2b23b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828379312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3828379312
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4010013197
Short name T972
Test name
Test status
Simulation time 89707988 ps
CPU time 1.67 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:04 PM PDT 24
Peak memory 208144 kb
Host smart-2311b813-6866-47d3-925f-0ab0c72fcb69
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010013197 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.4010013197
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.861143852
Short name T989
Test name
Test status
Simulation time 522165667 ps
CPU time 4.7 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 209232 kb
Host smart-93002174-2638-479b-a7b0-9ebe2198795e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861143852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.861143852
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4106914507
Short name T913
Test name
Test status
Simulation time 1378422185 ps
CPU time 6.88 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:09 PM PDT 24
Peak memory 208796 kb
Host smart-4d64473d-7b00-4baf-b766-b1b291ea842f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106914507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4106914507
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.161966769
Short name T930
Test name
Test status
Simulation time 158831837 ps
CPU time 4.2 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:07 PM PDT 24
Peak memory 211176 kb
Host smart-aba94e2e-55f2-4c91-b10c-dd987419c715
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161966769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.161966769
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2357321222
Short name T971
Test name
Test status
Simulation time 612236899 ps
CPU time 3.93 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:06 PM PDT 24
Peak memory 219336 kb
Host smart-c2f8b8dc-8af2-4502-ae58-a70b3d90cb31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235732
1222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2357321222
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.398230363
Short name T926
Test name
Test status
Simulation time 317255922 ps
CPU time 1.21 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:05 PM PDT 24
Peak memory 209528 kb
Host smart-98dbbc50-ba94-4cb9-89dc-55da8393672d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398230363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.398230363
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.332400263
Short name T990
Test name
Test status
Simulation time 32698346 ps
CPU time 1.59 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:07 PM PDT 24
Peak memory 209212 kb
Host smart-16545f94-4803-4bb0-a43a-21d48c0f99af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332400263 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.332400263
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2889529892
Short name T895
Test name
Test status
Simulation time 105328054 ps
CPU time 1.03 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:06 PM PDT 24
Peak memory 209632 kb
Host smart-5cfe4726-c988-46cf-a593-4231f1e2677b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889529892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2889529892
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1088939958
Short name T942
Test name
Test status
Simulation time 1148457893 ps
CPU time 3.51 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:07 PM PDT 24
Peak memory 217776 kb
Host smart-29eb7de1-b5b6-4aa3-8d5f-267bcaf3d003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088939958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1088939958
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1411587108
Short name T125
Test name
Test status
Simulation time 73051325 ps
CPU time 2.69 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:05 PM PDT 24
Peak memory 222496 kb
Host smart-4d1f65a0-dd07-4926-b16a-3edb781dbb50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411587108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1411587108
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2999917174
Short name T897
Test name
Test status
Simulation time 27668385 ps
CPU time 1.32 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 217892 kb
Host smart-703b6fa1-b4f6-4486-b578-6bb2abf17532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999917174 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2999917174
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2992044415
Short name T953
Test name
Test status
Simulation time 22341654 ps
CPU time 0.89 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:06 PM PDT 24
Peak memory 209528 kb
Host smart-38a4542f-e1f9-4cb8-baa2-8a87a2a4bac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992044415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2992044415
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2534284828
Short name T965
Test name
Test status
Simulation time 154384247 ps
CPU time 1.19 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:04 PM PDT 24
Peak memory 209360 kb
Host smart-c3e213b7-03d6-41f3-ab62-1feb35f87357
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534284828 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2534284828
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1159101519
Short name T934
Test name
Test status
Simulation time 1057257546 ps
CPU time 6.01 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:11 PM PDT 24
Peak memory 209228 kb
Host smart-18cce924-9e32-4c8b-9760-ca875453f782
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159101519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1159101519
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4005450091
Short name T112
Test name
Test status
Simulation time 420037303 ps
CPU time 5.15 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:07 PM PDT 24
Peak memory 209352 kb
Host smart-b27c2b03-4864-4852-ab4b-138d6894adee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005450091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4005450091
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.287865860
Short name T911
Test name
Test status
Simulation time 463499542 ps
CPU time 1.96 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:05 PM PDT 24
Peak memory 211152 kb
Host smart-bdc54f47-9e2d-4aee-9d04-6c7efba47b76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287865860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.287865860
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1313275426
Short name T920
Test name
Test status
Simulation time 566753105 ps
CPU time 3.26 seconds
Started Jul 19 04:46:58 PM PDT 24
Finished Jul 19 04:47:13 PM PDT 24
Peak memory 221180 kb
Host smart-016e5b44-10e5-4e99-a1f8-2093267a848d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131327
5426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1313275426
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4000243295
Short name T893
Test name
Test status
Simulation time 598833185 ps
CPU time 2.18 seconds
Started Jul 19 04:46:57 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 209464 kb
Host smart-09073b38-c4e4-4fe0-bd1b-2c275853d1c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000243295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4000243295
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1899558871
Short name T946
Test name
Test status
Simulation time 29831595 ps
CPU time 1.1 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:06 PM PDT 24
Peak memory 209632 kb
Host smart-e390215c-6c5c-43e7-94f7-807eb08cb292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899558871 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1899558871
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3766715474
Short name T885
Test name
Test status
Simulation time 43475199 ps
CPU time 1.31 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 211640 kb
Host smart-d8af6670-caf7-48e7-ae3d-71c0acfd7e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766715474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3766715474
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2309383131
Short name T921
Test name
Test status
Simulation time 123384641 ps
CPU time 4.71 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:10 PM PDT 24
Peak memory 217804 kb
Host smart-91e504a6-fa8b-4b19-8bb7-ac2e4a9b374a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309383131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2309383131
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2819808123
Short name T896
Test name
Test status
Simulation time 131961417 ps
CPU time 1.78 seconds
Started Jul 19 04:46:57 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 219544 kb
Host smart-535329b1-713d-4254-ad9a-6fe2314168e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819808123 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2819808123
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4078819171
Short name T952
Test name
Test status
Simulation time 51232000 ps
CPU time 0.92 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:05 PM PDT 24
Peak memory 209580 kb
Host smart-2aa9dc19-9bbb-4257-a503-21433c1a2ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078819171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4078819171
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2378232412
Short name T959
Test name
Test status
Simulation time 437998677 ps
CPU time 1.29 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:07 PM PDT 24
Peak memory 208200 kb
Host smart-356fbe8b-a18d-4048-9137-f37655145dbb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378232412 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2378232412
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3729704385
Short name T877
Test name
Test status
Simulation time 551774441 ps
CPU time 3.9 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:07 PM PDT 24
Peak memory 208696 kb
Host smart-fb500442-74c9-40c2-b9c6-44ba8ad8b956
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729704385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3729704385
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3543361002
Short name T875
Test name
Test status
Simulation time 689940567 ps
CPU time 18.84 seconds
Started Jul 19 04:46:57 PM PDT 24
Finished Jul 19 04:47:26 PM PDT 24
Peak memory 209240 kb
Host smart-f3487cda-757a-40fe-a8a0-a8f757ff77a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543361002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3543361002
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3352021462
Short name T867
Test name
Test status
Simulation time 307584860 ps
CPU time 2.86 seconds
Started Jul 19 04:46:53 PM PDT 24
Finished Jul 19 04:47:04 PM PDT 24
Peak memory 211372 kb
Host smart-fd9433e9-96ba-41f1-a7a7-3bb73258e510
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352021462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3352021462
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1459533027
Short name T963
Test name
Test status
Simulation time 132881769 ps
CPU time 3.87 seconds
Started Jul 19 04:46:59 PM PDT 24
Finished Jul 19 04:47:14 PM PDT 24
Peak memory 217764 kb
Host smart-99879683-4269-440f-883b-c9184bc77acc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145953
3027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1459533027
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.888530106
Short name T881
Test name
Test status
Simulation time 33651977 ps
CPU time 1.21 seconds
Started Jul 19 04:46:54 PM PDT 24
Finished Jul 19 04:47:03 PM PDT 24
Peak memory 209516 kb
Host smart-097e62a3-a627-4b91-be37-cca40a5099a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888530106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.888530106
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2989775045
Short name T918
Test name
Test status
Simulation time 29043151 ps
CPU time 1.05 seconds
Started Jul 19 04:46:55 PM PDT 24
Finished Jul 19 04:47:04 PM PDT 24
Peak memory 209676 kb
Host smart-03dfe892-b617-4883-998b-bd3ed9c0a286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989775045 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2989775045
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2696095371
Short name T188
Test name
Test status
Simulation time 67795751 ps
CPU time 1.32 seconds
Started Jul 19 04:46:57 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 209496 kb
Host smart-06cad4cb-4df4-4605-9324-386eba991ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696095371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2696095371
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1642189255
Short name T107
Test name
Test status
Simulation time 24409377 ps
CPU time 1.69 seconds
Started Jul 19 04:46:57 PM PDT 24
Finished Jul 19 04:47:08 PM PDT 24
Peak memory 217904 kb
Host smart-47517cbc-6982-422f-97c5-9a3145b8c767
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642189255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1642189255
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3192947615
Short name T931
Test name
Test status
Simulation time 316984748 ps
CPU time 1.69 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:15 PM PDT 24
Peak memory 218788 kb
Host smart-90fb963b-06e3-407b-ab7e-d75b10eb3322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192947615 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3192947615
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4259730302
Short name T869
Test name
Test status
Simulation time 55053070 ps
CPU time 1.1 seconds
Started Jul 19 04:47:07 PM PDT 24
Finished Jul 19 04:47:21 PM PDT 24
Peak memory 209268 kb
Host smart-b8ec94a4-bce5-4585-89df-ca42890e268f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259730302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4259730302
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3853477743
Short name T902
Test name
Test status
Simulation time 36225501 ps
CPU time 1.07 seconds
Started Jul 19 04:47:01 PM PDT 24
Finished Jul 19 04:47:14 PM PDT 24
Peak memory 209424 kb
Host smart-20fc4a75-962a-4289-81ac-5a72f5d4d14f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853477743 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3853477743
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1906883963
Short name T970
Test name
Test status
Simulation time 663043608 ps
CPU time 14.39 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:29 PM PDT 24
Peak memory 209312 kb
Host smart-e57e0991-2b33-4adc-993f-d2aee1a03fc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906883963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1906883963
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3859258980
Short name T883
Test name
Test status
Simulation time 17381127697 ps
CPU time 9.13 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:14 PM PDT 24
Peak memory 209504 kb
Host smart-9c09ae91-45dc-4827-9749-24a40e6f3afc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859258980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3859258980
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3500397394
Short name T922
Test name
Test status
Simulation time 793563438 ps
CPU time 2.19 seconds
Started Jul 19 04:46:57 PM PDT 24
Finished Jul 19 04:47:09 PM PDT 24
Peak memory 210912 kb
Host smart-c1966e86-d006-4b98-a024-ce1c8b7c5d05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500397394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3500397394
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.272478324
Short name T891
Test name
Test status
Simulation time 417700578 ps
CPU time 4.19 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 219364 kb
Host smart-e1189f6a-40a3-4fd7-a5e4-5e9be5e7d5cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272478
324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.272478324
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3436016052
Short name T129
Test name
Test status
Simulation time 162502102 ps
CPU time 1.24 seconds
Started Jul 19 04:46:56 PM PDT 24
Finished Jul 19 04:47:06 PM PDT 24
Peak memory 209532 kb
Host smart-bd10747f-10ef-4b82-aa16-10b21661afb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436016052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3436016052
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1122137879
Short name T960
Test name
Test status
Simulation time 160771127 ps
CPU time 1.13 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:15 PM PDT 24
Peak memory 209196 kb
Host smart-57e03758-bbcb-4365-968b-b915338f9d73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122137879 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1122137879
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2157066161
Short name T186
Test name
Test status
Simulation time 26444995 ps
CPU time 1.15 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:14 PM PDT 24
Peak memory 209612 kb
Host smart-ed91d124-49f2-4a3a-9fbc-5c3719075787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157066161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2157066161
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3517959892
Short name T966
Test name
Test status
Simulation time 109969755 ps
CPU time 3.17 seconds
Started Jul 19 04:47:08 PM PDT 24
Finished Jul 19 04:47:23 PM PDT 24
Peak memory 217792 kb
Host smart-c017a7cd-bb20-4e9e-92bc-780209325b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517959892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3517959892
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1282123547
Short name T101
Test name
Test status
Simulation time 76688503 ps
CPU time 3.36 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:21 PM PDT 24
Peak memory 222424 kb
Host smart-dbee43d7-df61-4404-985a-806f9e829f58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282123547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1282123547
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.703047941
Short name T168
Test name
Test status
Simulation time 30665830 ps
CPU time 1.71 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 217452 kb
Host smart-5de602e4-91c3-481b-bd4b-a438fc32b468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703047941 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.703047941
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.361507647
Short name T141
Test name
Test status
Simulation time 19954706 ps
CPU time 0.98 seconds
Started Jul 19 04:47:09 PM PDT 24
Finished Jul 19 04:47:22 PM PDT 24
Peak memory 209504 kb
Host smart-0edfa105-26e4-4d2b-b88e-d6c2abaa0bee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361507647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.361507647
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3010820792
Short name T868
Test name
Test status
Simulation time 47330669 ps
CPU time 1.26 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:16 PM PDT 24
Peak memory 208136 kb
Host smart-55559731-174d-4005-a933-2a0c4965c591
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010820792 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3010820792
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3104560282
Short name T969
Test name
Test status
Simulation time 478099193 ps
CPU time 4.75 seconds
Started Jul 19 04:47:08 PM PDT 24
Finished Jul 19 04:47:25 PM PDT 24
Peak memory 208680 kb
Host smart-42d43c38-2fc4-4320-a968-d9153890c83f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104560282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3104560282
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.634789543
Short name T908
Test name
Test status
Simulation time 40747395418 ps
CPU time 54.97 seconds
Started Jul 19 04:47:06 PM PDT 24
Finished Jul 19 04:48:15 PM PDT 24
Peak memory 208636 kb
Host smart-f1db0045-4aa0-4d80-941b-20141b2e0ffd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634789543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.634789543
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.147824281
Short name T909
Test name
Test status
Simulation time 387652484 ps
CPU time 2.22 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 211080 kb
Host smart-381ed1fa-81fc-4d2e-a311-d86b98dc7db1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147824281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.147824281
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.683720054
Short name T957
Test name
Test status
Simulation time 175311701 ps
CPU time 1.76 seconds
Started Jul 19 04:47:10 PM PDT 24
Finished Jul 19 04:47:24 PM PDT 24
Peak memory 209500 kb
Host smart-8b0632e5-5c08-4380-929f-aa45d3996fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683720054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.683720054
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2270953804
Short name T189
Test name
Test status
Simulation time 69525416 ps
CPU time 1.75 seconds
Started Jul 19 04:47:04 PM PDT 24
Finished Jul 19 04:47:19 PM PDT 24
Peak memory 217792 kb
Host smart-dc8bb2bf-0a78-4bfa-8abd-ebe4c2a3728e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270953804 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2270953804
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3573838117
Short name T182
Test name
Test status
Simulation time 127815924 ps
CPU time 1.65 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 211612 kb
Host smart-188fcb8b-4b20-4d22-bfca-3764aa093644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573838117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3573838117
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3165937897
Short name T108
Test name
Test status
Simulation time 168302096 ps
CPU time 3.43 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:22 PM PDT 24
Peak memory 217776 kb
Host smart-bb0f923a-b387-4be5-ac14-f0e62366ca16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165937897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3165937897
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.39537440
Short name T98
Test name
Test status
Simulation time 63475111 ps
CPU time 1.18 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:17 PM PDT 24
Peak memory 217836 kb
Host smart-75737214-9e55-4f53-af65-6cef9b37b9db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537440 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.39537440
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3057821933
Short name T184
Test name
Test status
Simulation time 38960968 ps
CPU time 0.84 seconds
Started Jul 19 04:47:07 PM PDT 24
Finished Jul 19 04:47:20 PM PDT 24
Peak memory 209384 kb
Host smart-0aebfa77-a4e9-46af-bad2-e7add8c366f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057821933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3057821933
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1395695307
Short name T947
Test name
Test status
Simulation time 47855957 ps
CPU time 1.81 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:17 PM PDT 24
Peak memory 209460 kb
Host smart-c35fc921-e09b-48cc-baa4-5654f9686fd7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395695307 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1395695307
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1365006964
Short name T128
Test name
Test status
Simulation time 765696815 ps
CPU time 5.8 seconds
Started Jul 19 04:47:05 PM PDT 24
Finished Jul 19 04:47:24 PM PDT 24
Peak memory 208796 kb
Host smart-87570377-ca05-46df-aa59-5d11819fc5f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365006964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1365006964
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1035892625
Short name T919
Test name
Test status
Simulation time 5086696849 ps
CPU time 29.63 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:45 PM PDT 24
Peak memory 209436 kb
Host smart-3f993253-2d18-432f-8216-42d9edcabf4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035892625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1035892625
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1805935106
Short name T903
Test name
Test status
Simulation time 1026630215 ps
CPU time 1.39 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 210920 kb
Host smart-d4fb3ce3-f82b-4342-88c9-accbd3c2917a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805935106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1805935106
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545354510
Short name T984
Test name
Test status
Simulation time 1053810880 ps
CPU time 2.63 seconds
Started Jul 19 04:47:03 PM PDT 24
Finished Jul 19 04:47:18 PM PDT 24
Peak memory 219456 kb
Host smart-13012000-7de6-4085-899e-96f7163b891e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154535
4510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545354510
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1877411149
Short name T988
Test name
Test status
Simulation time 131645075 ps
CPU time 1.64 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:16 PM PDT 24
Peak memory 209476 kb
Host smart-c819c107-e566-4798-813d-391dbd7515a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877411149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1877411149
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2395509204
Short name T944
Test name
Test status
Simulation time 189281222 ps
CPU time 1.45 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:14 PM PDT 24
Peak memory 209664 kb
Host smart-e40b4d99-e3c3-494a-a23b-af94e5a48247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395509204 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2395509204
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3288438898
Short name T954
Test name
Test status
Simulation time 57551917 ps
CPU time 1.39 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:16 PM PDT 24
Peak memory 209556 kb
Host smart-31c6dbd7-dcd0-4d44-8981-11590d96b02a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288438898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3288438898
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.162589598
Short name T114
Test name
Test status
Simulation time 195628362 ps
CPU time 1.74 seconds
Started Jul 19 04:47:02 PM PDT 24
Finished Jul 19 04:47:15 PM PDT 24
Peak memory 218460 kb
Host smart-34468983-0933-4d66-b38d-73f072d140a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162589598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.162589598
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1603111034
Short name T767
Test name
Test status
Simulation time 83040466 ps
CPU time 1.24 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:42:42 PM PDT 24
Peak memory 209144 kb
Host smart-e8d97fd2-4414-4fff-b26e-2de5ce246069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603111034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1603111034
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.435123663
Short name T627
Test name
Test status
Simulation time 601200778 ps
CPU time 14.77 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:42:58 PM PDT 24
Peak memory 218424 kb
Host smart-b892c366-a092-4052-b0ca-ed0db92de1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435123663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.435123663
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1534781141
Short name T786
Test name
Test status
Simulation time 429120108 ps
CPU time 5.2 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:42:46 PM PDT 24
Peak memory 217484 kb
Host smart-7dbb965e-9fda-46b2-8e17-f51e46fc67d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534781141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1534781141
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3099643235
Short name T394
Test name
Test status
Simulation time 857765232 ps
CPU time 8.56 seconds
Started Jul 19 05:42:40 PM PDT 24
Finished Jul 19 05:42:50 PM PDT 24
Peak memory 217672 kb
Host smart-e1ea7807-2615-40d9-a4fc-2a92c235639e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099643235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
099643235
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1077661983
Short name T396
Test name
Test status
Simulation time 3664423463 ps
CPU time 26.76 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:43:07 PM PDT 24
Peak memory 226020 kb
Host smart-dc2d0f49-09c5-46bc-a315-49bfea1a487e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077661983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1077661983
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3321182421
Short name T741
Test name
Test status
Simulation time 1348236953 ps
CPU time 21.04 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:43:01 PM PDT 24
Peak memory 217660 kb
Host smart-ef10fc1f-aee4-470f-aa5c-be6652658a28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321182421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3321182421
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1867207436
Short name T291
Test name
Test status
Simulation time 1782944955 ps
CPU time 14.18 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:42:54 PM PDT 24
Peak memory 217704 kb
Host smart-a11f8d8f-7680-409d-a01e-780744d7b84d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867207436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1867207436
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1236409182
Short name T706
Test name
Test status
Simulation time 4710267470 ps
CPU time 84.81 seconds
Started Jul 19 05:42:41 PM PDT 24
Finished Jul 19 05:44:08 PM PDT 24
Peak memory 278532 kb
Host smart-1b94331b-7cbc-4e3d-9078-4eb9bbb8fe8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236409182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1236409182
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2837448873
Short name T468
Test name
Test status
Simulation time 341708126 ps
CPU time 15.34 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:42:59 PM PDT 24
Peak memory 247584 kb
Host smart-e6aaee0f-aafc-4eff-8ed1-af727ea9bc10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837448873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2837448873
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1004373231
Short name T824
Test name
Test status
Simulation time 450501864 ps
CPU time 4.18 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:42:48 PM PDT 24
Peak memory 218352 kb
Host smart-17b119cf-30d6-4b95-80f6-22753d6e1aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004373231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1004373231
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1097427391
Short name T530
Test name
Test status
Simulation time 2125568086 ps
CPU time 20.13 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:43:00 PM PDT 24
Peak memory 217748 kb
Host smart-395d63fb-687d-43be-a476-4c2382b6385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097427391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1097427391
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2388891372
Short name T649
Test name
Test status
Simulation time 2132036445 ps
CPU time 11.36 seconds
Started Jul 19 05:42:40 PM PDT 24
Finished Jul 19 05:42:53 PM PDT 24
Peak memory 226160 kb
Host smart-b3ed6934-7f47-4eda-9e11-2b41831a0d9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388891372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2388891372
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2997745163
Short name T655
Test name
Test status
Simulation time 1278956790 ps
CPU time 11.07 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:42:51 PM PDT 24
Peak memory 226120 kb
Host smart-b7b2d108-6693-43d2-860a-04ef6108529c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997745163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2997745163
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3113628120
Short name T13
Test name
Test status
Simulation time 395425577 ps
CPU time 5.69 seconds
Started Jul 19 05:42:40 PM PDT 24
Finished Jul 19 05:42:46 PM PDT 24
Peak memory 218320 kb
Host smart-0b672aac-bd6b-4b16-bb79-8739488a40df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113628120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
113628120
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.543295226
Short name T524
Test name
Test status
Simulation time 55450567 ps
CPU time 2.83 seconds
Started Jul 19 05:42:40 PM PDT 24
Finished Jul 19 05:42:44 PM PDT 24
Peak memory 217768 kb
Host smart-fe49cb67-3cbf-40da-a765-20ebe2850176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543295226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.543295226
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3459909857
Short name T242
Test name
Test status
Simulation time 291456152 ps
CPU time 24.79 seconds
Started Jul 19 05:42:40 PM PDT 24
Finished Jul 19 05:43:06 PM PDT 24
Peak memory 251196 kb
Host smart-ad30c6f0-ed5d-4d2e-b229-62ff63c3b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459909857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3459909857
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1584473440
Short name T406
Test name
Test status
Simulation time 176928865 ps
CPU time 10.24 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:42:54 PM PDT 24
Peak memory 251076 kb
Host smart-6943a85b-d519-4993-bd1f-be595df4e554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584473440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1584473440
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1625207027
Short name T472
Test name
Test status
Simulation time 4399147365 ps
CPU time 164.96 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:45:28 PM PDT 24
Peak memory 277172 kb
Host smart-a7caaede-ed3e-4376-b470-fc956faf90fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625207027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1625207027
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.484210513
Short name T862
Test name
Test status
Simulation time 83189006953 ps
CPU time 592.1 seconds
Started Jul 19 05:42:40 PM PDT 24
Finished Jul 19 05:52:33 PM PDT 24
Peak memory 333236 kb
Host smart-da8ecbf6-8ba6-4549-95a8-b93a7751ca22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=484210513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.484210513
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3581139007
Short name T785
Test name
Test status
Simulation time 43805909 ps
CPU time 0.98 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:42:44 PM PDT 24
Peak memory 211984 kb
Host smart-8c270e32-d036-4e8e-bd96-a5c5d9bc9fbd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581139007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3581139007
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1808882407
Short name T828
Test name
Test status
Simulation time 13918026 ps
CPU time 1.04 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:42:51 PM PDT 24
Peak memory 208956 kb
Host smart-00cdd76b-857f-4b0b-aca6-5839dd49253c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808882407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1808882407
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2332904383
Short name T526
Test name
Test status
Simulation time 471687597 ps
CPU time 10.29 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:42:53 PM PDT 24
Peak memory 226140 kb
Host smart-e7cdbb62-d1df-4b06-8dc5-5fa2ea0398aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332904383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2332904383
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.4194424031
Short name T30
Test name
Test status
Simulation time 1574834899 ps
CPU time 10.68 seconds
Started Jul 19 05:42:46 PM PDT 24
Finished Jul 19 05:42:58 PM PDT 24
Peak memory 217404 kb
Host smart-2d1bad0e-3396-4fc5-9803-467f8f586831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194424031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.4194424031
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1597550714
Short name T467
Test name
Test status
Simulation time 1612691460 ps
CPU time 30.81 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:43:21 PM PDT 24
Peak memory 218352 kb
Host smart-09d979e6-e6e3-4b25-8080-ed7ac51ab11b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597550714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1597550714
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.233971133
Short name T439
Test name
Test status
Simulation time 1431549536 ps
CPU time 5.32 seconds
Started Jul 19 05:42:48 PM PDT 24
Finished Jul 19 05:42:55 PM PDT 24
Peak memory 217740 kb
Host smart-08bc13a1-8d7b-46e4-b2bb-613039366eb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233971133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.233971133
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.615203216
Short name T223
Test name
Test status
Simulation time 193112544 ps
CPU time 6.39 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:42:57 PM PDT 24
Peak memory 218368 kb
Host smart-67fac9d2-e910-45ae-8ff9-9a1c2e037bf3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615203216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.615203216
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3133466262
Short name T561
Test name
Test status
Simulation time 410778617 ps
CPU time 6.98 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:42:57 PM PDT 24
Peak memory 217728 kb
Host smart-98da9adc-b0d6-4961-a15f-ff6c7958ced5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133466262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3133466262
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.722904170
Short name T49
Test name
Test status
Simulation time 696771909 ps
CPU time 5.97 seconds
Started Jul 19 05:42:46 PM PDT 24
Finished Jul 19 05:42:52 PM PDT 24
Peak memory 217720 kb
Host smart-81de8ef3-1cdf-499e-b53c-30a9a0b29660
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722904170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.722904170
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.520438549
Short name T536
Test name
Test status
Simulation time 936939722 ps
CPU time 30.76 seconds
Started Jul 19 05:42:47 PM PDT 24
Finished Jul 19 05:43:18 PM PDT 24
Peak memory 251128 kb
Host smart-6a4e0f50-c80a-4fcd-afe5-8eee80da5516
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520438549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.520438549
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3973315485
Short name T83
Test name
Test status
Simulation time 3621181882 ps
CPU time 20.49 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:43:11 PM PDT 24
Peak memory 223836 kb
Host smart-e0f7982f-7ec2-4473-b851-b9418a38dbe6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973315485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3973315485
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.576701478
Short name T848
Test name
Test status
Simulation time 95329204 ps
CPU time 2.41 seconds
Started Jul 19 05:42:41 PM PDT 24
Finished Jul 19 05:42:45 PM PDT 24
Peak memory 218360 kb
Host smart-c3c9d577-8756-4418-a9d6-91bb6035c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576701478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.576701478
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2671807941
Short name T63
Test name
Test status
Simulation time 338172070 ps
CPU time 19.28 seconds
Started Jul 19 05:42:40 PM PDT 24
Finished Jul 19 05:43:00 PM PDT 24
Peak memory 217780 kb
Host smart-5f4d2adc-ea74-444c-a605-53597208a7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671807941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2671807941
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4276665073
Short name T75
Test name
Test status
Simulation time 787448806 ps
CPU time 26.25 seconds
Started Jul 19 05:42:48 PM PDT 24
Finished Jul 19 05:43:16 PM PDT 24
Peak memory 284596 kb
Host smart-9b828fc9-81df-47e4-8736-f68f8dd62bc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276665073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4276665073
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1453189692
Short name T770
Test name
Test status
Simulation time 337146615 ps
CPU time 10.42 seconds
Started Jul 19 05:42:51 PM PDT 24
Finished Jul 19 05:43:02 PM PDT 24
Peak memory 226132 kb
Host smart-177b44d9-b9d1-4008-b372-fd99858f57ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453189692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1453189692
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1046481437
Short name T858
Test name
Test status
Simulation time 382881624 ps
CPU time 12.54 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:43:03 PM PDT 24
Peak memory 225928 kb
Host smart-6be77a05-fb89-4e36-b499-37e888cf0d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046481437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1046481437
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3273981824
Short name T220
Test name
Test status
Simulation time 590287273 ps
CPU time 10.98 seconds
Started Jul 19 05:42:51 PM PDT 24
Finished Jul 19 05:43:03 PM PDT 24
Peak memory 218276 kb
Host smart-1ec010e0-01a7-40e1-b443-cf584c9f8e5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273981824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
273981824
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.856335078
Short name T42
Test name
Test status
Simulation time 1145917605 ps
CPU time 11.46 seconds
Started Jul 19 05:42:41 PM PDT 24
Finished Jul 19 05:42:54 PM PDT 24
Peak memory 225676 kb
Host smart-74defc41-189d-42eb-997a-7bb9bf499b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856335078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.856335078
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3936821104
Short name T231
Test name
Test status
Simulation time 237160723 ps
CPU time 1.19 seconds
Started Jul 19 05:42:39 PM PDT 24
Finished Jul 19 05:42:41 PM PDT 24
Peak memory 217808 kb
Host smart-d6c97907-d0ad-4610-98d6-f4a12b006274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936821104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3936821104
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3531535587
Short name T855
Test name
Test status
Simulation time 207244756 ps
CPU time 27.73 seconds
Started Jul 19 05:42:42 PM PDT 24
Finished Jul 19 05:43:11 PM PDT 24
Peak memory 246552 kb
Host smart-d331371a-a48f-4712-8edd-a20842dec557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531535587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3531535587
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.898522453
Short name T376
Test name
Test status
Simulation time 238724218 ps
CPU time 2.78 seconds
Started Jul 19 05:42:41 PM PDT 24
Finished Jul 19 05:42:45 PM PDT 24
Peak memory 226544 kb
Host smart-286f684d-86cc-43f4-828b-1722a4fc47e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898522453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.898522453
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2757047240
Short name T476
Test name
Test status
Simulation time 21132590082 ps
CPU time 192.95 seconds
Started Jul 19 05:42:46 PM PDT 24
Finished Jul 19 05:46:00 PM PDT 24
Peak memory 422148 kb
Host smart-e821adbd-ed5c-46b3-9d61-112b1dd1ffc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757047240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2757047240
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2277325308
Short name T71
Test name
Test status
Simulation time 50883875036 ps
CPU time 272.67 seconds
Started Jul 19 05:42:46 PM PDT 24
Finished Jul 19 05:47:20 PM PDT 24
Peak memory 278748 kb
Host smart-5c96260c-fdb5-4767-b7fe-291f66cfd6c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2277325308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2277325308
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1093239383
Short name T311
Test name
Test status
Simulation time 17080737 ps
CPU time 1.12 seconds
Started Jul 19 05:42:41 PM PDT 24
Finished Jul 19 05:42:43 PM PDT 24
Peak memory 217960 kb
Host smart-05491e88-fe0b-4df5-9bcd-84e9d41b5b6a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093239383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1093239383
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1690199205
Short name T691
Test name
Test status
Simulation time 30862538 ps
CPU time 1.06 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:43:49 PM PDT 24
Peak memory 209016 kb
Host smart-3dbc9e9a-d527-4cf6-a83b-0a01a6d94c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690199205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1690199205
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2727100035
Short name T650
Test name
Test status
Simulation time 1383015805 ps
CPU time 15.77 seconds
Started Jul 19 05:43:40 PM PDT 24
Finished Jul 19 05:43:58 PM PDT 24
Peak memory 218372 kb
Host smart-5acd194f-252f-49fc-b87c-65089521659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727100035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2727100035
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1118764060
Short name T32
Test name
Test status
Simulation time 1593785287 ps
CPU time 11.53 seconds
Started Jul 19 05:43:46 PM PDT 24
Finished Jul 19 05:44:00 PM PDT 24
Peak memory 217364 kb
Host smart-19e8b5a5-69af-433f-9551-a97767479161
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118764060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1118764060
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2693174759
Short name T209
Test name
Test status
Simulation time 4773322460 ps
CPU time 23.54 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:44:05 PM PDT 24
Peak memory 218488 kb
Host smart-78b50f3d-2dd6-4beb-8935-daaabef216b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693174759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2693174759
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2660750054
Short name T790
Test name
Test status
Simulation time 1227689046 ps
CPU time 17.63 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:58 PM PDT 24
Peak memory 218444 kb
Host smart-dc603a24-c12b-40ee-a6e2-40d6f0b13170
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660750054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2660750054
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2393860545
Short name T266
Test name
Test status
Simulation time 505345445 ps
CPU time 8.07 seconds
Started Jul 19 05:43:36 PM PDT 24
Finished Jul 19 05:43:46 PM PDT 24
Peak memory 217692 kb
Host smart-eb5cfe81-7bf8-491d-8a1d-f13a1c25c334
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393860545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2393860545
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2445530107
Short name T669
Test name
Test status
Simulation time 5337062526 ps
CPU time 59.58 seconds
Started Jul 19 05:43:36 PM PDT 24
Finished Jul 19 05:44:37 PM PDT 24
Peak memory 267540 kb
Host smart-bf4f09ee-0fb3-4a88-83f1-885959725dbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445530107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2445530107
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2665777605
Short name T385
Test name
Test status
Simulation time 1616178976 ps
CPU time 23.4 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:44:04 PM PDT 24
Peak memory 250128 kb
Host smart-9dbba0a3-28a5-442a-a17a-07933bdc5978
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665777605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2665777605
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1998582756
Short name T292
Test name
Test status
Simulation time 167044806 ps
CPU time 2.19 seconds
Started Jul 19 05:43:37 PM PDT 24
Finished Jul 19 05:43:42 PM PDT 24
Peak memory 218312 kb
Host smart-cde54e72-d759-4658-a685-ba49b04dcc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998582756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1998582756
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1475400729
Short name T84
Test name
Test status
Simulation time 184031276 ps
CPU time 8.61 seconds
Started Jul 19 05:43:43 PM PDT 24
Finished Jul 19 05:43:55 PM PDT 24
Peak memory 226180 kb
Host smart-3b5822c2-8eb9-4e44-b847-dcfe1f86857e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475400729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1475400729
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.154040504
Short name T357
Test name
Test status
Simulation time 1376718270 ps
CPU time 7.71 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:43:56 PM PDT 24
Peak memory 218424 kb
Host smart-97c2b362-5fb0-44c3-ab12-e0fd4479585e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154040504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.154040504
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1489676457
Short name T246
Test name
Test status
Simulation time 545521351 ps
CPU time 11.96 seconds
Started Jul 19 05:43:37 PM PDT 24
Finished Jul 19 05:43:51 PM PDT 24
Peak memory 225692 kb
Host smart-8c8129c6-5f91-4d36-9d3e-21a4744cd0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489676457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1489676457
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1388961793
Short name T298
Test name
Test status
Simulation time 79555909 ps
CPU time 2.72 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 217660 kb
Host smart-85e3284a-0c7c-4911-b699-6a77a6ec955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388961793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1388961793
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2211421929
Short name T347
Test name
Test status
Simulation time 265676573 ps
CPU time 17.12 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:57 PM PDT 24
Peak memory 251112 kb
Host smart-f9500534-5053-4ed1-a491-8199cc9bab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211421929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2211421929
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.597071543
Short name T695
Test name
Test status
Simulation time 624775403 ps
CPU time 6.88 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:48 PM PDT 24
Peak memory 250788 kb
Host smart-5afcd8a2-51b2-49c9-957c-aefbf2eddb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597071543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.597071543
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.695127392
Short name T312
Test name
Test status
Simulation time 10923027979 ps
CPU time 119.09 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:45:46 PM PDT 24
Peak memory 259332 kb
Host smart-49ce79ef-4a6c-4698-88c5-fdca22be8260
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695127392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.695127392
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2408770878
Short name T732
Test name
Test status
Simulation time 192989660 ps
CPU time 0.85 seconds
Started Jul 19 05:43:40 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 211952 kb
Host smart-5df4c4a5-208c-43ff-99a3-3c0b14518a71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408770878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2408770878
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.829606986
Short name T829
Test name
Test status
Simulation time 92965944 ps
CPU time 1.02 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:43:48 PM PDT 24
Peak memory 209000 kb
Host smart-59d20a59-5daa-4963-ba5a-b5650955aa14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829606986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.829606986
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3114422136
Short name T594
Test name
Test status
Simulation time 521026441 ps
CPU time 15.49 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:44:03 PM PDT 24
Peak memory 218304 kb
Host smart-16713cf0-ede1-4879-a47e-fc79f0c0b03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114422136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3114422136
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1579575393
Short name T653
Test name
Test status
Simulation time 621568697 ps
CPU time 9.13 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:43:57 PM PDT 24
Peak memory 217220 kb
Host smart-5c6a20a3-d0e4-4f93-8c8a-5656ff7f2829
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579575393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1579575393
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1890162747
Short name T289
Test name
Test status
Simulation time 1603203477 ps
CPU time 51.46 seconds
Started Jul 19 05:43:45 PM PDT 24
Finished Jul 19 05:44:40 PM PDT 24
Peak memory 219004 kb
Host smart-4a0307ec-376e-4eac-bffe-76485a265260
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890162747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1890162747
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.154406590
Short name T363
Test name
Test status
Simulation time 787006276 ps
CPU time 6.96 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:43:54 PM PDT 24
Peak memory 223084 kb
Host smart-6b33847b-14e2-429a-b3ec-b02a444ddc07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154406590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.154406590
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.864322894
Short name T725
Test name
Test status
Simulation time 1463595214 ps
CPU time 4.61 seconds
Started Jul 19 05:43:46 PM PDT 24
Finished Jul 19 05:43:53 PM PDT 24
Peak memory 217696 kb
Host smart-db99616c-d252-46f3-a322-90104dd91fc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864322894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
864322894
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.501002869
Short name T296
Test name
Test status
Simulation time 7126414090 ps
CPU time 45.56 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:44:33 PM PDT 24
Peak memory 277716 kb
Host smart-fcdfc9ce-0be5-4fce-a40c-123328191a7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501002869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.501002869
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1609483014
Short name T494
Test name
Test status
Simulation time 788717593 ps
CPU time 16.95 seconds
Started Jul 19 05:43:42 PM PDT 24
Finished Jul 19 05:44:01 PM PDT 24
Peak memory 250764 kb
Host smart-7f751abe-16a1-4091-84d1-9b2e2fbf9793
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609483014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1609483014
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3651467131
Short name T303
Test name
Test status
Simulation time 367011451 ps
CPU time 3.36 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:43:51 PM PDT 24
Peak memory 218368 kb
Host smart-3314783d-fafe-4958-b20f-2c00c289899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651467131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3651467131
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.97281403
Short name T264
Test name
Test status
Simulation time 957268906 ps
CPU time 21.66 seconds
Started Jul 19 05:43:42 PM PDT 24
Finished Jul 19 05:44:06 PM PDT 24
Peak memory 218416 kb
Host smart-5c1239da-8605-4600-9087-4ca8c81b5f2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97281403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.97281403
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.583762992
Short name T843
Test name
Test status
Simulation time 463655719 ps
CPU time 7.38 seconds
Started Jul 19 05:43:45 PM PDT 24
Finished Jul 19 05:43:55 PM PDT 24
Peak memory 226076 kb
Host smart-ae28bd02-cdf7-44db-9a45-29e0a553dfa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583762992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.583762992
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1645506172
Short name T501
Test name
Test status
Simulation time 423696831 ps
CPU time 6.73 seconds
Started Jul 19 05:43:43 PM PDT 24
Finished Jul 19 05:43:53 PM PDT 24
Peak memory 218312 kb
Host smart-19190a44-71e8-4bcd-ba5e-0c7baff7d998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645506172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1645506172
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.229993473
Short name T147
Test name
Test status
Simulation time 279905552 ps
CPU time 8.52 seconds
Started Jul 19 05:43:43 PM PDT 24
Finished Jul 19 05:43:55 PM PDT 24
Peak memory 226168 kb
Host smart-0299cca4-16fb-4ac7-a505-9141b77a0d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229993473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.229993473
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2483141055
Short name T745
Test name
Test status
Simulation time 81674811 ps
CPU time 3.19 seconds
Started Jul 19 05:43:42 PM PDT 24
Finished Jul 19 05:43:48 PM PDT 24
Peak memory 214948 kb
Host smart-7d29be77-f86a-4e37-a697-35e4cfa6b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483141055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2483141055
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2614458512
Short name T712
Test name
Test status
Simulation time 651603489 ps
CPU time 16.17 seconds
Started Jul 19 05:43:45 PM PDT 24
Finished Jul 19 05:44:04 PM PDT 24
Peak memory 251080 kb
Host smart-3b3e80c4-bb86-45af-8f2f-5e58e19a46bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614458512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2614458512
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3073256653
Short name T202
Test name
Test status
Simulation time 158463230 ps
CPU time 6.26 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:43:53 PM PDT 24
Peak memory 250504 kb
Host smart-39ceac0f-ffca-4410-ba3d-dda21c33ad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073256653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3073256653
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2090705486
Short name T316
Test name
Test status
Simulation time 52535639504 ps
CPU time 240.32 seconds
Started Jul 19 05:43:45 PM PDT 24
Finished Jul 19 05:47:48 PM PDT 24
Peak memory 252884 kb
Host smart-6b904809-c09c-4789-97bc-266738f77e36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090705486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2090705486
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.806711017
Short name T17
Test name
Test status
Simulation time 15529710 ps
CPU time 0.91 seconds
Started Jul 19 05:43:43 PM PDT 24
Finished Jul 19 05:43:48 PM PDT 24
Peak memory 217792 kb
Host smart-a3d4619e-ba48-49ac-9d7f-92529daf846f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806711017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.806711017
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.391051033
Short name T225
Test name
Test status
Simulation time 20936494 ps
CPU time 1.26 seconds
Started Jul 19 05:43:52 PM PDT 24
Finished Jul 19 05:43:56 PM PDT 24
Peak memory 209104 kb
Host smart-40c3b5f0-ba09-4a40-814b-aa0629270807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391051033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.391051033
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1932639463
Short name T608
Test name
Test status
Simulation time 837290849 ps
CPU time 11.56 seconds
Started Jul 19 05:43:51 PM PDT 24
Finished Jul 19 05:44:05 PM PDT 24
Peak memory 218372 kb
Host smart-f1e7830b-aeb2-4dea-abf0-30d14865d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932639463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1932639463
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2986167600
Short name T665
Test name
Test status
Simulation time 58712023 ps
CPU time 1.5 seconds
Started Jul 19 05:43:52 PM PDT 24
Finished Jul 19 05:43:56 PM PDT 24
Peak memory 217112 kb
Host smart-7a7a90d8-d925-4efa-92ec-3e4ab7f21462
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986167600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2986167600
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4266945169
Short name T418
Test name
Test status
Simulation time 2355665552 ps
CPU time 23.37 seconds
Started Jul 19 05:43:51 PM PDT 24
Finished Jul 19 05:44:17 PM PDT 24
Peak memory 219156 kb
Host smart-fc8673b3-a269-4a89-b7c8-6d702816c843
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266945169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4266945169
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1001493633
Short name T559
Test name
Test status
Simulation time 540283889 ps
CPU time 9.62 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:44:02 PM PDT 24
Peak memory 218288 kb
Host smart-687d85bf-2a1d-4be6-b90b-497da23f3698
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001493633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1001493633
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1600731946
Short name T64
Test name
Test status
Simulation time 1005231120 ps
CPU time 13.17 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:44:05 PM PDT 24
Peak memory 217704 kb
Host smart-a124f9e3-e0b1-4511-bc12-a46ae9e8676d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600731946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1600731946
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.29214747
Short name T761
Test name
Test status
Simulation time 3635468358 ps
CPU time 43.01 seconds
Started Jul 19 05:43:51 PM PDT 24
Finished Jul 19 05:44:37 PM PDT 24
Peak memory 268632 kb
Host smart-0d6a716a-3419-48f7-8c69-568afdd915b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29214747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_state_failure.29214747
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2160455194
Short name T425
Test name
Test status
Simulation time 3254992122 ps
CPU time 23.32 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:44:16 PM PDT 24
Peak memory 249612 kb
Host smart-8175af15-4981-478c-963e-abb5642c5993
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160455194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2160455194
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.111897298
Short name T300
Test name
Test status
Simulation time 426774179 ps
CPU time 4.55 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:43:56 PM PDT 24
Peak memory 218368 kb
Host smart-66d85193-82c4-42ab-8a07-f177b5fea926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111897298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.111897298
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.4051002617
Short name T413
Test name
Test status
Simulation time 1374207103 ps
CPU time 15.12 seconds
Started Jul 19 05:43:52 PM PDT 24
Finished Jul 19 05:44:10 PM PDT 24
Peak memory 226164 kb
Host smart-175cf40b-0150-48c0-a7c1-92688b61421e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051002617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.4051002617
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2904428437
Short name T842
Test name
Test status
Simulation time 263852211 ps
CPU time 11.1 seconds
Started Jul 19 05:43:53 PM PDT 24
Finished Jul 19 05:44:06 PM PDT 24
Peak memory 226076 kb
Host smart-872661a3-4f15-4c00-a340-e1f36e7897c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904428437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2904428437
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3965993541
Short name T90
Test name
Test status
Simulation time 329544064 ps
CPU time 7.94 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:44:01 PM PDT 24
Peak memory 226068 kb
Host smart-590ec2ab-95ca-4104-80e9-32e5f7523b49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965993541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3965993541
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1023227156
Short name T513
Test name
Test status
Simulation time 1215115160 ps
CPU time 13.09 seconds
Started Jul 19 05:43:51 PM PDT 24
Finished Jul 19 05:44:07 PM PDT 24
Peak memory 218436 kb
Host smart-5fc64aea-5524-42fe-ba21-f143b0f8e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023227156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1023227156
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2116848168
Short name T326
Test name
Test status
Simulation time 333589204 ps
CPU time 4.48 seconds
Started Jul 19 05:43:43 PM PDT 24
Finished Jul 19 05:43:51 PM PDT 24
Peak memory 217788 kb
Host smart-63da2211-96ff-4714-8784-b326867f2110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116848168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2116848168
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1197601498
Short name T500
Test name
Test status
Simulation time 802588633 ps
CPU time 26.89 seconds
Started Jul 19 05:43:44 PM PDT 24
Finished Jul 19 05:44:15 PM PDT 24
Peak memory 251236 kb
Host smart-f27bce66-359e-4778-9187-3fad1a3820a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197601498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1197601498
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3620866833
Short name T822
Test name
Test status
Simulation time 187726612 ps
CPU time 6.03 seconds
Started Jul 19 05:43:43 PM PDT 24
Finished Jul 19 05:43:53 PM PDT 24
Peak memory 250628 kb
Host smart-775f0127-101c-452f-bc45-427d509668ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620866833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3620866833
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.897861346
Short name T531
Test name
Test status
Simulation time 1606723644 ps
CPU time 52.86 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:44:45 PM PDT 24
Peak memory 250728 kb
Host smart-573034d8-5a45-4f88-988b-4d61de901803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897861346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.897861346
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1942307082
Short name T772
Test name
Test status
Simulation time 41150494 ps
CPU time 0.88 seconds
Started Jul 19 05:43:42 PM PDT 24
Finished Jul 19 05:43:46 PM PDT 24
Peak memory 211932 kb
Host smart-d0549693-fd9c-4175-83a3-b0a9daea0a84
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942307082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1942307082
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3953258037
Short name T335
Test name
Test status
Simulation time 19395277 ps
CPU time 1.11 seconds
Started Jul 19 05:43:55 PM PDT 24
Finished Jul 19 05:43:59 PM PDT 24
Peak memory 209040 kb
Host smart-5a92d981-71d2-452e-aa71-4e276820e316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953258037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3953258037
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.910901237
Short name T336
Test name
Test status
Simulation time 261869567 ps
CPU time 9.28 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:44:01 PM PDT 24
Peak memory 218260 kb
Host smart-16547104-9a61-443f-81ae-42c29cef3bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910901237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.910901237
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3647491016
Short name T29
Test name
Test status
Simulation time 437382587 ps
CPU time 2.46 seconds
Started Jul 19 05:43:52 PM PDT 24
Finished Jul 19 05:43:57 PM PDT 24
Peak memory 217228 kb
Host smart-fa776a8e-7ebe-464c-b1a2-e109c1f1f920
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647491016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3647491016
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1118405468
Short name T549
Test name
Test status
Simulation time 1766174943 ps
CPU time 49.39 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:44:43 PM PDT 24
Peak memory 218308 kb
Host smart-f37c0cdb-2d47-4dcb-a759-ee70ba066784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118405468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1118405468
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1965024959
Short name T835
Test name
Test status
Simulation time 659294897 ps
CPU time 5.08 seconds
Started Jul 19 05:43:49 PM PDT 24
Finished Jul 19 05:43:56 PM PDT 24
Peak memory 221880 kb
Host smart-c5459117-c750-4333-add8-9d1749371611
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965024959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1965024959
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2785034891
Short name T55
Test name
Test status
Simulation time 263401060 ps
CPU time 3.69 seconds
Started Jul 19 05:43:54 PM PDT 24
Finished Jul 19 05:44:00 PM PDT 24
Peak memory 217704 kb
Host smart-8142743b-8633-40bd-ae05-ec4ea2bb5a34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785034891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2785034891
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.814997107
Short name T262
Test name
Test status
Simulation time 5571107064 ps
CPU time 39.21 seconds
Started Jul 19 05:43:49 PM PDT 24
Finished Jul 19 05:44:30 PM PDT 24
Peak memory 275880 kb
Host smart-90766941-ccb2-41b1-a62b-f58cb8bc1362
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814997107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.814997107
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1196855908
Short name T850
Test name
Test status
Simulation time 2384268391 ps
CPU time 10.58 seconds
Started Jul 19 05:43:49 PM PDT 24
Finished Jul 19 05:44:01 PM PDT 24
Peak memory 224196 kb
Host smart-9ec598af-bba6-4290-8679-2fed7120b7e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196855908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1196855908
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2387129785
Short name T443
Test name
Test status
Simulation time 29756384 ps
CPU time 2.29 seconds
Started Jul 19 05:43:53 PM PDT 24
Finished Jul 19 05:43:57 PM PDT 24
Peak memory 218364 kb
Host smart-78a96893-4e7e-48d2-b829-c535a28ef6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387129785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2387129785
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.627149678
Short name T629
Test name
Test status
Simulation time 585726936 ps
CPU time 12.05 seconds
Started Jul 19 05:43:55 PM PDT 24
Finished Jul 19 05:44:09 PM PDT 24
Peak memory 226116 kb
Host smart-a9f2c156-fcaa-49be-b1d6-d00c7abd50f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627149678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.627149678
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.835585259
Short name T686
Test name
Test status
Simulation time 1112189390 ps
CPU time 12.54 seconds
Started Jul 19 05:43:49 PM PDT 24
Finished Jul 19 05:44:04 PM PDT 24
Peak memory 226164 kb
Host smart-b6f796ab-a9db-4b7e-8507-c84528492a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835585259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.835585259
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2742460781
Short name T779
Test name
Test status
Simulation time 204078200 ps
CPU time 7.96 seconds
Started Jul 19 05:43:51 PM PDT 24
Finished Jul 19 05:44:02 PM PDT 24
Peak memory 226104 kb
Host smart-b1ac48ac-4a7d-4ece-a94c-c36c0b997baf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742460781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2742460781
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1439794162
Short name T585
Test name
Test status
Simulation time 1136253637 ps
CPU time 10.73 seconds
Started Jul 19 05:43:49 PM PDT 24
Finished Jul 19 05:44:01 PM PDT 24
Peak memory 225260 kb
Host smart-d367523c-cbc7-4d51-8833-d0dbc1e4c3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439794162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1439794162
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.381459879
Short name T817
Test name
Test status
Simulation time 57748920 ps
CPU time 3.75 seconds
Started Jul 19 05:43:53 PM PDT 24
Finished Jul 19 05:43:59 PM PDT 24
Peak memory 217912 kb
Host smart-ebea185e-60e8-4de2-a767-96bc82c0e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381459879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.381459879
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2621817452
Short name T578
Test name
Test status
Simulation time 1134478022 ps
CPU time 21.88 seconds
Started Jul 19 05:43:49 PM PDT 24
Finished Jul 19 05:44:12 PM PDT 24
Peak memory 250924 kb
Host smart-50969a02-0dfb-4a10-9a8a-f35045fa9180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621817452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2621817452
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1209192899
Short name T688
Test name
Test status
Simulation time 81697891 ps
CPU time 7.15 seconds
Started Jul 19 05:43:50 PM PDT 24
Finished Jul 19 05:43:59 PM PDT 24
Peak memory 251072 kb
Host smart-237b33d5-7fc6-492d-9385-98e61e6aaed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209192899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1209192899
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3040741521
Short name T314
Test name
Test status
Simulation time 96840999229 ps
CPU time 838.71 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:58:00 PM PDT 24
Peak memory 285936 kb
Host smart-f5aa81f2-8c25-4e54-aac9-bc0b2e2ae493
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040741521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3040741521
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2987413049
Short name T754
Test name
Test status
Simulation time 90151680 ps
CPU time 0.88 seconds
Started Jul 19 05:43:51 PM PDT 24
Finished Jul 19 05:43:54 PM PDT 24
Peak memory 212956 kb
Host smart-8c9e539f-300e-4c7e-b69f-7466e1f29d2e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987413049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2987413049
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.714180177
Short name T604
Test name
Test status
Simulation time 44335827 ps
CPU time 1.2 seconds
Started Jul 19 05:43:54 PM PDT 24
Finished Jul 19 05:43:58 PM PDT 24
Peak memory 209176 kb
Host smart-0edd690d-61e3-436e-8d96-1e8bdd16b74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714180177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.714180177
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2020513877
Short name T618
Test name
Test status
Simulation time 274509063 ps
CPU time 14.47 seconds
Started Jul 19 05:43:56 PM PDT 24
Finished Jul 19 05:44:13 PM PDT 24
Peak memory 226164 kb
Host smart-249e2b9f-04e6-4ee5-bd19-c8b7823df921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020513877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2020513877
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1596027693
Short name T497
Test name
Test status
Simulation time 316694654 ps
CPU time 1.79 seconds
Started Jul 19 05:43:55 PM PDT 24
Finished Jul 19 05:44:00 PM PDT 24
Peak memory 217308 kb
Host smart-84b085c8-9acb-4b80-ae1f-4512ba92d009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596027693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1596027693
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3370074126
Short name T805
Test name
Test status
Simulation time 995476680 ps
CPU time 19.64 seconds
Started Jul 19 05:43:59 PM PDT 24
Finished Jul 19 05:44:22 PM PDT 24
Peak memory 218924 kb
Host smart-fa9414d9-084a-48ef-bc00-59e8e7df1d5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370074126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3370074126
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1715942648
Short name T243
Test name
Test status
Simulation time 2166816972 ps
CPU time 29.37 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:44:30 PM PDT 24
Peak memory 219184 kb
Host smart-fa66c338-df66-4ca0-b29a-63fa5488bb6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715942648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1715942648
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1921004214
Short name T345
Test name
Test status
Simulation time 772299334 ps
CPU time 5.89 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:44:06 PM PDT 24
Peak memory 217700 kb
Host smart-387e219e-ed14-44a0-a498-003b0faf6586
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921004214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1921004214
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3527566656
Short name T452
Test name
Test status
Simulation time 8237004436 ps
CPU time 68.83 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:45:09 PM PDT 24
Peak memory 267488 kb
Host smart-a0ea7ca8-a52a-4551-8f51-a598d8d4a911
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527566656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3527566656
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1802854089
Short name T709
Test name
Test status
Simulation time 716235407 ps
CPU time 13.77 seconds
Started Jul 19 05:43:55 PM PDT 24
Finished Jul 19 05:44:11 PM PDT 24
Peak memory 223304 kb
Host smart-1ac99634-7d85-439f-877a-8f90c9e9e078
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802854089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1802854089
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2639807263
Short name T82
Test name
Test status
Simulation time 25232775 ps
CPU time 1.46 seconds
Started Jul 19 05:43:56 PM PDT 24
Finished Jul 19 05:44:00 PM PDT 24
Peak memory 218360 kb
Host smart-28066912-8ca4-448f-aeb7-5806d0405f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639807263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2639807263
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1995190031
Short name T722
Test name
Test status
Simulation time 1052480288 ps
CPU time 8.62 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:44:08 PM PDT 24
Peak memory 226164 kb
Host smart-edf25bde-b1cf-49b4-99ea-3402ccc90bac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995190031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1995190031
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.288906803
Short name T599
Test name
Test status
Simulation time 1349398890 ps
CPU time 10.66 seconds
Started Jul 19 05:43:58 PM PDT 24
Finished Jul 19 05:44:12 PM PDT 24
Peak memory 226100 kb
Host smart-2408bcc3-f656-44ba-b974-8fd843859982
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288906803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.288906803
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2464645186
Short name T738
Test name
Test status
Simulation time 320849853 ps
CPU time 8.3 seconds
Started Jul 19 05:43:58 PM PDT 24
Finished Jul 19 05:44:09 PM PDT 24
Peak memory 218304 kb
Host smart-131e0791-0c34-48fd-a73b-459ac679367e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464645186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2464645186
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1762174739
Short name T40
Test name
Test status
Simulation time 1042907422 ps
CPU time 10.19 seconds
Started Jul 19 05:43:58 PM PDT 24
Finished Jul 19 05:44:11 PM PDT 24
Peak memory 224908 kb
Host smart-73a23205-d705-41ff-a9c6-1b316ca455e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762174739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1762174739
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1765089563
Short name T390
Test name
Test status
Simulation time 271770269 ps
CPU time 1.89 seconds
Started Jul 19 05:43:59 PM PDT 24
Finished Jul 19 05:44:05 PM PDT 24
Peak memory 217868 kb
Host smart-158977c3-856f-4b1f-a609-c1f228f4c82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765089563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1765089563
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.971986634
Short name T504
Test name
Test status
Simulation time 943595973 ps
CPU time 24.41 seconds
Started Jul 19 05:43:56 PM PDT 24
Finished Jul 19 05:44:23 PM PDT 24
Peak memory 251144 kb
Host smart-7c784d89-f901-4960-b77d-63033ccd995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971986634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.971986634
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.746260552
Short name T713
Test name
Test status
Simulation time 86805087 ps
CPU time 3.27 seconds
Started Jul 19 05:43:55 PM PDT 24
Finished Jul 19 05:44:01 PM PDT 24
Peak memory 222716 kb
Host smart-f9d6e5b6-1d6f-4a2d-9df1-a804da27fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746260552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.746260552
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1432760390
Short name T658
Test name
Test status
Simulation time 1725585407 ps
CPU time 74.7 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:45:15 PM PDT 24
Peak memory 251208 kb
Host smart-61ebce8c-db57-4e2d-9ba0-b9c520f7c35d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432760390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1432760390
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1624473261
Short name T782
Test name
Test status
Simulation time 12149134 ps
CPU time 1.01 seconds
Started Jul 19 05:43:59 PM PDT 24
Finished Jul 19 05:44:03 PM PDT 24
Peak memory 211972 kb
Host smart-a5093e95-4ad6-4824-b7d0-b955ed3c5946
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624473261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1624473261
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2431053719
Short name T746
Test name
Test status
Simulation time 23970722 ps
CPU time 1.19 seconds
Started Jul 19 05:44:06 PM PDT 24
Finished Jul 19 05:44:09 PM PDT 24
Peak memory 209008 kb
Host smart-c636be07-0cf7-4a65-ad5e-1842793155f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431053719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2431053719
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.793810831
Short name T428
Test name
Test status
Simulation time 2837898572 ps
CPU time 19.28 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:44:20 PM PDT 24
Peak memory 226232 kb
Host smart-a6942f75-6df9-4057-bc3d-c3e51844fbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793810831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.793810831
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.311640154
Short name T830
Test name
Test status
Simulation time 425518759 ps
CPU time 5.77 seconds
Started Jul 19 05:44:06 PM PDT 24
Finished Jul 19 05:44:13 PM PDT 24
Peak memory 217432 kb
Host smart-52bfbe43-914d-45c3-87c8-9d306a4523bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311640154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.311640154
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2555145379
Short name T638
Test name
Test status
Simulation time 6414677361 ps
CPU time 41.64 seconds
Started Jul 19 05:44:05 PM PDT 24
Finished Jul 19 05:44:49 PM PDT 24
Peak memory 218676 kb
Host smart-a2328804-3946-4af7-b9b4-9f63f3d58f46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555145379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2555145379
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3763694427
Short name T198
Test name
Test status
Simulation time 523501105 ps
CPU time 7.95 seconds
Started Jul 19 05:44:05 PM PDT 24
Finished Jul 19 05:44:15 PM PDT 24
Peak memory 222920 kb
Host smart-bbce3fc1-c771-4868-a421-892144087f5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763694427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3763694427
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3096792580
Short name T62
Test name
Test status
Simulation time 498297549 ps
CPU time 1.62 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:44:02 PM PDT 24
Peak memory 217720 kb
Host smart-18c15cda-fe2e-48ee-b02f-03d56e3b1b20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096792580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3096792580
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2411543219
Short name T521
Test name
Test status
Simulation time 1308062517 ps
CPU time 31.69 seconds
Started Jul 19 05:43:58 PM PDT 24
Finished Jul 19 05:44:33 PM PDT 24
Peak memory 251044 kb
Host smart-9988cd05-77fe-43cf-9c1d-eeed0fc5b8f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411543219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2411543219
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1307346554
Short name T251
Test name
Test status
Simulation time 448633689 ps
CPU time 18.36 seconds
Started Jul 19 05:43:57 PM PDT 24
Finished Jul 19 05:44:19 PM PDT 24
Peak memory 250600 kb
Host smart-1ab2d604-8969-4062-94f2-96a195f00a39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307346554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1307346554
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1819592181
Short name T383
Test name
Test status
Simulation time 25387016 ps
CPU time 2.13 seconds
Started Jul 19 05:43:58 PM PDT 24
Finished Jul 19 05:44:04 PM PDT 24
Peak memory 218360 kb
Host smart-1f673c54-eac2-4722-819e-6669e3872d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819592181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1819592181
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2306721109
Short name T717
Test name
Test status
Simulation time 2209691580 ps
CPU time 7.76 seconds
Started Jul 19 05:44:08 PM PDT 24
Finished Jul 19 05:44:17 PM PDT 24
Peak memory 226140 kb
Host smart-b8d51e88-e672-4345-9aec-9182b13a7423
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306721109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2306721109
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4138103778
Short name T715
Test name
Test status
Simulation time 936999754 ps
CPU time 9.63 seconds
Started Jul 19 05:44:05 PM PDT 24
Finished Jul 19 05:44:16 PM PDT 24
Peak memory 226104 kb
Host smart-fe32fb0d-af77-417e-84c0-2d09d08a92b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138103778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4138103778
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2785588408
Short name T318
Test name
Test status
Simulation time 76616898 ps
CPU time 3.53 seconds
Started Jul 19 05:43:58 PM PDT 24
Finished Jul 19 05:44:05 PM PDT 24
Peak memory 217820 kb
Host smart-d5f3dbf3-b86c-4987-b1d9-a26faab92df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785588408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2785588408
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1653497073
Short name T555
Test name
Test status
Simulation time 639714285 ps
CPU time 36.13 seconds
Started Jul 19 05:43:56 PM PDT 24
Finished Jul 19 05:44:35 PM PDT 24
Peak memory 251108 kb
Host smart-f22e10c0-6c7b-47e9-aca6-d34a7230b643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653497073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1653497073
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1702147498
Short name T512
Test name
Test status
Simulation time 342115885 ps
CPU time 8.16 seconds
Started Jul 19 05:43:59 PM PDT 24
Finished Jul 19 05:44:11 PM PDT 24
Peak memory 251064 kb
Host smart-2ebb049d-8621-4d13-bb37-183f466e52d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702147498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1702147498
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3990402348
Short name T261
Test name
Test status
Simulation time 4111925289 ps
CPU time 149.14 seconds
Started Jul 19 05:44:07 PM PDT 24
Finished Jul 19 05:46:38 PM PDT 24
Peak memory 267564 kb
Host smart-bb59e0dc-df82-4093-8d55-1519dd8c0090
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990402348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3990402348
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2936027193
Short name T664
Test name
Test status
Simulation time 14085495 ps
CPU time 0.9 seconds
Started Jul 19 05:44:03 PM PDT 24
Finished Jul 19 05:44:06 PM PDT 24
Peak memory 211948 kb
Host smart-d601277c-2ac0-4aeb-a795-ea8abb905a8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936027193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2936027193
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1219429511
Short name T724
Test name
Test status
Simulation time 48079872 ps
CPU time 1.27 seconds
Started Jul 19 05:44:19 PM PDT 24
Finished Jul 19 05:44:23 PM PDT 24
Peak memory 208920 kb
Host smart-482068f9-c59e-4658-a65b-1060a1a29523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219429511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1219429511
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3711577727
Short name T160
Test name
Test status
Simulation time 617011410 ps
CPU time 12.35 seconds
Started Jul 19 05:44:07 PM PDT 24
Finished Jul 19 05:44:20 PM PDT 24
Peak memory 218372 kb
Host smart-6d98b586-7a1b-4ddf-a9f7-a6b6dccdf9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711577727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3711577727
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1749792792
Short name T499
Test name
Test status
Simulation time 325716691 ps
CPU time 2.8 seconds
Started Jul 19 05:44:13 PM PDT 24
Finished Jul 19 05:44:18 PM PDT 24
Peak memory 217356 kb
Host smart-b169ba58-32f5-4b85-8ba1-facf0601a5eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749792792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1749792792
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3589033689
Short name T204
Test name
Test status
Simulation time 1743718582 ps
CPU time 55.58 seconds
Started Jul 19 05:44:12 PM PDT 24
Finished Jul 19 05:45:08 PM PDT 24
Peak memory 218924 kb
Host smart-68f6416c-9d4d-4749-ada4-3135e5cb3b92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589033689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3589033689
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3761081838
Short name T507
Test name
Test status
Simulation time 1318634941 ps
CPU time 11.64 seconds
Started Jul 19 05:44:14 PM PDT 24
Finished Jul 19 05:44:27 PM PDT 24
Peak memory 223256 kb
Host smart-811bd4b9-c892-4418-8ffe-bc695ec30501
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761081838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3761081838
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.4262890810
Short name T826
Test name
Test status
Simulation time 406797533 ps
CPU time 5.63 seconds
Started Jul 19 05:44:04 PM PDT 24
Finished Jul 19 05:44:11 PM PDT 24
Peak memory 217664 kb
Host smart-00821996-e577-4c83-a6ca-318f6937757e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262890810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.4262890810
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2440406440
Short name T569
Test name
Test status
Simulation time 1479468217 ps
CPU time 57.46 seconds
Started Jul 19 05:44:16 PM PDT 24
Finished Jul 19 05:45:15 PM PDT 24
Peak memory 268084 kb
Host smart-6b47924f-e0aa-4452-a16f-2e796c352c75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440406440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2440406440
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1137910288
Short name T667
Test name
Test status
Simulation time 2182349988 ps
CPU time 29.98 seconds
Started Jul 19 05:44:12 PM PDT 24
Finished Jul 19 05:44:43 PM PDT 24
Peak memory 250920 kb
Host smart-33705226-fa7a-4437-b6e1-5f28de7e6342
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137910288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1137910288
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2692468119
Short name T696
Test name
Test status
Simulation time 121830249 ps
CPU time 2.58 seconds
Started Jul 19 05:44:09 PM PDT 24
Finished Jul 19 05:44:12 PM PDT 24
Peak memory 218332 kb
Host smart-09f82631-5408-4594-9338-211a4b06d18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692468119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2692468119
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2536568310
Short name T483
Test name
Test status
Simulation time 1994055866 ps
CPU time 14.68 seconds
Started Jul 19 05:44:11 PM PDT 24
Finished Jul 19 05:44:27 PM PDT 24
Peak memory 226248 kb
Host smart-69fecf6d-30f2-48de-b259-0d5b46e26853
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536568310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2536568310
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.252403267
Short name T327
Test name
Test status
Simulation time 592892748 ps
CPU time 17.37 seconds
Started Jul 19 05:44:13 PM PDT 24
Finished Jul 19 05:44:32 PM PDT 24
Peak memory 226092 kb
Host smart-0d80941d-b9b8-48f2-99eb-881ee06cd5cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252403267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.252403267
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2469715257
Short name T640
Test name
Test status
Simulation time 455027362 ps
CPU time 10.27 seconds
Started Jul 19 05:44:18 PM PDT 24
Finished Jul 19 05:44:30 PM PDT 24
Peak memory 218356 kb
Host smart-24701ddc-de27-4112-94ff-562ba591979d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469715257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2469715257
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.4134904792
Short name T388
Test name
Test status
Simulation time 2860012383 ps
CPU time 12.78 seconds
Started Jul 19 05:44:05 PM PDT 24
Finished Jul 19 05:44:19 PM PDT 24
Peak memory 218384 kb
Host smart-24945ec5-64e3-4de0-a213-fc8c9b236832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134904792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.4134904792
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2246078706
Short name T711
Test name
Test status
Simulation time 310330905 ps
CPU time 2.13 seconds
Started Jul 19 05:44:09 PM PDT 24
Finished Jul 19 05:44:12 PM PDT 24
Peak memory 223588 kb
Host smart-15b94b31-26cb-4631-8714-cb816ba38a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246078706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2246078706
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1782960676
Short name T514
Test name
Test status
Simulation time 242678856 ps
CPU time 29.25 seconds
Started Jul 19 05:44:05 PM PDT 24
Finished Jul 19 05:44:36 PM PDT 24
Peak memory 251108 kb
Host smart-92abc700-7152-4b3c-87c6-6da0b6cc75d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782960676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1782960676
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.978299762
Short name T238
Test name
Test status
Simulation time 74584304 ps
CPU time 8.26 seconds
Started Jul 19 05:44:06 PM PDT 24
Finished Jul 19 05:44:16 PM PDT 24
Peak memory 251116 kb
Host smart-99c688d9-2761-4c65-90c5-c3db49e78225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978299762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.978299762
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.4005036679
Short name T134
Test name
Test status
Simulation time 76196883714 ps
CPU time 574.96 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:53:58 PM PDT 24
Peak memory 422464 kb
Host smart-cca07d17-805a-4860-bc7e-9a9c0c6c33f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4005036679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.4005036679
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.732050489
Short name T377
Test name
Test status
Simulation time 14690978 ps
CPU time 0.86 seconds
Started Jul 19 05:44:04 PM PDT 24
Finished Jul 19 05:44:07 PM PDT 24
Peak memory 211952 kb
Host smart-19e342df-9e45-48db-95ca-fc88afe282ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732050489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.732050489
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3928742864
Short name T236
Test name
Test status
Simulation time 50207049 ps
CPU time 0.98 seconds
Started Jul 19 05:44:15 PM PDT 24
Finished Jul 19 05:44:17 PM PDT 24
Peak memory 209004 kb
Host smart-04835258-7b87-458c-a14d-391a1014e149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928742864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3928742864
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1789481309
Short name T552
Test name
Test status
Simulation time 1151094728 ps
CPU time 14.89 seconds
Started Jul 19 05:44:14 PM PDT 24
Finished Jul 19 05:44:31 PM PDT 24
Peak memory 226164 kb
Host smart-321d54c5-07e5-4c1f-964c-32a2fa08a926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789481309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1789481309
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3648357581
Short name T788
Test name
Test status
Simulation time 2193838757 ps
CPU time 5.95 seconds
Started Jul 19 05:44:15 PM PDT 24
Finished Jul 19 05:44:23 PM PDT 24
Peak memory 217232 kb
Host smart-c2d422a1-a6b8-4d3d-9742-c7439e568559
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648357581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3648357581
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1771021460
Short name T759
Test name
Test status
Simulation time 9013937155 ps
CPU time 66.17 seconds
Started Jul 19 05:44:19 PM PDT 24
Finished Jul 19 05:45:28 PM PDT 24
Peak memory 218956 kb
Host smart-2c19ae5a-db14-45d9-a0c2-69ce3a462de4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771021460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1771021460
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4202119839
Short name T577
Test name
Test status
Simulation time 206175224 ps
CPU time 2.87 seconds
Started Jul 19 05:44:15 PM PDT 24
Finished Jul 19 05:44:20 PM PDT 24
Peak memory 218300 kb
Host smart-ff511d0a-b711-4e7b-a7a9-ceaf6a73aa58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202119839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4202119839
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2944004183
Short name T672
Test name
Test status
Simulation time 380964737 ps
CPU time 10.72 seconds
Started Jul 19 05:44:18 PM PDT 24
Finished Jul 19 05:44:30 PM PDT 24
Peak memory 217680 kb
Host smart-52b6f77c-5984-4954-bb74-c5cc8225676f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944004183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2944004183
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2686894004
Short name T278
Test name
Test status
Simulation time 1772279845 ps
CPU time 32.39 seconds
Started Jul 19 05:44:13 PM PDT 24
Finished Jul 19 05:44:47 PM PDT 24
Peak memory 283808 kb
Host smart-e108101d-13c3-4dd5-8531-73c019a07905
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686894004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2686894004
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2788490481
Short name T592
Test name
Test status
Simulation time 618050313 ps
CPU time 18.91 seconds
Started Jul 19 05:44:14 PM PDT 24
Finished Jul 19 05:44:35 PM PDT 24
Peak memory 250408 kb
Host smart-7edfbcb5-1454-443a-91c0-bc2f21e8a47f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788490481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2788490481
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.72739198
Short name T490
Test name
Test status
Simulation time 436364477 ps
CPU time 4.16 seconds
Started Jul 19 05:44:12 PM PDT 24
Finished Jul 19 05:44:18 PM PDT 24
Peak memory 218320 kb
Host smart-2db12bf7-720d-4e4f-8a8e-1e3fb80fbc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72739198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.72739198
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2512130728
Short name T703
Test name
Test status
Simulation time 571879596 ps
CPU time 12.48 seconds
Started Jul 19 05:44:13 PM PDT 24
Finished Jul 19 05:44:27 PM PDT 24
Peak memory 218444 kb
Host smart-d0c26274-ec27-4b74-bc4d-ebfe78269faa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512130728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2512130728
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.414890568
Short name T730
Test name
Test status
Simulation time 309820033 ps
CPU time 10.76 seconds
Started Jul 19 05:44:19 PM PDT 24
Finished Jul 19 05:44:32 PM PDT 24
Peak memory 225992 kb
Host smart-fdcc3f2c-d648-43ae-bbfd-b89b0059ddb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414890568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.414890568
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2201013914
Short name T457
Test name
Test status
Simulation time 1492864679 ps
CPU time 13.11 seconds
Started Jul 19 05:44:14 PM PDT 24
Finished Jul 19 05:44:29 PM PDT 24
Peak memory 218260 kb
Host smart-9799f4b6-cf43-47ef-bb6a-71cba988d868
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201013914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2201013914
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1466444510
Short name T574
Test name
Test status
Simulation time 448812046 ps
CPU time 10.14 seconds
Started Jul 19 05:44:12 PM PDT 24
Finished Jul 19 05:44:24 PM PDT 24
Peak memory 218440 kb
Host smart-7a9bd696-e551-48c1-bd85-6a3a2ca2a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466444510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1466444510
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.833090741
Short name T534
Test name
Test status
Simulation time 62703453 ps
CPU time 1.53 seconds
Started Jul 19 05:44:13 PM PDT 24
Finished Jul 19 05:44:16 PM PDT 24
Peak memory 213932 kb
Host smart-47fb3057-c0c3-430b-9a4c-3a6bb6243a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833090741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.833090741
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1766599139
Short name T582
Test name
Test status
Simulation time 1227538774 ps
CPU time 28.91 seconds
Started Jul 19 05:44:13 PM PDT 24
Finished Jul 19 05:44:43 PM PDT 24
Peak memory 251104 kb
Host smart-2b73a3b3-f25c-4b16-b72c-d4d9600ea273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766599139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1766599139
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3227060187
Short name T227
Test name
Test status
Simulation time 127008262 ps
CPU time 8.31 seconds
Started Jul 19 05:44:15 PM PDT 24
Finished Jul 19 05:44:24 PM PDT 24
Peak memory 251104 kb
Host smart-be3377fb-14a6-4983-84ab-8bee8a82f579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227060187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3227060187
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.319460319
Short name T749
Test name
Test status
Simulation time 36559127449 ps
CPU time 125.71 seconds
Started Jul 19 05:44:15 PM PDT 24
Finished Jul 19 05:46:22 PM PDT 24
Peak memory 251648 kb
Host smart-97971aba-4190-4d9b-b397-e516c4fde8ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319460319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.319460319
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3902457275
Short name T271
Test name
Test status
Simulation time 16227857 ps
CPU time 0.92 seconds
Started Jul 19 05:44:21 PM PDT 24
Finished Jul 19 05:44:25 PM PDT 24
Peak memory 208824 kb
Host smart-f366ba2a-e38c-4b50-a791-639b05775cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902457275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3902457275
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.23100920
Short name T143
Test name
Test status
Simulation time 4450170949 ps
CPU time 13.47 seconds
Started Jul 19 05:44:19 PM PDT 24
Finished Jul 19 05:44:34 PM PDT 24
Peak memory 218404 kb
Host smart-a812ae8a-b33d-461a-a891-b1d84f910254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23100920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.23100920
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3992594919
Short name T747
Test name
Test status
Simulation time 841823562 ps
CPU time 6.07 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:44:28 PM PDT 24
Peak memory 217408 kb
Host smart-eb6e95ad-fea2-48dd-8572-8ab5a6203929
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992594919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3992594919
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2584200045
Short name T833
Test name
Test status
Simulation time 1718540853 ps
CPU time 25.11 seconds
Started Jul 19 05:44:23 PM PDT 24
Finished Jul 19 05:44:51 PM PDT 24
Peak memory 218288 kb
Host smart-38338bf7-4744-4695-a17c-e21f54f367da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584200045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2584200045
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2268740065
Short name T755
Test name
Test status
Simulation time 615391485 ps
CPU time 10.33 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:44:34 PM PDT 24
Peak memory 218296 kb
Host smart-0eecc4a7-9ced-4eb6-9a42-54f9e7e92574
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268740065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2268740065
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3426827297
Short name T518
Test name
Test status
Simulation time 862247238 ps
CPU time 11.63 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:44:35 PM PDT 24
Peak memory 217704 kb
Host smart-1dce2e42-a809-4d1a-893a-6c9164e1bc37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426827297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3426827297
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3618365683
Short name T852
Test name
Test status
Simulation time 5234829908 ps
CPU time 51.03 seconds
Started Jul 19 05:44:23 PM PDT 24
Finished Jul 19 05:45:16 PM PDT 24
Peak memory 268796 kb
Host smart-e2391b72-39f8-413b-b6a4-c4985c87c603
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618365683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3618365683
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1292334560
Short name T389
Test name
Test status
Simulation time 2087547556 ps
CPU time 12.83 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:44:36 PM PDT 24
Peak memory 246768 kb
Host smart-ba596d08-d9fc-4c50-9ff2-2e42aaf2fa66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292334560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1292334560
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3063486851
Short name T447
Test name
Test status
Simulation time 95170374 ps
CPU time 3.97 seconds
Started Jul 19 05:44:21 PM PDT 24
Finished Jul 19 05:44:28 PM PDT 24
Peak memory 218312 kb
Host smart-3edaf013-14c5-4d7b-b7d5-dfdeed1c6e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063486851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3063486851
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3019117328
Short name T723
Test name
Test status
Simulation time 315160764 ps
CPU time 16.68 seconds
Started Jul 19 05:44:19 PM PDT 24
Finished Jul 19 05:44:38 PM PDT 24
Peak memory 220096 kb
Host smart-bd1a28ee-da55-48ba-9e70-bb900e3f13e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019117328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3019117328
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.69025557
Short name T682
Test name
Test status
Simulation time 302252427 ps
CPU time 11.74 seconds
Started Jul 19 05:44:26 PM PDT 24
Finished Jul 19 05:44:39 PM PDT 24
Peak memory 226092 kb
Host smart-224ca2f0-76b4-4996-9282-5747c5129c33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69025557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_dig
est.69025557
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2002933202
Short name T564
Test name
Test status
Simulation time 411880658 ps
CPU time 12.1 seconds
Started Jul 19 05:44:23 PM PDT 24
Finished Jul 19 05:44:38 PM PDT 24
Peak memory 218300 kb
Host smart-aab2bc11-bca6-458a-8671-23864f9a29e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002933202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2002933202
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.351806225
Short name T635
Test name
Test status
Simulation time 1489380750 ps
CPU time 14.52 seconds
Started Jul 19 05:44:25 PM PDT 24
Finished Jul 19 05:44:41 PM PDT 24
Peak memory 226180 kb
Host smart-cfc6db75-838e-4d72-911a-6189331e9b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351806225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.351806225
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4002046126
Short name T66
Test name
Test status
Simulation time 96023547 ps
CPU time 1.98 seconds
Started Jul 19 05:44:15 PM PDT 24
Finished Jul 19 05:44:19 PM PDT 24
Peak memory 214204 kb
Host smart-210d0ca4-41fd-4ec4-9ea7-d981fb7e0aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002046126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4002046126
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2063260903
Short name T794
Test name
Test status
Simulation time 881625715 ps
CPU time 21.67 seconds
Started Jul 19 05:44:26 PM PDT 24
Finished Jul 19 05:44:49 PM PDT 24
Peak memory 251104 kb
Host smart-5f1ad9c5-4ef4-4720-a680-26c9ea4f92f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063260903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2063260903
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2730439034
Short name T234
Test name
Test status
Simulation time 144206070 ps
CPU time 7.48 seconds
Started Jul 19 05:44:24 PM PDT 24
Finished Jul 19 05:44:33 PM PDT 24
Peak memory 250688 kb
Host smart-bea085b6-4381-4676-a79a-08270bd26b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730439034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2730439034
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1189251076
Short name T36
Test name
Test status
Simulation time 1033298199 ps
CPU time 48.79 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:45:13 PM PDT 24
Peak memory 226124 kb
Host smart-ffd84748-0b11-41fc-af01-17bbb4bf29b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189251076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1189251076
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1536047250
Short name T382
Test name
Test status
Simulation time 21834182 ps
CPU time 0.89 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:44:23 PM PDT 24
Peak memory 212004 kb
Host smart-d3f82c04-586f-40c9-9c0f-0d5f6a56aad9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536047250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1536047250
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2057662471
Short name T54
Test name
Test status
Simulation time 59431367 ps
CPU time 1.02 seconds
Started Jul 19 05:44:23 PM PDT 24
Finished Jul 19 05:44:27 PM PDT 24
Peak memory 209092 kb
Host smart-af0b1baf-8acd-4c21-89bd-ac2e3dc15730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057662471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2057662471
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3908518147
Short name T269
Test name
Test status
Simulation time 1261310201 ps
CPU time 12.51 seconds
Started Jul 19 05:44:21 PM PDT 24
Finished Jul 19 05:44:36 PM PDT 24
Peak memory 226164 kb
Host smart-86fa2832-d409-4f19-b209-31c4aac45c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908518147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3908518147
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.576907130
Short name T611
Test name
Test status
Simulation time 259401096 ps
CPU time 4.18 seconds
Started Jul 19 05:44:22 PM PDT 24
Finished Jul 19 05:44:29 PM PDT 24
Peak memory 217196 kb
Host smart-2b28fc88-ca8b-43fa-97e1-3bde6fbc08c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576907130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.576907130
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2644540709
Short name T407
Test name
Test status
Simulation time 1379674795 ps
CPU time 43.82 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:45:07 PM PDT 24
Peak memory 218960 kb
Host smart-c4f82ffb-439a-457d-95ff-47aa9f1e0a38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644540709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2644540709
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2350284494
Short name T735
Test name
Test status
Simulation time 2689357807 ps
CPU time 7.22 seconds
Started Jul 19 05:44:21 PM PDT 24
Finished Jul 19 05:44:31 PM PDT 24
Peak memory 218400 kb
Host smart-33764688-2004-46f1-99fa-9f7b6a6a9b40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350284494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2350284494
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2855300715
Short name T464
Test name
Test status
Simulation time 176958353 ps
CPU time 5.75 seconds
Started Jul 19 05:44:22 PM PDT 24
Finished Jul 19 05:44:30 PM PDT 24
Peak memory 217704 kb
Host smart-4f668699-c2da-47f3-9c43-94293840d392
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855300715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2855300715
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3203414117
Short name T440
Test name
Test status
Simulation time 4331017668 ps
CPU time 77.33 seconds
Started Jul 19 05:44:21 PM PDT 24
Finished Jul 19 05:45:41 PM PDT 24
Peak memory 273144 kb
Host smart-569dd32a-6346-466e-ad3d-9fee02ab7aca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203414117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3203414117
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.4273538179
Short name T757
Test name
Test status
Simulation time 2178558540 ps
CPU time 15.66 seconds
Started Jul 19 05:44:21 PM PDT 24
Finished Jul 19 05:44:40 PM PDT 24
Peak memory 224380 kb
Host smart-1b438526-cc78-487f-95ac-16f080dae888
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273538179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.4273538179
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3465783263
Short name T633
Test name
Test status
Simulation time 17281919 ps
CPU time 1.46 seconds
Started Jul 19 05:44:24 PM PDT 24
Finished Jul 19 05:44:27 PM PDT 24
Peak memory 218376 kb
Host smart-36132bb5-2a91-44d6-8a06-9ca8c2daffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465783263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3465783263
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3467160898
Short name T301
Test name
Test status
Simulation time 1947524628 ps
CPU time 17.33 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:44:40 PM PDT 24
Peak memory 226100 kb
Host smart-423c685b-3966-4441-8071-733062366daa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467160898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3467160898
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3478036885
Short name T12
Test name
Test status
Simulation time 586594509 ps
CPU time 11.68 seconds
Started Jul 19 05:44:22 PM PDT 24
Finished Jul 19 05:44:36 PM PDT 24
Peak memory 218332 kb
Host smart-e39b3fdc-232f-4575-ba10-ad4b1cef26b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478036885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3478036885
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2816283062
Short name T393
Test name
Test status
Simulation time 612205770 ps
CPU time 8.61 seconds
Started Jul 19 05:44:21 PM PDT 24
Finished Jul 19 05:44:32 PM PDT 24
Peak memory 226056 kb
Host smart-869f847d-952c-462d-90fe-27f2a4d594d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816283062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2816283062
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.812388693
Short name T65
Test name
Test status
Simulation time 147503941 ps
CPU time 2.48 seconds
Started Jul 19 05:44:21 PM PDT 24
Finished Jul 19 05:44:26 PM PDT 24
Peak memory 223808 kb
Host smart-bc17bae9-b3f0-4565-ac2f-3b235be6ea2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812388693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.812388693
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.4202751092
Short name T409
Test name
Test status
Simulation time 985422732 ps
CPU time 33.04 seconds
Started Jul 19 05:44:22 PM PDT 24
Finished Jul 19 05:44:58 PM PDT 24
Peak memory 250864 kb
Host smart-1c126db6-4af6-42c5-965e-4621da63b18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202751092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.4202751092
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1035824255
Short name T341
Test name
Test status
Simulation time 308642076 ps
CPU time 9.1 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:44:32 PM PDT 24
Peak memory 251096 kb
Host smart-7575b1dd-fe1d-49b6-b053-f8d888138d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035824255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1035824255
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2559772716
Short name T572
Test name
Test status
Simulation time 4620899819 ps
CPU time 55.81 seconds
Started Jul 19 05:44:20 PM PDT 24
Finished Jul 19 05:45:19 PM PDT 24
Peak memory 226168 kb
Host smart-a2fcae6f-0124-495e-b761-5ca6d0603d52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559772716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2559772716
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3838089868
Short name T683
Test name
Test status
Simulation time 28770575 ps
CPU time 0.93 seconds
Started Jul 19 05:44:22 PM PDT 24
Finished Jul 19 05:44:26 PM PDT 24
Peak memory 212080 kb
Host smart-458a75b7-d4ba-4539-9261-d0a1f28b1d28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838089868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3838089868
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3557368830
Short name T565
Test name
Test status
Simulation time 159996451 ps
CPU time 0.96 seconds
Started Jul 19 05:42:54 PM PDT 24
Finished Jul 19 05:42:56 PM PDT 24
Peak memory 208944 kb
Host smart-65f12ba2-de5c-4a90-aa07-60d6277f927d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557368830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3557368830
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3250416358
Short name T731
Test name
Test status
Simulation time 33584791 ps
CPU time 0.91 seconds
Started Jul 19 05:42:48 PM PDT 24
Finished Jul 19 05:42:50 PM PDT 24
Peak memory 208828 kb
Host smart-ec8414a0-aa5f-4fbf-9849-4d067998fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250416358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3250416358
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2749553772
Short name T423
Test name
Test status
Simulation time 482636613 ps
CPU time 10.55 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:43:01 PM PDT 24
Peak memory 218252 kb
Host smart-6eeae0cb-b127-4d2f-8fde-bbf7b6351d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749553772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2749553772
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.879112662
Short name T329
Test name
Test status
Simulation time 20962828841 ps
CPU time 25.67 seconds
Started Jul 19 05:42:46 PM PDT 24
Finished Jul 19 05:43:12 PM PDT 24
Peak memory 217844 kb
Host smart-17b71b97-dc08-4b0b-b448-8f79faad362c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879112662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.879112662
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.4233907494
Short name T86
Test name
Test status
Simulation time 6617749884 ps
CPU time 28.96 seconds
Started Jul 19 05:42:48 PM PDT 24
Finished Jul 19 05:43:18 PM PDT 24
Peak memory 219028 kb
Host smart-253e8e86-168e-45ef-ac3b-47625f4dd717
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233907494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.4233907494
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.4130639487
Short name T616
Test name
Test status
Simulation time 1223045089 ps
CPU time 7.69 seconds
Started Jul 19 05:42:47 PM PDT 24
Finished Jul 19 05:42:56 PM PDT 24
Peak memory 217868 kb
Host smart-24dad206-c22a-4e1b-86cb-7514d6a0019f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130639487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.4
130639487
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2970665931
Short name T684
Test name
Test status
Simulation time 2171371420 ps
CPU time 8.91 seconds
Started Jul 19 05:42:47 PM PDT 24
Finished Jul 19 05:42:57 PM PDT 24
Peak memory 218352 kb
Host smart-648ff74a-9837-41d5-9e31-5d41938245fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970665931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2970665931
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2239101821
Short name T254
Test name
Test status
Simulation time 3311318285 ps
CPU time 22.84 seconds
Started Jul 19 05:42:48 PM PDT 24
Finished Jul 19 05:43:12 PM PDT 24
Peak memory 217764 kb
Host smart-7bcb2e36-4f47-4414-90f4-9e469207eb3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239101821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2239101821
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3876497260
Short name T704
Test name
Test status
Simulation time 245783123 ps
CPU time 8.27 seconds
Started Jul 19 05:42:48 PM PDT 24
Finished Jul 19 05:42:57 PM PDT 24
Peak memory 217724 kb
Host smart-4ed16b15-ed65-4673-808b-209f4d2335ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876497260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3876497260
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2189614289
Short name T692
Test name
Test status
Simulation time 1246578089 ps
CPU time 55.94 seconds
Started Jul 19 05:42:51 PM PDT 24
Finished Jul 19 05:43:47 PM PDT 24
Peak memory 253204 kb
Host smart-7cb77f60-72b0-4760-bfd4-d10a6957e7d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189614289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2189614289
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1741937706
Short name T299
Test name
Test status
Simulation time 741114040 ps
CPU time 11.83 seconds
Started Jul 19 05:42:47 PM PDT 24
Finished Jul 19 05:43:00 PM PDT 24
Peak memory 247960 kb
Host smart-3d6b4467-2247-4df7-81ec-95072da777d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741937706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1741937706
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2938148034
Short name T498
Test name
Test status
Simulation time 19259607 ps
CPU time 1.49 seconds
Started Jul 19 05:42:50 PM PDT 24
Finished Jul 19 05:42:53 PM PDT 24
Peak memory 221784 kb
Host smart-73d9cac1-a224-4b4c-8de3-b167a07d1c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938148034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2938148034
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3416535733
Short name T615
Test name
Test status
Simulation time 785684697 ps
CPU time 11.83 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:43:02 PM PDT 24
Peak memory 214780 kb
Host smart-7f0d11ce-60e5-4a6a-bdb0-7a3d80a5a59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416535733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3416535733
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3511859434
Short name T77
Test name
Test status
Simulation time 223943186 ps
CPU time 24.86 seconds
Started Jul 19 05:42:56 PM PDT 24
Finished Jul 19 05:43:22 PM PDT 24
Peak memory 269488 kb
Host smart-8f59d427-4947-428d-8594-120cfbe01160
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511859434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3511859434
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3272428498
Short name T253
Test name
Test status
Simulation time 177522552 ps
CPU time 7.76 seconds
Started Jul 19 05:42:52 PM PDT 24
Finished Jul 19 05:43:01 PM PDT 24
Peak memory 226232 kb
Host smart-e2a54a89-1728-490d-b99a-9f28413c14eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272428498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3272428498
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.140245846
Short name T734
Test name
Test status
Simulation time 1332309317 ps
CPU time 6.91 seconds
Started Jul 19 05:42:53 PM PDT 24
Finished Jul 19 05:43:01 PM PDT 24
Peak memory 218308 kb
Host smart-a181a387-7941-4d27-9671-c1e0ea27aafa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140245846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.140245846
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.844840912
Short name T340
Test name
Test status
Simulation time 42779733 ps
CPU time 1.19 seconds
Started Jul 19 05:42:48 PM PDT 24
Finished Jul 19 05:42:50 PM PDT 24
Peak memory 213600 kb
Host smart-829f304e-6234-43b6-9b0f-eb09d5f25324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844840912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.844840912
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1629959949
Short name T677
Test name
Test status
Simulation time 712907523 ps
CPU time 30.66 seconds
Started Jul 19 05:42:46 PM PDT 24
Finished Jul 19 05:43:17 PM PDT 24
Peak memory 251064 kb
Host smart-e40a8b98-d2c2-4236-aa1b-646543bc6069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629959949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1629959949
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.487311424
Short name T587
Test name
Test status
Simulation time 177457299 ps
CPU time 7.43 seconds
Started Jul 19 05:42:49 PM PDT 24
Finished Jul 19 05:42:58 PM PDT 24
Peak memory 247180 kb
Host smart-f6f0aaa1-cb66-4e92-b40f-12f1373e22a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487311424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.487311424
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2959685171
Short name T145
Test name
Test status
Simulation time 46645651187 ps
CPU time 113.8 seconds
Started Jul 19 05:42:53 PM PDT 24
Finished Jul 19 05:44:48 PM PDT 24
Peak memory 278640 kb
Host smart-a09c8d7c-85d3-40fc-919e-3b38d0aca86a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959685171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2959685171
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2927215393
Short name T161
Test name
Test status
Simulation time 58234982 ps
CPU time 0.84 seconds
Started Jul 19 05:42:48 PM PDT 24
Finished Jul 19 05:42:49 PM PDT 24
Peak memory 211996 kb
Host smart-6d592e66-c64c-41d1-886a-ff9c98397691
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927215393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2927215393
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3082260907
Short name T416
Test name
Test status
Simulation time 19718416 ps
CPU time 1.16 seconds
Started Jul 19 05:44:31 PM PDT 24
Finished Jul 19 05:44:33 PM PDT 24
Peak memory 209020 kb
Host smart-fc207fdc-08f6-4c27-a918-0fff56fae221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082260907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3082260907
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2847425168
Short name T313
Test name
Test status
Simulation time 1145051055 ps
CPU time 15.27 seconds
Started Jul 19 05:44:30 PM PDT 24
Finished Jul 19 05:44:46 PM PDT 24
Peak memory 226236 kb
Host smart-11cf27f3-0370-4103-8aa0-afacca11a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847425168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2847425168
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.355972704
Short name T51
Test name
Test status
Simulation time 65397211 ps
CPU time 2.41 seconds
Started Jul 19 05:44:33 PM PDT 24
Finished Jul 19 05:44:36 PM PDT 24
Peak memory 217748 kb
Host smart-3a2bd09b-a5dc-4061-a738-f83ea0fe56c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355972704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.355972704
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.78978051
Short name T553
Test name
Test status
Simulation time 202641600 ps
CPU time 3.56 seconds
Started Jul 19 05:44:30 PM PDT 24
Finished Jul 19 05:44:34 PM PDT 24
Peak memory 222588 kb
Host smart-2119828c-2a03-48d0-8ff4-202ceb83e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78978051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.78978051
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2455430714
Short name T792
Test name
Test status
Simulation time 1282381056 ps
CPU time 19.48 seconds
Started Jul 19 05:44:29 PM PDT 24
Finished Jul 19 05:44:50 PM PDT 24
Peak memory 219016 kb
Host smart-6ff8928e-dd7d-47ff-a58b-6b86e96d0c66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455430714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2455430714
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1887296115
Short name T681
Test name
Test status
Simulation time 443158360 ps
CPU time 16.16 seconds
Started Jul 19 05:44:30 PM PDT 24
Finished Jul 19 05:44:47 PM PDT 24
Peak memory 226112 kb
Host smart-aea3e42d-0111-4472-a5c3-4e6d3d19888a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887296115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1887296115
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3206947748
Short name T421
Test name
Test status
Simulation time 520659606 ps
CPU time 10.68 seconds
Started Jul 19 05:44:31 PM PDT 24
Finished Jul 19 05:44:42 PM PDT 24
Peak memory 218272 kb
Host smart-de6b9ced-f7f2-4f50-ae9d-3f576e302bb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206947748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3206947748
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1007996466
Short name T91
Test name
Test status
Simulation time 668885082 ps
CPU time 9.73 seconds
Started Jul 19 05:44:28 PM PDT 24
Finished Jul 19 05:44:39 PM PDT 24
Peak memory 226144 kb
Host smart-8c9607e4-2134-4962-8029-8e6ed6102848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007996466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1007996466
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1888280344
Short name T48
Test name
Test status
Simulation time 365917952 ps
CPU time 3.05 seconds
Started Jul 19 05:44:29 PM PDT 24
Finished Jul 19 05:44:33 PM PDT 24
Peak memory 217792 kb
Host smart-610695bb-7357-48d9-80ab-ac9be9ca5f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888280344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1888280344
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.4207808847
Short name T419
Test name
Test status
Simulation time 268445124 ps
CPU time 23.76 seconds
Started Jul 19 05:44:32 PM PDT 24
Finished Jul 19 05:44:57 PM PDT 24
Peak memory 251116 kb
Host smart-fbe0462f-a583-499d-98ca-9d3c69a52847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207808847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.4207808847
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2407298700
Short name T781
Test name
Test status
Simulation time 214630575 ps
CPU time 7.3 seconds
Started Jul 19 05:44:30 PM PDT 24
Finished Jul 19 05:44:39 PM PDT 24
Peak memory 251332 kb
Host smart-acf4f292-af1a-413c-b2de-09ea9837c450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407298700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2407298700
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3106508388
Short name T400
Test name
Test status
Simulation time 5324236886 ps
CPU time 196.39 seconds
Started Jul 19 05:44:31 PM PDT 24
Finished Jul 19 05:47:48 PM PDT 24
Peak memory 270488 kb
Host smart-d5a23117-a3a7-41a7-ba21-cd67e406a7e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106508388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3106508388
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.189907504
Short name T153
Test name
Test status
Simulation time 8972616629 ps
CPU time 173.79 seconds
Started Jul 19 05:44:31 PM PDT 24
Finished Jul 19 05:47:26 PM PDT 24
Peak memory 282316 kb
Host smart-0d2798a9-7fb2-467e-9959-6ecbed6148be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=189907504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.189907504
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2123593320
Short name T492
Test name
Test status
Simulation time 111166722 ps
CPU time 1 seconds
Started Jul 19 05:44:30 PM PDT 24
Finished Jul 19 05:44:32 PM PDT 24
Peak memory 211984 kb
Host smart-3a6919ed-4192-439f-aee5-13028c1f0e6b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123593320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2123593320
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1539743456
Short name T58
Test name
Test status
Simulation time 32712745 ps
CPU time 1 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:41 PM PDT 24
Peak memory 208936 kb
Host smart-352b28e0-66c4-4b48-adbe-7460bd26105c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539743456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1539743456
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1417295237
Short name T445
Test name
Test status
Simulation time 411028435 ps
CPU time 14.01 seconds
Started Jul 19 05:44:28 PM PDT 24
Finished Jul 19 05:44:43 PM PDT 24
Peak memory 226148 kb
Host smart-5316c8ad-b857-4c72-ae48-7d72befe6d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417295237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1417295237
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4152327134
Short name T5
Test name
Test status
Simulation time 50740695 ps
CPU time 1.93 seconds
Started Jul 19 05:44:29 PM PDT 24
Finished Jul 19 05:44:32 PM PDT 24
Peak memory 217232 kb
Host smart-6c937515-b3c1-4e50-8fad-8a7b18e8de9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152327134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4152327134
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3277870165
Short name T714
Test name
Test status
Simulation time 46705815 ps
CPU time 1.78 seconds
Started Jul 19 05:44:35 PM PDT 24
Finished Jul 19 05:44:38 PM PDT 24
Peak memory 218372 kb
Host smart-b2b8a172-c9ee-49c1-9c17-9624dd6ce772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277870165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3277870165
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2464558400
Short name T798
Test name
Test status
Simulation time 230635562 ps
CPU time 10.61 seconds
Started Jul 19 05:44:36 PM PDT 24
Finished Jul 19 05:44:47 PM PDT 24
Peak memory 226104 kb
Host smart-a5e8e61d-7937-4dcb-838a-944e405504d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464558400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2464558400
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3196000742
Short name T804
Test name
Test status
Simulation time 868625932 ps
CPU time 9.27 seconds
Started Jul 19 05:44:29 PM PDT 24
Finished Jul 19 05:44:40 PM PDT 24
Peak memory 218384 kb
Host smart-9794c542-3b8d-42cf-8095-b0dbbda8fd74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196000742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3196000742
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.487726388
Short name T597
Test name
Test status
Simulation time 270917225 ps
CPU time 11.27 seconds
Started Jul 19 05:44:29 PM PDT 24
Finished Jul 19 05:44:42 PM PDT 24
Peak memory 218444 kb
Host smart-4eb840ab-c2a4-47a1-949f-5ccae62d640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487726388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.487726388
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1984134380
Short name T72
Test name
Test status
Simulation time 37229943 ps
CPU time 2.07 seconds
Started Jul 19 05:44:31 PM PDT 24
Finished Jul 19 05:44:34 PM PDT 24
Peak memory 217764 kb
Host smart-155bce31-c95e-4209-ac2f-b114d9187b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984134380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1984134380
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3284897039
Short name T285
Test name
Test status
Simulation time 506090853 ps
CPU time 25.23 seconds
Started Jul 19 05:44:28 PM PDT 24
Finished Jul 19 05:44:54 PM PDT 24
Peak memory 246132 kb
Host smart-059ff8ec-36ec-40fd-a6d9-6df253612156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284897039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3284897039
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3437736916
Short name T302
Test name
Test status
Simulation time 161108954 ps
CPU time 3.05 seconds
Started Jul 19 05:44:29 PM PDT 24
Finished Jul 19 05:44:34 PM PDT 24
Peak memory 222700 kb
Host smart-2a5eeb0f-cc93-4147-acf8-6a2a3130d706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437736916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3437736916
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3939836217
Short name T515
Test name
Test status
Simulation time 34309494952 ps
CPU time 169.57 seconds
Started Jul 19 05:44:35 PM PDT 24
Finished Jul 19 05:47:26 PM PDT 24
Peak memory 226160 kb
Host smart-52582a2b-f4ef-43b4-a72e-1bb9da83abf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939836217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3939836217
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2535557187
Short name T137
Test name
Test status
Simulation time 112482010422 ps
CPU time 577.99 seconds
Started Jul 19 05:44:40 PM PDT 24
Finished Jul 19 05:54:20 PM PDT 24
Peak memory 333196 kb
Host smart-c934bd21-e410-4ade-be21-491da507d54c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2535557187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.2535557187
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3097029242
Short name T861
Test name
Test status
Simulation time 20230625 ps
CPU time 1 seconds
Started Jul 19 05:44:32 PM PDT 24
Finished Jul 19 05:44:33 PM PDT 24
Peak memory 211996 kb
Host smart-d11d484c-0bf2-40fd-ba4a-3b48386e2b38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097029242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3097029242
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1591493196
Short name T474
Test name
Test status
Simulation time 22176778 ps
CPU time 1.3 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:42 PM PDT 24
Peak memory 209192 kb
Host smart-330a5a41-1f18-4b36-8aba-3cbed39c8dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591493196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1591493196
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1316740864
Short name T487
Test name
Test status
Simulation time 1704163883 ps
CPU time 10.75 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:51 PM PDT 24
Peak memory 225880 kb
Host smart-72ef2803-4dc6-4d75-a634-590ac849fa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316740864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1316740864
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1093906224
Short name T31
Test name
Test status
Simulation time 189934444 ps
CPU time 3.46 seconds
Started Jul 19 05:44:42 PM PDT 24
Finished Jul 19 05:44:47 PM PDT 24
Peak memory 217284 kb
Host smart-60e369eb-31b6-4ab1-b415-63c66ad2b40c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093906224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1093906224
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2642613681
Short name T282
Test name
Test status
Simulation time 42926515 ps
CPU time 1.97 seconds
Started Jul 19 05:44:41 PM PDT 24
Finished Jul 19 05:44:45 PM PDT 24
Peak memory 218420 kb
Host smart-8b48b95f-61ef-452e-89a8-cdb8c13e1670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642613681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2642613681
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1203904912
Short name T651
Test name
Test status
Simulation time 683116957 ps
CPU time 9.71 seconds
Started Jul 19 05:44:37 PM PDT 24
Finished Jul 19 05:44:48 PM PDT 24
Peak memory 226096 kb
Host smart-5d80d5d9-9c2b-431e-8ec2-c275fed6a65a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203904912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1203904912
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2707936468
Short name T275
Test name
Test status
Simulation time 1360585703 ps
CPU time 12.55 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:52 PM PDT 24
Peak memory 218312 kb
Host smart-8190d95d-9861-418a-9e1f-20850508d657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707936468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2707936468
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.802982603
Short name T482
Test name
Test status
Simulation time 2591337585 ps
CPU time 7.22 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:47 PM PDT 24
Peak memory 226232 kb
Host smart-063c0b02-81f1-4a81-903f-eea72c70a226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802982603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.802982603
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.382582073
Short name T844
Test name
Test status
Simulation time 50726145 ps
CPU time 1.71 seconds
Started Jul 19 05:44:39 PM PDT 24
Finished Jul 19 05:44:44 PM PDT 24
Peak memory 217780 kb
Host smart-4d7608f6-dc5f-476f-a970-3f09953aa714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382582073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.382582073
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3122973221
Short name T839
Test name
Test status
Simulation time 240375272 ps
CPU time 24.1 seconds
Started Jul 19 05:44:37 PM PDT 24
Finished Jul 19 05:45:02 PM PDT 24
Peak memory 251080 kb
Host smart-07435900-f5bf-4ec0-800b-fcd52dd00de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122973221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3122973221
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1693255542
Short name T404
Test name
Test status
Simulation time 147454841 ps
CPU time 10.39 seconds
Started Jul 19 05:44:35 PM PDT 24
Finished Jul 19 05:44:47 PM PDT 24
Peak memory 251108 kb
Host smart-4eca1640-ed6e-4a76-9013-452659a00274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693255542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1693255542
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2931628587
Short name T170
Test name
Test status
Simulation time 6776129613 ps
CPU time 122.95 seconds
Started Jul 19 05:44:37 PM PDT 24
Finished Jul 19 05:46:41 PM PDT 24
Peak memory 251168 kb
Host smart-9dcec4a2-bb45-4334-8ef8-7d5da22dfe6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931628587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2931628587
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3274026950
Short name T820
Test name
Test status
Simulation time 13237488 ps
CPU time 1.07 seconds
Started Jul 19 05:44:41 PM PDT 24
Finished Jul 19 05:44:44 PM PDT 24
Peak memory 213040 kb
Host smart-24d68f6b-abd9-40f3-b5ad-96bdf530c83f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274026950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3274026950
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2517416687
Short name T816
Test name
Test status
Simulation time 194633741 ps
CPU time 7.73 seconds
Started Jul 19 05:44:39 PM PDT 24
Finished Jul 19 05:44:49 PM PDT 24
Peak memory 218400 kb
Host smart-6e95128e-b0a0-4b08-8665-4261b2aec8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517416687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2517416687
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.4000124924
Short name T26
Test name
Test status
Simulation time 502101040 ps
CPU time 7.16 seconds
Started Jul 19 05:44:41 PM PDT 24
Finished Jul 19 05:44:50 PM PDT 24
Peak memory 217292 kb
Host smart-8703c526-a674-488b-8789-78effd9f563a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000124924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.4000124924
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.393026792
Short name T273
Test name
Test status
Simulation time 358871543 ps
CPU time 4.01 seconds
Started Jul 19 05:44:41 PM PDT 24
Finished Jul 19 05:44:47 PM PDT 24
Peak memory 222468 kb
Host smart-d60a288a-d0f1-4d70-b37a-ec2c483f4713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393026792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.393026792
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.595437165
Short name T566
Test name
Test status
Simulation time 1200376600 ps
CPU time 12.6 seconds
Started Jul 19 05:44:41 PM PDT 24
Finished Jul 19 05:44:56 PM PDT 24
Peak memory 226140 kb
Host smart-37f4e3a6-9482-43c5-a199-d78fdd5f15da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595437165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.595437165
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3584966259
Short name T634
Test name
Test status
Simulation time 374466253 ps
CPU time 14.73 seconds
Started Jul 19 05:44:37 PM PDT 24
Finished Jul 19 05:44:54 PM PDT 24
Peak memory 226096 kb
Host smart-f30cf15f-11f0-41c3-9d07-40178b112556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584966259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3584966259
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.308617178
Short name T496
Test name
Test status
Simulation time 559494427 ps
CPU time 8.08 seconds
Started Jul 19 05:44:39 PM PDT 24
Finished Jul 19 05:44:49 PM PDT 24
Peak memory 218304 kb
Host smart-4e9e87f6-0876-4807-9598-f5cf80909179
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308617178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.308617178
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2485391892
Short name T343
Test name
Test status
Simulation time 258803626 ps
CPU time 6.82 seconds
Started Jul 19 05:44:40 PM PDT 24
Finished Jul 19 05:44:50 PM PDT 24
Peak memory 218440 kb
Host smart-e0f5f4f7-d41c-4c92-9fe1-ae2786a05571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485391892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2485391892
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1920345224
Short name T619
Test name
Test status
Simulation time 14829660 ps
CPU time 1.34 seconds
Started Jul 19 05:44:39 PM PDT 24
Finished Jul 19 05:44:42 PM PDT 24
Peak memory 212120 kb
Host smart-24419c48-3a37-4a06-9b13-c2bd42f97a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920345224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1920345224
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1705206548
Short name T330
Test name
Test status
Simulation time 239609959 ps
CPU time 24.49 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:45:05 PM PDT 24
Peak memory 246248 kb
Host smart-6aa0cc30-6796-4f4b-9860-f0a173a1cff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705206548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1705206548
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2061315956
Short name T793
Test name
Test status
Simulation time 467213961 ps
CPU time 6.98 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:46 PM PDT 24
Peak memory 247060 kb
Host smart-4318dd96-25df-4be9-8bf3-1c9562a3188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061315956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2061315956
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3061899302
Short name T25
Test name
Test status
Simulation time 82678981382 ps
CPU time 516.59 seconds
Started Jul 19 05:44:41 PM PDT 24
Finished Jul 19 05:53:20 PM PDT 24
Peak memory 261492 kb
Host smart-b248a42d-ec90-43e3-89b2-f9abd7560f60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3061899302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3061899302
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3585915631
Short name T371
Test name
Test status
Simulation time 44310764 ps
CPU time 0.91 seconds
Started Jul 19 05:44:40 PM PDT 24
Finished Jul 19 05:44:43 PM PDT 24
Peak memory 212028 kb
Host smart-0a327df4-25b7-44ba-b826-c70f08f9b496
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585915631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3585915631
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3286274227
Short name T277
Test name
Test status
Simulation time 60246802 ps
CPU time 0.91 seconds
Started Jul 19 05:44:51 PM PDT 24
Finished Jul 19 05:44:53 PM PDT 24
Peak memory 208988 kb
Host smart-bc6ee3ee-b5a6-41fa-a6df-6687c3c2d5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286274227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3286274227
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3218957269
Short name T821
Test name
Test status
Simulation time 538238154 ps
CPU time 9.74 seconds
Started Jul 19 05:44:37 PM PDT 24
Finished Jul 19 05:44:47 PM PDT 24
Peak memory 226124 kb
Host smart-f6765ed1-b9fd-4852-b4ac-0717fb678093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218957269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3218957269
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3874697942
Short name T372
Test name
Test status
Simulation time 740680096 ps
CPU time 5.36 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:45 PM PDT 24
Peak memory 217292 kb
Host smart-9ae297b2-2886-4736-bb3a-55a9ceaf8efa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874697942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3874697942
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.514723744
Short name T503
Test name
Test status
Simulation time 44075022 ps
CPU time 1.58 seconds
Started Jul 19 05:44:42 PM PDT 24
Finished Jul 19 05:44:45 PM PDT 24
Peak memory 222008 kb
Host smart-01a995f2-a095-4435-a9a6-b1a39ecfa8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514723744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.514723744
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1392208345
Short name T163
Test name
Test status
Simulation time 539147640 ps
CPU time 13.46 seconds
Started Jul 19 05:44:39 PM PDT 24
Finished Jul 19 05:44:55 PM PDT 24
Peak memory 226096 kb
Host smart-30212a7c-f51e-43f0-ad70-e0093398d537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392208345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1392208345
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1985031425
Short name T508
Test name
Test status
Simulation time 986615586 ps
CPU time 7.91 seconds
Started Jul 19 05:44:40 PM PDT 24
Finished Jul 19 05:44:51 PM PDT 24
Peak memory 218320 kb
Host smart-0de99d4d-ccc3-47f5-ba3e-4d18491b9dbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985031425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1985031425
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2523796932
Short name T364
Test name
Test status
Simulation time 527906907 ps
CPU time 12.49 seconds
Started Jul 19 05:44:39 PM PDT 24
Finished Jul 19 05:44:54 PM PDT 24
Peak memory 218408 kb
Host smart-f43d95fe-1d0a-484a-a6c8-206024ddb6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523796932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2523796932
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2689123016
Short name T545
Test name
Test status
Simulation time 226961095 ps
CPU time 3.25 seconds
Started Jul 19 05:44:40 PM PDT 24
Finished Jul 19 05:44:45 PM PDT 24
Peak memory 217792 kb
Host smart-fe414a4b-6389-4978-b0fd-afe1e2c19097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689123016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2689123016
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.622297982
Short name T859
Test name
Test status
Simulation time 1831599323 ps
CPU time 28.39 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:45:09 PM PDT 24
Peak memory 251120 kb
Host smart-9fb3e2e5-e10d-464d-b796-48740d6ce190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622297982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.622297982
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.816182954
Short name T583
Test name
Test status
Simulation time 47973104 ps
CPU time 5.8 seconds
Started Jul 19 05:44:38 PM PDT 24
Finished Jul 19 05:44:46 PM PDT 24
Peak memory 242924 kb
Host smart-ad29b4b3-132a-439d-9e79-9e70feb70707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816182954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.816182954
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.545066942
Short name T43
Test name
Test status
Simulation time 5873024840 ps
CPU time 182.09 seconds
Started Jul 19 05:44:40 PM PDT 24
Finished Jul 19 05:47:45 PM PDT 24
Peak memory 251180 kb
Host smart-c0984fc2-1d23-4f89-be12-67715a517ecd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545066942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.545066942
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1313297853
Short name T766
Test name
Test status
Simulation time 34430466 ps
CPU time 0.93 seconds
Started Jul 19 05:44:39 PM PDT 24
Finished Jul 19 05:44:43 PM PDT 24
Peak memory 211920 kb
Host smart-5d056339-cea0-42c0-bd1f-8c91964adff8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313297853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1313297853
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3153529120
Short name T563
Test name
Test status
Simulation time 87462082 ps
CPU time 1.3 seconds
Started Jul 19 05:44:51 PM PDT 24
Finished Jul 19 05:44:54 PM PDT 24
Peak memory 209108 kb
Host smart-7e65f599-63b8-486d-95ef-e1d0591ae32d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153529120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3153529120
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2677150078
Short name T511
Test name
Test status
Simulation time 296259511 ps
CPU time 10.44 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:45:07 PM PDT 24
Peak memory 226048 kb
Host smart-74a2fc66-ccb1-4414-a844-0ae58bdce557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677150078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2677150078
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3356900455
Short name T760
Test name
Test status
Simulation time 11632529167 ps
CPU time 17.17 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:45:13 PM PDT 24
Peak memory 217820 kb
Host smart-9184eb1e-c354-4977-adc3-70e62c797379
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356900455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3356900455
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.4248960234
Short name T656
Test name
Test status
Simulation time 327156268 ps
CPU time 3.12 seconds
Started Jul 19 05:44:54 PM PDT 24
Finished Jul 19 05:44:59 PM PDT 24
Peak memory 218380 kb
Host smart-7260f3a4-7503-4786-9237-89d7c8e8f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248960234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4248960234
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.470720578
Short name T527
Test name
Test status
Simulation time 1485365854 ps
CPU time 16.4 seconds
Started Jul 19 05:44:58 PM PDT 24
Finished Jul 19 05:45:17 PM PDT 24
Peak memory 226160 kb
Host smart-a1b1b833-c63c-4052-87cd-fafcffa30d34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470720578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.470720578
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3740186170
Short name T44
Test name
Test status
Simulation time 1133443192 ps
CPU time 9.43 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:45:02 PM PDT 24
Peak memory 226236 kb
Host smart-d5c47525-84fe-4d27-8991-b20084b52cd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740186170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3740186170
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3109203945
Short name T784
Test name
Test status
Simulation time 2974394435 ps
CPU time 11.85 seconds
Started Jul 19 05:44:51 PM PDT 24
Finished Jul 19 05:45:03 PM PDT 24
Peak memory 218332 kb
Host smart-60541ea5-7efd-41cc-892c-dc40018c776b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109203945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3109203945
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1519619083
Short name T613
Test name
Test status
Simulation time 852286014 ps
CPU time 9.06 seconds
Started Jul 19 05:44:53 PM PDT 24
Finished Jul 19 05:45:03 PM PDT 24
Peak memory 225572 kb
Host smart-56418ea3-fd0f-4de9-8104-837ffba22644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519619083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1519619083
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.965528168
Short name T208
Test name
Test status
Simulation time 36107499 ps
CPU time 2.49 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:44:59 PM PDT 24
Peak memory 217736 kb
Host smart-1a13cf2b-8cbf-4c3a-a637-00de44a50ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965528168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.965528168
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2597225342
Short name T763
Test name
Test status
Simulation time 406240970 ps
CPU time 28.26 seconds
Started Jul 19 05:44:51 PM PDT 24
Finished Jul 19 05:45:21 PM PDT 24
Peak memory 251064 kb
Host smart-ab725777-4eac-418d-9571-4ea499df2226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597225342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2597225342
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1870848675
Short name T543
Test name
Test status
Simulation time 222073087 ps
CPU time 10.16 seconds
Started Jul 19 05:44:53 PM PDT 24
Finished Jul 19 05:45:04 PM PDT 24
Peak memory 251168 kb
Host smart-6eee0153-f49d-4123-b75e-d7039820efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870848675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1870848675
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2351967929
Short name T35
Test name
Test status
Simulation time 3587981757 ps
CPU time 103.72 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:46:38 PM PDT 24
Peak memory 275752 kb
Host smart-65bba4e3-3e05-4d47-9e86-4ec322b442b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351967929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2351967929
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1308056632
Short name T558
Test name
Test status
Simulation time 18841226 ps
CPU time 0.83 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:44:54 PM PDT 24
Peak memory 211952 kb
Host smart-9356b6a9-b9dd-4787-912a-3e8bb1a827d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308056632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1308056632
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2120468421
Short name T716
Test name
Test status
Simulation time 16668844 ps
CPU time 1.09 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:44:54 PM PDT 24
Peak memory 209044 kb
Host smart-834cfcfa-6420-4e03-b57c-b53dc806d649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120468421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2120468421
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4007952772
Short name T646
Test name
Test status
Simulation time 270827773 ps
CPU time 9.62 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:45:03 PM PDT 24
Peak memory 218328 kb
Host smart-81b69de1-e866-47ab-8cb3-c64488cd5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007952772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4007952772
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3301876574
Short name T370
Test name
Test status
Simulation time 4566644833 ps
CPU time 11.23 seconds
Started Jul 19 05:44:58 PM PDT 24
Finished Jul 19 05:45:11 PM PDT 24
Peak memory 217828 kb
Host smart-f64d2f9a-4b2a-48b9-8421-8dd83a7e894e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301876574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3301876574
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3551556454
Short name T865
Test name
Test status
Simulation time 38041866 ps
CPU time 1.83 seconds
Started Jul 19 05:44:56 PM PDT 24
Finished Jul 19 05:45:00 PM PDT 24
Peak memory 218360 kb
Host smart-18a55e42-030a-400d-ada0-6bba84401d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551556454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3551556454
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.813571928
Short name T460
Test name
Test status
Simulation time 257484706 ps
CPU time 10.73 seconds
Started Jul 19 05:44:54 PM PDT 24
Finished Jul 19 05:45:06 PM PDT 24
Peak memory 219016 kb
Host smart-28c0e0b3-3e3f-4173-8ab0-7dbbad94f808
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813571928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.813571928
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1119842098
Short name T758
Test name
Test status
Simulation time 417906497 ps
CPU time 11.66 seconds
Started Jul 19 05:44:53 PM PDT 24
Finished Jul 19 05:45:06 PM PDT 24
Peak memory 226104 kb
Host smart-ebc0834d-5a66-4a5a-9bf4-66a69b2eecea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119842098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1119842098
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2029248672
Short name T851
Test name
Test status
Simulation time 319309665 ps
CPU time 10.97 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:45:08 PM PDT 24
Peak memory 218304 kb
Host smart-4c9170c3-03ab-47c6-8503-d1f95a146e29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029248672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2029248672
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3226553126
Short name T378
Test name
Test status
Simulation time 1512013644 ps
CPU time 14.17 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:45:08 PM PDT 24
Peak memory 226168 kb
Host smart-3378eaa2-3756-4c77-a587-fed207550dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226553126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3226553126
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2722156923
Short name T622
Test name
Test status
Simulation time 55640294 ps
CPU time 1.34 seconds
Started Jul 19 05:44:51 PM PDT 24
Finished Jul 19 05:44:53 PM PDT 24
Peak memory 213832 kb
Host smart-ae840dd6-0a89-4acf-b20b-4391a3d48b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722156923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2722156923
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2578335375
Short name T769
Test name
Test status
Simulation time 3174151545 ps
CPU time 23.11 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:45:17 PM PDT 24
Peak memory 246060 kb
Host smart-21dc0f77-a810-4936-afa5-70bea3e7429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578335375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2578335375
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1805376645
Short name T631
Test name
Test status
Simulation time 80447475 ps
CPU time 3.92 seconds
Started Jul 19 05:44:53 PM PDT 24
Finished Jul 19 05:44:58 PM PDT 24
Peak memory 222728 kb
Host smart-433d127c-5f63-4d5d-83ed-c57b2010d1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805376645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1805376645
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4221275700
Short name T151
Test name
Test status
Simulation time 139924144738 ps
CPU time 334.55 seconds
Started Jul 19 05:44:56 PM PDT 24
Finished Jul 19 05:50:32 PM PDT 24
Peak memory 447628 kb
Host smart-eb2bca07-4746-4380-a8a0-5183c6e01a09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221275700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4221275700
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2405448504
Short name T610
Test name
Test status
Simulation time 51743772 ps
CPU time 1.07 seconds
Started Jul 19 05:44:54 PM PDT 24
Finished Jul 19 05:44:56 PM PDT 24
Peak memory 213072 kb
Host smart-d1239349-cbbb-4ef0-81d7-481b21497ab3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405448504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2405448504
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1537657325
Short name T614
Test name
Test status
Simulation time 17573066 ps
CPU time 0.86 seconds
Started Jul 19 05:44:54 PM PDT 24
Finished Jul 19 05:44:56 PM PDT 24
Peak memory 208964 kb
Host smart-eaedce1f-cab5-4c66-9a2c-8ea9fb5b9e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537657325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1537657325
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.35977190
Short name T401
Test name
Test status
Simulation time 569950914 ps
CPU time 8.59 seconds
Started Jul 19 05:44:59 PM PDT 24
Finished Jul 19 05:45:09 PM PDT 24
Peak memory 218304 kb
Host smart-6e94fa73-3c7f-4a85-8ac4-a64999fd3eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35977190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.35977190
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1813117009
Short name T427
Test name
Test status
Simulation time 233864087 ps
CPU time 7.22 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:45:04 PM PDT 24
Peak memory 217176 kb
Host smart-9def0d88-76bf-4b63-8292-edf5043e9485
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813117009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1813117009
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1702994591
Short name T678
Test name
Test status
Simulation time 164344207 ps
CPU time 2.14 seconds
Started Jul 19 05:44:56 PM PDT 24
Finished Jul 19 05:44:59 PM PDT 24
Peak memory 218360 kb
Host smart-5f3ada96-267b-4f67-b210-bb852f38cfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702994591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1702994591
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2956668591
Short name T438
Test name
Test status
Simulation time 212867729 ps
CPU time 8.97 seconds
Started Jul 19 05:44:58 PM PDT 24
Finished Jul 19 05:45:09 PM PDT 24
Peak memory 226096 kb
Host smart-adbc3e4d-120e-4c2d-9a73-85925c9e85e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956668591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2956668591
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.772540434
Short name T509
Test name
Test status
Simulation time 933344489 ps
CPU time 7.25 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:10 PM PDT 24
Peak memory 218316 kb
Host smart-50801239-dfa5-4d15-b303-d4044892ab6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772540434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.772540434
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.717793119
Short name T595
Test name
Test status
Simulation time 267339483 ps
CPU time 8.6 seconds
Started Jul 19 05:44:58 PM PDT 24
Finished Jul 19 05:45:09 PM PDT 24
Peak memory 218120 kb
Host smart-17f1b2bf-e786-4860-978c-f3d3e27fd0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717793119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.717793119
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2623127510
Short name T50
Test name
Test status
Simulation time 753327609 ps
CPU time 5.41 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:45:02 PM PDT 24
Peak memory 217780 kb
Host smart-101e2448-9383-4502-8673-fb23b199c68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623127510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2623127510
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.884473760
Short name T157
Test name
Test status
Simulation time 629177325 ps
CPU time 18.29 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:45:11 PM PDT 24
Peak memory 251108 kb
Host smart-8f89eec4-f860-4418-9721-8db7e6001455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884473760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.884473760
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3604691580
Short name T666
Test name
Test status
Simulation time 82324186 ps
CPU time 4.33 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:44:58 PM PDT 24
Peak memory 222776 kb
Host smart-88235b9f-0aac-48df-a133-253d4958b8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604691580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3604691580
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.128401
Short name T671
Test name
Test status
Simulation time 5290193643 ps
CPU time 116.28 seconds
Started Jul 19 05:44:57 PM PDT 24
Finished Jul 19 05:46:55 PM PDT 24
Peak memory 283860 kb
Host smart-74b09c87-1609-4565-9cb3-e1c3032b3bbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TES
T_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
lc_ctrl_stress_all.128401
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3310341454
Short name T93
Test name
Test status
Simulation time 23054844444 ps
CPU time 401.78 seconds
Started Jul 19 05:44:57 PM PDT 24
Finished Jul 19 05:51:40 PM PDT 24
Peak memory 267676 kb
Host smart-8322c4e6-28cc-4b95-aab0-ac709f1bd8e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3310341454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3310341454
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.817138884
Short name T787
Test name
Test status
Simulation time 13961405 ps
CPU time 0.89 seconds
Started Jul 19 05:44:52 PM PDT 24
Finished Jul 19 05:44:54 PM PDT 24
Peak memory 212000 kb
Host smart-0e2a4a93-2363-4659-b33f-bbd0fd78c258
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817138884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.817138884
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3174018965
Short name T346
Test name
Test status
Simulation time 82816289 ps
CPU time 1.06 seconds
Started Jul 19 05:44:56 PM PDT 24
Finished Jul 19 05:44:58 PM PDT 24
Peak memory 208976 kb
Host smart-322d054e-e155-46e2-abda-fe2f387ce510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174018965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3174018965
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4188839165
Short name T554
Test name
Test status
Simulation time 7002016041 ps
CPU time 26.75 seconds
Started Jul 19 05:44:58 PM PDT 24
Finished Jul 19 05:45:26 PM PDT 24
Peak memory 217804 kb
Host smart-c50cb3c5-6c64-48b7-b9db-a857d6e4cc00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188839165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.4188839165
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2430491352
Short name T402
Test name
Test status
Simulation time 151636931 ps
CPU time 3.36 seconds
Started Jul 19 05:44:57 PM PDT 24
Finished Jul 19 05:45:01 PM PDT 24
Peak memory 222260 kb
Host smart-4a639b82-2345-41f8-b4a7-08c4a6f8efac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430491352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2430491352
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3798862748
Short name T459
Test name
Test status
Simulation time 1180103742 ps
CPU time 13.2 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:15 PM PDT 24
Peak memory 218980 kb
Host smart-549492a3-d8ee-491e-b99d-6b1fea8f3704
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798862748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3798862748
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3160283858
Short name T380
Test name
Test status
Simulation time 1485024627 ps
CPU time 13.58 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:16 PM PDT 24
Peak memory 226108 kb
Host smart-5bdde132-13dc-49fb-836b-729df09ab724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160283858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3160283858
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2074803783
Short name T573
Test name
Test status
Simulation time 358989270 ps
CPU time 8.9 seconds
Started Jul 19 05:44:59 PM PDT 24
Finished Jul 19 05:45:10 PM PDT 24
Peak memory 218300 kb
Host smart-5fd1da2a-0653-464b-b805-73498947b6b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074803783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2074803783
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1129813623
Short name T520
Test name
Test status
Simulation time 927203873 ps
CPU time 6.46 seconds
Started Jul 19 05:44:57 PM PDT 24
Finished Jul 19 05:45:05 PM PDT 24
Peak memory 225032 kb
Host smart-bf386ef9-6278-4181-955f-8b0c1973a0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129813623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1129813623
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2243146262
Short name T68
Test name
Test status
Simulation time 39802010 ps
CPU time 1.82 seconds
Started Jul 19 05:44:56 PM PDT 24
Finished Jul 19 05:45:00 PM PDT 24
Peak memory 217788 kb
Host smart-b761274f-84d7-46f4-bcd2-8dc212751905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243146262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2243146262
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3280620526
Short name T226
Test name
Test status
Simulation time 480968750 ps
CPU time 24.7 seconds
Started Jul 19 05:44:53 PM PDT 24
Finished Jul 19 05:45:19 PM PDT 24
Peak memory 250992 kb
Host smart-cd41ce66-416d-4784-b952-728d840367ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280620526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3280620526
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2853666538
Short name T479
Test name
Test status
Simulation time 218168385 ps
CPU time 7.39 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:45:04 PM PDT 24
Peak memory 251108 kb
Host smart-68a15f8d-78e7-4e40-b774-6275daf07b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853666538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2853666538
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.4039495386
Short name T88
Test name
Test status
Simulation time 24664601701 ps
CPU time 58.98 seconds
Started Jul 19 05:44:58 PM PDT 24
Finished Jul 19 05:45:59 PM PDT 24
Peak memory 274736 kb
Host smart-48353758-750e-402a-8377-ffce2de1c4f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039495386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.4039495386
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3307766734
Short name T146
Test name
Test status
Simulation time 16767935 ps
CPU time 0.88 seconds
Started Jul 19 05:44:56 PM PDT 24
Finished Jul 19 05:44:59 PM PDT 24
Peak memory 212012 kb
Host smart-8547d1cb-4f49-4744-9744-9cad7cd16999
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307766734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3307766734
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2942199968
Short name T863
Test name
Test status
Simulation time 20081730 ps
CPU time 1.12 seconds
Started Jul 19 05:44:55 PM PDT 24
Finished Jul 19 05:44:57 PM PDT 24
Peak memory 209028 kb
Host smart-00112e52-7310-4984-82e8-5fffdde00f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942199968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2942199968
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1540346814
Short name T87
Test name
Test status
Simulation time 1252000485 ps
CPU time 11.4 seconds
Started Jul 19 05:44:59 PM PDT 24
Finished Jul 19 05:45:12 PM PDT 24
Peak memory 218372 kb
Host smart-23d0c88f-b621-4721-9eb6-9316aeec81ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540346814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1540346814
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3125959379
Short name T339
Test name
Test status
Simulation time 261393726 ps
CPU time 3.36 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:06 PM PDT 24
Peak memory 217796 kb
Host smart-52b4992a-4f1d-4fec-8694-ac3c3bd335bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125959379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3125959379
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2491212233
Short name T632
Test name
Test status
Simulation time 96730028 ps
CPU time 1.82 seconds
Started Jul 19 05:44:57 PM PDT 24
Finished Jul 19 05:45:00 PM PDT 24
Peak memory 218372 kb
Host smart-53fdc0df-c0a3-4fda-bfc1-2d056382e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491212233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2491212233
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2561078567
Short name T466
Test name
Test status
Simulation time 279070658 ps
CPU time 11.07 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:13 PM PDT 24
Peak memory 226132 kb
Host smart-d97999b9-eacb-425f-b5fb-18cca871263a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561078567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2561078567
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.762597791
Short name T488
Test name
Test status
Simulation time 1612806319 ps
CPU time 15.61 seconds
Started Jul 19 05:44:58 PM PDT 24
Finished Jul 19 05:45:16 PM PDT 24
Peak memory 225728 kb
Host smart-0f16b8fe-a46e-4033-a4e9-bd16498027f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762597791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.762597791
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1652767100
Short name T823
Test name
Test status
Simulation time 814020484 ps
CPU time 8.73 seconds
Started Jul 19 05:44:58 PM PDT 24
Finished Jul 19 05:45:09 PM PDT 24
Peak memory 218308 kb
Host smart-c07eb09b-0f6a-403a-a92b-a5136477fa40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652767100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1652767100
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3738658108
Short name T41
Test name
Test status
Simulation time 630676160 ps
CPU time 7.08 seconds
Started Jul 19 05:44:59 PM PDT 24
Finished Jul 19 05:45:08 PM PDT 24
Peak memory 218500 kb
Host smart-c6fd4d09-e1a3-4a6e-aa83-2e7320ce7fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738658108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3738658108
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4180750096
Short name T752
Test name
Test status
Simulation time 448582556 ps
CPU time 3.78 seconds
Started Jul 19 05:44:56 PM PDT 24
Finished Jul 19 05:45:02 PM PDT 24
Peak memory 217800 kb
Host smart-cc062aeb-924c-4074-8351-8ede55e43322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180750096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.4180750096
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.956308163
Short name T544
Test name
Test status
Simulation time 730619247 ps
CPU time 23.39 seconds
Started Jul 19 05:44:57 PM PDT 24
Finished Jul 19 05:45:23 PM PDT 24
Peak memory 245876 kb
Host smart-2a758135-d7ea-465b-9bc7-2b3f4b95613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956308163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.956308163
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2384023859
Short name T465
Test name
Test status
Simulation time 1249356288 ps
CPU time 8.63 seconds
Started Jul 19 05:44:57 PM PDT 24
Finished Jul 19 05:45:08 PM PDT 24
Peak memory 247240 kb
Host smart-9c477962-e8da-4abf-b0d0-b9b514507803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384023859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2384023859
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.519980382
Short name T217
Test name
Test status
Simulation time 11738371676 ps
CPU time 194.53 seconds
Started Jul 19 05:44:57 PM PDT 24
Finished Jul 19 05:48:14 PM PDT 24
Peak memory 235156 kb
Host smart-696fbc42-1cde-4963-a16e-b61a8178a3c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519980382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.519980382
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3740630474
Short name T429
Test name
Test status
Simulation time 15224260 ps
CPU time 0.94 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:03 PM PDT 24
Peak memory 212008 kb
Host smart-740bbc05-fdea-440c-bcee-7500c467e790
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740630474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3740630474
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.611386734
Short name T211
Test name
Test status
Simulation time 43293513 ps
CPU time 1.22 seconds
Started Jul 19 05:43:04 PM PDT 24
Finished Jul 19 05:43:07 PM PDT 24
Peak memory 208932 kb
Host smart-3e29a865-2aa1-430e-b51c-1c455ea5713d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611386734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.611386734
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1189852614
Short name T331
Test name
Test status
Simulation time 38625015 ps
CPU time 0.9 seconds
Started Jul 19 05:42:56 PM PDT 24
Finished Jul 19 05:42:57 PM PDT 24
Peak memory 209060 kb
Host smart-230be7f7-fb81-4fac-8fe4-2d752296ed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189852614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1189852614
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1503616763
Short name T433
Test name
Test status
Simulation time 477398274 ps
CPU time 15.06 seconds
Started Jul 19 05:42:58 PM PDT 24
Finished Jul 19 05:43:13 PM PDT 24
Peak memory 226172 kb
Host smart-4d7a412a-5e08-4e33-82d3-2bc3fcbe35d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503616763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1503616763
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2808742149
Short name T620
Test name
Test status
Simulation time 4233731381 ps
CPU time 22.94 seconds
Started Jul 19 05:42:54 PM PDT 24
Finished Jul 19 05:43:18 PM PDT 24
Peak memory 217836 kb
Host smart-d785f312-af7f-4eba-b0bf-08a1f3127823
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808742149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2808742149
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3596535113
Short name T777
Test name
Test status
Simulation time 9931249302 ps
CPU time 69.04 seconds
Started Jul 19 05:42:53 PM PDT 24
Finished Jul 19 05:44:04 PM PDT 24
Peak memory 218984 kb
Host smart-1b899595-c15b-45c4-b644-e6e3b352fd86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596535113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3596535113
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4075704042
Short name T446
Test name
Test status
Simulation time 4080963222 ps
CPU time 8.17 seconds
Started Jul 19 05:43:00 PM PDT 24
Finished Jul 19 05:43:08 PM PDT 24
Peak memory 217876 kb
Host smart-8b005c35-e4fa-454d-acaa-2804e6dcb264
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075704042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4
075704042
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3026173503
Short name T486
Test name
Test status
Simulation time 311637768 ps
CPU time 4.04 seconds
Started Jul 19 05:42:55 PM PDT 24
Finished Jul 19 05:43:00 PM PDT 24
Peak memory 218308 kb
Host smart-d6eebb92-610a-4d8f-a1ff-4aaeb4ef0e88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026173503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3026173503
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1862414763
Short name T679
Test name
Test status
Simulation time 3046751713 ps
CPU time 21.34 seconds
Started Jul 19 05:42:55 PM PDT 24
Finished Jul 19 05:43:18 PM PDT 24
Peak memory 217768 kb
Host smart-eb15f0e0-7ea1-41bb-89d9-9c4cf5290ea2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862414763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1862414763
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1233033990
Short name T59
Test name
Test status
Simulation time 673772550 ps
CPU time 2.85 seconds
Started Jul 19 05:42:55 PM PDT 24
Finished Jul 19 05:42:59 PM PDT 24
Peak memory 217888 kb
Host smart-4c1159a1-b4aa-4bd1-9d59-96006dfaea66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233033990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1233033990
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2576468723
Short name T306
Test name
Test status
Simulation time 20548541793 ps
CPU time 63.51 seconds
Started Jul 19 05:42:55 PM PDT 24
Finished Jul 19 05:44:00 PM PDT 24
Peak memory 277796 kb
Host smart-71814641-43de-41f4-a0b6-1b87172c4ddf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576468723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2576468723
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.458921054
Short name T240
Test name
Test status
Simulation time 4539629788 ps
CPU time 14.86 seconds
Started Jul 19 05:42:54 PM PDT 24
Finished Jul 19 05:43:10 PM PDT 24
Peak memory 251052 kb
Host smart-04e1c7bd-2b6a-4020-8125-4d0760fa3724
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458921054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.458921054
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2531185431
Short name T461
Test name
Test status
Simulation time 53817238 ps
CPU time 3.29 seconds
Started Jul 19 05:43:00 PM PDT 24
Finished Jul 19 05:43:04 PM PDT 24
Peak memory 218336 kb
Host smart-2f6e9076-9203-48c0-8447-c97e6b421b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531185431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2531185431
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1829407256
Short name T56
Test name
Test status
Simulation time 826789620 ps
CPU time 13.11 seconds
Started Jul 19 05:42:53 PM PDT 24
Finished Jul 19 05:43:07 PM PDT 24
Peak memory 214980 kb
Host smart-9ea959cc-627b-425f-9583-82d9897110ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829407256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1829407256
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.4134812046
Short name T80
Test name
Test status
Simulation time 106829522 ps
CPU time 22.85 seconds
Started Jul 19 05:43:08 PM PDT 24
Finished Jul 19 05:43:33 PM PDT 24
Peak memory 281172 kb
Host smart-d1e0bf3b-65d4-4b1a-9921-0c14da149b0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134812046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.4134812046
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1869710101
Short name T221
Test name
Test status
Simulation time 4516149071 ps
CPU time 19.1 seconds
Started Jul 19 05:42:55 PM PDT 24
Finished Jul 19 05:43:15 PM PDT 24
Peak memory 220104 kb
Host smart-8254124c-368a-4160-bb6c-cc9e705ff503
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869710101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1869710101
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3661342775
Short name T235
Test name
Test status
Simulation time 783055106 ps
CPU time 10.19 seconds
Started Jul 19 05:42:57 PM PDT 24
Finished Jul 19 05:43:08 PM PDT 24
Peak memory 226096 kb
Host smart-f48380ed-1e0f-4208-be44-5fc1d8172a5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661342775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3661342775
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2207227634
Short name T668
Test name
Test status
Simulation time 608765157 ps
CPU time 11.49 seconds
Started Jul 19 05:43:00 PM PDT 24
Finished Jul 19 05:43:12 PM PDT 24
Peak memory 226060 kb
Host smart-44eac2ae-0884-4c5b-a93b-9893b0ecdd9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207227634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
207227634
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3176003406
Short name T398
Test name
Test status
Simulation time 256829964 ps
CPU time 9.85 seconds
Started Jul 19 05:42:55 PM PDT 24
Finished Jul 19 05:43:06 PM PDT 24
Peak memory 225508 kb
Host smart-f6b9c03d-4aed-4a32-8991-f1b6d765000f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176003406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3176003406
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2032348905
Short name T284
Test name
Test status
Simulation time 122799703 ps
CPU time 2.39 seconds
Started Jul 19 05:42:53 PM PDT 24
Finished Jul 19 05:42:57 PM PDT 24
Peak memory 214380 kb
Host smart-814b3df2-83ff-4fc0-bb5a-17ab998e51a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032348905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2032348905
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1269477172
Short name T606
Test name
Test status
Simulation time 202092537 ps
CPU time 20.49 seconds
Started Jul 19 05:42:55 PM PDT 24
Finished Jul 19 05:43:16 PM PDT 24
Peak memory 251104 kb
Host smart-4a39f1a9-cc53-4f34-93c9-f9de6fb8a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269477172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1269477172
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.943018539
Short name T206
Test name
Test status
Simulation time 138830992 ps
CPU time 7.74 seconds
Started Jul 19 05:42:57 PM PDT 24
Finished Jul 19 05:43:05 PM PDT 24
Peak memory 251100 kb
Host smart-a2c64a5f-6cf9-4cdd-aa48-e4b023a08a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943018539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.943018539
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.768223620
Short name T841
Test name
Test status
Simulation time 2678335381 ps
CPU time 123.03 seconds
Started Jul 19 05:43:04 PM PDT 24
Finished Jul 19 05:45:09 PM PDT 24
Peak memory 267844 kb
Host smart-c7c9a033-c590-48a1-886b-d08aab552393
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768223620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.768223620
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1588781281
Short name T556
Test name
Test status
Simulation time 39134884 ps
CPU time 1.07 seconds
Started Jul 19 05:42:53 PM PDT 24
Finished Jul 19 05:42:55 PM PDT 24
Peak memory 213080 kb
Host smart-2be40f1b-72f2-4dc8-aff9-7054693275ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588781281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1588781281
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2234220601
Short name T832
Test name
Test status
Simulation time 41773739 ps
CPU time 0.97 seconds
Started Jul 19 05:45:04 PM PDT 24
Finished Jul 19 05:45:06 PM PDT 24
Peak memory 208984 kb
Host smart-ada4e9b2-421a-4ebc-8078-daae36b73d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234220601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2234220601
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.206674720
Short name T430
Test name
Test status
Simulation time 3443740051 ps
CPU time 13.75 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:17 PM PDT 24
Peak memory 219080 kb
Host smart-5ce2e118-e394-4f78-aff9-c828785bce2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206674720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.206674720
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1427703413
Short name T27
Test name
Test status
Simulation time 1406680707 ps
CPU time 4.49 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:08 PM PDT 24
Peak memory 217588 kb
Host smart-a2f6407c-2023-45fb-97d4-a5240140315e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427703413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1427703413
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.234990348
Short name T643
Test name
Test status
Simulation time 959418164 ps
CPU time 3.34 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:06 PM PDT 24
Peak memory 218360 kb
Host smart-600ee6ee-a639-4fe0-8024-932433673b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234990348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.234990348
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1178921789
Short name T399
Test name
Test status
Simulation time 344977469 ps
CPU time 13.09 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:15 PM PDT 24
Peak memory 226172 kb
Host smart-0c333ed2-de75-40c9-b0b7-3780cea0dcde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178921789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1178921789
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.444514465
Short name T819
Test name
Test status
Simulation time 1115367971 ps
CPU time 7.72 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:11 PM PDT 24
Peak memory 226236 kb
Host smart-8cc26c1b-4e3a-4caf-9609-d6dc277ee276
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444514465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.444514465
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3113662399
Short name T395
Test name
Test status
Simulation time 3026546986 ps
CPU time 10.79 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:13 PM PDT 24
Peak memory 218380 kb
Host smart-072beb59-8f17-4aba-a66a-0453e0d4a4f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113662399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3113662399
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1257052977
Short name T196
Test name
Test status
Simulation time 1452265007 ps
CPU time 9.71 seconds
Started Jul 19 05:45:08 PM PDT 24
Finished Jul 19 05:45:19 PM PDT 24
Peak memory 218436 kb
Host smart-9b19d446-0857-4b93-a350-cd646a2d2ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257052977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1257052977
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.24988864
Short name T358
Test name
Test status
Simulation time 1169969565 ps
CPU time 6.31 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:10 PM PDT 24
Peak memory 217788 kb
Host smart-c1b0147b-3404-4d59-b3ea-f2d8fab137d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24988864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.24988864
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2655723845
Short name T328
Test name
Test status
Simulation time 882992372 ps
CPU time 24.62 seconds
Started Jul 19 05:45:05 PM PDT 24
Finished Jul 19 05:45:30 PM PDT 24
Peak memory 251108 kb
Host smart-48833807-2dcf-47a6-a0ea-0380341875e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655723845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2655723845
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.182607948
Short name T810
Test name
Test status
Simulation time 1695682915 ps
CPU time 8.08 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:10 PM PDT 24
Peak memory 251116 kb
Host smart-d43cb7a4-32df-4f06-9ac4-e6e112e52489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182607948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.182607948
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2568468320
Short name T169
Test name
Test status
Simulation time 25859304397 ps
CPU time 187.08 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:48:09 PM PDT 24
Peak memory 255252 kb
Host smart-0765c2c2-5a73-4620-a3f4-af7c82547701
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568468320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2568468320
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2103920105
Short name T70
Test name
Test status
Simulation time 59017304847 ps
CPU time 328.23 seconds
Started Jul 19 05:45:08 PM PDT 24
Finished Jul 19 05:50:37 PM PDT 24
Peak memory 267640 kb
Host smart-1f62f7fc-48b6-420e-8c61-c1beabe35bbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2103920105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2103920105
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3413980199
Short name T449
Test name
Test status
Simulation time 46687416 ps
CPU time 0.86 seconds
Started Jul 19 05:45:03 PM PDT 24
Finished Jul 19 05:45:05 PM PDT 24
Peak memory 208276 kb
Host smart-2e8bc434-dbf6-43dd-8d7d-8038fe97002a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413980199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3413980199
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.4112305466
Short name T489
Test name
Test status
Simulation time 32721904 ps
CPU time 1.16 seconds
Started Jul 19 05:45:04 PM PDT 24
Finished Jul 19 05:45:06 PM PDT 24
Peak memory 209104 kb
Host smart-bcf7fd54-4eae-43e5-93ff-fadd4168e0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112305466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.4112305466
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2321153052
Short name T700
Test name
Test status
Simulation time 428735148 ps
CPU time 16.73 seconds
Started Jul 19 05:45:08 PM PDT 24
Finished Jul 19 05:45:25 PM PDT 24
Peak memory 218304 kb
Host smart-64ee9c18-ad70-46cb-9fd1-382fd7e0bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321153052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2321153052
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3740510691
Short name T689
Test name
Test status
Simulation time 286707476 ps
CPU time 2.26 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:06 PM PDT 24
Peak memory 217232 kb
Host smart-399dabba-14e3-4bdf-a5d5-df6cd89b590d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740510691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3740510691
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3093402365
Short name T571
Test name
Test status
Simulation time 104041909 ps
CPU time 3.49 seconds
Started Jul 19 05:45:02 PM PDT 24
Finished Jul 19 05:45:07 PM PDT 24
Peak memory 218304 kb
Host smart-10ed01de-9eb0-474d-9b9f-f40c6c48feb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093402365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3093402365
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2749450444
Short name T435
Test name
Test status
Simulation time 304159459 ps
CPU time 9.81 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:13 PM PDT 24
Peak memory 219004 kb
Host smart-1e9ad248-4800-46d5-a129-dc2fbeb3f63f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749450444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2749450444
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.311148909
Short name T510
Test name
Test status
Simulation time 502593316 ps
CPU time 17.46 seconds
Started Jul 19 05:45:02 PM PDT 24
Finished Jul 19 05:45:21 PM PDT 24
Peak memory 226108 kb
Host smart-ef76315a-dd4f-406c-87ff-9e917a85185e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311148909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.311148909
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.889137044
Short name T648
Test name
Test status
Simulation time 287226546 ps
CPU time 9.2 seconds
Started Jul 19 05:44:59 PM PDT 24
Finished Jul 19 05:45:10 PM PDT 24
Peak memory 218264 kb
Host smart-0e552237-d39c-4582-88d6-595753c354ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889137044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.889137044
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.943479877
Short name T853
Test name
Test status
Simulation time 984593074 ps
CPU time 9.87 seconds
Started Jul 19 05:45:02 PM PDT 24
Finished Jul 19 05:45:14 PM PDT 24
Peak memory 218436 kb
Host smart-77f865f5-f95e-4b7c-98da-e86469fa2365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943479877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.943479877
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.388499230
Short name T391
Test name
Test status
Simulation time 36206011 ps
CPU time 2.28 seconds
Started Jul 19 05:45:00 PM PDT 24
Finished Jul 19 05:45:05 PM PDT 24
Peak memory 217868 kb
Host smart-617abb87-c0cb-4068-b814-30ebb766d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388499230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.388499230
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.99293761
Short name T365
Test name
Test status
Simulation time 1038095552 ps
CPU time 29.76 seconds
Started Jul 19 05:45:03 PM PDT 24
Finished Jul 19 05:45:34 PM PDT 24
Peak memory 247192 kb
Host smart-74caf0a5-aef0-4302-95de-ff24e3a833f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99293761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.99293761
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1335056323
Short name T321
Test name
Test status
Simulation time 370814834 ps
CPU time 8.12 seconds
Started Jul 19 05:45:08 PM PDT 24
Finished Jul 19 05:45:17 PM PDT 24
Peak memory 250568 kb
Host smart-310bca34-2b1f-4d3b-8a45-71c65ec119ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335056323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1335056323
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3452716153
Short name T22
Test name
Test status
Simulation time 8745195244 ps
CPU time 119.59 seconds
Started Jul 19 05:45:02 PM PDT 24
Finished Jul 19 05:47:03 PM PDT 24
Peak memory 267508 kb
Host smart-353a558c-f7b1-43d7-a564-ccb0e32499e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452716153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3452716153
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1699228081
Short name T133
Test name
Test status
Simulation time 51284973671 ps
CPU time 610.29 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:55:13 PM PDT 24
Peak memory 316812 kb
Host smart-6904526c-d8ff-4d61-8ac3-93cc5f2d7425
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1699228081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1699228081
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1798001214
Short name T800
Test name
Test status
Simulation time 53683916 ps
CPU time 0.86 seconds
Started Jul 19 05:45:01 PM PDT 24
Finished Jul 19 05:45:04 PM PDT 24
Peak memory 212032 kb
Host smart-ead1efcc-6cd7-4719-ada0-83ee39441a54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798001214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1798001214
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1084252023
Short name T258
Test name
Test status
Simulation time 14845077 ps
CPU time 1.09 seconds
Started Jul 19 05:45:13 PM PDT 24
Finished Jul 19 05:45:15 PM PDT 24
Peak memory 208952 kb
Host smart-d30cfd11-4ece-4b33-ad36-ffad9551e630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084252023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1084252023
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3968921882
Short name T249
Test name
Test status
Simulation time 377215073 ps
CPU time 10.42 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:22 PM PDT 24
Peak memory 218348 kb
Host smart-2fbe040a-830d-4887-bd11-0dfddd46a8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968921882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3968921882
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2136161140
Short name T636
Test name
Test status
Simulation time 1025060000 ps
CPU time 3.62 seconds
Started Jul 19 05:45:12 PM PDT 24
Finished Jul 19 05:45:17 PM PDT 24
Peak memory 217320 kb
Host smart-12258b57-1f3d-4780-956a-bdaf89984137
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136161140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2136161140
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.567309267
Short name T676
Test name
Test status
Simulation time 70987311 ps
CPU time 2.76 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:14 PM PDT 24
Peak memory 222336 kb
Host smart-fa911e60-384c-4eee-bec6-2b80a73bcaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567309267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.567309267
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3651232865
Short name T802
Test name
Test status
Simulation time 644600210 ps
CPU time 14.72 seconds
Started Jul 19 05:45:09 PM PDT 24
Finished Jul 19 05:45:24 PM PDT 24
Peak memory 218384 kb
Host smart-f5eb69f9-e36e-4f4f-a804-92cef2b444c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651232865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3651232865
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2243450917
Short name T685
Test name
Test status
Simulation time 875246630 ps
CPU time 12.8 seconds
Started Jul 19 05:45:12 PM PDT 24
Finished Jul 19 05:45:26 PM PDT 24
Peak memory 226124 kb
Host smart-e1ede1b7-0193-42d0-93a1-fc5414935308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243450917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2243450917
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3606313070
Short name T762
Test name
Test status
Simulation time 320381241 ps
CPU time 10.6 seconds
Started Jul 19 05:45:15 PM PDT 24
Finished Jul 19 05:45:26 PM PDT 24
Peak memory 226064 kb
Host smart-db330700-396c-4b9c-acdf-8eeafef50375
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606313070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3606313070
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.486600344
Short name T660
Test name
Test status
Simulation time 6274011407 ps
CPU time 8.67 seconds
Started Jul 19 05:45:09 PM PDT 24
Finished Jul 19 05:45:19 PM PDT 24
Peak memory 226212 kb
Host smart-4dbef99d-bd44-4dbf-b477-33de1dc4cad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486600344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.486600344
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2681366345
Short name T422
Test name
Test status
Simulation time 38171497 ps
CPU time 2.43 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:14 PM PDT 24
Peak memory 217788 kb
Host smart-77c64863-0810-432f-a9c4-c1363749ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681366345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2681366345
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1373102667
Short name T268
Test name
Test status
Simulation time 299578485 ps
CPU time 25.92 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:37 PM PDT 24
Peak memory 251108 kb
Host smart-07d39c1b-4ad7-401e-af23-24091074d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373102667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1373102667
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1743970104
Short name T818
Test name
Test status
Simulation time 49130811 ps
CPU time 6.5 seconds
Started Jul 19 05:45:11 PM PDT 24
Finished Jul 19 05:45:18 PM PDT 24
Peak memory 247380 kb
Host smart-079e643c-5be3-42b5-91a3-13a5e0816b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743970104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1743970104
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1884021179
Short name T24
Test name
Test status
Simulation time 7316462142 ps
CPU time 250.39 seconds
Started Jul 19 05:45:11 PM PDT 24
Finished Jul 19 05:49:22 PM PDT 24
Peak memory 283924 kb
Host smart-b99beaf8-990d-4240-a286-6b53643d1ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884021179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1884021179
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3999534964
Short name T368
Test name
Test status
Simulation time 124269517 ps
CPU time 0.99 seconds
Started Jul 19 05:45:09 PM PDT 24
Finished Jul 19 05:45:11 PM PDT 24
Peak memory 211948 kb
Host smart-c10bd82f-edc9-44f4-977a-f3c7362141be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999534964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3999534964
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3774171429
Short name T609
Test name
Test status
Simulation time 76623690 ps
CPU time 1.13 seconds
Started Jul 19 05:45:12 PM PDT 24
Finished Jul 19 05:45:14 PM PDT 24
Peak memory 209008 kb
Host smart-d94a5a74-99ce-45f6-9b9f-a1a0bdbd850d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774171429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3774171429
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3198064756
Short name T34
Test name
Test status
Simulation time 619517349 ps
CPU time 13.49 seconds
Started Jul 19 05:45:12 PM PDT 24
Finished Jul 19 05:45:26 PM PDT 24
Peak memory 218372 kb
Host smart-146d1494-07e6-4feb-8541-d453d8beab0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198064756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3198064756
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2935450297
Short name T538
Test name
Test status
Simulation time 874867088 ps
CPU time 21.84 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:33 PM PDT 24
Peak memory 217516 kb
Host smart-d2ffe2ce-2924-4ebc-a5dc-6a2bbc67e2c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935450297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2935450297
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2598308223
Short name T540
Test name
Test status
Simulation time 291511124 ps
CPU time 3.34 seconds
Started Jul 19 05:45:13 PM PDT 24
Finished Jul 19 05:45:17 PM PDT 24
Peak memory 218336 kb
Host smart-f7ad593e-9bea-4ef6-9303-d55fcb4339ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598308223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2598308223
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2432930285
Short name T405
Test name
Test status
Simulation time 404620319 ps
CPU time 12.43 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:24 PM PDT 24
Peak memory 226068 kb
Host smart-622c054e-7418-41d0-b881-1a58b5a60b5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432930285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2432930285
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1139234603
Short name T605
Test name
Test status
Simulation time 226789468 ps
CPU time 7.49 seconds
Started Jul 19 05:45:09 PM PDT 24
Finished Jul 19 05:45:18 PM PDT 24
Peak memory 218316 kb
Host smart-68ba9272-0b23-4079-b2df-c145ac403161
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139234603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1139234603
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.990569012
Short name T733
Test name
Test status
Simulation time 278414194 ps
CPU time 7.51 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:18 PM PDT 24
Peak memory 225436 kb
Host smart-6c8e50dd-a949-4226-a2c7-b8874035bea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990569012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.990569012
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3805835161
Short name T362
Test name
Test status
Simulation time 67125723 ps
CPU time 3.68 seconds
Started Jul 19 05:45:09 PM PDT 24
Finished Jul 19 05:45:14 PM PDT 24
Peak memory 217756 kb
Host smart-9c67c54c-f6cf-4749-a56d-db817225cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805835161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3805835161
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2937093689
Short name T73
Test name
Test status
Simulation time 422954224 ps
CPU time 26.92 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:38 PM PDT 24
Peak memory 251108 kb
Host smart-cbffcf30-a97a-429c-8b7a-f28467e8340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937093689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2937093689
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1576517697
Short name T434
Test name
Test status
Simulation time 256298386 ps
CPU time 7.38 seconds
Started Jul 19 05:45:11 PM PDT 24
Finished Jul 19 05:45:20 PM PDT 24
Peak memory 242920 kb
Host smart-d8f633c5-6910-427f-9cd8-3213599abce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576517697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1576517697
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.402177792
Short name T229
Test name
Test status
Simulation time 5199266001 ps
CPU time 123.63 seconds
Started Jul 19 05:45:09 PM PDT 24
Finished Jul 19 05:47:13 PM PDT 24
Peak memory 283932 kb
Host smart-ddf5568e-8e1c-45a7-a119-15a0b94d2891
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402177792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.402177792
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3434406323
Short name T718
Test name
Test status
Simulation time 56295738 ps
CPU time 0.99 seconds
Started Jul 19 05:45:13 PM PDT 24
Finished Jul 19 05:45:15 PM PDT 24
Peak memory 217768 kb
Host smart-2906e9ce-a4bd-47aa-a50c-bf118d89fa3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434406323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3434406323
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2943087259
Short name T265
Test name
Test status
Simulation time 39734476 ps
CPU time 0.86 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:45:29 PM PDT 24
Peak memory 208796 kb
Host smart-445663fe-4d7c-4006-bff3-b161f386a2e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943087259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2943087259
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1165077455
Short name T707
Test name
Test status
Simulation time 533148548 ps
CPU time 12.45 seconds
Started Jul 19 05:45:11 PM PDT 24
Finished Jul 19 05:45:24 PM PDT 24
Peak memory 226168 kb
Host smart-0c14cec5-20da-48dd-a995-e54d87d773b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165077455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1165077455
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1841988829
Short name T737
Test name
Test status
Simulation time 879729357 ps
CPU time 8.64 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:20 PM PDT 24
Peak memory 217184 kb
Host smart-2bab70b5-6007-4b5c-b7ae-b0f1bda25a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841988829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1841988829
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1677369125
Short name T420
Test name
Test status
Simulation time 171384568 ps
CPU time 3.09 seconds
Started Jul 19 05:45:13 PM PDT 24
Finished Jul 19 05:45:17 PM PDT 24
Peak memory 222860 kb
Host smart-8a19bfb1-4507-4f8a-a3d7-30370e4271c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677369125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1677369125
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3509862207
Short name T348
Test name
Test status
Simulation time 1019099258 ps
CPU time 12.98 seconds
Started Jul 19 05:45:23 PM PDT 24
Finished Jul 19 05:45:36 PM PDT 24
Peak memory 226048 kb
Host smart-d458f614-d109-4f90-b6a4-1e29b1168f14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509862207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3509862207
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.4250518084
Short name T85
Test name
Test status
Simulation time 585772529 ps
CPU time 7.03 seconds
Started Jul 19 05:45:09 PM PDT 24
Finished Jul 19 05:45:17 PM PDT 24
Peak memory 218284 kb
Host smart-a605aaad-8b3f-4873-93ec-a49929b5c2b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250518084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
4250518084
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.994531155
Short name T255
Test name
Test status
Simulation time 528936490 ps
CPU time 11.25 seconds
Started Jul 19 05:45:11 PM PDT 24
Finished Jul 19 05:45:23 PM PDT 24
Peak memory 218416 kb
Host smart-3488ee77-d610-4ad1-87f9-0372a38524bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994531155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.994531155
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1474746720
Short name T272
Test name
Test status
Simulation time 432905241 ps
CPU time 2.68 seconds
Started Jul 19 05:45:10 PM PDT 24
Finished Jul 19 05:45:14 PM PDT 24
Peak memory 214768 kb
Host smart-edb620ed-7b40-46aa-b3d7-0a66111237c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474746720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1474746720
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.981123104
Short name T603
Test name
Test status
Simulation time 737120496 ps
CPU time 16.61 seconds
Started Jul 19 05:45:13 PM PDT 24
Finished Jul 19 05:45:31 PM PDT 24
Peak memory 251104 kb
Host smart-7e21a410-eac1-4ab6-8883-d986af711d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981123104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.981123104
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.655616577
Short name T354
Test name
Test status
Simulation time 46448981 ps
CPU time 8.81 seconds
Started Jul 19 05:45:11 PM PDT 24
Finished Jul 19 05:45:21 PM PDT 24
Peak memory 251108 kb
Host smart-9a04adbc-fd9d-423b-82f2-f8797737b149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655616577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.655616577
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2835523545
Short name T270
Test name
Test status
Simulation time 3429206153 ps
CPU time 74.13 seconds
Started Jul 19 05:45:24 PM PDT 24
Finished Jul 19 05:46:40 PM PDT 24
Peak memory 251172 kb
Host smart-a2fc293d-bb6a-4d07-870d-06420af08ce1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835523545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2835523545
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1893615531
Short name T131
Test name
Test status
Simulation time 25611831809 ps
CPU time 244.6 seconds
Started Jul 19 05:45:24 PM PDT 24
Finished Jul 19 05:49:31 PM PDT 24
Peak memory 284128 kb
Host smart-bec28363-d62c-4449-b34d-1b1f6145198e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1893615531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1893615531
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2412791559
Short name T408
Test name
Test status
Simulation time 14932248 ps
CPU time 1.11 seconds
Started Jul 19 05:45:08 PM PDT 24
Finished Jul 19 05:45:10 PM PDT 24
Peak memory 211864 kb
Host smart-e9a69793-6b7d-4f72-8b73-3f558c26c7a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412791559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2412791559
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1391164254
Short name T332
Test name
Test status
Simulation time 25737302 ps
CPU time 1.03 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:28 PM PDT 24
Peak memory 209064 kb
Host smart-17f0a190-c605-4c85-a415-c5b59deaa13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391164254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1391164254
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1522048775
Short name T205
Test name
Test status
Simulation time 1276698936 ps
CPU time 12.53 seconds
Started Jul 19 05:45:23 PM PDT 24
Finished Jul 19 05:45:37 PM PDT 24
Peak memory 218260 kb
Host smart-892662b2-e2c8-4ce1-b6b8-20d6b7d5350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522048775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1522048775
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2923668355
Short name T628
Test name
Test status
Simulation time 388668281 ps
CPU time 10.2 seconds
Started Jul 19 05:45:23 PM PDT 24
Finished Jul 19 05:45:34 PM PDT 24
Peak memory 217372 kb
Host smart-66e8b023-9976-433c-b054-febcd39111c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923668355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2923668355
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1678699040
Short name T212
Test name
Test status
Simulation time 276858358 ps
CPU time 3.13 seconds
Started Jul 19 05:45:24 PM PDT 24
Finished Jul 19 05:45:28 PM PDT 24
Peak memory 218352 kb
Host smart-3acb420f-c67f-4ff0-bc22-9c599b67ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678699040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1678699040
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2270036941
Short name T334
Test name
Test status
Simulation time 1343694009 ps
CPU time 20.66 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:47 PM PDT 24
Peak memory 226164 kb
Host smart-fbece0ec-7d74-42b1-a4e8-1be4a1c31425
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270036941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2270036941
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.754385819
Short name T654
Test name
Test status
Simulation time 470053048 ps
CPU time 12.69 seconds
Started Jul 19 05:45:27 PM PDT 24
Finished Jul 19 05:45:42 PM PDT 24
Peak memory 226076 kb
Host smart-a2a1eb92-cec4-4a97-a16b-13ec12322461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754385819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.754385819
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1623734497
Short name T218
Test name
Test status
Simulation time 568624284 ps
CPU time 9.19 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:37 PM PDT 24
Peak memory 218308 kb
Host smart-aaaddaa9-a90f-4e33-aa66-40a64e52980e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623734497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1623734497
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2697051919
Short name T375
Test name
Test status
Simulation time 361727986 ps
CPU time 13.15 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:41 PM PDT 24
Peak memory 226168 kb
Host smart-e24fcb59-3d77-4510-9952-95b531ead9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697051919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2697051919
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.574161749
Short name T550
Test name
Test status
Simulation time 35141053 ps
CPU time 1.65 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:29 PM PDT 24
Peak memory 217784 kb
Host smart-e49d6c8e-69c9-46c2-8a7e-4d78d1224feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574161749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.574161749
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.402276665
Short name T164
Test name
Test status
Simulation time 282129856 ps
CPU time 19.89 seconds
Started Jul 19 05:45:24 PM PDT 24
Finished Jul 19 05:45:46 PM PDT 24
Peak memory 251088 kb
Host smart-d1ee82ac-1e50-40b2-8b39-90fd407e47fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402276665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.402276665
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.999757561
Short name T748
Test name
Test status
Simulation time 326798280 ps
CPU time 4.35 seconds
Started Jul 19 05:45:29 PM PDT 24
Finished Jul 19 05:45:34 PM PDT 24
Peak memory 218372 kb
Host smart-ec310759-a0f4-46bf-84e9-f408aff58e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999757561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.999757561
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1045853153
Short name T525
Test name
Test status
Simulation time 4244381704 ps
CPU time 61 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:46:30 PM PDT 24
Peak memory 218180 kb
Host smart-1f91342a-86cb-4d6d-89b4-f7010f9bae08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045853153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1045853153
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1357425257
Short name T97
Test name
Test status
Simulation time 74546266448 ps
CPU time 786.72 seconds
Started Jul 19 05:45:24 PM PDT 24
Finished Jul 19 05:58:33 PM PDT 24
Peak memory 284044 kb
Host smart-1a1fcaf7-2a6d-46a8-a74b-c51f32a95dfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1357425257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1357425257
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.232984249
Short name T319
Test name
Test status
Simulation time 48654093 ps
CPU time 0.89 seconds
Started Jul 19 05:45:22 PM PDT 24
Finished Jul 19 05:45:24 PM PDT 24
Peak memory 211912 kb
Host smart-b301a084-944c-41ec-916c-ea36bbb27560
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232984249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.232984249
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.4275999257
Short name T612
Test name
Test status
Simulation time 277361376 ps
CPU time 1.42 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:29 PM PDT 24
Peak memory 209084 kb
Host smart-89cd2b68-faad-4684-a343-aba5eead1481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275999257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.4275999257
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.669881324
Short name T791
Test name
Test status
Simulation time 1053330017 ps
CPU time 10.78 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:38 PM PDT 24
Peak memory 218348 kb
Host smart-a1a7fe67-37e9-4b16-8b99-205ad7ee1d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669881324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.669881324
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.421948513
Short name T548
Test name
Test status
Simulation time 991907373 ps
CPU time 8.91 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:45:38 PM PDT 24
Peak memory 217472 kb
Host smart-ac8969b1-c946-4253-9f02-f747563b88cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421948513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.421948513
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1972928770
Short name T305
Test name
Test status
Simulation time 46915910 ps
CPU time 2.62 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:30 PM PDT 24
Peak memory 218368 kb
Host smart-0bd8805b-015a-48e5-82c6-4a7dc3bd6873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972928770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1972928770
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2859068854
Short name T535
Test name
Test status
Simulation time 931047980 ps
CPU time 11.39 seconds
Started Jul 19 05:45:28 PM PDT 24
Finished Jul 19 05:45:41 PM PDT 24
Peak memory 218452 kb
Host smart-bfe8bfc6-7f2e-455b-8565-425440bd6ee1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859068854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2859068854
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.152142213
Short name T720
Test name
Test status
Simulation time 600594677 ps
CPU time 9.71 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:37 PM PDT 24
Peak memory 226048 kb
Host smart-b885d01e-9876-41c6-91e2-2345aa4cafa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152142213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.152142213
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3780167716
Short name T259
Test name
Test status
Simulation time 2281504226 ps
CPU time 20.44 seconds
Started Jul 19 05:45:24 PM PDT 24
Finished Jul 19 05:45:46 PM PDT 24
Peak memory 218384 kb
Host smart-35b6a040-9c10-4bf8-b2ad-293b211f3c28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780167716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3780167716
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1406116576
Short name T837
Test name
Test status
Simulation time 208874875 ps
CPU time 9.25 seconds
Started Jul 19 05:45:23 PM PDT 24
Finished Jul 19 05:45:34 PM PDT 24
Peak memory 225456 kb
Host smart-d06348d6-6520-46fb-8bbb-40fdf73fecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406116576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1406116576
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2548906122
Short name T317
Test name
Test status
Simulation time 24140818 ps
CPU time 1.32 seconds
Started Jul 19 05:45:24 PM PDT 24
Finished Jul 19 05:45:26 PM PDT 24
Peak memory 217788 kb
Host smart-6125c7cc-6564-4d2e-87b0-fd7ef4d10a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548906122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2548906122
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.743155321
Short name T241
Test name
Test status
Simulation time 351993231 ps
CPU time 29.47 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:56 PM PDT 24
Peak memory 251132 kb
Host smart-242e7903-7eab-4c06-835b-1710f5403e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743155321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.743155321
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3267010333
Short name T342
Test name
Test status
Simulation time 88782081 ps
CPU time 6.43 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:33 PM PDT 24
Peak memory 246664 kb
Host smart-e3ba94a1-e08b-4694-9b50-ab646c11aac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267010333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3267010333
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.64167948
Short name T596
Test name
Test status
Simulation time 5860298842 ps
CPU time 98.45 seconds
Started Jul 19 05:45:23 PM PDT 24
Finished Jul 19 05:47:03 PM PDT 24
Peak memory 251152 kb
Host smart-14253ca8-97cc-4fb8-9ab3-3ae856d13ad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64167948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.lc_ctrl_stress_all.64167948
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1431795871
Short name T322
Test name
Test status
Simulation time 16072566 ps
CPU time 1.07 seconds
Started Jul 19 05:45:23 PM PDT 24
Finished Jul 19 05:45:25 PM PDT 24
Peak memory 211960 kb
Host smart-5f8e3f93-9a39-4b21-8b1a-65a6b0cec915
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431795871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1431795871
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1733381649
Short name T78
Test name
Test status
Simulation time 145187527 ps
CPU time 1.07 seconds
Started Jul 19 05:45:28 PM PDT 24
Finished Jul 19 05:45:30 PM PDT 24
Peak memory 208980 kb
Host smart-bc5858a0-87be-4ad4-a71d-b14639e4e76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733381649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1733381649
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2174595708
Short name T247
Test name
Test status
Simulation time 298055068 ps
CPU time 10.43 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:45:39 PM PDT 24
Peak memory 218448 kb
Host smart-22553531-c9f5-4da5-961c-6caf96c6253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174595708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2174595708
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.999839741
Short name T325
Test name
Test status
Simulation time 2105960736 ps
CPU time 11.97 seconds
Started Jul 19 05:45:29 PM PDT 24
Finished Jul 19 05:45:42 PM PDT 24
Peak memory 217192 kb
Host smart-8ce914a6-48e8-4afd-ada6-f4acfe923eb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999839741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.999839741
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2850279528
Short name T675
Test name
Test status
Simulation time 34551876 ps
CPU time 2.14 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:40 PM PDT 24
Peak memory 218344 kb
Host smart-6569d9f6-e8ed-42ae-9ea6-02c816793996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850279528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2850279528
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1316713101
Short name T309
Test name
Test status
Simulation time 1295367487 ps
CPU time 14.82 seconds
Started Jul 19 05:45:30 PM PDT 24
Finished Jul 19 05:45:46 PM PDT 24
Peak memory 226168 kb
Host smart-18c0b3a5-000b-413a-960c-47ea66801fe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316713101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1316713101
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2373944660
Short name T743
Test name
Test status
Simulation time 1752816460 ps
CPU time 11.64 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:39 PM PDT 24
Peak memory 226064 kb
Host smart-9f0249ba-e6d0-4973-a6f4-951b247606bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373944660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2373944660
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.29482969
Short name T250
Test name
Test status
Simulation time 1507537029 ps
CPU time 8.97 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:45:38 PM PDT 24
Peak memory 218256 kb
Host smart-d7d4d160-0e28-4012-a16c-e524b0571f4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29482969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.29482969
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1708962564
Short name T519
Test name
Test status
Simulation time 309997614 ps
CPU time 11.57 seconds
Started Jul 19 05:45:30 PM PDT 24
Finished Jul 19 05:45:42 PM PDT 24
Peak memory 226172 kb
Host smart-640a7737-eb56-4ff9-bc43-bc88d133cf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708962564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1708962564
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2373050397
Short name T260
Test name
Test status
Simulation time 56546344 ps
CPU time 2.49 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:30 PM PDT 24
Peak memory 214352 kb
Host smart-e7733cde-de37-47b5-8f52-acac84abcb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373050397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2373050397
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2212778301
Short name T783
Test name
Test status
Simulation time 251901185 ps
CPU time 32.17 seconds
Started Jul 19 05:45:23 PM PDT 24
Finished Jul 19 05:45:56 PM PDT 24
Peak memory 251180 kb
Host smart-eed5027a-fbca-4411-8c30-2c9c1bf119b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212778301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2212778301
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3711177421
Short name T414
Test name
Test status
Simulation time 87182240 ps
CPU time 7.73 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:34 PM PDT 24
Peak memory 246672 kb
Host smart-ec17e82c-ca65-4378-b5a2-ee0bba9fc237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711177421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3711177421
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4216626700
Short name T601
Test name
Test status
Simulation time 64139802928 ps
CPU time 212.18 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:49:00 PM PDT 24
Peak memory 284012 kb
Host smart-c39fb07a-3d4b-4cec-a6fa-41428ca53b37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216626700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4216626700
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1132561302
Short name T537
Test name
Test status
Simulation time 46357199 ps
CPU time 0.87 seconds
Started Jul 19 05:45:24 PM PDT 24
Finished Jul 19 05:45:26 PM PDT 24
Peak memory 211964 kb
Host smart-b2df20ea-7858-47cd-b320-5f98d5286454
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132561302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1132561302
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.4041262420
Short name T815
Test name
Test status
Simulation time 54686887 ps
CPU time 0.9 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:45:30 PM PDT 24
Peak memory 208944 kb
Host smart-5d023e64-8fb5-4f54-a2c3-878f14c69159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041262420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.4041262420
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2821980281
Short name T849
Test name
Test status
Simulation time 994598379 ps
CPU time 26.98 seconds
Started Jul 19 05:45:25 PM PDT 24
Finished Jul 19 05:45:55 PM PDT 24
Peak memory 218508 kb
Host smart-446bc83b-b3f0-4a47-84ca-13c4064a3494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821980281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2821980281
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1190575762
Short name T6
Test name
Test status
Simulation time 701134907 ps
CPU time 6.57 seconds
Started Jul 19 05:45:29 PM PDT 24
Finished Jul 19 05:45:36 PM PDT 24
Peak memory 217284 kb
Host smart-4366d6a2-ec3d-492c-aea4-2ad880f3ef42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190575762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1190575762
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3927552298
Short name T156
Test name
Test status
Simulation time 201123922 ps
CPU time 2.28 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:45:31 PM PDT 24
Peak memory 218360 kb
Host smart-e9406851-da78-4f05-b47d-7b903c2f8b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927552298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3927552298
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1620796475
Short name T621
Test name
Test status
Simulation time 1310025689 ps
CPU time 10.96 seconds
Started Jul 19 05:45:26 PM PDT 24
Finished Jul 19 05:45:40 PM PDT 24
Peak memory 226164 kb
Host smart-ca8b57db-ded6-4443-a508-8713b26bee52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620796475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1620796475
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2479539363
Short name T89
Test name
Test status
Simulation time 1333707357 ps
CPU time 16.84 seconds
Started Jul 19 05:45:31 PM PDT 24
Finished Jul 19 05:45:49 PM PDT 24
Peak memory 226144 kb
Host smart-619cb695-fc87-437f-9f90-9ee69f394a44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479539363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2479539363
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3337584456
Short name T458
Test name
Test status
Simulation time 456849091 ps
CPU time 10.37 seconds
Started Jul 19 05:45:28 PM PDT 24
Finished Jul 19 05:45:40 PM PDT 24
Peak memory 218308 kb
Host smart-7c61fc31-fd3a-4ed7-965f-9c806f9ef928
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337584456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3337584456
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.4134080456
Short name T230
Test name
Test status
Simulation time 388664457 ps
CPU time 11.14 seconds
Started Jul 19 05:45:31 PM PDT 24
Finished Jul 19 05:45:43 PM PDT 24
Peak memory 224996 kb
Host smart-a9115d0d-5024-45ef-b451-94ceb6fcf9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134080456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4134080456
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1526131344
Short name T710
Test name
Test status
Simulation time 82141081 ps
CPU time 2.79 seconds
Started Jul 19 05:45:27 PM PDT 24
Finished Jul 19 05:45:32 PM PDT 24
Peak memory 214604 kb
Host smart-2d2071fc-280f-4b08-82ad-c08fdb788b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526131344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1526131344
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3506631853
Short name T776
Test name
Test status
Simulation time 354469853 ps
CPU time 35.56 seconds
Started Jul 19 05:45:31 PM PDT 24
Finished Jul 19 05:46:07 PM PDT 24
Peak memory 250972 kb
Host smart-e50df02c-cdd0-4697-8b3c-5e2745f34be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506631853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3506631853
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2207663439
Short name T546
Test name
Test status
Simulation time 49739975 ps
CPU time 7.53 seconds
Started Jul 19 05:45:28 PM PDT 24
Finished Jul 19 05:45:37 PM PDT 24
Peak memory 251020 kb
Host smart-501b7388-a600-4afb-88b7-d2e668023b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207663439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2207663439
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3998637717
Short name T693
Test name
Test status
Simulation time 7678129999 ps
CPU time 140.42 seconds
Started Jul 19 05:45:30 PM PDT 24
Finished Jul 19 05:47:51 PM PDT 24
Peak memory 271496 kb
Host smart-fea3a82c-b014-4a5d-9e29-61e49811cd6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998637717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3998637717
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.661096792
Short name T856
Test name
Test status
Simulation time 9805501604 ps
CPU time 206.98 seconds
Started Jul 19 05:45:27 PM PDT 24
Finished Jul 19 05:48:56 PM PDT 24
Peak memory 283908 kb
Host smart-a4b69729-7625-4978-89de-c0e09f52c41a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=661096792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.661096792
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.435115582
Short name T801
Test name
Test status
Simulation time 44185055 ps
CPU time 0.96 seconds
Started Jul 19 05:45:30 PM PDT 24
Finished Jul 19 05:45:32 PM PDT 24
Peak memory 217776 kb
Host smart-c9564e01-7fae-4dcf-9baf-556d32a34923
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435115582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.435115582
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3420699663
Short name T471
Test name
Test status
Simulation time 35719471 ps
CPU time 1.25 seconds
Started Jul 19 05:45:38 PM PDT 24
Finished Jul 19 05:45:41 PM PDT 24
Peak memory 209028 kb
Host smart-eeb0f30d-6e16-4ba2-918d-376d10abec6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420699663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3420699663
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.631181019
Short name T415
Test name
Test status
Simulation time 1259980078 ps
CPU time 10.41 seconds
Started Jul 19 05:45:36 PM PDT 24
Finished Jul 19 05:45:48 PM PDT 24
Peak memory 226144 kb
Host smart-6e238ea6-98c4-4e12-b3d5-0852b69403e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631181019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.631181019
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2299015749
Short name T728
Test name
Test status
Simulation time 130809217 ps
CPU time 1.26 seconds
Started Jul 19 05:45:36 PM PDT 24
Finished Jul 19 05:45:39 PM PDT 24
Peak memory 217120 kb
Host smart-7bcca12d-3e55-481b-ac25-1cf54b765044
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299015749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2299015749
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1235869934
Short name T392
Test name
Test status
Simulation time 440108374 ps
CPU time 5.13 seconds
Started Jul 19 05:45:28 PM PDT 24
Finished Jul 19 05:45:35 PM PDT 24
Peak memory 218360 kb
Host smart-3485bdd0-f6d8-48ba-bf77-f0804220147a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235869934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1235869934
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.4200331168
Short name T200
Test name
Test status
Simulation time 371484530 ps
CPU time 13.97 seconds
Started Jul 19 05:45:37 PM PDT 24
Finished Jul 19 05:45:53 PM PDT 24
Peak memory 226080 kb
Host smart-9a3dbe01-7aca-4e42-acd3-c6d5c067ca9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200331168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.4200331168
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.4206479104
Short name T350
Test name
Test status
Simulation time 1546888285 ps
CPU time 10.33 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:48 PM PDT 24
Peak memory 226116 kb
Host smart-51a88403-ed08-44ce-87f0-a1cefe766949
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206479104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
4206479104
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1062872801
Short name T590
Test name
Test status
Simulation time 345719990 ps
CPU time 10.3 seconds
Started Jul 19 05:45:30 PM PDT 24
Finished Jul 19 05:45:40 PM PDT 24
Peak memory 226216 kb
Host smart-85e80fbb-e51b-42d1-ba63-19dee70030e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062872801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1062872801
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2481126486
Short name T522
Test name
Test status
Simulation time 45221524 ps
CPU time 1.45 seconds
Started Jul 19 05:45:27 PM PDT 24
Finished Jul 19 05:45:30 PM PDT 24
Peak memory 217780 kb
Host smart-9d7fc40a-11af-428e-8fc2-2e676b36c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481126486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2481126486
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.575652339
Short name T806
Test name
Test status
Simulation time 443983149 ps
CPU time 18.19 seconds
Started Jul 19 05:45:34 PM PDT 24
Finished Jul 19 05:45:54 PM PDT 24
Peak memory 251028 kb
Host smart-0894289a-7e04-4fbe-8201-329b8d24625e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575652339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.575652339
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1542761842
Short name T473
Test name
Test status
Simulation time 90525551 ps
CPU time 13.01 seconds
Started Jul 19 05:45:27 PM PDT 24
Finished Jul 19 05:45:42 PM PDT 24
Peak memory 244000 kb
Host smart-e3131c30-3b34-4717-9a7c-7f7f64e3c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542761842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1542761842
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.256999868
Short name T222
Test name
Test status
Simulation time 28660948180 ps
CPU time 105.97 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:47:23 PM PDT 24
Peak memory 251172 kb
Host smart-eeebad05-5d88-499d-a753-f26d0580f6bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256999868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.256999868
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.59776057
Short name T138
Test name
Test status
Simulation time 7878497118 ps
CPU time 290 seconds
Started Jul 19 05:45:38 PM PDT 24
Finished Jul 19 05:50:29 PM PDT 24
Peak memory 290068 kb
Host smart-7c6d276a-7742-4e62-b3c9-44e2b059491c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=59776057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.59776057
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2868233894
Short name T836
Test name
Test status
Simulation time 11659352 ps
CPU time 0.95 seconds
Started Jul 19 05:45:31 PM PDT 24
Finished Jul 19 05:45:32 PM PDT 24
Peak memory 212060 kb
Host smart-a043a5b4-41c3-4830-ab96-e570ac4857c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868233894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2868233894
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2584883452
Short name T228
Test name
Test status
Simulation time 108249052 ps
CPU time 0.89 seconds
Started Jul 19 05:43:11 PM PDT 24
Finished Jul 19 05:43:14 PM PDT 24
Peak memory 208976 kb
Host smart-673021a5-45d4-4088-9f25-89c914800e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584883452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2584883452
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2376002880
Short name T191
Test name
Test status
Simulation time 39235955 ps
CPU time 0.91 seconds
Started Jul 19 05:43:08 PM PDT 24
Finished Jul 19 05:43:11 PM PDT 24
Peak memory 208880 kb
Host smart-28ea0738-b299-437d-be0b-81061c9e21f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376002880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2376002880
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3264633995
Short name T453
Test name
Test status
Simulation time 1320448630 ps
CPU time 13.24 seconds
Started Jul 19 05:43:05 PM PDT 24
Finished Jul 19 05:43:19 PM PDT 24
Peak memory 226176 kb
Host smart-012c49e8-118f-480d-a470-ad1175b6d59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264633995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3264633995
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.18448765
Short name T708
Test name
Test status
Simulation time 2923537009 ps
CPU time 6.48 seconds
Started Jul 19 05:43:07 PM PDT 24
Finished Jul 19 05:43:16 PM PDT 24
Peak memory 217648 kb
Host smart-a83b03f1-62b2-4426-ba06-a5bed03897ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18448765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.18448765
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.622345476
Short name T455
Test name
Test status
Simulation time 1268754074 ps
CPU time 23.75 seconds
Started Jul 19 05:43:06 PM PDT 24
Finished Jul 19 05:43:31 PM PDT 24
Peak memory 218428 kb
Host smart-31004b74-5569-4997-906b-1b69cc83ca4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622345476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.622345476
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3201130096
Short name T827
Test name
Test status
Simulation time 2828975199 ps
CPU time 3.17 seconds
Started Jul 19 05:43:06 PM PDT 24
Finished Jul 19 05:43:11 PM PDT 24
Peak memory 217872 kb
Host smart-6f776953-747d-4989-915c-b7de4ff33001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201130096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
201130096
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1737132141
Short name T352
Test name
Test status
Simulation time 3097886370 ps
CPU time 9.37 seconds
Started Jul 19 05:43:06 PM PDT 24
Finished Jul 19 05:43:17 PM PDT 24
Peak memory 223916 kb
Host smart-29cf0f73-2100-4be7-9b1b-0f6edabdb08a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737132141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1737132141
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1674882757
Short name T657
Test name
Test status
Simulation time 1190756203 ps
CPU time 35.81 seconds
Started Jul 19 05:43:08 PM PDT 24
Finished Jul 19 05:43:46 PM PDT 24
Peak memory 217800 kb
Host smart-96fb94a0-ad5a-419c-8b8d-a28e67722dc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674882757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1674882757
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4227283324
Short name T659
Test name
Test status
Simulation time 904987310 ps
CPU time 4.63 seconds
Started Jul 19 05:43:04 PM PDT 24
Finished Jul 19 05:43:10 PM PDT 24
Peak memory 217664 kb
Host smart-ae8c3f53-700e-4ada-ad0d-b60ff510255e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227283324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
4227283324
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.77470030
Short name T799
Test name
Test status
Simulation time 3703229298 ps
CPU time 75.47 seconds
Started Jul 19 05:43:04 PM PDT 24
Finished Jul 19 05:44:21 PM PDT 24
Peak memory 283864 kb
Host smart-977c8a42-5768-4972-97bc-350e72938b60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77470030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
state_failure.77470030
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.838110748
Short name T541
Test name
Test status
Simulation time 1622115167 ps
CPU time 12.78 seconds
Started Jul 19 05:43:05 PM PDT 24
Finished Jul 19 05:43:19 PM PDT 24
Peak memory 250888 kb
Host smart-fe85e9ec-52ef-4367-8726-a56bb4912cd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838110748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.838110748
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.567616377
Short name T197
Test name
Test status
Simulation time 171501814 ps
CPU time 2.8 seconds
Started Jul 19 05:43:04 PM PDT 24
Finished Jul 19 05:43:08 PM PDT 24
Peak memory 218312 kb
Host smart-6e1bb688-5ab2-4f6a-8332-872255b3e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567616377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.567616377
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4047255805
Short name T789
Test name
Test status
Simulation time 1364784547 ps
CPU time 11.32 seconds
Started Jul 19 05:43:05 PM PDT 24
Finished Jul 19 05:43:18 PM PDT 24
Peak memory 217784 kb
Host smart-f6970cbb-6540-4277-853c-dc0c1a93981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047255805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4047255805
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3588754243
Short name T81
Test name
Test status
Simulation time 479718984 ps
CPU time 35.78 seconds
Started Jul 19 05:43:18 PM PDT 24
Finished Jul 19 05:43:56 PM PDT 24
Peak memory 284556 kb
Host smart-bfa31d2d-a00d-4b09-85a3-d335bf14f532
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588754243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3588754243
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3173915899
Short name T294
Test name
Test status
Simulation time 840614220 ps
CPU time 8.55 seconds
Started Jul 19 05:43:06 PM PDT 24
Finished Jul 19 05:43:16 PM PDT 24
Peak memory 226092 kb
Host smart-9dc9fea9-f6e1-4dfd-81cd-fdc1f3c4716f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173915899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3173915899
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.904117020
Short name T847
Test name
Test status
Simulation time 924468020 ps
CPU time 7.22 seconds
Started Jul 19 05:43:04 PM PDT 24
Finished Jul 19 05:43:13 PM PDT 24
Peak memory 226096 kb
Host smart-12732ef8-560c-46a9-986e-972314357952
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904117020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.904117020
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1152270715
Short name T232
Test name
Test status
Simulation time 390813266 ps
CPU time 8.07 seconds
Started Jul 19 05:43:05 PM PDT 24
Finished Jul 19 05:43:15 PM PDT 24
Peak memory 224608 kb
Host smart-deb5e495-bd07-4f0b-86eb-e27744bacaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152270715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1152270715
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2966852153
Short name T276
Test name
Test status
Simulation time 178634988 ps
CPU time 1.91 seconds
Started Jul 19 05:43:07 PM PDT 24
Finished Jul 19 05:43:11 PM PDT 24
Peak memory 217784 kb
Host smart-72e81c07-8e1c-4aee-b071-504ca56e86ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966852153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2966852153
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2311444782
Short name T581
Test name
Test status
Simulation time 394931306 ps
CPU time 17.06 seconds
Started Jul 19 05:43:04 PM PDT 24
Finished Jul 19 05:43:23 PM PDT 24
Peak memory 251108 kb
Host smart-68a6492f-37db-4835-a921-833146cb71f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311444782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2311444782
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2442241525
Short name T529
Test name
Test status
Simulation time 58895727 ps
CPU time 6.8 seconds
Started Jul 19 05:43:03 PM PDT 24
Finished Jul 19 05:43:11 PM PDT 24
Peak memory 242928 kb
Host smart-08badc9e-bac3-477d-99c1-d4c2231b2ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442241525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2442241525
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.220074557
Short name T288
Test name
Test status
Simulation time 1650062897 ps
CPU time 58.27 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:44:15 PM PDT 24
Peak memory 275828 kb
Host smart-1bc90db8-e836-45dd-a69d-ab12f66ca911
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220074557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.220074557
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.53052708
Short name T307
Test name
Test status
Simulation time 58765975 ps
CPU time 1.09 seconds
Started Jul 19 05:43:06 PM PDT 24
Finished Jul 19 05:43:08 PM PDT 24
Peak memory 213024 kb
Host smart-903e48f4-d729-4d11-9bfa-1f34f32d1d1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53052708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_volatile_unlock_smoke.53052708
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1120488639
Short name T701
Test name
Test status
Simulation time 121782824 ps
CPU time 1.01 seconds
Started Jul 19 05:45:34 PM PDT 24
Finished Jul 19 05:45:36 PM PDT 24
Peak memory 208984 kb
Host smart-4ba926e1-8e8e-4d10-b9a5-780b18a2bfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120488639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1120488639
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.69237142
Short name T570
Test name
Test status
Simulation time 387640539 ps
CPU time 17.07 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:55 PM PDT 24
Peak memory 218364 kb
Host smart-3eee0640-1d7a-445c-ab48-d835bb27b0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69237142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.69237142
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3949690717
Short name T600
Test name
Test status
Simulation time 156517737 ps
CPU time 4.79 seconds
Started Jul 19 05:45:36 PM PDT 24
Finished Jul 19 05:45:43 PM PDT 24
Peak memory 217360 kb
Host smart-8e5b04f9-11bf-496d-b173-539e955bb853
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949690717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3949690717
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2127860921
Short name T579
Test name
Test status
Simulation time 42381591 ps
CPU time 2.31 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:39 PM PDT 24
Peak memory 218340 kb
Host smart-d4f2f122-b499-45bf-9a8e-562e87eabfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127860921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2127860921
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1365237885
Short name T257
Test name
Test status
Simulation time 6861530413 ps
CPU time 15.3 seconds
Started Jul 19 05:45:37 PM PDT 24
Finished Jul 19 05:45:54 PM PDT 24
Peak memory 226136 kb
Host smart-2daf0443-0adf-41f2-9d43-ab4af34b8dfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365237885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1365237885
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1763554688
Short name T502
Test name
Test status
Simulation time 456736100 ps
CPU time 11.99 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:49 PM PDT 24
Peak memory 226224 kb
Host smart-0a2a8171-3aaa-4a95-b131-8358d1618b78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763554688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1763554688
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4068359573
Short name T387
Test name
Test status
Simulation time 509670438 ps
CPU time 11.89 seconds
Started Jul 19 05:45:38 PM PDT 24
Finished Jul 19 05:45:51 PM PDT 24
Peak memory 226008 kb
Host smart-c847f8f0-e8e9-494b-8857-2ef36231b443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068359573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4068359573
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3284864228
Short name T166
Test name
Test status
Simulation time 253093774 ps
CPU time 7.87 seconds
Started Jul 19 05:45:38 PM PDT 24
Finished Jul 19 05:45:47 PM PDT 24
Peak memory 224992 kb
Host smart-9781110b-7470-4ada-a3d0-07b96244f5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284864228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3284864228
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1725918343
Short name T803
Test name
Test status
Simulation time 76183824 ps
CPU time 1.51 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:39 PM PDT 24
Peak memory 213892 kb
Host smart-074736af-7cd1-4066-8e17-c912cf05a105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725918343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1725918343
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1622140287
Short name T441
Test name
Test status
Simulation time 227636113 ps
CPU time 18.74 seconds
Started Jul 19 05:45:37 PM PDT 24
Finished Jul 19 05:45:57 PM PDT 24
Peak memory 251112 kb
Host smart-2c1bb125-a118-418a-84db-9c84b07e8b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622140287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1622140287
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2925784728
Short name T210
Test name
Test status
Simulation time 242465055 ps
CPU time 5.74 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:42 PM PDT 24
Peak memory 246936 kb
Host smart-8b1d6ca3-fda6-476c-97b8-aa24380ea787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925784728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2925784728
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1350210825
Short name T279
Test name
Test status
Simulation time 2540710261 ps
CPU time 34.93 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:46:11 PM PDT 24
Peak memory 220304 kb
Host smart-8ed0a8f1-c052-426a-b19c-905d57341e17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350210825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1350210825
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3969516024
Short name T480
Test name
Test status
Simulation time 21825375 ps
CPU time 1.08 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:38 PM PDT 24
Peak memory 212992 kb
Host smart-8b8c2b23-2a6b-4397-aab7-06e0bf8067a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969516024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3969516024
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1859873649
Short name T369
Test name
Test status
Simulation time 27362886 ps
CPU time 1 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 05:45:48 PM PDT 24
Peak memory 209004 kb
Host smart-027dfc15-9043-420f-80cb-219f49cf5289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859873649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1859873649
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2407931167
Short name T736
Test name
Test status
Simulation time 349392736 ps
CPU time 12.42 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:50 PM PDT 24
Peak memory 218320 kb
Host smart-e846e440-13ca-4219-b80b-294cb403772d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407931167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2407931167
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1594554512
Short name T744
Test name
Test status
Simulation time 806772006 ps
CPU time 7.64 seconds
Started Jul 19 05:45:34 PM PDT 24
Finished Jul 19 05:45:42 PM PDT 24
Peak memory 217308 kb
Host smart-ad4da5f2-1c44-43ce-bc93-9d647696c1b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594554512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1594554512
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3961757054
Short name T47
Test name
Test status
Simulation time 289481024 ps
CPU time 2.67 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:39 PM PDT 24
Peak memory 218304 kb
Host smart-60c38eed-ef3e-4be6-9fe6-b4e4b7509a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961757054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3961757054
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2752720655
Short name T324
Test name
Test status
Simulation time 280706872 ps
CPU time 15.46 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:53 PM PDT 24
Peak memory 218380 kb
Host smart-58836bbc-1d72-4149-a054-17dc68f10a58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752720655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2752720655
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1768083706
Short name T825
Test name
Test status
Simulation time 459704486 ps
CPU time 10.18 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 05:45:57 PM PDT 24
Peak memory 226104 kb
Host smart-9dbeec0f-a7d1-47a8-a7e3-983d0b1da476
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768083706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1768083706
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.551510329
Short name T267
Test name
Test status
Simulation time 314076844 ps
CPU time 11.21 seconds
Started Jul 19 05:45:43 PM PDT 24
Finished Jul 19 05:45:56 PM PDT 24
Peak memory 218308 kb
Host smart-a57bd313-e784-436f-892a-49caf4ef4df6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551510329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.551510329
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3758095953
Short name T344
Test name
Test status
Simulation time 1397598676 ps
CPU time 8.94 seconds
Started Jul 19 05:45:37 PM PDT 24
Finished Jul 19 05:45:48 PM PDT 24
Peak memory 226136 kb
Host smart-12394982-4c33-4ed2-9182-d5670023a0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758095953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3758095953
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3620349488
Short name T14
Test name
Test status
Simulation time 34803800 ps
CPU time 2.24 seconds
Started Jul 19 05:45:35 PM PDT 24
Finished Jul 19 05:45:40 PM PDT 24
Peak memory 217780 kb
Host smart-94b5c5f1-337f-4204-8300-5429a7e718c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620349488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3620349488
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2603924979
Short name T750
Test name
Test status
Simulation time 2808074658 ps
CPU time 22.84 seconds
Started Jul 19 05:45:34 PM PDT 24
Finished Jul 19 05:45:59 PM PDT 24
Peak memory 251164 kb
Host smart-b810e1c7-ff8f-4d8c-b0ee-0e7bffd1f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603924979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2603924979
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3723348161
Short name T356
Test name
Test status
Simulation time 643682558 ps
CPU time 3.27 seconds
Started Jul 19 05:45:33 PM PDT 24
Finished Jul 19 05:45:37 PM PDT 24
Peak memory 222284 kb
Host smart-11fbbec7-b61b-48db-8568-595aa3712bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723348161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3723348161
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2331367043
Short name T293
Test name
Test status
Simulation time 11835266439 ps
CPU time 221.65 seconds
Started Jul 19 05:45:42 PM PDT 24
Finished Jul 19 05:49:26 PM PDT 24
Peak memory 276916 kb
Host smart-2aff3d87-98dd-4618-a0d9-d4a908992cc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331367043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2331367043
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.57775884
Short name T152
Test name
Test status
Simulation time 102658564973 ps
CPU time 1839.58 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 06:16:27 PM PDT 24
Peak memory 927892 kb
Host smart-354f978e-4dbf-41b1-99cc-eeedc091fdc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=57775884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.57775884
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.633224294
Short name T159
Test name
Test status
Simulation time 15823577 ps
CPU time 0.92 seconds
Started Jul 19 05:45:34 PM PDT 24
Finished Jul 19 05:45:37 PM PDT 24
Peak memory 211964 kb
Host smart-aadab402-cd3c-4fb8-93c6-6968fc924163
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633224294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.633224294
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1562388129
Short name T79
Test name
Test status
Simulation time 163509655 ps
CPU time 0.94 seconds
Started Jul 19 05:45:41 PM PDT 24
Finished Jul 19 05:45:43 PM PDT 24
Peak memory 208916 kb
Host smart-87ce128f-4dab-4b5a-a409-b89585aa72e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562388129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1562388129
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.4202470851
Short name T437
Test name
Test status
Simulation time 475669787 ps
CPU time 14.08 seconds
Started Jul 19 05:45:45 PM PDT 24
Finished Jul 19 05:46:02 PM PDT 24
Peak memory 218368 kb
Host smart-211f661d-0e3a-4e28-88a7-dd2fbea5c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202470851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4202470851
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.748217256
Short name T698
Test name
Test status
Simulation time 2232426598 ps
CPU time 4.07 seconds
Started Jul 19 05:45:43 PM PDT 24
Finished Jul 19 05:45:49 PM PDT 24
Peak memory 217252 kb
Host smart-7a55bce8-615d-431e-aafe-c76f0ff52502
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748217256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.748217256
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1289321935
Short name T201
Test name
Test status
Simulation time 77085465 ps
CPU time 2.78 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 05:45:50 PM PDT 24
Peak memory 222288 kb
Host smart-fd654ec3-f5ad-4d94-adcd-f2853348e9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289321935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1289321935
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.4224396843
Short name T436
Test name
Test status
Simulation time 403157087 ps
CPU time 12.06 seconds
Started Jul 19 05:45:43 PM PDT 24
Finished Jul 19 05:45:58 PM PDT 24
Peak memory 226112 kb
Host smart-13d6c6ed-fc31-4d8a-aa12-72380f2fd12a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224396843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.4224396843
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2040816634
Short name T374
Test name
Test status
Simulation time 1347625166 ps
CPU time 8.38 seconds
Started Jul 19 05:45:41 PM PDT 24
Finished Jul 19 05:45:51 PM PDT 24
Peak memory 218300 kb
Host smart-36a6edbd-93f7-4e2c-bc61-476db36721b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040816634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2040816634
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.291021472
Short name T462
Test name
Test status
Simulation time 421482225 ps
CPU time 10.57 seconds
Started Jul 19 05:45:49 PM PDT 24
Finished Jul 19 05:46:01 PM PDT 24
Peak memory 226128 kb
Host smart-686bcaa2-448a-43c3-baec-0351d5eabae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291021472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.291021472
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1763479059
Short name T742
Test name
Test status
Simulation time 20873230 ps
CPU time 1.69 seconds
Started Jul 19 05:45:42 PM PDT 24
Finished Jul 19 05:45:46 PM PDT 24
Peak memory 214288 kb
Host smart-a9ab1a63-26ec-422f-a382-ae2fff87aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763479059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1763479059
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2181076607
Short name T237
Test name
Test status
Simulation time 173015563 ps
CPU time 24.68 seconds
Started Jul 19 05:45:43 PM PDT 24
Finished Jul 19 05:46:10 PM PDT 24
Peak memory 246140 kb
Host smart-b6b0afe8-291e-4670-828a-6c085ffec1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181076607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2181076607
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3760624256
Short name T333
Test name
Test status
Simulation time 133547403 ps
CPU time 7.25 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 05:45:54 PM PDT 24
Peak memory 251108 kb
Host smart-b4ec2ba1-3fa6-478a-bcdf-11f3d0f6125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760624256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3760624256
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1503156504
Short name T729
Test name
Test status
Simulation time 1927927152 ps
CPU time 49.46 seconds
Started Jul 19 05:45:42 PM PDT 24
Finished Jul 19 05:46:33 PM PDT 24
Peak memory 271776 kb
Host smart-964e7309-0020-4a2d-8846-49510531d176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503156504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1503156504
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3859643301
Short name T140
Test name
Test status
Simulation time 208939945435 ps
CPU time 1855.41 seconds
Started Jul 19 05:45:42 PM PDT 24
Finished Jul 19 06:16:39 PM PDT 24
Peak memory 349620 kb
Host smart-55eb7ab6-dfcc-4103-9e6e-3109621f890f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3859643301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3859643301
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2520235106
Short name T411
Test name
Test status
Simulation time 13393617 ps
CPU time 1.14 seconds
Started Jul 19 05:45:43 PM PDT 24
Finished Jul 19 05:45:47 PM PDT 24
Peak memory 212108 kb
Host smart-c7e641d8-11ae-40f8-a372-755c79d4228c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520235106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2520235106
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.4000809000
Short name T532
Test name
Test status
Simulation time 54941268 ps
CPU time 1.08 seconds
Started Jul 19 05:45:49 PM PDT 24
Finished Jul 19 05:45:51 PM PDT 24
Peak memory 209128 kb
Host smart-2c7e512e-2830-4454-83b1-1c58126ab92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000809000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4000809000
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3122393934
Short name T617
Test name
Test status
Simulation time 236173147 ps
CPU time 10.07 seconds
Started Jul 19 05:45:42 PM PDT 24
Finished Jul 19 05:45:55 PM PDT 24
Peak memory 226148 kb
Host smart-5136dd9e-bf4f-4078-aa1b-5e3ce0e70139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122393934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3122393934
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1213928334
Short name T584
Test name
Test status
Simulation time 459890071 ps
CPU time 3.88 seconds
Started Jul 19 05:45:45 PM PDT 24
Finished Jul 19 05:45:51 PM PDT 24
Peak memory 217156 kb
Host smart-67f4ddc3-cd17-4766-8630-58c90479bca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213928334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1213928334
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3867581758
Short name T864
Test name
Test status
Simulation time 120210591 ps
CPU time 1.88 seconds
Started Jul 19 05:45:42 PM PDT 24
Finished Jul 19 05:45:47 PM PDT 24
Peak memory 222176 kb
Host smart-28e7e6aa-0227-4690-9b8c-eccf94f8c95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867581758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3867581758
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2272922145
Short name T355
Test name
Test status
Simulation time 339936532 ps
CPU time 13.36 seconds
Started Jul 19 05:45:45 PM PDT 24
Finished Jul 19 05:46:01 PM PDT 24
Peak memory 219160 kb
Host smart-9036ab3e-6e59-4cda-aec0-17b2e232edee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272922145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2272922145
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.430335183
Short name T315
Test name
Test status
Simulation time 668718598 ps
CPU time 16.73 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 05:46:04 PM PDT 24
Peak memory 226104 kb
Host smart-35ff62c6-7951-428e-a77b-17640bb34b30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430335183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.430335183
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1310169294
Short name T281
Test name
Test status
Simulation time 780323623 ps
CPU time 6.51 seconds
Started Jul 19 05:45:45 PM PDT 24
Finished Jul 19 05:45:54 PM PDT 24
Peak memory 218360 kb
Host smart-dd0e1e70-0b5e-4eb8-b53f-bbc790c3baaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310169294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1310169294
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.57805371
Short name T602
Test name
Test status
Simulation time 1306669737 ps
CPU time 8.13 seconds
Started Jul 19 05:45:43 PM PDT 24
Finished Jul 19 05:45:54 PM PDT 24
Peak memory 224956 kb
Host smart-3b1740d1-6888-4206-a6dd-d809414a94e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57805371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.57805371
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.668906410
Short name T67
Test name
Test status
Simulation time 37586406 ps
CPU time 1.57 seconds
Started Jul 19 05:45:43 PM PDT 24
Finished Jul 19 05:45:47 PM PDT 24
Peak memory 217744 kb
Host smart-f5aba935-ee0e-49df-9349-a5bb464f5a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668906410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.668906410
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1388796533
Short name T506
Test name
Test status
Simulation time 408087515 ps
CPU time 19.92 seconds
Started Jul 19 05:45:41 PM PDT 24
Finished Jul 19 05:46:02 PM PDT 24
Peak memory 251096 kb
Host smart-710cf524-c835-45c9-9a86-4a4f19bbf6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388796533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1388796533
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1552943497
Short name T216
Test name
Test status
Simulation time 91131864 ps
CPU time 7.58 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 05:45:55 PM PDT 24
Peak memory 248312 kb
Host smart-6ecabfbe-9fba-4303-897d-5ffa135d327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552943497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1552943497
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2786115537
Short name T623
Test name
Test status
Simulation time 886461987 ps
CPU time 55.46 seconds
Started Jul 19 05:45:45 PM PDT 24
Finished Jul 19 05:46:43 PM PDT 24
Peak memory 247068 kb
Host smart-068ee16e-0dae-4062-bd3e-240818cce60c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786115537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2786115537
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3476765962
Short name T807
Test name
Test status
Simulation time 30838130 ps
CPU time 0.92 seconds
Started Jul 19 05:45:41 PM PDT 24
Finished Jul 19 05:45:43 PM PDT 24
Peak memory 211972 kb
Host smart-0f0df4b9-146a-4581-a3f1-fc4815fab573
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476765962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3476765962
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1881755451
Short name T626
Test name
Test status
Simulation time 27532140 ps
CPU time 0.95 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:45:59 PM PDT 24
Peak memory 209040 kb
Host smart-bd791246-a144-495d-a7dc-5c1e5c6eeb3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881755451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1881755451
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3154273310
Short name T239
Test name
Test status
Simulation time 724964939 ps
CPU time 13.04 seconds
Started Jul 19 05:45:51 PM PDT 24
Finished Jul 19 05:46:06 PM PDT 24
Peak memory 218364 kb
Host smart-74fb1ddd-f8ad-40b4-92e0-eb85cb005bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154273310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3154273310
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2622865303
Short name T8
Test name
Test status
Simulation time 369985048 ps
CPU time 3.3 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:45:58 PM PDT 24
Peak memory 217184 kb
Host smart-c244ef19-6ff7-4de6-bc8c-46fae96d57ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622865303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2622865303
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2258349319
Short name T662
Test name
Test status
Simulation time 83148392 ps
CPU time 3.37 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 05:45:50 PM PDT 24
Peak memory 218352 kb
Host smart-976f8c1c-a6f5-40f6-94df-380f29b5320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258349319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2258349319
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.80902055
Short name T751
Test name
Test status
Simulation time 3826614333 ps
CPU time 13.53 seconds
Started Jul 19 05:45:56 PM PDT 24
Finished Jul 19 05:46:14 PM PDT 24
Peak memory 226204 kb
Host smart-907921d8-ad1c-4786-8a2e-f720e64fb596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80902055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.80902055
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.337745745
Short name T765
Test name
Test status
Simulation time 373593688 ps
CPU time 14.46 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:46:09 PM PDT 24
Peak memory 226056 kb
Host smart-eeec31d3-1176-4d8c-bb98-e69357c2b718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337745745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.337745745
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3635699695
Short name T386
Test name
Test status
Simulation time 765377351 ps
CPU time 7.9 seconds
Started Jul 19 05:45:55 PM PDT 24
Finished Jul 19 05:46:07 PM PDT 24
Peak memory 218300 kb
Host smart-a74b28a9-2e4d-4b9d-ba63-2077eb5404b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635699695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3635699695
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1998809733
Short name T359
Test name
Test status
Simulation time 1790873991 ps
CPU time 9.84 seconds
Started Jul 19 05:45:54 PM PDT 24
Finished Jul 19 05:46:08 PM PDT 24
Peak memory 226132 kb
Host smart-557f37d0-f4c3-4d40-baec-8468a35de17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998809733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1998809733
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.710503395
Short name T263
Test name
Test status
Simulation time 237565206 ps
CPU time 2.07 seconds
Started Jul 19 05:45:44 PM PDT 24
Finished Jul 19 05:45:49 PM PDT 24
Peak memory 217728 kb
Host smart-d9b79b78-5e50-44ad-b281-dd2c68ea2da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710503395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.710503395
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2571447360
Short name T557
Test name
Test status
Simulation time 1423615598 ps
CPU time 33.41 seconds
Started Jul 19 05:45:42 PM PDT 24
Finished Jul 19 05:46:17 PM PDT 24
Peak memory 251108 kb
Host smart-c0d51230-efc6-452c-988e-6d2e21ed35ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571447360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2571447360
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2368545137
Short name T775
Test name
Test status
Simulation time 412787762 ps
CPU time 8.19 seconds
Started Jul 19 05:45:49 PM PDT 24
Finished Jul 19 05:45:58 PM PDT 24
Peak memory 251092 kb
Host smart-3a719070-b171-4678-9905-a69467190c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368545137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2368545137
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1558794173
Short name T45
Test name
Test status
Simulation time 21443554160 ps
CPU time 193.73 seconds
Started Jul 19 05:45:50 PM PDT 24
Finished Jul 19 05:49:05 PM PDT 24
Peak memory 283344 kb
Host smart-1fd59556-83c1-4ab2-ae8e-6728d7de63a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558794173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1558794173
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.509599177
Short name T132
Test name
Test status
Simulation time 24814433014 ps
CPU time 411.61 seconds
Started Jul 19 05:45:55 PM PDT 24
Finished Jul 19 05:52:51 PM PDT 24
Peak memory 284048 kb
Host smart-6cbf6c6f-62c9-41e4-aadd-8649ef0613e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=509599177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.509599177
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1210314600
Short name T840
Test name
Test status
Simulation time 11768184 ps
CPU time 0.93 seconds
Started Jul 19 05:45:45 PM PDT 24
Finished Jul 19 05:45:48 PM PDT 24
Peak memory 212012 kb
Host smart-7abd6d3b-613c-4a81-a407-ef821ca8be8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210314600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1210314600
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4276607844
Short name T624
Test name
Test status
Simulation time 21418925 ps
CPU time 1.21 seconds
Started Jul 19 05:45:55 PM PDT 24
Finished Jul 19 05:46:00 PM PDT 24
Peak memory 209012 kb
Host smart-6773e062-eb66-4216-b194-3990d0c01042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276607844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4276607844
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.608785908
Short name T845
Test name
Test status
Simulation time 1234250813 ps
CPU time 11.58 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:46:09 PM PDT 24
Peak memory 218452 kb
Host smart-eef65b51-93c6-4919-94b7-1d394a65702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608785908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.608785908
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2320552669
Short name T469
Test name
Test status
Simulation time 678416604 ps
CPU time 5.3 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:46:00 PM PDT 24
Peak memory 217776 kb
Host smart-9d1854f9-9a29-486d-b164-f880c2bb2456
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320552669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2320552669
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.495284187
Short name T149
Test name
Test status
Simulation time 91434085 ps
CPU time 4.01 seconds
Started Jul 19 05:45:51 PM PDT 24
Finished Jul 19 05:45:58 PM PDT 24
Peak memory 222528 kb
Host smart-0f7d186a-e940-4ce7-97a3-27ef9eaf5fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495284187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.495284187
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2020467348
Short name T575
Test name
Test status
Simulation time 2024983519 ps
CPU time 13.9 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:46:09 PM PDT 24
Peak memory 225984 kb
Host smart-c539149a-a22f-4c7f-bb32-6a3f3a411622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020467348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2020467348
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3427732142
Short name T588
Test name
Test status
Simulation time 7298706521 ps
CPU time 16.43 seconds
Started Jul 19 05:45:51 PM PDT 24
Finished Jul 19 05:46:09 PM PDT 24
Peak memory 226300 kb
Host smart-349b2259-c461-4984-a06d-e065155270ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427732142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3427732142
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3357348923
Short name T834
Test name
Test status
Simulation time 474608044 ps
CPU time 7.98 seconds
Started Jul 19 05:45:51 PM PDT 24
Finished Jul 19 05:46:01 PM PDT 24
Peak memory 218332 kb
Host smart-164a0cb5-f2a5-42e3-a0c8-21fa41802eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357348923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3357348923
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3309564987
Short name T450
Test name
Test status
Simulation time 1086287629 ps
CPU time 9.03 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:46:06 PM PDT 24
Peak memory 224708 kb
Host smart-a94d463d-a131-4af0-aba0-c00e20f82399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309564987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3309564987
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4174946204
Short name T361
Test name
Test status
Simulation time 181116918 ps
CPU time 2.77 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:46:00 PM PDT 24
Peak memory 214788 kb
Host smart-6b9e7176-69bd-4cfc-a186-1f4ae7a90925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174946204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4174946204
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.96412660
Short name T831
Test name
Test status
Simulation time 165643283 ps
CPU time 21.38 seconds
Started Jul 19 05:45:55 PM PDT 24
Finished Jul 19 05:46:20 PM PDT 24
Peak memory 251080 kb
Host smart-3fa5a404-5f3e-4f07-9e8c-bacb7a098cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96412660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.96412660
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1475333534
Short name T593
Test name
Test status
Simulation time 109971908 ps
CPU time 10.79 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:46:08 PM PDT 24
Peak memory 250424 kb
Host smart-cbd23093-1b12-4ffc-a44e-b0af5ab721f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475333534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1475333534
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2856324993
Short name T245
Test name
Test status
Simulation time 14803193764 ps
CPU time 142.84 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:48:18 PM PDT 24
Peak memory 283924 kb
Host smart-2cbffff7-91e0-4d2f-bb7a-26f93f0426cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856324993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2856324993
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1000800556
Short name T517
Test name
Test status
Simulation time 118390187 ps
CPU time 1.02 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:45:56 PM PDT 24
Peak memory 211896 kb
Host smart-99d48a05-68b8-45ae-a119-8c4e55f020d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000800556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1000800556
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.369754248
Short name T203
Test name
Test status
Simulation time 70566554 ps
CPU time 0.8 seconds
Started Jul 19 05:45:51 PM PDT 24
Finished Jul 19 05:45:53 PM PDT 24
Peak memory 209144 kb
Host smart-efb6ed41-2462-4d29-acfc-587d044c12b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369754248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.369754248
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2797259330
Short name T647
Test name
Test status
Simulation time 1039400951 ps
CPU time 13.05 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:46:08 PM PDT 24
Peak memory 226164 kb
Host smart-7a2a7b50-4417-4f20-926f-b1afb041884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797259330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2797259330
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1894982814
Short name T323
Test name
Test status
Simulation time 1230336953 ps
CPU time 3.86 seconds
Started Jul 19 05:45:51 PM PDT 24
Finished Jul 19 05:45:57 PM PDT 24
Peak memory 217176 kb
Host smart-bb08faa2-b583-4d9b-9196-ee31d642dbef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894982814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1894982814
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2947909034
Short name T478
Test name
Test status
Simulation time 41223303 ps
CPU time 1.61 seconds
Started Jul 19 05:45:51 PM PDT 24
Finished Jul 19 05:45:55 PM PDT 24
Peak memory 218360 kb
Host smart-c6b94a23-721e-4c73-ab93-37de1145d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947909034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2947909034
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1462860967
Short name T37
Test name
Test status
Simulation time 231197690 ps
CPU time 11.27 seconds
Started Jul 19 05:45:54 PM PDT 24
Finished Jul 19 05:46:10 PM PDT 24
Peak memory 218360 kb
Host smart-34e0485d-5ae4-4b89-ae87-d8adede31e82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462860967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1462860967
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3629700597
Short name T432
Test name
Test status
Simulation time 786248217 ps
CPU time 10.3 seconds
Started Jul 19 05:45:51 PM PDT 24
Finished Jul 19 05:46:04 PM PDT 24
Peak memory 226104 kb
Host smart-aef18957-1d66-4f07-853f-df7bcb7cc82a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629700597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3629700597
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1777711168
Short name T283
Test name
Test status
Simulation time 279683092 ps
CPU time 8.28 seconds
Started Jul 19 05:45:54 PM PDT 24
Finished Jul 19 05:46:06 PM PDT 24
Peak memory 226104 kb
Host smart-99c62ff1-0cb6-48ec-b8a1-9a9d44c04af4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777711168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1777711168
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.111230661
Short name T773
Test name
Test status
Simulation time 2488571696 ps
CPU time 12.06 seconds
Started Jul 19 05:45:55 PM PDT 24
Finished Jul 19 05:46:11 PM PDT 24
Peak memory 225684 kb
Host smart-3ae76683-91e0-471c-a31a-4a61c54a15d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111230661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.111230661
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.402796309
Short name T753
Test name
Test status
Simulation time 142113078 ps
CPU time 4.69 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:46:00 PM PDT 24
Peak memory 217784 kb
Host smart-058229ab-1248-48a8-b2b9-88f22c4efd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402796309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.402796309
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3492910488
Short name T297
Test name
Test status
Simulation time 215474504 ps
CPU time 22.77 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:46:19 PM PDT 24
Peak memory 251060 kb
Host smart-48d880cb-2a7b-4b83-b7f5-01344109035a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492910488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3492910488
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3275918357
Short name T580
Test name
Test status
Simulation time 64843493 ps
CPU time 9.51 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:46:06 PM PDT 24
Peak memory 251112 kb
Host smart-34a89d1b-1fb9-4693-9e32-fe4905fdf6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275918357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3275918357
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2482835603
Short name T485
Test name
Test status
Simulation time 1443750156 ps
CPU time 40.42 seconds
Started Jul 19 05:45:56 PM PDT 24
Finished Jul 19 05:46:41 PM PDT 24
Peak memory 251076 kb
Host smart-5ceb9819-cdce-4983-8815-3e8b3a37bcbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482835603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2482835603
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1465880782
Short name T135
Test name
Test status
Simulation time 67436741701 ps
CPU time 818.49 seconds
Started Jul 19 05:45:52 PM PDT 24
Finished Jul 19 05:59:34 PM PDT 24
Peak memory 262760 kb
Host smart-4e34b9af-8e31-4e9a-bbf3-3e8ee448bccd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1465880782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1465880782
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4266992323
Short name T808
Test name
Test status
Simulation time 22012778 ps
CPU time 0.95 seconds
Started Jul 19 05:45:54 PM PDT 24
Finished Jul 19 05:45:59 PM PDT 24
Peak memory 212992 kb
Host smart-5a102eb7-79e2-4984-891c-2881be5e60db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266992323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4266992323
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1981649178
Short name T516
Test name
Test status
Simulation time 27319269 ps
CPU time 1 seconds
Started Jul 19 05:46:00 PM PDT 24
Finished Jul 19 05:46:04 PM PDT 24
Peak memory 209056 kb
Host smart-3f1f0a0a-905e-4058-91c2-2b2de6f1e317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981649178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1981649178
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.129519358
Short name T645
Test name
Test status
Simulation time 307319895 ps
CPU time 14.31 seconds
Started Jul 19 05:46:12 PM PDT 24
Finished Jul 19 05:46:28 PM PDT 24
Peak memory 226308 kb
Host smart-922f1d8e-e21e-4a37-baaa-30e54fb7ae89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129519358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.129519358
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3254877141
Short name T813
Test name
Test status
Simulation time 5213948588 ps
CPU time 11.71 seconds
Started Jul 19 05:46:00 PM PDT 24
Finished Jul 19 05:46:15 PM PDT 24
Peak memory 217924 kb
Host smart-b051ecf8-515b-46bd-9107-a6776cd9be37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254877141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3254877141
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.50092026
Short name T644
Test name
Test status
Simulation time 42738467 ps
CPU time 2.66 seconds
Started Jul 19 05:46:12 PM PDT 24
Finished Jul 19 05:46:16 PM PDT 24
Peak memory 218504 kb
Host smart-59e2b68b-4a37-4f82-a779-1c9e86c80bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50092026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.50092026
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3160166350
Short name T607
Test name
Test status
Simulation time 209985672 ps
CPU time 10.46 seconds
Started Jul 19 05:45:58 PM PDT 24
Finished Jul 19 05:46:12 PM PDT 24
Peak memory 218388 kb
Host smart-7ab5e25f-3cd4-497b-86f0-1c41b5b10b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160166350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3160166350
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1091456066
Short name T308
Test name
Test status
Simulation time 715641435 ps
CPU time 14.35 seconds
Started Jul 19 05:45:59 PM PDT 24
Finished Jul 19 05:46:17 PM PDT 24
Peak memory 226100 kb
Host smart-97c2573e-5c3d-4e2b-9900-53a983160ede
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091456066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1091456066
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2356582383
Short name T351
Test name
Test status
Simulation time 1450634192 ps
CPU time 12.92 seconds
Started Jul 19 05:46:12 PM PDT 24
Finished Jul 19 05:46:27 PM PDT 24
Peak memory 218452 kb
Host smart-ff5e3256-cfa6-4580-beaa-4938179c4652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356582383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2356582383
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2342753039
Short name T637
Test name
Test status
Simulation time 229187656 ps
CPU time 8.66 seconds
Started Jul 19 05:46:12 PM PDT 24
Finished Jul 19 05:46:22 PM PDT 24
Peak memory 224924 kb
Host smart-4a1ad062-cdd4-43ea-85b8-66065c8472c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342753039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2342753039
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2732301572
Short name T778
Test name
Test status
Simulation time 141454829 ps
CPU time 2.97 seconds
Started Jul 19 05:45:50 PM PDT 24
Finished Jul 19 05:45:55 PM PDT 24
Peak memory 217788 kb
Host smart-68c8b5f0-9a4a-4be9-ae66-b196c3bf261e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732301572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2732301572
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1079846778
Short name T560
Test name
Test status
Simulation time 3239182141 ps
CPU time 29.88 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:46:26 PM PDT 24
Peak memory 246456 kb
Host smart-b971976c-b379-4a04-a1ad-76e78a8b579d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079846778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1079846778
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2652521748
Short name T412
Test name
Test status
Simulation time 397586277 ps
CPU time 11.19 seconds
Started Jul 19 05:45:58 PM PDT 24
Finished Jul 19 05:46:13 PM PDT 24
Peak memory 251072 kb
Host smart-da0e7bdc-57a2-4126-af19-b33439a80770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652521748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2652521748
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2969687907
Short name T248
Test name
Test status
Simulation time 14335895 ps
CPU time 1.02 seconds
Started Jul 19 05:45:53 PM PDT 24
Finished Jul 19 05:45:57 PM PDT 24
Peak memory 211996 kb
Host smart-882f2694-e653-4f47-977e-f3bd4e2e4bcf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969687907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2969687907
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2589793278
Short name T491
Test name
Test status
Simulation time 62625236 ps
CPU time 1.12 seconds
Started Jul 19 05:46:01 PM PDT 24
Finished Jul 19 05:46:05 PM PDT 24
Peak memory 209064 kb
Host smart-119c72ff-6122-4b7b-8339-f07bd32aef5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589793278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2589793278
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.601831729
Short name T576
Test name
Test status
Simulation time 315862545 ps
CPU time 14.63 seconds
Started Jul 19 05:46:00 PM PDT 24
Finished Jul 19 05:46:17 PM PDT 24
Peak memory 226300 kb
Host smart-e98ba42d-523c-4dfe-baab-1b68277da04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601831729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.601831729
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1098458649
Short name T454
Test name
Test status
Simulation time 364522567 ps
CPU time 4.47 seconds
Started Jul 19 05:45:58 PM PDT 24
Finished Jul 19 05:46:06 PM PDT 24
Peak memory 217168 kb
Host smart-06bfe56a-c275-4e5b-861c-886964a54dba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098458649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1098458649
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1426095729
Short name T809
Test name
Test status
Simulation time 47042252 ps
CPU time 1.81 seconds
Started Jul 19 05:46:01 PM PDT 24
Finished Jul 19 05:46:06 PM PDT 24
Peak memory 218348 kb
Host smart-e03cce2b-064b-4a44-9002-0a1239d68ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426095729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1426095729
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.189154932
Short name T477
Test name
Test status
Simulation time 1538664657 ps
CPU time 18.58 seconds
Started Jul 19 05:46:02 PM PDT 24
Finished Jul 19 05:46:23 PM PDT 24
Peak memory 226172 kb
Host smart-4393e626-bdec-46de-953a-38f02feede67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189154932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.189154932
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1420190898
Short name T224
Test name
Test status
Simulation time 273420428 ps
CPU time 10.11 seconds
Started Jul 19 05:45:59 PM PDT 24
Finished Jul 19 05:46:12 PM PDT 24
Peak memory 226096 kb
Host smart-e87e1c7d-3810-4aa1-b5be-080ef8fb7e65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420190898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1420190898
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.138579764
Short name T373
Test name
Test status
Simulation time 245020858 ps
CPU time 6.17 seconds
Started Jul 19 05:46:11 PM PDT 24
Finished Jul 19 05:46:19 PM PDT 24
Peak memory 225620 kb
Host smart-1e37dd96-ec8b-4da8-96bc-209bc2bdda6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138579764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.138579764
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4053269111
Short name T397
Test name
Test status
Simulation time 454897399 ps
CPU time 11.84 seconds
Started Jul 19 05:46:11 PM PDT 24
Finished Jul 19 05:46:25 PM PDT 24
Peak memory 225684 kb
Host smart-f7e38b60-4c23-4c44-a3fa-5f82f87bc781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053269111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4053269111
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1411563195
Short name T53
Test name
Test status
Simulation time 405492588 ps
CPU time 7.35 seconds
Started Jul 19 05:46:02 PM PDT 24
Finished Jul 19 05:46:12 PM PDT 24
Peak memory 217800 kb
Host smart-30c895af-d629-4d3d-9715-eaea4dfbba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411563195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1411563195
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3722770806
Short name T360
Test name
Test status
Simulation time 462016383 ps
CPU time 35.35 seconds
Started Jul 19 05:46:13 PM PDT 24
Finished Jul 19 05:46:49 PM PDT 24
Peak memory 251160 kb
Host smart-26bb0c2d-4630-4a4d-b828-cb58765d87d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722770806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3722770806
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2565661329
Short name T568
Test name
Test status
Simulation time 71788512 ps
CPU time 7.05 seconds
Started Jul 19 05:45:59 PM PDT 24
Finished Jul 19 05:46:09 PM PDT 24
Peak memory 246156 kb
Host smart-7dd3dcb5-c995-471b-b5a3-a6fa70300828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565661329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2565661329
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2568687521
Short name T674
Test name
Test status
Simulation time 5354604923 ps
CPU time 10.24 seconds
Started Jul 19 05:45:59 PM PDT 24
Finished Jul 19 05:46:12 PM PDT 24
Peak memory 226236 kb
Host smart-6e688a5c-0e13-4f3e-908e-5b8517cb515b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568687521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2568687521
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3126986721
Short name T154
Test name
Test status
Simulation time 93821265251 ps
CPU time 784.71 seconds
Started Jul 19 05:45:59 PM PDT 24
Finished Jul 19 05:59:07 PM PDT 24
Peak memory 422268 kb
Host smart-f50b210c-9e1a-4112-bc04-cd9b93b40617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3126986721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3126986721
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.289844907
Short name T768
Test name
Test status
Simulation time 124983357 ps
CPU time 0.97 seconds
Started Jul 19 05:46:00 PM PDT 24
Finished Jul 19 05:46:04 PM PDT 24
Peak memory 212008 kb
Host smart-db95b4cc-6c1f-41c1-b66b-1f1884e1e345
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289844907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.289844907
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.43963795
Short name T670
Test name
Test status
Simulation time 68431539 ps
CPU time 1.41 seconds
Started Jul 19 05:46:06 PM PDT 24
Finished Jul 19 05:46:09 PM PDT 24
Peak memory 209060 kb
Host smart-5bba7580-aecf-44d3-aa59-932c20dc32b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43963795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.43963795
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2852629897
Short name T148
Test name
Test status
Simulation time 660773720 ps
CPU time 19.78 seconds
Started Jul 19 05:46:02 PM PDT 24
Finished Jul 19 05:46:24 PM PDT 24
Peak memory 218384 kb
Host smart-f86d49be-0ae3-450c-b352-588eed611446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852629897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2852629897
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.355360918
Short name T567
Test name
Test status
Simulation time 434866462 ps
CPU time 5.54 seconds
Started Jul 19 05:45:58 PM PDT 24
Finished Jul 19 05:46:07 PM PDT 24
Peak memory 217516 kb
Host smart-f712ca2e-8cb5-4c05-bd02-8808d99f5b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355360918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.355360918
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3569672324
Short name T764
Test name
Test status
Simulation time 68737505 ps
CPU time 1.5 seconds
Started Jul 19 05:46:01 PM PDT 24
Finished Jul 19 05:46:05 PM PDT 24
Peak memory 221764 kb
Host smart-d9a5451e-2e9f-4086-8550-a0fca6158a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569672324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3569672324
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2351580448
Short name T366
Test name
Test status
Simulation time 355798325 ps
CPU time 7.56 seconds
Started Jul 19 05:46:00 PM PDT 24
Finished Jul 19 05:46:11 PM PDT 24
Peak memory 218396 kb
Host smart-3dfa943f-e00f-4527-ab5d-36dc4b9f8482
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351580448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2351580448
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1334564462
Short name T215
Test name
Test status
Simulation time 997568375 ps
CPU time 14.25 seconds
Started Jul 19 05:46:06 PM PDT 24
Finished Jul 19 05:46:21 PM PDT 24
Peak memory 226096 kb
Host smart-a0712256-e565-4739-8b66-94e67909a650
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334564462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1334564462
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3288766344
Short name T642
Test name
Test status
Simulation time 1692709321 ps
CPU time 11.87 seconds
Started Jul 19 05:46:12 PM PDT 24
Finished Jul 19 05:46:25 PM PDT 24
Peak memory 218572 kb
Host smart-1cb34be7-4aff-4808-bc94-20d04ccd9b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288766344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3288766344
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2869928002
Short name T349
Test name
Test status
Simulation time 39900701 ps
CPU time 2.74 seconds
Started Jul 19 05:45:58 PM PDT 24
Finished Jul 19 05:46:04 PM PDT 24
Peak memory 214388 kb
Host smart-bce1d918-ec4d-4ca0-a38e-1f256d40966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869928002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2869928002
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1753780680
Short name T661
Test name
Test status
Simulation time 617036422 ps
CPU time 24.74 seconds
Started Jul 19 05:46:02 PM PDT 24
Finished Jul 19 05:46:29 PM PDT 24
Peak memory 251112 kb
Host smart-1b8c5fef-0429-417f-9799-ded10aa7f0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753780680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1753780680
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1646079970
Short name T448
Test name
Test status
Simulation time 1088499315 ps
CPU time 6.27 seconds
Started Jul 19 05:46:00 PM PDT 24
Finished Jul 19 05:46:09 PM PDT 24
Peak memory 247216 kb
Host smart-3f53a524-35bb-4805-abaf-db56a78fe4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646079970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1646079970
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3031998569
Short name T69
Test name
Test status
Simulation time 1960719705 ps
CPU time 64.32 seconds
Started Jul 19 05:46:06 PM PDT 24
Finished Jul 19 05:47:12 PM PDT 24
Peak memory 226104 kb
Host smart-17e9707b-8b52-4483-85fb-3b9f9bc1b735
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031998569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3031998569
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2397284052
Short name T162
Test name
Test status
Simulation time 28377309 ps
CPU time 1.1 seconds
Started Jul 19 05:46:01 PM PDT 24
Finished Jul 19 05:46:04 PM PDT 24
Peak memory 213056 kb
Host smart-d4e611c0-5429-4dbd-9c2f-414ac5d2be0a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397284052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2397284052
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1830225186
Short name T598
Test name
Test status
Simulation time 18353327 ps
CPU time 1.17 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:17 PM PDT 24
Peak memory 209092 kb
Host smart-1d860341-2019-4e07-922c-bc15300f9964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830225186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1830225186
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.4116766090
Short name T727
Test name
Test status
Simulation time 19615331 ps
CPU time 0.98 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:17 PM PDT 24
Peak memory 208876 kb
Host smart-b0fa8f08-38e3-4d6e-9a93-1b52a1bae078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116766090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.4116766090
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2016516869
Short name T694
Test name
Test status
Simulation time 589467154 ps
CPU time 14.19 seconds
Started Jul 19 05:43:15 PM PDT 24
Finished Jul 19 05:43:32 PM PDT 24
Peak memory 218372 kb
Host smart-b92f9e71-962c-40b8-be19-3c8d4741d237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016516869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2016516869
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3095970334
Short name T28
Test name
Test status
Simulation time 489125874 ps
CPU time 3.7 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:19 PM PDT 24
Peak memory 217452 kb
Host smart-48a2d5f6-f91d-4a5a-a0ca-9d77ecbba279
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095970334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3095970334
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.438493856
Short name T381
Test name
Test status
Simulation time 7195062875 ps
CPU time 51.45 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:44:08 PM PDT 24
Peak memory 226128 kb
Host smart-8cd270f9-465b-4602-8cf6-f86c52fd5bf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438493856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.438493856
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1659905641
Short name T1
Test name
Test status
Simulation time 377869648 ps
CPU time 5.85 seconds
Started Jul 19 05:43:16 PM PDT 24
Finished Jul 19 05:43:25 PM PDT 24
Peak memory 217836 kb
Host smart-062fd5ae-4c34-438b-9ae0-235704f31873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659905641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
659905641
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3714603284
Short name T244
Test name
Test status
Simulation time 194259988 ps
CPU time 3.65 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:20 PM PDT 24
Peak memory 218328 kb
Host smart-408055c6-e519-4ddd-bdaf-a9a2a37b7343
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714603284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3714603284
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.601518009
Short name T57
Test name
Test status
Simulation time 4945423900 ps
CPU time 18.78 seconds
Started Jul 19 05:43:12 PM PDT 24
Finished Jul 19 05:43:33 PM PDT 24
Peak memory 217736 kb
Host smart-e1d66a2d-d5d6-4607-8e10-648bf49bd450
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601518009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.601518009
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2162977873
Short name T719
Test name
Test status
Simulation time 2051476359 ps
CPU time 2 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:19 PM PDT 24
Peak memory 217816 kb
Host smart-c5ed5d67-7d0a-46c7-986d-43dc8732bf2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162977873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2162977873
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2223964424
Short name T663
Test name
Test status
Simulation time 5090169945 ps
CPU time 37.02 seconds
Started Jul 19 05:43:15 PM PDT 24
Finished Jul 19 05:43:55 PM PDT 24
Peak memory 267492 kb
Host smart-c0902b4b-ffca-42cc-b15f-26ee8113c23b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223964424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2223964424
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3933521234
Short name T463
Test name
Test status
Simulation time 368516336 ps
CPU time 12.64 seconds
Started Jul 19 05:43:12 PM PDT 24
Finished Jul 19 05:43:27 PM PDT 24
Peak memory 223176 kb
Host smart-42b2737e-4300-4332-bfb8-da95f28844e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933521234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3933521234
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1334855927
Short name T470
Test name
Test status
Simulation time 110974413 ps
CPU time 3.41 seconds
Started Jul 19 05:43:15 PM PDT 24
Finished Jul 19 05:43:21 PM PDT 24
Peak memory 218360 kb
Host smart-60d65df9-43e9-4224-bfca-8ad8c986ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334855927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1334855927
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2274747356
Short name T379
Test name
Test status
Simulation time 1667206353 ps
CPU time 5.38 seconds
Started Jul 19 05:43:12 PM PDT 24
Finished Jul 19 05:43:19 PM PDT 24
Peak memory 214236 kb
Host smart-4cd0cebf-910f-4101-972a-cfe82981e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274747356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2274747356
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1896331084
Short name T207
Test name
Test status
Simulation time 753389405 ps
CPU time 21.8 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:38 PM PDT 24
Peak memory 218376 kb
Host smart-c2ed3819-1e51-4c66-a426-bebe2cbabf25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896331084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1896331084
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2749048157
Short name T484
Test name
Test status
Simulation time 6049120271 ps
CPU time 26.23 seconds
Started Jul 19 05:43:11 PM PDT 24
Finished Jul 19 05:43:39 PM PDT 24
Peak memory 226156 kb
Host smart-ae8f0503-0d5e-4f37-aaf4-17f34ee679a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749048157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2749048157
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2522144564
Short name T756
Test name
Test status
Simulation time 288368386 ps
CPU time 10.73 seconds
Started Jul 19 05:43:12 PM PDT 24
Finished Jul 19 05:43:25 PM PDT 24
Peak memory 218296 kb
Host smart-343a88ac-cafb-4d6c-a048-07a39d85f2e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522144564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
522144564
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2613598957
Short name T812
Test name
Test status
Simulation time 588961779 ps
CPU time 8.56 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:23 PM PDT 24
Peak memory 226192 kb
Host smart-8ab427dd-de15-41fa-9f31-fbc04b94a020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613598957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2613598957
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3325750569
Short name T256
Test name
Test status
Simulation time 73855145 ps
CPU time 4.37 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:19 PM PDT 24
Peak memory 217692 kb
Host smart-b7d802e6-c3a0-4691-91d8-cc5f9bbde3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325750569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3325750569
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1406111377
Short name T384
Test name
Test status
Simulation time 240633504 ps
CPU time 32.65 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:50 PM PDT 24
Peak memory 247604 kb
Host smart-60f3f6a5-449e-4674-92bd-969b8a54b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406111377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1406111377
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1691958488
Short name T795
Test name
Test status
Simulation time 571110170 ps
CPU time 5.78 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:22 PM PDT 24
Peak memory 247504 kb
Host smart-b3397828-f04a-40a6-8ea8-956a43c516a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691958488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1691958488
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3084919227
Short name T353
Test name
Test status
Simulation time 12453555361 ps
CPU time 125.78 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:45:20 PM PDT 24
Peak memory 269048 kb
Host smart-0965d3b5-09b5-4568-98b0-d64782faaf28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084919227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3084919227
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3267936294
Short name T444
Test name
Test status
Simulation time 15680757 ps
CPU time 0.93 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:16 PM PDT 24
Peak memory 217764 kb
Host smart-47bf8b2b-89f9-46c5-97f1-f0ac23272837
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267936294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3267936294
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.294432503
Short name T304
Test name
Test status
Simulation time 18804901 ps
CPU time 0.95 seconds
Started Jul 19 05:43:21 PM PDT 24
Finished Jul 19 05:43:23 PM PDT 24
Peak memory 208976 kb
Host smart-723da231-4553-46bf-bb98-6fc619b14146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294432503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.294432503
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3689446515
Short name T158
Test name
Test status
Simulation time 46613154 ps
CPU time 0.79 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:15 PM PDT 24
Peak memory 209116 kb
Host smart-47197967-905b-49c0-a85b-cf7d8af62bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689446515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3689446515
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.878069172
Short name T690
Test name
Test status
Simulation time 780275921 ps
CPU time 25.53 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 218304 kb
Host smart-54867386-3fb1-4406-b840-29c0dc688bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878069172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.878069172
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2553067325
Short name T562
Test name
Test status
Simulation time 3713819313 ps
CPU time 20.33 seconds
Started Jul 19 05:43:12 PM PDT 24
Finished Jul 19 05:43:34 PM PDT 24
Peak memory 217792 kb
Host smart-e5a9dfb9-3127-4489-a3d1-a8ce9f8b6c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553067325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2553067325
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3072502838
Short name T451
Test name
Test status
Simulation time 6971334584 ps
CPU time 48.9 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:44:04 PM PDT 24
Peak memory 219040 kb
Host smart-495c2f55-0a22-49a7-af1e-be29dfbd17be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072502838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3072502838
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1018275525
Short name T456
Test name
Test status
Simulation time 437056124 ps
CPU time 3.7 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:20 PM PDT 24
Peak memory 217812 kb
Host smart-cf734e32-8344-48af-ad4d-c23e918be2d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018275525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
018275525
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2020364872
Short name T290
Test name
Test status
Simulation time 1229915007 ps
CPU time 5.41 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:20 PM PDT 24
Peak memory 218284 kb
Host smart-cd1ccf85-cf6c-4881-861b-b8b6c3420ce7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020364872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2020364872
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1279056224
Short name T219
Test name
Test status
Simulation time 4664787910 ps
CPU time 15.71 seconds
Started Jul 19 05:43:26 PM PDT 24
Finished Jul 19 05:43:42 PM PDT 24
Peak memory 217780 kb
Host smart-63b0c08d-fc91-43b9-b1bd-8d1faa70ad52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279056224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1279056224
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3521225346
Short name T338
Test name
Test status
Simulation time 224789740 ps
CPU time 4.21 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:19 PM PDT 24
Peak memory 217732 kb
Host smart-54177f4f-1f51-4f0b-b7fe-27708d40d244
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521225346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3521225346
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3905538565
Short name T630
Test name
Test status
Simulation time 31660744211 ps
CPU time 58.1 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:44:14 PM PDT 24
Peak memory 283864 kb
Host smart-6b30677e-e36f-4f94-8512-ddbabb465535
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905538565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3905538565
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.18358981
Short name T542
Test name
Test status
Simulation time 1198614740 ps
CPU time 18.67 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:36 PM PDT 24
Peak memory 249628 kb
Host smart-de9a0ddd-a5ce-46c9-8ac0-fbf1a1a47abc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18358981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt
ag_state_post_trans.18358981
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.4252353850
Short name T539
Test name
Test status
Simulation time 55748263 ps
CPU time 2.5 seconds
Started Jul 19 05:43:13 PM PDT 24
Finished Jul 19 05:43:18 PM PDT 24
Peak memory 222412 kb
Host smart-81920cad-aba5-4879-9e88-a7f85d9eb426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252353850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.4252353850
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1010653722
Short name T61
Test name
Test status
Simulation time 294326597 ps
CPU time 17.38 seconds
Started Jul 19 05:43:16 PM PDT 24
Finished Jul 19 05:43:36 PM PDT 24
Peak memory 214796 kb
Host smart-0ffb7431-af02-4af1-aa7e-17b05a3f5c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010653722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1010653722
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.633008647
Short name T199
Test name
Test status
Simulation time 177345023 ps
CPU time 8.21 seconds
Started Jul 19 05:43:18 PM PDT 24
Finished Jul 19 05:43:28 PM PDT 24
Peak memory 226092 kb
Host smart-5814384c-c7c1-433b-b1ba-4ca3019fcc94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633008647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.633008647
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4158246749
Short name T680
Test name
Test status
Simulation time 323549846 ps
CPU time 12.48 seconds
Started Jul 19 05:43:19 PM PDT 24
Finished Jul 19 05:43:33 PM PDT 24
Peak memory 226104 kb
Host smart-c72a1a47-2a7e-4fcf-b6f8-c21bc46cf982
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158246749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
158246749
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2194227830
Short name T740
Test name
Test status
Simulation time 491754469 ps
CPU time 9.8 seconds
Started Jul 19 05:43:15 PM PDT 24
Finished Jul 19 05:43:28 PM PDT 24
Peak memory 226168 kb
Host smart-add0cdd5-fccd-4130-a889-4433a49b9ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194227830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2194227830
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1290332155
Short name T426
Test name
Test status
Simulation time 16790727 ps
CPU time 1.26 seconds
Started Jul 19 05:43:11 PM PDT 24
Finished Jul 19 05:43:14 PM PDT 24
Peak memory 212232 kb
Host smart-160134fb-49cb-4dc1-bc1f-b3f95277ecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290332155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1290332155
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2093564706
Short name T475
Test name
Test status
Simulation time 812448336 ps
CPU time 15.89 seconds
Started Jul 19 05:43:15 PM PDT 24
Finished Jul 19 05:43:34 PM PDT 24
Peak memory 251248 kb
Host smart-7a1a2e43-657b-4744-b9fd-f94156120d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093564706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2093564706
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.629251280
Short name T814
Test name
Test status
Simulation time 77654967 ps
CPU time 7.2 seconds
Started Jul 19 05:43:14 PM PDT 24
Finished Jul 19 05:43:24 PM PDT 24
Peak memory 250552 kb
Host smart-99139879-479a-49d3-984a-f863918ab2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629251280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.629251280
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2336168087
Short name T295
Test name
Test status
Simulation time 47726070670 ps
CPU time 168.36 seconds
Started Jul 19 05:43:19 PM PDT 24
Finished Jul 19 05:46:08 PM PDT 24
Peak memory 251068 kb
Host smart-1ced3ceb-cab6-42ca-ada2-f258c2fb142e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336168087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2336168087
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2227935697
Short name T33
Test name
Test status
Simulation time 11884230 ps
CPU time 0.87 seconds
Started Jul 19 05:43:11 PM PDT 24
Finished Jul 19 05:43:13 PM PDT 24
Peak memory 211952 kb
Host smart-4009bd23-2bed-45ae-a37e-7b601cb24892
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227935697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2227935697
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.806458340
Short name T697
Test name
Test status
Simulation time 32005315 ps
CPU time 0.89 seconds
Started Jul 19 05:43:28 PM PDT 24
Finished Jul 19 05:43:30 PM PDT 24
Peak memory 208964 kb
Host smart-1ef47ae9-fd7d-4bf9-be09-364893aa005e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806458340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.806458340
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2952173824
Short name T774
Test name
Test status
Simulation time 349024245 ps
CPU time 15.44 seconds
Started Jul 19 05:43:21 PM PDT 24
Finished Jul 19 05:43:38 PM PDT 24
Peak memory 218444 kb
Host smart-2df4e65f-2fc1-43c5-b913-4403df8e5065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952173824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2952173824
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4032112680
Short name T838
Test name
Test status
Simulation time 3355960967 ps
CPU time 47.73 seconds
Started Jul 19 05:43:22 PM PDT 24
Finished Jul 19 05:44:11 PM PDT 24
Peak memory 219004 kb
Host smart-cbe7e4f5-f698-4fc5-baf8-ed0e01bb3da6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032112680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4032112680
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1572174747
Short name T39
Test name
Test status
Simulation time 1261761983 ps
CPU time 16.46 seconds
Started Jul 19 05:43:20 PM PDT 24
Finished Jul 19 05:43:38 PM PDT 24
Peak memory 217472 kb
Host smart-10d2b661-80ed-4602-8ba7-3f1ed6d198fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572174747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
572174747
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3670367872
Short name T442
Test name
Test status
Simulation time 249285187 ps
CPU time 4.36 seconds
Started Jul 19 05:43:19 PM PDT 24
Finished Jul 19 05:43:25 PM PDT 24
Peak memory 218340 kb
Host smart-d91fd051-c429-4392-93f5-45599746826a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670367872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3670367872
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2158917875
Short name T771
Test name
Test status
Simulation time 1542883091 ps
CPU time 21.74 seconds
Started Jul 19 05:43:21 PM PDT 24
Finished Jul 19 05:43:45 PM PDT 24
Peak memory 217696 kb
Host smart-098a8f1d-b0b8-4028-8702-d1de65add756
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158917875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2158917875
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3330458411
Short name T213
Test name
Test status
Simulation time 649164050 ps
CPU time 8.7 seconds
Started Jul 19 05:43:25 PM PDT 24
Finished Jul 19 05:43:35 PM PDT 24
Peak memory 217716 kb
Host smart-2f5ef398-588b-40a0-8bbb-15aa15205cb8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330458411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3330458411
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2126602031
Short name T337
Test name
Test status
Simulation time 1555997994 ps
CPU time 65.72 seconds
Started Jul 19 05:43:25 PM PDT 24
Finished Jul 19 05:44:32 PM PDT 24
Peak memory 267444 kb
Host smart-d1ef7cd9-cfa9-4061-8dfa-bf91046f557d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126602031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2126602031
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1563326546
Short name T721
Test name
Test status
Simulation time 3364218256 ps
CPU time 17.32 seconds
Started Jul 19 05:43:22 PM PDT 24
Finished Jul 19 05:43:41 PM PDT 24
Peak memory 247772 kb
Host smart-fbe467e8-789e-4529-8646-590a7483ad42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563326546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1563326546
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3783702331
Short name T625
Test name
Test status
Simulation time 25784860 ps
CPU time 1.56 seconds
Started Jul 19 05:43:20 PM PDT 24
Finished Jul 19 05:43:23 PM PDT 24
Peak memory 218384 kb
Host smart-6e7b9857-2991-420e-87a7-5c58218bdd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783702331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3783702331
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.966280404
Short name T424
Test name
Test status
Simulation time 1308153409 ps
CPU time 21.22 seconds
Started Jul 19 05:43:19 PM PDT 24
Finished Jul 19 05:43:42 PM PDT 24
Peak memory 217748 kb
Host smart-df5a90cb-cbf8-4164-86da-cb3472f0b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966280404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.966280404
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.4275600485
Short name T18
Test name
Test status
Simulation time 278103565 ps
CPU time 14.02 seconds
Started Jul 19 05:43:22 PM PDT 24
Finished Jul 19 05:43:38 PM PDT 24
Peak memory 226160 kb
Host smart-59ce6e22-74e6-4a54-8acd-7375bdf22c67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275600485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.4275600485
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2409624359
Short name T857
Test name
Test status
Simulation time 1339946183 ps
CPU time 9.61 seconds
Started Jul 19 05:43:26 PM PDT 24
Finished Jul 19 05:43:36 PM PDT 24
Peak memory 226056 kb
Host smart-50cd19c9-efa7-4fa1-b7b4-daf9d186f24c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409624359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2409624359
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.422349582
Short name T165
Test name
Test status
Simulation time 1704058047 ps
CPU time 13.97 seconds
Started Jul 19 05:43:21 PM PDT 24
Finished Jul 19 05:43:37 PM PDT 24
Peak memory 226104 kb
Host smart-641b937f-342d-4b49-a34a-5e8882fa4dc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422349582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.422349582
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1537525777
Short name T252
Test name
Test status
Simulation time 364028787 ps
CPU time 8.81 seconds
Started Jul 19 05:43:21 PM PDT 24
Finished Jul 19 05:43:31 PM PDT 24
Peak memory 226168 kb
Host smart-4ed852cd-3b61-414a-a00c-9fbc6b7a4a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537525777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1537525777
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2584014591
Short name T589
Test name
Test status
Simulation time 132451586 ps
CPU time 1.43 seconds
Started Jul 19 05:43:22 PM PDT 24
Finished Jul 19 05:43:25 PM PDT 24
Peak memory 217880 kb
Host smart-1f7d3e36-5378-4217-89a0-a3499342c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584014591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2584014591
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1259591851
Short name T551
Test name
Test status
Simulation time 2232965251 ps
CPU time 18.78 seconds
Started Jul 19 05:43:21 PM PDT 24
Finished Jul 19 05:43:41 PM PDT 24
Peak memory 251148 kb
Host smart-4bc78719-9948-49c5-8737-a26ad5c225fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259591851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1259591851
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1037879465
Short name T739
Test name
Test status
Simulation time 371273370 ps
CPU time 7.07 seconds
Started Jul 19 05:43:22 PM PDT 24
Finished Jul 19 05:43:30 PM PDT 24
Peak memory 250496 kb
Host smart-11427d53-57cb-4156-9db3-79284056ac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037879465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1037879465
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3050619039
Short name T854
Test name
Test status
Simulation time 15687571255 ps
CPU time 271.19 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:48:01 PM PDT 24
Peak memory 283820 kb
Host smart-2b9b28d7-75ea-46b1-8937-341978b4dbee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050619039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3050619039
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3335816967
Short name T673
Test name
Test status
Simulation time 16253723 ps
CPU time 1.2 seconds
Started Jul 19 05:43:19 PM PDT 24
Finished Jul 19 05:43:22 PM PDT 24
Peak memory 213132 kb
Host smart-94d66092-23d7-4dc0-9548-d4f74ed48eb9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335816967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3335816967
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2686547979
Short name T495
Test name
Test status
Simulation time 93002037 ps
CPU time 1.19 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:31 PM PDT 24
Peak memory 208908 kb
Host smart-2e897872-66eb-46b8-9768-1d3a077ba482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686547979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2686547979
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.272919635
Short name T274
Test name
Test status
Simulation time 14300853 ps
CPU time 0.84 seconds
Started Jul 19 05:43:25 PM PDT 24
Finished Jul 19 05:43:27 PM PDT 24
Peak memory 208772 kb
Host smart-c1c0123c-5f54-4fa3-89d0-311e4c40ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272919635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.272919635
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2708242390
Short name T2
Test name
Test status
Simulation time 413879192 ps
CPU time 13.88 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 218376 kb
Host smart-b51a3119-0e3a-4c36-b9aa-5cbc2fe3f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708242390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2708242390
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1657956260
Short name T320
Test name
Test status
Simulation time 1714874470 ps
CPU time 9.54 seconds
Started Jul 19 05:43:32 PM PDT 24
Finished Jul 19 05:43:42 PM PDT 24
Peak memory 217464 kb
Host smart-f403ddf0-d5c7-4b05-acbe-4fc1a2bb1c0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657956260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1657956260
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1572828667
Short name T233
Test name
Test status
Simulation time 18671962664 ps
CPU time 58.49 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:44:27 PM PDT 24
Peak memory 219744 kb
Host smart-33d26215-f3b2-47d7-aa9d-184b6ee4a632
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572828667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1572828667
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1062722276
Short name T52
Test name
Test status
Simulation time 1495793460 ps
CPU time 9.4 seconds
Started Jul 19 05:43:26 PM PDT 24
Finished Jul 19 05:43:37 PM PDT 24
Peak memory 217840 kb
Host smart-71e4240e-32f7-4945-ac9c-24e23f491e02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062722276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
062722276
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3099640230
Short name T367
Test name
Test status
Simulation time 2538127041 ps
CPU time 11.94 seconds
Started Jul 19 05:43:28 PM PDT 24
Finished Jul 19 05:43:42 PM PDT 24
Peak memory 218348 kb
Host smart-6274d70d-3d9a-489b-9dbf-9a3a9585974a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099640230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3099640230
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3374151496
Short name T726
Test name
Test status
Simulation time 1339911636 ps
CPU time 21.41 seconds
Started Jul 19 05:43:28 PM PDT 24
Finished Jul 19 05:43:51 PM PDT 24
Peak memory 217844 kb
Host smart-7984dbb8-f595-4b2a-8a77-0de9cdcae5a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374151496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3374151496
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1850364589
Short name T641
Test name
Test status
Simulation time 1194313193 ps
CPU time 8.56 seconds
Started Jul 19 05:43:26 PM PDT 24
Finished Jul 19 05:43:37 PM PDT 24
Peak memory 217716 kb
Host smart-554573a6-7b69-40a3-8049-d625f3c46ef9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850364589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1850364589
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.267671806
Short name T431
Test name
Test status
Simulation time 1272254566 ps
CPU time 51.24 seconds
Started Jul 19 05:43:26 PM PDT 24
Finished Jul 19 05:44:19 PM PDT 24
Peak memory 275628 kb
Host smart-ec82eb2e-6bb1-45cb-a06a-ba5be09d9288
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267671806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.267671806
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2125328949
Short name T481
Test name
Test status
Simulation time 1359937671 ps
CPU time 20.64 seconds
Started Jul 19 05:43:26 PM PDT 24
Finished Jul 19 05:43:49 PM PDT 24
Peak memory 251048 kb
Host smart-1b29b2e9-8c4a-4199-acc5-dcfbbdae1564
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125328949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2125328949
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1972442630
Short name T280
Test name
Test status
Simulation time 23111191 ps
CPU time 1.47 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:31 PM PDT 24
Peak memory 218360 kb
Host smart-26bb0c6f-e8fe-446e-8c48-fb1c265e19f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972442630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1972442630
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.429661558
Short name T403
Test name
Test status
Simulation time 980445118 ps
CPU time 6.02 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:35 PM PDT 24
Peak memory 214620 kb
Host smart-be6b23c4-ee41-438d-8f31-199a5c64aafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429661558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.429661558
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2482645327
Short name T702
Test name
Test status
Simulation time 1170917908 ps
CPU time 10.97 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:40 PM PDT 24
Peak memory 226084 kb
Host smart-626339ad-572c-4429-a734-dacd720e8fd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482645327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2482645327
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3659255942
Short name T780
Test name
Test status
Simulation time 1170442782 ps
CPU time 7.37 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:36 PM PDT 24
Peak memory 218300 kb
Host smart-0075a398-a3a8-4820-8b78-455c2b279017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659255942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
659255942
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2592288569
Short name T705
Test name
Test status
Simulation time 332113795 ps
CPU time 14.23 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 218388 kb
Host smart-67f3c4c4-8aec-4130-963d-02ba2866172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592288569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2592288569
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2022972766
Short name T286
Test name
Test status
Simulation time 60291316 ps
CPU time 1.99 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:30 PM PDT 24
Peak memory 217860 kb
Host smart-bb31b18d-f266-4ecc-a694-63b4f5297286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022972766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2022972766
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3053014779
Short name T144
Test name
Test status
Simulation time 1266286333 ps
CPU time 25.94 seconds
Started Jul 19 05:43:29 PM PDT 24
Finished Jul 19 05:43:56 PM PDT 24
Peak memory 250916 kb
Host smart-fed551a8-7153-42a8-b319-ab084b2f043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053014779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3053014779
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.4018612367
Short name T74
Test name
Test status
Simulation time 189378088 ps
CPU time 6.68 seconds
Started Jul 19 05:43:32 PM PDT 24
Finished Jul 19 05:43:40 PM PDT 24
Peak memory 246904 kb
Host smart-748ed177-904e-4e08-8b16-1cee4fe1881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018612367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4018612367
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2684682828
Short name T796
Test name
Test status
Simulation time 19721358058 ps
CPU time 148.17 seconds
Started Jul 19 05:43:33 PM PDT 24
Finished Jul 19 05:46:01 PM PDT 24
Peak memory 276528 kb
Host smart-59ae7f15-ed3f-48f3-b90c-d420396c0320
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684682828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2684682828
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1045214637
Short name T167
Test name
Test status
Simulation time 25834931064 ps
CPU time 1821.31 seconds
Started Jul 19 05:43:25 PM PDT 24
Finished Jul 19 06:13:48 PM PDT 24
Peak memory 1505568 kb
Host smart-8e22a9de-303b-47be-a139-b51210fd501b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1045214637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1045214637
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1610046048
Short name T505
Test name
Test status
Simulation time 54055542 ps
CPU time 0.84 seconds
Started Jul 19 05:43:27 PM PDT 24
Finished Jul 19 05:43:30 PM PDT 24
Peak memory 211948 kb
Host smart-873c1742-34bc-4152-a76e-5b3b7ef1f348
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610046048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1610046048
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3023258280
Short name T287
Test name
Test status
Simulation time 18483459 ps
CPU time 1.17 seconds
Started Jul 19 05:43:39 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 209076 kb
Host smart-7128ac58-7215-48ba-8e17-67bb4ade0435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023258280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3023258280
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2190692999
Short name T192
Test name
Test status
Simulation time 30886750 ps
CPU time 0.81 seconds
Started Jul 19 05:43:40 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 209100 kb
Host smart-7b2668d0-4550-4fc9-acd9-adc567f81a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190692999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2190692999
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3068397541
Short name T586
Test name
Test status
Simulation time 510680761 ps
CPU time 9.11 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:49 PM PDT 24
Peak memory 218384 kb
Host smart-7f1b8990-ef30-4d70-8bb1-1f0b1851818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068397541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3068397541
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2328700987
Short name T846
Test name
Test status
Simulation time 601595768 ps
CPU time 5.36 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:46 PM PDT 24
Peak memory 217176 kb
Host smart-1be6114e-b72f-4043-be3a-c9858c7235ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328700987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2328700987
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3639772309
Short name T811
Test name
Test status
Simulation time 1858954271 ps
CPU time 28.91 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:44:10 PM PDT 24
Peak memory 218296 kb
Host smart-b6eeb881-a48b-41ba-941a-8e6bd6507fec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639772309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3639772309
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1080256846
Short name T523
Test name
Test status
Simulation time 1403619563 ps
CPU time 23.08 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:44:04 PM PDT 24
Peak memory 217520 kb
Host smart-ac10c821-0363-414f-a0d4-e565600bbb03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080256846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
080256846
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3910842237
Short name T493
Test name
Test status
Simulation time 939901850 ps
CPU time 4.67 seconds
Started Jul 19 05:43:35 PM PDT 24
Finished Jul 19 05:43:41 PM PDT 24
Peak memory 222992 kb
Host smart-19dec36d-8f03-4594-838d-ced00509ebac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910842237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3910842237
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3941554482
Short name T533
Test name
Test status
Simulation time 6313172706 ps
CPU time 20.13 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:44:01 PM PDT 24
Peak memory 217768 kb
Host smart-b52106ab-97db-451e-8572-cf22587e3151
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941554482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3941554482
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2276674219
Short name T652
Test name
Test status
Simulation time 913897403 ps
CPU time 3.12 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 217728 kb
Host smart-0e2ca3e7-6a7e-46a0-b1fd-39c4ae83e3b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276674219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2276674219
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2744009871
Short name T214
Test name
Test status
Simulation time 2553994582 ps
CPU time 42.87 seconds
Started Jul 19 05:43:37 PM PDT 24
Finished Jul 19 05:44:22 PM PDT 24
Peak memory 271676 kb
Host smart-52153c73-449c-4e16-918e-2125090f9ef7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744009871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2744009871
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3387639498
Short name T860
Test name
Test status
Simulation time 771233115 ps
CPU time 28.63 seconds
Started Jul 19 05:43:36 PM PDT 24
Finished Jul 19 05:44:07 PM PDT 24
Peak memory 251060 kb
Host smart-0794251e-21d2-4fbd-868f-86ad2f742557
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387639498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3387639498
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.264805919
Short name T687
Test name
Test status
Simulation time 134963069 ps
CPU time 2.52 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:43 PM PDT 24
Peak memory 218312 kb
Host smart-781126ed-5250-4e9a-bc11-4d5a429a8da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264805919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.264805919
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.331407703
Short name T528
Test name
Test status
Simulation time 583547546 ps
CPU time 7.74 seconds
Started Jul 19 05:43:36 PM PDT 24
Finished Jul 19 05:43:45 PM PDT 24
Peak memory 214568 kb
Host smart-0cdfff2e-f8b3-45b7-b2b3-9c89f4fcc226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331407703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.331407703
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3210252708
Short name T699
Test name
Test status
Simulation time 2101063251 ps
CPU time 10.65 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:52 PM PDT 24
Peak memory 226164 kb
Host smart-377a135b-71d6-449b-be82-b596165336d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210252708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3210252708
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2605755859
Short name T547
Test name
Test status
Simulation time 653156179 ps
CPU time 13.18 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:54 PM PDT 24
Peak memory 226148 kb
Host smart-2a27509d-4463-4774-9930-fb31c175046e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605755859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2605755859
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3426241979
Short name T417
Test name
Test status
Simulation time 217780411 ps
CPU time 6.18 seconds
Started Jul 19 05:43:36 PM PDT 24
Finished Jul 19 05:43:44 PM PDT 24
Peak memory 218300 kb
Host smart-0daa5910-0f48-4e6c-b357-e4b4d54f06c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426241979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
426241979
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2275176104
Short name T797
Test name
Test status
Simulation time 2717392114 ps
CPU time 6.95 seconds
Started Jul 19 05:43:36 PM PDT 24
Finished Jul 19 05:43:45 PM PDT 24
Peak memory 225028 kb
Host smart-fc5c6822-0f45-427d-b383-272cb6c5b4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275176104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2275176104
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.955357930
Short name T21
Test name
Test status
Simulation time 27978709 ps
CPU time 1.86 seconds
Started Jul 19 05:43:39 PM PDT 24
Finished Jul 19 05:43:44 PM PDT 24
Peak memory 214068 kb
Host smart-2872fabc-4e0d-4f45-8674-64e7a2f534dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955357930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.955357930
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2421907059
Short name T410
Test name
Test status
Simulation time 959826186 ps
CPU time 28.72 seconds
Started Jul 19 05:43:36 PM PDT 24
Finished Jul 19 05:44:06 PM PDT 24
Peak memory 251092 kb
Host smart-02f96ff3-c975-4a90-aeef-bd3b40c4a3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421907059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2421907059
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3826537587
Short name T591
Test name
Test status
Simulation time 68338331 ps
CPU time 7 seconds
Started Jul 19 05:43:37 PM PDT 24
Finished Jul 19 05:43:46 PM PDT 24
Peak memory 246396 kb
Host smart-be1580f9-0039-4cbf-ba8a-9176ea616c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826537587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3826537587
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3549671566
Short name T60
Test name
Test status
Simulation time 1413907998 ps
CPU time 54.11 seconds
Started Jul 19 05:43:37 PM PDT 24
Finished Jul 19 05:44:34 PM PDT 24
Peak memory 247520 kb
Host smart-72fece89-6824-432f-b6cb-679603224db2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549671566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3549671566
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.35731823
Short name T639
Test name
Test status
Simulation time 37095006 ps
CPU time 0.96 seconds
Started Jul 19 05:43:38 PM PDT 24
Finished Jul 19 05:43:42 PM PDT 24
Peak memory 211912 kb
Host smart-b6ddec9d-07a3-490e-aa54-5873a8cddac7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35731823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_volatile_unlock_smoke.35731823
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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