Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119931501

1

T1

3480

T2

2074

T3

1260

auto[1]

1458266

1

T1

594

T4

297

T11

1386

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119932699

1

T1

3579

T2

2074

T3

1260

auto[1]

1457068

1

T1

495

T4

594

T11

1188

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7760884	1			T1	1056		T2	579		T3	94
auto[IdleSt]	24588851	1			T1	866		T2	533		T3	16
auto[ClkMuxSt]	38235	1			T1	11		T2	5		T3	1
auto[CntIncrSt]	38000	1			T1	11		T2	5		T3	1
auto[CntProgSt]	1786709	1			T1	22		T2	31		T3	2
auto[TransCheckSt]	29785	1			T2	5		T3	1		T10	1
auto[TokenHashSt]	51234134	1			T2	115		T3	12		T10	12
auto[FlashRmaSt]	37722	1			T2	5		T11	37		T13	1
auto[TokenCheck0St]	13607	1			T2	5		T11	37		T13	1
auto[TokenCheck1St]	10110	1			T2	5		T11	23		T13	1
auto[TransProgSt]	488936	1			T2	30		T11	1587		T13	6
auto[PostTransSt]	15158309	1			T1	631		T2	756		T3	1133
auto[ScrapSt]	203565	1			T41	3		T17	448		T42	552
auto[EscalateSt]	7273833	1			T1	1477		T4	1181		T11	3264
auto[InvalidSt]	12725027	1			T11	1008		T23	1082		T26	4868

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2060	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12725027	1			T11	1008		T23	1082		T26	4868
EscalateSt	7273833	1			T1	1477		T4	1181		T11	3264
ScrapSt	203565	1			T41	3		T17	448		T42	552
PostTransSt	15158309	1			T1	631		T2	756		T3	1133
TransProgSt	488936	1			T2	30		T11	1587		T13	6
TokenCheck1St	10110	1			T2	5		T11	23		T13	1
TokenCheck0St	13607	1			T2	5		T11	37		T13	1
FlashRmaSt	37722	1			T2	5		T11	37		T13	1
TokenHashSt	51234134	1			T2	115		T3	12		T10	12
TransCheckSt	29785	1			T2	5		T3	1		T10	1
CntProgSt	1786709	1			T1	22		T2	31		T3	2
CntIncrSt	38000	1			T1	11		T2	5		T3	1
ClkMuxSt	38235	1			T1	11		T2	5		T3	1
IdleSt	24588851	1			T1	866		T2	533		T3	16
ResetSt	7760884	1			T1	1056		T2	579		T3	94
arcs[ResetSt=>IdleSt]	58094	1			T1	12		T2	5		T3	1
arcs[IdleSt=>ScrapSt]	273	1			T41	1		T17	1		T42	1
arcs[IdleSt=>ClkMuxSt]	38049	1			T1	11		T2	5		T3	1
arcs[ClkMuxSt=>CntIncrSt]	38000	1			T1	11		T2	5		T3	1
arcs[CntIncrSt=>PostTransSt]	2134	1			T15	11		T16	12		T17	16
arcs[CntIncrSt=>CntProgSt]	35804	1			T1	11		T2	5		T3	1
arcs[CntProgSt=>PostTransSt]	4934	1			T1	11		T4	9		T11	13
arcs[CntProgSt=>TransCheckSt]	29785	1			T2	5		T3	1		T10	1
arcs[TransCheckSt=>PostTransSt]	4032	1			T15	10		T16	13		T17	11
arcs[TransCheckSt=>TokenHashSt]	25645	1			T2	5		T3	1		T10	1
arcs[TokenHashSt=>PostTransSt]	11274	1			T3	1		T10	1		T11	5
arcs[TokenHashSt=>FlashRmaSt]	13711	1			T2	5		T11	37		T13	1
arcs[FlashRmaSt=>TokenCheck0St]	13607	1			T2	5		T11	37		T13	1
arcs[TokenCheck0St=>PostTransSt]	3469	1			T11	14		T15	10		T16	6
arcs[TokenCheck0St=>TokenCheck1St]	10110	1			T2	5		T11	23		T13	1
arcs[TokenCheck1St=>PostTransSt]	618	1			T15	1		T16	2		T17	3
arcs[TransProgSt=>PostTransSt]	8618	1			T2	5		T11	23		T13	1
arcs[IdleSt=>EscalateSt]	233	1			T53	3		T41	3		T25	7
arcs[ClkMuxSt=>EscalateSt]	49	1			T53	2		T41	4		T25	1
arcs[CntIncrSt=>EscalateSt]	62	1			T53	1		T41	3		T25	1
arcs[CntProgSt=>EscalateSt]	1085	1			T14	22		T53	17		T41	25
arcs[TransCheckSt=>EscalateSt]	108	1			T14	1		T41	1		T19	1
arcs[TokenHashSt=>EscalateSt]	659	1			T14	7		T53	12		T41	4
arcs[FlashRmaSt=>EscalateSt]	104	1			T14	1		T53	2		T41	2
arcs[TokenCheck0St=>EscalateSt]	28	1			T53	1		T25	1		T54	2
arcs[TokenCheck1St=>EscalateSt]	163	1			T14	4		T53	3		T41	3
arcs[TransProgSt=>EscalateSt]	711	1			T14	15		T53	9		T41	15
arcs[PostTransSt=>EscalateSt]	5136	1			T1	11		T4	9		T11	13
arcs[InvalidSt=>EscalateSt]	15224	1			T11	13		T23	7		T26	66

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7760739	1			T1	1056		T2	579		T3	94
auto[0]	auto[IdleSt]	24588700	1			T1	866		T2	533		T3	16
auto[0]	auto[ClkMuxSt]	38203	1			T1	11		T2	5		T3	1
auto[0]	auto[CntIncrSt]	37957	1			T1	11		T2	5		T3	1
auto[0]	auto[CntProgSt]	1785968	1			T1	22		T2	31		T3	2
auto[0]	auto[TransCheckSt]	29719	1			T2	5		T3	1		T10	1
auto[0]	auto[TokenHashSt]	51233695	1			T2	115		T3	12		T10	12
auto[0]	auto[FlashRmaSt]	37653	1			T2	5		T11	37		T13	1
auto[0]	auto[TokenCheck0St]	13590	1			T2	5		T11	37		T13	1
auto[0]	auto[TokenCheck1St]	9999	1			T2	5		T11	23		T13	1
auto[0]	auto[TransProgSt]	488453	1			T2	30		T11	1587		T13	6
auto[0]	auto[PostTransSt]	15155705	1			T1	625		T2	756		T3	1133
auto[0]	auto[ScrapSt]	203524	1			T41	3		T17	448		T42	552
auto[0]	auto[EscalateSt]	5828126	1			T1	889		T4	887		T11	1892
auto[0]	auto[InvalidSt]	12717410	1			T11	1002		T23	1081		T26	4836
auto[1]	auto[ResetSt]	145	1			T14	2		T53	1		T41	3
auto[1]	auto[IdleSt]	151	1			T53	3		T41	1		T25	5
auto[1]	auto[ClkMuxSt]	32	1			T53	1		T41	4		T159	1
auto[1]	auto[CntIncrSt]	43	1			T41	1		T25	1		T19	1
auto[1]	auto[CntProgSt]	741	1			T14	17		T53	10		T41	19
auto[1]	auto[TransCheckSt]	66	1			T41	1		T54	4		T159	1
auto[1]	auto[TokenHashSt]	439	1			T14	3		T53	9		T41	3
auto[1]	auto[FlashRmaSt]	69	1			T14	1		T53	2		T25	1
auto[1]	auto[TokenCheck0St]	17	1			T53	1		T54	1		T159	1
auto[1]	auto[TokenCheck1St]	111	1			T14	3		T53	3		T41	1
auto[1]	auto[TransProgSt]	483	1			T14	11		T53	8		T41	12
auto[1]	auto[PostTransSt]	2604	1			T1	6		T4	3		T11	8
auto[1]	auto[ScrapSt]	41	1			T19	1		T206	2		T207	1
auto[1]	auto[EscalateSt]	1445707	1			T1	588		T4	294		T11	1372
auto[1]	auto[InvalidSt]	7617	1			T11	6		T23	1		T26	32

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7760743	1			T1	1056		T2	579		T3	94
auto[0]	auto[IdleSt]	24588696	1			T1	866		T2	533		T3	16
auto[0]	auto[ClkMuxSt]	38200	1			T1	11		T2	5		T3	1
auto[0]	auto[CntIncrSt]	37954	1			T1	11		T2	5		T3	1
auto[0]	auto[CntProgSt]	1785986	1			T1	22		T2	31		T3	2
auto[0]	auto[TransCheckSt]	29701	1			T2	5		T3	1		T10	1
auto[0]	auto[TokenHashSt]	51233693	1			T2	115		T3	12		T10	12
auto[0]	auto[FlashRmaSt]	37660	1			T2	5		T11	37		T13	1
auto[0]	auto[TokenCheck0St]	13586	1			T2	5		T11	37		T13	1
auto[0]	auto[TokenCheck1St]	10003	1			T2	5		T11	23		T13	1
auto[0]	auto[TransProgSt]	488454	1			T2	30		T11	1587		T13	6
auto[0]	auto[PostTransSt]	15155713	1			T1	626		T2	756		T3	1133
auto[0]	auto[ScrapSt]	203520	1			T41	2		T17	448		T42	552
auto[0]	auto[EscalateSt]	5829310	1			T1	987		T4	593		T11	2088
auto[0]	auto[InvalidSt]	12717420	1			T11	1001		T23	1076		T26	4834
auto[1]	auto[ResetSt]	141	1			T14	2		T53	1		T41	3
auto[1]	auto[IdleSt]	155	1			T53	2		T41	3		T25	3
auto[1]	auto[ClkMuxSt]	35	1			T53	2		T41	3		T25	1
auto[1]	auto[CntIncrSt]	46	1			T53	1		T41	3		T25	1
auto[1]	auto[CntProgSt]	723	1			T14	13		T53	11		T41	16
auto[1]	auto[TransCheckSt]	84	1			T14	1		T41	1		T19	1
auto[1]	auto[TokenHashSt]	441	1			T14	4		T53	8		T41	2
auto[1]	auto[FlashRmaSt]	62	1			T53	1		T41	2		T25	1
auto[1]	auto[TokenCheck0St]	21	1			T53	1		T25	1		T54	2
auto[1]	auto[TokenCheck1St]	107	1			T14	1		T53	1		T41	3
auto[1]	auto[TransProgSt]	482	1			T14	6		T53	6		T41	9
auto[1]	auto[PostTransSt]	2596	1			T1	5		T4	6		T11	5
auto[1]	auto[ScrapSt]	45	1			T41	1		T19	2		T54	1
auto[1]	auto[EscalateSt]	1444523	1			T1	490		T4	588		T11	1176
auto[1]	auto[InvalidSt]	7607	1			T11	7		T23	6		T26	34