Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49852 |
1 |
|
|
T1 |
72 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
1818 |
1 |
|
|
T1 |
13 |
|
T13 |
10 |
|
T14 |
12 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51028 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
642 |
1 |
|
|
T19 |
11 |
|
T44 |
12 |
|
T45 |
24 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49953 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
50 |
auto[1] |
1717 |
1 |
|
|
T3 |
8 |
|
T11 |
1 |
|
T29 |
3 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49855 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
54 |
auto[1] |
1815 |
1 |
|
|
T3 |
4 |
|
T11 |
1 |
|
T29 |
6 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49913 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
53 |
auto[1] |
1757 |
1 |
|
|
T3 |
5 |
|
T4 |
2 |
|
T29 |
4 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
46990 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
no_err_inj |
4680 |
1 |
|
|
T4 |
2 |
|
T11 |
6 |
|
T5 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49892 |
1 |
|
|
T1 |
77 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
1778 |
1 |
|
|
T1 |
8 |
|
T13 |
9 |
|
T14 |
13 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51084 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
586 |
1 |
|
|
T19 |
12 |
|
T44 |
14 |
|
T45 |
18 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36202 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
15468 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49874 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
54 |
auto[1] |
1796 |
1 |
|
|
T3 |
4 |
|
T4 |
3 |
|
T11 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49870 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
53 |
auto[1] |
1800 |
1 |
|
|
T3 |
5 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49831 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
52 |
auto[1] |
1839 |
1 |
|
|
T3 |
6 |
|
T4 |
1 |
|
T29 |
5 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49881 |
1 |
|
|
T1 |
78 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
1789 |
1 |
|
|
T1 |
7 |
|
T13 |
11 |
|
T14 |
18 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49346 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
2324 |
1 |
|
|
T9 |
13 |
|
T24 |
14 |
|
T30 |
9 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51006 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
664 |
1 |
|
|
T19 |
22 |
|
T44 |
16 |
|
T45 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51073 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
597 |
1 |
|
|
T19 |
14 |
|
T44 |
16 |
|
T45 |
22 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51057 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
613 |
1 |
|
|
T19 |
17 |
|
T44 |
7 |
|
T45 |
12 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48942 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
2728 |
1 |
|
|
T4 |
15 |
|
T11 |
11 |
|
T5 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48033 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
3637 |
1 |
|
|
T10 |
59 |
|
T15 |
93 |
|
T23 |
52 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49828 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
46 |
auto[1] |
1842 |
1 |
|
|
T3 |
12 |
|
T29 |
9 |
|
T21 |
6 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49849 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
49 |
auto[1] |
1821 |
1 |
|
|
T3 |
9 |
|
T4 |
2 |
|
T5 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49888 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
53 |
auto[1] |
1782 |
1 |
|
|
T3 |
5 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49968 |
1 |
|
|
T1 |
75 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
1702 |
1 |
|
|
T1 |
10 |
|
T13 |
8 |
|
T14 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46179 |
1 |
|
|
T1 |
69 |
|
T3 |
58 |
|
T4 |
15 |
auto[1] |
5491 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T13 |
11 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47848 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
3822 |
1 |
|
|
T12 |
52 |
|
T22 |
61 |
|
T16 |
89 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51670 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49874 |
1 |
|
|
T1 |
76 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
1796 |
1 |
|
|
T1 |
9 |
|
T13 |
15 |
|
T14 |
10 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49873 |
1 |
|
|
T1 |
72 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
1797 |
1 |
|
|
T1 |
13 |
|
T13 |
13 |
|
T14 |
11 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49905 |
1 |
|
|
T1 |
76 |
|
T2 |
62 |
|
T3 |
58 |
auto[1] |
1765 |
1 |
|
|
T1 |
9 |
|
T13 |
13 |
|
T14 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
45636 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[0] |
no_err_inj |
3306 |
1 |
|
|
T18 |
19 |
|
T21 |
23 |
|
T14 |
14 |
auto[1] |
err_inj |
1354 |
1 |
|
|
T4 |
13 |
|
T11 |
5 |
|
T5 |
6 |
auto[1] |
no_err_inj |
1374 |
1 |
|
|
T4 |
2 |
|
T11 |
6 |
|
T5 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47284 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
49 |
auto[0] |
auto[1] |
1658 |
1 |
|
|
T3 |
9 |
|
T29 |
9 |
|
T21 |
11 |
auto[1] |
auto[0] |
2565 |
1 |
|
|
T4 |
13 |
|
T11 |
11 |
|
T5 |
12 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T82 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47306 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
53 |
auto[0] |
auto[1] |
1636 |
1 |
|
|
T3 |
5 |
|
T29 |
7 |
|
T21 |
9 |
auto[1] |
auto[0] |
2564 |
1 |
|
|
T4 |
14 |
|
T11 |
9 |
|
T5 |
12 |
auto[1] |
auto[1] |
164 |
1 |
|
|
T4 |
1 |
|
T11 |
2 |
|
T5 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47296 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
53 |
auto[0] |
auto[1] |
1646 |
1 |
|
|
T3 |
5 |
|
T29 |
5 |
|
T21 |
8 |
auto[1] |
auto[0] |
2592 |
1 |
|
|
T4 |
11 |
|
T11 |
11 |
|
T5 |
12 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T4 |
4 |
|
T5 |
1 |
|
T82 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47256 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
54 |
auto[0] |
auto[1] |
1686 |
1 |
|
|
T3 |
4 |
|
T29 |
6 |
|
T21 |
12 |
auto[1] |
auto[0] |
2599 |
1 |
|
|
T4 |
15 |
|
T11 |
10 |
|
T5 |
13 |
auto[1] |
auto[1] |
129 |
1 |
|
|
T11 |
1 |
|
T82 |
1 |
|
T94 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47346 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
53 |
auto[0] |
auto[1] |
1596 |
1 |
|
|
T3 |
5 |
|
T29 |
4 |
|
T21 |
9 |
auto[1] |
auto[0] |
2567 |
1 |
|
|
T4 |
13 |
|
T11 |
11 |
|
T5 |
13 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T4 |
2 |
|
T87 |
1 |
|
T82 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47376 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
50 |
auto[0] |
auto[1] |
1566 |
1 |
|
|
T3 |
8 |
|
T29 |
3 |
|
T21 |
6 |
auto[1] |
auto[0] |
2577 |
1 |
|
|
T4 |
15 |
|
T11 |
10 |
|
T5 |
13 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T11 |
1 |
|
T87 |
1 |
|
T82 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35147 |
1 |
|
|
T1 |
72 |
|
T2 |
62 |
|
T3 |
58 |
auto[0] |
auto[1] |
1055 |
1 |
|
|
T1 |
13 |
|
T13 |
10 |
|
T82 |
6 |
auto[1] |
auto[0] |
14705 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
763 |
1 |
|
|
T14 |
12 |
|
T85 |
6 |
|
T41 |
6 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35162 |
1 |
|
|
T1 |
77 |
|
T2 |
62 |
|
T3 |
58 |
auto[0] |
auto[1] |
1040 |
1 |
|
|
T1 |
8 |
|
T13 |
9 |
|
T82 |
10 |
auto[1] |
auto[0] |
14730 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
738 |
1 |
|
|
T14 |
13 |
|
T85 |
12 |
|
T41 |
14 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34871 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[0] |
auto[1] |
1331 |
1 |
|
|
T9 |
13 |
|
T24 |
14 |
|
T30 |
9 |
auto[1] |
auto[0] |
14475 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T21 |
9 |
auto[1] |
auto[1] |
993 |
1 |
|
|
T25 |
6 |
|
T27 |
12 |
|
T28 |
18 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35163 |
1 |
|
|
T1 |
78 |
|
T2 |
62 |
|
T3 |
58 |
auto[0] |
auto[1] |
1039 |
1 |
|
|
T1 |
7 |
|
T13 |
11 |
|
T82 |
2 |
auto[1] |
auto[0] |
14718 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T14 |
18 |
|
T85 |
5 |
|
T41 |
14 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31470 |
1 |
|
|
T1 |
69 |
|
T3 |
58 |
|
T9 |
13 |
auto[0] |
auto[1] |
4732 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T13 |
11 |
auto[1] |
auto[0] |
14709 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
759 |
1 |
|
|
T14 |
10 |
|
T85 |
9 |
|
T41 |
17 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35100 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
49 |
auto[0] |
auto[1] |
1102 |
1 |
|
|
T3 |
9 |
|
T29 |
9 |
|
T21 |
11 |
auto[1] |
auto[0] |
14749 |
1 |
|
|
T4 |
13 |
|
T5 |
12 |
|
T25 |
6 |
auto[1] |
auto[1] |
719 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T233 |
8 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35133 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
46 |
auto[0] |
auto[1] |
1069 |
1 |
|
|
T3 |
12 |
|
T29 |
9 |
|
T21 |
6 |
auto[1] |
auto[0] |
14695 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
773 |
1 |
|
|
T233 |
11 |
|
T85 |
13 |
|
T97 |
4 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35130 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
53 |
auto[0] |
auto[1] |
1072 |
1 |
|
|
T3 |
5 |
|
T11 |
2 |
|
T29 |
7 |
auto[1] |
auto[0] |
14740 |
1 |
|
|
T4 |
14 |
|
T5 |
12 |
|
T25 |
6 |
auto[1] |
auto[1] |
728 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T233 |
9 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35098 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
54 |
auto[0] |
auto[1] |
1104 |
1 |
|
|
T3 |
4 |
|
T11 |
1 |
|
T29 |
4 |
auto[1] |
auto[0] |
14776 |
1 |
|
|
T4 |
12 |
|
T5 |
10 |
|
T25 |
6 |
auto[1] |
auto[1] |
692 |
1 |
|
|
T4 |
3 |
|
T5 |
3 |
|
T233 |
13 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35104 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
54 |
auto[0] |
auto[1] |
1098 |
1 |
|
|
T3 |
4 |
|
T11 |
1 |
|
T29 |
6 |
auto[1] |
auto[0] |
14751 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
717 |
1 |
|
|
T233 |
9 |
|
T85 |
10 |
|
T97 |
7 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35170 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
50 |
auto[0] |
auto[1] |
1032 |
1 |
|
|
T3 |
8 |
|
T11 |
1 |
|
T29 |
3 |
auto[1] |
auto[0] |
14783 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
685 |
1 |
|
|
T233 |
5 |
|
T85 |
7 |
|
T97 |
7 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35163 |
1 |
|
|
T1 |
76 |
|
T2 |
62 |
|
T3 |
58 |
auto[0] |
auto[1] |
1039 |
1 |
|
|
T1 |
9 |
|
T13 |
13 |
|
T82 |
8 |
auto[1] |
auto[0] |
14742 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
726 |
1 |
|
|
T14 |
9 |
|
T85 |
4 |
|
T41 |
9 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35177 |
1 |
|
|
T1 |
72 |
|
T2 |
62 |
|
T3 |
58 |
auto[0] |
auto[1] |
1025 |
1 |
|
|
T1 |
13 |
|
T13 |
13 |
|
T82 |
6 |
auto[1] |
auto[0] |
14696 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T25 |
6 |
auto[1] |
auto[1] |
772 |
1 |
|
|
T14 |
11 |
|
T85 |
9 |
|
T41 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34700 |
1 |
|
|
T1 |
85 |
|
T2 |
62 |
|
T3 |
58 |
auto[0] |
auto[1] |
1502 |
1 |
|
|
T11 |
11 |
|
T87 |
15 |
|
T82 |
14 |
auto[1] |
auto[0] |
14242 |
1 |
|
|
T25 |
6 |
|
T27 |
12 |
|
T28 |
18 |
auto[1] |
auto[1] |
1226 |
1 |
|
|
T4 |
15 |
|
T5 |
13 |
|
T79 |
46 |