Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100720469

1

T1

33719

T2

19114

T3

13715

auto[1]

1356267

1

T1

891

T3

2673

T4

196

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100738829

1

T1

34214

T2

19114

T3

14408

auto[1]

1337907

1

T1

396

T3

1980

T4

588

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6926919	1			T1	11642		T2	5420		T3	5968
auto[IdleSt]	21371968	1			T1	2464		T2	2208		T3	1008
auto[ClkMuxSt]	34496	1			T1	85		T2	62		T4	2
auto[CntIncrSt]	34254	1			T1	85		T2	62		T4	2
auto[CntProgSt]	1718194	1			T1	5120		T2	124		T4	6
auto[TransCheckSt]	26535	1			T1	59		T2	62		T4	2
auto[TokenHashSt]	40870819	1			T1	1012		T2	1757		T4	33
auto[FlashRmaSt]	33505	1			T1	15		T4	2		T10	29
auto[TokenCheck0St]	12103	1			T1	15		T4	2		T10	23
auto[TokenCheck1St]	8945	1			T1	7		T4	2		T10	21
auto[TransProgSt]	450935	1			T1	674		T4	13		T10	51
auto[PostTransSt]	13010900	1			T1	11781		T2	9419		T4	3539
auto[ScrapSt]	83592	1			T15	3		T39	3		T40	2
auto[EscalateSt]	6572610	1			T1	1651		T3	6009		T4	9476
auto[InvalidSt]	10919089	1			T3	3398		T4	10788		T11	343

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1872	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10919089	1			T3	3398		T4	10788		T11	343
EscalateSt	6572610	1			T1	1651		T3	6009		T4	9476
ScrapSt	83592	1			T15	3		T39	3		T40	2
PostTransSt	13010900	1			T1	11781		T2	9419		T4	3539
TransProgSt	450935	1			T1	674		T4	13		T10	51
TokenCheck1St	8945	1			T1	7		T4	2		T10	21
TokenCheck0St	12103	1			T1	15		T4	2		T10	23
FlashRmaSt	33505	1			T1	15		T4	2		T10	29
TokenHashSt	40870819	1			T1	1012		T2	1757		T4	33
TransCheckSt	26535	1			T1	59		T2	62		T4	2
CntProgSt	1718194	1			T1	5120		T2	124		T4	6
CntIncrSt	34254	1			T1	85		T2	62		T4	2
ClkMuxSt	34496	1			T1	85		T2	62		T4	2
IdleSt	21371968	1			T1	2464		T2	2208		T3	1008
ResetSt	6926919	1			T1	11642		T2	5420		T3	5968
arcs[ResetSt=>IdleSt]	51962	1			T1	86		T2	63		T3	53
arcs[IdleSt=>ScrapSt]	279	1			T15	1		T39	1		T40	2
arcs[IdleSt=>ClkMuxSt]	34314	1			T1	85		T2	62		T4	2
arcs[ClkMuxSt=>CntIncrSt]	34254	1			T1	85		T2	62		T4	2
arcs[CntIncrSt=>PostTransSt]	1800	1			T1	13		T13	13		T14	11
arcs[CntIncrSt=>CntProgSt]	32400	1			T1	72		T2	62		T4	2
arcs[CntProgSt=>PostTransSt]	4749	1			T1	13		T9	13		T24	14
arcs[CntProgSt=>TransCheckSt]	26535	1			T1	59		T2	62		T4	2
arcs[TransCheckSt=>PostTransSt]	3663	1			T1	9		T12	24		T13	13
arcs[TransCheckSt=>TokenHashSt]	22768	1			T1	50		T2	62		T4	2
arcs[TokenHashSt=>PostTransSt]	9944	1			T1	35		T2	62		T12	11
arcs[TokenHashSt=>FlashRmaSt]	12212	1			T1	15		T4	2		T10	27
arcs[FlashRmaSt=>TokenCheck0St]	12103	1			T1	15		T4	2		T10	23
arcs[TokenCheck0St=>PostTransSt]	3122	1			T1	8		T12	12		T13	8
arcs[TokenCheck0St=>TokenCheck1St]	8945	1			T1	7		T4	2		T10	21
arcs[TokenCheck1St=>PostTransSt]	628	1			T12	5		T13	1		T22	9
arcs[TransProgSt=>PostTransSt]	7452	1			T1	7		T4	2		T11	6
arcs[IdleSt=>EscalateSt]	207	1			T10	5		T15	5		T39	5
arcs[ClkMuxSt=>EscalateSt]	60	1			T10	2		T15	1		T23	1
arcs[CntIncrSt=>EscalateSt]	54	1			T10	2		T15	2		T51	1
arcs[CntProgSt=>EscalateSt]	1116	1			T10	15		T15	9		T23	21
arcs[TransCheckSt=>EscalateSt]	104	1			T15	10		T23	1		T39	1
arcs[TokenHashSt=>EscalateSt]	612	1			T10	1		T14	3		T15	32
arcs[FlashRmaSt=>EscalateSt]	109	1			T10	4		T15	3		T23	1
arcs[TokenCheck0St=>EscalateSt]	36	1			T10	2		T15	1		T54	1
arcs[TokenCheck1St=>EscalateSt]	142	1			T10	3		T15	2		T23	5
arcs[TransProgSt=>EscalateSt]	723	1			T10	18		T15	10		T23	10
arcs[PostTransSt=>EscalateSt]	4958	1			T1	13		T9	13		T24	14
arcs[InvalidSt=>EscalateSt]	13157	1			T3	47		T4	8		T11	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6926745	1			T1	11642		T2	5420		T3	5968
auto[0]	auto[IdleSt]	21371827	1			T1	2464		T2	2208		T3	1008
auto[0]	auto[ClkMuxSt]	34456	1			T1	85		T2	62		T4	2
auto[0]	auto[CntIncrSt]	34207	1			T1	85		T2	62		T4	2
auto[0]	auto[CntProgSt]	1717441	1			T1	5120		T2	124		T4	6
auto[0]	auto[TransCheckSt]	26459	1			T1	59		T2	62		T4	2
auto[0]	auto[TokenHashSt]	40870402	1			T1	1012		T2	1757		T4	33
auto[0]	auto[FlashRmaSt]	33429	1			T1	15		T4	2		T10	28
auto[0]	auto[TokenCheck0St]	12083	1			T1	15		T4	2		T10	22
auto[0]	auto[TokenCheck1St]	8851	1			T1	7		T4	2		T10	19
auto[0]	auto[TransProgSt]	450453	1			T1	674		T4	13		T10	39
auto[0]	auto[PostTransSt]	13008390	1			T1	11772		T2	9419		T4	3539
auto[0]	auto[ScrapSt]	83549	1			T15	3		T39	3		T40	2
auto[0]	auto[EscalateSt]	5227845	1			T1	769		T3	3363		T4	9282
auto[0]	auto[InvalidSt]	10912460	1			T3	3371		T4	10786		T11	341
auto[1]	auto[ResetSt]	174	1			T10	4		T15	3		T23	3
auto[1]	auto[IdleSt]	141	1			T10	2		T15	2		T39	4
auto[1]	auto[ClkMuxSt]	40	1			T10	2		T15	1		T54	1
auto[1]	auto[CntIncrSt]	47	1			T10	2		T15	1		T51	1
auto[1]	auto[CntProgSt]	753	1			T10	7		T15	6		T23	14
auto[1]	auto[TransCheckSt]	76	1			T15	6		T39	1		T54	2
auto[1]	auto[TokenHashSt]	417	1			T14	1		T15	16		T23	3
auto[1]	auto[FlashRmaSt]	76	1			T10	1		T15	2		T23	1
auto[1]	auto[TokenCheck0St]	20	1			T10	1		T15	1		T230	1
auto[1]	auto[TokenCheck1St]	94	1			T10	2		T15	1		T23	2
auto[1]	auto[TransProgSt]	482	1			T10	12		T15	8		T23	7
auto[1]	auto[PostTransSt]	2510	1			T1	9		T9	7		T24	8
auto[1]	auto[ScrapSt]	43	1			T51	1		T54	1		T231	1
auto[1]	auto[EscalateSt]	1344765	1			T1	882		T3	2646		T4	194
auto[1]	auto[InvalidSt]	6629	1			T3	27		T4	2		T11	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6926760	1			T1	11642		T2	5420		T3	5968
auto[0]	auto[IdleSt]	21371821	1			T1	2464		T2	2208		T3	1008
auto[0]	auto[ClkMuxSt]	34455	1			T1	85		T2	62		T4	2
auto[0]	auto[CntIncrSt]	34227	1			T1	85		T2	62		T4	2
auto[0]	auto[CntProgSt]	1717448	1			T1	5120		T2	124		T4	6
auto[0]	auto[TransCheckSt]	26469	1			T1	59		T2	62		T4	2
auto[0]	auto[TokenHashSt]	40870413	1			T1	1012		T2	1757		T4	33
auto[0]	auto[FlashRmaSt]	33437	1			T1	15		T4	2		T10	26
auto[0]	auto[TokenCheck0St]	12074	1			T1	15		T4	2		T10	21
auto[0]	auto[TokenCheck1St]	8846	1			T1	7		T4	2		T10	20
auto[0]	auto[TransProgSt]	450438	1			T1	674		T4	13		T10	43
auto[0]	auto[PostTransSt]	13008399	1			T1	11777		T2	9419		T4	3539
auto[0]	auto[ScrapSt]	83552	1			T15	2		T39	2		T40	2
auto[0]	auto[EscalateSt]	5246057	1			T1	1259		T3	4049		T4	8894
auto[0]	auto[InvalidSt]	10912561	1			T3	3378		T4	10782		T11	340
auto[1]	auto[ResetSt]	159	1			T10	5		T15	3		T23	4
auto[1]	auto[IdleSt]	147	1			T10	3		T15	4		T39	3
auto[1]	auto[ClkMuxSt]	41	1			T10	2		T23	1		T54	1
auto[1]	auto[CntIncrSt]	27	1			T15	1		T230	1		T232	1
auto[1]	auto[CntProgSt]	746	1			T10	12		T15	6		T23	16
auto[1]	auto[TransCheckSt]	66	1			T15	5		T23	1		T39	1
auto[1]	auto[TokenHashSt]	406	1			T10	1		T14	2		T15	24
auto[1]	auto[FlashRmaSt]	68	1			T10	3		T15	2		T51	2
auto[1]	auto[TokenCheck0St]	29	1			T10	2		T54	1		T231	4
auto[1]	auto[TokenCheck1St]	99	1			T10	1		T15	2		T23	4
auto[1]	auto[TransProgSt]	497	1			T10	8		T15	6		T23	7
auto[1]	auto[PostTransSt]	2501	1			T1	4		T9	6		T24	6
auto[1]	auto[ScrapSt]	40	1			T15	1		T39	1		T51	1
auto[1]	auto[EscalateSt]	1326553	1			T1	392		T3	1960		T4	582
auto[1]	auto[InvalidSt]	6528	1			T3	20		T4	6		T11	3