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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.81 97.92 95.56 93.40 97.62 98.52 98.51 96.11


Total test records in report: 992
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T816 /workspace/coverage/default/36.lc_ctrl_errors.571108203 Jul 21 06:26:47 PM PDT 24 Jul 21 06:26:58 PM PDT 24 168041658 ps
T817 /workspace/coverage/default/20.lc_ctrl_smoke.3614228357 Jul 21 06:25:53 PM PDT 24 Jul 21 06:25:56 PM PDT 24 105228244 ps
T818 /workspace/coverage/default/27.lc_ctrl_state_post_trans.591351919 Jul 21 06:26:04 PM PDT 24 Jul 21 06:26:11 PM PDT 24 176159163 ps
T819 /workspace/coverage/default/19.lc_ctrl_state_post_trans.3466634950 Jul 21 06:25:45 PM PDT 24 Jul 21 06:25:54 PM PDT 24 66619153 ps
T820 /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.808767281 Jul 21 06:25:00 PM PDT 24 Jul 21 06:25:23 PM PDT 24 1316957482 ps
T821 /workspace/coverage/default/17.lc_ctrl_jtag_access.2878352013 Jul 21 06:25:46 PM PDT 24 Jul 21 06:25:50 PM PDT 24 272052770 ps
T822 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1007124593 Jul 21 06:27:03 PM PDT 24 Jul 21 06:27:05 PM PDT 24 34794545 ps
T823 /workspace/coverage/default/21.lc_ctrl_errors.2134620099 Jul 21 06:25:55 PM PDT 24 Jul 21 06:26:06 PM PDT 24 258657986 ps
T824 /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1907035268 Jul 21 06:25:47 PM PDT 24 Jul 21 06:25:57 PM PDT 24 1097203236 ps
T825 /workspace/coverage/default/8.lc_ctrl_prog_failure.3262995119 Jul 21 06:25:01 PM PDT 24 Jul 21 06:25:09 PM PDT 24 92989867 ps
T228 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3403843222 Jul 21 06:24:59 PM PDT 24 Jul 21 06:25:04 PM PDT 24 15382010 ps
T826 /workspace/coverage/default/28.lc_ctrl_state_failure.2699158259 Jul 21 06:26:05 PM PDT 24 Jul 21 06:26:29 PM PDT 24 260985491 ps
T827 /workspace/coverage/default/13.lc_ctrl_stress_all.940584841 Jul 21 06:25:22 PM PDT 24 Jul 21 06:28:04 PM PDT 24 18613410987 ps
T828 /workspace/coverage/default/6.lc_ctrl_jtag_access.1618498127 Jul 21 06:24:57 PM PDT 24 Jul 21 06:25:14 PM PDT 24 1015528749 ps
T829 /workspace/coverage/default/30.lc_ctrl_stress_all.4026317068 Jul 21 06:26:18 PM PDT 24 Jul 21 06:29:07 PM PDT 24 4554079894 ps
T830 /workspace/coverage/default/44.lc_ctrl_security_escalation.3763585394 Jul 21 06:26:50 PM PDT 24 Jul 21 06:26:59 PM PDT 24 1024521663 ps
T831 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2993365845 Jul 21 06:25:38 PM PDT 24 Jul 21 06:26:18 PM PDT 24 4015034566 ps
T832 /workspace/coverage/default/17.lc_ctrl_alert_test.2187390037 Jul 21 06:25:47 PM PDT 24 Jul 21 06:25:49 PM PDT 24 26153812 ps
T833 /workspace/coverage/default/39.lc_ctrl_errors.3868428332 Jul 21 06:26:38 PM PDT 24 Jul 21 06:26:51 PM PDT 24 558779149 ps
T834 /workspace/coverage/default/41.lc_ctrl_jtag_access.1568317580 Jul 21 06:26:44 PM PDT 24 Jul 21 06:26:47 PM PDT 24 108278248 ps
T835 /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2816835586 Jul 21 06:26:22 PM PDT 24 Jul 21 06:26:23 PM PDT 24 13815456 ps
T836 /workspace/coverage/default/13.lc_ctrl_security_escalation.1721361100 Jul 21 06:25:22 PM PDT 24 Jul 21 06:25:30 PM PDT 24 256133045 ps
T837 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.246117278 Jul 21 06:25:13 PM PDT 24 Jul 21 06:25:17 PM PDT 24 396425946 ps
T95 /workspace/coverage/default/0.lc_ctrl_sec_cm.1216365776 Jul 21 06:24:35 PM PDT 24 Jul 21 06:24:58 PM PDT 24 336883674 ps
T838 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1794112920 Jul 21 06:25:00 PM PDT 24 Jul 21 06:25:17 PM PDT 24 649486168 ps
T839 /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2778823822 Jul 21 06:24:44 PM PDT 24 Jul 21 06:25:07 PM PDT 24 797623446 ps
T840 /workspace/coverage/default/20.lc_ctrl_alert_test.3030286123 Jul 21 06:25:54 PM PDT 24 Jul 21 06:25:55 PM PDT 24 15070933 ps
T841 /workspace/coverage/default/14.lc_ctrl_security_escalation.3842546534 Jul 21 06:25:27 PM PDT 24 Jul 21 06:25:37 PM PDT 24 618787437 ps
T842 /workspace/coverage/default/3.lc_ctrl_jtag_errors.2215887562 Jul 21 06:24:46 PM PDT 24 Jul 21 06:25:15 PM PDT 24 876284780 ps
T843 /workspace/coverage/default/11.lc_ctrl_prog_failure.2420267814 Jul 21 06:25:14 PM PDT 24 Jul 21 06:25:17 PM PDT 24 42604237 ps
T844 /workspace/coverage/default/21.lc_ctrl_stress_all.3711951035 Jul 21 06:25:55 PM PDT 24 Jul 21 06:31:23 PM PDT 24 167295278808 ps
T845 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3301585416 Jul 21 06:25:01 PM PDT 24 Jul 21 06:25:17 PM PDT 24 2070542643 ps
T846 /workspace/coverage/default/12.lc_ctrl_jtag_access.3615230007 Jul 21 06:25:23 PM PDT 24 Jul 21 06:25:30 PM PDT 24 6644337723 ps
T847 /workspace/coverage/default/26.lc_ctrl_errors.2060789589 Jul 21 06:26:06 PM PDT 24 Jul 21 06:26:17 PM PDT 24 655478190 ps
T848 /workspace/coverage/default/9.lc_ctrl_jtag_access.233177826 Jul 21 06:25:08 PM PDT 24 Jul 21 06:25:21 PM PDT 24 959880266 ps
T849 /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3745914109 Jul 21 06:24:45 PM PDT 24 Jul 21 06:24:53 PM PDT 24 504812138 ps
T850 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1155404679 Jul 21 06:24:46 PM PDT 24 Jul 21 06:25:35 PM PDT 24 13917253876 ps
T851 /workspace/coverage/default/18.lc_ctrl_stress_all.2980090564 Jul 21 06:25:53 PM PDT 24 Jul 21 06:26:58 PM PDT 24 3449056409 ps
T852 /workspace/coverage/default/12.lc_ctrl_prog_failure.1468547437 Jul 21 06:25:16 PM PDT 24 Jul 21 06:25:19 PM PDT 24 329105476 ps
T853 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2579946317 Jul 21 06:24:55 PM PDT 24 Jul 21 06:25:06 PM PDT 24 332536158 ps
T854 /workspace/coverage/default/30.lc_ctrl_security_escalation.2328644862 Jul 21 06:26:18 PM PDT 24 Jul 21 06:26:25 PM PDT 24 1498695855 ps
T855 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4150328986 Jul 21 06:26:25 PM PDT 24 Jul 21 06:26:40 PM PDT 24 1426594214 ps
T170 /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.299567744 Jul 21 06:27:00 PM PDT 24 Jul 21 06:34:33 PM PDT 24 47222468974 ps
T856 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4202725446 Jul 21 06:24:56 PM PDT 24 Jul 21 06:24:58 PM PDT 24 41212386 ps
T78 /workspace/coverage/default/2.lc_ctrl_smoke.2604292026 Jul 21 06:24:38 PM PDT 24 Jul 21 06:24:40 PM PDT 24 43320537 ps
T857 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.917176708 Jul 21 06:26:17 PM PDT 24 Jul 21 06:26:32 PM PDT 24 1599807779 ps
T858 /workspace/coverage/default/3.lc_ctrl_jtag_access.3460110241 Jul 21 06:24:45 PM PDT 24 Jul 21 06:25:00 PM PDT 24 2147349835 ps
T859 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.251571201 Jul 21 06:24:57 PM PDT 24 Jul 21 06:25:30 PM PDT 24 3588971157 ps
T860 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2784129948 Jul 21 06:25:25 PM PDT 24 Jul 21 06:25:29 PM PDT 24 1871870065 ps
T861 /workspace/coverage/default/28.lc_ctrl_errors.2617544884 Jul 21 06:26:07 PM PDT 24 Jul 21 06:26:20 PM PDT 24 216588835 ps
T862 /workspace/coverage/default/14.lc_ctrl_state_post_trans.1589730364 Jul 21 06:25:26 PM PDT 24 Jul 21 06:25:30 PM PDT 24 756571949 ps
T863 /workspace/coverage/default/22.lc_ctrl_state_post_trans.118761070 Jul 21 06:25:57 PM PDT 24 Jul 21 06:26:01 PM PDT 24 79769616 ps
T864 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.122062412 Jul 21 06:25:16 PM PDT 24 Jul 21 06:25:27 PM PDT 24 2342003625 ps
T865 /workspace/coverage/default/16.lc_ctrl_jtag_access.4053710665 Jul 21 06:25:39 PM PDT 24 Jul 21 06:25:43 PM PDT 24 523682874 ps
T866 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.4224711048 Jul 21 06:26:47 PM PDT 24 Jul 21 06:26:58 PM PDT 24 1216789931 ps
T867 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.510180975 Jul 21 06:25:17 PM PDT 24 Jul 21 06:25:24 PM PDT 24 345709719 ps
T868 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.745947160 Jul 21 06:24:40 PM PDT 24 Jul 21 06:25:07 PM PDT 24 734341820 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2352218103 Jul 21 06:22:26 PM PDT 24 Jul 21 06:22:29 PM PDT 24 123768038 ps
T107 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1255626585 Jul 21 06:23:10 PM PDT 24 Jul 21 06:23:29 PM PDT 24 32191416 ps
T116 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3680783591 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:04 PM PDT 24 101895688 ps
T110 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.275179674 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:11 PM PDT 24 24970467 ps
T111 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2754105480 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:39 PM PDT 24 33569161 ps
T869 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3576843383 Jul 21 06:22:20 PM PDT 24 Jul 21 06:22:22 PM PDT 24 134021619 ps
T113 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2018722849 Jul 21 06:23:01 PM PDT 24 Jul 21 06:23:16 PM PDT 24 94092079 ps
T112 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2200799332 Jul 21 06:22:45 PM PDT 24 Jul 21 06:22:56 PM PDT 24 119060277 ps
T202 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3405232797 Jul 21 06:22:54 PM PDT 24 Jul 21 06:23:05 PM PDT 24 30747069 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3587759227 Jul 21 06:22:23 PM PDT 24 Jul 21 06:22:27 PM PDT 24 18652582 ps
T871 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.24986741 Jul 21 06:22:39 PM PDT 24 Jul 21 06:22:46 PM PDT 24 52837868 ps
T108 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2074827312 Jul 21 06:22:23 PM PDT 24 Jul 21 06:22:28 PM PDT 24 352305749 ps
T117 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1881623313 Jul 21 06:22:40 PM PDT 24 Jul 21 06:22:47 PM PDT 24 105878141 ps
T142 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3120735269 Jul 21 06:22:41 PM PDT 24 Jul 21 06:22:51 PM PDT 24 91161909 ps
T217 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1182891048 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:04 PM PDT 24 41920075 ps
T143 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1516599282 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:34 PM PDT 24 1327268299 ps
T123 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1627651304 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:24 PM PDT 24 94625801 ps
T109 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.180178851 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:31 PM PDT 24 110580057 ps
T128 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2483856460 Jul 21 06:22:31 PM PDT 24 Jul 21 06:22:36 PM PDT 24 143061083 ps
T114 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1824036667 Jul 21 06:22:27 PM PDT 24 Jul 21 06:22:31 PM PDT 24 83198462 ps
T872 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1722267413 Jul 21 06:22:27 PM PDT 24 Jul 21 06:22:30 PM PDT 24 43858222 ps
T118 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1921262806 Jul 21 06:23:07 PM PDT 24 Jul 21 06:23:26 PM PDT 24 244120709 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2317041625 Jul 21 06:22:20 PM PDT 24 Jul 21 06:22:24 PM PDT 24 230374879 ps
T139 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2014224513 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:40 PM PDT 24 101309899 ps
T874 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3594690195 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:22 PM PDT 24 40046647 ps
T875 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2540068807 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:48 PM PDT 24 408297404 ps
T876 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1149187520 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:11 PM PDT 24 37912504 ps
T218 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2184194925 Jul 21 06:22:58 PM PDT 24 Jul 21 06:23:11 PM PDT 24 66059312 ps
T140 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4253248851 Jul 21 06:22:40 PM PDT 24 Jul 21 06:22:49 PM PDT 24 97940160 ps
T877 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3158524361 Jul 21 06:22:33 PM PDT 24 Jul 21 06:22:41 PM PDT 24 984662070 ps
T115 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1512546899 Jul 21 06:22:39 PM PDT 24 Jul 21 06:22:49 PM PDT 24 438325782 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.980366528 Jul 21 06:22:39 PM PDT 24 Jul 21 06:23:04 PM PDT 24 1398065486 ps
T119 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1114388543 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:32 PM PDT 24 59171503 ps
T126 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3866274674 Jul 21 06:22:54 PM PDT 24 Jul 21 06:23:05 PM PDT 24 48764533 ps
T131 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3709401164 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:07 PM PDT 24 223811360 ps
T219 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1293086119 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:11 PM PDT 24 75427545 ps
T158 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3854457 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:24 PM PDT 24 141008969 ps
T220 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2459668799 Jul 21 06:22:20 PM PDT 24 Jul 21 06:22:22 PM PDT 24 403070553 ps
T159 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1833120590 Jul 21 06:22:49 PM PDT 24 Jul 21 06:22:59 PM PDT 24 46201080 ps
T160 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1086504527 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:04 PM PDT 24 105941196 ps
T124 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.653571924 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:13 PM PDT 24 64569622 ps
T133 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1595035320 Jul 21 06:22:50 PM PDT 24 Jul 21 06:23:01 PM PDT 24 45713259 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.763541607 Jul 21 06:22:31 PM PDT 24 Jul 21 06:22:34 PM PDT 24 28794727 ps
T141 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1159301443 Jul 21 06:22:40 PM PDT 24 Jul 21 06:22:55 PM PDT 24 2991668886 ps
T221 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1792047338 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:39 PM PDT 24 56254589 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1297643164 Jul 21 06:22:33 PM PDT 24 Jul 21 06:22:41 PM PDT 24 412230701 ps
T881 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3912746392 Jul 21 06:22:41 PM PDT 24 Jul 21 06:22:50 PM PDT 24 258048302 ps
T203 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2856684920 Jul 21 06:22:58 PM PDT 24 Jul 21 06:23:09 PM PDT 24 143630010 ps
T882 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.591972768 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:04 PM PDT 24 118333964 ps
T204 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3525898027 Jul 21 06:22:48 PM PDT 24 Jul 21 06:22:58 PM PDT 24 17345522 ps
T883 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1019123316 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:33 PM PDT 24 2642354005 ps
T222 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3756471982 Jul 21 06:22:48 PM PDT 24 Jul 21 06:22:58 PM PDT 24 101181323 ps
T884 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.475768637 Jul 21 06:22:40 PM PDT 24 Jul 21 06:22:48 PM PDT 24 798928565 ps
T205 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4083804624 Jul 21 06:22:27 PM PDT 24 Jul 21 06:22:30 PM PDT 24 18325554 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.640066610 Jul 21 06:22:47 PM PDT 24 Jul 21 06:22:58 PM PDT 24 331971649 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1399963316 Jul 21 06:22:46 PM PDT 24 Jul 21 06:23:09 PM PDT 24 1159182048 ps
T887 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4249812616 Jul 21 06:22:29 PM PDT 24 Jul 21 06:22:34 PM PDT 24 526144473 ps
T888 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3780379995 Jul 21 06:22:58 PM PDT 24 Jul 21 06:23:10 PM PDT 24 96536657 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2289469763 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:31 PM PDT 24 84344483 ps
T127 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2114058187 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:13 PM PDT 24 180440649 ps
T890 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.913735886 Jul 21 06:22:41 PM PDT 24 Jul 21 06:22:49 PM PDT 24 33138542 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2370460129 Jul 21 06:22:48 PM PDT 24 Jul 21 06:22:59 PM PDT 24 374286211 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2687319414 Jul 21 06:23:08 PM PDT 24 Jul 21 06:23:27 PM PDT 24 232975531 ps
T206 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3742778896 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:10 PM PDT 24 33576527 ps
T892 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.113803472 Jul 21 06:22:40 PM PDT 24 Jul 21 06:22:49 PM PDT 24 34004927 ps
T893 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3203342444 Jul 21 06:22:55 PM PDT 24 Jul 21 06:23:07 PM PDT 24 68895664 ps
T894 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3633734515 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:05 PM PDT 24 133809722 ps
T895 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.915754448 Jul 21 06:22:32 PM PDT 24 Jul 21 06:22:36 PM PDT 24 15825636 ps
T896 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.700217967 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:24 PM PDT 24 83865349 ps
T207 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1298674732 Jul 21 06:23:10 PM PDT 24 Jul 21 06:23:27 PM PDT 24 57870858 ps
T897 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1055329791 Jul 21 06:22:51 PM PDT 24 Jul 21 06:23:03 PM PDT 24 498869692 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2613069109 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:46 PM PDT 24 1196242349 ps
T899 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1928558692 Jul 21 06:22:30 PM PDT 24 Jul 21 06:22:34 PM PDT 24 53238934 ps
T208 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.85877610 Jul 21 06:22:23 PM PDT 24 Jul 21 06:22:26 PM PDT 24 57414038 ps
T900 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.842371822 Jul 21 06:23:09 PM PDT 24 Jul 21 06:23:27 PM PDT 24 28978425 ps
T901 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2001328217 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:05 PM PDT 24 72386874 ps
T902 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2050012662 Jul 21 06:23:00 PM PDT 24 Jul 21 06:23:13 PM PDT 24 42907691 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2516379706 Jul 21 06:22:55 PM PDT 24 Jul 21 06:23:07 PM PDT 24 276618538 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1858713498 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:24 PM PDT 24 211990382 ps
T905 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1517594998 Jul 21 06:23:07 PM PDT 24 Jul 21 06:23:25 PM PDT 24 29236967 ps
T906 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1194586715 Jul 21 06:22:48 PM PDT 24 Jul 21 06:22:57 PM PDT 24 248062730 ps
T907 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1187428107 Jul 21 06:23:08 PM PDT 24 Jul 21 06:23:26 PM PDT 24 34333436 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2370097979 Jul 21 06:22:30 PM PDT 24 Jul 21 06:22:33 PM PDT 24 16689296 ps
T909 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2087630283 Jul 21 06:22:40 PM PDT 24 Jul 21 06:22:49 PM PDT 24 1793206393 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4072053872 Jul 21 06:22:40 PM PDT 24 Jul 21 06:22:48 PM PDT 24 39105237 ps
T911 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2022359456 Jul 21 06:22:22 PM PDT 24 Jul 21 06:22:25 PM PDT 24 56473569 ps
T912 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1191743215 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:26 PM PDT 24 386687900 ps
T913 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.6913809 Jul 21 06:22:31 PM PDT 24 Jul 21 06:22:38 PM PDT 24 782210143 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.820172185 Jul 21 06:22:23 PM PDT 24 Jul 21 06:22:27 PM PDT 24 81828909 ps
T915 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3443202158 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:39 PM PDT 24 81898513 ps
T916 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.245552857 Jul 21 06:22:52 PM PDT 24 Jul 21 06:23:02 PM PDT 24 131169781 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4270512829 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:15 PM PDT 24 1975064054 ps
T918 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2713910134 Jul 21 06:23:08 PM PDT 24 Jul 21 06:23:25 PM PDT 24 13783930 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1963423855 Jul 21 06:22:20 PM PDT 24 Jul 21 06:22:23 PM PDT 24 85998347 ps
T209 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3049542695 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:32 PM PDT 24 13611921 ps
T920 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1230936769 Jul 21 06:23:09 PM PDT 24 Jul 21 06:23:27 PM PDT 24 104707731 ps
T921 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4176476948 Jul 21 06:22:42 PM PDT 24 Jul 21 06:22:51 PM PDT 24 103990116 ps
T210 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1617650760 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:24 PM PDT 24 21410878 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3583561700 Jul 21 06:22:41 PM PDT 24 Jul 21 06:22:51 PM PDT 24 32105947 ps
T923 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2066587122 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:03 PM PDT 24 166652208 ps
T924 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1009970183 Jul 21 06:22:32 PM PDT 24 Jul 21 06:22:36 PM PDT 24 26740416 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.147915486 Jul 21 06:22:24 PM PDT 24 Jul 21 06:22:27 PM PDT 24 75102246 ps
T132 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2894857029 Jul 21 06:22:56 PM PDT 24 Jul 21 06:23:09 PM PDT 24 111044521 ps
T926 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1542796442 Jul 21 06:22:55 PM PDT 24 Jul 21 06:23:07 PM PDT 24 17748502 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.181065480 Jul 21 06:22:20 PM PDT 24 Jul 21 06:22:23 PM PDT 24 44122201 ps
T928 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4074842029 Jul 21 06:22:46 PM PDT 24 Jul 21 06:22:57 PM PDT 24 181554826 ps
T929 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2315825134 Jul 21 06:22:54 PM PDT 24 Jul 21 06:23:07 PM PDT 24 463519566 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.572924348 Jul 21 06:22:45 PM PDT 24 Jul 21 06:22:55 PM PDT 24 181575914 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.726596950 Jul 21 06:22:30 PM PDT 24 Jul 21 06:22:34 PM PDT 24 109088945 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1449499200 Jul 21 06:22:22 PM PDT 24 Jul 21 06:22:26 PM PDT 24 323439518 ps
T933 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2729894545 Jul 21 06:22:52 PM PDT 24 Jul 21 06:23:03 PM PDT 24 237763359 ps
T934 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.327628586 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:12 PM PDT 24 72848093 ps
T935 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.273028829 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:39 PM PDT 24 95038071 ps
T134 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3234698988 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:11 PM PDT 24 126425931 ps
T936 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2638143194 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:41 PM PDT 24 124389319 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3007306707 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:35 PM PDT 24 1958167228 ps
T938 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2754783442 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:24 PM PDT 24 44599304 ps
T120 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2801410227 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:12 PM PDT 24 99091689 ps
T138 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3910870319 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:05 PM PDT 24 101855015 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2304397644 Jul 21 06:22:27 PM PDT 24 Jul 21 06:22:30 PM PDT 24 15887628 ps
T940 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2081678713 Jul 21 06:23:07 PM PDT 24 Jul 21 06:23:24 PM PDT 24 22389792 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1815158372 Jul 21 06:22:54 PM PDT 24 Jul 21 06:23:06 PM PDT 24 58910681 ps
T942 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.550678212 Jul 21 06:22:40 PM PDT 24 Jul 21 06:22:48 PM PDT 24 50627267 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2367074374 Jul 21 06:22:41 PM PDT 24 Jul 21 06:22:52 PM PDT 24 388605719 ps
T944 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2487865942 Jul 21 06:22:22 PM PDT 24 Jul 21 06:22:35 PM PDT 24 4820712244 ps
T945 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3628793179 Jul 21 06:22:41 PM PDT 24 Jul 21 06:23:05 PM PDT 24 2992646043 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3868840607 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:03 PM PDT 24 100270674 ps
T947 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3773300674 Jul 21 06:23:07 PM PDT 24 Jul 21 06:23:27 PM PDT 24 155333422 ps
T948 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1834130412 Jul 21 06:22:46 PM PDT 24 Jul 21 06:22:58 PM PDT 24 532680591 ps
T949 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1833074346 Jul 21 06:23:07 PM PDT 24 Jul 21 06:23:24 PM PDT 24 122076922 ps
T211 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.82923178 Jul 21 06:22:23 PM PDT 24 Jul 21 06:22:27 PM PDT 24 61451878 ps
T950 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.302667669 Jul 21 06:22:48 PM PDT 24 Jul 21 06:23:09 PM PDT 24 2114974411 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1706273327 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:32 PM PDT 24 91755600 ps
T952 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2899848392 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:52 PM PDT 24 4041499179 ps
T212 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1617757288 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:04 PM PDT 24 41676540 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2124927857 Jul 21 06:22:41 PM PDT 24 Jul 21 06:22:58 PM PDT 24 351623117 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1213328673 Jul 21 06:22:22 PM PDT 24 Jul 21 06:22:30 PM PDT 24 1086529172 ps
T125 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2240803919 Jul 21 06:23:00 PM PDT 24 Jul 21 06:23:14 PM PDT 24 78934160 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.80797322 Jul 21 06:22:33 PM PDT 24 Jul 21 06:22:37 PM PDT 24 22039369 ps
T956 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1242169860 Jul 21 06:23:08 PM PDT 24 Jul 21 06:23:25 PM PDT 24 31119293 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3660470848 Jul 21 06:22:52 PM PDT 24 Jul 21 06:23:12 PM PDT 24 1902508896 ps
T121 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4277473918 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:40 PM PDT 24 759354829 ps
T958 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3769976699 Jul 21 06:22:21 PM PDT 24 Jul 21 06:22:26 PM PDT 24 154143447 ps
T959 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3883599455 Jul 21 06:23:07 PM PDT 24 Jul 21 06:23:25 PM PDT 24 86262823 ps
T960 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1012985831 Jul 21 06:22:27 PM PDT 24 Jul 21 06:22:42 PM PDT 24 6929497787 ps
T961 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3509708879 Jul 21 06:23:00 PM PDT 24 Jul 21 06:23:14 PM PDT 24 135441663 ps
T213 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3633781443 Jul 21 06:22:22 PM PDT 24 Jul 21 06:22:25 PM PDT 24 66860926 ps
T962 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.153103399 Jul 21 06:22:30 PM PDT 24 Jul 21 06:22:34 PM PDT 24 444448135 ps
T216 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2319760490 Jul 21 06:22:47 PM PDT 24 Jul 21 06:22:56 PM PDT 24 53211746 ps
T137 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1253780068 Jul 21 06:22:33 PM PDT 24 Jul 21 06:22:41 PM PDT 24 773480701 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2059026024 Jul 21 06:22:46 PM PDT 24 Jul 21 06:22:56 PM PDT 24 79394062 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2336910640 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:05 PM PDT 24 436449815 ps
T965 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1978541994 Jul 21 06:22:48 PM PDT 24 Jul 21 06:22:58 PM PDT 24 114412073 ps
T966 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.317410934 Jul 21 06:22:33 PM PDT 24 Jul 21 06:22:39 PM PDT 24 160777768 ps
T129 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2056612218 Jul 21 06:22:59 PM PDT 24 Jul 21 06:23:13 PM PDT 24 78193600 ps
T967 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1605291370 Jul 21 06:22:20 PM PDT 24 Jul 21 06:22:22 PM PDT 24 62237077 ps
T968 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.30969098 Jul 21 06:23:01 PM PDT 24 Jul 21 06:23:14 PM PDT 24 54564952 ps
T136 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1469715519 Jul 21 06:22:58 PM PDT 24 Jul 21 06:23:11 PM PDT 24 592833556 ps
T969 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1556909231 Jul 21 06:22:29 PM PDT 24 Jul 21 06:22:33 PM PDT 24 16022771 ps
T214 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1292133356 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:31 PM PDT 24 42009691 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2463049529 Jul 21 06:22:33 PM PDT 24 Jul 21 06:22:39 PM PDT 24 110718145 ps
T971 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3477356350 Jul 21 06:22:54 PM PDT 24 Jul 21 06:23:05 PM PDT 24 13662057 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1886205685 Jul 21 06:22:24 PM PDT 24 Jul 21 06:22:27 PM PDT 24 126112585 ps
T973 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1393852772 Jul 21 06:22:31 PM PDT 24 Jul 21 06:22:35 PM PDT 24 242493340 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4103535162 Jul 21 06:22:22 PM PDT 24 Jul 21 06:22:31 PM PDT 24 336520501 ps
T975 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1298846062 Jul 21 06:22:39 PM PDT 24 Jul 21 06:22:46 PM PDT 24 41030192 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2196082136 Jul 21 06:22:22 PM PDT 24 Jul 21 06:22:33 PM PDT 24 2200974587 ps
T977 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.645485949 Jul 21 06:22:33 PM PDT 24 Jul 21 06:22:37 PM PDT 24 112710700 ps
T978 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1597172776 Jul 21 06:22:49 PM PDT 24 Jul 21 06:23:00 PM PDT 24 163586958 ps
T979 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1519702443 Jul 21 06:22:41 PM PDT 24 Jul 21 06:22:51 PM PDT 24 1869669140 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2970824888 Jul 21 06:22:47 PM PDT 24 Jul 21 06:22:58 PM PDT 24 46787478 ps
T215 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.71767934 Jul 21 06:22:53 PM PDT 24 Jul 21 06:23:03 PM PDT 24 39948792 ps
T981 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.84358681 Jul 21 06:22:24 PM PDT 24 Jul 21 06:22:27 PM PDT 24 173586246 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1583455049 Jul 21 06:22:29 PM PDT 24 Jul 21 06:22:33 PM PDT 24 82210497 ps
T983 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2272918937 Jul 21 06:22:58 PM PDT 24 Jul 21 06:23:11 PM PDT 24 51534196 ps
T984 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.140675215 Jul 21 06:22:23 PM PDT 24 Jul 21 06:22:27 PM PDT 24 537847401 ps
T985 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2905797166 Jul 21 06:22:28 PM PDT 24 Jul 21 06:22:33 PM PDT 24 781125533 ps
T130 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2686344465 Jul 21 06:22:23 PM PDT 24 Jul 21 06:22:28 PM PDT 24 216602478 ps
T986 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2162543968 Jul 21 06:22:32 PM PDT 24 Jul 21 06:22:36 PM PDT 24 15636364 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2444955168 Jul 21 06:22:52 PM PDT 24 Jul 21 06:23:03 PM PDT 24 52281338 ps
T988 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3899770458 Jul 21 06:22:47 PM PDT 24 Jul 21 06:22:58 PM PDT 24 304271532 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.968967130 Jul 21 06:22:34 PM PDT 24 Jul 21 06:22:38 PM PDT 24 24962824 ps
T990 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1537239563 Jul 21 06:22:29 PM PDT 24 Jul 21 06:22:32 PM PDT 24 55519188 ps
T991 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2456172157 Jul 21 06:22:58 PM PDT 24 Jul 21 06:23:10 PM PDT 24 67147230 ps
T992 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3192148104 Jul 21 06:22:29 PM PDT 24 Jul 21 06:22:32 PM PDT 24 185371311 ps

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.571922041
Short name T10
Test name
Test status
Simulation time 728861252 ps
CPU time 7.72 seconds
Started Jul 21 06:26:35 PM PDT 24
Finished Jul 21 06:26:43 PM PDT 24
Peak memory 218572 kb
Host smart-1e719877-6644-4382-ab6e-36f8b0a83d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571922041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.571922041
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1707062343
Short name T21
Test name
Test status
Simulation time 3243615411 ps
CPU time 42.3 seconds
Started Jul 21 06:27:06 PM PDT 24
Finished Jul 21 06:27:49 PM PDT 24
Peak memory 251180 kb
Host smart-22bf7e4b-8298-4cf9-adad-97a4daf846a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707062343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1707062343
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3165264047
Short name T13
Test name
Test status
Simulation time 943950537 ps
CPU time 22.67 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:27:14 PM PDT 24
Peak memory 226164 kb
Host smart-9f02b21d-4b7d-448b-8545-01ee6501c214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165264047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3165264047
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3971994935
Short name T44
Test name
Test status
Simulation time 876738541 ps
CPU time 9.29 seconds
Started Jul 21 06:26:19 PM PDT 24
Finished Jul 21 06:26:29 PM PDT 24
Peak memory 219020 kb
Host smart-4bbcc8af-b270-4333-b9d2-58f023791364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971994935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3971994935
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1052607629
Short name T79
Test name
Test status
Simulation time 55277071819 ps
CPU time 510.77 seconds
Started Jul 21 06:26:11 PM PDT 24
Finished Jul 21 06:34:42 PM PDT 24
Peak memory 341440 kb
Host smart-0f3317b2-8ca3-4877-9f58-62bb03749c9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1052607629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1052607629
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1255626585
Short name T107
Test name
Test status
Simulation time 32191416 ps
CPU time 2.42 seconds
Started Jul 21 06:23:10 PM PDT 24
Finished Jul 21 06:23:29 PM PDT 24
Peak memory 218032 kb
Host smart-10b51b13-f2ff-476b-a2ab-2382d51ef13b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255626585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1255626585
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1655694487
Short name T14
Test name
Test status
Simulation time 43974997937 ps
CPU time 205.74 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:28:41 PM PDT 24
Peak memory 267576 kb
Host smart-621d4fcc-abfa-45ac-8972-feddb56c8615
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655694487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1655694487
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3963190319
Short name T15
Test name
Test status
Simulation time 347119029 ps
CPU time 14.43 seconds
Started Jul 21 06:25:34 PM PDT 24
Finished Jul 21 06:25:48 PM PDT 24
Peak memory 218424 kb
Host smart-14235e5e-4dd0-494d-b9ab-66686e3cd111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963190319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3963190319
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2626992878
Short name T53
Test name
Test status
Simulation time 215132465 ps
CPU time 35.34 seconds
Started Jul 21 06:24:41 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 282260 kb
Host smart-813054c5-3764-4db7-8e7c-95bdfa107fa2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626992878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2626992878
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.912442077
Short name T6
Test name
Test status
Simulation time 1669589897 ps
CPU time 11.3 seconds
Started Jul 21 06:25:17 PM PDT 24
Finished Jul 21 06:25:29 PM PDT 24
Peak memory 217448 kb
Host smart-7f97920b-1a3b-4a4e-9e11-0b359d14a404
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912442077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.912442077
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2074827312
Short name T108
Test name
Test status
Simulation time 352305749 ps
CPU time 3.38 seconds
Started Jul 21 06:22:23 PM PDT 24
Finished Jul 21 06:22:28 PM PDT 24
Peak memory 222752 kb
Host smart-9cd3a824-b3ee-4c4e-aa5f-204072acecba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074827312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2074827312
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2074267360
Short name T12
Test name
Test status
Simulation time 5060971886 ps
CPU time 7.75 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:14 PM PDT 24
Peak memory 218388 kb
Host smart-a4bbea0f-c5e6-4394-b958-07b98e78d8f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074267360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2074267360
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2804132119
Short name T37
Test name
Test status
Simulation time 33036169 ps
CPU time 1.12 seconds
Started Jul 21 06:27:08 PM PDT 24
Finished Jul 21 06:27:10 PM PDT 24
Peak memory 209216 kb
Host smart-f8f14e1f-fe36-48b5-9516-714b86be94a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804132119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2804132119
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2257879823
Short name T94
Test name
Test status
Simulation time 837722532 ps
CPU time 31.23 seconds
Started Jul 21 06:25:25 PM PDT 24
Finished Jul 21 06:25:56 PM PDT 24
Peak memory 251100 kb
Host smart-c426f5e9-5014-4d1b-bd53-7a9e458ce661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257879823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2257879823
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2200799332
Short name T112
Test name
Test status
Simulation time 119060277 ps
CPU time 2.25 seconds
Started Jul 21 06:22:45 PM PDT 24
Finished Jul 21 06:22:56 PM PDT 24
Peak memory 218976 kb
Host smart-1ab5d38d-4a71-413e-a89e-ef1e0d596f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220079
9332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2200799332
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.85877610
Short name T208
Test name
Test status
Simulation time 57414038 ps
CPU time 1.18 seconds
Started Jul 21 06:22:23 PM PDT 24
Finished Jul 21 06:22:26 PM PDT 24
Peak memory 217824 kb
Host smart-ff11078d-4c99-4adc-8170-4b02f8b0e5c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85877610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing.85877610
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3690380084
Short name T145
Test name
Test status
Simulation time 54152932912 ps
CPU time 1001.82 seconds
Started Jul 21 06:25:23 PM PDT 24
Finished Jul 21 06:42:06 PM PDT 24
Peak memory 497064 kb
Host smart-5a24d7e7-c7b5-4aec-8747-905d53accd4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3690380084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3690380084
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3709401164
Short name T131
Test name
Test status
Simulation time 223811360 ps
CPU time 3.95 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:07 PM PDT 24
Peak memory 217936 kb
Host smart-2bc37d14-b9cd-48f2-b3c2-dc1c40719d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709401164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3709401164
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2686344465
Short name T130
Test name
Test status
Simulation time 216602478 ps
CPU time 2.97 seconds
Started Jul 21 06:22:23 PM PDT 24
Finished Jul 21 06:22:28 PM PDT 24
Peak memory 217816 kb
Host smart-bec1e1ec-2b15-4143-84b6-8bbdfe785ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686344465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2686344465
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.86732166
Short name T38
Test name
Test status
Simulation time 15891353 ps
CPU time 1.1 seconds
Started Jul 21 06:26:39 PM PDT 24
Finished Jul 21 06:26:41 PM PDT 24
Peak memory 217716 kb
Host smart-6b07f4d4-9b6a-49ad-bc35-5922bd0a65b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86732166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctr
l_volatile_unlock_smoke.86732166
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1055329791
Short name T897
Test name
Test status
Simulation time 498869692 ps
CPU time 3.3 seconds
Started Jul 21 06:22:51 PM PDT 24
Finished Jul 21 06:23:03 PM PDT 24
Peak memory 218008 kb
Host smart-9d329924-6840-4c7b-8c4a-32514844e00b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055329791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1055329791
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2459668799
Short name T220
Test name
Test status
Simulation time 403070553 ps
CPU time 1.28 seconds
Started Jul 21 06:22:20 PM PDT 24
Finished Jul 21 06:22:22 PM PDT 24
Peak memory 209672 kb
Host smart-7eda35df-4957-4356-b203-0a44f52809a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459668799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2459668799
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1202634078
Short name T149
Test name
Test status
Simulation time 299198514 ps
CPU time 7.24 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:24:45 PM PDT 24
Peak memory 217784 kb
Host smart-e0adc849-a56d-45f9-880a-db84579ebb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202634078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1202634078
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2056612218
Short name T129
Test name
Test status
Simulation time 78193600 ps
CPU time 3.57 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:13 PM PDT 24
Peak memory 217812 kb
Host smart-e5d860e5-bee1-4af3-83fc-ac779db756ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056612218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2056612218
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1512546899
Short name T115
Test name
Test status
Simulation time 438325782 ps
CPU time 4.53 seconds
Started Jul 21 06:22:39 PM PDT 24
Finished Jul 21 06:22:49 PM PDT 24
Peak memory 217836 kb
Host smart-53c3a7b0-62cb-47ff-8c29-d981fe71c1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512546899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1512546899
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1960708288
Short name T229
Test name
Test status
Simulation time 34466837 ps
CPU time 0.79 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:24:37 PM PDT 24
Peak memory 209060 kb
Host smart-d0d8762d-2578-422a-a9d6-7b3948003cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960708288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1960708288
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1524648564
Short name T336
Test name
Test status
Simulation time 1581439240 ps
CPU time 9.6 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:20 PM PDT 24
Peak memory 226232 kb
Host smart-f42e34dd-c82f-42a1-babb-2d887cdbc9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524648564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1524648564
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1413870811
Short name T189
Test name
Test status
Simulation time 33173819 ps
CPU time 0.85 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:00 PM PDT 24
Peak memory 209088 kb
Host smart-50f3a3da-dbac-4598-b0e7-4f6cca0f7416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413870811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1413870811
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3403843222
Short name T228
Test name
Test status
Simulation time 15382010 ps
CPU time 0.91 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:04 PM PDT 24
Peak memory 208908 kb
Host smart-8b0da215-049e-4f53-82aa-7db3d34a0d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403843222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3403843222
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3345128071
Short name T18
Test name
Test status
Simulation time 239833942 ps
CPU time 3.47 seconds
Started Jul 21 06:26:04 PM PDT 24
Finished Jul 21 06:26:08 PM PDT 24
Peak memory 217816 kb
Host smart-2f88fa08-73f7-463f-8dac-e25a9e483869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345128071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3345128071
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.416524061
Short name T85
Test name
Test status
Simulation time 20040974438 ps
CPU time 61.82 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:25:39 PM PDT 24
Peak memory 274576 kb
Host smart-df81e648-7e7a-4f59-a621-523f35c9731c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416524061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.416524061
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1963423855
Short name T919
Test name
Test status
Simulation time 85998347 ps
CPU time 1.58 seconds
Started Jul 21 06:22:20 PM PDT 24
Finished Jul 21 06:22:23 PM PDT 24
Peak memory 217924 kb
Host smart-ce3647bc-5d69-4638-9cc7-d817d2e43c95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196342
3855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1963423855
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2240803919
Short name T125
Test name
Test status
Simulation time 78934160 ps
CPU time 2.74 seconds
Started Jul 21 06:23:00 PM PDT 24
Finished Jul 21 06:23:14 PM PDT 24
Peak memory 222864 kb
Host smart-943456a3-fead-4a7b-b6a3-856218e29009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240803919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2240803919
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2801410227
Short name T120
Test name
Test status
Simulation time 99091689 ps
CPU time 1.86 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:12 PM PDT 24
Peak memory 222156 kb
Host smart-0d5537bb-98d0-44ca-a4a2-1ed3cbae0c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801410227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2801410227
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1469715519
Short name T136
Test name
Test status
Simulation time 592833556 ps
CPU time 2.78 seconds
Started Jul 21 06:22:58 PM PDT 24
Finished Jul 21 06:23:11 PM PDT 24
Peak memory 222224 kb
Host smart-30023bf2-e72b-4c35-838d-5b7407d51bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469715519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1469715519
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1824036667
Short name T114
Test name
Test status
Simulation time 83198462 ps
CPU time 2.77 seconds
Started Jul 21 06:22:27 PM PDT 24
Finished Jul 21 06:22:31 PM PDT 24
Peak memory 222728 kb
Host smart-1860e2ad-b0ee-4278-aeea-2d727d7e4e08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824036667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1824036667
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1114388543
Short name T119
Test name
Test status
Simulation time 59171503 ps
CPU time 2.03 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:32 PM PDT 24
Peak memory 213336 kb
Host smart-bcabc941-b46d-4810-bc76-9ead6dc52f84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114388543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1114388543
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1253780068
Short name T137
Test name
Test status
Simulation time 773480701 ps
CPU time 3.99 seconds
Started Jul 21 06:22:33 PM PDT 24
Finished Jul 21 06:22:41 PM PDT 24
Peak memory 217932 kb
Host smart-fff38c71-155e-4793-91fc-0cb514cc78a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253780068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1253780068
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.33052275
Short name T50
Test name
Test status
Simulation time 50844299351 ps
CPU time 252.92 seconds
Started Jul 21 06:26:24 PM PDT 24
Finished Jul 21 06:30:38 PM PDT 24
Peak memory 226380 kb
Host smart-f399b013-aef1-44d1-b7bb-9040c1275415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33052275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.lc_ctrl_stress_all.33052275
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2667631411
Short name T3
Test name
Test status
Simulation time 327784752 ps
CPU time 28.95 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:25:45 PM PDT 24
Peak memory 246404 kb
Host smart-b3cf1690-59f6-45ce-aaf8-d842709d1dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667631411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2667631411
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3065024430
Short name T4
Test name
Test status
Simulation time 344799826 ps
CPU time 11.47 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 222984 kb
Host smart-efe37a4a-5dff-4518-808a-8afdcff0f47f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065024430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3065024430
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3587759227
Short name T870
Test name
Test status
Simulation time 18652582 ps
CPU time 1.34 seconds
Started Jul 21 06:22:23 PM PDT 24
Finished Jul 21 06:22:27 PM PDT 24
Peak memory 209680 kb
Host smart-d8984ba0-35af-4650-8c8a-84be969a42f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587759227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3587759227
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3576843383
Short name T869
Test name
Test status
Simulation time 134021619 ps
CPU time 1.29 seconds
Started Jul 21 06:22:20 PM PDT 24
Finished Jul 21 06:22:22 PM PDT 24
Peak memory 219544 kb
Host smart-8f14e17d-2582-45d5-b768-eed04c70f7d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576843383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3576843383
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.147915486
Short name T925
Test name
Test status
Simulation time 75102246 ps
CPU time 1.02 seconds
Started Jul 21 06:22:24 PM PDT 24
Finished Jul 21 06:22:27 PM PDT 24
Peak memory 217932 kb
Host smart-2578d6c2-15e7-41db-b5ae-e970bfa044dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147915486 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.147915486
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3594690195
Short name T874
Test name
Test status
Simulation time 40046647 ps
CPU time 0.98 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:22 PM PDT 24
Peak memory 209192 kb
Host smart-e8c35ba2-d8fc-4dd2-b567-3efe70f2cef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594690195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3594690195
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1886205685
Short name T972
Test name
Test status
Simulation time 126112585 ps
CPU time 1.02 seconds
Started Jul 21 06:22:24 PM PDT 24
Finished Jul 21 06:22:27 PM PDT 24
Peak memory 208184 kb
Host smart-cbca6365-3146-483e-9973-2d506e87aa9b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886205685 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1886205685
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1213328673
Short name T954
Test name
Test status
Simulation time 1086529172 ps
CPU time 6.07 seconds
Started Jul 21 06:22:22 PM PDT 24
Finished Jul 21 06:22:30 PM PDT 24
Peak memory 209444 kb
Host smart-1db7e7b9-bd4c-45aa-b201-2cfbbc6b3ad3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213328673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1213328673
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2487865942
Short name T944
Test name
Test status
Simulation time 4820712244 ps
CPU time 12.13 seconds
Started Jul 21 06:22:22 PM PDT 24
Finished Jul 21 06:22:35 PM PDT 24
Peak memory 208696 kb
Host smart-c9a377ea-6732-49b5-94f5-008749975a59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487865942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2487865942
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2022359456
Short name T911
Test name
Test status
Simulation time 56473569 ps
CPU time 1.41 seconds
Started Jul 21 06:22:22 PM PDT 24
Finished Jul 21 06:22:25 PM PDT 24
Peak memory 211080 kb
Host smart-86581214-536c-47db-8198-174d85f2d75f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022359456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2022359456
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.84358681
Short name T981
Test name
Test status
Simulation time 173586246 ps
CPU time 1.18 seconds
Started Jul 21 06:22:24 PM PDT 24
Finished Jul 21 06:22:27 PM PDT 24
Peak memory 209520 kb
Host smart-f92252b4-fd81-4c71-beed-080f8630c7e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84358681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 0.lc_ctrl_jtag_csr_rw.84358681
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.700217967
Short name T896
Test name
Test status
Simulation time 83865349 ps
CPU time 1.05 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:24 PM PDT 24
Peak memory 209652 kb
Host smart-32fcffda-e0b7-48de-9cb0-48769f0b96e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700217967 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.700217967
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1449499200
Short name T932
Test name
Test status
Simulation time 323439518 ps
CPU time 2.55 seconds
Started Jul 21 06:22:22 PM PDT 24
Finished Jul 21 06:22:26 PM PDT 24
Peak memory 217996 kb
Host smart-2c67eeb5-fd8d-4d12-a1e0-5820939f4d73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449499200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1449499200
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3633781443
Short name T213
Test name
Test status
Simulation time 66860926 ps
CPU time 1.02 seconds
Started Jul 21 06:22:22 PM PDT 24
Finished Jul 21 06:22:25 PM PDT 24
Peak memory 209764 kb
Host smart-b3d7f40e-0a37-4c4e-8f31-fecac3ef48ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633781443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3633781443
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.645485949
Short name T977
Test name
Test status
Simulation time 112710700 ps
CPU time 1.24 seconds
Started Jul 21 06:22:33 PM PDT 24
Finished Jul 21 06:22:37 PM PDT 24
Peak memory 208404 kb
Host smart-2da4cfaa-968e-4bee-bd7c-05951268c198
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645485949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.645485949
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.82923178
Short name T211
Test name
Test status
Simulation time 61451878 ps
CPU time 1.15 seconds
Started Jul 21 06:22:23 PM PDT 24
Finished Jul 21 06:22:27 PM PDT 24
Peak memory 211732 kb
Host smart-d9be3890-6ac1-486e-a3c7-88553645c0b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82923178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset.82923178
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3854457
Short name T158
Test name
Test status
Simulation time 141008969 ps
CPU time 1.21 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:24 PM PDT 24
Peak memory 218068 kb
Host smart-ad331594-7f8d-4933-a2c1-4164deb2c625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854457 -assert nopostproc +UVM_TESTNAME=lc
_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3854457
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1617650760
Short name T210
Test name
Test status
Simulation time 21410878 ps
CPU time 0.98 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:24 PM PDT 24
Peak memory 209624 kb
Host smart-e0c79b37-372f-42ed-afa3-8352e88d94f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617650760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1617650760
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2754783442
Short name T938
Test name
Test status
Simulation time 44599304 ps
CPU time 1.29 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:24 PM PDT 24
Peak memory 209428 kb
Host smart-b5ccbbf7-1951-42f3-8128-b1c392035b1e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754783442 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2754783442
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4103535162
Short name T974
Test name
Test status
Simulation time 336520501 ps
CPU time 8.15 seconds
Started Jul 21 06:22:22 PM PDT 24
Finished Jul 21 06:22:31 PM PDT 24
Peak memory 209404 kb
Host smart-1ce23112-d6d9-45b4-97cc-498d1b672a68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103535162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4103535162
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2196082136
Short name T976
Test name
Test status
Simulation time 2200974587 ps
CPU time 9.38 seconds
Started Jul 21 06:22:22 PM PDT 24
Finished Jul 21 06:22:33 PM PDT 24
Peak memory 209620 kb
Host smart-3337ed66-d050-4efe-a254-88cdc6943eef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196082136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2196082136
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1191743215
Short name T912
Test name
Test status
Simulation time 386687900 ps
CPU time 3.06 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:26 PM PDT 24
Peak memory 211124 kb
Host smart-90d85b61-3ea3-4c7e-af33-627fe4a87cac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191743215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1191743215
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3769976699
Short name T958
Test name
Test status
Simulation time 154143447 ps
CPU time 4.65 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:26 PM PDT 24
Peak memory 219352 kb
Host smart-c0a6c0cd-054d-4fef-b0c6-b144bfe4e65f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376997
6699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3769976699
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1858713498
Short name T904
Test name
Test status
Simulation time 211990382 ps
CPU time 1.48 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:24 PM PDT 24
Peak memory 209516 kb
Host smart-21b15d89-9275-4b52-be21-ef18506dc046
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858713498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1858713498
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.140675215
Short name T984
Test name
Test status
Simulation time 537847401 ps
CPU time 1.31 seconds
Started Jul 21 06:22:23 PM PDT 24
Finished Jul 21 06:22:27 PM PDT 24
Peak memory 211248 kb
Host smart-1cf88581-1410-4a78-89c7-8b0233db40e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140675215 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.140675215
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.181065480
Short name T927
Test name
Test status
Simulation time 44122201 ps
CPU time 1.41 seconds
Started Jul 21 06:22:20 PM PDT 24
Finished Jul 21 06:22:23 PM PDT 24
Peak memory 209656 kb
Host smart-70cd6eff-30db-40d1-96fc-90906bb4f00a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181065480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.181065480
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1627651304
Short name T123
Test name
Test status
Simulation time 94625801 ps
CPU time 1.43 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:24 PM PDT 24
Peak memory 218816 kb
Host smart-a5aedd3c-8e85-4038-8b26-3882c1577337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627651304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1627651304
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.591972768
Short name T882
Test name
Test status
Simulation time 118333964 ps
CPU time 1.55 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:04 PM PDT 24
Peak memory 218048 kb
Host smart-3c520588-d71b-4db1-9974-a9991145f1ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591972768 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.591972768
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.71767934
Short name T215
Test name
Test status
Simulation time 39948792 ps
CPU time 0.86 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:03 PM PDT 24
Peak memory 209544 kb
Host smart-fb834955-61e2-44bb-97d6-c3b6b8b2b0d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71767934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.71767934
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3203342444
Short name T893
Test name
Test status
Simulation time 68895664 ps
CPU time 1.28 seconds
Started Jul 21 06:22:55 PM PDT 24
Finished Jul 21 06:23:07 PM PDT 24
Peak memory 209228 kb
Host smart-ee056656-657a-45b0-9fb9-45903ac8da60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203342444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3203342444
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2729894545
Short name T933
Test name
Test status
Simulation time 237763359 ps
CPU time 1.84 seconds
Started Jul 21 06:22:52 PM PDT 24
Finished Jul 21 06:23:03 PM PDT 24
Peak memory 217800 kb
Host smart-4af89265-3015-42a4-a457-bf086704b719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729894545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2729894545
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2894857029
Short name T132
Test name
Test status
Simulation time 111044521 ps
CPU time 2.87 seconds
Started Jul 21 06:22:56 PM PDT 24
Finished Jul 21 06:23:09 PM PDT 24
Peak memory 222324 kb
Host smart-ddf50ea3-0c72-4763-9cd2-a9bef02a0249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894857029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2894857029
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1086504527
Short name T160
Test name
Test status
Simulation time 105941196 ps
CPU time 1.37 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:04 PM PDT 24
Peak memory 219304 kb
Host smart-06372bfd-1c4e-4627-a987-52fd2fa66cbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086504527 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1086504527
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1617757288
Short name T212
Test name
Test status
Simulation time 41676540 ps
CPU time 1.01 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:04 PM PDT 24
Peak memory 209624 kb
Host smart-3d4ede7c-4add-450f-95ee-3f35f4ca365c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617757288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1617757288
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1542796442
Short name T926
Test name
Test status
Simulation time 17748502 ps
CPU time 1.22 seconds
Started Jul 21 06:22:55 PM PDT 24
Finished Jul 21 06:23:07 PM PDT 24
Peak memory 209148 kb
Host smart-562571f4-58e5-48ec-b054-3f52cad745a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542796442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1542796442
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3633734515
Short name T894
Test name
Test status
Simulation time 133809722 ps
CPU time 2.38 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:05 PM PDT 24
Peak memory 218752 kb
Host smart-f36c8de4-47d2-488b-8f54-69f2cf337774
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633734515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3633734515
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3866274674
Short name T126
Test name
Test status
Simulation time 48764533 ps
CPU time 1.64 seconds
Started Jul 21 06:22:54 PM PDT 24
Finished Jul 21 06:23:05 PM PDT 24
Peak memory 219772 kb
Host smart-79c46c88-2b27-4ba2-8d18-d498dc35f1a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866274674 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3866274674
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3405232797
Short name T202
Test name
Test status
Simulation time 30747069 ps
CPU time 1.08 seconds
Started Jul 21 06:22:54 PM PDT 24
Finished Jul 21 06:23:05 PM PDT 24
Peak memory 209360 kb
Host smart-83dca26b-cb37-4e08-b570-85ec5959d7bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405232797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3405232797
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1182891048
Short name T217
Test name
Test status
Simulation time 41920075 ps
CPU time 1.46 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:04 PM PDT 24
Peak memory 211572 kb
Host smart-15c03998-1565-4ede-81f8-34044bea40c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182891048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1182891048
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3910870319
Short name T138
Test name
Test status
Simulation time 101855015 ps
CPU time 2.37 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:05 PM PDT 24
Peak memory 222352 kb
Host smart-61c2d6ca-e61e-443d-9142-94468ee60681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910870319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3910870319
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1242169860
Short name T956
Test name
Test status
Simulation time 31119293 ps
CPU time 1.09 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:25 PM PDT 24
Peak memory 217912 kb
Host smart-07ea9f49-acce-439b-a656-0b17ab9c7a5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242169860 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1242169860
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3742778896
Short name T206
Test name
Test status
Simulation time 33576527 ps
CPU time 0.92 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:10 PM PDT 24
Peak memory 209624 kb
Host smart-f72e1fae-f4c0-403e-b9f4-81a09c8eeb10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742778896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3742778896
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3780379995
Short name T888
Test name
Test status
Simulation time 96536657 ps
CPU time 1.07 seconds
Started Jul 21 06:22:58 PM PDT 24
Finished Jul 21 06:23:10 PM PDT 24
Peak memory 209620 kb
Host smart-da6f727b-5ddb-46d6-a727-16ebb8d34672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780379995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3780379995
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3509708879
Short name T961
Test name
Test status
Simulation time 135441663 ps
CPU time 2.33 seconds
Started Jul 21 06:23:00 PM PDT 24
Finished Jul 21 06:23:14 PM PDT 24
Peak memory 218900 kb
Host smart-358f0bcc-d979-44ab-8a82-471a078bea04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509708879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3509708879
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.653571924
Short name T124
Test name
Test status
Simulation time 64569622 ps
CPU time 2.63 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:13 PM PDT 24
Peak memory 217848 kb
Host smart-650c186f-d32f-4d54-b6fa-de2090cddd07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653571924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.653571924
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1149187520
Short name T876
Test name
Test status
Simulation time 37912504 ps
CPU time 1.45 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:11 PM PDT 24
Peak memory 222556 kb
Host smart-5f7ade48-a731-405b-a719-fd7005e596c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149187520 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1149187520
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2856684920
Short name T203
Test name
Test status
Simulation time 143630010 ps
CPU time 0.89 seconds
Started Jul 21 06:22:58 PM PDT 24
Finished Jul 21 06:23:09 PM PDT 24
Peak memory 209620 kb
Host smart-ed05058c-46ff-4dbc-b144-0151d99e3b25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856684920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2856684920
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1293086119
Short name T219
Test name
Test status
Simulation time 75427545 ps
CPU time 1.44 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:11 PM PDT 24
Peak memory 211560 kb
Host smart-0ec9374e-b849-4164-adcd-112dd1bb3031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293086119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1293086119
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2114058187
Short name T127
Test name
Test status
Simulation time 180440649 ps
CPU time 3.36 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:13 PM PDT 24
Peak memory 219024 kb
Host smart-1da212d1-a8b1-4190-b02a-4e50a4da4d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114058187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2114058187
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.275179674
Short name T110
Test name
Test status
Simulation time 24970467 ps
CPU time 1.54 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:11 PM PDT 24
Peak memory 218164 kb
Host smart-c1e4e2a5-d683-4244-8e8c-c2e5f790731c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275179674 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.275179674
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.30969098
Short name T968
Test name
Test status
Simulation time 54564952 ps
CPU time 0.91 seconds
Started Jul 21 06:23:01 PM PDT 24
Finished Jul 21 06:23:14 PM PDT 24
Peak memory 209588 kb
Host smart-8b6756c1-514d-4268-ba45-007fb0e313c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.30969098
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1833074346
Short name T949
Test name
Test status
Simulation time 122076922 ps
CPU time 1.03 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:24 PM PDT 24
Peak memory 209612 kb
Host smart-6f996f91-2af8-41f0-b1ad-e0d63190aed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833074346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1833074346
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1921262806
Short name T118
Test name
Test status
Simulation time 244120709 ps
CPU time 3.76 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:26 PM PDT 24
Peak memory 218024 kb
Host smart-8575adcc-d452-4d54-9f34-1756516b011a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921262806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1921262806
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2081678713
Short name T940
Test name
Test status
Simulation time 22389792 ps
CPU time 0.98 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:24 PM PDT 24
Peak memory 217872 kb
Host smart-505faf42-bb5b-4e17-acc4-e68a6d525586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081678713 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2081678713
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2050012662
Short name T902
Test name
Test status
Simulation time 42907691 ps
CPU time 0.83 seconds
Started Jul 21 06:23:00 PM PDT 24
Finished Jul 21 06:23:13 PM PDT 24
Peak memory 209036 kb
Host smart-5129d055-7170-4ffe-9433-794503011a5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050012662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2050012662
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2184194925
Short name T218
Test name
Test status
Simulation time 66059312 ps
CPU time 1.38 seconds
Started Jul 21 06:22:58 PM PDT 24
Finished Jul 21 06:23:11 PM PDT 24
Peak memory 209604 kb
Host smart-9fb26ff6-2f8a-47bd-9382-37e43ebbe935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184194925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2184194925
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2272918937
Short name T983
Test name
Test status
Simulation time 51534196 ps
CPU time 2.28 seconds
Started Jul 21 06:22:58 PM PDT 24
Finished Jul 21 06:23:11 PM PDT 24
Peak memory 218248 kb
Host smart-0df7c070-9ad2-4a24-8aa7-8a5fa0342dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272918937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2272918937
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2456172157
Short name T991
Test name
Test status
Simulation time 67147230 ps
CPU time 1.34 seconds
Started Jul 21 06:22:58 PM PDT 24
Finished Jul 21 06:23:10 PM PDT 24
Peak memory 218060 kb
Host smart-b89a0782-37f4-4a56-ab93-37cd20815434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456172157 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2456172157
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2713910134
Short name T918
Test name
Test status
Simulation time 13783930 ps
CPU time 0.9 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:25 PM PDT 24
Peak memory 209624 kb
Host smart-f890cdc5-f01a-4d2c-bcec-b468ddb660e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713910134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2713910134
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.327628586
Short name T934
Test name
Test status
Simulation time 72848093 ps
CPU time 1.19 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:12 PM PDT 24
Peak memory 209660 kb
Host smart-0eab5031-0acd-4455-a236-d40d1fc1485f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327628586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.327628586
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2018722849
Short name T113
Test name
Test status
Simulation time 94092079 ps
CPU time 2.61 seconds
Started Jul 21 06:23:01 PM PDT 24
Finished Jul 21 06:23:16 PM PDT 24
Peak memory 217804 kb
Host smart-e6c3fa57-02ec-4182-bf53-11d1b10fa31c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018722849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2018722849
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1230936769
Short name T920
Test name
Test status
Simulation time 104707731 ps
CPU time 1.31 seconds
Started Jul 21 06:23:09 PM PDT 24
Finished Jul 21 06:23:27 PM PDT 24
Peak memory 218052 kb
Host smart-90ceaf36-0973-4f77-b007-c306c03d4c8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230936769 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1230936769
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1298674732
Short name T207
Test name
Test status
Simulation time 57870858 ps
CPU time 0.96 seconds
Started Jul 21 06:23:10 PM PDT 24
Finished Jul 21 06:23:27 PM PDT 24
Peak memory 209636 kb
Host smart-aaa47328-c1f2-471d-9c6b-936a89bdaecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298674732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1298674732
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3883599455
Short name T959
Test name
Test status
Simulation time 86262823 ps
CPU time 1.84 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:25 PM PDT 24
Peak memory 211724 kb
Host smart-1b925b46-3803-4f98-bdec-e49eb807732c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883599455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3883599455
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3773300674
Short name T947
Test name
Test status
Simulation time 155333422 ps
CPU time 3.96 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:27 PM PDT 24
Peak memory 218432 kb
Host smart-1e4554c8-3877-41e1-b642-68df83e966c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773300674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3773300674
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3234698988
Short name T134
Test name
Test status
Simulation time 126425931 ps
CPU time 2.04 seconds
Started Jul 21 06:22:59 PM PDT 24
Finished Jul 21 06:23:11 PM PDT 24
Peak memory 221928 kb
Host smart-917caf40-d88a-44d4-a514-da54465b6d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234698988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3234698988
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.842371822
Short name T900
Test name
Test status
Simulation time 28978425 ps
CPU time 1.43 seconds
Started Jul 21 06:23:09 PM PDT 24
Finished Jul 21 06:23:27 PM PDT 24
Peak memory 221424 kb
Host smart-308b35e1-043c-4815-872e-67655ee8271f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842371822 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.842371822
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1517594998
Short name T905
Test name
Test status
Simulation time 29236967 ps
CPU time 0.9 seconds
Started Jul 21 06:23:07 PM PDT 24
Finished Jul 21 06:23:25 PM PDT 24
Peak memory 209624 kb
Host smart-54d2de44-49dd-466f-ad35-1f9d8a5fe2f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517594998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1517594998
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1187428107
Short name T907
Test name
Test status
Simulation time 34333436 ps
CPU time 1.41 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:26 PM PDT 24
Peak memory 211568 kb
Host smart-ec7b57f7-9ecd-4825-afab-344f7d702f10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187428107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1187428107
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2687319414
Short name T135
Test name
Test status
Simulation time 232975531 ps
CPU time 2.54 seconds
Started Jul 21 06:23:08 PM PDT 24
Finished Jul 21 06:23:27 PM PDT 24
Peak memory 217788 kb
Host smart-a2eed793-deca-4741-a124-8f8bbc066e70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687319414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2687319414
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1292133356
Short name T214
Test name
Test status
Simulation time 42009691 ps
CPU time 1.33 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:31 PM PDT 24
Peak memory 209604 kb
Host smart-d6d6dc2c-5286-4eb5-86a6-d122b7282bb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292133356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1292133356
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4249812616
Short name T887
Test name
Test status
Simulation time 526144473 ps
CPU time 2.53 seconds
Started Jul 21 06:22:29 PM PDT 24
Finished Jul 21 06:22:34 PM PDT 24
Peak memory 208756 kb
Host smart-b8adb7dc-eecc-43ac-bcb3-09c1d9a2fa86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249812616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4249812616
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2370097979
Short name T908
Test name
Test status
Simulation time 16689296 ps
CPU time 1.16 seconds
Started Jul 21 06:22:30 PM PDT 24
Finished Jul 21 06:22:33 PM PDT 24
Peak memory 210208 kb
Host smart-66838734-c140-4b50-997c-6bb353fb6685
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370097979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2370097979
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2352218103
Short name T122
Test name
Test status
Simulation time 123768038 ps
CPU time 1.26 seconds
Started Jul 21 06:22:26 PM PDT 24
Finished Jul 21 06:22:29 PM PDT 24
Peak memory 219256 kb
Host smart-d3057a4e-9b99-42ff-b6a7-16569416d741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352218103 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2352218103
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2304397644
Short name T939
Test name
Test status
Simulation time 15887628 ps
CPU time 0.89 seconds
Started Jul 21 06:22:27 PM PDT 24
Finished Jul 21 06:22:30 PM PDT 24
Peak memory 209628 kb
Host smart-99ee620d-79c9-4db5-9b19-23e636936ff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304397644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2304397644
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2289469763
Short name T889
Test name
Test status
Simulation time 84344483 ps
CPU time 0.95 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:31 PM PDT 24
Peak memory 209440 kb
Host smart-e6d9b22f-3e0a-43de-96d4-126d337ce0ad
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289469763 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2289469763
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2317041625
Short name T873
Test name
Test status
Simulation time 230374879 ps
CPU time 3.3 seconds
Started Jul 21 06:22:20 PM PDT 24
Finished Jul 21 06:22:24 PM PDT 24
Peak memory 208780 kb
Host smart-40daaa23-b041-48da-8f5f-5591838b15fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317041625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2317041625
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1019123316
Short name T883
Test name
Test status
Simulation time 2642354005 ps
CPU time 11.53 seconds
Started Jul 21 06:22:21 PM PDT 24
Finished Jul 21 06:22:33 PM PDT 24
Peak memory 209592 kb
Host smart-fa25109f-902d-4801-a1c4-bd5c225f0ce7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019123316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1019123316
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.820172185
Short name T914
Test name
Test status
Simulation time 81828909 ps
CPU time 1.79 seconds
Started Jul 21 06:22:23 PM PDT 24
Finished Jul 21 06:22:27 PM PDT 24
Peak memory 211076 kb
Host smart-e0423126-751c-49b6-ae6b-86f48d4074ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820172185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.820172185
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2483856460
Short name T128
Test name
Test status
Simulation time 143061083 ps
CPU time 2.49 seconds
Started Jul 21 06:22:31 PM PDT 24
Finished Jul 21 06:22:36 PM PDT 24
Peak memory 217952 kb
Host smart-7587cc6e-cbc5-45ae-a08a-16a30be6fd06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248385
6460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2483856460
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1605291370
Short name T967
Test name
Test status
Simulation time 62237077 ps
CPU time 1.46 seconds
Started Jul 21 06:22:20 PM PDT 24
Finished Jul 21 06:22:22 PM PDT 24
Peak memory 208748 kb
Host smart-3e04abd2-83e2-4fbe-9a84-62f891e1906f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605291370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1605291370
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1537239563
Short name T990
Test name
Test status
Simulation time 55519188 ps
CPU time 1.18 seconds
Started Jul 21 06:22:29 PM PDT 24
Finished Jul 21 06:22:32 PM PDT 24
Peak memory 209644 kb
Host smart-5a48bfed-2f49-41b5-bb50-239cea9f7f74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537239563 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1537239563
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1556909231
Short name T969
Test name
Test status
Simulation time 16022771 ps
CPU time 1.18 seconds
Started Jul 21 06:22:29 PM PDT 24
Finished Jul 21 06:22:33 PM PDT 24
Peak memory 209628 kb
Host smart-fbe23d5d-9313-4c58-944b-d650c98521c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556909231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1556909231
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2905797166
Short name T985
Test name
Test status
Simulation time 781125533 ps
CPU time 3.27 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:33 PM PDT 24
Peak memory 219092 kb
Host smart-40fdae83-b06e-4838-8a4a-d767d10aa7c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905797166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2905797166
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1722267413
Short name T872
Test name
Test status
Simulation time 43858222 ps
CPU time 1.05 seconds
Started Jul 21 06:22:27 PM PDT 24
Finished Jul 21 06:22:30 PM PDT 24
Peak memory 209588 kb
Host smart-11d3e413-5f31-4327-b65f-5b56fa4153a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722267413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1722267413
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1928558692
Short name T899
Test name
Test status
Simulation time 53238934 ps
CPU time 2.01 seconds
Started Jul 21 06:22:30 PM PDT 24
Finished Jul 21 06:22:34 PM PDT 24
Peak memory 209632 kb
Host smart-086283a5-649b-4719-84f5-3abdab707da0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928558692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1928558692
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3049542695
Short name T209
Test name
Test status
Simulation time 13611921 ps
CPU time 1.03 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:32 PM PDT 24
Peak memory 209844 kb
Host smart-82e249ab-f9ec-49b9-b660-06ecc99b4d6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049542695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3049542695
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.180178851
Short name T109
Test name
Test status
Simulation time 110580057 ps
CPU time 1.21 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:31 PM PDT 24
Peak memory 217980 kb
Host smart-6e5fb81e-9344-48c7-af62-b3dd4f351453
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180178851 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.180178851
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4083804624
Short name T205
Test name
Test status
Simulation time 18325554 ps
CPU time 1.16 seconds
Started Jul 21 06:22:27 PM PDT 24
Finished Jul 21 06:22:30 PM PDT 24
Peak memory 209612 kb
Host smart-cc1b7d94-762e-4af0-98e4-888385a2586b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083804624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4083804624
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.763541607
Short name T879
Test name
Test status
Simulation time 28794727 ps
CPU time 1.15 seconds
Started Jul 21 06:22:31 PM PDT 24
Finished Jul 21 06:22:34 PM PDT 24
Peak memory 209412 kb
Host smart-4d5b5672-9f8c-4ddd-965e-ef3d382920c9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763541607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.763541607
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1012985831
Short name T960
Test name
Test status
Simulation time 6929497787 ps
CPU time 14.57 seconds
Started Jul 21 06:22:27 PM PDT 24
Finished Jul 21 06:22:42 PM PDT 24
Peak memory 209568 kb
Host smart-80456e6c-8a40-4d88-9932-b917ef09438b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012985831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1012985831
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2899848392
Short name T952
Test name
Test status
Simulation time 4041499179 ps
CPU time 21.8 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:52 PM PDT 24
Peak memory 209568 kb
Host smart-c30badc8-8397-437e-a9f5-9b10d8293eae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899848392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2899848392
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.6913809
Short name T913
Test name
Test status
Simulation time 782210143 ps
CPU time 4.77 seconds
Started Jul 21 06:22:31 PM PDT 24
Finished Jul 21 06:22:38 PM PDT 24
Peak memory 211308 kb
Host smart-713f028a-07da-422f-b519-f3e73c9d7a8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6913809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base
_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.lc_ctrl_jtag_csr_hw_reset.6913809
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1516599282
Short name T143
Test name
Test status
Simulation time 1327268299 ps
CPU time 3.2 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:34 PM PDT 24
Peak memory 217980 kb
Host smart-4b3b71f0-f0cb-4e1e-9eac-6137a968c207
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151659
9282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1516599282
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1393852772
Short name T973
Test name
Test status
Simulation time 242493340 ps
CPU time 1.74 seconds
Started Jul 21 06:22:31 PM PDT 24
Finished Jul 21 06:22:35 PM PDT 24
Peak memory 209596 kb
Host smart-755e22f9-207f-4c45-8473-74db4e63ff50
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393852772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1393852772
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3192148104
Short name T992
Test name
Test status
Simulation time 185371311 ps
CPU time 1.55 seconds
Started Jul 21 06:22:29 PM PDT 24
Finished Jul 21 06:22:32 PM PDT 24
Peak memory 209704 kb
Host smart-0821de80-4747-465c-998a-f6860906df95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192148104 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3192148104
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.153103399
Short name T962
Test name
Test status
Simulation time 444448135 ps
CPU time 1.37 seconds
Started Jul 21 06:22:30 PM PDT 24
Finished Jul 21 06:22:34 PM PDT 24
Peak memory 209640 kb
Host smart-8b4f62fc-c059-407c-b901-9eb694928e77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153103399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.153103399
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1583455049
Short name T982
Test name
Test status
Simulation time 82210497 ps
CPU time 2.23 seconds
Started Jul 21 06:22:29 PM PDT 24
Finished Jul 21 06:22:33 PM PDT 24
Peak memory 217780 kb
Host smart-d026b5f3-4450-4158-86a8-3dd73ed85acd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583455049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1583455049
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.80797322
Short name T955
Test name
Test status
Simulation time 22039369 ps
CPU time 1.27 seconds
Started Jul 21 06:22:33 PM PDT 24
Finished Jul 21 06:22:37 PM PDT 24
Peak memory 209636 kb
Host smart-92b161b5-7faa-4fa4-a504-88cae7dcfe31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80797322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing.80797322
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.273028829
Short name T935
Test name
Test status
Simulation time 95038071 ps
CPU time 1.7 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:39 PM PDT 24
Peak memory 208952 kb
Host smart-caa34ae2-ec96-4bc1-be52-34a6a24c6c24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273028829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.273028829
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.24986741
Short name T871
Test name
Test status
Simulation time 52837868 ps
CPU time 1.09 seconds
Started Jul 21 06:22:39 PM PDT 24
Finished Jul 21 06:22:46 PM PDT 24
Peak memory 210316 kb
Host smart-af0185ac-f015-4f32-a30e-c8c6f8e32bd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24986741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset.24986741
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1298846062
Short name T975
Test name
Test status
Simulation time 41030192 ps
CPU time 0.95 seconds
Started Jul 21 06:22:39 PM PDT 24
Finished Jul 21 06:22:46 PM PDT 24
Peak memory 217872 kb
Host smart-51b50e87-0520-43ff-814e-899a581e8a18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298846062 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1298846062
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.968967130
Short name T989
Test name
Test status
Simulation time 24962824 ps
CPU time 0.99 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:38 PM PDT 24
Peak memory 209608 kb
Host smart-df9d8d28-ccb2-4730-bb81-7a00de952d48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968967130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.968967130
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1009970183
Short name T924
Test name
Test status
Simulation time 26740416 ps
CPU time 1.04 seconds
Started Jul 21 06:22:32 PM PDT 24
Finished Jul 21 06:22:36 PM PDT 24
Peak memory 208192 kb
Host smart-3fd453f6-5b25-4bdf-b368-76aa4d88b860
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009970183 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1009970183
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2613069109
Short name T898
Test name
Test status
Simulation time 1196242349 ps
CPU time 8.64 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:46 PM PDT 24
Peak memory 209328 kb
Host smart-9e4eba47-fd8e-4c85-abd7-d5aec5a4c35d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613069109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2613069109
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3007306707
Short name T937
Test name
Test status
Simulation time 1958167228 ps
CPU time 5.27 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:35 PM PDT 24
Peak memory 209312 kb
Host smart-b1824bf5-5bab-49f9-84b9-bc61aac492c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007306707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3007306707
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.726596950
Short name T931
Test name
Test status
Simulation time 109088945 ps
CPU time 1.35 seconds
Started Jul 21 06:22:30 PM PDT 24
Finished Jul 21 06:22:34 PM PDT 24
Peak memory 210660 kb
Host smart-01a2e92f-e1c5-46ed-ba22-b4f77af40b8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726596950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.726596950
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2014224513
Short name T139
Test name
Test status
Simulation time 101309899 ps
CPU time 2.28 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:40 PM PDT 24
Peak memory 219144 kb
Host smart-ac55e5cc-6e2d-41d4-970f-6541aa2118e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201422
4513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2014224513
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1706273327
Short name T951
Test name
Test status
Simulation time 91755600 ps
CPU time 2.02 seconds
Started Jul 21 06:22:28 PM PDT 24
Finished Jul 21 06:22:32 PM PDT 24
Peak memory 209568 kb
Host smart-32836f3e-9744-4301-b1c3-91a1ca1ecd31
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706273327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1706273327
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2162543968
Short name T986
Test name
Test status
Simulation time 15636364 ps
CPU time 1.23 seconds
Started Jul 21 06:22:32 PM PDT 24
Finished Jul 21 06:22:36 PM PDT 24
Peak memory 209696 kb
Host smart-28c8a143-3443-43d3-bd47-bb9e60d01e99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162543968 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2162543968
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.113803472
Short name T892
Test name
Test status
Simulation time 34004927 ps
CPU time 1.39 seconds
Started Jul 21 06:22:40 PM PDT 24
Finished Jul 21 06:22:49 PM PDT 24
Peak memory 209612 kb
Host smart-fb09acb8-48d6-4e28-9a64-161c187d45e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113803472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.113803472
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.317410934
Short name T966
Test name
Test status
Simulation time 160777768 ps
CPU time 2.72 seconds
Started Jul 21 06:22:33 PM PDT 24
Finished Jul 21 06:22:39 PM PDT 24
Peak memory 217780 kb
Host smart-f3b7b085-8fcb-4d54-a263-b2050baa845a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317410934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.317410934
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2754105480
Short name T111
Test name
Test status
Simulation time 33569161 ps
CPU time 1.55 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:39 PM PDT 24
Peak memory 217984 kb
Host smart-3b9dad08-a365-46a9-96c1-19a4e7d88867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754105480 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2754105480
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.915754448
Short name T895
Test name
Test status
Simulation time 15825636 ps
CPU time 1.06 seconds
Started Jul 21 06:22:32 PM PDT 24
Finished Jul 21 06:22:36 PM PDT 24
Peak memory 209344 kb
Host smart-0253d4eb-638e-428e-9c28-21c234239aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915754448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.915754448
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2463049529
Short name T970
Test name
Test status
Simulation time 110718145 ps
CPU time 2.52 seconds
Started Jul 21 06:22:33 PM PDT 24
Finished Jul 21 06:22:39 PM PDT 24
Peak memory 209492 kb
Host smart-b7b9dbdb-7b4e-4cdf-a80b-da2a78a23122
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463049529 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2463049529
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2540068807
Short name T875
Test name
Test status
Simulation time 408297404 ps
CPU time 9.79 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:48 PM PDT 24
Peak memory 208060 kb
Host smart-923bc42c-2a26-4dc7-8ab6-d9b5ff443a78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540068807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2540068807
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3158524361
Short name T877
Test name
Test status
Simulation time 984662070 ps
CPU time 4.67 seconds
Started Jul 21 06:22:33 PM PDT 24
Finished Jul 21 06:22:41 PM PDT 24
Peak memory 208800 kb
Host smart-11c7ee58-8a29-4a5d-9beb-a3b875321e6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158524361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3158524361
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2638143194
Short name T936
Test name
Test status
Simulation time 124389319 ps
CPU time 3.58 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:41 PM PDT 24
Peak memory 211396 kb
Host smart-038f4776-182f-483e-9dcd-f3436fc22ffb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638143194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2638143194
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.475768637
Short name T884
Test name
Test status
Simulation time 798928565 ps
CPU time 1.79 seconds
Started Jul 21 06:22:40 PM PDT 24
Finished Jul 21 06:22:48 PM PDT 24
Peak memory 217872 kb
Host smart-e1e336a0-fba2-4d42-8dd4-6f04d4fdb53c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475768
637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.475768637
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4072053872
Short name T910
Test name
Test status
Simulation time 39105237 ps
CPU time 1.24 seconds
Started Jul 21 06:22:40 PM PDT 24
Finished Jul 21 06:22:48 PM PDT 24
Peak memory 209508 kb
Host smart-cc8cb59a-7a17-4986-a13f-1af5d9a060ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072053872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4072053872
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1792047338
Short name T221
Test name
Test status
Simulation time 56254589 ps
CPU time 1.46 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:39 PM PDT 24
Peak memory 209700 kb
Host smart-7a2bccc3-7c77-4984-b0aa-b637f2894400
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792047338 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1792047338
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3443202158
Short name T915
Test name
Test status
Simulation time 81898513 ps
CPU time 1.37 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:39 PM PDT 24
Peak memory 211424 kb
Host smart-1b92fcb7-19d8-4b0f-8396-53443bb60b14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443202158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3443202158
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1297643164
Short name T880
Test name
Test status
Simulation time 412230701 ps
CPU time 4.33 seconds
Started Jul 21 06:22:33 PM PDT 24
Finished Jul 21 06:22:41 PM PDT 24
Peak memory 217868 kb
Host smart-808fce9c-cd75-4892-b90a-27111ae10917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297643164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1297643164
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4277473918
Short name T121
Test name
Test status
Simulation time 759354829 ps
CPU time 2.78 seconds
Started Jul 21 06:22:34 PM PDT 24
Finished Jul 21 06:22:40 PM PDT 24
Peak memory 222516 kb
Host smart-7fb911ad-ed88-40e4-929f-7adec29e1696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277473918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4277473918
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4176476948
Short name T921
Test name
Test status
Simulation time 103990116 ps
CPU time 1.08 seconds
Started Jul 21 06:22:42 PM PDT 24
Finished Jul 21 06:22:51 PM PDT 24
Peak memory 217932 kb
Host smart-062b0f0d-8a59-4523-aa1c-76e9e0e31dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176476948 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.4176476948
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.913735886
Short name T890
Test name
Test status
Simulation time 33138542 ps
CPU time 0.91 seconds
Started Jul 21 06:22:41 PM PDT 24
Finished Jul 21 06:22:49 PM PDT 24
Peak memory 209640 kb
Host smart-c056d320-9bf9-4fc8-82d9-b1d46daf2f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913735886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.913735886
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.550678212
Short name T942
Test name
Test status
Simulation time 50627267 ps
CPU time 1.92 seconds
Started Jul 21 06:22:40 PM PDT 24
Finished Jul 21 06:22:48 PM PDT 24
Peak memory 208256 kb
Host smart-14b946c7-6f76-4e61-8a4f-3b08e023bf4f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550678212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.550678212
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3628793179
Short name T945
Test name
Test status
Simulation time 2992646043 ps
CPU time 17.09 seconds
Started Jul 21 06:22:41 PM PDT 24
Finished Jul 21 06:23:05 PM PDT 24
Peak memory 209644 kb
Host smart-e8f6939d-1948-4187-aca2-289c9d677750
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628793179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3628793179
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.980366528
Short name T878
Test name
Test status
Simulation time 1398065486 ps
CPU time 18.82 seconds
Started Jul 21 06:22:39 PM PDT 24
Finished Jul 21 06:23:04 PM PDT 24
Peak memory 209524 kb
Host smart-f06f3218-4b02-45d2-bd38-c945edbff2b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980366528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.980366528
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4253248851
Short name T140
Test name
Test status
Simulation time 97940160 ps
CPU time 3.14 seconds
Started Jul 21 06:22:40 PM PDT 24
Finished Jul 21 06:22:49 PM PDT 24
Peak memory 211268 kb
Host smart-fa319953-54a2-4048-b038-87d985fb62a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253248851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4253248851
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2087630283
Short name T909
Test name
Test status
Simulation time 1793206393 ps
CPU time 2.36 seconds
Started Jul 21 06:22:40 PM PDT 24
Finished Jul 21 06:22:49 PM PDT 24
Peak memory 219628 kb
Host smart-2c36b9d8-77ba-48e1-bc84-27e465b6112d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208763
0283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2087630283
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3912746392
Short name T881
Test name
Test status
Simulation time 258048302 ps
CPU time 2.43 seconds
Started Jul 21 06:22:41 PM PDT 24
Finished Jul 21 06:22:50 PM PDT 24
Peak memory 209552 kb
Host smart-6785b55a-8616-4073-a813-4aff166f9faf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912746392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3912746392
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1881623313
Short name T117
Test name
Test status
Simulation time 105878141 ps
CPU time 1.22 seconds
Started Jul 21 06:22:40 PM PDT 24
Finished Jul 21 06:22:47 PM PDT 24
Peak memory 209660 kb
Host smart-fadf2e00-0c78-4a00-817c-e0acf15857a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881623313 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1881623313
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3583561700
Short name T922
Test name
Test status
Simulation time 32105947 ps
CPU time 1.54 seconds
Started Jul 21 06:22:41 PM PDT 24
Finished Jul 21 06:22:51 PM PDT 24
Peak memory 209632 kb
Host smart-678d5c37-090c-4ade-8fdb-a670fca74a0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583561700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3583561700
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2367074374
Short name T943
Test name
Test status
Simulation time 388605719 ps
CPU time 2.98 seconds
Started Jul 21 06:22:41 PM PDT 24
Finished Jul 21 06:22:52 PM PDT 24
Peak memory 217816 kb
Host smart-47f888dd-2a1a-43a8-8b98-5d97a3d22b53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367074374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2367074374
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.572924348
Short name T930
Test name
Test status
Simulation time 181575914 ps
CPU time 1.51 seconds
Started Jul 21 06:22:45 PM PDT 24
Finished Jul 21 06:22:55 PM PDT 24
Peak memory 217900 kb
Host smart-5d03fb5e-0256-424d-b732-4a0f5b350215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572924348 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.572924348
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2319760490
Short name T216
Test name
Test status
Simulation time 53211746 ps
CPU time 1.02 seconds
Started Jul 21 06:22:47 PM PDT 24
Finished Jul 21 06:22:56 PM PDT 24
Peak memory 209596 kb
Host smart-8999a148-3d33-44ec-865a-0cac299d7fd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319760490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2319760490
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1978541994
Short name T965
Test name
Test status
Simulation time 114412073 ps
CPU time 1.44 seconds
Started Jul 21 06:22:48 PM PDT 24
Finished Jul 21 06:22:58 PM PDT 24
Peak memory 209468 kb
Host smart-a915ae81-92ad-4893-b361-dd0cd4b537ff
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978541994 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1978541994
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1159301443
Short name T141
Test name
Test status
Simulation time 2991668886 ps
CPU time 7.6 seconds
Started Jul 21 06:22:40 PM PDT 24
Finished Jul 21 06:22:55 PM PDT 24
Peak memory 208892 kb
Host smart-70500880-2899-4d37-83fb-f2b71458bc25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159301443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1159301443
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2124927857
Short name T953
Test name
Test status
Simulation time 351623117 ps
CPU time 9.33 seconds
Started Jul 21 06:22:41 PM PDT 24
Finished Jul 21 06:22:58 PM PDT 24
Peak memory 209548 kb
Host smart-2acf566c-d847-4c8a-9909-e153337c7323
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124927857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2124927857
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1519702443
Short name T979
Test name
Test status
Simulation time 1869669140 ps
CPU time 1.85 seconds
Started Jul 21 06:22:41 PM PDT 24
Finished Jul 21 06:22:51 PM PDT 24
Peak memory 211144 kb
Host smart-9d5e80ef-0533-4980-b116-f5cfa9b03ed3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519702443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1519702443
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3120735269
Short name T142
Test name
Test status
Simulation time 91161909 ps
CPU time 2.43 seconds
Started Jul 21 06:22:41 PM PDT 24
Finished Jul 21 06:22:51 PM PDT 24
Peak memory 209496 kb
Host smart-a7055ef4-983f-4441-b213-365439e46797
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120735269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3120735269
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3680783591
Short name T116
Test name
Test status
Simulation time 101895688 ps
CPU time 1.29 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:04 PM PDT 24
Peak memory 209612 kb
Host smart-af9a7ceb-db4f-40ed-a8aa-fc73f6a86ccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680783591 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3680783591
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1597172776
Short name T978
Test name
Test status
Simulation time 163586958 ps
CPU time 1.83 seconds
Started Jul 21 06:22:49 PM PDT 24
Finished Jul 21 06:23:00 PM PDT 24
Peak memory 209620 kb
Host smart-e1257f0a-2bfb-4910-8fa4-8da2463b9c9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597172776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1597172776
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2970824888
Short name T980
Test name
Test status
Simulation time 46787478 ps
CPU time 2.95 seconds
Started Jul 21 06:22:47 PM PDT 24
Finished Jul 21 06:22:58 PM PDT 24
Peak memory 219860 kb
Host smart-4b6d3f90-d6f0-4cc1-804d-c2a5ea102ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970824888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2970824888
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1595035320
Short name T133
Test name
Test status
Simulation time 45713259 ps
CPU time 2.36 seconds
Started Jul 21 06:22:50 PM PDT 24
Finished Jul 21 06:23:01 PM PDT 24
Peak memory 222320 kb
Host smart-19e652b1-801d-4031-9e2a-a47c4578eb61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595035320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1595035320
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2059026024
Short name T963
Test name
Test status
Simulation time 79394062 ps
CPU time 1.35 seconds
Started Jul 21 06:22:46 PM PDT 24
Finished Jul 21 06:22:56 PM PDT 24
Peak memory 218536 kb
Host smart-a675f553-22d3-48bb-89fc-e8e1c5c4ad7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059026024 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2059026024
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3525898027
Short name T204
Test name
Test status
Simulation time 17345522 ps
CPU time 0.97 seconds
Started Jul 21 06:22:48 PM PDT 24
Finished Jul 21 06:22:58 PM PDT 24
Peak memory 209608 kb
Host smart-10de1130-3480-422d-8b26-db1dfc4fb534
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525898027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3525898027
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1194586715
Short name T906
Test name
Test status
Simulation time 248062730 ps
CPU time 1.13 seconds
Started Jul 21 06:22:48 PM PDT 24
Finished Jul 21 06:22:57 PM PDT 24
Peak memory 209468 kb
Host smart-354f51c2-894e-4f6c-8e40-14562f06376b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194586715 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1194586715
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1399963316
Short name T886
Test name
Test status
Simulation time 1159182048 ps
CPU time 14.04 seconds
Started Jul 21 06:22:46 PM PDT 24
Finished Jul 21 06:23:09 PM PDT 24
Peak memory 208772 kb
Host smart-043e1205-049f-4a79-9835-561f34bae64d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399963316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1399963316
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.302667669
Short name T950
Test name
Test status
Simulation time 2114974411 ps
CPU time 12.83 seconds
Started Jul 21 06:22:48 PM PDT 24
Finished Jul 21 06:23:09 PM PDT 24
Peak memory 209416 kb
Host smart-fc61c16c-ec8c-4d6c-bfa2-cf929e89a6ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302667669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.302667669
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.640066610
Short name T885
Test name
Test status
Simulation time 331971649 ps
CPU time 2.67 seconds
Started Jul 21 06:22:47 PM PDT 24
Finished Jul 21 06:22:58 PM PDT 24
Peak memory 211028 kb
Host smart-29731f64-7a3b-4653-b167-dee86326f390
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640066610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.640066610
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2370460129
Short name T891
Test name
Test status
Simulation time 374286211 ps
CPU time 2.13 seconds
Started Jul 21 06:22:48 PM PDT 24
Finished Jul 21 06:22:59 PM PDT 24
Peak memory 217908 kb
Host smart-842e89e5-290e-4d65-8755-f71ec39d813e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237046
0129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2370460129
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1834130412
Short name T948
Test name
Test status
Simulation time 532680591 ps
CPU time 3.89 seconds
Started Jul 21 06:22:46 PM PDT 24
Finished Jul 21 06:22:58 PM PDT 24
Peak memory 209552 kb
Host smart-e5e94937-89db-4b33-93c1-7b967bca521b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834130412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1834130412
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3756471982
Short name T222
Test name
Test status
Simulation time 101181323 ps
CPU time 1.53 seconds
Started Jul 21 06:22:48 PM PDT 24
Finished Jul 21 06:22:58 PM PDT 24
Peak memory 211784 kb
Host smart-1a7b25c6-8da6-4580-9503-e4b0c50a539c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756471982 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3756471982
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1833120590
Short name T159
Test name
Test status
Simulation time 46201080 ps
CPU time 1.51 seconds
Started Jul 21 06:22:49 PM PDT 24
Finished Jul 21 06:22:59 PM PDT 24
Peak memory 209768 kb
Host smart-876722bb-fd3e-4340-8ae0-d6efac3965dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833120590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1833120590
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4074842029
Short name T928
Test name
Test status
Simulation time 181554826 ps
CPU time 2.85 seconds
Started Jul 21 06:22:46 PM PDT 24
Finished Jul 21 06:22:57 PM PDT 24
Peak memory 218856 kb
Host smart-edf1a9a1-d048-40d4-8f12-a91e129b0b4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074842029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.4074842029
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3899770458
Short name T988
Test name
Test status
Simulation time 304271532 ps
CPU time 2.7 seconds
Started Jul 21 06:22:47 PM PDT 24
Finished Jul 21 06:22:58 PM PDT 24
Peak memory 217828 kb
Host smart-7414a26e-2f98-419d-af82-30c603fa26b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899770458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3899770458
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2001328217
Short name T901
Test name
Test status
Simulation time 72386874 ps
CPU time 1.48 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:05 PM PDT 24
Peak memory 217928 kb
Host smart-407c26a3-4bbf-4a4e-9fed-d163791ce4a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001328217 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2001328217
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3477356350
Short name T971
Test name
Test status
Simulation time 13662057 ps
CPU time 1.1 seconds
Started Jul 21 06:22:54 PM PDT 24
Finished Jul 21 06:23:05 PM PDT 24
Peak memory 209260 kb
Host smart-cbdfab7c-635e-41d8-a35d-915ee27c6639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477356350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3477356350
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2066587122
Short name T923
Test name
Test status
Simulation time 166652208 ps
CPU time 1.37 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:03 PM PDT 24
Peak memory 209460 kb
Host smart-2b72e444-2541-4f22-80a0-500df3375c0a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066587122 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2066587122
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4270512829
Short name T917
Test name
Test status
Simulation time 1975064054 ps
CPU time 12.37 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:15 PM PDT 24
Peak memory 208808 kb
Host smart-84d27f3e-227e-4d77-9264-99e769b7d17f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270512829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.4270512829
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3660470848
Short name T957
Test name
Test status
Simulation time 1902508896 ps
CPU time 11.21 seconds
Started Jul 21 06:22:52 PM PDT 24
Finished Jul 21 06:23:12 PM PDT 24
Peak memory 209376 kb
Host smart-a6484d3b-ac86-4b71-8c52-26f71075556e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660470848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3660470848
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2516379706
Short name T903
Test name
Test status
Simulation time 276618538 ps
CPU time 1.58 seconds
Started Jul 21 06:22:55 PM PDT 24
Finished Jul 21 06:23:07 PM PDT 24
Peak memory 211012 kb
Host smart-74af9f20-7d2c-4e18-baa7-f04bded26f8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516379706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2516379706
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2336910640
Short name T964
Test name
Test status
Simulation time 436449815 ps
CPU time 2.63 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:05 PM PDT 24
Peak memory 219128 kb
Host smart-8a214856-d7a9-4f7b-a425-4becd456efed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233691
0640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2336910640
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.245552857
Short name T916
Test name
Test status
Simulation time 131169781 ps
CPU time 1.39 seconds
Started Jul 21 06:22:52 PM PDT 24
Finished Jul 21 06:23:02 PM PDT 24
Peak memory 209556 kb
Host smart-1ece0843-995f-470c-9516-1cf7b5d5c4ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245552857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.245552857
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3868840607
Short name T946
Test name
Test status
Simulation time 100270674 ps
CPU time 1.17 seconds
Started Jul 21 06:22:53 PM PDT 24
Finished Jul 21 06:23:03 PM PDT 24
Peak memory 209616 kb
Host smart-247a1d32-6cc3-4c7b-bec3-a800a6a8553d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868840607 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3868840607
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2444955168
Short name T987
Test name
Test status
Simulation time 52281338 ps
CPU time 1.17 seconds
Started Jul 21 06:22:52 PM PDT 24
Finished Jul 21 06:23:03 PM PDT 24
Peak memory 209792 kb
Host smart-1e702135-e508-4b8e-b048-20923ce71aa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444955168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2444955168
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2315825134
Short name T929
Test name
Test status
Simulation time 463519566 ps
CPU time 2.9 seconds
Started Jul 21 06:22:54 PM PDT 24
Finished Jul 21 06:23:07 PM PDT 24
Peak memory 218612 kb
Host smart-8ea67b24-35d1-4605-9408-f4f4970917a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315825134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2315825134
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1815158372
Short name T941
Test name
Test status
Simulation time 58910681 ps
CPU time 2.01 seconds
Started Jul 21 06:22:54 PM PDT 24
Finished Jul 21 06:23:06 PM PDT 24
Peak memory 222576 kb
Host smart-ddeb9783-b5b8-4647-8028-9462fdb080f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815158372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1815158372
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.857999857
Short name T260
Test name
Test status
Simulation time 46737802 ps
CPU time 1.16 seconds
Started Jul 21 06:24:33 PM PDT 24
Finished Jul 21 06:24:35 PM PDT 24
Peak memory 209040 kb
Host smart-32832cf9-374e-4a26-ac6e-c1ed248e269f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857999857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.857999857
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2907029874
Short name T648
Test name
Test status
Simulation time 591654060 ps
CPU time 14.42 seconds
Started Jul 21 06:24:32 PM PDT 24
Finished Jul 21 06:24:48 PM PDT 24
Peak memory 218388 kb
Host smart-f694dd0a-428a-43fb-bea7-ef373b235a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907029874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2907029874
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3046010447
Short name T755
Test name
Test status
Simulation time 4863038619 ps
CPU time 10.93 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:24:51 PM PDT 24
Peak memory 217836 kb
Host smart-8f8c6164-4124-4af4-b95d-fe0c0706a003
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046010447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3046010447
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2845288362
Short name T419
Test name
Test status
Simulation time 3565997897 ps
CPU time 45.48 seconds
Started Jul 21 06:24:32 PM PDT 24
Finished Jul 21 06:25:19 PM PDT 24
Peak memory 220032 kb
Host smart-c9d53fed-a2e1-41ef-a68c-dd04b95ea3af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845288362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2845288362
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1677716944
Short name T766
Test name
Test status
Simulation time 228399852 ps
CPU time 3.73 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:24:42 PM PDT 24
Peak memory 217828 kb
Host smart-1b9e2c6a-e8d8-473b-b190-3671ac7bdff3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677716944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
677716944
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.375766
Short name T390
Test name
Test status
Simulation time 3067838452 ps
CPU time 10.09 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:42 PM PDT 24
Peak memory 225936 kb
Host smart-facbb235-d1a9-44ee-a6fb-f2be66ebdf6b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_pro
g_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_pro
g_failure.375766
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3907129970
Short name T68
Test name
Test status
Simulation time 914602286 ps
CPU time 25.51 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:57 PM PDT 24
Peak memory 217704 kb
Host smart-d0caba18-3933-41f7-b56c-96ec70be93e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907129970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3907129970
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2827702859
Short name T331
Test name
Test status
Simulation time 119182887 ps
CPU time 4.71 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:37 PM PDT 24
Peak memory 217732 kb
Host smart-fa956263-5e9f-4226-883b-ea646a398308
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827702859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2827702859
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1175568955
Short name T731
Test name
Test status
Simulation time 9429491139 ps
CPU time 49.72 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:25:26 PM PDT 24
Peak memory 275732 kb
Host smart-5062dbc0-4d7e-4740-beaf-174df3450adb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175568955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1175568955
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.745947160
Short name T868
Test name
Test status
Simulation time 734341820 ps
CPU time 26.45 seconds
Started Jul 21 06:24:40 PM PDT 24
Finished Jul 21 06:25:07 PM PDT 24
Peak memory 251000 kb
Host smart-1e75a4d1-c48e-4de1-ae14-caad6418ffc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745947160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.745947160
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.342042685
Short name T591
Test name
Test status
Simulation time 87938398 ps
CPU time 1.68 seconds
Started Jul 21 06:24:40 PM PDT 24
Finished Jul 21 06:24:42 PM PDT 24
Peak memory 218320 kb
Host smart-240455d0-4a78-4b7e-82b8-c6e87e4b7800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342042685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.342042685
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1216365776
Short name T95
Test name
Test status
Simulation time 336883674 ps
CPU time 22.14 seconds
Started Jul 21 06:24:35 PM PDT 24
Finished Jul 21 06:24:58 PM PDT 24
Peak memory 282436 kb
Host smart-8ba51598-4a1b-440f-90b6-31e3148a9e95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216365776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1216365776
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2797968400
Short name T455
Test name
Test status
Simulation time 383427497 ps
CPU time 15 seconds
Started Jul 21 06:24:35 PM PDT 24
Finished Jul 21 06:24:51 PM PDT 24
Peak memory 226124 kb
Host smart-6d6882e6-2702-4cb9-8db4-1624b9e13c25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797968400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2797968400
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3611789558
Short name T536
Test name
Test status
Simulation time 568380691 ps
CPU time 16.55 seconds
Started Jul 21 06:24:32 PM PDT 24
Finished Jul 21 06:24:50 PM PDT 24
Peak memory 226080 kb
Host smart-22ed7d01-45b5-4246-b471-7a1ef0b770eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611789558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3611789558
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3116691490
Short name T267
Test name
Test status
Simulation time 977744186 ps
CPU time 9.92 seconds
Started Jul 21 06:24:35 PM PDT 24
Finished Jul 21 06:24:45 PM PDT 24
Peak memory 218320 kb
Host smart-5753a83f-9117-4f44-b503-a1db8abea22d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116691490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
116691490
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3982034126
Short name T330
Test name
Test status
Simulation time 175858200 ps
CPU time 6.47 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:38 PM PDT 24
Peak memory 218428 kb
Host smart-a9fa2182-7a0e-4e21-a080-0e3e71228167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982034126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3982034126
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1275109953
Short name T423
Test name
Test status
Simulation time 174473169 ps
CPU time 2.02 seconds
Started Jul 21 06:24:32 PM PDT 24
Finished Jul 21 06:24:35 PM PDT 24
Peak memory 214040 kb
Host smart-62b5a417-5d73-487b-b398-098755e4abfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275109953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1275109953
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2528010165
Short name T387
Test name
Test status
Simulation time 206406942 ps
CPU time 18.77 seconds
Started Jul 21 06:24:32 PM PDT 24
Finished Jul 21 06:24:51 PM PDT 24
Peak memory 250908 kb
Host smart-2fb805f8-2eef-4a82-a054-44673d5c8e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528010165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2528010165
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1376390260
Short name T365
Test name
Test status
Simulation time 220025121 ps
CPU time 6.51 seconds
Started Jul 21 06:24:35 PM PDT 24
Finished Jul 21 06:24:41 PM PDT 24
Peak memory 247280 kb
Host smart-010a20f4-27f8-45c9-8b58-c3b98e6f509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376390260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1376390260
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2143027640
Short name T335
Test name
Test status
Simulation time 153347484 ps
CPU time 0.97 seconds
Started Jul 21 06:24:34 PM PDT 24
Finished Jul 21 06:24:35 PM PDT 24
Peak memory 212000 kb
Host smart-881de0f9-1319-4f7d-94bd-d0316b248f4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143027640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2143027640
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1074909641
Short name T778
Test name
Test status
Simulation time 23663932 ps
CPU time 0.97 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:24:41 PM PDT 24
Peak memory 208860 kb
Host smart-4ebeb86e-1812-4ae8-b166-515f14989af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074909641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1074909641
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2777705272
Short name T310
Test name
Test status
Simulation time 13463659 ps
CPU time 0.98 seconds
Started Jul 21 06:24:38 PM PDT 24
Finished Jul 21 06:24:40 PM PDT 24
Peak memory 208932 kb
Host smart-15bb17b3-b277-4651-88aa-1b7d4f6df82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777705272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2777705272
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2916192003
Short name T666
Test name
Test status
Simulation time 1187714203 ps
CPU time 13.21 seconds
Started Jul 21 06:24:33 PM PDT 24
Finished Jul 21 06:24:47 PM PDT 24
Peak memory 218376 kb
Host smart-d9fdb86e-5774-4911-a292-b4dfbdbd8708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916192003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2916192003
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3643373146
Short name T474
Test name
Test status
Simulation time 696756714 ps
CPU time 5.37 seconds
Started Jul 21 06:24:40 PM PDT 24
Finished Jul 21 06:24:46 PM PDT 24
Peak memory 217368 kb
Host smart-12d0bf7c-d8de-4e1e-969d-cec2aba23132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643373146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3643373146
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3072551817
Short name T41
Test name
Test status
Simulation time 11641935323 ps
CPU time 84.22 seconds
Started Jul 21 06:24:43 PM PDT 24
Finished Jul 21 06:26:07 PM PDT 24
Peak memory 218976 kb
Host smart-73e18425-b084-472e-ba6f-8901ef7df9c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072551817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3072551817
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.4052789946
Short name T165
Test name
Test status
Simulation time 777555724 ps
CPU time 5.74 seconds
Started Jul 21 06:24:45 PM PDT 24
Finished Jul 21 06:24:52 PM PDT 24
Peak memory 217496 kb
Host smart-e651301b-60a7-4364-8c84-6f8ef471a590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052789946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.4
052789946
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1377994171
Short name T25
Test name
Test status
Simulation time 676017602 ps
CPU time 3.89 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:24:42 PM PDT 24
Peak memory 218312 kb
Host smart-07a09bf7-f78b-45a1-983f-c71a61a7f6e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377994171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1377994171
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1661906347
Short name T282
Test name
Test status
Simulation time 8141902395 ps
CPU time 21.52 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:25:01 PM PDT 24
Peak memory 217756 kb
Host smart-9ceff328-859e-4b88-aca4-f49948a83768
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661906347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1661906347
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3375973981
Short name T542
Test name
Test status
Simulation time 2331432107 ps
CPU time 5.82 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:24:44 PM PDT 24
Peak memory 217828 kb
Host smart-a1d462d2-cdd9-4997-bab8-8f2555968d54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375973981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3375973981
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.371123170
Short name T409
Test name
Test status
Simulation time 44278085506 ps
CPU time 90.31 seconds
Started Jul 21 06:24:40 PM PDT 24
Finished Jul 21 06:26:11 PM PDT 24
Peak memory 280520 kb
Host smart-38bbf6b0-6e04-4d07-93a2-7107c0614733
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371123170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.371123170
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1198135907
Short name T441
Test name
Test status
Simulation time 1564847401 ps
CPU time 16.34 seconds
Started Jul 21 06:24:38 PM PDT 24
Finished Jul 21 06:24:55 PM PDT 24
Peak memory 245516 kb
Host smart-c9cb571a-beb8-4342-814e-8b4190d90f12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198135907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1198135907
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1273968337
Short name T191
Test name
Test status
Simulation time 72022779 ps
CPU time 3.47 seconds
Started Jul 21 06:24:33 PM PDT 24
Finished Jul 21 06:24:38 PM PDT 24
Peak memory 218388 kb
Host smart-fa78526b-0891-48a9-8e5b-b8f295f6d7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273968337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1273968337
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.363224729
Short name T473
Test name
Test status
Simulation time 865218132 ps
CPU time 14.22 seconds
Started Jul 21 06:24:43 PM PDT 24
Finished Jul 21 06:24:57 PM PDT 24
Peak memory 214156 kb
Host smart-333247a6-783a-4d94-af6f-ec9f2e7bb7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363224729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.363224729
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1544288034
Short name T40
Test name
Test status
Simulation time 477414051 ps
CPU time 26.09 seconds
Started Jul 21 06:24:42 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 268992 kb
Host smart-b4174269-68b7-4638-a494-06b9dad1354d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544288034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1544288034
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.695788509
Short name T177
Test name
Test status
Simulation time 430132798 ps
CPU time 14.49 seconds
Started Jul 21 06:24:40 PM PDT 24
Finished Jul 21 06:24:56 PM PDT 24
Peak memory 219040 kb
Host smart-1b4a0746-f184-43d6-9751-60296a54f217
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695788509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.695788509
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1160619039
Short name T430
Test name
Test status
Simulation time 387075006 ps
CPU time 10.39 seconds
Started Jul 21 06:24:45 PM PDT 24
Finished Jul 21 06:24:56 PM PDT 24
Peak memory 226100 kb
Host smart-f6480af5-2d57-4689-9cde-02d20dfd3a19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160619039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1160619039
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1176252708
Short name T808
Test name
Test status
Simulation time 2963502875 ps
CPU time 14.48 seconds
Started Jul 21 06:24:43 PM PDT 24
Finished Jul 21 06:24:58 PM PDT 24
Peak memory 218328 kb
Host smart-b37938dd-71f2-4436-9e1a-443155893a40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176252708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
176252708
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3141632917
Short name T490
Test name
Test status
Simulation time 1729828016 ps
CPU time 6.95 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:24:44 PM PDT 24
Peak memory 226160 kb
Host smart-28f8aa88-6290-49e4-8bc7-f939d113398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141632917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3141632917
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3795187302
Short name T432
Test name
Test status
Simulation time 14119481 ps
CPU time 1.24 seconds
Started Jul 21 06:24:34 PM PDT 24
Finished Jul 21 06:24:36 PM PDT 24
Peak memory 214080 kb
Host smart-edaf38a7-26d9-4aef-9f1d-214cbf913e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795187302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3795187302
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.4041776125
Short name T592
Test name
Test status
Simulation time 255667912 ps
CPU time 32.02 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:25:10 PM PDT 24
Peak memory 251104 kb
Host smart-9e695342-626f-443e-a72a-3a5c4ac4ce4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041776125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.4041776125
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.881808719
Short name T600
Test name
Test status
Simulation time 127870332 ps
CPU time 7.33 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:24:46 PM PDT 24
Peak memory 251104 kb
Host smart-4b9e2c2c-6add-48a0-b50a-5fc13b374aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881808719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.881808719
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.571327953
Short name T46
Test name
Test status
Simulation time 3871296345 ps
CPU time 104.28 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:26:23 PM PDT 24
Peak memory 251244 kb
Host smart-02319bca-f534-409b-9be1-9c479ad29d56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571327953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.571327953
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2034804157
Short name T306
Test name
Test status
Simulation time 23051557 ps
CPU time 0.84 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:24:38 PM PDT 24
Peak memory 211980 kb
Host smart-8122a1c8-f9ab-4437-855a-af1682ec24e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034804157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2034804157
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.312196843
Short name T377
Test name
Test status
Simulation time 26611131 ps
CPU time 1.01 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 208960 kb
Host smart-3c74f801-a0eb-4d08-b53f-666ec4ce3c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312196843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.312196843
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2136795536
Short name T475
Test name
Test status
Simulation time 2174578859 ps
CPU time 15.52 seconds
Started Jul 21 06:25:11 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 226240 kb
Host smart-5ba061e6-10fa-4e6d-8ab5-a7e4f3dbbe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136795536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2136795536
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2457789194
Short name T727
Test name
Test status
Simulation time 488886339 ps
CPU time 6.3 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:18 PM PDT 24
Peak memory 217564 kb
Host smart-6235ec0f-8304-4074-aa5b-279d1031f0db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457789194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2457789194
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.643574350
Short name T291
Test name
Test status
Simulation time 8489644116 ps
CPU time 27.57 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:39 PM PDT 24
Peak memory 218504 kb
Host smart-e57d1e55-daf8-4b73-8044-05865f72ec03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643574350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.643574350
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2166667531
Short name T581
Test name
Test status
Simulation time 163743961 ps
CPU time 5.76 seconds
Started Jul 21 06:25:12 PM PDT 24
Finished Jul 21 06:25:18 PM PDT 24
Peak memory 218316 kb
Host smart-c2dc3731-4e84-4679-8f78-4c639e7a589d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166667531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2166667531
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.91876840
Short name T81
Test name
Test status
Simulation time 687133483 ps
CPU time 5.59 seconds
Started Jul 21 06:25:11 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 217716 kb
Host smart-efa4004d-506e-4690-b6ef-ed372e7b3467
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91876840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.91876840
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3296198895
Short name T705
Test name
Test status
Simulation time 5615359473 ps
CPU time 44.24 seconds
Started Jul 21 06:25:11 PM PDT 24
Finished Jul 21 06:25:56 PM PDT 24
Peak memory 275692 kb
Host smart-da6aef73-1430-4d7f-a16f-7d519b504270
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296198895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3296198895
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1796193858
Short name T312
Test name
Test status
Simulation time 495357051 ps
CPU time 21.62 seconds
Started Jul 21 06:25:12 PM PDT 24
Finished Jul 21 06:25:34 PM PDT 24
Peak memory 251064 kb
Host smart-c05d969d-783a-494a-bd4d-7b7c7139930b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796193858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1796193858
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.609407583
Short name T249
Test name
Test status
Simulation time 964341071 ps
CPU time 3.08 seconds
Started Jul 21 06:25:11 PM PDT 24
Finished Jul 21 06:25:15 PM PDT 24
Peak memory 218364 kb
Host smart-28d73dfb-bd6d-4922-902b-4e1382da1bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609407583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.609407583
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1948677870
Short name T286
Test name
Test status
Simulation time 1307206764 ps
CPU time 11.74 seconds
Started Jul 21 06:25:08 PM PDT 24
Finished Jul 21 06:25:21 PM PDT 24
Peak memory 219036 kb
Host smart-a3f88243-e994-4ab9-b8f8-2a15c87efdd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948677870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1948677870
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.231809968
Short name T769
Test name
Test status
Simulation time 1089816161 ps
CPU time 11.15 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:22 PM PDT 24
Peak memory 225500 kb
Host smart-c7835c17-8be3-4399-9605-60d95cfb2b41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231809968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.231809968
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2594862431
Short name T562
Test name
Test status
Simulation time 7400479291 ps
CPU time 10.79 seconds
Started Jul 21 06:25:08 PM PDT 24
Finished Jul 21 06:25:20 PM PDT 24
Peak memory 218316 kb
Host smart-9bc8ee62-f3d7-42ce-9c21-577f3d145b5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594862431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2594862431
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.769276353
Short name T75
Test name
Test status
Simulation time 99790784 ps
CPU time 2.39 seconds
Started Jul 21 06:25:11 PM PDT 24
Finished Jul 21 06:25:14 PM PDT 24
Peak memory 217848 kb
Host smart-b74283c8-c05f-46ce-ba30-7c45f249befc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769276353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.769276353
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.129634902
Short name T105
Test name
Test status
Simulation time 350590510 ps
CPU time 31.51 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:42 PM PDT 24
Peak memory 251096 kb
Host smart-73758d1f-c7eb-461f-b739-bc16cd7dfb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129634902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.129634902
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1290491346
Short name T459
Test name
Test status
Simulation time 406373428 ps
CPU time 6.51 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 247092 kb
Host smart-478479a8-07bd-4c5f-b560-6f5c84cf1afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290491346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1290491346
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.4081997282
Short name T683
Test name
Test status
Simulation time 4192221836 ps
CPU time 83.96 seconds
Started Jul 21 06:25:08 PM PDT 24
Finished Jul 21 06:26:33 PM PDT 24
Peak memory 276356 kb
Host smart-cccff5fe-b950-411d-87cc-c28dd13ec1d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081997282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.4081997282
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.843697754
Short name T169
Test name
Test status
Simulation time 161521857979 ps
CPU time 1101.79 seconds
Started Jul 21 06:25:09 PM PDT 24
Finished Jul 21 06:43:32 PM PDT 24
Peak memory 447932 kb
Host smart-2ace4d78-60cf-497f-b1a5-c017b3da8c00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=843697754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.843697754
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3767767204
Short name T252
Test name
Test status
Simulation time 14054367 ps
CPU time 0.96 seconds
Started Jul 21 06:25:11 PM PDT 24
Finished Jul 21 06:25:13 PM PDT 24
Peak memory 211904 kb
Host smart-10a773ab-650f-4c15-a5f2-2e5cfb9bc886
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767767204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3767767204
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3976699406
Short name T192
Test name
Test status
Simulation time 37119581 ps
CPU time 0.88 seconds
Started Jul 21 06:25:17 PM PDT 24
Finished Jul 21 06:25:19 PM PDT 24
Peak memory 208732 kb
Host smart-962d4012-d0cb-479b-ac4e-c83b7fc28f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976699406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3976699406
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.4069237916
Short name T259
Test name
Test status
Simulation time 999128578 ps
CPU time 13.97 seconds
Started Jul 21 06:25:14 PM PDT 24
Finished Jul 21 06:25:28 PM PDT 24
Peak memory 218320 kb
Host smart-a64ab765-0b9b-450b-954b-61c146c90077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069237916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.4069237916
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.706367538
Short name T47
Test name
Test status
Simulation time 4361306445 ps
CPU time 28.58 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:25:45 PM PDT 24
Peak memory 218984 kb
Host smart-6786c33d-77ed-4413-a862-aa3b59d04f40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706367538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.706367538
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.122062412
Short name T864
Test name
Test status
Simulation time 2342003625 ps
CPU time 9.39 seconds
Started Jul 21 06:25:16 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 218384 kb
Host smart-a5f053ca-bea0-4011-948f-bc09d6c12af1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122062412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.122062412
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.510180975
Short name T867
Test name
Test status
Simulation time 345709719 ps
CPU time 5.71 seconds
Started Jul 21 06:25:17 PM PDT 24
Finished Jul 21 06:25:24 PM PDT 24
Peak memory 217596 kb
Host smart-81eb8079-396c-47bd-8510-ed8f7e791c92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510180975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
510180975
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.93953190
Short name T233
Test name
Test status
Simulation time 3296268285 ps
CPU time 59.18 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:26:16 PM PDT 24
Peak memory 267516 kb
Host smart-429b8554-509b-4a73-b6cf-23013f8f78ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93953190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_state_failure.93953190
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3283291427
Short name T568
Test name
Test status
Simulation time 472391296 ps
CPU time 14.36 seconds
Started Jul 21 06:25:17 PM PDT 24
Finished Jul 21 06:25:32 PM PDT 24
Peak memory 251088 kb
Host smart-f9fb9c9c-2748-4118-9805-56e678d80da7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283291427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3283291427
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2420267814
Short name T843
Test name
Test status
Simulation time 42604237 ps
CPU time 2.19 seconds
Started Jul 21 06:25:14 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 218436 kb
Host smart-8f1383a9-66d7-4e44-8ba4-a44e1aa3ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420267814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2420267814
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.638332074
Short name T384
Test name
Test status
Simulation time 507664934 ps
CPU time 8.81 seconds
Started Jul 21 06:25:17 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 226152 kb
Host smart-d0894abf-d38d-40cd-8b63-4651c3d1583c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638332074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.638332074
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3930781864
Short name T660
Test name
Test status
Simulation time 362470443 ps
CPU time 14.52 seconds
Started Jul 21 06:25:14 PM PDT 24
Finished Jul 21 06:25:29 PM PDT 24
Peak memory 226120 kb
Host smart-0fa5f9ea-4033-4bd7-a597-06591759f0a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930781864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3930781864
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2363741570
Short name T315
Test name
Test status
Simulation time 277198880 ps
CPU time 8.04 seconds
Started Jul 21 06:25:17 PM PDT 24
Finished Jul 21 06:25:26 PM PDT 24
Peak memory 218320 kb
Host smart-051f2f14-3068-4252-b2aa-f36e90747aaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363741570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2363741570
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2094431522
Short name T734
Test name
Test status
Simulation time 292239891 ps
CPU time 11.17 seconds
Started Jul 21 06:25:17 PM PDT 24
Finished Jul 21 06:25:29 PM PDT 24
Peak memory 226164 kb
Host smart-8172fcf9-2144-46cf-aaf9-b5d5cbc8b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094431522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2094431522
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2734540001
Short name T435
Test name
Test status
Simulation time 108509957 ps
CPU time 1.31 seconds
Started Jul 21 06:25:16 PM PDT 24
Finished Jul 21 06:25:18 PM PDT 24
Peak memory 213788 kb
Host smart-bd946536-753a-45d6-8160-f2562e06316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734540001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2734540001
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3403849490
Short name T523
Test name
Test status
Simulation time 328796940 ps
CPU time 29.9 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:25:46 PM PDT 24
Peak memory 246388 kb
Host smart-b18e6bd3-92fa-4dcc-befb-7f0a41f91f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403849490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3403849490
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3451375502
Short name T577
Test name
Test status
Simulation time 218084362 ps
CPU time 3.69 seconds
Started Jul 21 06:25:16 PM PDT 24
Finished Jul 21 06:25:20 PM PDT 24
Peak memory 226516 kb
Host smart-877bc03a-ab73-4602-948b-41f8577969e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451375502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3451375502
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3135351309
Short name T572
Test name
Test status
Simulation time 39321114 ps
CPU time 0.91 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 211964 kb
Host smart-774eb4b6-5e32-4c54-b2c8-39fdf9782cfd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135351309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3135351309
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.246161825
Short name T489
Test name
Test status
Simulation time 14890286 ps
CPU time 1.07 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:23 PM PDT 24
Peak memory 209068 kb
Host smart-632e672a-dd4c-4113-ba91-2c9c6571d325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246161825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.246161825
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1923235851
Short name T1
Test name
Test status
Simulation time 1442211629 ps
CPU time 15.86 seconds
Started Jul 21 06:25:17 PM PDT 24
Finished Jul 21 06:25:34 PM PDT 24
Peak memory 218368 kb
Host smart-18ce5420-6bda-49be-b36b-0a116b88b772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923235851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1923235851
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3615230007
Short name T846
Test name
Test status
Simulation time 6644337723 ps
CPU time 6.75 seconds
Started Jul 21 06:25:23 PM PDT 24
Finished Jul 21 06:25:30 PM PDT 24
Peak memory 217808 kb
Host smart-3981759e-174d-4e38-bf53-f4553461d85e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615230007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3615230007
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3664953566
Short name T89
Test name
Test status
Simulation time 2827397468 ps
CPU time 34.08 seconds
Started Jul 21 06:25:23 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 218504 kb
Host smart-1b0e2b34-5d53-46ad-aa82-04bb097db348
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664953566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3664953566
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2631246474
Short name T493
Test name
Test status
Simulation time 157728093 ps
CPU time 3.82 seconds
Started Jul 21 06:25:25 PM PDT 24
Finished Jul 21 06:25:29 PM PDT 24
Peak memory 218304 kb
Host smart-a33e76a8-c4a7-4d57-a3b2-5bb7b6ac9fea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631246474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2631246474
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1421372121
Short name T549
Test name
Test status
Simulation time 232214686 ps
CPU time 4.91 seconds
Started Jul 21 06:25:16 PM PDT 24
Finished Jul 21 06:25:22 PM PDT 24
Peak memory 217876 kb
Host smart-44b8d850-57ab-49b5-b5a7-3232d5135423
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421372121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1421372121
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3543295438
Short name T649
Test name
Test status
Simulation time 3469081784 ps
CPU time 47.87 seconds
Started Jul 21 06:25:15 PM PDT 24
Finished Jul 21 06:26:04 PM PDT 24
Peak memory 251132 kb
Host smart-d9bb1c43-4291-4148-807e-748d8beab639
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543295438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3543295438
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1468547437
Short name T852
Test name
Test status
Simulation time 329105476 ps
CPU time 2.26 seconds
Started Jul 21 06:25:16 PM PDT 24
Finished Jul 21 06:25:19 PM PDT 24
Peak memory 222432 kb
Host smart-eac2655b-1f19-4d17-a5d5-110c0cf9369c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468547437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1468547437
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.854883254
Short name T677
Test name
Test status
Simulation time 3066472599 ps
CPU time 21.26 seconds
Started Jul 21 06:25:21 PM PDT 24
Finished Jul 21 06:25:43 PM PDT 24
Peak memory 226260 kb
Host smart-23a009de-0596-48ab-8baf-2a46a98417a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854883254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.854883254
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1906687501
Short name T150
Test name
Test status
Simulation time 792026421 ps
CPU time 21 seconds
Started Jul 21 06:25:20 PM PDT 24
Finished Jul 21 06:25:42 PM PDT 24
Peak memory 226144 kb
Host smart-5f6b76dd-f746-4ac9-a0a5-eec60d4a5e0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906687501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1906687501
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.712764857
Short name T511
Test name
Test status
Simulation time 414892279 ps
CPU time 10.8 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:33 PM PDT 24
Peak memory 218340 kb
Host smart-614966d2-93f4-464b-ae96-3d51c206efd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712764857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.712764857
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1823762570
Short name T447
Test name
Test status
Simulation time 302684047 ps
CPU time 9.4 seconds
Started Jul 21 06:25:14 PM PDT 24
Finished Jul 21 06:25:24 PM PDT 24
Peak memory 226172 kb
Host smart-2217e75b-6b2a-4872-8ae8-ed00ee8e8de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823762570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1823762570
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2575811481
Short name T417
Test name
Test status
Simulation time 23258657 ps
CPU time 1.8 seconds
Started Jul 21 06:25:16 PM PDT 24
Finished Jul 21 06:25:19 PM PDT 24
Peak memory 214092 kb
Host smart-8505506a-38f3-4144-839a-658d6eeff962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575811481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2575811481
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2177301046
Short name T465
Test name
Test status
Simulation time 70774650 ps
CPU time 7.22 seconds
Started Jul 21 06:25:16 PM PDT 24
Finished Jul 21 06:25:24 PM PDT 24
Peak memory 251260 kb
Host smart-9f5d71e7-071a-4ec0-bdd1-e8a6af79e4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177301046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2177301046
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1444438728
Short name T157
Test name
Test status
Simulation time 230311640808 ps
CPU time 962.56 seconds
Started Jul 21 06:25:21 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 326080 kb
Host smart-ac451eef-a442-490a-a49c-3fa8154be457
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1444438728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.1444438728
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3586209145
Short name T742
Test name
Test status
Simulation time 19212919 ps
CPU time 1.02 seconds
Started Jul 21 06:25:21 PM PDT 24
Finished Jul 21 06:25:22 PM PDT 24
Peak memory 213060 kb
Host smart-3c387fda-44b4-4ea5-9c4d-5b5487c8376f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586209145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3586209145
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2546860083
Short name T376
Test name
Test status
Simulation time 43153482 ps
CPU time 1.02 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:24 PM PDT 24
Peak memory 209080 kb
Host smart-d404d82a-e6a3-4b84-aeb4-53c3362abcb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546860083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2546860083
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1692219142
Short name T706
Test name
Test status
Simulation time 1809582855 ps
CPU time 15.23 seconds
Started Jul 21 06:25:21 PM PDT 24
Finished Jul 21 06:25:37 PM PDT 24
Peak memory 218428 kb
Host smart-dd896dc2-4ecb-4534-afad-87a5c19c3bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692219142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1692219142
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4266374736
Short name T8
Test name
Test status
Simulation time 105520247 ps
CPU time 3.54 seconds
Started Jul 21 06:25:23 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 217264 kb
Host smart-a980cabc-127a-4963-a442-57c30352db76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266374736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4266374736
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1276579607
Short name T296
Test name
Test status
Simulation time 2302582548 ps
CPU time 21.95 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:45 PM PDT 24
Peak memory 218608 kb
Host smart-761dd749-e1f3-4330-8953-22c8d672835b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276579607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1276579607
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.223820981
Short name T194
Test name
Test status
Simulation time 184871144 ps
CPU time 6.13 seconds
Started Jul 21 06:25:21 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 218244 kb
Host smart-0a8fb83e-5222-408b-8acf-8631f2dd912d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223820981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.223820981
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.781943589
Short name T446
Test name
Test status
Simulation time 144832874 ps
CPU time 2.99 seconds
Started Jul 21 06:25:23 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 217724 kb
Host smart-8da86611-529d-4206-addf-df56f07014d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781943589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
781943589
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3013576118
Short name T498
Test name
Test status
Simulation time 6899615167 ps
CPU time 75.39 seconds
Started Jul 21 06:25:20 PM PDT 24
Finished Jul 21 06:26:36 PM PDT 24
Peak memory 267604 kb
Host smart-fdaf8f2d-8ad0-4556-b306-df45e11e77c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013576118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3013576118
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.429920017
Short name T805
Test name
Test status
Simulation time 1258240965 ps
CPU time 21.1 seconds
Started Jul 21 06:25:21 PM PDT 24
Finished Jul 21 06:25:43 PM PDT 24
Peak memory 246168 kb
Host smart-fa9980ad-d7fc-4173-8626-299d3174c935
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429920017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.429920017
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.970313647
Short name T499
Test name
Test status
Simulation time 44682435 ps
CPU time 1.8 seconds
Started Jul 21 06:25:23 PM PDT 24
Finished Jul 21 06:25:25 PM PDT 24
Peak memory 222156 kb
Host smart-75642ecc-eb22-4185-b900-803b8d6cd40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970313647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.970313647
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1906816520
Short name T269
Test name
Test status
Simulation time 710439356 ps
CPU time 9.31 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:32 PM PDT 24
Peak memory 218312 kb
Host smart-7258781d-461e-4eef-b65a-9ac9bcbbf073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906816520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1906816520
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3057164303
Short name T737
Test name
Test status
Simulation time 639511477 ps
CPU time 14.75 seconds
Started Jul 21 06:25:25 PM PDT 24
Finished Jul 21 06:25:40 PM PDT 24
Peak memory 226104 kb
Host smart-bb565bd4-5c3c-4756-a561-4e61bd3ef264
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057164303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3057164303
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.303633101
Short name T340
Test name
Test status
Simulation time 794030132 ps
CPU time 14.01 seconds
Started Jul 21 06:25:23 PM PDT 24
Finished Jul 21 06:25:37 PM PDT 24
Peak memory 226100 kb
Host smart-9858b4f9-d775-44fd-830a-3da3118785ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303633101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.303633101
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1721361100
Short name T836
Test name
Test status
Simulation time 256133045 ps
CPU time 7.8 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:30 PM PDT 24
Peak memory 226080 kb
Host smart-6d51aa23-30af-4e7f-ae55-cc1f7e26fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721361100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1721361100
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3754954091
Short name T360
Test name
Test status
Simulation time 32575406 ps
CPU time 2.2 seconds
Started Jul 21 06:25:23 PM PDT 24
Finished Jul 21 06:25:26 PM PDT 24
Peak memory 214180 kb
Host smart-e5734ec9-6074-4fb0-b98b-f66285fb01f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754954091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3754954091
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1821727007
Short name T751
Test name
Test status
Simulation time 365274863 ps
CPU time 27.79 seconds
Started Jul 21 06:25:21 PM PDT 24
Finished Jul 21 06:25:49 PM PDT 24
Peak memory 251220 kb
Host smart-2b0de889-3d56-4a81-bab0-a3cd19b0226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821727007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1821727007
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2315900037
Short name T397
Test name
Test status
Simulation time 59064161 ps
CPU time 6.95 seconds
Started Jul 21 06:25:25 PM PDT 24
Finished Jul 21 06:25:33 PM PDT 24
Peak memory 242940 kb
Host smart-cf06b072-37f4-49a0-a3db-99855eb98e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315900037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2315900037
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.940584841
Short name T827
Test name
Test status
Simulation time 18613410987 ps
CPU time 161.02 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:28:04 PM PDT 24
Peak memory 284028 kb
Host smart-2b724e22-d1d6-42b3-9e1f-bf0698506448
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940584841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.940584841
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2209931770
Short name T96
Test name
Test status
Simulation time 27248887 ps
CPU time 0.94 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:23 PM PDT 24
Peak memory 211976 kb
Host smart-429d8c0f-7b2e-4a10-966e-d4577a7e16ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209931770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2209931770
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2354573189
Short name T361
Test name
Test status
Simulation time 40043006 ps
CPU time 1 seconds
Started Jul 21 06:25:25 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 208936 kb
Host smart-89020682-f801-4fac-9dbd-993c3f09dae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354573189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2354573189
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.975377777
Short name T729
Test name
Test status
Simulation time 1049371185 ps
CPU time 10.94 seconds
Started Jul 21 06:25:27 PM PDT 24
Finished Jul 21 06:25:38 PM PDT 24
Peak memory 226228 kb
Host smart-263af0c2-9cc1-4a97-9b23-c8e78fae99ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975377777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.975377777
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1798625134
Short name T407
Test name
Test status
Simulation time 195738295 ps
CPU time 5.88 seconds
Started Jul 21 06:25:24 PM PDT 24
Finished Jul 21 06:25:30 PM PDT 24
Peak memory 217536 kb
Host smart-0a8ee8e1-759c-4c34-831a-d4fc1a7f5ef9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798625134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1798625134
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1707332336
Short name T630
Test name
Test status
Simulation time 3240714036 ps
CPU time 48.72 seconds
Started Jul 21 06:25:26 PM PDT 24
Finished Jul 21 06:26:15 PM PDT 24
Peak memory 218968 kb
Host smart-d3e75023-f182-4bff-9033-5ca668f00c86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707332336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1707332336
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.4237293557
Short name T27
Test name
Test status
Simulation time 1196871228 ps
CPU time 5.41 seconds
Started Jul 21 06:25:27 PM PDT 24
Finished Jul 21 06:25:33 PM PDT 24
Peak memory 218304 kb
Host smart-42f7af44-112e-4ef0-bf7e-3ac57b3d0961
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237293557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.4237293557
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2784129948
Short name T860
Test name
Test status
Simulation time 1871870065 ps
CPU time 4.39 seconds
Started Jul 21 06:25:25 PM PDT 24
Finished Jul 21 06:25:29 PM PDT 24
Peak memory 217728 kb
Host smart-1f181ca7-65c3-466d-9be6-eed8bb817ed7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784129948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2784129948
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.697391198
Short name T606
Test name
Test status
Simulation time 10987540256 ps
CPU time 89.15 seconds
Started Jul 21 06:25:29 PM PDT 24
Finished Jul 21 06:26:59 PM PDT 24
Peak memory 283664 kb
Host smart-5f81a37e-6fa5-499d-beb4-94e553c04c8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697391198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.697391198
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1534879884
Short name T185
Test name
Test status
Simulation time 3013512365 ps
CPU time 15.03 seconds
Started Jul 21 06:25:26 PM PDT 24
Finished Jul 21 06:25:42 PM PDT 24
Peak memory 224492 kb
Host smart-ea7306b4-30db-461f-9bb8-d9936d24fa31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534879884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1534879884
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2895184316
Short name T370
Test name
Test status
Simulation time 309167739 ps
CPU time 3.12 seconds
Started Jul 21 06:25:26 PM PDT 24
Finished Jul 21 06:25:29 PM PDT 24
Peak memory 218316 kb
Host smart-46b06ef1-4be9-49f6-a997-6ac8d7eb1388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895184316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2895184316
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2983142667
Short name T719
Test name
Test status
Simulation time 781576871 ps
CPU time 9.48 seconds
Started Jul 21 06:25:26 PM PDT 24
Finished Jul 21 06:25:36 PM PDT 24
Peak memory 226204 kb
Host smart-e84ae04a-c00e-4324-bb3a-1f5b67dd9641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983142667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2983142667
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3594181171
Short name T673
Test name
Test status
Simulation time 1678043717 ps
CPU time 9.95 seconds
Started Jul 21 06:25:27 PM PDT 24
Finished Jul 21 06:25:37 PM PDT 24
Peak memory 226144 kb
Host smart-5b03f9c9-845c-4b6c-b035-42aca8c9aca3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594181171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3594181171
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1245435075
Short name T756
Test name
Test status
Simulation time 1643699014 ps
CPU time 24.4 seconds
Started Jul 21 06:25:25 PM PDT 24
Finished Jul 21 06:25:50 PM PDT 24
Peak memory 226040 kb
Host smart-7afae739-b4cb-49fc-a504-a5573d37d6ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245435075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1245435075
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3842546534
Short name T841
Test name
Test status
Simulation time 618787437 ps
CPU time 9.44 seconds
Started Jul 21 06:25:27 PM PDT 24
Finished Jul 21 06:25:37 PM PDT 24
Peak memory 226180 kb
Host smart-147f44b4-771d-46ed-a6b0-a548feff7520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842546534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3842546534
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2779382493
Short name T713
Test name
Test status
Simulation time 54265648 ps
CPU time 2.05 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:25 PM PDT 24
Peak memory 217792 kb
Host smart-f4090410-d247-458d-b0a6-952d1b39c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779382493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2779382493
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.174264136
Short name T153
Test name
Test status
Simulation time 2670444619 ps
CPU time 21.87 seconds
Started Jul 21 06:25:21 PM PDT 24
Finished Jul 21 06:25:44 PM PDT 24
Peak memory 251156 kb
Host smart-7f739d37-ae8c-463b-8980-9712aff3aef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174264136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.174264136
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1589730364
Short name T862
Test name
Test status
Simulation time 756571949 ps
CPU time 3.65 seconds
Started Jul 21 06:25:26 PM PDT 24
Finished Jul 21 06:25:30 PM PDT 24
Peak memory 222780 kb
Host smart-a1ece135-e52c-47cf-a913-ecb731a10f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589730364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1589730364
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.633848986
Short name T403
Test name
Test status
Simulation time 21045397586 ps
CPU time 636.82 seconds
Started Jul 21 06:25:28 PM PDT 24
Finished Jul 21 06:36:05 PM PDT 24
Peak memory 259432 kb
Host smart-484c1177-8c17-45ff-ab28-a22773d2b69c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633848986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.633848986
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1298336249
Short name T245
Test name
Test status
Simulation time 14191475 ps
CPU time 0.91 seconds
Started Jul 21 06:25:22 PM PDT 24
Finished Jul 21 06:25:24 PM PDT 24
Peak memory 211976 kb
Host smart-da53b64a-6f4e-4ceb-9088-42a311d45305
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298336249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1298336249
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2458765481
Short name T350
Test name
Test status
Simulation time 142000774 ps
CPU time 1.06 seconds
Started Jul 21 06:25:33 PM PDT 24
Finished Jul 21 06:25:35 PM PDT 24
Peak memory 208932 kb
Host smart-490c709b-e56d-496e-b0ee-0e2f4a8829f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458765481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2458765481
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3596931600
Short name T415
Test name
Test status
Simulation time 699676873 ps
CPU time 11.53 seconds
Started Jul 21 06:25:35 PM PDT 24
Finished Jul 21 06:25:47 PM PDT 24
Peak memory 218400 kb
Host smart-2e61e9ad-5b39-4382-a577-09f4e99f71db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596931600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3596931600
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1323647700
Short name T379
Test name
Test status
Simulation time 538808707 ps
CPU time 2.9 seconds
Started Jul 21 06:25:33 PM PDT 24
Finished Jul 21 06:25:37 PM PDT 24
Peak memory 217252 kb
Host smart-8aa93ae1-85e6-4db2-a202-1b9d329aeb0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323647700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1323647700
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1957781025
Short name T661
Test name
Test status
Simulation time 1735821231 ps
CPU time 31.04 seconds
Started Jul 21 06:25:33 PM PDT 24
Finished Jul 21 06:26:04 PM PDT 24
Peak memory 218368 kb
Host smart-d1e3b8be-ab01-46ee-8015-b47481c401b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957781025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1957781025
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.404858610
Short name T579
Test name
Test status
Simulation time 5004227873 ps
CPU time 12.58 seconds
Started Jul 21 06:25:37 PM PDT 24
Finished Jul 21 06:25:50 PM PDT 24
Peak memory 226152 kb
Host smart-67f754c8-c171-42ea-bb0b-6559526088f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404858610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.404858610
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2829610711
Short name T63
Test name
Test status
Simulation time 318295878 ps
CPU time 3.19 seconds
Started Jul 21 06:25:34 PM PDT 24
Finished Jul 21 06:25:38 PM PDT 24
Peak memory 217748 kb
Host smart-3a66521d-dbc4-40ad-b9e8-e098d2366258
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829610711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2829610711
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.741981432
Short name T615
Test name
Test status
Simulation time 37041796729 ps
CPU time 92.88 seconds
Started Jul 21 06:25:34 PM PDT 24
Finished Jul 21 06:27:08 PM PDT 24
Peak memory 283796 kb
Host smart-7c33d52b-ce4c-48f5-8558-54f5c2df473f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741981432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.741981432
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.500934576
Short name T508
Test name
Test status
Simulation time 1970901197 ps
CPU time 17.9 seconds
Started Jul 21 06:25:35 PM PDT 24
Finished Jul 21 06:25:53 PM PDT 24
Peak memory 247720 kb
Host smart-692742c8-0b91-47f0-b55f-150813cf225f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500934576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.500934576
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1916651911
Short name T98
Test name
Test status
Simulation time 26008459 ps
CPU time 2.08 seconds
Started Jul 21 06:25:36 PM PDT 24
Finished Jul 21 06:25:38 PM PDT 24
Peak memory 222020 kb
Host smart-d74eebef-87b7-40f5-ad2d-7c58b4433530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916651911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1916651911
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2634926704
Short name T45
Test name
Test status
Simulation time 399482750 ps
CPU time 16.17 seconds
Started Jul 21 06:25:32 PM PDT 24
Finished Jul 21 06:25:48 PM PDT 24
Peak memory 225956 kb
Host smart-3fe1509e-f483-4c05-92d2-bf018bd5b422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634926704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2634926704
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1738934907
Short name T635
Test name
Test status
Simulation time 454896252 ps
CPU time 10.84 seconds
Started Jul 21 06:25:33 PM PDT 24
Finished Jul 21 06:25:45 PM PDT 24
Peak memory 226092 kb
Host smart-ae88e35b-77c6-4b0e-a3e0-ac1e6f690f03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738934907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1738934907
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2739668392
Short name T692
Test name
Test status
Simulation time 206742887 ps
CPU time 6.24 seconds
Started Jul 21 06:25:32 PM PDT 24
Finished Jul 21 06:25:39 PM PDT 24
Peak memory 218320 kb
Host smart-17e48c03-4ab1-4e37-8f52-9a4fade0adf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739668392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2739668392
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3294589043
Short name T782
Test name
Test status
Simulation time 122672583 ps
CPU time 1.12 seconds
Started Jul 21 06:25:30 PM PDT 24
Finished Jul 21 06:25:31 PM PDT 24
Peak memory 212124 kb
Host smart-37dc0bdc-0a1f-40b0-bb19-81efefb15854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294589043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3294589043
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1793065089
Short name T736
Test name
Test status
Simulation time 1270159033 ps
CPU time 32.85 seconds
Started Jul 21 06:25:30 PM PDT 24
Finished Jul 21 06:26:03 PM PDT 24
Peak memory 251132 kb
Host smart-b34243c0-817e-4893-acd1-a8c03e158116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793065089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1793065089
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3572003822
Short name T667
Test name
Test status
Simulation time 416561560 ps
CPU time 8.48 seconds
Started Jul 21 06:25:25 PM PDT 24
Finished Jul 21 06:25:34 PM PDT 24
Peak memory 250668 kb
Host smart-c07272f8-5fc3-420f-b16e-6ff5dca3de74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572003822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3572003822
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1244529379
Short name T509
Test name
Test status
Simulation time 1131388996 ps
CPU time 18.56 seconds
Started Jul 21 06:25:34 PM PDT 24
Finished Jul 21 06:25:53 PM PDT 24
Peak memory 226492 kb
Host smart-b34f85a1-52fa-4523-9ebb-a571ee1a25dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244529379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1244529379
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.946251392
Short name T757
Test name
Test status
Simulation time 13624540 ps
CPU time 0.92 seconds
Started Jul 21 06:25:27 PM PDT 24
Finished Jul 21 06:25:29 PM PDT 24
Peak memory 211916 kb
Host smart-616a1faa-7493-404e-85d4-2ff0ff4b3e21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946251392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.946251392
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2171759597
Short name T248
Test name
Test status
Simulation time 22567874 ps
CPU time 0.93 seconds
Started Jul 21 06:25:42 PM PDT 24
Finished Jul 21 06:25:43 PM PDT 24
Peak memory 208948 kb
Host smart-ef7d2a1a-9826-4de0-ae99-d8d2e24d4981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171759597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2171759597
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3150106435
Short name T583
Test name
Test status
Simulation time 781143842 ps
CPU time 9.75 seconds
Started Jul 21 06:25:40 PM PDT 24
Finished Jul 21 06:25:51 PM PDT 24
Peak memory 218372 kb
Host smart-7e183998-64c5-42c9-9a43-6a9670abd656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150106435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3150106435
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.4053710665
Short name T865
Test name
Test status
Simulation time 523682874 ps
CPU time 3.65 seconds
Started Jul 21 06:25:39 PM PDT 24
Finished Jul 21 06:25:43 PM PDT 24
Peak memory 217328 kb
Host smart-6ffd77ec-b961-412a-8fc9-f2c8c2608742
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053710665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.4053710665
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3950714958
Short name T297
Test name
Test status
Simulation time 5923833826 ps
CPU time 31.13 seconds
Started Jul 21 06:25:41 PM PDT 24
Finished Jul 21 06:26:13 PM PDT 24
Peak memory 219052 kb
Host smart-c0098b37-b527-4245-9b62-7cecb31afbc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950714958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3950714958
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1350385501
Short name T631
Test name
Test status
Simulation time 53763053 ps
CPU time 2.02 seconds
Started Jul 21 06:25:40 PM PDT 24
Finished Jul 21 06:25:43 PM PDT 24
Peak memory 218304 kb
Host smart-a97955a8-72ee-4525-8b82-f4cc317c889f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350385501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1350385501
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.881300991
Short name T664
Test name
Test status
Simulation time 186663661 ps
CPU time 2.24 seconds
Started Jul 21 06:25:40 PM PDT 24
Finished Jul 21 06:25:43 PM PDT 24
Peak memory 217712 kb
Host smart-79f217a1-29bb-47ca-a929-8634cbabb759
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881300991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
881300991
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3511609524
Short name T735
Test name
Test status
Simulation time 1743283364 ps
CPU time 71.73 seconds
Started Jul 21 06:25:39 PM PDT 24
Finished Jul 21 06:26:51 PM PDT 24
Peak memory 267432 kb
Host smart-63d66022-1477-4fdb-ac61-a1ef1367819b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511609524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3511609524
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3949707329
Short name T412
Test name
Test status
Simulation time 2275270845 ps
CPU time 12.67 seconds
Started Jul 21 06:25:40 PM PDT 24
Finished Jul 21 06:25:53 PM PDT 24
Peak memory 246308 kb
Host smart-3bd167de-9715-4f30-802c-d5569ca0596f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949707329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3949707329
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.67746168
Short name T545
Test name
Test status
Simulation time 97946494 ps
CPU time 3.42 seconds
Started Jul 21 06:25:41 PM PDT 24
Finished Jul 21 06:25:45 PM PDT 24
Peak memory 218368 kb
Host smart-12cfc313-828e-4d73-af8f-02fd7fa70743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67746168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.67746168
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3264984190
Short name T738
Test name
Test status
Simulation time 7745844836 ps
CPU time 14.39 seconds
Started Jul 21 06:25:43 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 219688 kb
Host smart-6e10276b-202b-478d-821c-0d877b85bc22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264984190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3264984190
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.151024453
Short name T443
Test name
Test status
Simulation time 290726444 ps
CPU time 8.36 seconds
Started Jul 21 06:25:41 PM PDT 24
Finished Jul 21 06:25:50 PM PDT 24
Peak memory 226124 kb
Host smart-5643c414-c15b-4570-b9d3-c07bad59297d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151024453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.151024453
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.627583120
Short name T783
Test name
Test status
Simulation time 2033194559 ps
CPU time 10.8 seconds
Started Jul 21 06:25:41 PM PDT 24
Finished Jul 21 06:25:52 PM PDT 24
Peak memory 218520 kb
Host smart-ffad4e5b-8a27-4059-b5e7-64b2781ad387
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627583120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.627583120
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3681152876
Short name T585
Test name
Test status
Simulation time 624635978 ps
CPU time 8.46 seconds
Started Jul 21 06:25:41 PM PDT 24
Finished Jul 21 06:25:50 PM PDT 24
Peak memory 226184 kb
Host smart-1ddca5b5-1798-44d4-9e54-f0f07f3dca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681152876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3681152876
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2284197086
Short name T371
Test name
Test status
Simulation time 69630854 ps
CPU time 1.14 seconds
Started Jul 21 06:25:35 PM PDT 24
Finished Jul 21 06:25:36 PM PDT 24
Peak memory 217788 kb
Host smart-7ec38656-8a76-4321-8372-1f7124ffa45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284197086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2284197086
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2734732941
Short name T775
Test name
Test status
Simulation time 475397679 ps
CPU time 26.62 seconds
Started Jul 21 06:25:37 PM PDT 24
Finished Jul 21 06:26:04 PM PDT 24
Peak memory 245820 kb
Host smart-17054671-121e-4444-afbe-046be6d1ec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734732941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2734732941
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3968165798
Short name T454
Test name
Test status
Simulation time 72996009 ps
CPU time 7.63 seconds
Started Jul 21 06:25:39 PM PDT 24
Finished Jul 21 06:25:47 PM PDT 24
Peak memory 250560 kb
Host smart-4819e1a5-0650-453b-8851-3bd90e0d0f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968165798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3968165798
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2679797924
Short name T166
Test name
Test status
Simulation time 6024207947 ps
CPU time 143.62 seconds
Started Jul 21 06:25:39 PM PDT 24
Finished Jul 21 06:28:03 PM PDT 24
Peak memory 267552 kb
Host smart-f9bfe746-f848-406f-b954-f4f05ae5192c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679797924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2679797924
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1013415043
Short name T239
Test name
Test status
Simulation time 14037007 ps
CPU time 0.76 seconds
Started Jul 21 06:25:34 PM PDT 24
Finished Jul 21 06:25:35 PM PDT 24
Peak memory 208116 kb
Host smart-d543cfb0-47a2-41a8-84b6-10aeb1166ade
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013415043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1013415043
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2187390037
Short name T832
Test name
Test status
Simulation time 26153812 ps
CPU time 1.18 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:25:49 PM PDT 24
Peak memory 209016 kb
Host smart-3aa25341-36f2-4d59-8994-9bc04f6c3463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187390037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2187390037
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3698306026
Short name T510
Test name
Test status
Simulation time 1927986777 ps
CPU time 17.7 seconds
Started Jul 21 06:25:40 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 218472 kb
Host smart-759f45e2-26c5-4dcb-9898-81b73e7d449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698306026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3698306026
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2878352013
Short name T821
Test name
Test status
Simulation time 272052770 ps
CPU time 3.71 seconds
Started Jul 21 06:25:46 PM PDT 24
Finished Jul 21 06:25:50 PM PDT 24
Peak memory 217204 kb
Host smart-2be1412e-ddd2-4ba3-b87a-7f3c0fa71fb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878352013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2878352013
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3493836233
Short name T526
Test name
Test status
Simulation time 15779383559 ps
CPU time 47.45 seconds
Started Jul 21 06:25:48 PM PDT 24
Finished Jul 21 06:26:36 PM PDT 24
Peak memory 219892 kb
Host smart-3b621743-c462-441a-aa99-4e0d367692b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493836233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3493836233
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1907035268
Short name T824
Test name
Test status
Simulation time 1097203236 ps
CPU time 8.91 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:25:57 PM PDT 24
Peak memory 218328 kb
Host smart-80b6e0ff-ac83-4879-a536-0c750e181c75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907035268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1907035268
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.339652974
Short name T506
Test name
Test status
Simulation time 1739124616 ps
CPU time 7.4 seconds
Started Jul 21 06:25:42 PM PDT 24
Finished Jul 21 06:25:50 PM PDT 24
Peak memory 217736 kb
Host smart-66c4263a-9954-4755-bfb5-fd40615930e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339652974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
339652974
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2993365845
Short name T831
Test name
Test status
Simulation time 4015034566 ps
CPU time 39.1 seconds
Started Jul 21 06:25:38 PM PDT 24
Finished Jul 21 06:26:18 PM PDT 24
Peak memory 251084 kb
Host smart-d91b245d-aea6-4285-bd6f-314d281732cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993365845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2993365845
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3506707620
Short name T477
Test name
Test status
Simulation time 743252209 ps
CPU time 10.28 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 246224 kb
Host smart-f8828974-84a6-499e-b270-3f5068469d83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506707620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3506707620
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1029544819
Short name T449
Test name
Test status
Simulation time 64591008 ps
CPU time 2.77 seconds
Started Jul 21 06:25:40 PM PDT 24
Finished Jul 21 06:25:43 PM PDT 24
Peak memory 218380 kb
Host smart-edd93aff-6e76-4fb1-9c4b-bf7b579d83f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029544819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1029544819
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2581669677
Short name T567
Test name
Test status
Simulation time 557968238 ps
CPU time 17.91 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:26:05 PM PDT 24
Peak memory 226176 kb
Host smart-877bb704-5975-4656-8722-3891191e44c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581669677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2581669677
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1280786372
Short name T184
Test name
Test status
Simulation time 742120419 ps
CPU time 8.69 seconds
Started Jul 21 06:25:49 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 226108 kb
Host smart-c0a3809d-8756-490f-9606-a4302eef550e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280786372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1280786372
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2487955105
Short name T429
Test name
Test status
Simulation time 225613510 ps
CPU time 9.55 seconds
Started Jul 21 06:25:46 PM PDT 24
Finished Jul 21 06:25:56 PM PDT 24
Peak memory 226120 kb
Host smart-d3ca9005-8691-44fe-b629-75378466f8a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487955105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2487955105
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2111431898
Short name T359
Test name
Test status
Simulation time 924993064 ps
CPU time 7.68 seconds
Started Jul 21 06:25:39 PM PDT 24
Finished Jul 21 06:25:47 PM PDT 24
Peak memory 225144 kb
Host smart-923633c2-863d-4a6d-b37a-41e1142e7b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111431898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2111431898
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2180895656
Short name T343
Test name
Test status
Simulation time 183219036 ps
CPU time 3.35 seconds
Started Jul 21 06:25:38 PM PDT 24
Finished Jul 21 06:25:42 PM PDT 24
Peak memory 217804 kb
Host smart-8453ee55-fc77-4133-9b46-1eb4e9877120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180895656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2180895656
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3768065861
Short name T521
Test name
Test status
Simulation time 195650909 ps
CPU time 17.24 seconds
Started Jul 21 06:25:41 PM PDT 24
Finished Jul 21 06:25:59 PM PDT 24
Peak memory 251124 kb
Host smart-6de7e04e-22c6-4db1-83ad-28b57b35bbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768065861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3768065861
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1055057114
Short name T609
Test name
Test status
Simulation time 65856073 ps
CPU time 7.81 seconds
Started Jul 21 06:25:39 PM PDT 24
Finished Jul 21 06:25:47 PM PDT 24
Peak memory 251056 kb
Host smart-afa81117-a1eb-4956-980c-94d3e7715919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055057114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1055057114
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.706713708
Short name T672
Test name
Test status
Simulation time 25539527283 ps
CPU time 225.98 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:29:39 PM PDT 24
Peak memory 300316 kb
Host smart-3971ac48-7cb3-4f29-9c6d-c2ee251d9aa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706713708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.706713708
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1466240557
Short name T102
Test name
Test status
Simulation time 134774895013 ps
CPU time 2584.75 seconds
Started Jul 21 06:25:48 PM PDT 24
Finished Jul 21 07:08:54 PM PDT 24
Peak memory 758636 kb
Host smart-f8d1bd91-6539-4457-b78e-6afd80523168
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1466240557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1466240557
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2306080980
Short name T450
Test name
Test status
Simulation time 38265522 ps
CPU time 0.82 seconds
Started Jul 21 06:25:41 PM PDT 24
Finished Jul 21 06:25:43 PM PDT 24
Peak memory 211856 kb
Host smart-5fe0b813-d050-4323-bd13-39ac90234752
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306080980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2306080980
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3531400245
Short name T161
Test name
Test status
Simulation time 15157361 ps
CPU time 1.1 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:25:52 PM PDT 24
Peak memory 208952 kb
Host smart-22ce8f94-6643-49f5-973b-7352e7730001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531400245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3531400245
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1313459428
Short name T386
Test name
Test status
Simulation time 1151810708 ps
CPU time 13.61 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:26:01 PM PDT 24
Peak memory 218360 kb
Host smart-714264c6-c643-481a-b3bb-18341fc0759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313459428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1313459428
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.726822233
Short name T36
Test name
Test status
Simulation time 300930446 ps
CPU time 8.14 seconds
Started Jul 21 06:25:46 PM PDT 24
Finished Jul 21 06:25:55 PM PDT 24
Peak memory 217412 kb
Host smart-4acf43e8-b35e-4a45-bc93-d48d2fd91bdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726822233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.726822233
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3717470580
Short name T809
Test name
Test status
Simulation time 1278063327 ps
CPU time 24.26 seconds
Started Jul 21 06:25:48 PM PDT 24
Finished Jul 21 06:26:13 PM PDT 24
Peak memory 218884 kb
Host smart-b27e8ea4-6211-442f-a3c3-0f0c9359c0af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717470580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3717470580
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4187966226
Short name T28
Test name
Test status
Simulation time 597321780 ps
CPU time 17.44 seconds
Started Jul 21 06:25:48 PM PDT 24
Finished Jul 21 06:26:06 PM PDT 24
Peak memory 218284 kb
Host smart-efb68cf1-042c-4966-88e4-b83ef88f2b83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187966226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.4187966226
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.589256411
Short name T332
Test name
Test status
Simulation time 226337562 ps
CPU time 1.91 seconds
Started Jul 21 06:25:48 PM PDT 24
Finished Jul 21 06:25:51 PM PDT 24
Peak memory 217748 kb
Host smart-662f6c6c-fa81-42b3-9fd7-b1082475c295
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589256411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
589256411
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.173400143
Short name T586
Test name
Test status
Simulation time 6686780619 ps
CPU time 47.37 seconds
Started Jul 21 06:25:46 PM PDT 24
Finished Jul 21 06:26:34 PM PDT 24
Peak memory 251500 kb
Host smart-7b73d5fd-4101-4b5a-980f-6fb3acf74633
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173400143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.173400143
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2659215395
Short name T5
Test name
Test status
Simulation time 1395048996 ps
CPU time 7.7 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:26:01 PM PDT 24
Peak memory 223280 kb
Host smart-76ceed80-9231-46b6-bee4-141b802c0e3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659215395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2659215395
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2513518023
Short name T698
Test name
Test status
Simulation time 226624117 ps
CPU time 2.76 seconds
Started Jul 21 06:25:45 PM PDT 24
Finished Jul 21 06:25:49 PM PDT 24
Peak memory 218296 kb
Host smart-ea0320aa-c371-4274-bfa7-bfe041d2e3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513518023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2513518023
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.911362225
Short name T810
Test name
Test status
Simulation time 3405944079 ps
CPU time 11.46 seconds
Started Jul 21 06:25:48 PM PDT 24
Finished Jul 21 06:26:00 PM PDT 24
Peak memory 220452 kb
Host smart-d611a397-7ea1-4b63-acb8-f95945425ad8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911362225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.911362225
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1795662839
Short name T685
Test name
Test status
Simulation time 524074122 ps
CPU time 11.12 seconds
Started Jul 21 06:25:45 PM PDT 24
Finished Jul 21 06:25:57 PM PDT 24
Peak memory 226028 kb
Host smart-419c2c70-f988-4b27-ac7a-efe597271e9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795662839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1795662839
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.76412404
Short name T445
Test name
Test status
Simulation time 297610238 ps
CPU time 6.86 seconds
Started Jul 21 06:25:49 PM PDT 24
Finished Jul 21 06:25:56 PM PDT 24
Peak memory 226112 kb
Host smart-0cc39807-fe74-48f4-9cbb-e2d49a498952
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76412404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.76412404
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.101757374
Short name T608
Test name
Test status
Simulation time 258844241 ps
CPU time 11.12 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:25:59 PM PDT 24
Peak memory 226116 kb
Host smart-6d083f9f-fa99-486e-a635-24dd0cfdb744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101757374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.101757374
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3557877181
Short name T80
Test name
Test status
Simulation time 134857012 ps
CPU time 3.32 seconds
Started Jul 21 06:25:44 PM PDT 24
Finished Jul 21 06:25:47 PM PDT 24
Peak memory 223352 kb
Host smart-a633d776-422a-4fc8-9a44-aee39dc29a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557877181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3557877181
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.204202921
Short name T179
Test name
Test status
Simulation time 756055738 ps
CPU time 22.99 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:26:11 PM PDT 24
Peak memory 246060 kb
Host smart-988fd46a-bf10-4919-a24a-d72bfbd376d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204202921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.204202921
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1599492688
Short name T313
Test name
Test status
Simulation time 79289151 ps
CPU time 7.41 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:25:59 PM PDT 24
Peak memory 251060 kb
Host smart-319fdc48-4efb-4458-b7b4-b66ec82c6cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599492688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1599492688
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2980090564
Short name T851
Test name
Test status
Simulation time 3449056409 ps
CPU time 63.72 seconds
Started Jul 21 06:25:53 PM PDT 24
Finished Jul 21 06:26:58 PM PDT 24
Peak memory 251016 kb
Host smart-c1df3878-a276-47b5-8088-5427597f4cce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980090564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2980090564
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2492167030
Short name T752
Test name
Test status
Simulation time 67815221 ps
CPU time 0.87 seconds
Started Jul 21 06:25:50 PM PDT 24
Finished Jul 21 06:25:51 PM PDT 24
Peak memory 211872 kb
Host smart-cd886249-6530-4483-bc47-745a37c3ec11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492167030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2492167030
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3420795899
Short name T333
Test name
Test status
Simulation time 22410473 ps
CPU time 0.89 seconds
Started Jul 21 06:25:50 PM PDT 24
Finished Jul 21 06:25:52 PM PDT 24
Peak memory 208960 kb
Host smart-49e5d855-0d13-4e39-b153-c4a21fa516e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420795899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3420795899
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1835958528
Short name T604
Test name
Test status
Simulation time 3604777846 ps
CPU time 14.15 seconds
Started Jul 21 06:25:49 PM PDT 24
Finished Jul 21 06:26:04 PM PDT 24
Peak memory 226236 kb
Host smart-9938a6b6-5df2-4e74-a842-3981de9d2424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835958528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1835958528
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2820446489
Short name T198
Test name
Test status
Simulation time 595837172 ps
CPU time 4.48 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 217220 kb
Host smart-d870c193-3ed0-487d-ba7d-1851aba452a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820446489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2820446489
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.103105470
Short name T797
Test name
Test status
Simulation time 6288885756 ps
CPU time 39.01 seconds
Started Jul 21 06:25:48 PM PDT 24
Finished Jul 21 06:26:28 PM PDT 24
Peak memory 218692 kb
Host smart-47b96bcd-4dc0-47eb-ad51-9cf64dd379c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103105470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.103105470
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1628728084
Short name T318
Test name
Test status
Simulation time 397401428 ps
CPU time 11.44 seconds
Started Jul 21 06:25:46 PM PDT 24
Finished Jul 21 06:25:57 PM PDT 24
Peak memory 218300 kb
Host smart-ae32dc64-ee8c-4034-ac61-cd30b4cd26d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628728084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1628728084
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2167730043
Short name T341
Test name
Test status
Simulation time 616355012 ps
CPU time 2.4 seconds
Started Jul 21 06:25:53 PM PDT 24
Finished Jul 21 06:25:57 PM PDT 24
Peak memory 217700 kb
Host smart-6b91a6aa-163d-42c1-9ef8-01891d7a5973
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167730043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2167730043
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1488218213
Short name T546
Test name
Test status
Simulation time 1069471792 ps
CPU time 29.38 seconds
Started Jul 21 06:25:45 PM PDT 24
Finished Jul 21 06:26:15 PM PDT 24
Peak memory 276068 kb
Host smart-c7123637-664a-4b30-9b27-007f142b5162
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488218213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1488218213
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1535951831
Short name T308
Test name
Test status
Simulation time 4161132567 ps
CPU time 24.45 seconds
Started Jul 21 06:25:45 PM PDT 24
Finished Jul 21 06:26:10 PM PDT 24
Peak memory 223868 kb
Host smart-60648512-15bb-4aaf-8de2-1e85bd6be2cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535951831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1535951831
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.195441841
Short name T470
Test name
Test status
Simulation time 238956731 ps
CPU time 3.35 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:25:51 PM PDT 24
Peak memory 218320 kb
Host smart-af9a87ca-5345-46b3-8368-7c44678a6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195441841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.195441841
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3551891577
Short name T704
Test name
Test status
Simulation time 1161189180 ps
CPU time 11.05 seconds
Started Jul 21 06:25:46 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 226104 kb
Host smart-e31731f5-023e-4387-86d0-4130159e9f27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551891577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3551891577
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.186720915
Short name T281
Test name
Test status
Simulation time 342669502 ps
CPU time 8.89 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:25:57 PM PDT 24
Peak memory 218344 kb
Host smart-c09c6003-5809-4a3a-88d4-651cee1fe33a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186720915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.186720915
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3296436010
Short name T352
Test name
Test status
Simulation time 1266503635 ps
CPU time 12.77 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:26:01 PM PDT 24
Peak memory 226116 kb
Host smart-1eca3228-3360-464f-bc66-8733b7fd97fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296436010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3296436010
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1386836361
Short name T173
Test name
Test status
Simulation time 269368616 ps
CPU time 3.02 seconds
Started Jul 21 06:25:47 PM PDT 24
Finished Jul 21 06:25:51 PM PDT 24
Peak memory 223056 kb
Host smart-74cee2bd-7b02-4c2d-bb7a-245a6b68c63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386836361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1386836361
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1396748347
Short name T436
Test name
Test status
Simulation time 489153131 ps
CPU time 19.17 seconds
Started Jul 21 06:25:46 PM PDT 24
Finished Jul 21 06:26:06 PM PDT 24
Peak memory 251116 kb
Host smart-7f5177b6-2db5-47c8-8dee-665c1aaefd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396748347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1396748347
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3466634950
Short name T819
Test name
Test status
Simulation time 66619153 ps
CPU time 7.62 seconds
Started Jul 21 06:25:45 PM PDT 24
Finished Jul 21 06:25:54 PM PDT 24
Peak memory 250700 kb
Host smart-d373792c-2fda-4887-974a-417522f01928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466634950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3466634950
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3843847586
Short name T641
Test name
Test status
Simulation time 3235126821 ps
CPU time 51.67 seconds
Started Jul 21 06:25:48 PM PDT 24
Finished Jul 21 06:26:41 PM PDT 24
Peak memory 226264 kb
Host smart-b0179580-d5f3-4d8a-a49c-61f4bc7bd93b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843847586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3843847586
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3332809687
Short name T293
Test name
Test status
Simulation time 21665942 ps
CPU time 0.97 seconds
Started Jul 21 06:25:46 PM PDT 24
Finished Jul 21 06:25:47 PM PDT 24
Peak memory 212036 kb
Host smart-0c95adde-97c2-42a2-a42e-b9c860e15780
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332809687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3332809687
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1835702434
Short name T642
Test name
Test status
Simulation time 38141364 ps
CPU time 1.18 seconds
Started Jul 21 06:24:45 PM PDT 24
Finished Jul 21 06:24:47 PM PDT 24
Peak memory 209136 kb
Host smart-b9f5f201-e174-4757-b066-17cbcc178ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835702434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1835702434
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1083979002
Short name T394
Test name
Test status
Simulation time 37870603 ps
CPU time 0.9 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:24:38 PM PDT 24
Peak memory 208880 kb
Host smart-b849abc5-8520-4174-bee8-ba161fd2bb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083979002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1083979002
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2901290741
Short name T478
Test name
Test status
Simulation time 1929453587 ps
CPU time 9.42 seconds
Started Jul 21 06:24:38 PM PDT 24
Finished Jul 21 06:24:48 PM PDT 24
Peak memory 218424 kb
Host smart-5d0bb987-565b-4933-a2a2-a467b8b75b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901290741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2901290741
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1958477722
Short name T512
Test name
Test status
Simulation time 3634351122 ps
CPU time 11.01 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:24:49 PM PDT 24
Peak memory 217792 kb
Host smart-07bee20b-9bdb-4b45-806b-6aab3957aefb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958477722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1958477722
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3004825998
Short name T773
Test name
Test status
Simulation time 5620233412 ps
CPU time 36.46 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 218692 kb
Host smart-3277db96-f94e-48a1-a8e3-163202a85990
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004825998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3004825998
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3377152617
Short name T582
Test name
Test status
Simulation time 225197309 ps
CPU time 2.14 seconds
Started Jul 21 06:24:43 PM PDT 24
Finished Jul 21 06:24:46 PM PDT 24
Peak memory 217792 kb
Host smart-c79fb063-e3d6-40d2-bb6b-be8479bdc75c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377152617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
377152617
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1390737735
Short name T458
Test name
Test status
Simulation time 317084363 ps
CPU time 6.19 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:24:44 PM PDT 24
Peak memory 218336 kb
Host smart-880d7de1-28e3-42e7-a772-6909be8170e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390737735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1390737735
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.515235186
Short name T60
Test name
Test status
Simulation time 5593262556 ps
CPU time 17.56 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:24:57 PM PDT 24
Peak memory 217760 kb
Host smart-0181e001-7f7d-45a6-8e1a-9f6a9b64740b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515235186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.515235186
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1580582736
Short name T625
Test name
Test status
Simulation time 1053518302 ps
CPU time 4.19 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:24:44 PM PDT 24
Peak memory 217684 kb
Host smart-4eceba98-9f52-4d7a-94c4-a2ffeae7c98f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580582736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1580582736
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2456946757
Short name T558
Test name
Test status
Simulation time 4263522678 ps
CPU time 47.31 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:25:25 PM PDT 24
Peak memory 283812 kb
Host smart-052f0973-6899-44e7-b34a-84055f80f471
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456946757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2456946757
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2357144141
Short name T564
Test name
Test status
Simulation time 2425411158 ps
CPU time 24.16 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:25:04 PM PDT 24
Peak memory 251128 kb
Host smart-54c23f73-98ae-41b7-bada-f2571fb50d20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357144141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2357144141
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2697272872
Short name T481
Test name
Test status
Simulation time 303151181 ps
CPU time 3.63 seconds
Started Jul 21 06:24:38 PM PDT 24
Finished Jul 21 06:24:42 PM PDT 24
Peak memory 218360 kb
Host smart-7d0376da-33f7-45e0-9e08-93c5226a20b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697272872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2697272872
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.4071549300
Short name T152
Test name
Test status
Simulation time 3407196190 ps
CPU time 9.41 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:24:46 PM PDT 24
Peak memory 215424 kb
Host smart-488c17fe-f971-47e8-836c-a49e8341b62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071549300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.4071549300
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3036344067
Short name T292
Test name
Test status
Simulation time 544651676 ps
CPU time 12.52 seconds
Started Jul 21 06:24:42 PM PDT 24
Finished Jul 21 06:24:55 PM PDT 24
Peak memory 226116 kb
Host smart-5a9b9d5e-67f2-4515-8f57-a6882491318b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036344067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3036344067
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2771804555
Short name T190
Test name
Test status
Simulation time 582922221 ps
CPU time 9.49 seconds
Started Jul 21 06:24:38 PM PDT 24
Finished Jul 21 06:24:48 PM PDT 24
Peak memory 226036 kb
Host smart-cc82aef3-829a-4989-a0b7-013059802677
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771804555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2771804555
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2997847908
Short name T236
Test name
Test status
Simulation time 384025034 ps
CPU time 8.37 seconds
Started Jul 21 06:24:41 PM PDT 24
Finished Jul 21 06:24:50 PM PDT 24
Peak memory 218308 kb
Host smart-2cdd6f7c-f530-4b69-b69d-b167b4ecb6b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997847908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
997847908
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1873333948
Short name T550
Test name
Test status
Simulation time 799877976 ps
CPU time 9.81 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:24:50 PM PDT 24
Peak memory 226316 kb
Host smart-678b7209-8a6a-42f1-93ff-8a758e8ce2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873333948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1873333948
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2604292026
Short name T78
Test name
Test status
Simulation time 43320537 ps
CPU time 1.32 seconds
Started Jul 21 06:24:38 PM PDT 24
Finished Jul 21 06:24:40 PM PDT 24
Peak memory 217816 kb
Host smart-07ccc540-57d8-460f-99be-b74141444100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604292026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2604292026
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1355959092
Short name T264
Test name
Test status
Simulation time 646299318 ps
CPU time 20.92 seconds
Started Jul 21 06:24:38 PM PDT 24
Finished Jul 21 06:25:00 PM PDT 24
Peak memory 251216 kb
Host smart-e9a2c650-ab6f-4af7-8157-e5a9ce2ec5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355959092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1355959092
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2654962411
Short name T598
Test name
Test status
Simulation time 122123185 ps
CPU time 4.2 seconds
Started Jul 21 06:24:45 PM PDT 24
Finished Jul 21 06:24:50 PM PDT 24
Peak memory 222812 kb
Host smart-c9d9fe4e-9de4-465c-bacd-2ce2a769bbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654962411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2654962411
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.457348006
Short name T744
Test name
Test status
Simulation time 22512297688 ps
CPU time 65.63 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:25:44 PM PDT 24
Peak memory 251084 kb
Host smart-d90a5db3-14c2-4e0b-90d0-08052588d235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457348006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.457348006
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3750123380
Short name T106
Test name
Test status
Simulation time 9954764591 ps
CPU time 335.72 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:30:21 PM PDT 24
Peak memory 292272 kb
Host smart-128f33a4-7f21-4d40-a15f-01b2934f9b12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3750123380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3750123380
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1572181781
Short name T408
Test name
Test status
Simulation time 49328667 ps
CPU time 0.89 seconds
Started Jul 21 06:24:41 PM PDT 24
Finished Jul 21 06:24:42 PM PDT 24
Peak memory 211900 kb
Host smart-8ed644f9-1ef4-4aba-b367-7f2aaf3f5946
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572181781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1572181781
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3030286123
Short name T840
Test name
Test status
Simulation time 15070933 ps
CPU time 1.06 seconds
Started Jul 21 06:25:54 PM PDT 24
Finished Jul 21 06:25:55 PM PDT 24
Peak memory 209104 kb
Host smart-45668cd6-a8b1-4d63-ab0f-c24de4a8ebca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030286123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3030286123
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2542496284
Short name T494
Test name
Test status
Simulation time 2397681386 ps
CPU time 11.05 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:26:04 PM PDT 24
Peak memory 226244 kb
Host smart-af239aac-fe93-4715-9998-2e3f09beb36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542496284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2542496284
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.71185501
Short name T7
Test name
Test status
Simulation time 1221805179 ps
CPU time 6.77 seconds
Started Jul 21 06:25:55 PM PDT 24
Finished Jul 21 06:26:02 PM PDT 24
Peak memory 217436 kb
Host smart-1672ee79-85c6-489f-af59-942f4fa1b3d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71185501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.71185501
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.631944602
Short name T254
Test name
Test status
Simulation time 31913568 ps
CPU time 2.28 seconds
Started Jul 21 06:25:53 PM PDT 24
Finished Jul 21 06:25:56 PM PDT 24
Peak memory 222340 kb
Host smart-6ff1a821-199f-498c-b0f4-70098404edc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631944602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.631944602
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.587096592
Short name T2
Test name
Test status
Simulation time 382301242 ps
CPU time 8.16 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:26:01 PM PDT 24
Peak memory 226116 kb
Host smart-05e37a64-a682-466b-bacc-983704707edf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587096592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.587096592
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3134376773
Short name T151
Test name
Test status
Simulation time 328040905 ps
CPU time 10.18 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:11 PM PDT 24
Peak memory 226112 kb
Host smart-cf198ad4-e3c9-492f-b7dc-269284b5e96e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134376773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3134376773
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2173204596
Short name T410
Test name
Test status
Simulation time 433729802 ps
CPU time 9.86 seconds
Started Jul 21 06:25:55 PM PDT 24
Finished Jul 21 06:26:05 PM PDT 24
Peak memory 225756 kb
Host smart-1febabd0-68b6-4f8d-81b7-27031f547d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173204596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2173204596
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3614228357
Short name T817
Test name
Test status
Simulation time 105228244 ps
CPU time 2.17 seconds
Started Jul 21 06:25:53 PM PDT 24
Finished Jul 21 06:25:56 PM PDT 24
Peak memory 214404 kb
Host smart-57b2e217-d72a-41c6-bc92-309bf978f251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614228357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3614228357
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1466748798
Short name T796
Test name
Test status
Simulation time 226286131 ps
CPU time 29.81 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:26:22 PM PDT 24
Peak memory 251216 kb
Host smart-038e1294-fe43-4d20-bd45-8848be825295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466748798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1466748798
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4285152269
Short name T702
Test name
Test status
Simulation time 193557394 ps
CPU time 6.55 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:25:59 PM PDT 24
Peak memory 246904 kb
Host smart-f85dc561-2064-48bc-9b6a-33ca2073eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285152269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4285152269
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1718804084
Short name T779
Test name
Test status
Simulation time 11686317584 ps
CPU time 104.35 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:27:45 PM PDT 24
Peak memory 246520 kb
Host smart-cb653d51-98c2-48fc-961d-d46fcc693b1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718804084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1718804084
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.542905595
Short name T144
Test name
Test status
Simulation time 402062710459 ps
CPU time 2277.55 seconds
Started Jul 21 06:25:55 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 775668 kb
Host smart-8f5aee58-3e23-45af-a0f2-45440c0f8454
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=542905595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.542905595
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3328230360
Short name T619
Test name
Test status
Simulation time 26530397 ps
CPU time 1.03 seconds
Started Jul 21 06:25:50 PM PDT 24
Finished Jul 21 06:25:52 PM PDT 24
Peak memory 217836 kb
Host smart-26a3b2c4-1984-4ee9-8a87-fba8982b9938
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328230360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3328230360
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3160142056
Short name T504
Test name
Test status
Simulation time 65778596 ps
CPU time 0.9 seconds
Started Jul 21 06:25:54 PM PDT 24
Finished Jul 21 06:25:56 PM PDT 24
Peak memory 208948 kb
Host smart-594a1baa-fb27-4117-b7b7-b6f5241794c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160142056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3160142056
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2134620099
Short name T823
Test name
Test status
Simulation time 258657986 ps
CPU time 10.09 seconds
Started Jul 21 06:25:55 PM PDT 24
Finished Jul 21 06:26:06 PM PDT 24
Peak memory 226180 kb
Host smart-8ee58fc2-7870-4546-a005-38867bf5ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134620099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2134620099
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.612877681
Short name T174
Test name
Test status
Simulation time 38093657 ps
CPU time 1.67 seconds
Started Jul 21 06:25:56 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 217108 kb
Host smart-816f3c8d-89a8-4440-9c0d-1c9e80a5e5b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612877681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.612877681
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1966596134
Short name T588
Test name
Test status
Simulation time 133884327 ps
CPU time 1.96 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:25:55 PM PDT 24
Peak memory 218320 kb
Host smart-f778b328-2a4a-4e3e-8481-4066e5e20a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966596134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1966596134
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1965858939
Short name T19
Test name
Test status
Simulation time 1073664412 ps
CPU time 13.67 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:26:07 PM PDT 24
Peak memory 226140 kb
Host smart-88dd459a-a3f3-4181-8131-75eed6601abf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965858939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1965858939
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3930638617
Short name T251
Test name
Test status
Simulation time 502575571 ps
CPU time 10.65 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:26:04 PM PDT 24
Peak memory 226100 kb
Host smart-98eaf9e0-384b-49ef-b36c-075f8d9cd998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930638617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3930638617
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3697522278
Short name T574
Test name
Test status
Simulation time 1304333261 ps
CPU time 11.3 seconds
Started Jul 21 06:25:55 PM PDT 24
Finished Jul 21 06:26:07 PM PDT 24
Peak memory 218320 kb
Host smart-84af47e5-dedb-459a-969a-599a465e0816
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697522278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3697522278
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.813898382
Short name T323
Test name
Test status
Simulation time 2212661026 ps
CPU time 12.64 seconds
Started Jul 21 06:25:54 PM PDT 24
Finished Jul 21 06:26:07 PM PDT 24
Peak memory 226252 kb
Host smart-6763d319-0fbc-4c32-bd33-c4037e295e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813898382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.813898382
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.714249888
Short name T171
Test name
Test status
Simulation time 619199182 ps
CPU time 2.73 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:25:56 PM PDT 24
Peak memory 214784 kb
Host smart-2af9c773-b8ec-471e-81c6-783b1416e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714249888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.714249888
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1974214917
Short name T701
Test name
Test status
Simulation time 1113268413 ps
CPU time 20.63 seconds
Started Jul 21 06:25:58 PM PDT 24
Finished Jul 21 06:26:20 PM PDT 24
Peak memory 251112 kb
Host smart-829332d6-e53b-4849-8d3d-9a41a2c9e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974214917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1974214917
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2468809823
Short name T300
Test name
Test status
Simulation time 134851823 ps
CPU time 3.64 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:05 PM PDT 24
Peak memory 223088 kb
Host smart-338a5ae0-5b8f-4e52-9792-3a65426338fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468809823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2468809823
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3711951035
Short name T844
Test name
Test status
Simulation time 167295278808 ps
CPU time 327.81 seconds
Started Jul 21 06:25:55 PM PDT 24
Finished Jul 21 06:31:23 PM PDT 24
Peak memory 316736 kb
Host smart-0b3ac967-ac16-4e20-8ff1-8fc4ea0868ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711951035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3711951035
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.315632154
Short name T226
Test name
Test status
Simulation time 97776634304 ps
CPU time 441.85 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:33:15 PM PDT 24
Peak memory 284060 kb
Host smart-56e9e1e9-5cca-49ba-b02b-fe4ecf9cf543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=315632154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.315632154
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2644381997
Short name T793
Test name
Test status
Simulation time 108517813 ps
CPU time 0.95 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:25:52 PM PDT 24
Peak memory 211984 kb
Host smart-00f04c42-386c-46dd-9eff-7bf8167fdd64
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644381997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2644381997
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1238819048
Short name T670
Test name
Test status
Simulation time 66638978 ps
CPU time 0.91 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:02 PM PDT 24
Peak memory 209020 kb
Host smart-977dc090-1b82-4661-b724-1ebd8ba54425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238819048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1238819048
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2689043418
Short name T83
Test name
Test status
Simulation time 912492815 ps
CPU time 15.6 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:26:08 PM PDT 24
Peak memory 218400 kb
Host smart-90c36870-ac7f-47e5-82a5-ae2a138a5b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689043418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2689043418
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1366273531
Short name T733
Test name
Test status
Simulation time 1052821620 ps
CPU time 6.02 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:07 PM PDT 24
Peak memory 217120 kb
Host smart-9ca820ac-7ba0-4405-82f4-c55b7dcf23f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366273531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1366273531
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2978772444
Short name T175
Test name
Test status
Simulation time 43381015 ps
CPU time 2.74 seconds
Started Jul 21 06:25:53 PM PDT 24
Finished Jul 21 06:25:57 PM PDT 24
Peak memory 218356 kb
Host smart-b65861d2-f343-42ef-b038-c9a11da68e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978772444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2978772444
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3335348324
Short name T187
Test name
Test status
Simulation time 1049614905 ps
CPU time 8.62 seconds
Started Jul 21 06:25:56 PM PDT 24
Finished Jul 21 06:26:06 PM PDT 24
Peak memory 226168 kb
Host smart-600b98a1-eea5-4da3-b900-f7ab2b3614a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335348324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3335348324
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3535704231
Short name T500
Test name
Test status
Simulation time 639467018 ps
CPU time 16.13 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:26:09 PM PDT 24
Peak memory 226076 kb
Host smart-fce2ac16-252b-43e1-bf55-b214d8b92e3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535704231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3535704231
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3820208162
Short name T56
Test name
Test status
Simulation time 758467383 ps
CPU time 8.05 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:10 PM PDT 24
Peak memory 218264 kb
Host smart-62577dc6-7dc7-4ca3-b4c9-8256ec139d9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820208162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3820208162
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2405658877
Short name T442
Test name
Test status
Simulation time 2465263456 ps
CPU time 11.68 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:26:04 PM PDT 24
Peak memory 226060 kb
Host smart-ef76b396-d6ce-497d-911f-1d2407c6b135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405658877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2405658877
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2923288957
Short name T322
Test name
Test status
Simulation time 156187652 ps
CPU time 1.19 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:25:53 PM PDT 24
Peak memory 221864 kb
Host smart-c59ee79e-633b-4f0e-bcec-c6ce5c8637b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923288957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2923288957
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3140536895
Short name T197
Test name
Test status
Simulation time 539527375 ps
CPU time 23.01 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:24 PM PDT 24
Peak memory 251140 kb
Host smart-13511e4f-9a8a-4da5-ad41-0302472d92a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140536895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3140536895
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.118761070
Short name T863
Test name
Test status
Simulation time 79769616 ps
CPU time 3.42 seconds
Started Jul 21 06:25:57 PM PDT 24
Finished Jul 21 06:26:01 PM PDT 24
Peak memory 226536 kb
Host smart-599fb80f-5036-4b6d-9620-1205023e662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118761070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.118761070
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.899804849
Short name T279
Test name
Test status
Simulation time 46612269985 ps
CPU time 198.57 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:29:12 PM PDT 24
Peak memory 268996 kb
Host smart-c9911a1c-360a-4a76-8627-39738a8ef89d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899804849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.899804849
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.272400691
Short name T148
Test name
Test status
Simulation time 22975167463 ps
CPU time 416.17 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 277060 kb
Host smart-d78f4931-bd53-4b59-a031-d1289d95df7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=272400691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.272400691
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.721643687
Short name T263
Test name
Test status
Simulation time 16011304 ps
CPU time 0.92 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:01 PM PDT 24
Peak memory 211952 kb
Host smart-82912032-0e05-463d-80df-da281c26aca3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721643687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.721643687
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2547856707
Short name T697
Test name
Test status
Simulation time 41657726 ps
CPU time 0.88 seconds
Started Jul 21 06:26:01 PM PDT 24
Finished Jul 21 06:26:03 PM PDT 24
Peak memory 208792 kb
Host smart-41936f95-585b-47e9-8cb4-2f05d5308726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547856707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2547856707
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3288731851
Short name T351
Test name
Test status
Simulation time 654513931 ps
CPU time 12.36 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:26:05 PM PDT 24
Peak memory 226188 kb
Host smart-4a10f2a8-2d86-4ba1-b9cd-707b47b3752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288731851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3288731851
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2224624365
Short name T199
Test name
Test status
Simulation time 100752244 ps
CPU time 1.7 seconds
Started Jul 21 06:25:56 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 217112 kb
Host smart-a185ce2a-8b74-4678-b0c1-baeafc17229a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224624365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2224624365
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2317642028
Short name T395
Test name
Test status
Simulation time 96210199 ps
CPU time 3.44 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:03 PM PDT 24
Peak memory 218316 kb
Host smart-f35cba62-9b74-4033-aa51-7ec42e80e6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317642028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2317642028
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3135474813
Short name T246
Test name
Test status
Simulation time 596946640 ps
CPU time 14.4 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:16 PM PDT 24
Peak memory 226168 kb
Host smart-5f274e91-7f2a-4234-89cf-9ecb530828ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135474813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3135474813
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3089966430
Short name T638
Test name
Test status
Simulation time 375630965 ps
CPU time 11.4 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:18 PM PDT 24
Peak memory 226092 kb
Host smart-31ccdfc0-8732-4fdf-bb49-dc8ee1ea1fe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089966430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3089966430
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.4025271189
Short name T724
Test name
Test status
Simulation time 456146340 ps
CPU time 9.6 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:11 PM PDT 24
Peak memory 218300 kb
Host smart-924ec59e-dcba-4ed6-8786-034615cd98b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025271189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
4025271189
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2447095400
Short name T355
Test name
Test status
Simulation time 373936183 ps
CPU time 11.66 seconds
Started Jul 21 06:25:51 PM PDT 24
Finished Jul 21 06:26:04 PM PDT 24
Peak memory 226132 kb
Host smart-5496aa2d-ead0-4213-8741-a3a9eef7166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447095400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2447095400
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.4039943242
Short name T682
Test name
Test status
Simulation time 254425956 ps
CPU time 2.61 seconds
Started Jul 21 06:25:53 PM PDT 24
Finished Jul 21 06:25:57 PM PDT 24
Peak memory 217772 kb
Host smart-da0a744a-466a-4563-81a7-ecee0ec644e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039943242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.4039943242
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3956029388
Short name T771
Test name
Test status
Simulation time 192371607 ps
CPU time 21.61 seconds
Started Jul 21 06:25:50 PM PDT 24
Finished Jul 21 06:26:12 PM PDT 24
Peak memory 251120 kb
Host smart-dcd335eb-f02f-48e9-b56c-9d9581b0c463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956029388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3956029388
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3834718552
Short name T665
Test name
Test status
Simulation time 74388217 ps
CPU time 7.8 seconds
Started Jul 21 06:25:52 PM PDT 24
Finished Jul 21 06:26:01 PM PDT 24
Peak memory 244196 kb
Host smart-8e30514b-6926-4312-82fa-8b78cd9d8895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834718552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3834718552
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.497699092
Short name T48
Test name
Test status
Simulation time 8540712484 ps
CPU time 99.42 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:27:41 PM PDT 24
Peak memory 252916 kb
Host smart-172039f9-f0b6-479c-9b18-1044258e664b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497699092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.497699092
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1734950200
Short name T678
Test name
Test status
Simulation time 49198435 ps
CPU time 1.02 seconds
Started Jul 21 06:25:58 PM PDT 24
Finished Jul 21 06:26:00 PM PDT 24
Peak memory 213068 kb
Host smart-62488b26-e8f0-4ff8-b704-c26c1ca95196
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734950200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1734950200
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3719672067
Short name T347
Test name
Test status
Simulation time 22510974 ps
CPU time 0.83 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:01 PM PDT 24
Peak memory 208784 kb
Host smart-2a4dca1e-bd83-4faa-8d8d-59a148caa104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719672067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3719672067
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.915293694
Short name T467
Test name
Test status
Simulation time 255412169 ps
CPU time 9.2 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:09 PM PDT 24
Peak memory 218376 kb
Host smart-5d15d3f8-b8db-4e38-a771-a0e774bd6c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915293694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.915293694
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2744236381
Short name T26
Test name
Test status
Simulation time 1885340085 ps
CPU time 7.98 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:08 PM PDT 24
Peak memory 217524 kb
Host smart-84345bf8-a031-456b-b448-2e5d323b9bdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744236381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2744236381
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1787019332
Short name T486
Test name
Test status
Simulation time 329460204 ps
CPU time 2.34 seconds
Started Jul 21 06:25:57 PM PDT 24
Finished Jul 21 06:26:00 PM PDT 24
Peak memory 222388 kb
Host smart-e5d74f80-bad4-4174-8c98-bbe9ed6604bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787019332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1787019332
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3242304686
Short name T428
Test name
Test status
Simulation time 1964801012 ps
CPU time 12.61 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:13 PM PDT 24
Peak memory 226304 kb
Host smart-bfc91ba0-8298-4807-a7d0-d795d1799274
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242304686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3242304686
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1161347362
Short name T389
Test name
Test status
Simulation time 2028994909 ps
CPU time 13.35 seconds
Started Jul 21 06:25:56 PM PDT 24
Finished Jul 21 06:26:10 PM PDT 24
Peak memory 226116 kb
Host smart-ed0f940c-e19c-43ba-9406-310639ad18e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161347362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1161347362
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1178293251
Short name T289
Test name
Test status
Simulation time 1033528097 ps
CPU time 9.54 seconds
Started Jul 21 06:25:57 PM PDT 24
Finished Jul 21 06:26:07 PM PDT 24
Peak memory 218252 kb
Host smart-f1074f46-0583-436c-9937-6af4e923662d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178293251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1178293251
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2100736590
Short name T671
Test name
Test status
Simulation time 2014422121 ps
CPU time 9.49 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:11 PM PDT 24
Peak memory 225044 kb
Host smart-5dc3daed-10b7-4059-a5d2-6652771f93f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100736590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2100736590
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2530731362
Short name T807
Test name
Test status
Simulation time 111026731 ps
CPU time 3.64 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:05 PM PDT 24
Peak memory 217924 kb
Host smart-ea4e098c-f5f7-45ed-b1f2-7998f52ca686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530731362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2530731362
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.349906719
Short name T86
Test name
Test status
Simulation time 628746383 ps
CPU time 23.3 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:25 PM PDT 24
Peak memory 251120 kb
Host smart-444403db-7ff9-49a3-bcf3-5428ca9609c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349906719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.349906719
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1758527165
Short name T422
Test name
Test status
Simulation time 659528295 ps
CPU time 4.53 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:05 PM PDT 24
Peak memory 223136 kb
Host smart-6f8a0ad9-b1d6-472c-a7d4-4e9d13075938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758527165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1758527165
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3379666963
Short name T632
Test name
Test status
Simulation time 5263680418 ps
CPU time 55.79 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:57 PM PDT 24
Peak memory 251188 kb
Host smart-7ec02eea-6692-4561-ba70-37ac56af9c54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379666963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3379666963
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1958510721
Short name T188
Test name
Test status
Simulation time 25951030034 ps
CPU time 564.79 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:35:26 PM PDT 24
Peak memory 283920 kb
Host smart-5b3c3a8f-b421-449f-9a6e-493b112d38b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1958510721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1958510721
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3717435264
Short name T552
Test name
Test status
Simulation time 36623173 ps
CPU time 0.95 seconds
Started Jul 21 06:25:58 PM PDT 24
Finished Jul 21 06:26:00 PM PDT 24
Peak memory 211936 kb
Host smart-461f2e60-2777-483b-addf-67f506f92ada
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717435264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3717435264
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.517383427
Short name T240
Test name
Test status
Simulation time 28149182 ps
CPU time 1.34 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:08 PM PDT 24
Peak memory 209092 kb
Host smart-391aa3eb-7774-4cdf-9079-6cbddca967c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517383427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.517383427
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2011698325
Short name T548
Test name
Test status
Simulation time 443320215 ps
CPU time 17.19 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:17 PM PDT 24
Peak memory 218356 kb
Host smart-ebd3d27e-fe7a-4493-82d8-560bb567648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011698325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2011698325
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3842971002
Short name T62
Test name
Test status
Simulation time 1597344104 ps
CPU time 4.57 seconds
Started Jul 21 06:25:59 PM PDT 24
Finished Jul 21 06:26:05 PM PDT 24
Peak memory 217340 kb
Host smart-0b62d51d-2b63-460e-8982-a8d968d24f7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842971002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3842971002
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3857080757
Short name T517
Test name
Test status
Simulation time 90275349 ps
CPU time 1.93 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:03 PM PDT 24
Peak memory 218396 kb
Host smart-f9f668d5-542c-4ce4-8416-a1be532d9995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857080757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3857080757
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2529540280
Short name T325
Test name
Test status
Simulation time 1061711908 ps
CPU time 12.82 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:19 PM PDT 24
Peak memory 226236 kb
Host smart-b53953d9-d653-4cca-babd-635c76104891
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529540280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2529540280
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1784394125
Short name T690
Test name
Test status
Simulation time 2813391464 ps
CPU time 9.88 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:16 PM PDT 24
Peak memory 226148 kb
Host smart-a67a93da-92d3-4a86-ae53-a00f1fb79014
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784394125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1784394125
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2213318890
Short name T662
Test name
Test status
Simulation time 246341421 ps
CPU time 9.44 seconds
Started Jul 21 06:26:04 PM PDT 24
Finished Jul 21 06:26:14 PM PDT 24
Peak memory 226120 kb
Host smart-433437c0-a67b-4611-87db-c8d9708c2233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213318890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2213318890
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1331705920
Short name T687
Test name
Test status
Simulation time 290228054 ps
CPU time 8.42 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:10 PM PDT 24
Peak memory 225072 kb
Host smart-76355a78-601e-4892-b732-6f220cdb5f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331705920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1331705920
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2238943396
Short name T64
Test name
Test status
Simulation time 68797646 ps
CPU time 1.14 seconds
Started Jul 21 06:26:00 PM PDT 24
Finished Jul 21 06:26:02 PM PDT 24
Peak memory 212176 kb
Host smart-a7841450-06d0-4a0c-8bf1-fde66d8748a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238943396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2238943396
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.54888064
Short name T337
Test name
Test status
Simulation time 232266804 ps
CPU time 20.63 seconds
Started Jul 21 06:26:01 PM PDT 24
Finished Jul 21 06:26:22 PM PDT 24
Peak memory 251060 kb
Host smart-dee2a5cd-c208-42c0-abf6-fd3696a4fff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54888064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.54888064
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.266955654
Short name T87
Test name
Test status
Simulation time 205410361 ps
CPU time 9.59 seconds
Started Jul 21 06:25:58 PM PDT 24
Finished Jul 21 06:26:09 PM PDT 24
Peak memory 251180 kb
Host smart-962f7c76-5d48-419e-945f-3533ccb329c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266955654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.266955654
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1429843340
Short name T320
Test name
Test status
Simulation time 19718447991 ps
CPU time 46.81 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:55 PM PDT 24
Peak memory 219520 kb
Host smart-05fafcfc-340d-44eb-9828-b923b4f5013d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429843340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1429843340
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3513404659
Short name T294
Test name
Test status
Simulation time 11902406 ps
CPU time 0.86 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:08 PM PDT 24
Peak memory 211952 kb
Host smart-3ec6b4c8-ae69-4a16-b281-235050a98745
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513404659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3513404659
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2911332960
Short name T272
Test name
Test status
Simulation time 183578245 ps
CPU time 0.88 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:09 PM PDT 24
Peak memory 209020 kb
Host smart-0f63b8f0-c0e1-40af-a1ad-2f0e7de8dc75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911332960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2911332960
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2060789589
Short name T847
Test name
Test status
Simulation time 655478190 ps
CPU time 8.92 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:17 PM PDT 24
Peak memory 218396 kb
Host smart-376cf3da-b423-4574-865a-1e819b00afb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060789589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2060789589
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.815546013
Short name T35
Test name
Test status
Simulation time 376902848 ps
CPU time 9.47 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:18 PM PDT 24
Peak memory 217480 kb
Host smart-fe7935c5-0988-47f6-b7c3-4574e4f75bd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815546013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.815546013
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2864540335
Short name T368
Test name
Test status
Simulation time 171969298 ps
CPU time 2.22 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:10 PM PDT 24
Peak memory 218380 kb
Host smart-d8992ca2-919d-4c02-a40e-8a43e3732c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864540335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2864540335
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.630203268
Short name T480
Test name
Test status
Simulation time 295984298 ps
CPU time 10.42 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:16 PM PDT 24
Peak memory 226036 kb
Host smart-54222511-095b-4058-b461-3b939d3ac6dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630203268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.630203268
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2079183179
Short name T571
Test name
Test status
Simulation time 719237175 ps
CPU time 7.54 seconds
Started Jul 21 06:26:04 PM PDT 24
Finished Jul 21 06:26:12 PM PDT 24
Peak memory 218308 kb
Host smart-d922b591-9945-45ed-a9f7-32758a78ed44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079183179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2079183179
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2211724659
Short name T342
Test name
Test status
Simulation time 212471056 ps
CPU time 9.11 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:17 PM PDT 24
Peak memory 226168 kb
Host smart-84c06f25-73a8-4831-9d75-54ecda797522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211724659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2211724659
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2546064948
Short name T620
Test name
Test status
Simulation time 193555518 ps
CPU time 6.13 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:14 PM PDT 24
Peak memory 217864 kb
Host smart-79ad644e-b296-4120-ad74-f1da0e8dde1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546064948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2546064948
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3537100233
Short name T324
Test name
Test status
Simulation time 244857161 ps
CPU time 26.42 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:32 PM PDT 24
Peak memory 251232 kb
Host smart-e3e74abd-c702-46e2-9c6e-2e2df058e7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537100233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3537100233
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2763419201
Short name T597
Test name
Test status
Simulation time 89960805 ps
CPU time 8.14 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:16 PM PDT 24
Peak memory 251044 kb
Host smart-8345daf9-f22f-4288-997e-9b7bc2b1642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763419201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2763419201
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.399065927
Short name T103
Test name
Test status
Simulation time 19199145125 ps
CPU time 300.18 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:31:07 PM PDT 24
Peak memory 275724 kb
Host smart-5ca010a4-7253-41d7-b1ec-ab5346934408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399065927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.399065927
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1821644704
Short name T693
Test name
Test status
Simulation time 37182511 ps
CPU time 0.96 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:09 PM PDT 24
Peak memory 213048 kb
Host smart-a9aed838-dc7b-4ffd-8fdb-0af0ce29a0e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821644704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1821644704
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1195318065
Short name T764
Test name
Test status
Simulation time 20937279 ps
CPU time 0.95 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:08 PM PDT 24
Peak memory 208944 kb
Host smart-10f4abaf-d87d-4792-9134-7e7e1a98d41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195318065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1195318065
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.327732018
Short name T348
Test name
Test status
Simulation time 216625100 ps
CPU time 9.06 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:17 PM PDT 24
Peak memory 218308 kb
Host smart-40102aae-8130-4477-a6ca-1ad9c6f43ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327732018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.327732018
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.298892672
Short name T720
Test name
Test status
Simulation time 245148083 ps
CPU time 7.86 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:14 PM PDT 24
Peak memory 217552 kb
Host smart-16e5383c-aabe-4e7b-909b-9ee9ed0ec8d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298892672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.298892672
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3474631743
Short name T183
Test name
Test status
Simulation time 193267423 ps
CPU time 2.33 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:10 PM PDT 24
Peak memory 218296 kb
Host smart-e3647c9e-5d05-4d7c-8401-c447e95066de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474631743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3474631743
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3043120276
Short name T460
Test name
Test status
Simulation time 237933643 ps
CPU time 12.35 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:21 PM PDT 24
Peak memory 219000 kb
Host smart-f9fe4696-6edf-44a8-99fe-c3901288feb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043120276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3043120276
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1809156357
Short name T732
Test name
Test status
Simulation time 318498404 ps
CPU time 9.71 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:16 PM PDT 24
Peak memory 226104 kb
Host smart-d3968427-417f-4023-a530-2143f3fc1af7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809156357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1809156357
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2020912624
Short name T230
Test name
Test status
Simulation time 316655731 ps
CPU time 7.82 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:15 PM PDT 24
Peak memory 226208 kb
Host smart-90cdf3bd-c601-4a2c-af72-9393949c15c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020912624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2020912624
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.440944365
Short name T627
Test name
Test status
Simulation time 294418621 ps
CPU time 19.56 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:27 PM PDT 24
Peak memory 251092 kb
Host smart-08e80e32-c7d7-4f11-a6d3-6492bd80c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440944365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.440944365
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.591351919
Short name T818
Test name
Test status
Simulation time 176159163 ps
CPU time 6.36 seconds
Started Jul 21 06:26:04 PM PDT 24
Finished Jul 21 06:26:11 PM PDT 24
Peak memory 244528 kb
Host smart-57fb52a9-02ae-48e4-ac49-5da9148ef7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591351919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.591351919
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1970817925
Short name T589
Test name
Test status
Simulation time 4966258159 ps
CPU time 56.04 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:27:02 PM PDT 24
Peak memory 253408 kb
Host smart-c466056d-c686-445e-bd10-59752118cd0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970817925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1970817925
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4294040434
Short name T223
Test name
Test status
Simulation time 45500907 ps
CPU time 0.82 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:08 PM PDT 24
Peak memory 211992 kb
Host smart-7b60876d-acdf-4a03-941f-148cac634373
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294040434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4294040434
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.951980157
Short name T594
Test name
Test status
Simulation time 16822323 ps
CPU time 0.95 seconds
Started Jul 21 06:26:12 PM PDT 24
Finished Jul 21 06:26:14 PM PDT 24
Peak memory 208928 kb
Host smart-7c313fe2-ae88-43e1-ad4a-df32e9be2278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951980157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.951980157
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2617544884
Short name T861
Test name
Test status
Simulation time 216588835 ps
CPU time 11.49 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:20 PM PDT 24
Peak memory 226196 kb
Host smart-294097a5-fe2b-4a2f-b8df-5204eb7017c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617544884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2617544884
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3085380121
Short name T31
Test name
Test status
Simulation time 3787876316 ps
CPU time 9.38 seconds
Started Jul 21 06:26:12 PM PDT 24
Finished Jul 21 06:26:22 PM PDT 24
Peak memory 217176 kb
Host smart-8f89039e-c5ee-4d5f-b22f-c71d1efc4194
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085380121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3085380121
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.881597119
Short name T374
Test name
Test status
Simulation time 141858811 ps
CPU time 5.73 seconds
Started Jul 21 06:26:07 PM PDT 24
Finished Jul 21 06:26:14 PM PDT 24
Peak memory 218316 kb
Host smart-03b602cf-37ad-45d2-9e8a-8c54ab1455bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881597119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.881597119
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3391524105
Short name T242
Test name
Test status
Simulation time 1627815256 ps
CPU time 18.44 seconds
Started Jul 21 06:26:11 PM PDT 24
Finished Jul 21 06:26:30 PM PDT 24
Peak memory 219020 kb
Host smart-0c12f516-772c-430f-9ab5-a58131fc7683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391524105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3391524105
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2080149314
Short name T317
Test name
Test status
Simulation time 1922585586 ps
CPU time 18.73 seconds
Started Jul 21 06:26:13 PM PDT 24
Finished Jul 21 06:26:32 PM PDT 24
Peak memory 226100 kb
Host smart-4aac6eb2-c768-438c-99d0-65f3e223b6d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080149314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2080149314
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.353862920
Short name T471
Test name
Test status
Simulation time 628880223 ps
CPU time 10.52 seconds
Started Jul 21 06:26:08 PM PDT 24
Finished Jul 21 06:26:19 PM PDT 24
Peak memory 218320 kb
Host smart-c9122065-895c-49d8-ae6d-7d4e2f29ecdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353862920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.353862920
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3279306658
Short name T438
Test name
Test status
Simulation time 764203496 ps
CPU time 13.38 seconds
Started Jul 21 06:26:11 PM PDT 24
Finished Jul 21 06:26:25 PM PDT 24
Peak memory 226176 kb
Host smart-0382092b-bfdf-46e5-9673-dd3b1302af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279306658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3279306658
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2614412010
Short name T679
Test name
Test status
Simulation time 63940577 ps
CPU time 3.28 seconds
Started Jul 21 06:26:03 PM PDT 24
Finished Jul 21 06:26:06 PM PDT 24
Peak memory 217792 kb
Host smart-e168a6f3-c049-4e1e-9a26-ab451b78cd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614412010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2614412010
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2699158259
Short name T826
Test name
Test status
Simulation time 260985491 ps
CPU time 23.44 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:29 PM PDT 24
Peak memory 250740 kb
Host smart-db7d656d-f91b-421a-8f9e-718a61286b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699158259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2699158259
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1800760498
Short name T645
Test name
Test status
Simulation time 104899426 ps
CPU time 4.06 seconds
Started Jul 21 06:26:05 PM PDT 24
Finished Jul 21 06:26:10 PM PDT 24
Peak memory 218516 kb
Host smart-49d6929a-ccdc-4e77-a7aa-3d4a8fa6020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800760498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1800760498
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3419748972
Short name T104
Test name
Test status
Simulation time 6188022008 ps
CPU time 160.13 seconds
Started Jul 21 06:26:11 PM PDT 24
Finished Jul 21 06:28:52 PM PDT 24
Peak memory 277792 kb
Host smart-50c07257-1fbd-4772-92a7-f85367aa08ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419748972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3419748972
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.744491854
Short name T100
Test name
Test status
Simulation time 42015849 ps
CPU time 0.96 seconds
Started Jul 21 06:26:06 PM PDT 24
Finished Jul 21 06:26:09 PM PDT 24
Peak memory 211992 kb
Host smart-24404db3-ecb2-4db6-a7de-220b9096630c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744491854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.744491854
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2884575871
Short name T84
Test name
Test status
Simulation time 61472711 ps
CPU time 0.97 seconds
Started Jul 21 06:26:14 PM PDT 24
Finished Jul 21 06:26:15 PM PDT 24
Peak memory 208968 kb
Host smart-9d9e6e10-12ff-4d1a-89bd-01b023ceb046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884575871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2884575871
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.590158030
Short name T492
Test name
Test status
Simulation time 2514415469 ps
CPU time 13.38 seconds
Started Jul 21 06:26:19 PM PDT 24
Finished Jul 21 06:26:33 PM PDT 24
Peak memory 226236 kb
Host smart-29b22b59-b323-46a1-a86f-aca63c841c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590158030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.590158030
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.616866684
Short name T32
Test name
Test status
Simulation time 318367490 ps
CPU time 3.85 seconds
Started Jul 21 06:26:15 PM PDT 24
Finished Jul 21 06:26:19 PM PDT 24
Peak memory 217104 kb
Host smart-7fd2e114-7928-4c2c-bbc8-10fc11a7825f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616866684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.616866684
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2754421475
Short name T663
Test name
Test status
Simulation time 254407515 ps
CPU time 2.78 seconds
Started Jul 21 06:26:13 PM PDT 24
Finished Jul 21 06:26:16 PM PDT 24
Peak memory 218360 kb
Host smart-5db7609b-f760-4baf-a51a-d77e35e4f148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754421475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2754421475
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1268708170
Short name T305
Test name
Test status
Simulation time 630517436 ps
CPU time 7.85 seconds
Started Jul 21 06:26:12 PM PDT 24
Finished Jul 21 06:26:20 PM PDT 24
Peak memory 226084 kb
Host smart-849e6fe2-90c1-4ed1-af4b-b0b5cf226c83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268708170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1268708170
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3114629138
Short name T172
Test name
Test status
Simulation time 11944158151 ps
CPU time 25.62 seconds
Started Jul 21 06:26:15 PM PDT 24
Finished Jul 21 06:26:41 PM PDT 24
Peak memory 218348 kb
Host smart-101491bb-6eaa-4cb2-b564-c02895a6a2c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114629138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3114629138
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3612547315
Short name T271
Test name
Test status
Simulation time 1035151396 ps
CPU time 6.55 seconds
Started Jul 21 06:26:12 PM PDT 24
Finished Jul 21 06:26:19 PM PDT 24
Peak memory 217924 kb
Host smart-d16d7524-ead9-4f55-8515-54180c561173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612547315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3612547315
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1431730064
Short name T314
Test name
Test status
Simulation time 56853085 ps
CPU time 1.58 seconds
Started Jul 21 06:26:10 PM PDT 24
Finished Jul 21 06:26:12 PM PDT 24
Peak memory 217776 kb
Host smart-4d3c5f9b-997d-486f-8c66-9ed2422104c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431730064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1431730064
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1496193304
Short name T718
Test name
Test status
Simulation time 848745432 ps
CPU time 25.58 seconds
Started Jul 21 06:26:10 PM PDT 24
Finished Jul 21 06:26:36 PM PDT 24
Peak memory 245808 kb
Host smart-3f0416b9-5e35-470c-999a-2b48164d93c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496193304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1496193304
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3862734090
Short name T196
Test name
Test status
Simulation time 62553339 ps
CPU time 5.91 seconds
Started Jul 21 06:26:12 PM PDT 24
Finished Jul 21 06:26:19 PM PDT 24
Peak memory 242900 kb
Host smart-893f6901-0bb9-4d4b-a516-0706f74a5ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862734090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3862734090
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1625920226
Short name T334
Test name
Test status
Simulation time 11138143998 ps
CPU time 309.22 seconds
Started Jul 21 06:26:13 PM PDT 24
Finished Jul 21 06:31:23 PM PDT 24
Peak memory 219932 kb
Host smart-80d71e17-2ff1-4a64-b707-b1a009bf5848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625920226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1625920226
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2154574029
Short name T712
Test name
Test status
Simulation time 27240222752 ps
CPU time 871.43 seconds
Started Jul 21 06:26:10 PM PDT 24
Finished Jul 21 06:40:42 PM PDT 24
Peak memory 284048 kb
Host smart-e6307b61-4fd1-45f8-a566-0d8a4720803e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2154574029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2154574029
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3827637735
Short name T427
Test name
Test status
Simulation time 22264082 ps
CPU time 1.01 seconds
Started Jul 21 06:26:10 PM PDT 24
Finished Jul 21 06:26:12 PM PDT 24
Peak memory 211992 kb
Host smart-1618fd1d-1f0a-428d-b704-fac3247257c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827637735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3827637735
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1129577778
Short name T392
Test name
Test status
Simulation time 55974841 ps
CPU time 1.07 seconds
Started Jul 21 06:24:48 PM PDT 24
Finished Jul 21 06:24:50 PM PDT 24
Peak memory 208936 kb
Host smart-579bb873-b85e-467e-97af-36d477fed0cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129577778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1129577778
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3185804583
Short name T265
Test name
Test status
Simulation time 41075400 ps
CPU time 0.83 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:46 PM PDT 24
Peak memory 208716 kb
Host smart-48c2e6b9-e365-4119-b714-f317bb828c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185804583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3185804583
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1094225710
Short name T556
Test name
Test status
Simulation time 390955523 ps
CPU time 15.92 seconds
Started Jul 21 06:24:47 PM PDT 24
Finished Jul 21 06:25:03 PM PDT 24
Peak memory 218340 kb
Host smart-02541289-c158-4591-ad30-224277466c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094225710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1094225710
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3460110241
Short name T858
Test name
Test status
Simulation time 2147349835 ps
CPU time 13.97 seconds
Started Jul 21 06:24:45 PM PDT 24
Finished Jul 21 06:25:00 PM PDT 24
Peak memory 217576 kb
Host smart-b72c2293-70c2-4b24-8b1c-b81cc6cdc634
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460110241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3460110241
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2215887562
Short name T842
Test name
Test status
Simulation time 876284780 ps
CPU time 28.9 seconds
Started Jul 21 06:24:46 PM PDT 24
Finished Jul 21 06:25:15 PM PDT 24
Peak memory 218376 kb
Host smart-a3675667-f31a-452e-99c4-0fbb560840ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215887562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2215887562
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1364096652
Short name T225
Test name
Test status
Simulation time 494080859 ps
CPU time 3.2 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:48 PM PDT 24
Peak memory 217732 kb
Host smart-03efef8b-7fa8-4778-bab9-2aeccacf9647
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364096652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
364096652
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.617466244
Short name T497
Test name
Test status
Simulation time 873781391 ps
CPU time 6.68 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:51 PM PDT 24
Peak memory 218292 kb
Host smart-8a8d28f3-0b4f-43a7-951d-a9b7dcb5ed77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617466244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.617466244
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2778823822
Short name T839
Test name
Test status
Simulation time 797623446 ps
CPU time 22.01 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:25:07 PM PDT 24
Peak memory 217652 kb
Host smart-807e1493-6728-4d83-9498-a5a34edbb9cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778823822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2778823822
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3745914109
Short name T849
Test name
Test status
Simulation time 504812138 ps
CPU time 7.16 seconds
Started Jul 21 06:24:45 PM PDT 24
Finished Jul 21 06:24:53 PM PDT 24
Peak memory 217752 kb
Host smart-a61e0105-3703-462e-abef-5226c4b62f0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745914109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3745914109
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1155404679
Short name T850
Test name
Test status
Simulation time 13917253876 ps
CPU time 49.11 seconds
Started Jul 21 06:24:46 PM PDT 24
Finished Jul 21 06:25:35 PM PDT 24
Peak memory 267520 kb
Host smart-040419b0-5539-4674-a858-1c97f25a9410
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155404679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1155404679
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2297661869
Short name T551
Test name
Test status
Simulation time 452183828 ps
CPU time 6.69 seconds
Started Jul 21 06:24:43 PM PDT 24
Finished Jul 21 06:24:50 PM PDT 24
Peak memory 223024 kb
Host smart-783000a7-33b9-4773-98f7-1ed62d629c31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297661869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2297661869
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1012198191
Short name T575
Test name
Test status
Simulation time 30029035 ps
CPU time 1.75 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:46 PM PDT 24
Peak memory 218360 kb
Host smart-9cb419a9-18d9-4800-9d13-d5ffe3e33cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012198191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1012198191
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3031750768
Short name T406
Test name
Test status
Simulation time 241178058 ps
CPU time 6.44 seconds
Started Jul 21 06:24:48 PM PDT 24
Finished Jul 21 06:24:55 PM PDT 24
Peak memory 217752 kb
Host smart-890ed823-6ce0-4cbf-a59f-ed4dea9d6588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031750768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3031750768
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1019099738
Short name T52
Test name
Test status
Simulation time 250355538 ps
CPU time 43.94 seconds
Started Jul 21 06:24:43 PM PDT 24
Finished Jul 21 06:25:27 PM PDT 24
Peak memory 269080 kb
Host smart-c283669c-d898-4bc3-bb59-766c9da5e08f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019099738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1019099738
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.873807403
Short name T728
Test name
Test status
Simulation time 4259678665 ps
CPU time 17.5 seconds
Started Jul 21 06:24:43 PM PDT 24
Finished Jul 21 06:25:01 PM PDT 24
Peak memory 226184 kb
Host smart-599eebb5-0fb5-47d6-b334-8c10d660120f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873807403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.873807403
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1272171591
Short name T518
Test name
Test status
Simulation time 226897026 ps
CPU time 6.6 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:51 PM PDT 24
Peak memory 218368 kb
Host smart-b1759f24-ca53-4c5e-852d-6bb49d687eaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272171591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
272171591
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2130296589
Short name T162
Test name
Test status
Simulation time 1386235271 ps
CPU time 13.79 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:59 PM PDT 24
Peak memory 218416 kb
Host smart-5fd2554a-5d3f-4114-8229-85ccc81223a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130296589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2130296589
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1313424096
Short name T71
Test name
Test status
Simulation time 35923044 ps
CPU time 1.54 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:46 PM PDT 24
Peak memory 217816 kb
Host smart-6643af21-dbfe-4f47-87c8-0ccc53f3b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313424096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1313424096
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3545336182
Short name T195
Test name
Test status
Simulation time 305066470 ps
CPU time 31.55 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:25:12 PM PDT 24
Peak memory 251112 kb
Host smart-29e6acdd-ce6a-4b83-8772-818131e8c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545336182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3545336182
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1754523079
Short name T288
Test name
Test status
Simulation time 124346071 ps
CPU time 9.28 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:54 PM PDT 24
Peak memory 251116 kb
Host smart-f28b23ad-5be4-4604-9469-a43e9a4f6d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754523079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1754523079
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1254722837
Short name T65
Test name
Test status
Simulation time 284567574 ps
CPU time 8.99 seconds
Started Jul 21 06:24:43 PM PDT 24
Finished Jul 21 06:24:53 PM PDT 24
Peak memory 251124 kb
Host smart-50d9e609-6ab4-4a77-a091-eafb981be443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254722837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1254722837
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.862731275
Short name T674
Test name
Test status
Simulation time 51426736462 ps
CPU time 331.42 seconds
Started Jul 21 06:24:42 PM PDT 24
Finished Jul 21 06:30:14 PM PDT 24
Peak memory 277372 kb
Host smart-da68aa98-ce80-481f-a2e6-44c262e993c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=862731275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.862731275
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3422999252
Short name T316
Test name
Test status
Simulation time 20944589 ps
CPU time 0.96 seconds
Started Jul 21 06:24:40 PM PDT 24
Finished Jul 21 06:24:42 PM PDT 24
Peak memory 211900 kb
Host smart-5ac0e45f-a3ad-4935-ae9c-a5274c34a417
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422999252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3422999252
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1765078059
Short name T812
Test name
Test status
Simulation time 38742559 ps
CPU time 1.13 seconds
Started Jul 21 06:26:16 PM PDT 24
Finished Jul 21 06:26:17 PM PDT 24
Peak memory 209056 kb
Host smart-418ce824-0fe7-4a8e-b47c-477f60b9b2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765078059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1765078059
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2551143777
Short name T328
Test name
Test status
Simulation time 1343097605 ps
CPU time 15 seconds
Started Jul 21 06:26:16 PM PDT 24
Finished Jul 21 06:26:32 PM PDT 24
Peak memory 218424 kb
Host smart-b224e560-acd0-47e0-a2a3-65b8e5616774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551143777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2551143777
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1315405133
Short name T537
Test name
Test status
Simulation time 1129610816 ps
CPU time 7.34 seconds
Started Jul 21 06:26:18 PM PDT 24
Finished Jul 21 06:26:26 PM PDT 24
Peak memory 217496 kb
Host smart-9c397ad6-9d4c-464f-8448-293b0b1fb421
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315405133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1315405133
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1965093881
Short name T740
Test name
Test status
Simulation time 120974565 ps
CPU time 3.54 seconds
Started Jul 21 06:26:11 PM PDT 24
Finished Jul 21 06:26:15 PM PDT 24
Peak memory 218376 kb
Host smart-5548c895-b80f-4a47-a0f6-1dd43651d627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965093881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1965093881
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4058583995
Short name T749
Test name
Test status
Simulation time 3687135431 ps
CPU time 9.23 seconds
Started Jul 21 06:26:20 PM PDT 24
Finished Jul 21 06:26:30 PM PDT 24
Peak memory 226232 kb
Host smart-32335bbb-cf59-47c4-9de9-0d7cffdae0db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058583995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4058583995
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1539290515
Short name T595
Test name
Test status
Simulation time 626320893 ps
CPU time 13.39 seconds
Started Jul 21 06:26:18 PM PDT 24
Finished Jul 21 06:26:33 PM PDT 24
Peak memory 226064 kb
Host smart-389b54e9-3687-4239-b43b-bc301d12afee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539290515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1539290515
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.917176708
Short name T857
Test name
Test status
Simulation time 1599807779 ps
CPU time 14.67 seconds
Started Jul 21 06:26:17 PM PDT 24
Finished Jul 21 06:26:32 PM PDT 24
Peak memory 226080 kb
Host smart-3040faa4-3c0e-406c-b869-1f80bb70f550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917176708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.917176708
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2328644862
Short name T854
Test name
Test status
Simulation time 1498695855 ps
CPU time 6.41 seconds
Started Jul 21 06:26:18 PM PDT 24
Finished Jul 21 06:26:25 PM PDT 24
Peak memory 218436 kb
Host smart-2e8edda5-5c1c-4e4f-8448-8ec26736dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328644862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2328644862
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.437774678
Short name T290
Test name
Test status
Simulation time 108838772 ps
CPU time 3.54 seconds
Started Jul 21 06:26:11 PM PDT 24
Finished Jul 21 06:26:15 PM PDT 24
Peak memory 222872 kb
Host smart-e09bf071-389e-453d-a6c9-808434a38e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437774678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.437774678
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3969852265
Short name T250
Test name
Test status
Simulation time 299588664 ps
CPU time 29.14 seconds
Started Jul 21 06:26:18 PM PDT 24
Finished Jul 21 06:26:48 PM PDT 24
Peak memory 251108 kb
Host smart-f0e0ce78-08c2-4ec5-861e-51f9cbef7145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969852265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3969852265
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.696515559
Short name T495
Test name
Test status
Simulation time 249835147 ps
CPU time 9.59 seconds
Started Jul 21 06:26:13 PM PDT 24
Finished Jul 21 06:26:23 PM PDT 24
Peak memory 251088 kb
Host smart-962d6803-b8f7-4cc7-9fdd-eaedb1ef9b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696515559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.696515559
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.4026317068
Short name T829
Test name
Test status
Simulation time 4554079894 ps
CPU time 167.34 seconds
Started Jul 21 06:26:18 PM PDT 24
Finished Jul 21 06:29:07 PM PDT 24
Peak memory 251068 kb
Host smart-c20f2489-3978-47cb-ab65-fddd779c68e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026317068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.4026317068
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.710120966
Short name T273
Test name
Test status
Simulation time 20780507 ps
CPU time 0.98 seconds
Started Jul 21 06:26:10 PM PDT 24
Finished Jul 21 06:26:12 PM PDT 24
Peak memory 212956 kb
Host smart-9929fed8-3e9b-4e68-bcbb-b26f49ac3e28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710120966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.710120966
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3057812417
Short name T699
Test name
Test status
Simulation time 163261727 ps
CPU time 1.01 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:27 PM PDT 24
Peak memory 208968 kb
Host smart-0f3264d0-eeb5-4506-89e5-be16a2f88e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057812417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3057812417
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1420287362
Short name T689
Test name
Test status
Simulation time 3159780073 ps
CPU time 28.91 seconds
Started Jul 21 06:26:16 PM PDT 24
Finished Jul 21 06:26:45 PM PDT 24
Peak memory 219244 kb
Host smart-e6274e50-f157-4184-b3fd-6e2bba1c1448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420287362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1420287362
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.688466314
Short name T33
Test name
Test status
Simulation time 489737423 ps
CPU time 7.01 seconds
Started Jul 21 06:26:16 PM PDT 24
Finished Jul 21 06:26:24 PM PDT 24
Peak memory 217524 kb
Host smart-4952ed08-97c7-4f08-ab3c-4aa4ea2c8580
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688466314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.688466314
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2179986500
Short name T277
Test name
Test status
Simulation time 20294574 ps
CPU time 1.57 seconds
Started Jul 21 06:26:18 PM PDT 24
Finished Jul 21 06:26:20 PM PDT 24
Peak memory 218376 kb
Host smart-d94d0752-a55e-49f7-96ff-b5912f6ef468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179986500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2179986500
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.261830358
Short name T629
Test name
Test status
Simulation time 1652494119 ps
CPU time 15.52 seconds
Started Jul 21 06:26:21 PM PDT 24
Finished Jul 21 06:26:37 PM PDT 24
Peak memory 226168 kb
Host smart-95d05716-7257-493f-8f65-5d9eea98985e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261830358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.261830358
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3177677699
Short name T338
Test name
Test status
Simulation time 708717700 ps
CPU time 11.26 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:37 PM PDT 24
Peak memory 226000 kb
Host smart-ec34f341-3a75-4941-ad4c-d987cd6a2cad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177677699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3177677699
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.111543193
Short name T22
Test name
Test status
Simulation time 403085517 ps
CPU time 8.01 seconds
Started Jul 21 06:26:23 PM PDT 24
Finished Jul 21 06:26:32 PM PDT 24
Peak memory 226100 kb
Host smart-632d5855-26a7-4823-81bf-f640762b5135
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111543193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.111543193
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.844994905
Short name T39
Test name
Test status
Simulation time 883712200 ps
CPU time 9.31 seconds
Started Jul 21 06:26:16 PM PDT 24
Finished Jul 21 06:26:26 PM PDT 24
Peak memory 225104 kb
Host smart-f87d6de5-bc38-4248-b984-762420eca9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844994905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.844994905
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.772695499
Short name T468
Test name
Test status
Simulation time 19660130 ps
CPU time 1.52 seconds
Started Jul 21 06:26:18 PM PDT 24
Finished Jul 21 06:26:20 PM PDT 24
Peak memory 213736 kb
Host smart-41f4c27e-1c1c-4f3b-b2a3-b17735fd6fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772695499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.772695499
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1399949058
Short name T29
Test name
Test status
Simulation time 154855776 ps
CPU time 18.57 seconds
Started Jul 21 06:26:16 PM PDT 24
Finished Jul 21 06:26:35 PM PDT 24
Peak memory 251128 kb
Host smart-d3fd58b7-066e-468f-b442-da27b05503bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399949058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1399949058
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.645486840
Short name T694
Test name
Test status
Simulation time 66656686 ps
CPU time 8.43 seconds
Started Jul 21 06:26:15 PM PDT 24
Finished Jul 21 06:26:24 PM PDT 24
Peak memory 244048 kb
Host smart-b21c0f41-1262-4765-a768-c54e113fa831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645486840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.645486840
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.685814285
Short name T554
Test name
Test status
Simulation time 15258045229 ps
CPU time 174.63 seconds
Started Jul 21 06:26:26 PM PDT 24
Finished Jul 21 06:29:21 PM PDT 24
Peak memory 281644 kb
Host smart-aca92b10-2de4-4a99-aa99-54b25e115cc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685814285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.685814285
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2730180234
Short name T725
Test name
Test status
Simulation time 22327943 ps
CPU time 0.95 seconds
Started Jul 21 06:26:16 PM PDT 24
Finished Jul 21 06:26:17 PM PDT 24
Peak memory 217920 kb
Host smart-814ea4e0-05bd-493e-82a9-507e93395250
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730180234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2730180234
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1120841156
Short name T437
Test name
Test status
Simulation time 49575408 ps
CPU time 1.23 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:27 PM PDT 24
Peak memory 209120 kb
Host smart-444315cd-7471-4b01-b166-58033fbc507c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120841156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1120841156
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2706233047
Short name T605
Test name
Test status
Simulation time 932731163 ps
CPU time 17.2 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:43 PM PDT 24
Peak memory 218308 kb
Host smart-1eaf73fb-54dd-4561-8133-a62cfdcac27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706233047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2706233047
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.619179380
Short name T200
Test name
Test status
Simulation time 2790869895 ps
CPU time 8.48 seconds
Started Jul 21 06:26:26 PM PDT 24
Finished Jul 21 06:26:35 PM PDT 24
Peak memory 217852 kb
Host smart-69fe4214-99d0-4a0c-a45a-dddc3a19257e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619179380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.619179380
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2197912599
Short name T680
Test name
Test status
Simulation time 44584625 ps
CPU time 1.6 seconds
Started Jul 21 06:26:23 PM PDT 24
Finished Jul 21 06:26:25 PM PDT 24
Peak memory 218404 kb
Host smart-73c2991a-05b6-4076-9150-a767b04fe592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197912599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2197912599
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1507823214
Short name T457
Test name
Test status
Simulation time 6511388515 ps
CPU time 16.87 seconds
Started Jul 21 06:26:24 PM PDT 24
Finished Jul 21 06:26:42 PM PDT 24
Peak memory 226244 kb
Host smart-6001e551-00e4-4668-bf6e-4f41c72344f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507823214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1507823214
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2318673360
Short name T462
Test name
Test status
Simulation time 1112937078 ps
CPU time 12.38 seconds
Started Jul 21 06:26:30 PM PDT 24
Finished Jul 21 06:26:42 PM PDT 24
Peak memory 226044 kb
Host smart-66fca0ea-dac3-4371-8de8-07a63bc6a8b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318673360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2318673360
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4150328986
Short name T855
Test name
Test status
Simulation time 1426594214 ps
CPU time 13.3 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:40 PM PDT 24
Peak memory 218244 kb
Host smart-33245870-112b-41e1-9a1c-500643bea85c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150328986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4150328986
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1401878170
Short name T483
Test name
Test status
Simulation time 621018222 ps
CPU time 11.56 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:38 PM PDT 24
Peak memory 218488 kb
Host smart-5e728a4c-8e7f-42f5-b640-68cf6031a285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401878170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1401878170
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3815642649
Short name T501
Test name
Test status
Simulation time 455788004 ps
CPU time 6.27 seconds
Started Jul 21 06:26:23 PM PDT 24
Finished Jul 21 06:26:30 PM PDT 24
Peak memory 217744 kb
Host smart-e86fb6f3-c2bb-4bc1-9447-6c71a400b05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815642649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3815642649
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2496077997
Short name T747
Test name
Test status
Simulation time 554278012 ps
CPU time 28.52 seconds
Started Jul 21 06:26:24 PM PDT 24
Finished Jul 21 06:26:53 PM PDT 24
Peak memory 251112 kb
Host smart-1934774a-9a52-4fff-a965-7fbe31776c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496077997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2496077997
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.859184557
Short name T326
Test name
Test status
Simulation time 135646493 ps
CPU time 8.22 seconds
Started Jul 21 06:26:24 PM PDT 24
Finished Jul 21 06:26:34 PM PDT 24
Peak memory 251096 kb
Host smart-654f287b-54af-4685-ad65-e4888a1bea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859184557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.859184557
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2004364675
Short name T146
Test name
Test status
Simulation time 26045749832 ps
CPU time 637.81 seconds
Started Jul 21 06:26:26 PM PDT 24
Finished Jul 21 06:37:05 PM PDT 24
Peak memory 316016 kb
Host smart-5a38630f-d624-4cc6-afb5-a2e47dcfd0c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2004364675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2004364675
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2684418964
Short name T356
Test name
Test status
Simulation time 15577268 ps
CPU time 0.93 seconds
Started Jul 21 06:26:24 PM PDT 24
Finished Jul 21 06:26:26 PM PDT 24
Peak memory 211864 kb
Host smart-9ce10edb-b992-40f8-9a1f-6326e295a64e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684418964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2684418964
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1443043035
Short name T708
Test name
Test status
Simulation time 179469560 ps
CPU time 1.6 seconds
Started Jul 21 06:26:30 PM PDT 24
Finished Jul 21 06:26:32 PM PDT 24
Peak memory 209112 kb
Host smart-ff54fdc4-b12b-4205-8a75-aabbadfcff2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443043035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1443043035
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1917336596
Short name T275
Test name
Test status
Simulation time 527412167 ps
CPU time 13.58 seconds
Started Jul 21 06:26:26 PM PDT 24
Finished Jul 21 06:26:40 PM PDT 24
Peak memory 218392 kb
Host smart-85dcaed0-69df-4508-a138-038cdc6fd1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917336596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1917336596
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3487518812
Short name T34
Test name
Test status
Simulation time 503603672 ps
CPU time 6.73 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:33 PM PDT 24
Peak memory 217236 kb
Host smart-c4926cf6-d6a7-4904-81b7-703c3f303f8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487518812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3487518812
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1952782069
Short name T789
Test name
Test status
Simulation time 59465322 ps
CPU time 3.17 seconds
Started Jul 21 06:26:27 PM PDT 24
Finished Jul 21 06:26:31 PM PDT 24
Peak memory 218428 kb
Host smart-7ec2bf89-4535-431f-9973-a5db0310dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952782069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1952782069
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2800078905
Short name T524
Test name
Test status
Simulation time 2453297481 ps
CPU time 18.19 seconds
Started Jul 21 06:26:24 PM PDT 24
Finished Jul 21 06:26:43 PM PDT 24
Peak memory 226248 kb
Host smart-52bea192-172e-4377-a194-be4d4a3c5479
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800078905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2800078905
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2711702515
Short name T569
Test name
Test status
Simulation time 3049676790 ps
CPU time 12.3 seconds
Started Jul 21 06:26:34 PM PDT 24
Finished Jul 21 06:26:47 PM PDT 24
Peak memory 226108 kb
Host smart-06918b84-3209-4456-885f-a54d4c0a84aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711702515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2711702515
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3890036652
Short name T399
Test name
Test status
Simulation time 198216733 ps
CPU time 6.85 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:33 PM PDT 24
Peak memory 218248 kb
Host smart-35438312-5c91-4a12-a913-ae20142c8758
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890036652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3890036652
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2693308703
Short name T23
Test name
Test status
Simulation time 215791362 ps
CPU time 6.87 seconds
Started Jul 21 06:26:27 PM PDT 24
Finished Jul 21 06:26:35 PM PDT 24
Peak memory 218556 kb
Host smart-3abede53-1b3b-4d88-989f-b14bd5898acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693308703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2693308703
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.186371989
Short name T74
Test name
Test status
Simulation time 88755167 ps
CPU time 1.58 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:28 PM PDT 24
Peak memory 217820 kb
Host smart-08bd1194-1305-4c42-be9c-1be58d1d35e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186371989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.186371989
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2174812465
Short name T628
Test name
Test status
Simulation time 1144651223 ps
CPU time 27.96 seconds
Started Jul 21 06:26:24 PM PDT 24
Finished Jul 21 06:26:53 PM PDT 24
Peak memory 251140 kb
Host smart-02190366-33f0-42b0-ba2c-018d41015c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174812465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2174812465
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3724741103
Short name T668
Test name
Test status
Simulation time 53768623 ps
CPU time 7.8 seconds
Started Jul 21 06:26:25 PM PDT 24
Finished Jul 21 06:26:34 PM PDT 24
Peak memory 251116 kb
Host smart-33e2b5c3-3bde-4051-b8ac-4285c479b5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724741103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3724741103
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2222553290
Short name T815
Test name
Test status
Simulation time 5918523861 ps
CPU time 191.57 seconds
Started Jul 21 06:26:33 PM PDT 24
Finished Jul 21 06:29:45 PM PDT 24
Peak memory 251072 kb
Host smart-081ea63f-bf50-4dc0-8741-43b1a87342b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222553290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2222553290
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2816835586
Short name T835
Test name
Test status
Simulation time 13815456 ps
CPU time 0.92 seconds
Started Jul 21 06:26:22 PM PDT 24
Finished Jul 21 06:26:23 PM PDT 24
Peak memory 211872 kb
Host smart-94a536f0-e109-405a-bf2e-e8796d8cb31b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816835586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2816835586
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3129784893
Short name T636
Test name
Test status
Simulation time 18511733 ps
CPU time 1.17 seconds
Started Jul 21 06:26:34 PM PDT 24
Finished Jul 21 06:26:36 PM PDT 24
Peak memory 209060 kb
Host smart-48623396-432f-44ec-b0f0-89b8648e20da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129784893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3129784893
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2054274738
Short name T622
Test name
Test status
Simulation time 3502364745 ps
CPU time 19.22 seconds
Started Jul 21 06:26:30 PM PDT 24
Finished Jul 21 06:26:50 PM PDT 24
Peak memory 219084 kb
Host smart-f33cc5e6-9611-4dec-bb79-76f9e8f54ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054274738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2054274738
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3593806172
Short name T369
Test name
Test status
Simulation time 538327354 ps
CPU time 3.94 seconds
Started Jul 21 06:26:30 PM PDT 24
Finished Jul 21 06:26:34 PM PDT 24
Peak memory 217268 kb
Host smart-5d0da7e9-d7ee-4580-be69-0acb77899926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593806172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3593806172
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.22861093
Short name T561
Test name
Test status
Simulation time 64562203 ps
CPU time 2.86 seconds
Started Jul 21 06:26:34 PM PDT 24
Finished Jul 21 06:26:38 PM PDT 24
Peak memory 218512 kb
Host smart-0648baa1-6c34-4cbf-a67c-c3ed85660114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22861093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.22861093
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1401772295
Short name T553
Test name
Test status
Simulation time 1540320939 ps
CPU time 14.13 seconds
Started Jul 21 06:26:33 PM PDT 24
Finished Jul 21 06:26:48 PM PDT 24
Peak memory 226156 kb
Host smart-f615d440-6b7f-4448-98ba-2e86269290a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401772295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1401772295
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.4290503341
Short name T466
Test name
Test status
Simulation time 847353604 ps
CPU time 6.7 seconds
Started Jul 21 06:26:32 PM PDT 24
Finished Jul 21 06:26:40 PM PDT 24
Peak memory 226136 kb
Host smart-06105ec2-3b46-496c-bc21-7a85a19a4fe1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290503341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.4290503341
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2011549437
Short name T278
Test name
Test status
Simulation time 237232495 ps
CPU time 9.61 seconds
Started Jul 21 06:26:33 PM PDT 24
Finished Jul 21 06:26:43 PM PDT 24
Peak memory 218352 kb
Host smart-8a278c10-ac5e-4358-a5ae-6b92b2e6f725
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011549437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2011549437
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.127779589
Short name T761
Test name
Test status
Simulation time 630605874 ps
CPU time 6.89 seconds
Started Jul 21 06:26:30 PM PDT 24
Finished Jul 21 06:26:38 PM PDT 24
Peak memory 225144 kb
Host smart-ec4debf9-2cab-45b2-a51c-eebe69831104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127779589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.127779589
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2766494634
Short name T543
Test name
Test status
Simulation time 320095140 ps
CPU time 3.76 seconds
Started Jul 21 06:26:32 PM PDT 24
Finished Jul 21 06:26:36 PM PDT 24
Peak memory 217856 kb
Host smart-030abce7-d5e4-479b-a841-c249b9cfcb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766494634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2766494634
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1977504822
Short name T255
Test name
Test status
Simulation time 228431515 ps
CPU time 26.02 seconds
Started Jul 21 06:26:37 PM PDT 24
Finished Jul 21 06:27:03 PM PDT 24
Peak memory 251100 kb
Host smart-a0d79714-92ab-4adb-8aa0-1451c07a281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977504822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1977504822
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2346910811
Short name T601
Test name
Test status
Simulation time 162533292 ps
CPU time 9.27 seconds
Started Jul 21 06:26:30 PM PDT 24
Finished Jul 21 06:26:40 PM PDT 24
Peak memory 251088 kb
Host smart-b820461a-1bdf-409d-ae41-34e4323a3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346910811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2346910811
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3402803686
Short name T603
Test name
Test status
Simulation time 4958554672 ps
CPU time 65.86 seconds
Started Jul 21 06:26:31 PM PDT 24
Finished Jul 21 06:27:37 PM PDT 24
Peak memory 274196 kb
Host smart-e0ac6bd2-4982-44aa-83f3-27499b78817c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402803686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3402803686
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2359015333
Short name T624
Test name
Test status
Simulation time 12779097 ps
CPU time 1.04 seconds
Started Jul 21 06:26:32 PM PDT 24
Finished Jul 21 06:26:34 PM PDT 24
Peak memory 211908 kb
Host smart-d8a8799f-da63-48c2-850b-90d3eaaa60eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359015333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2359015333
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.407113338
Short name T602
Test name
Test status
Simulation time 14426500 ps
CPU time 0.84 seconds
Started Jul 21 06:26:31 PM PDT 24
Finished Jul 21 06:26:32 PM PDT 24
Peak memory 208752 kb
Host smart-6a3bd7fd-fb3a-47e4-b23f-77b2676362c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407113338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.407113338
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.419842749
Short name T657
Test name
Test status
Simulation time 2011002388 ps
CPU time 12.47 seconds
Started Jul 21 06:26:32 PM PDT 24
Finished Jul 21 06:26:45 PM PDT 24
Peak memory 218376 kb
Host smart-392b0fb7-f606-48de-bd4e-c49fa9b5a76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419842749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.419842749
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3282141797
Short name T803
Test name
Test status
Simulation time 156776811 ps
CPU time 1.59 seconds
Started Jul 21 06:26:29 PM PDT 24
Finished Jul 21 06:26:31 PM PDT 24
Peak memory 217256 kb
Host smart-50d93ae7-0d25-46f8-a3f1-01b303ca6dcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282141797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3282141797
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2071089587
Short name T659
Test name
Test status
Simulation time 259607168 ps
CPU time 2.69 seconds
Started Jul 21 06:26:31 PM PDT 24
Finished Jul 21 06:26:34 PM PDT 24
Peak memory 218272 kb
Host smart-3aa76c52-25c2-457b-8507-e61e7ecf4049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071089587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2071089587
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3851100665
Short name T353
Test name
Test status
Simulation time 917561611 ps
CPU time 9.72 seconds
Started Jul 21 06:26:34 PM PDT 24
Finished Jul 21 06:26:44 PM PDT 24
Peak memory 226164 kb
Host smart-e94799c1-6f2d-4bb8-b02f-dfbe1baf6d87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851100665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3851100665
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3464448150
Short name T650
Test name
Test status
Simulation time 510084702 ps
CPU time 11.6 seconds
Started Jul 21 06:26:33 PM PDT 24
Finished Jul 21 06:26:45 PM PDT 24
Peak memory 226100 kb
Host smart-4a0d98ca-bc92-48c7-a049-9bb40e306bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464448150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3464448150
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2998023441
Short name T16
Test name
Test status
Simulation time 3546070862 ps
CPU time 16.49 seconds
Started Jul 21 06:26:31 PM PDT 24
Finished Jul 21 06:26:49 PM PDT 24
Peak memory 218404 kb
Host smart-91d10190-854c-49fd-bb80-167a59be5fd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998023441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2998023441
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.781046068
Short name T491
Test name
Test status
Simulation time 187375410 ps
CPU time 1.57 seconds
Started Jul 21 06:26:31 PM PDT 24
Finished Jul 21 06:26:34 PM PDT 24
Peak memory 217800 kb
Host smart-f7cf179d-1426-4c7b-acc3-796c552daa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781046068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.781046068
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.367734986
Short name T461
Test name
Test status
Simulation time 964921847 ps
CPU time 16.23 seconds
Started Jul 21 06:26:34 PM PDT 24
Finished Jul 21 06:26:51 PM PDT 24
Peak memory 251120 kb
Host smart-bc63e7bc-9bfd-491d-994c-92f05e6df8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367734986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.367734986
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.657761999
Short name T617
Test name
Test status
Simulation time 117601023 ps
CPU time 8.01 seconds
Started Jul 21 06:26:33 PM PDT 24
Finished Jul 21 06:26:42 PM PDT 24
Peak memory 251104 kb
Host smart-7027a659-aba7-48f6-af0c-59468f8729be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657761999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.657761999
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2325390901
Short name T164
Test name
Test status
Simulation time 16672059594 ps
CPU time 141.93 seconds
Started Jul 21 06:26:31 PM PDT 24
Finished Jul 21 06:28:53 PM PDT 24
Peak memory 284004 kb
Host smart-71f7175d-8d69-4741-9022-4420998abf8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325390901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2325390901
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1690710556
Short name T726
Test name
Test status
Simulation time 30164804613 ps
CPU time 518.21 seconds
Started Jul 21 06:26:33 PM PDT 24
Finished Jul 21 06:35:12 PM PDT 24
Peak memory 333156 kb
Host smart-98f6a3b6-8cad-4c36-9cbc-56afb677b8c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1690710556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1690710556
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3397293034
Short name T383
Test name
Test status
Simulation time 30198708 ps
CPU time 0.91 seconds
Started Jul 21 06:26:32 PM PDT 24
Finished Jul 21 06:26:34 PM PDT 24
Peak memory 211856 kb
Host smart-1758bb89-f29d-4218-be76-b7ee0fb16ba2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397293034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3397293034
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.844748936
Short name T502
Test name
Test status
Simulation time 19086889 ps
CPU time 0.96 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:26:44 PM PDT 24
Peak memory 209072 kb
Host smart-2cefe033-68df-46ba-88f9-1760f00f21d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844748936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.844748936
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.571108203
Short name T816
Test name
Test status
Simulation time 168041658 ps
CPU time 8.56 seconds
Started Jul 21 06:26:47 PM PDT 24
Finished Jul 21 06:26:58 PM PDT 24
Peak memory 218312 kb
Host smart-45c97df4-b00d-4b6d-9325-0f93b24331c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571108203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.571108203
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2907116164
Short name T599
Test name
Test status
Simulation time 6680822603 ps
CPU time 10.54 seconds
Started Jul 21 06:26:38 PM PDT 24
Finished Jul 21 06:26:49 PM PDT 24
Peak memory 217812 kb
Host smart-0eec188b-addb-4fac-afcb-3664766cf5bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907116164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2907116164
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.81993027
Short name T266
Test name
Test status
Simulation time 117355805 ps
CPU time 1.92 seconds
Started Jul 21 06:26:37 PM PDT 24
Finished Jul 21 06:26:40 PM PDT 24
Peak memory 218452 kb
Host smart-83de780f-3fc5-4e38-859c-c8490b0a76c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81993027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.81993027
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.165448469
Short name T362
Test name
Test status
Simulation time 183409554 ps
CPU time 10.17 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:26:54 PM PDT 24
Peak memory 225404 kb
Host smart-30048144-ef11-494f-be84-bf015c49fb51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165448469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.165448469
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2050276559
Short name T431
Test name
Test status
Simulation time 1682230891 ps
CPU time 10.87 seconds
Started Jul 21 06:26:36 PM PDT 24
Finished Jul 21 06:26:48 PM PDT 24
Peak memory 226164 kb
Host smart-88bc6f06-1747-46f7-8f26-a5fcb5384efc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050276559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2050276559
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4148222032
Short name T707
Test name
Test status
Simulation time 221942515 ps
CPU time 8.14 seconds
Started Jul 21 06:26:39 PM PDT 24
Finished Jul 21 06:26:48 PM PDT 24
Peak memory 218256 kb
Host smart-1e5bcf18-23d0-409a-b8df-3b1f0ae8753c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148222032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
4148222032
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1266943885
Short name T525
Test name
Test status
Simulation time 4433079671 ps
CPU time 11.49 seconds
Started Jul 21 06:26:38 PM PDT 24
Finished Jul 21 06:26:50 PM PDT 24
Peak memory 218492 kb
Host smart-4277ced7-1fe8-4a0e-9829-cc6ae33a8f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266943885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1266943885
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.964357539
Short name T378
Test name
Test status
Simulation time 245068419 ps
CPU time 2.49 seconds
Started Jul 21 06:26:34 PM PDT 24
Finished Jul 21 06:26:38 PM PDT 24
Peak memory 222680 kb
Host smart-2eff1a73-ca68-4f39-8c11-5f237a05c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964357539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.964357539
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2853234720
Short name T235
Test name
Test status
Simulation time 1184866084 ps
CPU time 30.62 seconds
Started Jul 21 06:26:37 PM PDT 24
Finished Jul 21 06:27:09 PM PDT 24
Peak memory 247232 kb
Host smart-c2badeb5-ea0f-4512-bd54-77f124be891e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853234720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2853234720
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4056331612
Short name T261
Test name
Test status
Simulation time 35601480 ps
CPU time 6.08 seconds
Started Jul 21 06:26:42 PM PDT 24
Finished Jul 21 06:26:50 PM PDT 24
Peak memory 244660 kb
Host smart-78d923c5-4870-4646-9e55-f56aa169c91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056331612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4056331612
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1108071402
Short name T762
Test name
Test status
Simulation time 6523041090 ps
CPU time 180.35 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:29:44 PM PDT 24
Peak memory 268312 kb
Host smart-69589a72-30f4-412b-ac52-9b67f2e844bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108071402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1108071402
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1774747296
Short name T237
Test name
Test status
Simulation time 14400342 ps
CPU time 0.89 seconds
Started Jul 21 06:26:37 PM PDT 24
Finished Jul 21 06:26:39 PM PDT 24
Peak memory 211968 kb
Host smart-8e470d15-d48f-46bc-8192-ae5eeb7fb559
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774747296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1774747296
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1730305455
Short name T385
Test name
Test status
Simulation time 22869919 ps
CPU time 1.28 seconds
Started Jul 21 06:26:36 PM PDT 24
Finished Jul 21 06:26:39 PM PDT 24
Peak memory 209104 kb
Host smart-01830942-7e22-4b9e-9839-0f99ae378df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730305455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1730305455
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3884279997
Short name T669
Test name
Test status
Simulation time 1465331605 ps
CPU time 12.62 seconds
Started Jul 21 06:26:38 PM PDT 24
Finished Jul 21 06:26:52 PM PDT 24
Peak memory 226124 kb
Host smart-9e93fea7-06c4-411b-8efa-be7d190df2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884279997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3884279997
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.619314816
Short name T813
Test name
Test status
Simulation time 113287943 ps
CPU time 1.78 seconds
Started Jul 21 06:26:39 PM PDT 24
Finished Jul 21 06:26:42 PM PDT 24
Peak memory 217156 kb
Host smart-04edf816-d671-4cf3-8578-f8938509b031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619314816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.619314816
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2780391830
Short name T681
Test name
Test status
Simulation time 85426042 ps
CPU time 1.75 seconds
Started Jul 21 06:26:36 PM PDT 24
Finished Jul 21 06:26:38 PM PDT 24
Peak memory 218296 kb
Host smart-1815ec6b-7bf4-468c-879d-4eb15c6b0d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780391830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2780391830
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2392745372
Short name T717
Test name
Test status
Simulation time 3628531480 ps
CPU time 15.22 seconds
Started Jul 21 06:26:37 PM PDT 24
Finished Jul 21 06:26:53 PM PDT 24
Peak memory 226192 kb
Host smart-576e182b-083b-4d48-bd1d-6d4bd0615f59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392745372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2392745372
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2345430258
Short name T181
Test name
Test status
Simulation time 384112261 ps
CPU time 9.03 seconds
Started Jul 21 06:26:39 PM PDT 24
Finished Jul 21 06:26:49 PM PDT 24
Peak memory 218300 kb
Host smart-7a151839-4b4e-4e4c-988f-f396be7bb3c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345430258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2345430258
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3041896483
Short name T54
Test name
Test status
Simulation time 318546088 ps
CPU time 8.99 seconds
Started Jul 21 06:26:37 PM PDT 24
Finished Jul 21 06:26:47 PM PDT 24
Peak memory 226196 kb
Host smart-d29c7941-bbb6-4c4d-9924-b41e930e2d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041896483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3041896483
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.513165545
Short name T66
Test name
Test status
Simulation time 57833886 ps
CPU time 2.67 seconds
Started Jul 21 06:26:40 PM PDT 24
Finished Jul 21 06:26:43 PM PDT 24
Peak memory 217780 kb
Host smart-1f4b5d6b-5677-42d5-b797-efc30e69ba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513165545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.513165545
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1577998316
Short name T576
Test name
Test status
Simulation time 900203076 ps
CPU time 23.34 seconds
Started Jul 21 06:26:42 PM PDT 24
Finished Jul 21 06:27:07 PM PDT 24
Peak memory 246396 kb
Host smart-56695668-e41b-4b26-beef-32094c48a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577998316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1577998316
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1742872126
Short name T515
Test name
Test status
Simulation time 121905134 ps
CPU time 6.93 seconds
Started Jul 21 06:26:39 PM PDT 24
Finished Jul 21 06:26:46 PM PDT 24
Peak memory 243628 kb
Host smart-d917b460-19d8-4b0e-8d43-c12f8a24a326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742872126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1742872126
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2309844774
Short name T57
Test name
Test status
Simulation time 2999420641 ps
CPU time 83.96 seconds
Started Jul 21 06:26:38 PM PDT 24
Finished Jul 21 06:28:03 PM PDT 24
Peak memory 251136 kb
Host smart-e7786883-fc5a-47f8-804b-dccc3c504871
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309844774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2309844774
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.4196968239
Short name T176
Test name
Test status
Simulation time 37251137 ps
CPU time 0.97 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:26:44 PM PDT 24
Peak memory 208928 kb
Host smart-c5c5ee3b-f418-42ab-874a-64c920ed9e76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196968239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.4196968239
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1062408758
Short name T238
Test name
Test status
Simulation time 223369395 ps
CPU time 10.1 seconds
Started Jul 21 06:26:40 PM PDT 24
Finished Jul 21 06:26:51 PM PDT 24
Peak memory 218396 kb
Host smart-b5957e54-b8aa-4c2c-8670-18003648fa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062408758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1062408758
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3136404319
Short name T614
Test name
Test status
Simulation time 1613933713 ps
CPU time 9.6 seconds
Started Jul 21 06:26:39 PM PDT 24
Finished Jul 21 06:26:50 PM PDT 24
Peak memory 217428 kb
Host smart-63a53c52-f101-4ff9-833c-52a4200899ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136404319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3136404319
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1892951991
Short name T618
Test name
Test status
Simulation time 135857850 ps
CPU time 2.66 seconds
Started Jul 21 06:26:40 PM PDT 24
Finished Jul 21 06:26:43 PM PDT 24
Peak memory 218384 kb
Host smart-f74b1c3b-ebcd-483f-9d1e-9308ad203b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892951991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1892951991
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3414134316
Short name T593
Test name
Test status
Simulation time 274059050 ps
CPU time 13.5 seconds
Started Jul 21 06:26:38 PM PDT 24
Finished Jul 21 06:26:53 PM PDT 24
Peak memory 226120 kb
Host smart-107e630e-fa4c-44fe-be02-1f062cf87f91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414134316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3414134316
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.56420092
Short name T560
Test name
Test status
Simulation time 1336625392 ps
CPU time 16.23 seconds
Started Jul 21 06:26:39 PM PDT 24
Finished Jul 21 06:26:56 PM PDT 24
Peak memory 226060 kb
Host smart-5237623f-267a-44ad-95c8-ebfc731e6d19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56420092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_dig
est.56420092
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2264640793
Short name T424
Test name
Test status
Simulation time 4724201799 ps
CPU time 8.93 seconds
Started Jul 21 06:26:47 PM PDT 24
Finished Jul 21 06:26:57 PM PDT 24
Peak memory 226108 kb
Host smart-bcbcc932-d60b-4297-8e7a-27fade9b06e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264640793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2264640793
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.502275873
Short name T741
Test name
Test status
Simulation time 821551795 ps
CPU time 7.85 seconds
Started Jul 21 06:26:37 PM PDT 24
Finished Jul 21 06:26:46 PM PDT 24
Peak memory 225100 kb
Host smart-26e06252-5cf6-458a-be4b-aef351cc3ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502275873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.502275873
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.344404491
Short name T357
Test name
Test status
Simulation time 387562703 ps
CPU time 5.02 seconds
Started Jul 21 06:26:38 PM PDT 24
Finished Jul 21 06:26:44 PM PDT 24
Peak memory 217736 kb
Host smart-9d28a42e-bbfc-47e1-a052-bb90d5c8dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344404491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.344404491
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1699978963
Short name T621
Test name
Test status
Simulation time 732204896 ps
CPU time 21.47 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:27:11 PM PDT 24
Peak memory 251048 kb
Host smart-a0f0dd24-79e6-46bc-a547-ec91fadd89af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699978963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1699978963
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1746890482
Short name T241
Test name
Test status
Simulation time 301191669 ps
CPU time 6.34 seconds
Started Jul 21 06:26:38 PM PDT 24
Finished Jul 21 06:26:45 PM PDT 24
Peak memory 247040 kb
Host smart-889d6bb0-7873-4192-bff7-5f227746f0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746890482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1746890482
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1893220070
Short name T611
Test name
Test status
Simulation time 13218481324 ps
CPU time 250.84 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:30:54 PM PDT 24
Peak memory 226380 kb
Host smart-211d2f19-7c98-41e7-a451-e098f0427919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893220070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1893220070
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3357382984
Short name T93
Test name
Test status
Simulation time 136595617234 ps
CPU time 1228.75 seconds
Started Jul 21 06:26:42 PM PDT 24
Finished Jul 21 06:47:12 PM PDT 24
Peak memory 496840 kb
Host smart-ce3785d5-034c-4507-83ec-ccee43c6b20c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3357382984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3357382984
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3760848035
Short name T716
Test name
Test status
Simulation time 38375258 ps
CPU time 1 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:26:44 PM PDT 24
Peak memory 211892 kb
Host smart-8b48b058-2219-477e-9f4f-b32992dcf5a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760848035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3760848035
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.747687588
Short name T398
Test name
Test status
Simulation time 25894663 ps
CPU time 0.82 seconds
Started Jul 21 06:26:45 PM PDT 24
Finished Jul 21 06:26:47 PM PDT 24
Peak memory 208940 kb
Host smart-58f1b9a2-3964-4ea6-99ea-a82e3b027e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747687588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.747687588
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3868428332
Short name T833
Test name
Test status
Simulation time 558779149 ps
CPU time 12.78 seconds
Started Jul 21 06:26:38 PM PDT 24
Finished Jul 21 06:26:51 PM PDT 24
Peak memory 218252 kb
Host smart-47bcb3ec-1b11-471c-8cf5-97a335cf63a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868428332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3868428332
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1018275182
Short name T814
Test name
Test status
Simulation time 497015647 ps
CPU time 2.14 seconds
Started Jul 21 06:26:44 PM PDT 24
Finished Jul 21 06:26:47 PM PDT 24
Peak memory 217244 kb
Host smart-4289c347-9a4e-4250-a3c1-d0c54d6b1855
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018275182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1018275182
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2955885943
Short name T633
Test name
Test status
Simulation time 41414518 ps
CPU time 1.39 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:26:51 PM PDT 24
Peak memory 218300 kb
Host smart-669647d2-475e-4215-b9d8-f186820b8406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955885943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2955885943
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.80325722
Short name T714
Test name
Test status
Simulation time 4057398631 ps
CPU time 12.02 seconds
Started Jul 21 06:26:42 PM PDT 24
Finished Jul 21 06:26:56 PM PDT 24
Peak memory 226216 kb
Host smart-2fbb6f58-2d70-42b7-a1c9-3991f4c212b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80325722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.80325722
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2926700686
Short name T388
Test name
Test status
Simulation time 3138192979 ps
CPU time 26.14 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:27:15 PM PDT 24
Peak memory 226180 kb
Host smart-c526da09-2be3-48ac-a0b0-172dc277541e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926700686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2926700686
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.4224711048
Short name T866
Test name
Test status
Simulation time 1216789931 ps
CPU time 9.25 seconds
Started Jul 21 06:26:47 PM PDT 24
Finished Jul 21 06:26:58 PM PDT 24
Peak memory 218328 kb
Host smart-0a234433-5750-4875-a167-ced3f720fc94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224711048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
4224711048
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3000763848
Short name T51
Test name
Test status
Simulation time 275993971 ps
CPU time 8.11 seconds
Started Jul 21 06:26:42 PM PDT 24
Finished Jul 21 06:26:52 PM PDT 24
Peak memory 226176 kb
Host smart-f9003070-3cda-42c6-8780-4f9a4245fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000763848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3000763848
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1815409701
Short name T781
Test name
Test status
Simulation time 83571703 ps
CPU time 2.38 seconds
Started Jul 21 06:26:39 PM PDT 24
Finished Jul 21 06:26:42 PM PDT 24
Peak memory 217788 kb
Host smart-b9561b4b-7c6e-479d-8466-78fb154bd3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815409701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1815409701
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.110643463
Short name T754
Test name
Test status
Simulation time 395855671 ps
CPU time 29.07 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:27:19 PM PDT 24
Peak memory 251048 kb
Host smart-f3f6b3c2-230f-413d-a27f-a500086f6179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110643463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.110643463
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.602121439
Short name T366
Test name
Test status
Simulation time 1040122834 ps
CPU time 8.38 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:26:58 PM PDT 24
Peak memory 251172 kb
Host smart-282a3af7-c3e2-412e-ae10-02926d5e21ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602121439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.602121439
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1584326429
Short name T527
Test name
Test status
Simulation time 61298220193 ps
CPU time 539.12 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:35:52 PM PDT 24
Peak memory 269988 kb
Host smart-456d29e7-81af-4102-9e0f-efc0adb03abe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584326429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1584326429
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3218457645
Short name T193
Test name
Test status
Simulation time 21061898 ps
CPU time 0.92 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:26:42 PM PDT 24
Peak memory 211964 kb
Host smart-9b534f60-ce65-453b-b44d-e5aadde969d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218457645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3218457645
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2346743428
Short name T790
Test name
Test status
Simulation time 17945184 ps
CPU time 1.14 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:02 PM PDT 24
Peak memory 209000 kb
Host smart-6fb39fdd-6b62-4f4f-b6fb-274a3cbbd229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346743428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2346743428
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3205257100
Short name T514
Test name
Test status
Simulation time 176521546 ps
CPU time 7.6 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:12 PM PDT 24
Peak memory 226128 kb
Host smart-d98c6f65-539f-4195-9a41-01859652a194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205257100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3205257100
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1696717340
Short name T753
Test name
Test status
Simulation time 450952700 ps
CPU time 9.2 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 217464 kb
Host smart-c29df304-73b5-4251-aed9-ae5e057ea438
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696717340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1696717340
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1000230537
Short name T653
Test name
Test status
Simulation time 2470612635 ps
CPU time 67.31 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:26:09 PM PDT 24
Peak memory 218976 kb
Host smart-6a285156-6d24-48f7-a372-2db93baf5776
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000230537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1000230537
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1603491032
Short name T358
Test name
Test status
Simulation time 1637993782 ps
CPU time 11.39 seconds
Started Jul 21 06:24:56 PM PDT 24
Finished Jul 21 06:25:10 PM PDT 24
Peak memory 217876 kb
Host smart-14efb688-9fcd-41a2-bb3b-8de32c48f584
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603491032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
603491032
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.384269430
Short name T363
Test name
Test status
Simulation time 301708196 ps
CPU time 3 seconds
Started Jul 21 06:24:54 PM PDT 24
Finished Jul 21 06:24:58 PM PDT 24
Peak memory 218336 kb
Host smart-d50dc7f9-ea08-46c0-adcb-563d0fb1bef2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384269430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.384269430
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2153776817
Short name T566
Test name
Test status
Simulation time 668202428 ps
CPU time 8.77 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:10 PM PDT 24
Peak memory 217676 kb
Host smart-204e64cb-ca99-4b6f-acbe-d5aca8ee7dd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153776817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2153776817
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1684599996
Short name T375
Test name
Test status
Simulation time 47468114 ps
CPU time 1.41 seconds
Started Jul 21 06:24:54 PM PDT 24
Finished Jul 21 06:24:56 PM PDT 24
Peak memory 217728 kb
Host smart-227f79a6-5a92-4d71-bfbd-689c2712b7ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684599996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1684599996
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.4239521128
Short name T748
Test name
Test status
Simulation time 1156926634 ps
CPU time 36.08 seconds
Started Jul 21 06:24:56 PM PDT 24
Finished Jul 21 06:25:34 PM PDT 24
Peak memory 267532 kb
Host smart-cf9d291e-fa71-4896-8916-c6e74835fda9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239521128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.4239521128
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2440326132
Short name T163
Test name
Test status
Simulation time 424542844 ps
CPU time 8.05 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:04 PM PDT 24
Peak memory 223300 kb
Host smart-7889b635-3586-4bf7-9aff-c9a5c996d93d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440326132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2440326132
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3390620217
Short name T30
Test name
Test status
Simulation time 53803832 ps
CPU time 2.13 seconds
Started Jul 21 06:24:56 PM PDT 24
Finished Jul 21 06:25:00 PM PDT 24
Peak memory 222256 kb
Host smart-68a9a0e2-d868-4526-9ff4-564eade36085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390620217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3390620217
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2947894468
Short name T710
Test name
Test status
Simulation time 623977259 ps
CPU time 11.03 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 214724 kb
Host smart-96565e16-faba-424e-bacd-64195a5ff691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947894468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2947894468
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2129542688
Short name T90
Test name
Test status
Simulation time 912195533 ps
CPU time 20.85 seconds
Started Jul 21 06:24:54 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 281548 kb
Host smart-72f175ae-6438-4aa0-b316-291c1f07bcec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129542688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2129542688
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.570288901
Short name T404
Test name
Test status
Simulation time 5330644366 ps
CPU time 15.3 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 226244 kb
Host smart-cd1f2907-ef9e-4a87-93bb-f38b6f0dcdb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570288901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.570288901
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2579946317
Short name T853
Test name
Test status
Simulation time 332536158 ps
CPU time 9.79 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:06 PM PDT 24
Peak memory 226144 kb
Host smart-fd0233b3-0d69-4383-ba10-d6ffbcceb81e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579946317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2579946317
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3593075020
Short name T784
Test name
Test status
Simulation time 828762326 ps
CPU time 10.19 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:06 PM PDT 24
Peak memory 218320 kb
Host smart-c857b370-08db-42ef-93ca-76b4ef031143
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593075020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
593075020
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3323401586
Short name T547
Test name
Test status
Simulation time 2091444322 ps
CPU time 14.95 seconds
Started Jul 21 06:24:54 PM PDT 24
Finished Jul 21 06:25:10 PM PDT 24
Peak memory 218428 kb
Host smart-c7deab80-b13a-478c-91ea-eb74cba8518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323401586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3323401586
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3950115375
Short name T73
Test name
Test status
Simulation time 196339213 ps
CPU time 2.36 seconds
Started Jul 21 06:24:46 PM PDT 24
Finished Jul 21 06:24:49 PM PDT 24
Peak memory 214528 kb
Host smart-42abee3e-62ee-42cc-8999-8fb5adab3c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950115375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3950115375
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3265103432
Short name T55
Test name
Test status
Simulation time 908728365 ps
CPU time 27.28 seconds
Started Jul 21 06:24:48 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 251060 kb
Host smart-b816a43a-94f3-40fa-8cdd-7768e9d1026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265103432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3265103432
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.4020346062
Short name T520
Test name
Test status
Simulation time 143634221 ps
CPU time 7.97 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:11 PM PDT 24
Peak memory 251112 kb
Host smart-9320ecfd-388d-446d-98f8-38662d0ab25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020346062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.4020346062
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2466130636
Short name T802
Test name
Test status
Simulation time 59105535806 ps
CPU time 99.35 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:26:43 PM PDT 24
Peak memory 283652 kb
Host smart-350a331d-20b7-4d49-a96e-e831c93b1d35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466130636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2466130636
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.529805461
Short name T691
Test name
Test status
Simulation time 21059246 ps
CPU time 0.95 seconds
Started Jul 21 06:24:44 PM PDT 24
Finished Jul 21 06:24:45 PM PDT 24
Peak memory 212028 kb
Host smart-461c0da0-9826-4d22-91a3-20b5a06af1c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529805461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.529805461
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.951643519
Short name T529
Test name
Test status
Simulation time 146847263 ps
CPU time 1.21 seconds
Started Jul 21 06:26:43 PM PDT 24
Finished Jul 21 06:26:46 PM PDT 24
Peak memory 209156 kb
Host smart-10a76739-828a-411a-8a1f-2b4679e30e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951643519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.951643519
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2423609630
Short name T303
Test name
Test status
Simulation time 1423067937 ps
CPU time 11.59 seconds
Started Jul 21 06:26:51 PM PDT 24
Finished Jul 21 06:27:04 PM PDT 24
Peak memory 226128 kb
Host smart-4176bd73-302f-4162-a533-27dfb7de6578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423609630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2423609630
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2119971613
Short name T544
Test name
Test status
Simulation time 315890886 ps
CPU time 2.71 seconds
Started Jul 21 06:26:46 PM PDT 24
Finished Jul 21 06:26:50 PM PDT 24
Peak memory 216816 kb
Host smart-46f3badd-e4d9-4c5c-ad24-cb483abf1028
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119971613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2119971613
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1385598999
Short name T304
Test name
Test status
Simulation time 71102556 ps
CPU time 2.86 seconds
Started Jul 21 06:26:43 PM PDT 24
Finished Jul 21 06:26:47 PM PDT 24
Peak memory 218376 kb
Host smart-4bed81b9-b6e6-471f-b9be-ac01cda082c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385598999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1385598999
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1417967860
Short name T476
Test name
Test status
Simulation time 232424634 ps
CPU time 9.28 seconds
Started Jul 21 06:26:43 PM PDT 24
Finished Jul 21 06:26:54 PM PDT 24
Peak memory 218392 kb
Host smart-d1cffe90-7e01-4b9a-8c5d-9ad08cc23fe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417967860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1417967860
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2898097609
Short name T522
Test name
Test status
Simulation time 339291122 ps
CPU time 10.14 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:26:53 PM PDT 24
Peak memory 226108 kb
Host smart-74380b98-25d8-4187-b61b-bf1bf4ebcf5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898097609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2898097609
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3051193957
Short name T654
Test name
Test status
Simulation time 172764996 ps
CPU time 6.61 seconds
Started Jul 21 06:26:40 PM PDT 24
Finished Jul 21 06:26:48 PM PDT 24
Peak memory 218380 kb
Host smart-425a897d-42a4-4cb1-b817-ccdea2932063
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051193957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3051193957
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2606344950
Short name T405
Test name
Test status
Simulation time 1058673602 ps
CPU time 6.68 seconds
Started Jul 21 06:26:44 PM PDT 24
Finished Jul 21 06:26:52 PM PDT 24
Peak memory 224404 kb
Host smart-4e7ca8bc-1962-44ae-9cf2-353dee5b8621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606344950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2606344950
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1303652074
Short name T77
Test name
Test status
Simulation time 318619374 ps
CPU time 3.52 seconds
Started Jul 21 06:26:47 PM PDT 24
Finished Jul 21 06:26:52 PM PDT 24
Peak memory 217808 kb
Host smart-0772b65e-41b4-4f81-87a8-f652424a2abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303652074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1303652074
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.187069390
Short name T715
Test name
Test status
Simulation time 383317075 ps
CPU time 29.63 seconds
Started Jul 21 06:26:44 PM PDT 24
Finished Jul 21 06:27:15 PM PDT 24
Peak memory 251064 kb
Host smart-8dcf5415-ed51-4400-a68c-70bfc5df2514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187069390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.187069390
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1265986005
Short name T610
Test name
Test status
Simulation time 232412225 ps
CPU time 3.58 seconds
Started Jul 21 06:26:43 PM PDT 24
Finished Jul 21 06:26:48 PM PDT 24
Peak memory 226548 kb
Host smart-b5adcc4e-6a4b-40fb-bf56-02eaf45de74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265986005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1265986005
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.4097015319
Short name T401
Test name
Test status
Simulation time 579655123 ps
CPU time 23.79 seconds
Started Jul 21 06:26:45 PM PDT 24
Finished Jul 21 06:27:10 PM PDT 24
Peak memory 251260 kb
Host smart-eb6f4d50-29f6-47e6-be07-3f1d71839a58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097015319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.4097015319
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.214461110
Short name T505
Test name
Test status
Simulation time 42418194 ps
CPU time 0.86 seconds
Started Jul 21 06:26:43 PM PDT 24
Finished Jul 21 06:26:46 PM PDT 24
Peak memory 211976 kb
Host smart-11e16d15-24cf-4132-b0bc-70642c6693ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214461110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.214461110
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1621667886
Short name T444
Test name
Test status
Simulation time 39777904 ps
CPU time 0.86 seconds
Started Jul 21 06:26:47 PM PDT 24
Finished Jul 21 06:26:50 PM PDT 24
Peak memory 208796 kb
Host smart-be75011c-75d3-480a-b2a6-b02e56600251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621667886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1621667886
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1432466483
Short name T42
Test name
Test status
Simulation time 549268255 ps
CPU time 12.35 seconds
Started Jul 21 06:26:43 PM PDT 24
Finished Jul 21 06:26:57 PM PDT 24
Peak memory 226176 kb
Host smart-ee90e0b7-40cf-4831-9b5d-a45ed99973b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432466483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1432466483
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1568317580
Short name T834
Test name
Test status
Simulation time 108278248 ps
CPU time 1.42 seconds
Started Jul 21 06:26:44 PM PDT 24
Finished Jul 21 06:26:47 PM PDT 24
Peak memory 217164 kb
Host smart-5d521669-d9c4-4aa7-af38-cda355361d5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568317580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1568317580
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1412251607
Short name T695
Test name
Test status
Simulation time 114133502 ps
CPU time 2.46 seconds
Started Jul 21 06:26:44 PM PDT 24
Finished Jul 21 06:26:48 PM PDT 24
Peak memory 218316 kb
Host smart-352761c5-e5ae-45e0-89ec-869d16fe6d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412251607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1412251607
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.951233400
Short name T723
Test name
Test status
Simulation time 435523362 ps
CPU time 13.96 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:26:57 PM PDT 24
Peak memory 225936 kb
Host smart-3e5dc13e-923b-4286-b81c-1df1357f94f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951233400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.951233400
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.609524046
Short name T354
Test name
Test status
Simulation time 1798347157 ps
CPU time 16.88 seconds
Started Jul 21 06:26:47 PM PDT 24
Finished Jul 21 06:27:06 PM PDT 24
Peak memory 226188 kb
Host smart-38d01bc9-e29d-45aa-bce6-1f3a539fb411
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609524046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.609524046
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4118719227
Short name T555
Test name
Test status
Simulation time 1975656312 ps
CPU time 6.1 seconds
Started Jul 21 06:26:41 PM PDT 24
Finished Jul 21 06:26:49 PM PDT 24
Peak memory 218304 kb
Host smart-dc678495-939e-494e-8adc-3bc8ecdc42c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118719227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4118719227
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.19073093
Short name T770
Test name
Test status
Simulation time 761903759 ps
CPU time 10.44 seconds
Started Jul 21 06:26:47 PM PDT 24
Finished Jul 21 06:26:59 PM PDT 24
Peak memory 226188 kb
Host smart-6b2328a2-ded1-4f1f-b7e8-cd2559f55e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19073093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.19073093
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.336845479
Short name T69
Test name
Test status
Simulation time 126585981 ps
CPU time 2.73 seconds
Started Jul 21 06:26:42 PM PDT 24
Finished Jul 21 06:26:46 PM PDT 24
Peak memory 214544 kb
Host smart-8aa90caa-69f6-4f01-abad-3fb278e808f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336845479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.336845479
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1564740502
Short name T101
Test name
Test status
Simulation time 239311384 ps
CPU time 26.38 seconds
Started Jul 21 06:26:46 PM PDT 24
Finished Jul 21 06:27:13 PM PDT 24
Peak memory 251264 kb
Host smart-e0dde53d-4ed3-49c5-90eb-a1551d7aade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564740502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1564740502
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1598016734
Short name T786
Test name
Test status
Simulation time 55142592 ps
CPU time 6.72 seconds
Started Jul 21 06:26:46 PM PDT 24
Finished Jul 21 06:26:55 PM PDT 24
Peak memory 250676 kb
Host smart-ab16cf73-5bdc-41ea-977e-07c8ec1f526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598016734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1598016734
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1763931309
Short name T746
Test name
Test status
Simulation time 6884041850 ps
CPU time 188.73 seconds
Started Jul 21 06:26:46 PM PDT 24
Finished Jul 21 06:29:56 PM PDT 24
Peak memory 220940 kb
Host smart-621b0690-2d02-4e37-9252-4702d8d012e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763931309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1763931309
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3708903892
Short name T479
Test name
Test status
Simulation time 35761321 ps
CPU time 1.01 seconds
Started Jul 21 06:26:42 PM PDT 24
Finished Jul 21 06:26:45 PM PDT 24
Peak memory 211988 kb
Host smart-71573f1e-b98c-410a-818e-8dd18e936062
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708903892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3708903892
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.4016015399
Short name T440
Test name
Test status
Simulation time 18821517 ps
CPU time 1.15 seconds
Started Jul 21 06:26:51 PM PDT 24
Finished Jul 21 06:26:54 PM PDT 24
Peak memory 208924 kb
Host smart-d2345950-950e-4373-8d32-e82396cda7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016015399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.4016015399
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3108647383
Short name T639
Test name
Test status
Simulation time 288032992 ps
CPU time 7.96 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:27:00 PM PDT 24
Peak memory 217172 kb
Host smart-5ce1b7c0-1df9-493b-af1e-5bebfa5669e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108647383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3108647383
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1110656072
Short name T24
Test name
Test status
Simulation time 180866903 ps
CPU time 3.39 seconds
Started Jul 21 06:26:40 PM PDT 24
Finished Jul 21 06:26:44 PM PDT 24
Peak memory 218232 kb
Host smart-2037ef4f-046f-4f90-9150-e3b1fe691848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110656072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1110656072
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2435357497
Short name T799
Test name
Test status
Simulation time 2203669573 ps
CPU time 15.05 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:27:07 PM PDT 24
Peak memory 226184 kb
Host smart-b1661f0f-9d97-473f-83ad-e74e81a7aab3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435357497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2435357497
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2779158361
Short name T367
Test name
Test status
Simulation time 232392597 ps
CPU time 7.3 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:26:59 PM PDT 24
Peak memory 226108 kb
Host smart-dd4f54a0-3599-4e6a-86e3-b5cd48f7b10f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779158361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2779158361
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.789516303
Short name T396
Test name
Test status
Simulation time 384418406 ps
CPU time 10.04 seconds
Started Jul 21 06:26:52 PM PDT 24
Finished Jul 21 06:27:03 PM PDT 24
Peak memory 218300 kb
Host smart-6136e16e-34be-4a5a-b8bd-76a6d5df9d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789516303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.789516303
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3092016422
Short name T607
Test name
Test status
Simulation time 957715595 ps
CPU time 10.38 seconds
Started Jul 21 06:26:51 PM PDT 24
Finished Jul 21 06:27:03 PM PDT 24
Peak memory 218428 kb
Host smart-ebb6d29e-b220-4566-bc82-ca36b81596c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092016422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3092016422
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2501216999
Short name T578
Test name
Test status
Simulation time 118798824 ps
CPU time 3.26 seconds
Started Jul 21 06:26:46 PM PDT 24
Finished Jul 21 06:26:51 PM PDT 24
Peak memory 217812 kb
Host smart-fdc4e6b2-3e9e-44e8-af19-7c6acb80988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501216999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2501216999
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3711229613
Short name T256
Test name
Test status
Simulation time 255762517 ps
CPU time 23.73 seconds
Started Jul 21 06:26:51 PM PDT 24
Finished Jul 21 06:27:16 PM PDT 24
Peak memory 251108 kb
Host smart-6c41ffda-f33c-4993-8ab4-dacdb284043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711229613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3711229613
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.239464262
Short name T262
Test name
Test status
Simulation time 91348629 ps
CPU time 3.63 seconds
Started Jul 21 06:26:43 PM PDT 24
Finished Jul 21 06:26:48 PM PDT 24
Peak memory 222912 kb
Host smart-1d15094b-9f61-4711-adb3-807728aa7591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239464262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.239464262
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1837441251
Short name T535
Test name
Test status
Simulation time 16885350187 ps
CPU time 149.2 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:29:19 PM PDT 24
Peak memory 251116 kb
Host smart-c4808414-ce7e-49bc-9cc5-4c40894c195d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837441251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1837441251
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.924032094
Short name T186
Test name
Test status
Simulation time 80237605995 ps
CPU time 374.14 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:33:06 PM PDT 24
Peak memory 447964 kb
Host smart-32e6ea76-134e-4c3e-8f89-9c558e81f110
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=924032094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.924032094
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1645500761
Short name T345
Test name
Test status
Simulation time 14253707 ps
CPU time 1.1 seconds
Started Jul 21 06:26:44 PM PDT 24
Finished Jul 21 06:26:46 PM PDT 24
Peak memory 211976 kb
Host smart-9b77e180-eaa6-4c15-8dd2-bb9d2cd8965f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645500761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1645500761
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3200023769
Short name T533
Test name
Test status
Simulation time 16178950 ps
CPU time 0.93 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:26:53 PM PDT 24
Peak memory 209016 kb
Host smart-814764f1-76ea-4d1f-82b7-69ed7a7b1728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200023769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3200023769
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2710931184
Short name T17
Test name
Test status
Simulation time 1155472622 ps
CPU time 12.07 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:27:03 PM PDT 24
Peak memory 218408 kb
Host smart-dc58faca-a7fa-4f3d-9d7a-1bae281d7c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710931184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2710931184
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.824142924
Short name T655
Test name
Test status
Simulation time 4625801048 ps
CPU time 11.27 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:27:04 PM PDT 24
Peak memory 217872 kb
Host smart-b118491d-4c01-4669-b6b7-cb5c746156c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824142924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.824142924
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.4114526466
Short name T616
Test name
Test status
Simulation time 102820048 ps
CPU time 2.48 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:26:55 PM PDT 24
Peak memory 222628 kb
Host smart-7faf374d-e38d-4460-b4b5-76a378029c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114526466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.4114526466
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1665214096
Short name T418
Test name
Test status
Simulation time 300842062 ps
CPU time 10.03 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:27:00 PM PDT 24
Peak memory 226116 kb
Host smart-20b7692e-0f9a-4cfc-abf5-7a044916b78c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665214096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1665214096
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3523219443
Short name T167
Test name
Test status
Simulation time 470015512 ps
CPU time 17.02 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:27:08 PM PDT 24
Peak memory 218336 kb
Host smart-d8332f59-2c44-4458-8387-3a97fc812af7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523219443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3523219443
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.190202893
Short name T767
Test name
Test status
Simulation time 1569701747 ps
CPU time 10.38 seconds
Started Jul 21 06:26:52 PM PDT 24
Finished Jul 21 06:27:03 PM PDT 24
Peak memory 218572 kb
Host smart-083f349f-6f7a-4650-8f86-4248fbf242b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190202893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.190202893
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.4160159300
Short name T414
Test name
Test status
Simulation time 25481345 ps
CPU time 1.61 seconds
Started Jul 21 06:26:47 PM PDT 24
Finished Jul 21 06:26:50 PM PDT 24
Peak memory 213960 kb
Host smart-f1dbb310-7d1f-4f0b-9e19-9a4e5356f0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160159300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.4160159300
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2525089987
Short name T448
Test name
Test status
Simulation time 205102362 ps
CPU time 26.53 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:27:17 PM PDT 24
Peak memory 246328 kb
Host smart-73c9b670-2a20-4f33-abe7-30a2c4d429de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525089987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2525089987
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2307280639
Short name T507
Test name
Test status
Simulation time 105448380 ps
CPU time 6.37 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:26:59 PM PDT 24
Peak memory 250552 kb
Host smart-03617610-1a38-4733-b986-69c8450b35ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307280639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2307280639
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.52871167
Short name T590
Test name
Test status
Simulation time 76781302944 ps
CPU time 389.12 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:33:21 PM PDT 24
Peak memory 251168 kb
Host smart-9478bdcf-b853-48aa-9438-651e34571f0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52871167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.lc_ctrl_stress_all.52871167
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2235338434
Short name T92
Test name
Test status
Simulation time 403951286158 ps
CPU time 847.18 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:40:57 PM PDT 24
Peak memory 333252 kb
Host smart-b94403ec-e6f7-444a-b221-0df9854e17de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2235338434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2235338434
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.19606590
Short name T224
Test name
Test status
Simulation time 18289001 ps
CPU time 1.03 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:26:51 PM PDT 24
Peak memory 211884 kb
Host smart-abbf134c-a4ee-4475-98f5-b07a3f1fb9f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19606590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctr
l_volatile_unlock_smoke.19606590
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2719706819
Short name T91
Test name
Test status
Simulation time 14704433 ps
CPU time 0.85 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:26:55 PM PDT 24
Peak memory 208784 kb
Host smart-e7cc15b3-a9e3-4e81-aa13-1403f8fb9ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719706819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2719706819
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1644056073
Short name T573
Test name
Test status
Simulation time 927405923 ps
CPU time 11.84 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:27:03 PM PDT 24
Peak memory 226104 kb
Host smart-e30b96d6-fc16-4244-a5ae-0eecc3f6b76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644056073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1644056073
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.55681577
Short name T451
Test name
Test status
Simulation time 232109720 ps
CPU time 6.72 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:26:59 PM PDT 24
Peak memory 217428 kb
Host smart-d37cca9f-1a56-45c8-b689-d4f2d6c93497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55681577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.55681577
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.470177673
Short name T646
Test name
Test status
Simulation time 199856928 ps
CPU time 3.15 seconds
Started Jul 21 06:26:48 PM PDT 24
Finished Jul 21 06:26:53 PM PDT 24
Peak memory 218376 kb
Host smart-1dd34b1d-d51f-4587-836c-727ef1e1b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470177673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.470177673
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2522478002
Short name T156
Test name
Test status
Simulation time 1318846537 ps
CPU time 11.14 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:27:02 PM PDT 24
Peak memory 226132 kb
Host smart-678b5b74-9daa-4344-b614-428219ccea78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522478002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2522478002
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4099740273
Short name T528
Test name
Test status
Simulation time 479631720 ps
CPU time 12 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:27:06 PM PDT 24
Peak memory 226104 kb
Host smart-28a47c1d-03f3-4ef7-bccd-a73db74042e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099740273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4099740273
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.572811395
Short name T439
Test name
Test status
Simulation time 1109506925 ps
CPU time 9.41 seconds
Started Jul 21 06:26:51 PM PDT 24
Finished Jul 21 06:27:02 PM PDT 24
Peak memory 226108 kb
Host smart-7310d7b5-7985-42f2-867e-62ae9f32b194
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572811395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.572811395
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3763585394
Short name T830
Test name
Test status
Simulation time 1024521663 ps
CPU time 7.04 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:26:59 PM PDT 24
Peak memory 225184 kb
Host smart-d1c9c24c-f8be-42e4-8df8-045bd3fd1afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763585394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3763585394
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.492088250
Short name T61
Test name
Test status
Simulation time 60316204 ps
CPU time 1.91 seconds
Started Jul 21 06:26:46 PM PDT 24
Finished Jul 21 06:26:49 PM PDT 24
Peak memory 214108 kb
Host smart-618af868-68cb-4861-a3e4-d6e4c899377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492088250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.492088250
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3717315662
Short name T456
Test name
Test status
Simulation time 177362009 ps
CPU time 25.97 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:27:18 PM PDT 24
Peak memory 251212 kb
Host smart-2b1ba130-5204-497d-bbfb-890b649c8855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717315662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3717315662
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2357853887
Short name T559
Test name
Test status
Simulation time 149618562 ps
CPU time 4.84 seconds
Started Jul 21 06:26:50 PM PDT 24
Finished Jul 21 06:26:57 PM PDT 24
Peak memory 226524 kb
Host smart-46c91b4c-3fba-4373-8004-73d7bc052ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357853887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2357853887
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.926875998
Short name T298
Test name
Test status
Simulation time 14174562 ps
CPU time 0.86 seconds
Started Jul 21 06:26:49 PM PDT 24
Finished Jul 21 06:26:52 PM PDT 24
Peak memory 208272 kb
Host smart-004c2a51-85f3-4cf5-80e0-b25fbc376053
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926875998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.926875998
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.167494525
Short name T722
Test name
Test status
Simulation time 36240238 ps
CPU time 1.15 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:26:57 PM PDT 24
Peak memory 209112 kb
Host smart-eaa3acca-0ec3-4f6c-993a-603e0fbbab74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167494525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.167494525
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1339058559
Short name T180
Test name
Test status
Simulation time 1255541476 ps
CPU time 10.87 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:27:07 PM PDT 24
Peak memory 218384 kb
Host smart-f7ab3d63-a452-4257-8c48-03f1dc681c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339058559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1339058559
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3835400497
Short name T612
Test name
Test status
Simulation time 104532516 ps
CPU time 3.42 seconds
Started Jul 21 06:26:56 PM PDT 24
Finished Jul 21 06:27:00 PM PDT 24
Peak memory 217156 kb
Host smart-51137ab7-271c-4b44-9d99-37f3292e6d19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835400497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3835400497
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3695697950
Short name T257
Test name
Test status
Simulation time 36488281 ps
CPU time 2.1 seconds
Started Jul 21 06:26:58 PM PDT 24
Finished Jul 21 06:27:01 PM PDT 24
Peak memory 218308 kb
Host smart-bb5f7068-86cf-4da7-a630-b2b4219fe272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695697950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3695697950
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.288189441
Short name T285
Test name
Test status
Simulation time 323765381 ps
CPU time 15.64 seconds
Started Jul 21 06:26:57 PM PDT 24
Finished Jul 21 06:27:13 PM PDT 24
Peak memory 226108 kb
Host smart-e3773f4e-0ec4-4ad5-8563-b965dcf8ff38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288189441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.288189441
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.703607868
Short name T287
Test name
Test status
Simulation time 321633183 ps
CPU time 10.82 seconds
Started Jul 21 06:26:58 PM PDT 24
Finished Jul 21 06:27:10 PM PDT 24
Peak memory 218256 kb
Host smart-4e375e51-56d2-42ca-a821-3f14b4d6f40e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703607868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.703607868
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.892734945
Short name T750
Test name
Test status
Simulation time 2188665401 ps
CPU time 9.7 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:27:05 PM PDT 24
Peak memory 225616 kb
Host smart-229949b1-9723-4ca7-b335-5ea4fefe653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892734945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.892734945
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3120151750
Short name T426
Test name
Test status
Simulation time 305482277 ps
CPU time 2.91 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:26:59 PM PDT 24
Peak memory 222964 kb
Host smart-5ccf8586-b0d9-49c7-8f8f-1727a7780e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120151750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3120151750
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.376195640
Short name T760
Test name
Test status
Simulation time 1057830563 ps
CPU time 23.29 seconds
Started Jul 21 06:26:57 PM PDT 24
Finished Jul 21 06:27:22 PM PDT 24
Peak memory 251124 kb
Host smart-f8555367-efd9-4e50-b167-0c26283a55c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376195640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.376195640
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.654364183
Short name T295
Test name
Test status
Simulation time 209966665 ps
CPU time 8.91 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:27:05 PM PDT 24
Peak memory 247596 kb
Host smart-ed91f39f-bd21-4a62-9094-a814d662381b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654364183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.654364183
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.553394405
Short name T640
Test name
Test status
Simulation time 31606416526 ps
CPU time 114.1 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:28:50 PM PDT 24
Peak memory 251052 kb
Host smart-79daa656-01ec-4ef9-8106-62b8fd79550a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553394405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.553394405
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.845574195
Short name T147
Test name
Test status
Simulation time 73547125852 ps
CPU time 654.16 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:37:49 PM PDT 24
Peak memory 422324 kb
Host smart-bbf72099-f8c2-4e33-8523-175b7e883e08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=845574195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.845574195
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3676881871
Short name T806
Test name
Test status
Simulation time 36475733 ps
CPU time 0.92 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:26:56 PM PDT 24
Peak memory 211944 kb
Host smart-16cad73c-2b05-4d98-9db5-126a250ce356
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676881871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3676881871
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2791224455
Short name T284
Test name
Test status
Simulation time 31616514 ps
CPU time 1 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:26:55 PM PDT 24
Peak memory 209008 kb
Host smart-f4a03744-a573-4f59-853b-566e0df90bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791224455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2791224455
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1523177939
Short name T329
Test name
Test status
Simulation time 428666034 ps
CPU time 14.23 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:27:11 PM PDT 24
Peak memory 218380 kb
Host smart-e488cf6d-a26f-4436-9ce5-feab2cb7c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523177939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1523177939
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3010372801
Short name T349
Test name
Test status
Simulation time 501546331 ps
CPU time 1.98 seconds
Started Jul 21 06:26:59 PM PDT 24
Finished Jul 21 06:27:02 PM PDT 24
Peak memory 217104 kb
Host smart-e78a422f-a6ee-47dd-8b90-3732d6321614
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010372801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3010372801
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4116854331
Short name T464
Test name
Test status
Simulation time 166766046 ps
CPU time 4.64 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:27:01 PM PDT 24
Peak memory 222764 kb
Host smart-1e0ed0ae-2d34-4d88-b9cc-c1810d3115a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116854331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4116854331
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2096695512
Short name T472
Test name
Test status
Simulation time 1811569887 ps
CPU time 11.58 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:27:07 PM PDT 24
Peak memory 219036 kb
Host smart-231eaa4b-e64b-4a78-803f-bfca2b0fa23e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096695512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2096695512
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1451515156
Short name T711
Test name
Test status
Simulation time 288088825 ps
CPU time 11.26 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:27:08 PM PDT 24
Peak memory 226104 kb
Host smart-80968029-eb93-4882-9341-55192e487629
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451515156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1451515156
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3130730187
Short name T155
Test name
Test status
Simulation time 673356421 ps
CPU time 11.03 seconds
Started Jul 21 06:26:53 PM PDT 24
Finished Jul 21 06:27:04 PM PDT 24
Peak memory 218260 kb
Host smart-9a8e3cf5-699f-4a8b-a7dd-667d9ffa08e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130730187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3130730187
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1378657364
Short name T557
Test name
Test status
Simulation time 186707697 ps
CPU time 9.24 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:27:05 PM PDT 24
Peak memory 226156 kb
Host smart-739879c4-b953-4e94-8e80-05f2d873cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378657364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1378657364
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.4269922915
Short name T530
Test name
Test status
Simulation time 16624017 ps
CPU time 1.2 seconds
Started Jul 21 06:26:56 PM PDT 24
Finished Jul 21 06:26:58 PM PDT 24
Peak memory 217784 kb
Host smart-e4c1b2f3-a622-4c0d-9d30-8969a9b3b8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269922915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4269922915
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1352168414
Short name T344
Test name
Test status
Simulation time 1027089441 ps
CPU time 25.48 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:27:22 PM PDT 24
Peak memory 251084 kb
Host smart-7fc818f7-e52f-4b46-8422-5b7f7c877ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352168414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1352168414
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.278116838
Short name T637
Test name
Test status
Simulation time 111420211 ps
CPU time 7.34 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:27:04 PM PDT 24
Peak memory 250828 kb
Host smart-ef3e5905-9519-4bc4-a2fa-b9b13f0eb569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278116838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.278116838
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.299567744
Short name T170
Test name
Test status
Simulation time 47222468974 ps
CPU time 452.65 seconds
Started Jul 21 06:27:00 PM PDT 24
Finished Jul 21 06:34:33 PM PDT 24
Peak memory 277956 kb
Host smart-6258e3f0-ca45-432a-bb44-803540c5f168
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=299567744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.299567744
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.968990213
Short name T453
Test name
Test status
Simulation time 14804192 ps
CPU time 1.07 seconds
Started Jul 21 06:26:57 PM PDT 24
Finished Jul 21 06:26:59 PM PDT 24
Peak memory 211904 kb
Host smart-c21baf22-4188-46d7-a1ce-ecf4ed59ae05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968990213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.968990213
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2370599380
Short name T565
Test name
Test status
Simulation time 27302120 ps
CPU time 1.08 seconds
Started Jul 21 06:27:03 PM PDT 24
Finished Jul 21 06:27:05 PM PDT 24
Peak memory 208992 kb
Host smart-18c21386-6089-4c43-a479-fcf99294fd3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370599380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2370599380
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.206239727
Short name T531
Test name
Test status
Simulation time 213087638 ps
CPU time 10.34 seconds
Started Jul 21 06:26:59 PM PDT 24
Finished Jul 21 06:27:10 PM PDT 24
Peak memory 218332 kb
Host smart-9e6f8cc7-ae62-42d3-bec3-aaad2a909a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206239727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.206239727
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1886169145
Short name T201
Test name
Test status
Simulation time 507628865 ps
CPU time 13.05 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:16 PM PDT 24
Peak memory 217504 kb
Host smart-df9c9a6c-ff1c-42d7-8989-a63cb4382e2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886169145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1886169145
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2864389440
Short name T709
Test name
Test status
Simulation time 19595139 ps
CPU time 1.63 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:26:58 PM PDT 24
Peak memory 218420 kb
Host smart-463f7f7c-307e-41d8-a7ad-617b310f6dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864389440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2864389440
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2319833235
Short name T804
Test name
Test status
Simulation time 344054801 ps
CPU time 14.5 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:16 PM PDT 24
Peak memory 226116 kb
Host smart-e7f4e99b-8ef4-43c6-aaae-a5e92bede6e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319833235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2319833235
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1512843121
Short name T798
Test name
Test status
Simulation time 376227455 ps
CPU time 11.16 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:13 PM PDT 24
Peak memory 226124 kb
Host smart-f4fb608c-6018-40fd-bb89-2616bce1746d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512843121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1512843121
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.41809412
Short name T765
Test name
Test status
Simulation time 264236528 ps
CPU time 9.06 seconds
Started Jul 21 06:27:05 PM PDT 24
Finished Jul 21 06:27:15 PM PDT 24
Peak memory 225572 kb
Host smart-fcf1a193-80e5-4234-8791-3bee55297d56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.41809412
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.801601111
Short name T772
Test name
Test status
Simulation time 397143447 ps
CPU time 6.45 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:09 PM PDT 24
Peak memory 218468 kb
Host smart-2b3f3f79-8588-46a4-8768-1c19f2676cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801601111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.801601111
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.4121722330
Short name T739
Test name
Test status
Simulation time 109948826 ps
CPU time 1.94 seconds
Started Jul 21 06:26:55 PM PDT 24
Finished Jul 21 06:26:58 PM PDT 24
Peak memory 217856 kb
Host smart-8527b6ef-4601-4972-8aef-81714c97adcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121722330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.4121722330
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3324689911
Short name T253
Test name
Test status
Simulation time 302665395 ps
CPU time 34.29 seconds
Started Jul 21 06:26:54 PM PDT 24
Finished Jul 21 06:27:29 PM PDT 24
Peak memory 251132 kb
Host smart-67f63502-48ab-48eb-9d90-d8bec5b17adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324689911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3324689911
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.936882013
Short name T421
Test name
Test status
Simulation time 316058773 ps
CPU time 2.51 seconds
Started Jul 21 06:26:56 PM PDT 24
Finished Jul 21 06:27:00 PM PDT 24
Peak memory 218304 kb
Host smart-281fd4e3-dc4c-4084-a950-c456ccd445aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936882013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.936882013
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1621512130
Short name T776
Test name
Test status
Simulation time 490187200 ps
CPU time 30.15 seconds
Started Jul 21 06:27:00 PM PDT 24
Finished Jul 21 06:27:31 PM PDT 24
Peak memory 251104 kb
Host smart-7c127eab-7012-4f41-a565-0238d2e5d626
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621512130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1621512130
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.4208036757
Short name T400
Test name
Test status
Simulation time 18077648 ps
CPU time 0.89 seconds
Started Jul 21 06:26:58 PM PDT 24
Finished Jul 21 06:27:00 PM PDT 24
Peak memory 211888 kb
Host smart-b0283535-3475-4e21-8a86-1c3d3043293d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208036757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.4208036757
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3387140527
Short name T67
Test name
Test status
Simulation time 17245484 ps
CPU time 0.91 seconds
Started Jul 21 06:27:08 PM PDT 24
Finished Jul 21 06:27:09 PM PDT 24
Peak memory 208916 kb
Host smart-23aa9153-c0be-48e7-8515-be2b4d275163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387140527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3387140527
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1885249224
Short name T339
Test name
Test status
Simulation time 3259964796 ps
CPU time 9.94 seconds
Started Jul 21 06:27:02 PM PDT 24
Finished Jul 21 06:27:13 PM PDT 24
Peak memory 219196 kb
Host smart-65202139-a9a7-4bad-8a59-4fc514f52aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885249224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1885249224
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2687560713
Short name T519
Test name
Test status
Simulation time 1454391745 ps
CPU time 5.55 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:07 PM PDT 24
Peak memory 217180 kb
Host smart-0601ec61-cc43-44bc-9e0e-e78818fcfa5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687560713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2687560713
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2420257785
Short name T99
Test name
Test status
Simulation time 289076079 ps
CPU time 4.22 seconds
Started Jul 21 06:27:03 PM PDT 24
Finished Jul 21 06:27:08 PM PDT 24
Peak memory 218364 kb
Host smart-a0199e1e-4e08-42f0-b418-76c50ebce3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420257785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2420257785
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1325571247
Short name T688
Test name
Test status
Simulation time 3442271746 ps
CPU time 13.7 seconds
Started Jul 21 06:27:02 PM PDT 24
Finished Jul 21 06:27:17 PM PDT 24
Peak memory 219008 kb
Host smart-b9ac1c09-5a2f-4a45-a201-030708162e9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325571247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1325571247
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1836534614
Short name T452
Test name
Test status
Simulation time 2550711180 ps
CPU time 8.81 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:11 PM PDT 24
Peak memory 226204 kb
Host smart-f67db57b-8bb8-468e-b839-bc0f934586e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836534614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1836534614
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.4139706274
Short name T513
Test name
Test status
Simulation time 1022516157 ps
CPU time 8.34 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:11 PM PDT 24
Peak memory 218248 kb
Host smart-3ca814f4-e3ab-4944-a545-c119fc58c06e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139706274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
4139706274
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4189378594
Short name T299
Test name
Test status
Simulation time 841258778 ps
CPU time 7.02 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:10 PM PDT 24
Peak memory 224988 kb
Host smart-94a86011-0390-4483-abad-4644069edd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189378594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4189378594
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.393618597
Short name T411
Test name
Test status
Simulation time 24293995 ps
CPU time 2.24 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:04 PM PDT 24
Peak memory 214024 kb
Host smart-3d7bfed8-ed15-427a-8527-05595d426cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393618597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.393618597
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2254274646
Short name T587
Test name
Test status
Simulation time 1789444330 ps
CPU time 20.47 seconds
Started Jul 21 06:27:06 PM PDT 24
Finished Jul 21 06:27:27 PM PDT 24
Peak memory 251108 kb
Host smart-0bba2b90-ca14-4196-88ce-335750d10f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254274646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2254274646
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3414357420
Short name T675
Test name
Test status
Simulation time 160454919 ps
CPU time 7.86 seconds
Started Jul 21 06:27:02 PM PDT 24
Finished Jul 21 06:27:11 PM PDT 24
Peak memory 251056 kb
Host smart-2c5d65d4-e7cf-431d-a3b2-19e82ce0adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414357420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3414357420
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.4241858854
Short name T801
Test name
Test status
Simulation time 20364318444 ps
CPU time 54.93 seconds
Started Jul 21 06:27:01 PM PDT 24
Finished Jul 21 06:27:58 PM PDT 24
Peak memory 267592 kb
Host smart-3a61b87d-0315-47ac-ab64-64d31f721ba3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241858854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.4241858854
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1007124593
Short name T822
Test name
Test status
Simulation time 34794545 ps
CPU time 0.89 seconds
Started Jul 21 06:27:03 PM PDT 24
Finished Jul 21 06:27:05 PM PDT 24
Peak memory 211996 kb
Host smart-0e0f03c5-9f4f-43ea-9caa-254e9fea6677
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007124593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1007124593
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.53704978
Short name T745
Test name
Test status
Simulation time 2253196782 ps
CPU time 15.22 seconds
Started Jul 21 06:27:08 PM PDT 24
Finished Jul 21 06:27:24 PM PDT 24
Peak memory 218444 kb
Host smart-02e2ae3f-8130-49c8-a48c-f6031c79cd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53704978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.53704978
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1158865030
Short name T402
Test name
Test status
Simulation time 1043564318 ps
CPU time 6.69 seconds
Started Jul 21 06:27:07 PM PDT 24
Finished Jul 21 06:27:14 PM PDT 24
Peak memory 217308 kb
Host smart-32ada3b8-c727-4f95-a033-a44840bdfb71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158865030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1158865030
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.30369955
Short name T647
Test name
Test status
Simulation time 145078444 ps
CPU time 3.29 seconds
Started Jul 21 06:27:08 PM PDT 24
Finished Jul 21 06:27:12 PM PDT 24
Peak memory 222660 kb
Host smart-26b2a5ca-47ca-48aa-8074-ca8085ed8da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30369955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.30369955
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3416142643
Short name T532
Test name
Test status
Simulation time 520205305 ps
CPU time 8.68 seconds
Started Jul 21 06:27:10 PM PDT 24
Finished Jul 21 06:27:20 PM PDT 24
Peak memory 219044 kb
Host smart-de1fc0fd-ef77-4bca-a76e-c14aa2c7eb27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416142643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3416142643
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1352003247
Short name T794
Test name
Test status
Simulation time 1956968077 ps
CPU time 6.82 seconds
Started Jul 21 06:27:09 PM PDT 24
Finished Jul 21 06:27:16 PM PDT 24
Peak memory 226104 kb
Host smart-c22f330e-a19b-47c6-8373-84d0a7b69880
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352003247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1352003247
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2634169691
Short name T684
Test name
Test status
Simulation time 4433451445 ps
CPU time 8.64 seconds
Started Jul 21 06:27:10 PM PDT 24
Finished Jul 21 06:27:19 PM PDT 24
Peak memory 226304 kb
Host smart-c7634a35-0fa9-4381-a591-de60b0806392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634169691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2634169691
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4063301628
Short name T743
Test name
Test status
Simulation time 694950821 ps
CPU time 9.72 seconds
Started Jul 21 06:27:09 PM PDT 24
Finished Jul 21 06:27:19 PM PDT 24
Peak memory 225540 kb
Host smart-42cba914-2b7e-4d75-866a-bbdbf426e2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063301628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4063301628
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1961393366
Short name T496
Test name
Test status
Simulation time 85951373 ps
CPU time 3.3 seconds
Started Jul 21 06:27:09 PM PDT 24
Finished Jul 21 06:27:13 PM PDT 24
Peak memory 215216 kb
Host smart-56c64cde-cab1-411c-9de1-dd01ca4c03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961393366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1961393366
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.4075381870
Short name T487
Test name
Test status
Simulation time 180637429 ps
CPU time 23.85 seconds
Started Jul 21 06:27:08 PM PDT 24
Finished Jul 21 06:27:32 PM PDT 24
Peak memory 247528 kb
Host smart-f7b14bea-6883-4f99-9b4c-a0a690b58fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075381870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.4075381870
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1937057987
Short name T634
Test name
Test status
Simulation time 326616767 ps
CPU time 6.38 seconds
Started Jul 21 06:27:11 PM PDT 24
Finished Jul 21 06:27:18 PM PDT 24
Peak memory 250656 kb
Host smart-9a348d18-6ab4-42cc-9022-d639299e71f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937057987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1937057987
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.16792499
Short name T643
Test name
Test status
Simulation time 34806157 ps
CPU time 0.89 seconds
Started Jul 21 06:27:08 PM PDT 24
Finished Jul 21 06:27:09 PM PDT 24
Peak memory 211964 kb
Host smart-08c588f8-341b-4cda-8205-384f73f974e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctr
l_volatile_unlock_smoke.16792499
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2876303668
Short name T696
Test name
Test status
Simulation time 21584397 ps
CPU time 1.21 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:00 PM PDT 24
Peak memory 209084 kb
Host smart-61dbf135-b9eb-4e8a-9223-2e238b7b1c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876303668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2876303668
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1200976110
Short name T227
Test name
Test status
Simulation time 55783026 ps
CPU time 0.79 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:01 PM PDT 24
Peak memory 209092 kb
Host smart-ebde387b-ebd3-473f-b3dc-76bc6d736c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200976110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1200976110
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.285016746
Short name T381
Test name
Test status
Simulation time 373402551 ps
CPU time 12.65 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:15 PM PDT 24
Peak memory 218400 kb
Host smart-cd54cde4-7b1e-4363-8c4c-e4f641b3e447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285016746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.285016746
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1966334021
Short name T346
Test name
Test status
Simulation time 569180552 ps
CPU time 2.57 seconds
Started Jul 21 06:24:56 PM PDT 24
Finished Jul 21 06:25:00 PM PDT 24
Peak memory 217080 kb
Host smart-1dcc4449-e90d-492c-bc12-7773e9becd51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966334021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1966334021
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1578879837
Short name T283
Test name
Test status
Simulation time 2383857667 ps
CPU time 31.93 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:34 PM PDT 24
Peak memory 219164 kb
Host smart-0759f398-2034-42f7-a5f6-6bb516a5479e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578879837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1578879837
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1707886759
Short name T485
Test name
Test status
Simulation time 11569946928 ps
CPU time 14.39 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:15 PM PDT 24
Peak memory 217884 kb
Host smart-810d9cbd-618b-4fdc-972e-e5a2674b301d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707886759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
707886759
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1904167953
Short name T276
Test name
Test status
Simulation time 248735780 ps
CPU time 7.98 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:11 PM PDT 24
Peak memory 223188 kb
Host smart-fb34c880-1535-4828-a782-b88bb689b4dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904167953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1904167953
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1245538700
Short name T656
Test name
Test status
Simulation time 4566643311 ps
CPU time 12.51 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:15 PM PDT 24
Peak memory 217824 kb
Host smart-58ad49d8-7c20-439f-93b8-8e99eecb8486
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245538700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1245538700
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.922214625
Short name T307
Test name
Test status
Simulation time 5516552256 ps
CPU time 5.63 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:02 PM PDT 24
Peak memory 217812 kb
Host smart-a588ebb2-2045-492f-8719-f8398752200a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922214625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.922214625
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2471866598
Short name T416
Test name
Test status
Simulation time 9513085403 ps
CPU time 148.38 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:27:29 PM PDT 24
Peak memory 283836 kb
Host smart-5af6d0cd-8661-44a0-9440-d39e9e875d9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471866598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2471866598
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.251571201
Short name T859
Test name
Test status
Simulation time 3588971157 ps
CPU time 28.73 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:30 PM PDT 24
Peak memory 245628 kb
Host smart-5dc1ca82-7153-440d-9b07-756e973cdad5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251571201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.251571201
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3510411266
Short name T234
Test name
Test status
Simulation time 97507915 ps
CPU time 1.78 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:06 PM PDT 24
Peak memory 218312 kb
Host smart-18d6bb2a-e621-46c1-a2eb-ecb6794a04e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510411266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3510411266
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.537749627
Short name T70
Test name
Test status
Simulation time 377087169 ps
CPU time 5.87 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:02 PM PDT 24
Peak memory 217760 kb
Host smart-04832969-c75e-4508-aedb-6c7cdd093676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537749627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.537749627
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.449677869
Short name T372
Test name
Test status
Simulation time 1373795776 ps
CPU time 13.65 seconds
Started Jul 21 06:25:03 PM PDT 24
Finished Jul 21 06:25:20 PM PDT 24
Peak memory 226008 kb
Host smart-e78ea8c1-d955-4cbd-836b-95bb035f2701
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449677869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.449677869
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2842116768
Short name T463
Test name
Test status
Simulation time 875879606 ps
CPU time 7.29 seconds
Started Jul 21 06:24:56 PM PDT 24
Finished Jul 21 06:25:06 PM PDT 24
Peak memory 218252 kb
Host smart-260d2eca-5d3d-446f-ad9c-f35d1a30a8c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842116768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
842116768
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.232627604
Short name T792
Test name
Test status
Simulation time 250934561 ps
CPU time 7.13 seconds
Started Jul 21 06:24:56 PM PDT 24
Finished Jul 21 06:25:05 PM PDT 24
Peak memory 224676 kb
Host smart-15f86b93-5644-46ce-b638-9c0e2450676d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232627604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.232627604
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1671821929
Short name T482
Test name
Test status
Simulation time 141051561 ps
CPU time 2.09 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:02 PM PDT 24
Peak memory 214276 kb
Host smart-be846f4f-69d0-436b-94bb-af81ba1f2ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671821929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1671821929
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3286835821
Short name T280
Test name
Test status
Simulation time 353636404 ps
CPU time 21.23 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:22 PM PDT 24
Peak memory 251128 kb
Host smart-55653fe5-ae9b-4a1a-88cf-41e2f876080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286835821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3286835821
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1443310247
Short name T721
Test name
Test status
Simulation time 55397565 ps
CPU time 6.77 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 250540 kb
Host smart-44eff32c-51a4-4a65-b381-a9898419d4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443310247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1443310247
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1819060651
Short name T382
Test name
Test status
Simulation time 24800869023 ps
CPU time 144.04 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:27:29 PM PDT 24
Peak memory 226232 kb
Host smart-f28dc7ca-b3ab-48dc-b307-89f0c5f721cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819060651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1819060651
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1237709595
Short name T763
Test name
Test status
Simulation time 12477038462 ps
CPU time 258.03 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:29:23 PM PDT 24
Peak memory 273732 kb
Host smart-f9a852c3-6a16-4dc1-9a8c-4341914f1713
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1237709595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1237709595
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4202725446
Short name T856
Test name
Test status
Simulation time 41212386 ps
CPU time 1.03 seconds
Started Jul 21 06:24:56 PM PDT 24
Finished Jul 21 06:24:58 PM PDT 24
Peak memory 213288 kb
Host smart-ef0fc2db-2a2d-423b-a314-b376536ea738
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202725446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.4202725446
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3206973555
Short name T488
Test name
Test status
Simulation time 15250382 ps
CPU time 0.9 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:06 PM PDT 24
Peak memory 208924 kb
Host smart-3fdf1004-516e-4f4e-b6e5-8de0a5e7af54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206973555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3206973555
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1402500646
Short name T274
Test name
Test status
Simulation time 121590382 ps
CPU time 0.83 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:05 PM PDT 24
Peak memory 209104 kb
Host smart-d66674a3-5322-49fe-ac70-4878b91f99d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402500646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1402500646
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3599717380
Short name T540
Test name
Test status
Simulation time 398517941 ps
CPU time 10.66 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:11 PM PDT 24
Peak memory 218320 kb
Host smart-be429bfb-b43c-4712-81d9-ac52177f37fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599717380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3599717380
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1618498127
Short name T828
Test name
Test status
Simulation time 1015528749 ps
CPU time 13.78 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:14 PM PDT 24
Peak memory 217780 kb
Host smart-3f08e1fd-691a-4351-a907-25f8a99e8bd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618498127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1618498127
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1036774168
Short name T43
Test name
Test status
Simulation time 4484107248 ps
CPU time 41.39 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:46 PM PDT 24
Peak memory 218940 kb
Host smart-d881dcc3-2768-4fce-8712-e5a1d4aae964
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036774168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1036774168
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2939398024
Short name T780
Test name
Test status
Simulation time 1535975867 ps
CPU time 19.91 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 217784 kb
Host smart-6f4dd893-e375-4700-9c4b-6f67cdc217d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939398024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
939398024
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3456807932
Short name T425
Test name
Test status
Simulation time 245756029 ps
CPU time 8.17 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:12 PM PDT 24
Peak memory 223184 kb
Host smart-71a4075d-1cf7-4ad1-b6e7-489626bb3d17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456807932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3456807932
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1401971048
Short name T311
Test name
Test status
Simulation time 773814693 ps
CPU time 23.62 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:25:28 PM PDT 24
Peak memory 217744 kb
Host smart-a770e6e7-722c-42ac-9109-b3d1de56320e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401971048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1401971048
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2105662759
Short name T393
Test name
Test status
Simulation time 93143330 ps
CPU time 2.7 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:06 PM PDT 24
Peak memory 217704 kb
Host smart-3302eb3e-e4f0-4144-bc85-0328f4d58e6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105662759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2105662759
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4168455736
Short name T247
Test name
Test status
Simulation time 863314978 ps
CPU time 36.23 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:33 PM PDT 24
Peak memory 251056 kb
Host smart-d8e7e0a3-dbdd-48b3-9392-c60938a853c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168455736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4168455736
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3157056133
Short name T503
Test name
Test status
Simulation time 2742374314 ps
CPU time 12.47 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:12 PM PDT 24
Peak memory 251132 kb
Host smart-f0bbf2b3-8ad1-4111-9457-cbab04ffd783
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157056133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3157056133
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1584003684
Short name T785
Test name
Test status
Simulation time 88430209 ps
CPU time 3.25 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:05 PM PDT 24
Peak memory 218340 kb
Host smart-a846af65-f898-4328-9d3e-9c77bf61f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584003684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1584003684
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2612235264
Short name T58
Test name
Test status
Simulation time 459391602 ps
CPU time 15.1 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 214504 kb
Host smart-5a7afd28-df2d-424d-ba9d-f3e5279fa912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612235264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2612235264
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1202817210
Short name T538
Test name
Test status
Simulation time 276441238 ps
CPU time 11.77 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:14 PM PDT 24
Peak memory 226100 kb
Host smart-df46035f-d961-4b19-8dfd-46eca85ab360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202817210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1202817210
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2060903787
Short name T484
Test name
Test status
Simulation time 167863321 ps
CPU time 7.83 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:13 PM PDT 24
Peak memory 226076 kb
Host smart-414d5069-717b-43e6-9f7b-8318f93b1b92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060903787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2060903787
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1794112920
Short name T838
Test name
Test status
Simulation time 649486168 ps
CPU time 12.38 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 226080 kb
Host smart-165f5e01-7a8c-4cdf-bbc9-b733ca49a21e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794112920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
794112920
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1202484431
Short name T232
Test name
Test status
Simulation time 2310217200 ps
CPU time 9.19 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 225000 kb
Host smart-284f128b-0b6e-46d6-b430-f804df37bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202484431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1202484431
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3236408307
Short name T72
Test name
Test status
Simulation time 23480926 ps
CPU time 1.24 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:06 PM PDT 24
Peak memory 217756 kb
Host smart-66561256-6a57-4ab5-89fa-9fe19ae25950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236408307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3236408307
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.275931192
Short name T154
Test name
Test status
Simulation time 210027803 ps
CPU time 16.9 seconds
Started Jul 21 06:24:55 PM PDT 24
Finished Jul 21 06:25:13 PM PDT 24
Peak memory 251152 kb
Host smart-4153c5b9-3afb-4426-b037-13875766552a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275931192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.275931192
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.557565439
Short name T11
Test name
Test status
Simulation time 205929149 ps
CPU time 6.76 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:10 PM PDT 24
Peak memory 250896 kb
Host smart-56b21837-28f0-4a7c-91ed-57c3d07e0773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557565439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.557565439
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4218909298
Short name T686
Test name
Test status
Simulation time 4077827416 ps
CPU time 104.48 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:26:49 PM PDT 24
Peak memory 272028 kb
Host smart-3adb6c2e-8e39-4176-91ac-54faaf774119
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218909298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4218909298
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.734874186
Short name T563
Test name
Test status
Simulation time 43190349 ps
CPU time 0.89 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:25:06 PM PDT 24
Peak memory 212060 kb
Host smart-45b80492-2d93-484f-bd25-6dda594014fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734874186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.734874186
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1505331515
Short name T777
Test name
Test status
Simulation time 47772778 ps
CPU time 1.07 seconds
Started Jul 21 06:25:03 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 209060 kb
Host smart-ead5b6b7-95d0-4269-aff8-306eb74ac9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505331515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1505331515
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.4065853598
Short name T626
Test name
Test status
Simulation time 684633614 ps
CPU time 10.45 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 218228 kb
Host smart-53c0eeb3-5a20-4305-baa5-cac9593a6bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065853598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.4065853598
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.14774297
Short name T791
Test name
Test status
Simulation time 1438528884 ps
CPU time 8.35 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:10 PM PDT 24
Peak memory 217312 kb
Host smart-e283bc20-860e-4ec2-9aaa-4cb35363f18b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14774297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.14774297
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3922661713
Short name T700
Test name
Test status
Simulation time 5211002886 ps
CPU time 19.85 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:22 PM PDT 24
Peak memory 219060 kb
Host smart-e83e65b5-9418-4c03-a915-900083ba246a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922661713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3922661713
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.74660474
Short name T319
Test name
Test status
Simulation time 559122450 ps
CPU time 7.77 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:15 PM PDT 24
Peak memory 217812 kb
Host smart-64fb7b8c-5b62-4e47-8625-0f40d17d2beb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74660474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.74660474
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3869276359
Short name T364
Test name
Test status
Simulation time 901338851 ps
CPU time 4.58 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:25:10 PM PDT 24
Peak memory 218136 kb
Host smart-a11a88b4-81f8-40ef-9dff-03ee3ac085cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869276359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3869276359
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.808767281
Short name T820
Test name
Test status
Simulation time 1316957482 ps
CPU time 18.24 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:23 PM PDT 24
Peak memory 217744 kb
Host smart-b5a4738e-0481-4f6f-98c4-9a69c7f32492
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808767281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.808767281
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.444556877
Short name T420
Test name
Test status
Simulation time 427380643 ps
CPU time 5.91 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 217696 kb
Host smart-16e272ef-58c2-4fcf-9062-4093cf863b76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444556877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.444556877
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1431246682
Short name T97
Test name
Test status
Simulation time 1522867760 ps
CPU time 56.59 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:26:00 PM PDT 24
Peak memory 267420 kb
Host smart-d42f9e08-b201-4e6d-a7b1-fd22f6ab51d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431246682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1431246682
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.4079129597
Short name T301
Test name
Test status
Simulation time 981538166 ps
CPU time 19.76 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:25:25 PM PDT 24
Peak memory 251012 kb
Host smart-0a00d315-3f99-45e5-ad42-6ae73230c7e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079129597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.4079129597
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.430663966
Short name T433
Test name
Test status
Simulation time 83992744 ps
CPU time 3.36 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:07 PM PDT 24
Peak memory 218380 kb
Host smart-0a89cad4-9f61-455b-94c1-e2a8a3beda82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430663966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.430663966
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1413347185
Short name T811
Test name
Test status
Simulation time 202486290 ps
CPU time 8.24 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:13 PM PDT 24
Peak memory 214608 kb
Host smart-d8d9d965-ee7a-4abf-9bb4-64caade38294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413347185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1413347185
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1541301597
Short name T541
Test name
Test status
Simulation time 288241803 ps
CPU time 11.76 seconds
Started Jul 21 06:24:57 PM PDT 24
Finished Jul 21 06:25:12 PM PDT 24
Peak memory 218316 kb
Host smart-0535b475-f2b1-4489-956a-a96c20c2c257
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541301597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1541301597
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3301585416
Short name T845
Test name
Test status
Simulation time 2070542643 ps
CPU time 11.17 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 226116 kb
Host smart-e8ac0aee-2791-437b-857d-ab34437f3ddf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301585416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3301585416
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.4040633279
Short name T658
Test name
Test status
Simulation time 1309712883 ps
CPU time 14.77 seconds
Started Jul 21 06:24:58 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 218340 kb
Host smart-c4ce3a9b-8d75-492a-a07d-581d4c834a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040633279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.4
040633279
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3518677299
Short name T580
Test name
Test status
Simulation time 1156859853 ps
CPU time 9.94 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 218440 kb
Host smart-769c4639-b1ff-495d-a01a-f091c1504e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518677299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3518677299
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1789059707
Short name T596
Test name
Test status
Simulation time 720039207 ps
CPU time 3.64 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 217720 kb
Host smart-d13f7ed4-3cdf-425a-8cc2-5f8a0e43c2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789059707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1789059707
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2970755620
Short name T88
Test name
Test status
Simulation time 1175537012 ps
CPU time 18.14 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:24 PM PDT 24
Peak memory 251056 kb
Host smart-6e78b6f8-0877-48a0-8a5b-08bebd257c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970755620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2970755620
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3744624623
Short name T730
Test name
Test status
Simulation time 86102872 ps
CPU time 10.13 seconds
Started Jul 21 06:25:00 PM PDT 24
Finished Jul 21 06:25:15 PM PDT 24
Peak memory 251112 kb
Host smart-3449353e-00a3-4458-b9d1-6e40d976dda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744624623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3744624623
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3212908789
Short name T539
Test name
Test status
Simulation time 7813308545 ps
CPU time 202.42 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:28:29 PM PDT 24
Peak memory 282080 kb
Host smart-cc84e8b1-23f1-4989-a93d-ec8e87761998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212908789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3212908789
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3432329642
Short name T759
Test name
Test status
Simulation time 128045628402 ps
CPU time 565.94 seconds
Started Jul 21 06:25:03 PM PDT 24
Finished Jul 21 06:34:33 PM PDT 24
Peak memory 349620 kb
Host smart-02c16b60-d3ed-4fdf-968f-82d0277bd7a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3432329642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.3432329642
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3702634011
Short name T570
Test name
Test status
Simulation time 13969459 ps
CPU time 1.05 seconds
Started Jul 21 06:24:59 PM PDT 24
Finished Jul 21 06:25:04 PM PDT 24
Peak memory 212004 kb
Host smart-a77baf3f-b7aa-47d7-8221-864f33718015
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702634011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3702634011
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1137483999
Short name T774
Test name
Test status
Simulation time 14389703 ps
CPU time 0.83 seconds
Started Jul 21 06:25:04 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 208732 kb
Host smart-eb6242c4-bd80-4324-b168-6b1ca1c685a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137483999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1137483999
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.600741996
Short name T380
Test name
Test status
Simulation time 13625295 ps
CPU time 0.82 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:07 PM PDT 24
Peak memory 208704 kb
Host smart-47accc62-d630-4f62-b333-a6bc18b16455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600741996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.600741996
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2296773396
Short name T469
Test name
Test status
Simulation time 448297971 ps
CPU time 9.07 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 218284 kb
Host smart-32c887a4-9a48-4c22-8e85-5c9e5748f455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296773396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2296773396
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2910174631
Short name T584
Test name
Test status
Simulation time 1371093134 ps
CPU time 5.16 seconds
Started Jul 21 06:25:04 PM PDT 24
Finished Jul 21 06:25:12 PM PDT 24
Peak memory 217340 kb
Host smart-db1cafb1-dc97-4d18-b729-e3d1c61083f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910174631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2910174631
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2533808219
Short name T788
Test name
Test status
Simulation time 13064825220 ps
CPU time 77.18 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:26:25 PM PDT 24
Peak memory 219856 kb
Host smart-eed740d7-0885-4f4e-84d1-3b8e0c55d35c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533808219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2533808219
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4039033422
Short name T652
Test name
Test status
Simulation time 2452409208 ps
CPU time 6.69 seconds
Started Jul 21 06:25:04 PM PDT 24
Finished Jul 21 06:25:14 PM PDT 24
Peak memory 217888 kb
Host smart-d3727625-e6d5-4750-91c1-a85d1607000d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039033422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.4
039033422
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1629012621
Short name T243
Test name
Test status
Simulation time 250284417 ps
CPU time 8.84 seconds
Started Jul 21 06:25:03 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 223196 kb
Host smart-687892ca-1144-4cde-a28b-9a45c41105e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629012621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1629012621
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.708396348
Short name T76
Test name
Test status
Simulation time 1041367428 ps
CPU time 24.98 seconds
Started Jul 21 06:25:03 PM PDT 24
Finished Jul 21 06:25:32 PM PDT 24
Peak memory 217708 kb
Host smart-7b1869f2-07d2-4ce4-9bd5-41e3f0efc439
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708396348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.708396348
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1679626294
Short name T800
Test name
Test status
Simulation time 447524547 ps
CPU time 5.81 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:25:14 PM PDT 24
Peak memory 217628 kb
Host smart-49fd980a-533e-44c9-aa20-030a21ad211a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679626294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1679626294
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2414380529
Short name T309
Test name
Test status
Simulation time 2837010594 ps
CPU time 41.06 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:25:49 PM PDT 24
Peak memory 267512 kb
Host smart-32eba43d-840c-4ce4-83a6-edc304400bbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414380529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2414380529
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2982857976
Short name T613
Test name
Test status
Simulation time 1223426745 ps
CPU time 15.59 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:21 PM PDT 24
Peak memory 251080 kb
Host smart-ded97c5c-a9cd-4851-93b4-c69928be7829
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982857976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2982857976
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3262995119
Short name T825
Test name
Test status
Simulation time 92989867 ps
CPU time 3.22 seconds
Started Jul 21 06:25:01 PM PDT 24
Finished Jul 21 06:25:09 PM PDT 24
Peak memory 218344 kb
Host smart-d9437150-8ba8-4410-96d1-6070555d4024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262995119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3262995119
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.566545106
Short name T758
Test name
Test status
Simulation time 1323903484 ps
CPU time 7.88 seconds
Started Jul 21 06:25:07 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 217808 kb
Host smart-9fac0641-5bf4-4083-bb11-edc7698fa678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566545106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.566545106
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.702269097
Short name T623
Test name
Test status
Simulation time 302282875 ps
CPU time 13.45 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:20 PM PDT 24
Peak memory 219080 kb
Host smart-388714d3-d621-4e4f-8d5c-6151d80d975d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702269097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.702269097
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3402330675
Short name T20
Test name
Test status
Simulation time 651313410 ps
CPU time 17.94 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:25:26 PM PDT 24
Peak memory 226092 kb
Host smart-42a8739a-bf5b-4b96-947a-31907589aed7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402330675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3402330675
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1907122569
Short name T413
Test name
Test status
Simulation time 1627891785 ps
CPU time 7.36 seconds
Started Jul 21 06:25:07 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 218308 kb
Host smart-1d1d3ff5-b243-41f3-b295-62c08ad67404
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907122569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
907122569
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3956740789
Short name T231
Test name
Test status
Simulation time 349938034 ps
CPU time 12.89 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:19 PM PDT 24
Peak memory 226200 kb
Host smart-e083d090-3edd-44e1-9aa4-432f61e02855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956740789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3956740789
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.4077565244
Short name T795
Test name
Test status
Simulation time 337842539 ps
CPU time 3.18 seconds
Started Jul 21 06:25:02 PM PDT 24
Finished Jul 21 06:25:09 PM PDT 24
Peak memory 217788 kb
Host smart-f2824bcf-857a-44ed-b8e6-4503a61769b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077565244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4077565244
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1659677176
Short name T676
Test name
Test status
Simulation time 213119686 ps
CPU time 22.96 seconds
Started Jul 21 06:25:07 PM PDT 24
Finished Jul 21 06:25:32 PM PDT 24
Peak memory 246204 kb
Host smart-ae08b03c-dd3f-4705-a1da-8dab5e8e0dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659677176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1659677176
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1013185820
Short name T244
Test name
Test status
Simulation time 662846000 ps
CPU time 3.43 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:25:11 PM PDT 24
Peak memory 226544 kb
Host smart-17ca8e2d-4e4c-4721-833b-25a505fac97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013185820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1013185820
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1550050735
Short name T59
Test name
Test status
Simulation time 5407775288 ps
CPU time 132.57 seconds
Started Jul 21 06:25:06 PM PDT 24
Finished Jul 21 06:27:21 PM PDT 24
Peak memory 225648 kb
Host smart-2c96dc42-bd27-4bd7-b3c6-952715e0fc1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550050735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1550050735
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2915667380
Short name T787
Test name
Test status
Simulation time 13035227 ps
CPU time 0.85 seconds
Started Jul 21 06:25:04 PM PDT 24
Finished Jul 21 06:25:08 PM PDT 24
Peak memory 211944 kb
Host smart-482607b9-dda1-4e79-8537-91d7f899e89e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915667380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2915667380
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3450191327
Short name T644
Test name
Test status
Simulation time 18280612 ps
CPU time 1.08 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:12 PM PDT 24
Peak memory 208972 kb
Host smart-d54b4b9e-2344-440b-a279-157252fba567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450191327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3450191327
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2947855571
Short name T703
Test name
Test status
Simulation time 43089298 ps
CPU time 0.79 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:25:09 PM PDT 24
Peak memory 209004 kb
Host smart-207377a2-0149-46c2-8578-c282d4ecd3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947855571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2947855571
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1108269353
Short name T268
Test name
Test status
Simulation time 2484859757 ps
CPU time 13.43 seconds
Started Jul 21 06:25:04 PM PDT 24
Finished Jul 21 06:25:21 PM PDT 24
Peak memory 226260 kb
Host smart-69dffbb1-b27a-4df7-b6f2-7f5f55ae3ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108269353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1108269353
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.233177826
Short name T848
Test name
Test status
Simulation time 959880266 ps
CPU time 12.38 seconds
Started Jul 21 06:25:08 PM PDT 24
Finished Jul 21 06:25:21 PM PDT 24
Peak memory 217836 kb
Host smart-bd951ddf-ae1f-4084-9fac-d9b91e6ce9b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233177826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.233177826
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4066261583
Short name T49
Test name
Test status
Simulation time 9329312235 ps
CPU time 41.17 seconds
Started Jul 21 06:25:12 PM PDT 24
Finished Jul 21 06:25:54 PM PDT 24
Peak memory 218940 kb
Host smart-fee16f4c-8ec8-4aa8-a7d6-cd1e21f1355c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066261583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4066261583
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.419609440
Short name T651
Test name
Test status
Simulation time 535257815 ps
CPU time 13.77 seconds
Started Jul 21 06:25:07 PM PDT 24
Finished Jul 21 06:25:23 PM PDT 24
Peak memory 217812 kb
Host smart-57d499cb-2bfb-4b06-ab2b-8abfbabfe230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419609440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.419609440
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1947782341
Short name T327
Test name
Test status
Simulation time 239096690 ps
CPU time 7.86 seconds
Started Jul 21 06:25:09 PM PDT 24
Finished Jul 21 06:25:18 PM PDT 24
Peak memory 223076 kb
Host smart-9ab09f85-514a-427c-8643-a2710ba09677
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947782341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1947782341
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.53597890
Short name T516
Test name
Test status
Simulation time 1345107179 ps
CPU time 19.59 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:30 PM PDT 24
Peak memory 217664 kb
Host smart-0936cd65-be9a-4c4e-b8d6-023e578e6b6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53597890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt
ag_regwen_during_op.53597890
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.246117278
Short name T837
Test name
Test status
Simulation time 396425946 ps
CPU time 3.72 seconds
Started Jul 21 06:25:13 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 217644 kb
Host smart-8ddfbbec-4335-467e-89ad-a075a317bf15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246117278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.246117278
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1781383568
Short name T258
Test name
Test status
Simulation time 4510458204 ps
CPU time 37.18 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:25:48 PM PDT 24
Peak memory 252352 kb
Host smart-121b80e5-569d-49d3-a34f-5b07120027d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781383568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1781383568
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1481985503
Short name T768
Test name
Test status
Simulation time 3642475443 ps
CPU time 29.83 seconds
Started Jul 21 06:25:12 PM PDT 24
Finished Jul 21 06:25:42 PM PDT 24
Peak memory 251148 kb
Host smart-5298d3a6-0630-4498-9f2a-76ee7ef14387
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481985503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1481985503
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2334023686
Short name T9
Test name
Test status
Simulation time 74100460 ps
CPU time 2.89 seconds
Started Jul 21 06:25:03 PM PDT 24
Finished Jul 21 06:25:10 PM PDT 24
Peak memory 218320 kb
Host smart-b07c183e-6ffe-48df-b39e-c8d91ebf6a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334023686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2334023686
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2584099162
Short name T182
Test name
Test status
Simulation time 367318258 ps
CPU time 8.5 seconds
Started Jul 21 06:25:07 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 214824 kb
Host smart-fcd71d87-d439-48d3-b37e-7d6086aa7d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584099162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2584099162
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1948547469
Short name T302
Test name
Test status
Simulation time 1481901296 ps
CPU time 12.02 seconds
Started Jul 21 06:25:12 PM PDT 24
Finished Jul 21 06:25:24 PM PDT 24
Peak memory 226188 kb
Host smart-3b4334b2-d2c8-4448-8242-42c83ef73e2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948547469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1948547469
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.926415000
Short name T534
Test name
Test status
Simulation time 573600947 ps
CPU time 14.44 seconds
Started Jul 21 06:25:09 PM PDT 24
Finished Jul 21 06:25:25 PM PDT 24
Peak memory 226028 kb
Host smart-0ba4b99c-e877-457f-8d58-bc4b1a19bb12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926415000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.926415000
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1609716156
Short name T391
Test name
Test status
Simulation time 1490758914 ps
CPU time 9.61 seconds
Started Jul 21 06:25:09 PM PDT 24
Finished Jul 21 06:25:19 PM PDT 24
Peak memory 218240 kb
Host smart-866b6c76-c59c-43f3-b82b-a96d0e6cc9a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609716156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
609716156
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3919096656
Short name T321
Test name
Test status
Simulation time 1437460002 ps
CPU time 8.63 seconds
Started Jul 21 06:25:04 PM PDT 24
Finished Jul 21 06:25:16 PM PDT 24
Peak memory 218500 kb
Host smart-63c2b7e1-878e-4162-95cc-57a599402453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919096656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3919096656
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.645024219
Short name T270
Test name
Test status
Simulation time 44440259 ps
CPU time 2.3 seconds
Started Jul 21 06:25:07 PM PDT 24
Finished Jul 21 06:25:11 PM PDT 24
Peak memory 214476 kb
Host smart-3c1376f2-0473-451a-95a8-2c6bc1e594ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645024219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.645024219
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.791914014
Short name T434
Test name
Test status
Simulation time 510555985 ps
CPU time 32.25 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:25:40 PM PDT 24
Peak memory 251052 kb
Host smart-49c70e4f-20eb-40e2-a1b2-39eaa3254aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791914014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.791914014
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1095304638
Short name T178
Test name
Test status
Simulation time 64890821 ps
CPU time 9.77 seconds
Started Jul 21 06:25:03 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 251152 kb
Host smart-3e25d3e8-79f6-44c0-9500-5e1dd869cf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095304638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1095304638
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2010109411
Short name T82
Test name
Test status
Simulation time 12743552322 ps
CPU time 45.56 seconds
Started Jul 21 06:25:13 PM PDT 24
Finished Jul 21 06:25:58 PM PDT 24
Peak memory 249276 kb
Host smart-3a15d112-8f97-4eed-a059-9d88bc4b9ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010109411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2010109411
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3251557404
Short name T168
Test name
Test status
Simulation time 38059437390 ps
CPU time 735.29 seconds
Started Jul 21 06:25:10 PM PDT 24
Finished Jul 21 06:37:26 PM PDT 24
Peak memory 270140 kb
Host smart-c0dd1a15-36d1-49da-a7f7-e64001bb574d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3251557404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3251557404
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.777235121
Short name T373
Test name
Test status
Simulation time 63406986 ps
CPU time 1.14 seconds
Started Jul 21 06:25:05 PM PDT 24
Finished Jul 21 06:25:09 PM PDT 24
Peak memory 217660 kb
Host smart-b84d4020-c6dc-44d5-b651-e60caf58cc1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777235121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.777235121
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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