Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58276 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
172 |
auto[1] |
1972 |
1 |
|
|
T3 |
7 |
|
T14 |
7 |
|
T11 |
5 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59688 |
1 |
|
|
T1 |
48 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
560 |
1 |
|
|
T1 |
13 |
|
T46 |
13 |
|
T47 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57905 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[1] |
2343 |
1 |
|
|
T3 |
10 |
|
T27 |
15 |
|
T48 |
8 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57829 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
174 |
auto[1] |
2419 |
1 |
|
|
T3 |
5 |
|
T15 |
1 |
|
T27 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57945 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
163 |
auto[1] |
2303 |
1 |
|
|
T3 |
16 |
|
T15 |
1 |
|
T27 |
15 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
54276 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
171 |
no_err_inj |
5972 |
1 |
|
|
T3 |
8 |
|
T15 |
6 |
|
T16 |
11 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58274 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
172 |
auto[1] |
1974 |
1 |
|
|
T3 |
7 |
|
T14 |
6 |
|
T11 |
14 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59664 |
1 |
|
|
T1 |
53 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
584 |
1 |
|
|
T1 |
8 |
|
T46 |
12 |
|
T47 |
19 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40425 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
19823 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
165 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57916 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[1] |
2332 |
1 |
|
|
T3 |
10 |
|
T27 |
11 |
|
T48 |
4 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57928 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
167 |
auto[1] |
2320 |
1 |
|
|
T3 |
12 |
|
T15 |
1 |
|
T27 |
8 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57874 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
171 |
auto[1] |
2374 |
1 |
|
|
T3 |
8 |
|
T15 |
1 |
|
T27 |
14 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58205 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[1] |
2043 |
1 |
|
|
T3 |
10 |
|
T14 |
8 |
|
T11 |
5 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57528 |
1 |
|
|
T1 |
61 |
|
T3 |
163 |
|
T13 |
83 |
auto[1] |
2720 |
1 |
|
|
T2 |
8 |
|
T3 |
16 |
|
T5 |
18 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59666 |
1 |
|
|
T1 |
49 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
582 |
1 |
|
|
T1 |
12 |
|
T46 |
13 |
|
T47 |
18 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59651 |
1 |
|
|
T1 |
46 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
597 |
1 |
|
|
T1 |
15 |
|
T46 |
8 |
|
T47 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59648 |
1 |
|
|
T1 |
48 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
600 |
1 |
|
|
T1 |
13 |
|
T46 |
20 |
|
T47 |
16 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56773 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
3475 |
1 |
|
|
T15 |
12 |
|
T64 |
13 |
|
T11 |
63 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56386 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
3862 |
1 |
|
|
T13 |
83 |
|
T20 |
100 |
|
T49 |
87 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57913 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
174 |
auto[1] |
2335 |
1 |
|
|
T3 |
5 |
|
T15 |
1 |
|
T27 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57878 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[1] |
2370 |
1 |
|
|
T3 |
10 |
|
T15 |
1 |
|
T27 |
9 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57933 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[1] |
2315 |
1 |
|
|
T3 |
10 |
|
T27 |
6 |
|
T48 |
6 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58244 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[1] |
2004 |
1 |
|
|
T3 |
10 |
|
T14 |
6 |
|
T11 |
15 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54374 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
174 |
auto[1] |
5874 |
1 |
|
|
T3 |
5 |
|
T14 |
7 |
|
T17 |
84 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56485 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
179 |
auto[1] |
3763 |
1 |
|
|
T22 |
82 |
|
T21 |
54 |
|
T55 |
87 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60248 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
179 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58183 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[1] |
2065 |
1 |
|
|
T3 |
10 |
|
T14 |
4 |
|
T11 |
9 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58248 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
166 |
auto[1] |
2000 |
1 |
|
|
T3 |
13 |
|
T14 |
5 |
|
T11 |
11 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58283 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
172 |
auto[1] |
1965 |
1 |
|
|
T3 |
7 |
|
T14 |
10 |
|
T11 |
11 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
52582 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
171 |
auto[0] |
no_err_inj |
4191 |
1 |
|
|
T3 |
8 |
|
T16 |
11 |
|
T6 |
7 |
auto[1] |
err_inj |
1694 |
1 |
|
|
T15 |
6 |
|
T64 |
5 |
|
T11 |
36 |
auto[1] |
no_err_inj |
1781 |
1 |
|
|
T15 |
6 |
|
T64 |
8 |
|
T11 |
27 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54594 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[0] |
auto[1] |
2179 |
1 |
|
|
T3 |
10 |
|
T27 |
9 |
|
T48 |
7 |
auto[1] |
auto[0] |
3284 |
1 |
|
|
T15 |
11 |
|
T64 |
12 |
|
T11 |
58 |
auto[1] |
auto[1] |
191 |
1 |
|
|
T15 |
1 |
|
T64 |
1 |
|
T11 |
5 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54655 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
167 |
auto[0] |
auto[1] |
2118 |
1 |
|
|
T3 |
12 |
|
T27 |
8 |
|
T48 |
9 |
auto[1] |
auto[0] |
3273 |
1 |
|
|
T15 |
11 |
|
T64 |
11 |
|
T11 |
58 |
auto[1] |
auto[1] |
202 |
1 |
|
|
T15 |
1 |
|
T64 |
2 |
|
T11 |
5 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54641 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[0] |
auto[1] |
2132 |
1 |
|
|
T3 |
10 |
|
T27 |
6 |
|
T48 |
6 |
auto[1] |
auto[0] |
3292 |
1 |
|
|
T15 |
12 |
|
T64 |
13 |
|
T11 |
59 |
auto[1] |
auto[1] |
183 |
1 |
|
|
T11 |
4 |
|
T23 |
5 |
|
T25 |
7 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54539 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
174 |
auto[0] |
auto[1] |
2234 |
1 |
|
|
T3 |
5 |
|
T27 |
8 |
|
T48 |
7 |
auto[1] |
auto[0] |
3290 |
1 |
|
|
T15 |
11 |
|
T64 |
12 |
|
T11 |
59 |
auto[1] |
auto[1] |
185 |
1 |
|
|
T15 |
1 |
|
T64 |
1 |
|
T11 |
4 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54670 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
163 |
auto[0] |
auto[1] |
2103 |
1 |
|
|
T3 |
16 |
|
T27 |
15 |
|
T48 |
12 |
auto[1] |
auto[0] |
3275 |
1 |
|
|
T15 |
11 |
|
T64 |
12 |
|
T11 |
60 |
auto[1] |
auto[1] |
200 |
1 |
|
|
T15 |
1 |
|
T64 |
1 |
|
T11 |
3 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54621 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[0] |
auto[1] |
2152 |
1 |
|
|
T3 |
10 |
|
T27 |
15 |
|
T48 |
8 |
auto[1] |
auto[0] |
3284 |
1 |
|
|
T15 |
12 |
|
T64 |
13 |
|
T11 |
58 |
auto[1] |
auto[1] |
191 |
1 |
|
|
T11 |
5 |
|
T23 |
2 |
|
T25 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39271 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
172 |
auto[0] |
auto[1] |
1154 |
1 |
|
|
T3 |
7 |
|
T14 |
7 |
|
T11 |
5 |
auto[1] |
auto[0] |
19005 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
165 |
auto[1] |
auto[1] |
818 |
1 |
|
|
T23 |
19 |
|
T25 |
25 |
|
T26 |
13 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39266 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
172 |
auto[0] |
auto[1] |
1159 |
1 |
|
|
T3 |
7 |
|
T14 |
6 |
|
T11 |
14 |
auto[1] |
auto[0] |
19008 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
165 |
auto[1] |
auto[1] |
815 |
1 |
|
|
T23 |
20 |
|
T25 |
24 |
|
T26 |
17 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38912 |
1 |
|
|
T1 |
61 |
|
T3 |
163 |
|
T13 |
83 |
auto[0] |
auto[1] |
1513 |
1 |
|
|
T2 |
8 |
|
T3 |
16 |
|
T11 |
31 |
auto[1] |
auto[0] |
18616 |
1 |
|
|
T6 |
7 |
|
T11 |
144 |
|
T23 |
922 |
auto[1] |
auto[1] |
1207 |
1 |
|
|
T5 |
18 |
|
T11 |
21 |
|
T23 |
42 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39231 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[0] |
auto[1] |
1194 |
1 |
|
|
T3 |
10 |
|
T14 |
8 |
|
T11 |
5 |
auto[1] |
auto[0] |
18974 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
165 |
auto[1] |
auto[1] |
849 |
1 |
|
|
T23 |
36 |
|
T25 |
24 |
|
T26 |
9 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35352 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
174 |
auto[0] |
auto[1] |
5073 |
1 |
|
|
T3 |
5 |
|
T14 |
7 |
|
T17 |
84 |
auto[1] |
auto[0] |
19022 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
165 |
auto[1] |
auto[1] |
801 |
1 |
|
|
T23 |
31 |
|
T25 |
26 |
|
T26 |
7 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39087 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[0] |
auto[1] |
1338 |
1 |
|
|
T3 |
10 |
|
T15 |
1 |
|
T27 |
9 |
auto[1] |
auto[0] |
18791 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
152 |
auto[1] |
auto[1] |
1032 |
1 |
|
|
T11 |
13 |
|
T23 |
67 |
|
T24 |
6 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39134 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
174 |
auto[0] |
auto[1] |
1291 |
1 |
|
|
T3 |
5 |
|
T15 |
1 |
|
T27 |
9 |
auto[1] |
auto[0] |
18779 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
151 |
auto[1] |
auto[1] |
1044 |
1 |
|
|
T11 |
14 |
|
T23 |
73 |
|
T24 |
10 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39109 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
167 |
auto[0] |
auto[1] |
1316 |
1 |
|
|
T3 |
12 |
|
T15 |
1 |
|
T27 |
8 |
auto[1] |
auto[0] |
18819 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
156 |
auto[1] |
auto[1] |
1004 |
1 |
|
|
T11 |
9 |
|
T23 |
61 |
|
T24 |
11 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39164 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[0] |
auto[1] |
1261 |
1 |
|
|
T3 |
10 |
|
T27 |
11 |
|
T48 |
4 |
auto[1] |
auto[0] |
18752 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
155 |
auto[1] |
auto[1] |
1071 |
1 |
|
|
T11 |
10 |
|
T23 |
73 |
|
T24 |
14 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39080 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
174 |
auto[0] |
auto[1] |
1345 |
1 |
|
|
T3 |
5 |
|
T15 |
1 |
|
T27 |
8 |
auto[1] |
auto[0] |
18749 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
156 |
auto[1] |
auto[1] |
1074 |
1 |
|
|
T11 |
9 |
|
T23 |
73 |
|
T24 |
8 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39145 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
169 |
auto[0] |
auto[1] |
1280 |
1 |
|
|
T3 |
10 |
|
T27 |
15 |
|
T48 |
8 |
auto[1] |
auto[0] |
18760 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
157 |
auto[1] |
auto[1] |
1063 |
1 |
|
|
T11 |
8 |
|
T23 |
71 |
|
T24 |
11 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39290 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
172 |
auto[0] |
auto[1] |
1135 |
1 |
|
|
T3 |
7 |
|
T14 |
10 |
|
T11 |
11 |
auto[1] |
auto[0] |
18993 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
165 |
auto[1] |
auto[1] |
830 |
1 |
|
|
T23 |
24 |
|
T25 |
21 |
|
T26 |
13 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39253 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
166 |
auto[0] |
auto[1] |
1172 |
1 |
|
|
T3 |
13 |
|
T14 |
5 |
|
T11 |
11 |
auto[1] |
auto[0] |
18995 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
165 |
auto[1] |
auto[1] |
828 |
1 |
|
|
T23 |
21 |
|
T25 |
20 |
|
T26 |
12 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38373 |
1 |
|
|
T1 |
61 |
|
T2 |
8 |
|
T3 |
179 |
auto[0] |
auto[1] |
2052 |
1 |
|
|
T15 |
12 |
|
T64 |
13 |
|
T11 |
40 |
auto[1] |
auto[0] |
18400 |
1 |
|
|
T5 |
18 |
|
T6 |
7 |
|
T11 |
142 |
auto[1] |
auto[1] |
1423 |
1 |
|
|
T11 |
23 |
|
T23 |
34 |
|
T25 |
46 |