Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117781811

1

T1

36163

T2

4388

T3

222055

auto[1]

1590638

1

T1

1089

T2

693

T3

3663

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117788798

1

T1

35569

T2

4982

T3

220372

auto[1]

1583651

1

T1

1683

T2

99

T3

5346

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8652457	1			T1	8571		T2	895		T3	16557
auto[IdleSt]	23743478	1			T1	5579		T2	2032		T3	5250
auto[ClkMuxSt]	38235	1			T1	46		T2	8		T3	92
auto[CntIncrSt]	37891	1			T1	46		T2	8		T3	92
auto[CntProgSt]	1904114	1			T1	79		T2	330		T3	1899
auto[TransCheckSt]	29413	1			T1	33		T3	56		T12	1
auto[TokenHashSt]	45708214	1			T1	9352		T3	172799		T12	37
auto[FlashRmaSt]	38852	1			T1	41		T3	62		T13	73
auto[TokenCheck0St]	13751	1			T1	22		T3	24		T13	20
auto[TokenCheck1St]	10454	1			T1	15		T3	17		T13	19
auto[TransProgSt]	506405	1			T1	28		T3	431		T13	82
auto[PostTransSt]	14452456	1			T1	7041		T2	660		T3	11729
auto[ScrapSt]	151866	1			T3	16		T13	9		T6	1349
auto[EscalateSt]	8417970	1			T1	3909		T2	1148		T3	11572
auto[InvalidSt]	15664499	1			T1	2490		T3	5110		T15	1090

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2394	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	15664499	1			T1	2490		T3	5110		T15	1090
EscalateSt	8417970	1			T1	3909		T2	1148		T3	11572
ScrapSt	151866	1			T3	16		T13	9		T6	1349
PostTransSt	14452456	1			T1	7041		T2	660		T3	11729
TransProgSt	506405	1			T1	28		T3	431		T13	82
TokenCheck1St	10454	1			T1	15		T3	17		T13	19
TokenCheck0St	13751	1			T1	22		T3	24		T13	20
FlashRmaSt	38852	1			T1	41		T3	62		T13	73
TokenHashSt	45708214	1			T1	9352		T3	172799		T12	37
TransCheckSt	29413	1			T1	33		T3	56		T12	1
CntProgSt	1904114	1			T1	79		T2	330		T3	1899
CntIncrSt	37891	1			T1	46		T2	8		T3	92
ClkMuxSt	38235	1			T1	46		T2	8		T3	92
IdleSt	23743478	1			T1	5579		T2	2032		T3	5250
ResetSt	8652457	1			T1	8571		T2	895		T3	16557
arcs[ResetSt=>IdleSt]	60195	1			T1	62		T2	9		T3	175
arcs[IdleSt=>ScrapSt]	294	1			T3	1		T13	3		T6	1
arcs[IdleSt=>ClkMuxSt]	37955	1			T1	46		T2	8		T3	92
arcs[ClkMuxSt=>CntIncrSt]	37891	1			T1	46		T2	8		T3	92
arcs[CntIncrSt=>PostTransSt]	2003	1			T3	13		T14	5		T11	11
arcs[CntIncrSt=>CntProgSt]	35819	1			T1	46		T2	8		T3	79
arcs[CntProgSt=>PostTransSt]	5221	1			T1	13		T2	8		T3	23
arcs[CntProgSt=>TransCheckSt]	29413	1			T1	33		T3	56		T12	1
arcs[TransCheckSt=>PostTransSt]	3865	1			T3	7		T14	10		T22	46
arcs[TransCheckSt=>TokenHashSt]	25419	1			T1	33		T3	49		T12	1
arcs[TokenHashSt=>PostTransSt]	10913	1			T1	11		T3	25		T12	1
arcs[TokenHashSt=>FlashRmaSt]	13852	1			T1	22		T3	24		T13	24
arcs[FlashRmaSt=>TokenCheck0St]	13751	1			T1	22		T3	24		T13	20
arcs[TokenCheck0St=>PostTransSt]	3262	1			T1	7		T3	7		T14	5
arcs[TokenCheck0St=>TokenCheck1St]	10454	1			T1	15		T3	17		T13	19
arcs[TokenCheck1St=>PostTransSt]	629	1			T1	1		T14	1		T22	8
arcs[TransProgSt=>PostTransSt]	8909	1			T1	14		T3	17		T13	5
arcs[IdleSt=>EscalateSt]	174	1			T13	6		T49	6		T42	5
arcs[ClkMuxSt=>EscalateSt]	64	1			T13	1		T20	3		T49	1
arcs[CntIncrSt=>EscalateSt]	69	1			T20	3		T49	2		T42	4
arcs[CntProgSt=>EscalateSt]	1185	1			T13	32		T20	49		T49	18
arcs[TransCheckSt=>EscalateSt]	129	1			T13	1		T20	1		T49	9
arcs[TokenHashSt=>EscalateSt]	653	1			T13	10		T20	12		T23	2
arcs[FlashRmaSt=>EscalateSt]	101	1			T13	4		T14	1		T20	1
arcs[TokenCheck0St=>EscalateSt]	35	1			T13	1		T20	1		T49	1
arcs[TokenCheck1St=>EscalateSt]	140	1			T13	1		T20	2		T49	4
arcs[TransProgSt=>EscalateSt]	776	1			T13	13		T20	21		T49	12
arcs[PostTransSt=>EscalateSt]	5458	1			T1	13		T2	8		T3	23
arcs[InvalidSt=>EscalateSt]	17041	1			T1	15		T3	68		T15	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8652275	1			T1	8571		T2	895		T3	16557
auto[0]	auto[IdleSt]	23743370	1			T1	5579		T2	2032		T3	5250
auto[0]	auto[ClkMuxSt]	38187	1			T1	46		T2	8		T3	92
auto[0]	auto[CntIncrSt]	37847	1			T1	46		T2	8		T3	92
auto[0]	auto[CntProgSt]	1903316	1			T1	79		T2	330		T3	1899
auto[0]	auto[TransCheckSt]	29321	1			T1	33		T3	56		T12	1
auto[0]	auto[TokenHashSt]	45707787	1			T1	9352		T3	172799		T12	37
auto[0]	auto[FlashRmaSt]	38781	1			T1	41		T3	62		T13	70
auto[0]	auto[TokenCheck0St]	13728	1			T1	22		T3	24		T13	19
auto[0]	auto[TokenCheck1St]	10362	1			T1	15		T3	17		T13	19
auto[0]	auto[TransProgSt]	505900	1			T1	28		T3	431		T13	73
auto[0]	auto[PostTransSt]	14449655	1			T1	7033		T2	653		T3	11723
auto[0]	auto[ScrapSt]	151830	1			T3	16		T13	7		T6	1349
auto[0]	auto[EscalateSt]	6841139	1			T1	2831		T2	462		T3	7946
auto[0]	auto[InvalidSt]	15655919	1			T1	2487		T3	5079		T15	1088
auto[1]	auto[ResetSt]	182	1			T13	5		T20	4		T49	7
auto[1]	auto[IdleSt]	108	1			T13	2		T49	3		T42	3
auto[1]	auto[ClkMuxSt]	48	1			T20	2		T49	1		T42	1
auto[1]	auto[CntIncrSt]	44	1			T20	2		T49	1		T42	4
auto[1]	auto[CntProgSt]	798	1			T13	21		T20	37		T49	12
auto[1]	auto[TransCheckSt]	92	1			T20	1		T49	8		T192	1
auto[1]	auto[TokenHashSt]	427	1			T13	6		T20	7		T23	1
auto[1]	auto[FlashRmaSt]	71	1			T13	3		T20	1		T49	1
auto[1]	auto[TokenCheck0St]	23	1			T13	1		T49	1		T143	1
auto[1]	auto[TokenCheck1St]	92	1			T20	2		T49	4		T42	3
auto[1]	auto[TransProgSt]	505	1			T13	9		T20	19		T49	9
auto[1]	auto[PostTransSt]	2801	1			T1	8		T2	7		T3	6
auto[1]	auto[ScrapSt]	36	1			T13	2		T49	1		T193	2
auto[1]	auto[EscalateSt]	1576831	1			T1	1078		T2	686		T3	3626
auto[1]	auto[InvalidSt]	8580	1			T1	3		T3	31		T15	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8652249	1			T1	8571		T2	895		T3	16557
auto[0]	auto[IdleSt]	23743352	1			T1	5579		T2	2032		T3	5250
auto[0]	auto[ClkMuxSt]	38195	1			T1	46		T2	8		T3	92
auto[0]	auto[CntIncrSt]	37838	1			T1	46		T2	8		T3	92
auto[0]	auto[CntProgSt]	1903329	1			T1	79		T2	330		T3	1899
auto[0]	auto[TransCheckSt]	29337	1			T1	33		T3	56		T12	1
auto[0]	auto[TokenHashSt]	45707765	1			T1	9352		T3	172799		T12	37
auto[0]	auto[FlashRmaSt]	38779	1			T1	41		T3	62		T13	71
auto[0]	auto[TokenCheck0St]	13731	1			T1	22		T3	24		T13	20
auto[0]	auto[TokenCheck1St]	10364	1			T1	15		T3	17		T13	18
auto[0]	auto[TransProgSt]	505873	1			T1	28		T3	431		T13	71
auto[0]	auto[PostTransSt]	14449729	1			T1	7036		T2	659		T3	11712
auto[0]	auto[ScrapSt]	151840	1			T3	16		T13	7		T6	1349
auto[0]	auto[EscalateSt]	6847985	1			T1	2243		T2	1050		T3	6280
auto[0]	auto[InvalidSt]	15656038	1			T1	2478		T3	5073		T15	1087
auto[1]	auto[ResetSt]	208	1			T13	2		T20	4		T49	5
auto[1]	auto[IdleSt]	126	1			T13	5		T49	4		T42	4
auto[1]	auto[ClkMuxSt]	40	1			T13	1		T20	2		T49	1
auto[1]	auto[CntIncrSt]	53	1			T20	2		T49	2		T42	4
auto[1]	auto[CntProgSt]	785	1			T13	20		T20	33		T49	11
auto[1]	auto[TransCheckSt]	76	1			T13	1		T49	1		T192	1
auto[1]	auto[TokenHashSt]	449	1			T13	6		T20	8		T23	1
auto[1]	auto[FlashRmaSt]	73	1			T13	2		T14	1		T20	1
auto[1]	auto[TokenCheck0St]	20	1			T20	1		T49	1		T143	1
auto[1]	auto[TokenCheck1St]	90	1			T13	1		T20	1		T49	2
auto[1]	auto[TransProgSt]	532	1			T13	11		T20	11		T49	7
auto[1]	auto[PostTransSt]	2727	1			T1	5		T2	1		T3	17
auto[1]	auto[ScrapSt]	26	1			T13	2		T49	1		T50	1
auto[1]	auto[EscalateSt]	1569985	1			T1	1666		T2	98		T3	5292
auto[1]	auto[InvalidSt]	8461	1			T1	12		T3	37		T15	3