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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 97.92 95.75 93.40 100.00 98.52 98.51 96.11


Total test records in report: 998
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T141 /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3227712435 Jul 22 07:23:11 PM PDT 24 Jul 22 07:26:24 PM PDT 24 156062491485 ps
T810 /workspace/coverage/default/29.lc_ctrl_security_escalation.1989667012 Jul 22 07:24:23 PM PDT 24 Jul 22 07:25:25 PM PDT 24 1422145982 ps
T811 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2718767422 Jul 22 07:23:28 PM PDT 24 Jul 22 07:24:01 PM PDT 24 458441589 ps
T812 /workspace/coverage/default/4.lc_ctrl_stress_all.1587011109 Jul 22 07:24:14 PM PDT 24 Jul 22 07:29:45 PM PDT 24 21779678179 ps
T813 /workspace/coverage/default/9.lc_ctrl_alert_test.2811773550 Jul 22 07:24:57 PM PDT 24 Jul 22 07:26:05 PM PDT 24 92147236 ps
T814 /workspace/coverage/default/15.lc_ctrl_jtag_errors.3897133204 Jul 22 07:22:58 PM PDT 24 Jul 22 07:23:56 PM PDT 24 3388289478 ps
T815 /workspace/coverage/default/6.lc_ctrl_jtag_priority.904315114 Jul 22 07:23:18 PM PDT 24 Jul 22 07:23:50 PM PDT 24 5384494430 ps
T816 /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2602620408 Jul 22 07:20:59 PM PDT 24 Jul 22 07:21:35 PM PDT 24 26779877 ps
T817 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2132391400 Jul 22 07:25:55 PM PDT 24 Jul 22 07:27:26 PM PDT 24 686259133 ps
T818 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4047278936 Jul 22 07:22:07 PM PDT 24 Jul 22 07:22:50 PM PDT 24 1219991859 ps
T819 /workspace/coverage/default/21.lc_ctrl_alert_test.3318102211 Jul 22 07:23:47 PM PDT 24 Jul 22 07:24:13 PM PDT 24 83617761 ps
T820 /workspace/coverage/default/16.lc_ctrl_state_post_trans.537899585 Jul 22 07:23:10 PM PDT 24 Jul 22 07:23:42 PM PDT 24 340367669 ps
T821 /workspace/coverage/default/38.lc_ctrl_alert_test.227259957 Jul 22 07:25:06 PM PDT 24 Jul 22 07:26:19 PM PDT 24 17615326 ps
T822 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1421203408 Jul 22 07:23:41 PM PDT 24 Jul 22 07:24:31 PM PDT 24 3651493727 ps
T823 /workspace/coverage/default/4.lc_ctrl_jtag_errors.4168583592 Jul 22 07:23:33 PM PDT 24 Jul 22 07:24:26 PM PDT 24 2338322462 ps
T824 /workspace/coverage/default/23.lc_ctrl_smoke.2139312136 Jul 22 07:24:02 PM PDT 24 Jul 22 07:24:36 PM PDT 24 29971828 ps
T825 /workspace/coverage/default/47.lc_ctrl_sec_mubi.2969380479 Jul 22 07:26:17 PM PDT 24 Jul 22 07:27:46 PM PDT 24 289480650 ps
T826 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3276949562 Jul 22 07:23:48 PM PDT 24 Jul 22 07:24:21 PM PDT 24 823511365 ps
T827 /workspace/coverage/default/44.lc_ctrl_smoke.2423457076 Jul 22 07:25:49 PM PDT 24 Jul 22 07:27:09 PM PDT 24 31321190 ps
T828 /workspace/coverage/default/37.lc_ctrl_state_failure.4171184956 Jul 22 07:24:58 PM PDT 24 Jul 22 07:26:32 PM PDT 24 892560263 ps
T829 /workspace/coverage/default/4.lc_ctrl_alert_test.2914697789 Jul 22 07:23:33 PM PDT 24 Jul 22 07:23:53 PM PDT 24 15671510 ps
T830 /workspace/coverage/default/26.lc_ctrl_security_escalation.3862683473 Jul 22 07:24:10 PM PDT 24 Jul 22 07:25:06 PM PDT 24 1915611058 ps
T831 /workspace/coverage/default/47.lc_ctrl_security_escalation.3614559942 Jul 22 07:26:09 PM PDT 24 Jul 22 07:27:36 PM PDT 24 413698264 ps
T832 /workspace/coverage/default/18.lc_ctrl_prog_failure.1181390307 Jul 22 07:23:17 PM PDT 24 Jul 22 07:23:40 PM PDT 24 23549003 ps
T833 /workspace/coverage/default/38.lc_ctrl_state_failure.2727490954 Jul 22 07:25:07 PM PDT 24 Jul 22 07:26:50 PM PDT 24 975350451 ps
T834 /workspace/coverage/default/3.lc_ctrl_jtag_access.3858933620 Jul 22 07:20:53 PM PDT 24 Jul 22 07:21:22 PM PDT 24 494311604 ps
T835 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1200606 Jul 22 07:23:10 PM PDT 24 Jul 22 07:23:37 PM PDT 24 2187418339 ps
T836 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1172172334 Jul 22 07:22:09 PM PDT 24 Jul 22 07:22:41 PM PDT 24 40860423 ps
T79 /workspace/coverage/default/4.lc_ctrl_sec_cm.79050181 Jul 22 07:23:33 PM PDT 24 Jul 22 07:24:16 PM PDT 24 229534109 ps
T837 /workspace/coverage/default/46.lc_ctrl_smoke.728076830 Jul 22 07:26:06 PM PDT 24 Jul 22 07:27:26 PM PDT 24 39405926 ps
T838 /workspace/coverage/default/23.lc_ctrl_sec_mubi.2141465239 Jul 22 07:25:01 PM PDT 24 Jul 22 07:26:23 PM PDT 24 1347639684 ps
T839 /workspace/coverage/default/23.lc_ctrl_security_escalation.2465292509 Jul 22 07:24:01 PM PDT 24 Jul 22 07:24:47 PM PDT 24 663891589 ps
T840 /workspace/coverage/default/14.lc_ctrl_alert_test.1663043460 Jul 22 07:22:45 PM PDT 24 Jul 22 07:23:14 PM PDT 24 26492817 ps
T841 /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4232047789 Jul 22 07:24:14 PM PDT 24 Jul 22 07:25:05 PM PDT 24 716194907 ps
T842 /workspace/coverage/default/19.lc_ctrl_alert_test.4025631092 Jul 22 07:23:37 PM PDT 24 Jul 22 07:23:59 PM PDT 24 18560209 ps
T843 /workspace/coverage/default/24.lc_ctrl_sec_mubi.2024333372 Jul 22 07:24:03 PM PDT 24 Jul 22 07:24:47 PM PDT 24 406117377 ps
T844 /workspace/coverage/default/33.lc_ctrl_prog_failure.1840917201 Jul 22 07:24:51 PM PDT 24 Jul 22 07:25:57 PM PDT 24 74656468 ps
T845 /workspace/coverage/default/32.lc_ctrl_errors.1980713612 Jul 22 07:24:36 PM PDT 24 Jul 22 07:25:38 PM PDT 24 484044378 ps
T846 /workspace/coverage/default/3.lc_ctrl_claim_transition_if.337190718 Jul 22 07:21:04 PM PDT 24 Jul 22 07:21:44 PM PDT 24 24229499 ps
T847 /workspace/coverage/default/43.lc_ctrl_stress_all.1524991934 Jul 22 07:25:47 PM PDT 24 Jul 22 07:30:15 PM PDT 24 19171661015 ps
T848 /workspace/coverage/default/41.lc_ctrl_jtag_access.247742179 Jul 22 07:25:28 PM PDT 24 Jul 22 07:26:55 PM PDT 24 2112282992 ps
T849 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.602326381 Jul 22 07:23:33 PM PDT 24 Jul 22 07:23:58 PM PDT 24 205589669 ps
T850 /workspace/coverage/default/43.lc_ctrl_state_post_trans.2501946261 Jul 22 07:25:35 PM PDT 24 Jul 22 07:27:06 PM PDT 24 93413354 ps
T851 /workspace/coverage/default/19.lc_ctrl_jtag_errors.345669243 Jul 22 07:23:32 PM PDT 24 Jul 22 07:24:31 PM PDT 24 5233521509 ps
T852 /workspace/coverage/default/20.lc_ctrl_security_escalation.2804685911 Jul 22 07:23:42 PM PDT 24 Jul 22 07:24:13 PM PDT 24 1054929524 ps
T853 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1911095479 Jul 22 07:24:11 PM PDT 24 Jul 22 07:25:05 PM PDT 24 955595368 ps
T854 /workspace/coverage/default/20.lc_ctrl_state_failure.3722732119 Jul 22 07:23:37 PM PDT 24 Jul 22 07:24:26 PM PDT 24 1711669677 ps
T855 /workspace/coverage/default/40.lc_ctrl_state_post_trans.3839622689 Jul 22 07:25:18 PM PDT 24 Jul 22 07:26:42 PM PDT 24 254126128 ps
T856 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1854920126 Jul 22 07:24:14 PM PDT 24 Jul 22 07:26:11 PM PDT 24 2414060747 ps
T857 /workspace/coverage/default/5.lc_ctrl_sec_mubi.2951766634 Jul 22 07:21:14 PM PDT 24 Jul 22 07:22:11 PM PDT 24 1271884001 ps
T858 /workspace/coverage/default/35.lc_ctrl_jtag_access.3271327221 Jul 22 07:26:39 PM PDT 24 Jul 22 07:28:09 PM PDT 24 409650569 ps
T859 /workspace/coverage/default/49.lc_ctrl_security_escalation.2328870343 Jul 22 07:26:28 PM PDT 24 Jul 22 07:27:59 PM PDT 24 300383264 ps
T860 /workspace/coverage/default/31.lc_ctrl_stress_all.4042943284 Jul 22 07:24:38 PM PDT 24 Jul 22 07:28:43 PM PDT 24 25159306346 ps
T861 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2416354663 Jul 22 07:20:49 PM PDT 24 Jul 22 07:21:26 PM PDT 24 1039289242 ps
T862 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2577271203 Jul 22 07:23:00 PM PDT 24 Jul 22 07:23:30 PM PDT 24 3720959282 ps
T863 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.257001220 Jul 22 07:26:43 PM PDT 24 Jul 22 07:27:59 PM PDT 24 15444258 ps
T864 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3942693412 Jul 22 07:27:18 PM PDT 24 Jul 22 07:28:37 PM PDT 24 432915869 ps
T865 /workspace/coverage/default/9.lc_ctrl_security_escalation.523055204 Jul 22 07:22:10 PM PDT 24 Jul 22 07:22:52 PM PDT 24 1615026360 ps
T866 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.689864127 Jul 22 07:23:33 PM PDT 24 Jul 22 07:23:53 PM PDT 24 43511490 ps
T867 /workspace/coverage/default/30.lc_ctrl_smoke.2536447088 Jul 22 07:24:21 PM PDT 24 Jul 22 07:25:14 PM PDT 24 83101585 ps
T868 /workspace/coverage/default/36.lc_ctrl_state_post_trans.3743828506 Jul 22 07:26:39 PM PDT 24 Jul 22 07:28:07 PM PDT 24 402165282 ps
T869 /workspace/coverage/default/24.lc_ctrl_jtag_access.2562416640 Jul 22 07:24:05 PM PDT 24 Jul 22 07:24:41 PM PDT 24 391425478 ps
T870 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2757272798 Jul 22 07:20:45 PM PDT 24 Jul 22 07:21:28 PM PDT 24 6729309912 ps
T93 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3005668595 Jul 22 06:46:31 PM PDT 24 Jul 22 06:46:36 PM PDT 24 56988256 ps
T103 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2523076977 Jul 22 06:47:21 PM PDT 24 Jul 22 06:47:25 PM PDT 24 234995317 ps
T104 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3076391424 Jul 22 06:47:31 PM PDT 24 Jul 22 06:47:35 PM PDT 24 194080545 ps
T102 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3925747638 Jul 22 06:46:21 PM PDT 24 Jul 22 06:46:27 PM PDT 24 96792788 ps
T129 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2975585294 Jul 22 06:47:39 PM PDT 24 Jul 22 06:47:43 PM PDT 24 226841798 ps
T167 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.488152374 Jul 22 06:47:29 PM PDT 24 Jul 22 06:47:33 PM PDT 24 43283813 ps
T130 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.102682972 Jul 22 06:46:47 PM PDT 24 Jul 22 06:46:56 PM PDT 24 974491392 ps
T178 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1807632548 Jul 22 06:47:11 PM PDT 24 Jul 22 06:47:21 PM PDT 24 27735056 ps
T105 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3313685888 Jul 22 06:46:32 PM PDT 24 Jul 22 06:46:35 PM PDT 24 95573111 ps
T871 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.772218168 Jul 22 06:47:29 PM PDT 24 Jul 22 06:47:33 PM PDT 24 15659935 ps
T179 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3425142090 Jul 22 06:47:33 PM PDT 24 Jul 22 06:47:38 PM PDT 24 144070308 ps
T150 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.915424707 Jul 22 06:45:53 PM PDT 24 Jul 22 06:45:57 PM PDT 24 84464354 ps
T126 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1827615888 Jul 22 06:45:48 PM PDT 24 Jul 22 06:45:52 PM PDT 24 534859151 ps
T872 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.242578865 Jul 22 06:47:00 PM PDT 24 Jul 22 06:47:02 PM PDT 24 445178272 ps
T94 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2249827686 Jul 22 06:46:43 PM PDT 24 Jul 22 06:46:47 PM PDT 24 89443537 ps
T180 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4049774880 Jul 22 06:46:58 PM PDT 24 Jul 22 06:47:00 PM PDT 24 32226276 ps
T181 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.399176180 Jul 22 06:47:39 PM PDT 24 Jul 22 06:47:42 PM PDT 24 21121094 ps
T182 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1237184108 Jul 22 06:47:18 PM PDT 24 Jul 22 06:47:23 PM PDT 24 67645311 ps
T127 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2247697601 Jul 22 06:45:49 PM PDT 24 Jul 22 06:45:56 PM PDT 24 560624369 ps
T95 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1891766253 Jul 22 06:47:16 PM PDT 24 Jul 22 06:47:23 PM PDT 24 61236703 ps
T168 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1882442741 Jul 22 06:47:29 PM PDT 24 Jul 22 06:47:33 PM PDT 24 79118457 ps
T97 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.246922363 Jul 22 06:46:32 PM PDT 24 Jul 22 06:46:38 PM PDT 24 78461509 ps
T98 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.968077369 Jul 22 06:47:17 PM PDT 24 Jul 22 06:47:24 PM PDT 24 26244984 ps
T163 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.106674414 Jul 22 06:47:33 PM PDT 24 Jul 22 06:47:38 PM PDT 24 24980533 ps
T873 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1407360572 Jul 22 06:46:41 PM PDT 24 Jul 22 06:46:44 PM PDT 24 35284644 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.615874367 Jul 22 06:46:30 PM PDT 24 Jul 22 06:46:35 PM PDT 24 179096842 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.976372414 Jul 22 06:46:13 PM PDT 24 Jul 22 06:46:19 PM PDT 24 776897048 ps
T875 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3622946332 Jul 22 06:46:41 PM PDT 24 Jul 22 06:46:45 PM PDT 24 1032710218 ps
T183 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3924423431 Jul 22 06:46:15 PM PDT 24 Jul 22 06:46:18 PM PDT 24 45712188 ps
T99 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3164891851 Jul 22 06:48:15 PM PDT 24 Jul 22 06:48:20 PM PDT 24 1399653603 ps
T184 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2123934928 Jul 22 06:47:39 PM PDT 24 Jul 22 06:47:42 PM PDT 24 42770344 ps
T106 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4032640060 Jul 22 06:46:13 PM PDT 24 Jul 22 06:46:17 PM PDT 24 127761694 ps
T876 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2814354281 Jul 22 06:45:49 PM PDT 24 Jul 22 06:45:51 PM PDT 24 54055418 ps
T877 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2448475864 Jul 22 06:45:56 PM PDT 24 Jul 22 06:46:01 PM PDT 24 185878861 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3811711218 Jul 22 06:46:47 PM PDT 24 Jul 22 06:46:51 PM PDT 24 15472260 ps
T116 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2291135830 Jul 22 06:47:50 PM PDT 24 Jul 22 06:47:52 PM PDT 24 46312522 ps
T107 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2572668105 Jul 22 06:48:14 PM PDT 24 Jul 22 06:48:17 PM PDT 24 571628972 ps
T879 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3175376008 Jul 22 06:47:01 PM PDT 24 Jul 22 06:47:04 PM PDT 24 275764318 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2741037294 Jul 22 06:48:09 PM PDT 24 Jul 22 06:48:19 PM PDT 24 373170666 ps
T881 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2094650076 Jul 22 06:46:58 PM PDT 24 Jul 22 06:47:03 PM PDT 24 1337537238 ps
T882 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1220624559 Jul 22 06:47:32 PM PDT 24 Jul 22 06:47:37 PM PDT 24 33892847 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4003986040 Jul 22 06:46:40 PM PDT 24 Jul 22 06:46:43 PM PDT 24 410470332 ps
T169 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3444418262 Jul 22 06:45:49 PM PDT 24 Jul 22 06:45:51 PM PDT 24 14532790 ps
T884 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1020579937 Jul 22 06:47:09 PM PDT 24 Jul 22 06:47:20 PM PDT 24 102172699 ps
T170 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.531281451 Jul 22 06:47:18 PM PDT 24 Jul 22 06:47:23 PM PDT 24 30206699 ps
T110 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2606610094 Jul 22 06:47:30 PM PDT 24 Jul 22 06:47:35 PM PDT 24 77669511 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3209096799 Jul 22 06:46:56 PM PDT 24 Jul 22 06:47:00 PM PDT 24 135658787 ps
T886 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1535208678 Jul 22 06:47:18 PM PDT 24 Jul 22 06:47:24 PM PDT 24 281568731 ps
T171 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2669023452 Jul 22 06:47:23 PM PDT 24 Jul 22 06:47:25 PM PDT 24 16127809 ps
T887 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1932983652 Jul 22 06:47:35 PM PDT 24 Jul 22 06:47:39 PM PDT 24 119079275 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3250983712 Jul 22 06:47:22 PM PDT 24 Jul 22 06:47:31 PM PDT 24 3172624951 ps
T889 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.424283561 Jul 22 06:47:31 PM PDT 24 Jul 22 06:47:35 PM PDT 24 43927138 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2558551347 Jul 22 06:46:28 PM PDT 24 Jul 22 06:46:34 PM PDT 24 47844811 ps
T100 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2558930411 Jul 22 06:46:48 PM PDT 24 Jul 22 06:46:55 PM PDT 24 120047864 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1976168294 Jul 22 06:46:57 PM PDT 24 Jul 22 06:47:23 PM PDT 24 2367334827 ps
T892 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.436085542 Jul 22 06:48:14 PM PDT 24 Jul 22 06:48:17 PM PDT 24 420286625 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3475355875 Jul 22 06:46:15 PM PDT 24 Jul 22 06:46:19 PM PDT 24 38662233 ps
T894 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.686261966 Jul 22 06:48:38 PM PDT 24 Jul 22 06:48:42 PM PDT 24 521535100 ps
T895 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.553194912 Jul 22 06:47:22 PM PDT 24 Jul 22 06:47:25 PM PDT 24 32183716 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3333129253 Jul 22 06:46:29 PM PDT 24 Jul 22 06:46:34 PM PDT 24 55411807 ps
T172 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2398769515 Jul 22 06:46:13 PM PDT 24 Jul 22 06:46:16 PM PDT 24 15890647 ps
T897 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1137884315 Jul 22 06:46:41 PM PDT 24 Jul 22 06:46:44 PM PDT 24 25026268 ps
T898 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2629538898 Jul 22 06:47:42 PM PDT 24 Jul 22 06:47:44 PM PDT 24 12568159 ps
T899 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.11344048 Jul 22 06:46:30 PM PDT 24 Jul 22 06:46:35 PM PDT 24 51181802 ps
T900 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1017944427 Jul 22 06:47:01 PM PDT 24 Jul 22 06:47:02 PM PDT 24 11730575 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1800941444 Jul 22 06:45:54 PM PDT 24 Jul 22 06:45:59 PM PDT 24 55674760 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1455862883 Jul 22 06:46:59 PM PDT 24 Jul 22 06:47:01 PM PDT 24 127578100 ps
T903 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2067477823 Jul 22 06:46:40 PM PDT 24 Jul 22 06:46:46 PM PDT 24 769644689 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2399344705 Jul 22 06:48:15 PM PDT 24 Jul 22 06:48:17 PM PDT 24 52460567 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1465376064 Jul 22 06:46:33 PM PDT 24 Jul 22 06:46:36 PM PDT 24 52216932 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2218284822 Jul 22 06:47:41 PM PDT 24 Jul 22 06:47:45 PM PDT 24 63513977 ps
T907 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2527213959 Jul 22 06:46:39 PM PDT 24 Jul 22 06:46:41 PM PDT 24 46065141 ps
T908 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2518811154 Jul 22 06:46:58 PM PDT 24 Jul 22 06:47:01 PM PDT 24 51534062 ps
T909 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.295028295 Jul 22 06:47:32 PM PDT 24 Jul 22 06:47:40 PM PDT 24 313249014 ps
T910 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4052599599 Jul 22 06:46:58 PM PDT 24 Jul 22 06:47:00 PM PDT 24 65961223 ps
T101 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4124171120 Jul 22 06:46:40 PM PDT 24 Jul 22 06:46:45 PM PDT 24 108158383 ps
T911 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1081160882 Jul 22 06:46:39 PM PDT 24 Jul 22 06:46:42 PM PDT 24 33419375 ps
T117 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2799504494 Jul 22 06:46:39 PM PDT 24 Jul 22 06:46:44 PM PDT 24 97364817 ps
T912 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4056492213 Jul 22 06:47:30 PM PDT 24 Jul 22 06:47:34 PM PDT 24 92850913 ps
T125 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.873473333 Jul 22 06:47:01 PM PDT 24 Jul 22 06:47:03 PM PDT 24 155289301 ps
T913 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3568863285 Jul 22 06:46:31 PM PDT 24 Jul 22 06:46:35 PM PDT 24 113683320 ps
T914 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1789168211 Jul 22 06:47:07 PM PDT 24 Jul 22 06:47:18 PM PDT 24 54584876 ps
T915 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.361169302 Jul 22 06:46:32 PM PDT 24 Jul 22 06:46:42 PM PDT 24 733617291 ps
T916 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.998601405 Jul 22 06:47:44 PM PDT 24 Jul 22 06:47:46 PM PDT 24 19251947 ps
T113 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3160900049 Jul 22 06:47:30 PM PDT 24 Jul 22 06:47:38 PM PDT 24 494194562 ps
T917 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.977168767 Jul 22 06:46:43 PM PDT 24 Jul 22 06:46:48 PM PDT 24 242673080 ps
T918 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4069046078 Jul 22 06:47:17 PM PDT 24 Jul 22 06:47:24 PM PDT 24 145737068 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1147570524 Jul 22 06:45:47 PM PDT 24 Jul 22 06:45:50 PM PDT 24 269596376 ps
T920 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1735497520 Jul 22 06:47:29 PM PDT 24 Jul 22 06:47:34 PM PDT 24 156004660 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.84337733 Jul 22 06:46:57 PM PDT 24 Jul 22 06:47:00 PM PDT 24 83840882 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2080515094 Jul 22 06:46:43 PM PDT 24 Jul 22 06:46:51 PM PDT 24 666811278 ps
T923 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4067525773 Jul 22 06:46:43 PM PDT 24 Jul 22 06:46:50 PM PDT 24 1222553627 ps
T924 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2518918368 Jul 22 06:46:13 PM PDT 24 Jul 22 06:46:17 PM PDT 24 398643453 ps
T111 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2541427116 Jul 22 06:47:18 PM PDT 24 Jul 22 06:47:24 PM PDT 24 271228765 ps
T925 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3486023330 Jul 22 06:47:14 PM PDT 24 Jul 22 06:47:24 PM PDT 24 558890718 ps
T926 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.664177440 Jul 22 06:47:48 PM PDT 24 Jul 22 06:47:51 PM PDT 24 49060519 ps
T927 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1451118686 Jul 22 06:47:29 PM PDT 24 Jul 22 06:47:34 PM PDT 24 173411561 ps
T928 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2835906645 Jul 22 06:46:52 PM PDT 24 Jul 22 06:46:55 PM PDT 24 29138690 ps
T929 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.885367310 Jul 22 06:46:14 PM PDT 24 Jul 22 06:46:21 PM PDT 24 373058964 ps
T930 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.330053071 Jul 22 06:47:47 PM PDT 24 Jul 22 06:47:49 PM PDT 24 97609696 ps
T108 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1099383733 Jul 22 06:46:12 PM PDT 24 Jul 22 06:46:17 PM PDT 24 83645137 ps
T118 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2870044678 Jul 22 06:47:41 PM PDT 24 Jul 22 06:47:45 PM PDT 24 328374029 ps
T931 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4020378047 Jul 22 06:48:21 PM PDT 24 Jul 22 06:48:23 PM PDT 24 20704766 ps
T173 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3508726459 Jul 22 06:45:55 PM PDT 24 Jul 22 06:45:59 PM PDT 24 177112523 ps
T932 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3083619970 Jul 22 06:47:24 PM PDT 24 Jul 22 06:47:26 PM PDT 24 16155212 ps
T933 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.667856666 Jul 22 06:46:38 PM PDT 24 Jul 22 06:46:45 PM PDT 24 746110325 ps
T115 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3088035147 Jul 22 06:47:22 PM PDT 24 Jul 22 06:47:26 PM PDT 24 154480943 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2812389939 Jul 22 06:46:30 PM PDT 24 Jul 22 06:46:34 PM PDT 24 21815690 ps
T935 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.239689620 Jul 22 06:47:02 PM PDT 24 Jul 22 06:47:05 PM PDT 24 290196959 ps
T936 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2334250760 Jul 22 06:47:16 PM PDT 24 Jul 22 06:47:24 PM PDT 24 119985499 ps
T937 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2092872374 Jul 22 06:46:14 PM PDT 24 Jul 22 06:46:18 PM PDT 24 100016584 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1010386181 Jul 22 06:46:39 PM PDT 24 Jul 22 06:46:42 PM PDT 24 200459239 ps
T939 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1875816298 Jul 22 06:46:31 PM PDT 24 Jul 22 06:46:35 PM PDT 24 16701070 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.844139849 Jul 22 06:45:49 PM PDT 24 Jul 22 06:46:07 PM PDT 24 2250287626 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1106971630 Jul 22 06:48:06 PM PDT 24 Jul 22 06:48:09 PM PDT 24 230023899 ps
T942 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3337949350 Jul 22 06:47:31 PM PDT 24 Jul 22 06:47:35 PM PDT 24 23679066 ps
T943 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1657221070 Jul 22 06:48:38 PM PDT 24 Jul 22 06:48:41 PM PDT 24 19151139 ps
T944 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.557654421 Jul 22 06:46:41 PM PDT 24 Jul 22 06:46:44 PM PDT 24 45850948 ps
T112 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2137781199 Jul 22 06:47:33 PM PDT 24 Jul 22 06:47:40 PM PDT 24 116066261 ps
T121 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.146019468 Jul 22 06:46:32 PM PDT 24 Jul 22 06:46:37 PM PDT 24 98926990 ps
T174 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3496083130 Jul 22 06:46:32 PM PDT 24 Jul 22 06:46:36 PM PDT 24 398882882 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2494821636 Jul 22 06:45:53 PM PDT 24 Jul 22 06:45:57 PM PDT 24 20217611 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4082389601 Jul 22 06:46:58 PM PDT 24 Jul 22 06:47:04 PM PDT 24 1165633165 ps
T947 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.775033394 Jul 22 06:47:17 PM PDT 24 Jul 22 06:47:25 PM PDT 24 149761454 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.463139151 Jul 22 06:46:45 PM PDT 24 Jul 22 06:46:49 PM PDT 24 66549844 ps
T949 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.381352116 Jul 22 06:48:39 PM PDT 24 Jul 22 06:48:44 PM PDT 24 203073508 ps
T950 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.583133435 Jul 22 06:47:19 PM PDT 24 Jul 22 06:47:24 PM PDT 24 29205336 ps
T119 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1891530188 Jul 22 06:47:44 PM PDT 24 Jul 22 06:47:48 PM PDT 24 110336804 ps
T951 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2856967783 Jul 22 06:46:58 PM PDT 24 Jul 22 06:47:01 PM PDT 24 176998524 ps
T175 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.560453716 Jul 22 06:48:39 PM PDT 24 Jul 22 06:48:41 PM PDT 24 27502666 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.356415461 Jul 22 06:46:57 PM PDT 24 Jul 22 06:47:00 PM PDT 24 29561747 ps
T953 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1599429033 Jul 22 06:46:43 PM PDT 24 Jul 22 06:46:49 PM PDT 24 837934394 ps
T176 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3302872956 Jul 22 06:46:30 PM PDT 24 Jul 22 06:46:34 PM PDT 24 87578060 ps
T954 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3403579307 Jul 22 06:47:22 PM PDT 24 Jul 22 06:47:24 PM PDT 24 17325459 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.905374073 Jul 22 06:45:49 PM PDT 24 Jul 22 06:45:52 PM PDT 24 312469430 ps
T956 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.943836928 Jul 22 06:47:32 PM PDT 24 Jul 22 06:47:40 PM PDT 24 1873700120 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1842984733 Jul 22 06:46:29 PM PDT 24 Jul 22 06:46:35 PM PDT 24 96214039 ps
T122 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.342557845 Jul 22 06:48:20 PM PDT 24 Jul 22 06:48:24 PM PDT 24 226042111 ps
T958 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.897937816 Jul 22 06:46:12 PM PDT 24 Jul 22 06:46:15 PM PDT 24 480101003 ps
T959 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3018532283 Jul 22 06:46:41 PM PDT 24 Jul 22 06:46:44 PM PDT 24 17566524 ps
T123 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.345441180 Jul 22 06:47:19 PM PDT 24 Jul 22 06:47:25 PM PDT 24 157238066 ps
T960 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1310533240 Jul 22 06:47:29 PM PDT 24 Jul 22 06:47:34 PM PDT 24 50460889 ps
T124 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1497700679 Jul 22 06:47:32 PM PDT 24 Jul 22 06:47:38 PM PDT 24 255291725 ps
T961 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.549961568 Jul 22 06:46:40 PM PDT 24 Jul 22 06:46:43 PM PDT 24 97752721 ps
T962 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1146153178 Jul 22 06:46:47 PM PDT 24 Jul 22 06:46:52 PM PDT 24 55355021 ps
T963 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.224704266 Jul 22 06:47:08 PM PDT 24 Jul 22 06:47:19 PM PDT 24 105774673 ps
T120 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2030498022 Jul 22 06:47:44 PM PDT 24 Jul 22 06:47:48 PM PDT 24 142759852 ps
T964 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2334529277 Jul 22 06:47:34 PM PDT 24 Jul 22 06:47:39 PM PDT 24 239400396 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1183674009 Jul 22 06:47:49 PM PDT 24 Jul 22 06:47:51 PM PDT 24 39069248 ps
T966 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2797965469 Jul 22 06:46:12 PM PDT 24 Jul 22 06:46:14 PM PDT 24 20632894 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4103584313 Jul 22 06:46:32 PM PDT 24 Jul 22 06:46:36 PM PDT 24 68650198 ps
T177 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2385946671 Jul 22 06:47:41 PM PDT 24 Jul 22 06:47:44 PM PDT 24 69746506 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3533234073 Jul 22 06:47:08 PM PDT 24 Jul 22 06:47:19 PM PDT 24 23097733 ps
T969 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2049817869 Jul 22 06:46:47 PM PDT 24 Jul 22 06:46:52 PM PDT 24 49025626 ps
T970 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2810385415 Jul 22 06:47:31 PM PDT 24 Jul 22 06:47:35 PM PDT 24 235833109 ps
T971 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.255324460 Jul 22 06:45:53 PM PDT 24 Jul 22 06:46:05 PM PDT 24 909771451 ps
T972 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1739871152 Jul 22 06:47:18 PM PDT 24 Jul 22 06:47:23 PM PDT 24 20342275 ps
T973 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.377892501 Jul 22 06:46:40 PM PDT 24 Jul 22 06:46:44 PM PDT 24 82103074 ps
T974 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1238414981 Jul 22 06:46:58 PM PDT 24 Jul 22 06:47:00 PM PDT 24 89857821 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2192008605 Jul 22 06:46:41 PM PDT 24 Jul 22 06:46:44 PM PDT 24 64724265 ps
T976 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.912904889 Jul 22 06:46:41 PM PDT 24 Jul 22 06:46:44 PM PDT 24 91994093 ps
T977 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4128094694 Jul 22 06:47:19 PM PDT 24 Jul 22 06:47:24 PM PDT 24 17960943 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3187477073 Jul 22 06:47:07 PM PDT 24 Jul 22 06:47:20 PM PDT 24 389501416 ps
T979 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3237341482 Jul 22 06:46:48 PM PDT 24 Jul 22 06:46:56 PM PDT 24 1544612475 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1052456667 Jul 22 06:46:41 PM PDT 24 Jul 22 06:46:44 PM PDT 24 83111699 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3369905124 Jul 22 06:45:55 PM PDT 24 Jul 22 06:46:04 PM PDT 24 806929652 ps
T982 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2885202413 Jul 22 06:47:32 PM PDT 24 Jul 22 06:47:37 PM PDT 24 138956035 ps
T983 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.226600950 Jul 22 06:46:31 PM PDT 24 Jul 22 06:46:35 PM PDT 24 22273546 ps
T984 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3775405313 Jul 22 06:45:47 PM PDT 24 Jul 22 06:45:49 PM PDT 24 56536151 ps
T985 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3791611078 Jul 22 06:47:30 PM PDT 24 Jul 22 06:47:37 PM PDT 24 384138308 ps
T986 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3424714232 Jul 22 06:46:40 PM PDT 24 Jul 22 06:46:43 PM PDT 24 28256477 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1595667983 Jul 22 06:47:07 PM PDT 24 Jul 22 06:47:19 PM PDT 24 792838680 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.476360963 Jul 22 06:48:31 PM PDT 24 Jul 22 06:48:53 PM PDT 24 15935046790 ps
T989 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.650585965 Jul 22 06:46:40 PM PDT 24 Jul 22 06:46:43 PM PDT 24 22328929 ps
T114 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1463754037 Jul 22 06:47:32 PM PDT 24 Jul 22 06:47:39 PM PDT 24 103229683 ps
T990 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.12958388 Jul 22 06:46:43 PM PDT 24 Jul 22 06:46:46 PM PDT 24 22376661 ps
T991 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3601217977 Jul 22 06:46:57 PM PDT 24 Jul 22 06:47:11 PM PDT 24 2276102683 ps
T992 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1686964532 Jul 22 06:46:15 PM PDT 24 Jul 22 06:46:20 PM PDT 24 112914126 ps
T993 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1729005248 Jul 22 06:46:29 PM PDT 24 Jul 22 06:46:34 PM PDT 24 54394726 ps
T994 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3128544877 Jul 22 06:47:20 PM PDT 24 Jul 22 06:47:24 PM PDT 24 13221259 ps
T995 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2769474570 Jul 22 06:47:25 PM PDT 24 Jul 22 06:47:27 PM PDT 24 428811375 ps
T109 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3097170427 Jul 22 06:47:26 PM PDT 24 Jul 22 06:47:29 PM PDT 24 43333681 ps
T996 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1823065871 Jul 22 06:47:28 PM PDT 24 Jul 22 06:47:32 PM PDT 24 43513782 ps
T997 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.426124849 Jul 22 06:47:11 PM PDT 24 Jul 22 06:47:30 PM PDT 24 974880390 ps
T998 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2912209837 Jul 22 06:47:09 PM PDT 24 Jul 22 06:47:20 PM PDT 24 23511749 ps

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.319184245
Short name T1
Test name
Test status
Simulation time 384055563 ps
CPU time 9.95 seconds
Started Jul 22 07:25:22 PM PDT 24
Finished Jul 22 07:26:53 PM PDT 24
Peak memory 217948 kb
Host smart-636f494b-262b-4f59-82ee-6cfe03df6dd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319184245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.319184245
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3439707868
Short name T23
Test name
Test status
Simulation time 59249366018 ps
CPU time 2187.71 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 08:00:20 PM PDT 24
Peak memory 1538008 kb
Host smart-fdc1d338-3d31-4868-9987-750d8e13fe49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3439707868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3439707868
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2125002027
Short name T13
Test name
Test status
Simulation time 1431677583 ps
CPU time 12.51 seconds
Started Jul 22 07:25:21 PM PDT 24
Finished Jul 22 07:26:53 PM PDT 24
Peak memory 217924 kb
Host smart-cd60ea56-e247-4f2e-a569-8c5f088987c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125002027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2125002027
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3005668595
Short name T93
Test name
Test status
Simulation time 56988256 ps
CPU time 2.44 seconds
Started Jul 22 06:46:31 PM PDT 24
Finished Jul 22 06:46:36 PM PDT 24
Peak memory 217880 kb
Host smart-9a26e3a2-02e7-4b70-b1b1-f29d560e9e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300566
8595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3005668595
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4063845339
Short name T51
Test name
Test status
Simulation time 3882156308 ps
CPU time 43.12 seconds
Started Jul 22 07:20:49 PM PDT 24
Finished Jul 22 07:21:54 PM PDT 24
Peak memory 269204 kb
Host smart-fcd1d479-3fbe-4a20-9a9c-6c59b385f335
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063845339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4063845339
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1099686568
Short name T20
Test name
Test status
Simulation time 402682377 ps
CPU time 11.28 seconds
Started Jul 22 07:24:18 PM PDT 24
Finished Jul 22 07:25:18 PM PDT 24
Peak memory 217920 kb
Host smart-7590e02e-e746-41c4-8e65-e807841df137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099686568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1099686568
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3280117139
Short name T22
Test name
Test status
Simulation time 339364755 ps
CPU time 8.91 seconds
Started Jul 22 07:21:23 PM PDT 24
Finished Jul 22 07:22:14 PM PDT 24
Peak memory 225572 kb
Host smart-c33656ff-df86-4fea-88d3-4cf7bfd31260
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280117139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
280117139
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.488152374
Short name T167
Test name
Test status
Simulation time 43283813 ps
CPU time 0.81 seconds
Started Jul 22 06:47:29 PM PDT 24
Finished Jul 22 06:47:33 PM PDT 24
Peak memory 209008 kb
Host smart-c46b6af3-1546-4add-9494-4ff6c3ab09e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488152374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.488152374
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2404684987
Short name T9
Test name
Test status
Simulation time 532806015 ps
CPU time 5.23 seconds
Started Jul 22 07:22:47 PM PDT 24
Finished Jul 22 07:23:18 PM PDT 24
Peak memory 217272 kb
Host smart-c9d28f14-e0b7-4d51-bc69-470d2b732e28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404684987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2404684987
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3160900049
Short name T113
Test name
Test status
Simulation time 494194562 ps
CPU time 4.38 seconds
Started Jul 22 06:47:30 PM PDT 24
Finished Jul 22 06:47:38 PM PDT 24
Peak memory 217792 kb
Host smart-d7981862-83b3-42e2-8b08-4e0896f0dca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160900049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3160900049
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1839488148
Short name T147
Test name
Test status
Simulation time 475063711 ps
CPU time 9.47 seconds
Started Jul 22 07:24:56 PM PDT 24
Finished Jul 22 07:26:11 PM PDT 24
Peak memory 217848 kb
Host smart-d42a0084-c2ba-4eef-8632-1fc69a17fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839488148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1839488148
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2551106936
Short name T76
Test name
Test status
Simulation time 29076503 ps
CPU time 1.29 seconds
Started Jul 22 07:24:57 PM PDT 24
Finished Jul 22 07:26:05 PM PDT 24
Peak memory 208652 kb
Host smart-8b80c0b3-cab4-4bba-9475-bb3d89c425da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551106936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2551106936
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.968077369
Short name T98
Test name
Test status
Simulation time 26244984 ps
CPU time 1.96 seconds
Started Jul 22 06:47:17 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 217992 kb
Host smart-83c171e2-848b-4c12-b89e-b1e5bdbc65c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968077369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.968077369
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3697399401
Short name T11
Test name
Test status
Simulation time 11880836412 ps
CPU time 286.71 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:29:59 PM PDT 24
Peak memory 283752 kb
Host smart-e88f8918-b304-4570-ba39-ff6e3046306a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3697399401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.3697399401
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.921845911
Short name T253
Test name
Test status
Simulation time 285608994 ps
CPU time 13.49 seconds
Started Jul 22 07:20:47 PM PDT 24
Finished Jul 22 07:21:19 PM PDT 24
Peak memory 218560 kb
Host smart-2d011f7a-816c-482e-8c08-f92a38f7a2e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921845911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.921845911
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2870044678
Short name T118
Test name
Test status
Simulation time 328374029 ps
CPU time 2.69 seconds
Started Jul 22 06:47:41 PM PDT 24
Finished Jul 22 06:47:45 PM PDT 24
Peak memory 222272 kb
Host smart-b33c3b45-22ee-4587-a06b-2e2701644ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870044678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2870044678
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2523076977
Short name T103
Test name
Test status
Simulation time 234995317 ps
CPU time 2.02 seconds
Started Jul 22 06:47:21 PM PDT 24
Finished Jul 22 06:47:25 PM PDT 24
Peak memory 217808 kb
Host smart-389190de-80cf-4ca6-9600-369dccfebccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523076977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2523076977
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2558930411
Short name T100
Test name
Test status
Simulation time 120047864 ps
CPU time 4.46 seconds
Started Jul 22 06:46:48 PM PDT 24
Finished Jul 22 06:46:55 PM PDT 24
Peak memory 217776 kb
Host smart-db5ade8f-2ceb-4986-9c25-c7cede8548de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558930411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2558930411
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.661784083
Short name T19
Test name
Test status
Simulation time 19106527 ps
CPU time 0.91 seconds
Started Jul 22 07:25:24 PM PDT 24
Finished Jul 22 07:26:46 PM PDT 24
Peak memory 211412 kb
Host smart-b7de616b-61c6-4248-b369-4b9c70d670d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661784083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.661784083
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3164891851
Short name T99
Test name
Test status
Simulation time 1399653603 ps
CPU time 4.23 seconds
Started Jul 22 06:48:15 PM PDT 24
Finished Jul 22 06:48:20 PM PDT 24
Peak memory 217868 kb
Host smart-e4ca02ec-debb-41fe-b029-4925f9c97323
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164891851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3164891851
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1099383733
Short name T108
Test name
Test status
Simulation time 83645137 ps
CPU time 2.51 seconds
Started Jul 22 06:46:12 PM PDT 24
Finished Jul 22 06:46:17 PM PDT 24
Peak memory 222512 kb
Host smart-8ae281e4-a48b-4e88-9895-9c203a294892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099383733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1099383733
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3508726459
Short name T173
Test name
Test status
Simulation time 177112523 ps
CPU time 1.22 seconds
Started Jul 22 06:45:55 PM PDT 24
Finished Jul 22 06:45:59 PM PDT 24
Peak memory 209568 kb
Host smart-a0dd0d2a-0b38-43a0-9be0-32cc7fca4d1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508726459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3508726459
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2541427116
Short name T111
Test name
Test status
Simulation time 271228765 ps
CPU time 1.98 seconds
Started Jul 22 06:47:18 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 221484 kb
Host smart-882eb3ba-22c6-4218-8010-e5d85880d1d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541427116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2541427116
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1463754037
Short name T114
Test name
Test status
Simulation time 103229683 ps
CPU time 2.92 seconds
Started Jul 22 06:47:32 PM PDT 24
Finished Jul 22 06:47:39 PM PDT 24
Peak memory 217856 kb
Host smart-7418721a-092c-47db-b248-64465457329f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463754037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1463754037
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2030498022
Short name T120
Test name
Test status
Simulation time 142759852 ps
CPU time 3.61 seconds
Started Jul 22 06:47:44 PM PDT 24
Finished Jul 22 06:47:48 PM PDT 24
Peak memory 217760 kb
Host smart-e1a9492a-f9b1-4248-b551-386d77c4d815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030498022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2030498022
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1941706282
Short name T187
Test name
Test status
Simulation time 31408614 ps
CPU time 0.87 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:21:02 PM PDT 24
Peak memory 208624 kb
Host smart-33a50ceb-7170-447d-a0b8-8e2e57d1d9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941706282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1941706282
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.279303882
Short name T189
Test name
Test status
Simulation time 24709818 ps
CPU time 0.79 seconds
Started Jul 22 07:20:51 PM PDT 24
Finished Jul 22 07:21:16 PM PDT 24
Peak memory 208248 kb
Host smart-8b7f8dbd-25d4-4614-b2c5-e9e8e69de615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279303882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.279303882
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2128876165
Short name T190
Test name
Test status
Simulation time 12898875 ps
CPU time 0.96 seconds
Started Jul 22 07:21:26 PM PDT 24
Finished Jul 22 07:22:08 PM PDT 24
Peak memory 208536 kb
Host smart-c7f871f0-60e0-4444-987e-bca9b37b3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128876165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2128876165
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1270108747
Short name T27
Test name
Test status
Simulation time 681042272 ps
CPU time 37.09 seconds
Started Jul 22 07:24:48 PM PDT 24
Finished Jul 22 07:26:27 PM PDT 24
Peak memory 250600 kb
Host smart-cb49d143-e604-48ef-b8e9-a35f13b35c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270108747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1270108747
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2247697601
Short name T127
Test name
Test status
Simulation time 560624369 ps
CPU time 6.17 seconds
Started Jul 22 06:45:49 PM PDT 24
Finished Jul 22 06:45:56 PM PDT 24
Peak memory 209344 kb
Host smart-3bc7efc7-cf10-493c-b021-b1edea7a056f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247697601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2247697601
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1497700679
Short name T124
Test name
Test status
Simulation time 255291725 ps
CPU time 2.36 seconds
Started Jul 22 06:47:32 PM PDT 24
Finished Jul 22 06:47:38 PM PDT 24
Peak memory 217812 kb
Host smart-7328609a-e535-45ef-8cc6-872146a6a70d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497700679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1497700679
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.873473333
Short name T125
Test name
Test status
Simulation time 155289301 ps
CPU time 1.92 seconds
Started Jul 22 06:47:01 PM PDT 24
Finished Jul 22 06:47:03 PM PDT 24
Peak memory 222456 kb
Host smart-642805a9-4bb4-49f2-a7f1-f3f777bd4dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873473333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.873473333
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2224892562
Short name T56
Test name
Test status
Simulation time 58574587 ps
CPU time 2.88 seconds
Started Jul 22 07:24:56 PM PDT 24
Finished Jul 22 07:26:05 PM PDT 24
Peak memory 217420 kb
Host smart-a7b7a17c-800e-43a5-9101-9cfa2d791036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224892562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2224892562
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2399344705
Short name T904
Test name
Test status
Simulation time 52460567 ps
CPU time 1.48 seconds
Started Jul 22 06:48:15 PM PDT 24
Finished Jul 22 06:48:17 PM PDT 24
Peak memory 209532 kb
Host smart-b2e8053c-266b-442c-9cf8-1f44f8552321
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399344705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2399344705
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3444418262
Short name T169
Test name
Test status
Simulation time 14532790 ps
CPU time 1.15 seconds
Started Jul 22 06:45:49 PM PDT 24
Finished Jul 22 06:45:51 PM PDT 24
Peak memory 219428 kb
Host smart-5baa075c-9ddf-4ca9-8c27-bc21e1c08791
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444418262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3444418262
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.915424707
Short name T150
Test name
Test status
Simulation time 84464354 ps
CPU time 1.65 seconds
Started Jul 22 06:45:53 PM PDT 24
Finished Jul 22 06:45:57 PM PDT 24
Peak memory 217844 kb
Host smart-f8444996-f7ea-439e-ac18-b8ec3afc1525
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915424707 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.915424707
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3775405313
Short name T984
Test name
Test status
Simulation time 56536151 ps
CPU time 0.9 seconds
Started Jul 22 06:45:47 PM PDT 24
Finished Jul 22 06:45:49 PM PDT 24
Peak memory 209440 kb
Host smart-7b81c988-1cf0-4281-bf09-d593c1d85a12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775405313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3775405313
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1147570524
Short name T919
Test name
Test status
Simulation time 269596376 ps
CPU time 1.32 seconds
Started Jul 22 06:45:47 PM PDT 24
Finished Jul 22 06:45:50 PM PDT 24
Peak memory 208076 kb
Host smart-a880a3ca-044a-4820-a3e9-7ca560232649
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147570524 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1147570524
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.844139849
Short name T940
Test name
Test status
Simulation time 2250287626 ps
CPU time 17.36 seconds
Started Jul 22 06:45:49 PM PDT 24
Finished Jul 22 06:46:07 PM PDT 24
Peak memory 209400 kb
Host smart-a004e025-ac98-416e-b272-21b70b2bf23a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844139849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.844139849
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.905374073
Short name T955
Test name
Test status
Simulation time 312469430 ps
CPU time 1.57 seconds
Started Jul 22 06:45:49 PM PDT 24
Finished Jul 22 06:45:52 PM PDT 24
Peak memory 210972 kb
Host smart-e57d6592-bc34-43ea-a5a9-046889fd361a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905374073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.905374073
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1827615888
Short name T126
Test name
Test status
Simulation time 534859151 ps
CPU time 2.31 seconds
Started Jul 22 06:45:48 PM PDT 24
Finished Jul 22 06:45:52 PM PDT 24
Peak memory 217932 kb
Host smart-ca0d0b1d-cfd1-4ab1-b11a-c81a7146198c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182761
5888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1827615888
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2814354281
Short name T876
Test name
Test status
Simulation time 54055418 ps
CPU time 1.27 seconds
Started Jul 22 06:45:49 PM PDT 24
Finished Jul 22 06:45:51 PM PDT 24
Peak memory 209508 kb
Host smart-694c7e3c-d0be-4d12-88b8-f754b118c7ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814354281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2814354281
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1657221070
Short name T943
Test name
Test status
Simulation time 19151139 ps
CPU time 1.45 seconds
Started Jul 22 06:48:38 PM PDT 24
Finished Jul 22 06:48:41 PM PDT 24
Peak memory 209604 kb
Host smart-fd67880e-eea5-4da3-8e17-6dcae6017add
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657221070 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1657221070
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2448475864
Short name T877
Test name
Test status
Simulation time 185878861 ps
CPU time 1.41 seconds
Started Jul 22 06:45:56 PM PDT 24
Finished Jul 22 06:46:01 PM PDT 24
Peak memory 209836 kb
Host smart-1d4f5680-0bdf-4ea8-89be-63f76ac59689
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448475864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2448475864
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.686261966
Short name T894
Test name
Test status
Simulation time 521535100 ps
CPU time 3.25 seconds
Started Jul 22 06:48:38 PM PDT 24
Finished Jul 22 06:48:42 PM PDT 24
Peak memory 217812 kb
Host smart-f3486f08-26ff-46a5-af53-cb71ca6271e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686261966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.686261966
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1823065871
Short name T996
Test name
Test status
Simulation time 43513782 ps
CPU time 1.09 seconds
Started Jul 22 06:47:28 PM PDT 24
Finished Jul 22 06:47:32 PM PDT 24
Peak memory 208924 kb
Host smart-ea63618e-ef20-40db-9a86-3f805ed8f4f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823065871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1823065871
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2797965469
Short name T966
Test name
Test status
Simulation time 20632894 ps
CPU time 1.45 seconds
Started Jul 22 06:46:12 PM PDT 24
Finished Jul 22 06:46:14 PM PDT 24
Peak memory 209616 kb
Host smart-cedff5b4-dfb8-45d5-9aef-c696c9f18b4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797965469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2797965469
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2385946671
Short name T177
Test name
Test status
Simulation time 69746506 ps
CPU time 1.32 seconds
Started Jul 22 06:47:41 PM PDT 24
Finished Jul 22 06:47:44 PM PDT 24
Peak memory 211692 kb
Host smart-2768d9ac-9c3a-4847-9e2d-e01ec3b65473
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385946671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2385946671
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2092872374
Short name T937
Test name
Test status
Simulation time 100016584 ps
CPU time 1.33 seconds
Started Jul 22 06:46:14 PM PDT 24
Finished Jul 22 06:46:18 PM PDT 24
Peak memory 222904 kb
Host smart-b51d75da-5db5-4d5e-a80d-16041a573b8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092872374 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2092872374
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2494821636
Short name T945
Test name
Test status
Simulation time 20217611 ps
CPU time 0.95 seconds
Started Jul 22 06:45:53 PM PDT 24
Finished Jul 22 06:45:57 PM PDT 24
Peak memory 209088 kb
Host smart-6f63abc4-9010-4316-87ef-dcf98279efc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494821636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2494821636
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.436085542
Short name T892
Test name
Test status
Simulation time 420286625 ps
CPU time 3.05 seconds
Started Jul 22 06:48:14 PM PDT 24
Finished Jul 22 06:48:17 PM PDT 24
Peak memory 208736 kb
Host smart-7c5d9667-8b5f-4acb-8798-5f5a829fe1c0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436085542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.436085542
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3369905124
Short name T981
Test name
Test status
Simulation time 806929652 ps
CPU time 4.72 seconds
Started Jul 22 06:45:55 PM PDT 24
Finished Jul 22 06:46:04 PM PDT 24
Peak memory 208836 kb
Host smart-9130d63c-a083-46ee-ad3b-ffe4baa50e67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369905124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3369905124
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.255324460
Short name T971
Test name
Test status
Simulation time 909771451 ps
CPU time 11.75 seconds
Started Jul 22 06:45:53 PM PDT 24
Finished Jul 22 06:46:05 PM PDT 24
Peak memory 209396 kb
Host smart-ce5011f2-ae89-4888-a0de-4ba8a48887bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255324460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.255324460
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2975585294
Short name T129
Test name
Test status
Simulation time 226841798 ps
CPU time 2.01 seconds
Started Jul 22 06:47:39 PM PDT 24
Finished Jul 22 06:47:43 PM PDT 24
Peak memory 210968 kb
Host smart-21589e7e-ce7a-4809-9bd4-e80c6baa6695
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975585294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2975585294
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1800941444
Short name T901
Test name
Test status
Simulation time 55674760 ps
CPU time 1.64 seconds
Started Jul 22 06:45:54 PM PDT 24
Finished Jul 22 06:45:59 PM PDT 24
Peak memory 217808 kb
Host smart-c770874c-3698-4428-90a2-4c210ff7545c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180094
1444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1800941444
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2218284822
Short name T906
Test name
Test status
Simulation time 63513977 ps
CPU time 2.3 seconds
Started Jul 22 06:47:41 PM PDT 24
Finished Jul 22 06:47:45 PM PDT 24
Peak memory 209500 kb
Host smart-e4be0ec7-0b22-428b-a46d-66ceb22798d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218284822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2218284822
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.399176180
Short name T181
Test name
Test status
Simulation time 21121094 ps
CPU time 1.22 seconds
Started Jul 22 06:47:39 PM PDT 24
Finished Jul 22 06:47:42 PM PDT 24
Peak memory 209692 kb
Host smart-d79ee1c4-0727-42b3-828b-25cd89dc0897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399176180 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.399176180
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1052456667
Short name T980
Test name
Test status
Simulation time 83111699 ps
CPU time 1.3 seconds
Started Jul 22 06:46:41 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 209684 kb
Host smart-27d62f10-b121-46ad-a83c-2ed0442af90a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052456667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1052456667
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2572668105
Short name T107
Test name
Test status
Simulation time 571628972 ps
CPU time 2.89 seconds
Started Jul 22 06:48:14 PM PDT 24
Finished Jul 22 06:48:17 PM PDT 24
Peak memory 217804 kb
Host smart-a0a0267a-2fed-40fb-a951-03cad82f7584
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572668105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2572668105
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4128094694
Short name T977
Test name
Test status
Simulation time 17960943 ps
CPU time 1.23 seconds
Started Jul 22 06:47:19 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 217880 kb
Host smart-025d1ed2-82d9-478a-b7e3-3a5c12cafbbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128094694 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4128094694
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.553194912
Short name T895
Test name
Test status
Simulation time 32183716 ps
CPU time 0.88 seconds
Started Jul 22 06:47:22 PM PDT 24
Finished Jul 22 06:47:25 PM PDT 24
Peak memory 209588 kb
Host smart-ee844003-75fe-4dad-9832-b734827f612c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553194912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.553194912
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1237184108
Short name T182
Test name
Test status
Simulation time 67645311 ps
CPU time 1.31 seconds
Started Jul 22 06:47:18 PM PDT 24
Finished Jul 22 06:47:23 PM PDT 24
Peak memory 209592 kb
Host smart-8ffc4b40-4502-4bf5-b9ae-66f342113929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237184108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1237184108
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.775033394
Short name T947
Test name
Test status
Simulation time 149761454 ps
CPU time 2.93 seconds
Started Jul 22 06:47:17 PM PDT 24
Finished Jul 22 06:47:25 PM PDT 24
Peak memory 217820 kb
Host smart-6a5c8d9a-aa02-452b-844c-51dbe4a1e0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775033394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.775033394
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3097170427
Short name T109
Test name
Test status
Simulation time 43333681 ps
CPU time 1.93 seconds
Started Jul 22 06:47:26 PM PDT 24
Finished Jul 22 06:47:29 PM PDT 24
Peak memory 222284 kb
Host smart-97733f3a-84d2-4ecf-969d-d345350a125e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097170427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3097170427
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1739871152
Short name T972
Test name
Test status
Simulation time 20342275 ps
CPU time 1.12 seconds
Started Jul 22 06:47:18 PM PDT 24
Finished Jul 22 06:47:23 PM PDT 24
Peak memory 219836 kb
Host smart-c2511db1-2672-47ae-be0b-a9c4bddc0cb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739871152 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1739871152
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.531281451
Short name T170
Test name
Test status
Simulation time 30206699 ps
CPU time 0.84 seconds
Started Jul 22 06:47:18 PM PDT 24
Finished Jul 22 06:47:23 PM PDT 24
Peak memory 209516 kb
Host smart-a3d4373e-d512-47f6-ad04-5cae23035124
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531281451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.531281451
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.583133435
Short name T950
Test name
Test status
Simulation time 29205336 ps
CPU time 1.5 seconds
Started Jul 22 06:47:19 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 209648 kb
Host smart-ad6ef648-be4f-4a2b-a87b-1eef08eafb39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583133435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.583133435
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.342557845
Short name T122
Test name
Test status
Simulation time 226042111 ps
CPU time 3.47 seconds
Started Jul 22 06:48:20 PM PDT 24
Finished Jul 22 06:48:24 PM PDT 24
Peak memory 222604 kb
Host smart-00886bbe-7f51-4df8-b311-c4b51fcd5eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342557845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.342557845
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4020378047
Short name T931
Test name
Test status
Simulation time 20704766 ps
CPU time 1.15 seconds
Started Jul 22 06:48:21 PM PDT 24
Finished Jul 22 06:48:23 PM PDT 24
Peak memory 217960 kb
Host smart-90ed9990-bb18-49e5-85cc-5894e9d4769d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020378047 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4020378047
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2669023452
Short name T171
Test name
Test status
Simulation time 16127809 ps
CPU time 0.9 seconds
Started Jul 22 06:47:23 PM PDT 24
Finished Jul 22 06:47:25 PM PDT 24
Peak memory 217784 kb
Host smart-7d96db96-4be8-4290-a06b-7b89ed6e0da9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669023452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2669023452
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4069046078
Short name T918
Test name
Test status
Simulation time 145737068 ps
CPU time 2.11 seconds
Started Jul 22 06:47:17 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 217768 kb
Host smart-fb5957ad-7cb5-41aa-a3b1-f51739ddfb2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069046078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4069046078
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.345441180
Short name T123
Test name
Test status
Simulation time 157238066 ps
CPU time 2.19 seconds
Started Jul 22 06:47:19 PM PDT 24
Finished Jul 22 06:47:25 PM PDT 24
Peak memory 222144 kb
Host smart-7365f30b-ff6e-44a6-a4e9-c1c60088f714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345441180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.345441180
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1220624559
Short name T882
Test name
Test status
Simulation time 33892847 ps
CPU time 1.4 seconds
Started Jul 22 06:47:32 PM PDT 24
Finished Jul 22 06:47:37 PM PDT 24
Peak memory 219176 kb
Host smart-ae2b8b1b-a9a7-43b0-bb5b-ccf2c29564ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220624559 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1220624559
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3128544877
Short name T994
Test name
Test status
Simulation time 13221259 ps
CPU time 1.04 seconds
Started Jul 22 06:47:20 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 209016 kb
Host smart-0c4ebec7-aca6-49d1-8eb8-d4d4f0d81a82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128544877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3128544877
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4056492213
Short name T912
Test name
Test status
Simulation time 92850913 ps
CPU time 1.14 seconds
Started Jul 22 06:47:30 PM PDT 24
Finished Jul 22 06:47:34 PM PDT 24
Peak memory 218000 kb
Host smart-dbbb474e-390c-446e-9ae2-e0dd77a5e5cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056492213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.4056492213
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2334250760
Short name T936
Test name
Test status
Simulation time 119985499 ps
CPU time 2.95 seconds
Started Jul 22 06:47:16 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 217792 kb
Host smart-689227df-9972-41a2-8ff3-722cbafb2dc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334250760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2334250760
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1735497520
Short name T920
Test name
Test status
Simulation time 156004660 ps
CPU time 2 seconds
Started Jul 22 06:47:29 PM PDT 24
Finished Jul 22 06:47:34 PM PDT 24
Peak memory 217872 kb
Host smart-e94c0848-b949-4566-93ea-feacda53680a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735497520 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1735497520
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1882442741
Short name T168
Test name
Test status
Simulation time 79118457 ps
CPU time 0.95 seconds
Started Jul 22 06:47:29 PM PDT 24
Finished Jul 22 06:47:33 PM PDT 24
Peak memory 209572 kb
Host smart-60b5069e-36c6-437b-9249-f7d36ff6dfe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882442741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1882442741
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1451118686
Short name T927
Test name
Test status
Simulation time 173411561 ps
CPU time 1.68 seconds
Started Jul 22 06:47:29 PM PDT 24
Finished Jul 22 06:47:34 PM PDT 24
Peak memory 209720 kb
Host smart-d2747ea4-7656-4e10-b484-1510954b7ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451118686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1451118686
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2606610094
Short name T110
Test name
Test status
Simulation time 77669511 ps
CPU time 2.47 seconds
Started Jul 22 06:47:30 PM PDT 24
Finished Jul 22 06:47:35 PM PDT 24
Peak memory 217944 kb
Host smart-c4f1d738-bfdc-48f1-a32a-ed74133f0564
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606610094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2606610094
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2137781199
Short name T112
Test name
Test status
Simulation time 116066261 ps
CPU time 3.16 seconds
Started Jul 22 06:47:33 PM PDT 24
Finished Jul 22 06:47:40 PM PDT 24
Peak memory 222796 kb
Host smart-0745e4c5-edab-4f77-a090-05587b1810e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137781199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2137781199
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2810385415
Short name T970
Test name
Test status
Simulation time 235833109 ps
CPU time 1.64 seconds
Started Jul 22 06:47:31 PM PDT 24
Finished Jul 22 06:47:35 PM PDT 24
Peak memory 217924 kb
Host smart-3f86a0ad-615f-433e-99c1-45b10b8c840f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810385415 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2810385415
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.330053071
Short name T930
Test name
Test status
Simulation time 97609696 ps
CPU time 1.13 seconds
Started Jul 22 06:47:47 PM PDT 24
Finished Jul 22 06:47:49 PM PDT 24
Peak memory 209688 kb
Host smart-74b45f99-9992-4232-8a44-e9e4888b27d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330053071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.330053071
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3791611078
Short name T985
Test name
Test status
Simulation time 384138308 ps
CPU time 3.96 seconds
Started Jul 22 06:47:30 PM PDT 24
Finished Jul 22 06:47:37 PM PDT 24
Peak memory 217816 kb
Host smart-4d160e98-fb38-417d-8e89-a3e3d400edeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791611078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3791611078
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3337949350
Short name T942
Test name
Test status
Simulation time 23679066 ps
CPU time 1.63 seconds
Started Jul 22 06:47:31 PM PDT 24
Finished Jul 22 06:47:35 PM PDT 24
Peak memory 217904 kb
Host smart-0a0ff02c-0daf-4811-aadb-9b4faa6ff5c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337949350 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3337949350
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1932983652
Short name T887
Test name
Test status
Simulation time 119079275 ps
CPU time 1.04 seconds
Started Jul 22 06:47:35 PM PDT 24
Finished Jul 22 06:47:39 PM PDT 24
Peak memory 209592 kb
Host smart-2e771f57-cec3-4019-a680-c6e1c44bd117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932983652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1932983652
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3076391424
Short name T104
Test name
Test status
Simulation time 194080545 ps
CPU time 1.08 seconds
Started Jul 22 06:47:31 PM PDT 24
Finished Jul 22 06:47:35 PM PDT 24
Peak memory 209692 kb
Host smart-3ebb3c32-9295-4b9f-8be1-de5bf7b9ebf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076391424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3076391424
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.943836928
Short name T956
Test name
Test status
Simulation time 1873700120 ps
CPU time 4.59 seconds
Started Jul 22 06:47:32 PM PDT 24
Finished Jul 22 06:47:40 PM PDT 24
Peak memory 217800 kb
Host smart-db4f100e-ad30-4bb2-9f33-1b412a871d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943836928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.943836928
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2885202413
Short name T982
Test name
Test status
Simulation time 138956035 ps
CPU time 2.44 seconds
Started Jul 22 06:47:32 PM PDT 24
Finished Jul 22 06:47:37 PM PDT 24
Peak memory 217800 kb
Host smart-f5d1fb85-6baa-4fd6-b6c9-d6112b82dbf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885202413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2885202413
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.106674414
Short name T163
Test name
Test status
Simulation time 24980533 ps
CPU time 1.21 seconds
Started Jul 22 06:47:33 PM PDT 24
Finished Jul 22 06:47:38 PM PDT 24
Peak memory 217876 kb
Host smart-ccd9ceaf-76f1-4c55-a890-e0376f46deb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106674414 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.106674414
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.772218168
Short name T871
Test name
Test status
Simulation time 15659935 ps
CPU time 0.94 seconds
Started Jul 22 06:47:29 PM PDT 24
Finished Jul 22 06:47:33 PM PDT 24
Peak memory 209280 kb
Host smart-4091aa5b-c57b-4a39-844b-caca30cdcb93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772218168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.772218168
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1310533240
Short name T960
Test name
Test status
Simulation time 50460889 ps
CPU time 1.52 seconds
Started Jul 22 06:47:29 PM PDT 24
Finished Jul 22 06:47:34 PM PDT 24
Peak memory 209576 kb
Host smart-6b9032f0-82e3-4b4d-90fc-546c9e906f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310533240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1310533240
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.664177440
Short name T926
Test name
Test status
Simulation time 49060519 ps
CPU time 1.95 seconds
Started Jul 22 06:47:48 PM PDT 24
Finished Jul 22 06:47:51 PM PDT 24
Peak memory 217764 kb
Host smart-e69c6203-c8c3-4d54-a309-981b5b6a2c27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664177440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.664177440
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2291135830
Short name T116
Test name
Test status
Simulation time 46312522 ps
CPU time 1.49 seconds
Started Jul 22 06:47:50 PM PDT 24
Finished Jul 22 06:47:52 PM PDT 24
Peak memory 217884 kb
Host smart-c7d0dae2-8e2d-4fd3-9fe1-06569780bd85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291135830 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2291135830
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.424283561
Short name T889
Test name
Test status
Simulation time 43927138 ps
CPU time 1.02 seconds
Started Jul 22 06:47:31 PM PDT 24
Finished Jul 22 06:47:35 PM PDT 24
Peak memory 209576 kb
Host smart-8bd0a5aa-5180-4c23-851c-16080d0e92c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424283561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.424283561
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3425142090
Short name T179
Test name
Test status
Simulation time 144070308 ps
CPU time 1.41 seconds
Started Jul 22 06:47:33 PM PDT 24
Finished Jul 22 06:47:38 PM PDT 24
Peak memory 209712 kb
Host smart-ce669cd5-a500-4154-84e0-d1e656195c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425142090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3425142090
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2334529277
Short name T964
Test name
Test status
Simulation time 239400396 ps
CPU time 1.91 seconds
Started Jul 22 06:47:34 PM PDT 24
Finished Jul 22 06:47:39 PM PDT 24
Peak memory 217800 kb
Host smart-d4953e72-806c-48d6-a81a-466dc94ca83c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334529277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2334529277
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.998601405
Short name T916
Test name
Test status
Simulation time 19251947 ps
CPU time 1.69 seconds
Started Jul 22 06:47:44 PM PDT 24
Finished Jul 22 06:47:46 PM PDT 24
Peak memory 219392 kb
Host smart-6627eb68-4b56-4ba9-bc20-ffb5bd06a92a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998601405 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.998601405
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2629538898
Short name T898
Test name
Test status
Simulation time 12568159 ps
CPU time 1.02 seconds
Started Jul 22 06:47:42 PM PDT 24
Finished Jul 22 06:47:44 PM PDT 24
Peak memory 209552 kb
Host smart-993c0761-8b11-4335-86c3-424eef94cffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629538898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2629538898
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2123934928
Short name T184
Test name
Test status
Simulation time 42770344 ps
CPU time 0.97 seconds
Started Jul 22 06:47:39 PM PDT 24
Finished Jul 22 06:47:42 PM PDT 24
Peak memory 209768 kb
Host smart-a2f94b9b-3b03-4b2a-9196-4dd7d1ee29b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123934928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2123934928
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.295028295
Short name T909
Test name
Test status
Simulation time 313249014 ps
CPU time 3.47 seconds
Started Jul 22 06:47:32 PM PDT 24
Finished Jul 22 06:47:40 PM PDT 24
Peak memory 217840 kb
Host smart-875019c9-143b-4b53-a9fb-89bdc9a59604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295028295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.295028295
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3403579307
Short name T954
Test name
Test status
Simulation time 17325459 ps
CPU time 1.02 seconds
Started Jul 22 06:47:22 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 209524 kb
Host smart-61af70b6-2364-4633-8aa6-8c3938877d1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403579307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3403579307
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2558551347
Short name T890
Test name
Test status
Simulation time 47844811 ps
CPU time 2.05 seconds
Started Jul 22 06:46:28 PM PDT 24
Finished Jul 22 06:46:34 PM PDT 24
Peak memory 209508 kb
Host smart-834b0dfb-6be7-4b42-9125-715077ea0754
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558551347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2558551347
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3475355875
Short name T893
Test name
Test status
Simulation time 38662233 ps
CPU time 1.21 seconds
Started Jul 22 06:46:15 PM PDT 24
Finished Jul 22 06:46:19 PM PDT 24
Peak memory 211900 kb
Host smart-3aa99a6b-2118-42ec-a74a-22bd606d19c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475355875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3475355875
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3925747638
Short name T102
Test name
Test status
Simulation time 96792788 ps
CPU time 1.21 seconds
Started Jul 22 06:46:21 PM PDT 24
Finished Jul 22 06:46:27 PM PDT 24
Peak memory 217924 kb
Host smart-218d77c6-30bf-4cf0-80e2-3ee3c8b1432a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925747638 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3925747638
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2398769515
Short name T172
Test name
Test status
Simulation time 15890647 ps
CPU time 0.91 seconds
Started Jul 22 06:46:13 PM PDT 24
Finished Jul 22 06:46:16 PM PDT 24
Peak memory 209532 kb
Host smart-b45d709d-df7f-467f-8cb8-a13fa6c9ffa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398769515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2398769515
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2518918368
Short name T924
Test name
Test status
Simulation time 398643453 ps
CPU time 1.85 seconds
Started Jul 22 06:46:13 PM PDT 24
Finished Jul 22 06:46:17 PM PDT 24
Peak memory 209412 kb
Host smart-b98e2a3c-f1e0-4a78-9758-cb1171c36888
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518918368 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2518918368
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.885367310
Short name T929
Test name
Test status
Simulation time 373058964 ps
CPU time 5.1 seconds
Started Jul 22 06:46:14 PM PDT 24
Finished Jul 22 06:46:21 PM PDT 24
Peak memory 209340 kb
Host smart-a8676957-b60b-4f64-bc24-4e4b20185b32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885367310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.885367310
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.976372414
Short name T874
Test name
Test status
Simulation time 776897048 ps
CPU time 4.86 seconds
Started Jul 22 06:46:13 PM PDT 24
Finished Jul 22 06:46:19 PM PDT 24
Peak memory 208824 kb
Host smart-f46bf03b-3ad3-450d-aa8d-cc21aa9155cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976372414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.976372414
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.897937816
Short name T958
Test name
Test status
Simulation time 480101003 ps
CPU time 1.74 seconds
Started Jul 22 06:46:12 PM PDT 24
Finished Jul 22 06:46:15 PM PDT 24
Peak memory 210884 kb
Host smart-a33522fb-8890-45fe-9518-64ed383ee299
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897937816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.897937816
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.377892501
Short name T973
Test name
Test status
Simulation time 82103074 ps
CPU time 2.86 seconds
Started Jul 22 06:46:40 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 218692 kb
Host smart-afef73ad-8aa5-41a9-96b7-a3e263fecd40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377892
501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.377892501
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1686964532
Short name T992
Test name
Test status
Simulation time 112914126 ps
CPU time 2.16 seconds
Started Jul 22 06:46:15 PM PDT 24
Finished Jul 22 06:46:20 PM PDT 24
Peak memory 209532 kb
Host smart-0da94f14-2615-4d5d-adf5-6c0f08545199
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686964532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1686964532
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3924423431
Short name T183
Test name
Test status
Simulation time 45712188 ps
CPU time 1.18 seconds
Started Jul 22 06:46:15 PM PDT 24
Finished Jul 22 06:46:18 PM PDT 24
Peak memory 209632 kb
Host smart-24552354-ab47-4623-9847-c0bdf3b637a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924423431 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3924423431
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3333129253
Short name T896
Test name
Test status
Simulation time 55411807 ps
CPU time 1.23 seconds
Started Jul 22 06:46:29 PM PDT 24
Finished Jul 22 06:46:34 PM PDT 24
Peak memory 209600 kb
Host smart-dca8954c-c71f-4650-af76-e4d2fcc5a5e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333129253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3333129253
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4032640060
Short name T106
Test name
Test status
Simulation time 127761694 ps
CPU time 2.34 seconds
Started Jul 22 06:46:13 PM PDT 24
Finished Jul 22 06:46:17 PM PDT 24
Peak memory 217860 kb
Host smart-e2c71012-d798-461b-b368-92253fd6d65d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032640060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.4032640060
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3313685888
Short name T105
Test name
Test status
Simulation time 95573111 ps
CPU time 1.26 seconds
Started Jul 22 06:46:32 PM PDT 24
Finished Jul 22 06:46:35 PM PDT 24
Peak memory 209572 kb
Host smart-1fd792ee-5ddd-4891-9d53-e461fd8f3a6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313685888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3313685888
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3496083130
Short name T174
Test name
Test status
Simulation time 398882882 ps
CPU time 2.12 seconds
Started Jul 22 06:46:32 PM PDT 24
Finished Jul 22 06:46:36 PM PDT 24
Peak memory 209664 kb
Host smart-b3e22fba-fa9b-49cc-a7ca-0d2dde7bff2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496083130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3496083130
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3302872956
Short name T176
Test name
Test status
Simulation time 87578060 ps
CPU time 1.08 seconds
Started Jul 22 06:46:30 PM PDT 24
Finished Jul 22 06:46:34 PM PDT 24
Peak memory 218408 kb
Host smart-bc19781a-ae5b-44b3-9eb1-d9c47f24ce6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302872956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3302872956
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3568863285
Short name T913
Test name
Test status
Simulation time 113683320 ps
CPU time 1.3 seconds
Started Jul 22 06:46:31 PM PDT 24
Finished Jul 22 06:46:35 PM PDT 24
Peak memory 219036 kb
Host smart-8fc503ff-9b8c-4fe7-82e6-7d159e884343
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568863285 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3568863285
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1183674009
Short name T965
Test name
Test status
Simulation time 39069248 ps
CPU time 0.94 seconds
Started Jul 22 06:47:49 PM PDT 24
Finished Jul 22 06:47:51 PM PDT 24
Peak memory 209528 kb
Host smart-b0377f99-d308-4351-851e-2490180165cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183674009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1183674009
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.11344048
Short name T899
Test name
Test status
Simulation time 51181802 ps
CPU time 2.19 seconds
Started Jul 22 06:46:30 PM PDT 24
Finished Jul 22 06:46:35 PM PDT 24
Peak memory 209512 kb
Host smart-48624736-0e10-429b-a53f-c057a506d527
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11344048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_alert_test.11344048
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2741037294
Short name T880
Test name
Test status
Simulation time 373170666 ps
CPU time 8.98 seconds
Started Jul 22 06:48:09 PM PDT 24
Finished Jul 22 06:48:19 PM PDT 24
Peak memory 209260 kb
Host smart-64b0805b-4904-4150-97bb-32e49d0bce56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741037294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2741037294
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.476360963
Short name T988
Test name
Test status
Simulation time 15935046790 ps
CPU time 21.49 seconds
Started Jul 22 06:48:31 PM PDT 24
Finished Jul 22 06:48:53 PM PDT 24
Peak memory 209568 kb
Host smart-dd0bf295-1412-4be1-afc0-41363e3c57e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476360963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.476360963
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.667856666
Short name T933
Test name
Test status
Simulation time 746110325 ps
CPU time 6.35 seconds
Started Jul 22 06:46:38 PM PDT 24
Finished Jul 22 06:46:45 PM PDT 24
Peak memory 211264 kb
Host smart-d3091e41-dbc7-4097-a89e-f6ab456eb0d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667856666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.667856666
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1729005248
Short name T993
Test name
Test status
Simulation time 54394726 ps
CPU time 1.43 seconds
Started Jul 22 06:46:29 PM PDT 24
Finished Jul 22 06:46:34 PM PDT 24
Peak memory 209436 kb
Host smart-95cb43a9-eea8-4d08-8f02-4a6b9b47d5bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729005248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1729005248
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2812389939
Short name T934
Test name
Test status
Simulation time 21815690 ps
CPU time 1.2 seconds
Started Jul 22 06:46:30 PM PDT 24
Finished Jul 22 06:46:34 PM PDT 24
Peak memory 209592 kb
Host smart-052a3a1c-779f-4b39-a1a8-f879152d7759
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812389939 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2812389939
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.226600950
Short name T983
Test name
Test status
Simulation time 22273546 ps
CPU time 1.37 seconds
Started Jul 22 06:46:31 PM PDT 24
Finished Jul 22 06:46:35 PM PDT 24
Peak memory 209676 kb
Host smart-30bcbaa2-8798-44f3-856b-5eb1e3e51b54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226600950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.226600950
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.246922363
Short name T97
Test name
Test status
Simulation time 78461509 ps
CPU time 3.43 seconds
Started Jul 22 06:46:32 PM PDT 24
Finished Jul 22 06:46:38 PM PDT 24
Peak memory 217848 kb
Host smart-8a853006-88c2-4b73-9891-8c7cab657e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246922363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.246922363
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.146019468
Short name T121
Test name
Test status
Simulation time 98926990 ps
CPU time 3.13 seconds
Started Jul 22 06:46:32 PM PDT 24
Finished Jul 22 06:46:37 PM PDT 24
Peak memory 222496 kb
Host smart-879cf1c3-9d23-4a16-ab8d-59b9a1bc8857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146019468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.146019468
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1407360572
Short name T873
Test name
Test status
Simulation time 35284644 ps
CPU time 1.37 seconds
Started Jul 22 06:46:41 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 209656 kb
Host smart-a927a13e-4306-4164-ade5-c4107d4ee048
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407360572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1407360572
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4003986040
Short name T883
Test name
Test status
Simulation time 410470332 ps
CPU time 2.52 seconds
Started Jul 22 06:46:40 PM PDT 24
Finished Jul 22 06:46:43 PM PDT 24
Peak memory 209520 kb
Host smart-7745130a-7ec3-4845-b002-46011121ae3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003986040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4003986040
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3018532283
Short name T959
Test name
Test status
Simulation time 17566524 ps
CPU time 1.23 seconds
Started Jul 22 06:46:41 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 211804 kb
Host smart-624b0ff3-e10f-4044-aa67-415e8e29cab6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018532283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3018532283
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1081160882
Short name T911
Test name
Test status
Simulation time 33419375 ps
CPU time 1.76 seconds
Started Jul 22 06:46:39 PM PDT 24
Finished Jul 22 06:46:42 PM PDT 24
Peak memory 217852 kb
Host smart-827a2d61-4787-4c32-8eda-f9eecdde22ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081160882 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1081160882
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.557654421
Short name T944
Test name
Test status
Simulation time 45850948 ps
CPU time 0.95 seconds
Started Jul 22 06:46:41 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 209748 kb
Host smart-eb3fc7a6-6966-43cc-9761-4b1cd6092dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557654421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.557654421
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1465376064
Short name T905
Test name
Test status
Simulation time 52216932 ps
CPU time 0.98 seconds
Started Jul 22 06:46:33 PM PDT 24
Finished Jul 22 06:46:36 PM PDT 24
Peak memory 208140 kb
Host smart-a72f2157-95cc-449f-a1a5-6ae43268de24
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465376064 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1465376064
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.361169302
Short name T915
Test name
Test status
Simulation time 733617291 ps
CPU time 7.22 seconds
Started Jul 22 06:46:32 PM PDT 24
Finished Jul 22 06:46:42 PM PDT 24
Peak memory 209384 kb
Host smart-26504d87-e677-414f-82b7-5e9b7d86c208
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361169302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.361169302
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3250983712
Short name T888
Test name
Test status
Simulation time 3172624951 ps
CPU time 7.22 seconds
Started Jul 22 06:47:22 PM PDT 24
Finished Jul 22 06:47:31 PM PDT 24
Peak memory 209368 kb
Host smart-b341f8e4-5485-44b2-8c34-5dc4525aea99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250983712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3250983712
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.615874367
Short name T128
Test name
Test status
Simulation time 179096842 ps
CPU time 1.64 seconds
Started Jul 22 06:46:30 PM PDT 24
Finished Jul 22 06:46:35 PM PDT 24
Peak memory 210928 kb
Host smart-04d2007b-b0a0-4722-9048-c27a4f34f762
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615874367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.615874367
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4103584313
Short name T967
Test name
Test status
Simulation time 68650198 ps
CPU time 1.81 seconds
Started Jul 22 06:46:32 PM PDT 24
Finished Jul 22 06:46:36 PM PDT 24
Peak memory 218984 kb
Host smart-8b42c4a0-e1c6-4b96-ad59-ec72ca646f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410358
4313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4103584313
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1842984733
Short name T957
Test name
Test status
Simulation time 96214039 ps
CPU time 1.83 seconds
Started Jul 22 06:46:29 PM PDT 24
Finished Jul 22 06:46:35 PM PDT 24
Peak memory 209480 kb
Host smart-1eb46586-23e7-493c-a133-1d40dd1fa3e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842984733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1842984733
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1875816298
Short name T939
Test name
Test status
Simulation time 16701070 ps
CPU time 1.21 seconds
Started Jul 22 06:46:31 PM PDT 24
Finished Jul 22 06:46:35 PM PDT 24
Peak memory 209680 kb
Host smart-cbe0596a-089d-4c7c-b565-18d3bd9e9a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875816298 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1875816298
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3424714232
Short name T986
Test name
Test status
Simulation time 28256477 ps
CPU time 1.08 seconds
Started Jul 22 06:46:40 PM PDT 24
Finished Jul 22 06:46:43 PM PDT 24
Peak memory 209572 kb
Host smart-a0a7e8cc-f81e-4620-b202-ecbf175d529c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424714232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3424714232
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2249827686
Short name T94
Test name
Test status
Simulation time 89443537 ps
CPU time 2.7 seconds
Started Jul 22 06:46:43 PM PDT 24
Finished Jul 22 06:46:47 PM PDT 24
Peak memory 218152 kb
Host smart-3de4fb71-ae33-44f0-840c-2b7dc9b9d94b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249827686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2249827686
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2799504494
Short name T117
Test name
Test status
Simulation time 97364817 ps
CPU time 3.34 seconds
Started Jul 22 06:46:39 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 222460 kb
Host smart-bdc4f766-4b67-4888-aae2-f6fa4648facd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799504494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2799504494
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1137884315
Short name T897
Test name
Test status
Simulation time 25026268 ps
CPU time 1.56 seconds
Started Jul 22 06:46:41 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 217844 kb
Host smart-43eeffa1-5959-46ea-a2e7-c423b141286e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137884315 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1137884315
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.560453716
Short name T175
Test name
Test status
Simulation time 27502666 ps
CPU time 0.89 seconds
Started Jul 22 06:48:39 PM PDT 24
Finished Jul 22 06:48:41 PM PDT 24
Peak memory 209568 kb
Host smart-0489550e-3d1b-45c1-a101-082927d2927a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560453716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.560453716
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2527213959
Short name T907
Test name
Test status
Simulation time 46065141 ps
CPU time 1.73 seconds
Started Jul 22 06:46:39 PM PDT 24
Finished Jul 22 06:46:41 PM PDT 24
Peak memory 209456 kb
Host smart-d34e571e-4063-45ca-b7a2-d24199b6be0d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527213959 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2527213959
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4067525773
Short name T923
Test name
Test status
Simulation time 1222553627 ps
CPU time 5.12 seconds
Started Jul 22 06:46:43 PM PDT 24
Finished Jul 22 06:46:50 PM PDT 24
Peak memory 209340 kb
Host smart-37f27422-f83d-4fe5-b440-3216907cbd3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067525773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4067525773
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2067477823
Short name T903
Test name
Test status
Simulation time 769644689 ps
CPU time 5.14 seconds
Started Jul 22 06:46:40 PM PDT 24
Finished Jul 22 06:46:46 PM PDT 24
Peak memory 209496 kb
Host smart-c1689eff-5e7c-46dd-9e92-18d2e81bd25a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067477823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2067477823
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3622946332
Short name T875
Test name
Test status
Simulation time 1032710218 ps
CPU time 2.91 seconds
Started Jul 22 06:46:41 PM PDT 24
Finished Jul 22 06:46:45 PM PDT 24
Peak memory 211136 kb
Host smart-e45ba2be-8754-4b61-b6d5-4ae9f9ab66a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622946332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3622946332
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1010386181
Short name T938
Test name
Test status
Simulation time 200459239 ps
CPU time 1.5 seconds
Started Jul 22 06:46:39 PM PDT 24
Finished Jul 22 06:46:42 PM PDT 24
Peak memory 219440 kb
Host smart-d43adc56-1c6d-4f50-98ad-37911724ee09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101038
6181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1010386181
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.549961568
Short name T961
Test name
Test status
Simulation time 97752721 ps
CPU time 1.23 seconds
Started Jul 22 06:46:40 PM PDT 24
Finished Jul 22 06:46:43 PM PDT 24
Peak memory 209512 kb
Host smart-5e0df8f8-f010-4e0c-9706-f28262e729ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549961568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.549961568
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.12958388
Short name T990
Test name
Test status
Simulation time 22376661 ps
CPU time 1.58 seconds
Started Jul 22 06:46:43 PM PDT 24
Finished Jul 22 06:46:46 PM PDT 24
Peak memory 211772 kb
Host smart-d42cce36-8188-4443-9931-372f3e0637c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12958388 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.12958388
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.650585965
Short name T989
Test name
Test status
Simulation time 22328929 ps
CPU time 1.42 seconds
Started Jul 22 06:46:40 PM PDT 24
Finished Jul 22 06:46:43 PM PDT 24
Peak memory 211680 kb
Host smart-75d8c5c3-ee27-4952-b0bd-68523bc9a730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650585965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.650585965
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.381352116
Short name T949
Test name
Test status
Simulation time 203073508 ps
CPU time 3.88 seconds
Started Jul 22 06:48:39 PM PDT 24
Finished Jul 22 06:48:44 PM PDT 24
Peak memory 217856 kb
Host smart-19baa3a4-f59b-4d7c-a193-090ce2514cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381352116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.381352116
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4124171120
Short name T101
Test name
Test status
Simulation time 108158383 ps
CPU time 4.39 seconds
Started Jul 22 06:46:40 PM PDT 24
Finished Jul 22 06:46:45 PM PDT 24
Peak memory 217796 kb
Host smart-c049d303-9eda-4c02-b581-c497148cd676
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124171120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4124171120
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2835906645
Short name T928
Test name
Test status
Simulation time 29138690 ps
CPU time 1.28 seconds
Started Jul 22 06:46:52 PM PDT 24
Finished Jul 22 06:46:55 PM PDT 24
Peak memory 219068 kb
Host smart-3c19725a-69c8-4764-bed4-bbd569e9b6cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835906645 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2835906645
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3811711218
Short name T878
Test name
Test status
Simulation time 15472260 ps
CPU time 0.85 seconds
Started Jul 22 06:46:47 PM PDT 24
Finished Jul 22 06:46:51 PM PDT 24
Peak memory 209556 kb
Host smart-d1d13859-63f2-455e-9224-d5e0c3d6e5e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811711218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3811711218
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3209096799
Short name T885
Test name
Test status
Simulation time 135658787 ps
CPU time 1.9 seconds
Started Jul 22 06:46:56 PM PDT 24
Finished Jul 22 06:47:00 PM PDT 24
Peak memory 208228 kb
Host smart-f4085f30-aa89-4228-951c-7aaecd4cc2c2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209096799 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3209096799
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2080515094
Short name T922
Test name
Test status
Simulation time 666811278 ps
CPU time 6.23 seconds
Started Jul 22 06:46:43 PM PDT 24
Finished Jul 22 06:46:51 PM PDT 24
Peak memory 209292 kb
Host smart-5a4cf069-7687-485d-bdff-2765a286a1b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080515094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2080515094
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1599429033
Short name T953
Test name
Test status
Simulation time 837934394 ps
CPU time 5.06 seconds
Started Jul 22 06:46:43 PM PDT 24
Finished Jul 22 06:46:49 PM PDT 24
Peak memory 208708 kb
Host smart-971d888b-efed-477b-808c-120b65359948
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599429033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1599429033
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.912904889
Short name T976
Test name
Test status
Simulation time 91994093 ps
CPU time 1.55 seconds
Started Jul 22 06:46:41 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 211156 kb
Host smart-7510e644-9d8f-462c-839f-2c42343214a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912904889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.912904889
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2094650076
Short name T881
Test name
Test status
Simulation time 1337537238 ps
CPU time 3.88 seconds
Started Jul 22 06:46:58 PM PDT 24
Finished Jul 22 06:47:03 PM PDT 24
Peak memory 218892 kb
Host smart-26fd13a8-58f7-45c8-b67a-d9a2d3e87c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209465
0076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2094650076
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.463139151
Short name T948
Test name
Test status
Simulation time 66549844 ps
CPU time 2.44 seconds
Started Jul 22 06:46:45 PM PDT 24
Finished Jul 22 06:46:49 PM PDT 24
Peak memory 209504 kb
Host smart-b1eb74e3-6270-40b9-9b59-0cdc722b9cb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463139151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.463139151
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2192008605
Short name T975
Test name
Test status
Simulation time 64724265 ps
CPU time 1.17 seconds
Started Jul 22 06:46:41 PM PDT 24
Finished Jul 22 06:46:44 PM PDT 24
Peak memory 209880 kb
Host smart-fab2cb71-05d9-4a0b-821a-06e413a92d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192008605 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2192008605
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4049774880
Short name T180
Test name
Test status
Simulation time 32226276 ps
CPU time 1.14 seconds
Started Jul 22 06:46:58 PM PDT 24
Finished Jul 22 06:47:00 PM PDT 24
Peak memory 209600 kb
Host smart-71983aed-7726-4cb8-bb6b-e54c3aa8f033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049774880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.4049774880
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.977168767
Short name T917
Test name
Test status
Simulation time 242673080 ps
CPU time 3.22 seconds
Started Jul 22 06:46:43 PM PDT 24
Finished Jul 22 06:46:48 PM PDT 24
Peak memory 217840 kb
Host smart-3e9dd4e6-6fc2-4e83-9426-5e389859838b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977168767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.977168767
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4052599599
Short name T910
Test name
Test status
Simulation time 65961223 ps
CPU time 1.05 seconds
Started Jul 22 06:46:58 PM PDT 24
Finished Jul 22 06:47:00 PM PDT 24
Peak memory 219572 kb
Host smart-20684101-f9b2-426c-a622-6bf5ba07032a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052599599 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.4052599599
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1017944427
Short name T900
Test name
Test status
Simulation time 11730575 ps
CPU time 0.88 seconds
Started Jul 22 06:47:01 PM PDT 24
Finished Jul 22 06:47:02 PM PDT 24
Peak memory 209640 kb
Host smart-cf07a325-837a-402e-948b-93ef1cf480f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017944427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1017944427
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2856967783
Short name T951
Test name
Test status
Simulation time 176998524 ps
CPU time 1.55 seconds
Started Jul 22 06:46:58 PM PDT 24
Finished Jul 22 06:47:01 PM PDT 24
Peak memory 209252 kb
Host smart-31d6066d-837f-4fa7-9945-1e0018b8b2cb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856967783 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2856967783
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3237341482
Short name T979
Test name
Test status
Simulation time 1544612475 ps
CPU time 4.83 seconds
Started Jul 22 06:46:48 PM PDT 24
Finished Jul 22 06:46:56 PM PDT 24
Peak memory 209280 kb
Host smart-de8979e8-27cb-455d-826a-b603d6f2be27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237341482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3237341482
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.102682972
Short name T130
Test name
Test status
Simulation time 974491392 ps
CPU time 5.71 seconds
Started Jul 22 06:46:47 PM PDT 24
Finished Jul 22 06:46:56 PM PDT 24
Peak memory 209308 kb
Host smart-25f02b45-dced-4b98-a491-8d8652b5d747
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102682972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.102682972
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1146153178
Short name T962
Test name
Test status
Simulation time 55355021 ps
CPU time 1.42 seconds
Started Jul 22 06:46:47 PM PDT 24
Finished Jul 22 06:46:52 PM PDT 24
Peak memory 211152 kb
Host smart-f43df4ab-b20c-4a93-bca9-c13025840c41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146153178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1146153178
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2518811154
Short name T908
Test name
Test status
Simulation time 51534062 ps
CPU time 1.4 seconds
Started Jul 22 06:46:58 PM PDT 24
Finished Jul 22 06:47:01 PM PDT 24
Peak memory 218952 kb
Host smart-311af601-0539-432d-b096-b6ae1aceddbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251881
1154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2518811154
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2049817869
Short name T969
Test name
Test status
Simulation time 49025626 ps
CPU time 1.02 seconds
Started Jul 22 06:46:47 PM PDT 24
Finished Jul 22 06:46:52 PM PDT 24
Peak memory 209432 kb
Host smart-7fe892a3-9c1a-4407-b241-1dbe584a3a3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049817869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2049817869
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1238414981
Short name T974
Test name
Test status
Simulation time 89857821 ps
CPU time 1.06 seconds
Started Jul 22 06:46:58 PM PDT 24
Finished Jul 22 06:47:00 PM PDT 24
Peak memory 209604 kb
Host smart-bdf16002-7c9a-499d-af9a-01e26c7022f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238414981 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1238414981
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.84337733
Short name T921
Test name
Test status
Simulation time 83840882 ps
CPU time 1.09 seconds
Started Jul 22 06:46:57 PM PDT 24
Finished Jul 22 06:47:00 PM PDT 24
Peak memory 209580 kb
Host smart-cf492985-3d04-4173-a2d8-d8c7a7196ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84337733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_s
ame_csr_outstanding.84337733
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4082389601
Short name T946
Test name
Test status
Simulation time 1165633165 ps
CPU time 4.64 seconds
Started Jul 22 06:46:58 PM PDT 24
Finished Jul 22 06:47:04 PM PDT 24
Peak memory 217872 kb
Host smart-d8a53a15-71f5-4398-90d4-d0d12ebd1a31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082389601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4082389601
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2912209837
Short name T998
Test name
Test status
Simulation time 23511749 ps
CPU time 1.58 seconds
Started Jul 22 06:47:09 PM PDT 24
Finished Jul 22 06:47:20 PM PDT 24
Peak memory 223872 kb
Host smart-9883a6a4-669d-4460-afc0-6cac92578da3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912209837 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2912209837
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1789168211
Short name T914
Test name
Test status
Simulation time 54584876 ps
CPU time 1.06 seconds
Started Jul 22 06:47:07 PM PDT 24
Finished Jul 22 06:47:18 PM PDT 24
Peak memory 209600 kb
Host smart-467a88b4-27d3-44cf-8306-00496b77fda8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789168211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1789168211
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.242578865
Short name T872
Test name
Test status
Simulation time 445178272 ps
CPU time 1.81 seconds
Started Jul 22 06:47:00 PM PDT 24
Finished Jul 22 06:47:02 PM PDT 24
Peak memory 208188 kb
Host smart-eda44780-a573-44cb-8122-e274e77d99a4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242578865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.242578865
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3601217977
Short name T991
Test name
Test status
Simulation time 2276102683 ps
CPU time 12.19 seconds
Started Jul 22 06:46:57 PM PDT 24
Finished Jul 22 06:47:11 PM PDT 24
Peak memory 209340 kb
Host smart-171fb8bf-540e-4b86-a9da-06a6b5d1b2c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601217977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3601217977
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1976168294
Short name T891
Test name
Test status
Simulation time 2367334827 ps
CPU time 24.74 seconds
Started Jul 22 06:46:57 PM PDT 24
Finished Jul 22 06:47:23 PM PDT 24
Peak memory 209596 kb
Host smart-801809e5-c2c7-46b5-a667-ee7d58b38261
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976168294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1976168294
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1455862883
Short name T902
Test name
Test status
Simulation time 127578100 ps
CPU time 1.66 seconds
Started Jul 22 06:46:59 PM PDT 24
Finished Jul 22 06:47:01 PM PDT 24
Peak memory 211228 kb
Host smart-5191243a-50d4-41ac-a95a-c5090617df23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455862883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1455862883
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.239689620
Short name T935
Test name
Test status
Simulation time 290196959 ps
CPU time 2.47 seconds
Started Jul 22 06:47:02 PM PDT 24
Finished Jul 22 06:47:05 PM PDT 24
Peak memory 217736 kb
Host smart-404a99e8-63a3-4444-a73f-2507a3c42aed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239689
620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.239689620
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3175376008
Short name T879
Test name
Test status
Simulation time 275764318 ps
CPU time 1.71 seconds
Started Jul 22 06:47:01 PM PDT 24
Finished Jul 22 06:47:04 PM PDT 24
Peak memory 209536 kb
Host smart-c1ab07b5-897e-42f9-995f-e59587a2b9c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175376008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3175376008
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.356415461
Short name T952
Test name
Test status
Simulation time 29561747 ps
CPU time 1.46 seconds
Started Jul 22 06:46:57 PM PDT 24
Finished Jul 22 06:47:00 PM PDT 24
Peak memory 209628 kb
Host smart-685f80a4-3cbc-4d8c-bf5b-4f112bec3403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356415461 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.356415461
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3533234073
Short name T968
Test name
Test status
Simulation time 23097733 ps
CPU time 1.34 seconds
Started Jul 22 06:47:08 PM PDT 24
Finished Jul 22 06:47:19 PM PDT 24
Peak memory 217716 kb
Host smart-921b5fa8-a188-4de0-af85-749354b07e95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533234073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3533234073
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3187477073
Short name T978
Test name
Test status
Simulation time 389501416 ps
CPU time 3.44 seconds
Started Jul 22 06:47:07 PM PDT 24
Finished Jul 22 06:47:20 PM PDT 24
Peak memory 217820 kb
Host smart-5a0b7816-78ff-4d7b-81db-696672fa9201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187477073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3187477073
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1891530188
Short name T119
Test name
Test status
Simulation time 110336804 ps
CPU time 2.77 seconds
Started Jul 22 06:47:44 PM PDT 24
Finished Jul 22 06:47:48 PM PDT 24
Peak memory 222560 kb
Host smart-1af2f75e-574f-4d8c-9a96-8082cd633841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891530188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1891530188
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1891766253
Short name T95
Test name
Test status
Simulation time 61236703 ps
CPU time 1.48 seconds
Started Jul 22 06:47:16 PM PDT 24
Finished Jul 22 06:47:23 PM PDT 24
Peak memory 217900 kb
Host smart-c72626d8-0b71-43eb-9c24-851aed90ff1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891766253 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1891766253
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3083619970
Short name T932
Test name
Test status
Simulation time 16155212 ps
CPU time 1.09 seconds
Started Jul 22 06:47:24 PM PDT 24
Finished Jul 22 06:47:26 PM PDT 24
Peak memory 217548 kb
Host smart-6b7b5d8b-63f4-4539-8149-3dd9f5d01e77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083619970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3083619970
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1020579937
Short name T884
Test name
Test status
Simulation time 102172699 ps
CPU time 0.97 seconds
Started Jul 22 06:47:09 PM PDT 24
Finished Jul 22 06:47:20 PM PDT 24
Peak memory 209368 kb
Host smart-922f9850-eae7-463e-af70-e04adf1d5fbc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020579937 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1020579937
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1106971630
Short name T941
Test name
Test status
Simulation time 230023899 ps
CPU time 3.32 seconds
Started Jul 22 06:48:06 PM PDT 24
Finished Jul 22 06:48:09 PM PDT 24
Peak memory 209316 kb
Host smart-b5f542e2-695a-4c9a-b225-4c8eab889d18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106971630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1106971630
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.426124849
Short name T997
Test name
Test status
Simulation time 974880390 ps
CPU time 10.24 seconds
Started Jul 22 06:47:11 PM PDT 24
Finished Jul 22 06:47:30 PM PDT 24
Peak memory 209500 kb
Host smart-20cb93ff-7a41-47bf-bbbe-9f1a735d81ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426124849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.426124849
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3486023330
Short name T925
Test name
Test status
Simulation time 558890718 ps
CPU time 3.97 seconds
Started Jul 22 06:47:14 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 211228 kb
Host smart-890cfe27-b258-4191-adf2-8f58d56dcadf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486023330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3486023330
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1595667983
Short name T987
Test name
Test status
Simulation time 792838680 ps
CPU time 1.64 seconds
Started Jul 22 06:47:07 PM PDT 24
Finished Jul 22 06:47:19 PM PDT 24
Peak memory 218888 kb
Host smart-e09dec33-ce26-430d-9ac9-3d294b45d177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159566
7983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1595667983
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.224704266
Short name T963
Test name
Test status
Simulation time 105774673 ps
CPU time 1.35 seconds
Started Jul 22 06:47:08 PM PDT 24
Finished Jul 22 06:47:19 PM PDT 24
Peak memory 209512 kb
Host smart-839c9687-1a28-44f9-8c14-d3e4c4fe3e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224704266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.224704266
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1807632548
Short name T178
Test name
Test status
Simulation time 27735056 ps
CPU time 1.08 seconds
Started Jul 22 06:47:11 PM PDT 24
Finished Jul 22 06:47:21 PM PDT 24
Peak memory 209672 kb
Host smart-a693acb8-3fb2-48b9-85fd-c5dee32caca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807632548 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1807632548
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2769474570
Short name T995
Test name
Test status
Simulation time 428811375 ps
CPU time 1.91 seconds
Started Jul 22 06:47:25 PM PDT 24
Finished Jul 22 06:47:27 PM PDT 24
Peak memory 211608 kb
Host smart-6bc3f1bd-5d77-43fa-a6ed-ccb48c68845c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769474570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2769474570
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1535208678
Short name T886
Test name
Test status
Simulation time 281568731 ps
CPU time 1.79 seconds
Started Jul 22 06:47:18 PM PDT 24
Finished Jul 22 06:47:24 PM PDT 24
Peak memory 218068 kb
Host smart-daef3ee3-d9dc-4387-b46b-1ffd9ac5e9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535208678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1535208678
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3088035147
Short name T115
Test name
Test status
Simulation time 154480943 ps
CPU time 1.77 seconds
Started Jul 22 06:47:22 PM PDT 24
Finished Jul 22 06:47:26 PM PDT 24
Peak memory 222176 kb
Host smart-abb52b13-a3a5-41e8-a063-2fb24d306c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088035147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3088035147
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3099077682
Short name T624
Test name
Test status
Simulation time 14612415 ps
CPU time 0.93 seconds
Started Jul 22 07:20:50 PM PDT 24
Finished Jul 22 07:21:15 PM PDT 24
Peak memory 208612 kb
Host smart-9bc7801e-39bf-4b85-9219-d16f2b147a22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099077682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3099077682
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3147938977
Short name T678
Test name
Test status
Simulation time 1483464095 ps
CPU time 16.29 seconds
Started Jul 22 07:20:44 PM PDT 24
Finished Jul 22 07:21:12 PM PDT 24
Peak memory 225628 kb
Host smart-d7e6015e-c4f7-4af5-917d-a67c6a8d1af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147938977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3147938977
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1198308521
Short name T373
Test name
Test status
Simulation time 157203646 ps
CPU time 1.37 seconds
Started Jul 22 07:20:44 PM PDT 24
Finished Jul 22 07:20:59 PM PDT 24
Peak memory 217220 kb
Host smart-2c0550d8-93f0-4e4a-a5b4-f91c9eda771b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198308521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1198308521
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.536634605
Short name T754
Test name
Test status
Simulation time 1289313711 ps
CPU time 40.09 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:21:40 PM PDT 24
Peak memory 218412 kb
Host smart-c8d391fa-d695-4b72-9ea6-62bc1dd85f60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536634605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.536634605
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.20191670
Short name T660
Test name
Test status
Simulation time 604944484 ps
CPU time 4.89 seconds
Started Jul 22 07:20:22 PM PDT 24
Finished Jul 22 07:20:35 PM PDT 24
Peak memory 217268 kb
Host smart-b3dc0ae0-4573-417c-80b5-cc8bc3005858
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20191670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.20191670
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3468678060
Short name T382
Test name
Test status
Simulation time 252375551 ps
CPU time 9.06 seconds
Started Jul 22 07:20:46 PM PDT 24
Finished Jul 22 07:21:12 PM PDT 24
Peak memory 217720 kb
Host smart-88c8c37b-25ee-41fc-b984-6801cd7750bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468678060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3468678060
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2757272798
Short name T870
Test name
Test status
Simulation time 6729309912 ps
CPU time 27.42 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:21:28 PM PDT 24
Peak memory 217324 kb
Host smart-23c65ebb-207e-43b9-a7a2-d04733481349
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757272798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2757272798
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.936761252
Short name T445
Test name
Test status
Simulation time 131986861 ps
CPU time 4.23 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:21:03 PM PDT 24
Peak memory 217204 kb
Host smart-bfbb2b67-a4f5-4dc8-83a4-13072fe36741
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936761252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.936761252
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4166062404
Short name T320
Test name
Test status
Simulation time 24042313413 ps
CPU time 53.96 seconds
Started Jul 22 07:20:43 PM PDT 24
Finished Jul 22 07:21:49 PM PDT 24
Peak memory 283340 kb
Host smart-a037e7e2-4a29-4aa7-9ccd-283b87e7522c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166062404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4166062404
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4242608553
Short name T386
Test name
Test status
Simulation time 5869711088 ps
CPU time 14.22 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:21:13 PM PDT 24
Peak memory 246776 kb
Host smart-d82111f2-cfdf-4262-a8ed-9f3073cb51bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242608553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.4242608553
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3574187723
Short name T336
Test name
Test status
Simulation time 245299738 ps
CPU time 3.2 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:55 PM PDT 24
Peak memory 217788 kb
Host smart-838dfaf7-5c33-4173-84ff-321fcb7d23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574187723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3574187723
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3544848933
Short name T63
Test name
Test status
Simulation time 1596536866 ps
CPU time 18.34 seconds
Started Jul 22 07:20:45 PM PDT 24
Finished Jul 22 07:21:20 PM PDT 24
Peak memory 214344 kb
Host smart-2ceae629-cf6d-466b-81ec-a4a92beb9a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544848933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3544848933
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2416354663
Short name T861
Test name
Test status
Simulation time 1039289242 ps
CPU time 14.25 seconds
Started Jul 22 07:20:49 PM PDT 24
Finished Jul 22 07:21:26 PM PDT 24
Peak memory 217832 kb
Host smart-ec661195-1992-4a3b-a64d-722d42006eba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416354663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2416354663
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3555385553
Short name T151
Test name
Test status
Simulation time 288741581 ps
CPU time 8.03 seconds
Started Jul 22 07:20:46 PM PDT 24
Finished Jul 22 07:21:13 PM PDT 24
Peak memory 217800 kb
Host smart-e86421b7-e561-43a9-83a5-9c2e4bc89002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555385553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
555385553
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.850491598
Short name T384
Test name
Test status
Simulation time 2164361027 ps
CPU time 10.94 seconds
Started Jul 22 07:20:51 PM PDT 24
Finished Jul 22 07:21:26 PM PDT 24
Peak memory 217948 kb
Host smart-48f7b6e0-512b-4036-b6f0-b7b9b78f7c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850491598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.850491598
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1027203660
Short name T283
Test name
Test status
Simulation time 34165104 ps
CPU time 1.73 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:53 PM PDT 24
Peak memory 213552 kb
Host smart-9ea61728-4bcc-4161-83a5-01cdb969c10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027203660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1027203660
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.682575959
Short name T300
Test name
Test status
Simulation time 477452857 ps
CPU time 26.73 seconds
Started Jul 22 07:24:45 PM PDT 24
Finished Jul 22 07:26:10 PM PDT 24
Peak memory 250572 kb
Host smart-fe26782a-b440-4ea9-ac32-392f9a63469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682575959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.682575959
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2478984433
Short name T434
Test name
Test status
Simulation time 44728832 ps
CPU time 5.42 seconds
Started Jul 22 07:24:45 PM PDT 24
Finished Jul 22 07:25:49 PM PDT 24
Peak memory 246324 kb
Host smart-303946c8-83aa-48ab-85c3-ae173f0a4ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478984433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2478984433
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.407232238
Short name T338
Test name
Test status
Simulation time 39542409100 ps
CPU time 116.09 seconds
Started Jul 22 07:20:49 PM PDT 24
Finished Jul 22 07:23:08 PM PDT 24
Peak memory 283480 kb
Host smart-8fe8c95a-cbc1-4a7b-8627-c05fe8477b5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407232238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.407232238
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3246809043
Short name T54
Test name
Test status
Simulation time 154495478469 ps
CPU time 749.11 seconds
Started Jul 22 07:20:48 PM PDT 24
Finished Jul 22 07:33:40 PM PDT 24
Peak memory 562072 kb
Host smart-6788d1ea-fd07-4a26-aa7d-7c35c686e346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3246809043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.3246809043
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3811738015
Short name T317
Test name
Test status
Simulation time 11467162 ps
CPU time 1.03 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:53 PM PDT 24
Peak memory 211392 kb
Host smart-0b195338-fdeb-4d06-93a7-96ad1c2638ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811738015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3811738015
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.188690627
Short name T294
Test name
Test status
Simulation time 137746524 ps
CPU time 1.41 seconds
Started Jul 22 07:20:57 PM PDT 24
Finished Jul 22 07:21:30 PM PDT 24
Peak memory 208652 kb
Host smart-0ab0813d-229b-4852-bfd8-3dfa3a4f49df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188690627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.188690627
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1176168391
Short name T134
Test name
Test status
Simulation time 1172562817 ps
CPU time 13.66 seconds
Started Jul 22 07:20:54 PM PDT 24
Finished Jul 22 07:21:35 PM PDT 24
Peak memory 217832 kb
Host smart-5a572171-8c76-4da5-8821-f5449392e600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176168391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1176168391
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.988710239
Short name T448
Test name
Test status
Simulation time 247741306 ps
CPU time 6.41 seconds
Started Jul 22 07:20:56 PM PDT 24
Finished Jul 22 07:21:33 PM PDT 24
Peak memory 217276 kb
Host smart-41ced634-b2cc-4627-a156-e4da52dd3991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988710239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.988710239
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2924424013
Short name T357
Test name
Test status
Simulation time 278117497 ps
CPU time 7.32 seconds
Started Jul 22 07:20:56 PM PDT 24
Finished Jul 22 07:21:32 PM PDT 24
Peak memory 217032 kb
Host smart-757bb7b2-29ba-4f0d-a7c6-6872b9c65b7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924424013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
924424013
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3333860798
Short name T699
Test name
Test status
Simulation time 633922087 ps
CPU time 18.33 seconds
Started Jul 22 07:20:56 PM PDT 24
Finished Jul 22 07:21:45 PM PDT 24
Peak memory 222844 kb
Host smart-f3d00b86-4d1c-480f-845d-c214b46f0c0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333860798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3333860798
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2313303066
Short name T73
Test name
Test status
Simulation time 3437004209 ps
CPU time 23.5 seconds
Started Jul 22 07:20:55 PM PDT 24
Finished Jul 22 07:21:47 PM PDT 24
Peak memory 217284 kb
Host smart-ff9f06f2-d8dc-4a43-9743-c4541b785b3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313303066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2313303066
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.134369399
Short name T800
Test name
Test status
Simulation time 1064316558 ps
CPU time 3.4 seconds
Started Jul 22 07:23:55 PM PDT 24
Finished Jul 22 07:24:25 PM PDT 24
Peak memory 217180 kb
Host smart-fcdcb3e5-8ea5-437c-83c7-8b9f2a6f79db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134369399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.134369399
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.4121066644
Short name T337
Test name
Test status
Simulation time 1752032762 ps
CPU time 61.9 seconds
Started Jul 22 07:23:43 PM PDT 24
Finished Jul 22 07:25:08 PM PDT 24
Peak memory 266932 kb
Host smart-489d6248-999e-4beb-ba1a-a188d3426161
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121066644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.4121066644
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1421203408
Short name T822
Test name
Test status
Simulation time 3651493727 ps
CPU time 26.69 seconds
Started Jul 22 07:23:41 PM PDT 24
Finished Jul 22 07:24:31 PM PDT 24
Peak memory 246556 kb
Host smart-4d84e35f-8813-42ad-b453-2eb1f5dcf9aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421203408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1421203408
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1248010592
Short name T565
Test name
Test status
Simulation time 30587155 ps
CPU time 1.61 seconds
Started Jul 22 07:20:51 PM PDT 24
Finished Jul 22 07:21:16 PM PDT 24
Peak memory 217820 kb
Host smart-07c00cd7-c2b8-4612-989b-21a833efb86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248010592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1248010592
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1319368381
Short name T801
Test name
Test status
Simulation time 665943039 ps
CPU time 22.8 seconds
Started Jul 22 07:23:41 PM PDT 24
Finished Jul 22 07:24:26 PM PDT 24
Peak memory 214500 kb
Host smart-b5114cf8-d159-4ae6-9fea-c4bfbba0271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319368381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1319368381
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.448818773
Short name T53
Test name
Test status
Simulation time 226080980 ps
CPU time 36.02 seconds
Started Jul 22 07:20:56 PM PDT 24
Finished Jul 22 07:22:03 PM PDT 24
Peak memory 270772 kb
Host smart-1f4f8f98-5af6-4850-8e46-6d52ffe879e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448818773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.448818773
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1913184801
Short name T735
Test name
Test status
Simulation time 171636228 ps
CPU time 8.77 seconds
Started Jul 22 07:20:56 PM PDT 24
Finished Jul 22 07:21:36 PM PDT 24
Peak memory 225584 kb
Host smart-3390673d-a10c-425d-8b9c-3b50084fed20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913184801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1913184801
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3013428973
Short name T414
Test name
Test status
Simulation time 546008343 ps
CPU time 18.16 seconds
Started Jul 22 07:20:54 PM PDT 24
Finished Jul 22 07:21:41 PM PDT 24
Peak memory 225588 kb
Host smart-1a6bddbd-a844-4a17-a74c-10d809ad7f21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013428973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
013428973
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3143776568
Short name T547
Test name
Test status
Simulation time 470815392 ps
CPU time 11.64 seconds
Started Jul 22 07:20:51 PM PDT 24
Finished Jul 22 07:21:26 PM PDT 24
Peak memory 217832 kb
Host smart-cd990a95-29f0-44e7-aeda-0c455bec5bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143776568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3143776568
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.755092442
Short name T72
Test name
Test status
Simulation time 241487029 ps
CPU time 2.26 seconds
Started Jul 22 07:20:50 PM PDT 24
Finished Jul 22 07:21:16 PM PDT 24
Peak memory 214172 kb
Host smart-9b53c883-2b14-40bb-9a0f-ce713628e6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755092442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.755092442
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.276064060
Short name T339
Test name
Test status
Simulation time 222668146 ps
CPU time 22.64 seconds
Started Jul 22 07:20:42 PM PDT 24
Finished Jul 22 07:21:12 PM PDT 24
Peak memory 250608 kb
Host smart-4d39e3d3-e3a4-4881-9c62-14c374f3a1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276064060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.276064060
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2180765811
Short name T651
Test name
Test status
Simulation time 54982997 ps
CPU time 3.64 seconds
Started Jul 22 07:20:50 PM PDT 24
Finished Jul 22 07:21:18 PM PDT 24
Peak memory 218052 kb
Host smart-04b3b87a-6d2a-4ef1-965f-e8f82c7724ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180765811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2180765811
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.486348033
Short name T412
Test name
Test status
Simulation time 28799184723 ps
CPU time 230.07 seconds
Started Jul 22 07:20:54 PM PDT 24
Finished Jul 22 07:25:11 PM PDT 24
Peak memory 274684 kb
Host smart-43f6c600-1b75-4868-9c79-ff56275a751a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486348033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.486348033
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2837464676
Short name T549
Test name
Test status
Simulation time 40213210 ps
CPU time 0.85 seconds
Started Jul 22 07:20:48 PM PDT 24
Finished Jul 22 07:21:12 PM PDT 24
Peak memory 211488 kb
Host smart-15a26596-49f2-4c03-a011-b284fb9a3330
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837464676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2837464676
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3201771510
Short name T653
Test name
Test status
Simulation time 660781412 ps
CPU time 15.37 seconds
Started Jul 22 07:22:26 PM PDT 24
Finished Jul 22 07:23:12 PM PDT 24
Peak memory 217832 kb
Host smart-63ed10e2-5e65-4fbe-b788-2d39a4bcf5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201771510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3201771510
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3328833160
Short name T539
Test name
Test status
Simulation time 381559975 ps
CPU time 9.57 seconds
Started Jul 22 07:22:23 PM PDT 24
Finished Jul 22 07:23:03 PM PDT 24
Peak memory 217336 kb
Host smart-814459ea-60cb-4552-b100-fb486a83c8f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328833160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3328833160
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3147774959
Short name T26
Test name
Test status
Simulation time 4694435689 ps
CPU time 69.5 seconds
Started Jul 22 07:22:24 PM PDT 24
Finished Jul 22 07:24:04 PM PDT 24
Peak memory 218532 kb
Host smart-f2e837df-1b51-4c9e-a0fd-b6f28a9aa20f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147774959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3147774959
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3214986032
Short name T275
Test name
Test status
Simulation time 1482748973 ps
CPU time 2.74 seconds
Started Jul 22 07:22:25 PM PDT 24
Finished Jul 22 07:22:58 PM PDT 24
Peak memory 221408 kb
Host smart-e2100fd4-418c-42f5-8963-9867b0610ad5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214986032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3214986032
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4000070163
Short name T795
Test name
Test status
Simulation time 124813430 ps
CPU time 2.12 seconds
Started Jul 22 07:22:24 PM PDT 24
Finished Jul 22 07:22:57 PM PDT 24
Peak memory 217268 kb
Host smart-4b4b4eb3-84d6-4e54-95fd-0983f3a44836
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000070163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.4000070163
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1319294417
Short name T504
Test name
Test status
Simulation time 4789889458 ps
CPU time 54.74 seconds
Started Jul 22 07:22:25 PM PDT 24
Finished Jul 22 07:23:51 PM PDT 24
Peak memory 283016 kb
Host smart-b6691f2d-adeb-4a99-9f16-be493ebcbe95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319294417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1319294417
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3084924335
Short name T474
Test name
Test status
Simulation time 497614893 ps
CPU time 14.39 seconds
Started Jul 22 07:22:26 PM PDT 24
Finished Jul 22 07:23:10 PM PDT 24
Peak memory 250552 kb
Host smart-e1550b36-df5f-4bb4-9b2d-ddc84d9cb6a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084924335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3084924335
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2831193222
Short name T292
Test name
Test status
Simulation time 28822394 ps
CPU time 2.12 seconds
Started Jul 22 07:22:24 PM PDT 24
Finished Jul 22 07:22:57 PM PDT 24
Peak memory 217844 kb
Host smart-da402d46-7b44-4817-b039-094f8ae1db92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831193222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2831193222
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.151146649
Short name T18
Test name
Test status
Simulation time 1038671662 ps
CPU time 10.31 seconds
Started Jul 22 07:22:27 PM PDT 24
Finished Jul 22 07:23:07 PM PDT 24
Peak memory 225576 kb
Host smart-54b44619-74d0-4f60-ab33-160d39b39a84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151146649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.151146649
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.888665301
Short name T435
Test name
Test status
Simulation time 229199802 ps
CPU time 6.27 seconds
Started Jul 22 07:22:31 PM PDT 24
Finished Jul 22 07:23:07 PM PDT 24
Peak memory 217836 kb
Host smart-2eb4c8bc-505a-4938-8779-56120f20e74a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888665301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.888665301
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1120515570
Short name T42
Test name
Test status
Simulation time 3108074646 ps
CPU time 9.46 seconds
Started Jul 22 07:22:27 PM PDT 24
Finished Jul 22 07:23:06 PM PDT 24
Peak memory 217952 kb
Host smart-8b44b77d-73e2-4259-a52e-b8ed9282cd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120515570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1120515570
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3355107496
Short name T534
Test name
Test status
Simulation time 74593022 ps
CPU time 2.82 seconds
Started Jul 22 07:22:27 PM PDT 24
Finished Jul 22 07:23:00 PM PDT 24
Peak memory 217260 kb
Host smart-ac26ea6a-3728-4e5a-89bc-0e2d983ee293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355107496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3355107496
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1013362713
Short name T202
Test name
Test status
Simulation time 237561171 ps
CPU time 26.51 seconds
Started Jul 22 07:22:25 PM PDT 24
Finished Jul 22 07:23:22 PM PDT 24
Peak memory 246216 kb
Host smart-e43b3528-eefc-41fa-bda9-7689c1e60251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013362713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1013362713
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4008321714
Short name T658
Test name
Test status
Simulation time 191614372 ps
CPU time 6.41 seconds
Started Jul 22 07:24:57 PM PDT 24
Finished Jul 22 07:26:10 PM PDT 24
Peak memory 247040 kb
Host smart-ca629eec-b7be-4e6a-88ba-a30a40e4bb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008321714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4008321714
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3838300486
Short name T157
Test name
Test status
Simulation time 35620657510 ps
CPU time 179.5 seconds
Started Jul 22 07:22:25 PM PDT 24
Finished Jul 22 07:25:54 PM PDT 24
Peak memory 272956 kb
Host smart-7a79a1df-fbf0-4783-8fe6-b4fabc8824a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838300486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3838300486
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1704981858
Short name T667
Test name
Test status
Simulation time 15421154 ps
CPU time 0.98 seconds
Started Jul 22 07:22:24 PM PDT 24
Finished Jul 22 07:22:55 PM PDT 24
Peak memory 211476 kb
Host smart-3f167f9c-15b4-480f-8449-b0b648bad548
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704981858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1704981858
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.731194062
Short name T603
Test name
Test status
Simulation time 18581075 ps
CPU time 1.03 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:07 PM PDT 24
Peak memory 208476 kb
Host smart-a6d29688-040a-44cd-8bac-6c4238da5e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731194062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.731194062
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.4197799428
Short name T767
Test name
Test status
Simulation time 482787697 ps
CPU time 12.79 seconds
Started Jul 22 07:22:37 PM PDT 24
Finished Jul 22 07:23:19 PM PDT 24
Peak memory 217864 kb
Host smart-9f1ae3e6-6785-4cbc-92ef-3af8d77dc012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197799428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.4197799428
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1469147400
Short name T31
Test name
Test status
Simulation time 604583346 ps
CPU time 14.66 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:20 PM PDT 24
Peak memory 216764 kb
Host smart-3d8ecc1b-6986-44f8-8bd9-59afce565bf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469147400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1469147400
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1005201387
Short name T439
Test name
Test status
Simulation time 14862034900 ps
CPU time 61.2 seconds
Started Jul 22 07:22:39 PM PDT 24
Finished Jul 22 07:24:08 PM PDT 24
Peak memory 218504 kb
Host smart-59a4476c-7bc1-4b28-944f-56a39c8cd93a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005201387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1005201387
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1711610373
Short name T301
Test name
Test status
Simulation time 698521898 ps
CPU time 12.32 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 217740 kb
Host smart-64942401-8053-4be6-9c76-e059b972d6f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711610373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1711610373
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3530131842
Short name T67
Test name
Test status
Simulation time 1540657846 ps
CPU time 5.89 seconds
Started Jul 22 07:22:42 PM PDT 24
Finished Jul 22 07:23:15 PM PDT 24
Peak memory 217200 kb
Host smart-c88ab861-ea8d-498b-8230-e93ed18af4dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530131842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3530131842
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.897143764
Short name T596
Test name
Test status
Simulation time 21638754429 ps
CPU time 47.75 seconds
Started Jul 22 07:22:39 PM PDT 24
Finished Jul 22 07:23:54 PM PDT 24
Peak memory 267844 kb
Host smart-dbbda1e3-12fb-4af4-8210-593c0492730f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897143764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.897143764
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2610878621
Short name T593
Test name
Test status
Simulation time 1771762635 ps
CPU time 13.7 seconds
Started Jul 22 07:22:37 PM PDT 24
Finished Jul 22 07:23:20 PM PDT 24
Peak memory 246372 kb
Host smart-494dac52-1d99-4d26-878a-be674f5ec137
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610878621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2610878621
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1133674774
Short name T417
Test name
Test status
Simulation time 93352587 ps
CPU time 2.84 seconds
Started Jul 22 07:22:39 PM PDT 24
Finished Jul 22 07:23:09 PM PDT 24
Peak memory 217784 kb
Host smart-b53f2aab-b192-4d18-b529-06b42dfd3daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133674774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1133674774
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.22043348
Short name T610
Test name
Test status
Simulation time 338794372 ps
CPU time 13.25 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:19 PM PDT 24
Peak memory 225512 kb
Host smart-8e90a3cb-e0f1-40e8-a1ea-17b619ffab82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22043348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_dig
est.22043348
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.556420752
Short name T721
Test name
Test status
Simulation time 281745024 ps
CPU time 10.82 seconds
Started Jul 22 07:22:38 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 225656 kb
Host smart-26b47359-182f-478b-930d-7c8cdc3714d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556420752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.556420752
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1674240889
Short name T348
Test name
Test status
Simulation time 291572403 ps
CPU time 7.62 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:13 PM PDT 24
Peak memory 224580 kb
Host smart-5b1c8f55-b54d-478e-81ed-b9e7baf59447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674240889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1674240889
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1542879246
Short name T36
Test name
Test status
Simulation time 119845217 ps
CPU time 2.47 seconds
Started Jul 22 07:22:27 PM PDT 24
Finished Jul 22 07:22:59 PM PDT 24
Peak memory 214284 kb
Host smart-d210014a-7aec-4348-adc9-280f4a351fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542879246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1542879246
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4256658563
Short name T74
Test name
Test status
Simulation time 288546679 ps
CPU time 27.54 seconds
Started Jul 22 07:23:45 PM PDT 24
Finished Jul 22 07:24:36 PM PDT 24
Peak memory 250540 kb
Host smart-1812effa-3923-4c8c-ace6-148cffa47e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256658563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4256658563
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1768897098
Short name T496
Test name
Test status
Simulation time 66575397 ps
CPU time 8.22 seconds
Started Jul 22 07:22:49 PM PDT 24
Finished Jul 22 07:23:22 PM PDT 24
Peak memory 250524 kb
Host smart-0644f3fe-c4fe-4b08-b859-59c6745e9536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768897098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1768897098
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1896894890
Short name T492
Test name
Test status
Simulation time 14734264430 ps
CPU time 162.23 seconds
Started Jul 22 07:22:44 PM PDT 24
Finished Jul 22 07:25:53 PM PDT 24
Peak memory 283220 kb
Host smart-26b7a424-c9dd-4b96-8d5b-ba29f9ee6e04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896894890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1896894890
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1005088988
Short name T132
Test name
Test status
Simulation time 13518631511 ps
CPU time 319.05 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:28:24 PM PDT 24
Peak memory 421604 kb
Host smart-49999232-32da-4f09-a625-5136adc9422b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1005088988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.1005088988
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1254503695
Short name T191
Test name
Test status
Simulation time 13266211 ps
CPU time 1.1 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:07 PM PDT 24
Peak memory 211452 kb
Host smart-a4317aae-4b15-48ec-9d1d-e2556dbc8da1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254503695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1254503695
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3864285181
Short name T722
Test name
Test status
Simulation time 42819454 ps
CPU time 0.99 seconds
Started Jul 22 07:22:44 PM PDT 24
Finished Jul 22 07:23:12 PM PDT 24
Peak memory 208480 kb
Host smart-5a775386-4ac1-4ed9-af9c-16f285657dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864285181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3864285181
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.4278638451
Short name T304
Test name
Test status
Simulation time 410951924 ps
CPU time 12.87 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:19 PM PDT 24
Peak memory 217852 kb
Host smart-45abef95-c3b8-49ab-a8bf-c43b9682c444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278638451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.4278638451
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2832993241
Short name T10
Test name
Test status
Simulation time 291883613 ps
CPU time 4.82 seconds
Started Jul 22 07:22:39 PM PDT 24
Finished Jul 22 07:23:11 PM PDT 24
Peak memory 217268 kb
Host smart-fafce5b6-5a31-4edc-a9cc-f27b8c644b3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832993241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2832993241
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2636441062
Short name T682
Test name
Test status
Simulation time 10388352909 ps
CPU time 30.63 seconds
Started Jul 22 07:22:44 PM PDT 24
Finished Jul 22 07:23:42 PM PDT 24
Peak memory 217832 kb
Host smart-e459458f-6339-470b-b488-9917858b621a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636441062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2636441062
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3503201562
Short name T648
Test name
Test status
Simulation time 366771054 ps
CPU time 11.37 seconds
Started Jul 22 07:22:37 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 217780 kb
Host smart-b0d4bab9-9ef3-4443-a696-8bf4a6afc5cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503201562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3503201562
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.4196626811
Short name T497
Test name
Test status
Simulation time 148701133 ps
CPU time 4.31 seconds
Started Jul 22 07:22:35 PM PDT 24
Finished Jul 22 07:23:09 PM PDT 24
Peak memory 217188 kb
Host smart-6b5bb104-bbd3-4609-ac51-9fea494e69d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196626811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.4196626811
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3198589137
Short name T432
Test name
Test status
Simulation time 1176191075 ps
CPU time 35.21 seconds
Started Jul 22 07:22:35 PM PDT 24
Finished Jul 22 07:23:40 PM PDT 24
Peak memory 266912 kb
Host smart-31dbece2-05ae-4273-8522-7593c3215c66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198589137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3198589137
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2346800096
Short name T38
Test name
Test status
Simulation time 3434977347 ps
CPU time 24.26 seconds
Started Jul 22 07:22:43 PM PDT 24
Finished Jul 22 07:23:34 PM PDT 24
Peak memory 226024 kb
Host smart-44ae9cfe-06c7-406d-90ba-17a9eb40e26c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346800096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2346800096
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.4042536301
Short name T803
Test name
Test status
Simulation time 56297989 ps
CPU time 2.69 seconds
Started Jul 22 07:22:37 PM PDT 24
Finished Jul 22 07:23:08 PM PDT 24
Peak memory 221956 kb
Host smart-68d84c94-5f99-437f-a8e9-d98a93e4f992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042536301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4042536301
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2580664889
Short name T600
Test name
Test status
Simulation time 1344432671 ps
CPU time 17.66 seconds
Started Jul 22 07:22:39 PM PDT 24
Finished Jul 22 07:23:24 PM PDT 24
Peak memory 218568 kb
Host smart-de673d8f-5a90-4be4-a594-356ba501e81c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580664889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2580664889
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1655107035
Short name T533
Test name
Test status
Simulation time 4632725414 ps
CPU time 26.12 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:40 PM PDT 24
Peak memory 225668 kb
Host smart-e54db545-3ce0-452f-84c2-14571b50bcf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655107035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1655107035
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.4216095564
Short name T675
Test name
Test status
Simulation time 329256515 ps
CPU time 11.21 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:25 PM PDT 24
Peak memory 217836 kb
Host smart-f2c055a5-efcc-4a41-9392-57db7e23cfb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216095564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
4216095564
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3360837201
Short name T346
Test name
Test status
Simulation time 375808367 ps
CPU time 11.5 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 217956 kb
Host smart-9432bdcd-8ce1-4aeb-a089-b35e1a081fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360837201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3360837201
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3818399148
Short name T752
Test name
Test status
Simulation time 528456021 ps
CPU time 3.41 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 217164 kb
Host smart-48057012-9621-4de6-863a-9f5a4a5edd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818399148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3818399148
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1169480435
Short name T655
Test name
Test status
Simulation time 172201725 ps
CPU time 17.46 seconds
Started Jul 22 07:22:38 PM PDT 24
Finished Jul 22 07:23:24 PM PDT 24
Peak memory 246072 kb
Host smart-c4690579-9b34-4ae7-8a81-452c5fbc9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169480435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1169480435
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1845531688
Short name T247
Test name
Test status
Simulation time 38853663 ps
CPU time 6.63 seconds
Started Jul 22 07:22:35 PM PDT 24
Finished Jul 22 07:23:12 PM PDT 24
Peak memory 250016 kb
Host smart-333b7cab-5ef0-43b5-b2c8-b6d22aec1fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845531688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1845531688
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.763989792
Short name T697
Test name
Test status
Simulation time 26665830863 ps
CPU time 207.73 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:26:42 PM PDT 24
Peak memory 250508 kb
Host smart-5c764730-0918-4391-b9ea-00a84d4af416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763989792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.763989792
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.351583108
Short name T137
Test name
Test status
Simulation time 166367165630 ps
CPU time 571.12 seconds
Started Jul 22 07:22:44 PM PDT 24
Finished Jul 22 07:32:42 PM PDT 24
Peak memory 277204 kb
Host smart-44c4ef54-386e-4028-b2da-873120ffab4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=351583108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.351583108
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3056569168
Short name T259
Test name
Test status
Simulation time 12696396 ps
CPU time 0.86 seconds
Started Jul 22 07:22:36 PM PDT 24
Finished Jul 22 07:23:07 PM PDT 24
Peak memory 211452 kb
Host smart-1ec37f10-b72f-4327-8821-c2594322975b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056569168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3056569168
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3995794836
Short name T778
Test name
Test status
Simulation time 15431392 ps
CPU time 1.09 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:23:24 PM PDT 24
Peak memory 208448 kb
Host smart-c0ca520f-4296-42a1-86db-f2c2f966cbaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995794836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3995794836
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.655936385
Short name T563
Test name
Test status
Simulation time 278965263 ps
CPU time 12.07 seconds
Started Jul 22 07:22:38 PM PDT 24
Finished Jul 22 07:23:18 PM PDT 24
Peak memory 217928 kb
Host smart-8c554602-c524-4d90-b6cb-c8dbe82852af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655936385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.655936385
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3449173982
Short name T734
Test name
Test status
Simulation time 3079440410 ps
CPU time 47.18 seconds
Started Jul 22 07:22:46 PM PDT 24
Finished Jul 22 07:24:00 PM PDT 24
Peak memory 218488 kb
Host smart-61b51be0-087c-4583-a444-9c68b2c2e6c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449173982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3449173982
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3061216458
Short name T695
Test name
Test status
Simulation time 639901712 ps
CPU time 9.22 seconds
Started Jul 22 07:23:45 PM PDT 24
Finished Jul 22 07:24:18 PM PDT 24
Peak memory 223772 kb
Host smart-5e926fa1-78b9-4cfc-ac21-efd44d353f3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061216458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3061216458
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2311593202
Short name T809
Test name
Test status
Simulation time 5415301082 ps
CPU time 13.76 seconds
Started Jul 22 07:23:45 PM PDT 24
Finished Jul 22 07:24:22 PM PDT 24
Peak memory 217268 kb
Host smart-cbd0b563-813a-4098-89da-985c3e01be79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311593202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2311593202
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.456825564
Short name T249
Test name
Test status
Simulation time 2074999934 ps
CPU time 54.46 seconds
Started Jul 22 07:22:39 PM PDT 24
Finished Jul 22 07:24:01 PM PDT 24
Peak memory 270452 kb
Host smart-e1954457-054f-4a04-a074-875d4775f6f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456825564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.456825564
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2354903681
Short name T572
Test name
Test status
Simulation time 304482968 ps
CPU time 11.91 seconds
Started Jul 22 07:22:44 PM PDT 24
Finished Jul 22 07:23:22 PM PDT 24
Peak memory 250536 kb
Host smart-000bcb68-afd5-4dd1-9d90-705347646426
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354903681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2354903681
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1442326975
Short name T688
Test name
Test status
Simulation time 46488375 ps
CPU time 1.98 seconds
Started Jul 22 07:22:42 PM PDT 24
Finished Jul 22 07:23:10 PM PDT 24
Peak memory 217852 kb
Host smart-39a11112-4c83-4cb1-a2e8-e85a795d800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442326975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1442326975
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3761766108
Short name T225
Test name
Test status
Simulation time 236300111 ps
CPU time 10.53 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:23:33 PM PDT 24
Peak memory 225556 kb
Host smart-34e26ceb-08b0-4a86-a18a-ecb636554675
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761766108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3761766108
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3171563322
Short name T331
Test name
Test status
Simulation time 1661826745 ps
CPU time 9.56 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:23 PM PDT 24
Peak memory 225592 kb
Host smart-e1e00dfa-1c03-41c3-892e-2f34857de5f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171563322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3171563322
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3201882445
Short name T537
Test name
Test status
Simulation time 264323966 ps
CPU time 10.77 seconds
Started Jul 22 07:22:37 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 218104 kb
Host smart-ad82c391-5030-413a-9430-484ed522dd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201882445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3201882445
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2087258768
Short name T58
Test name
Test status
Simulation time 71230140 ps
CPU time 2.4 seconds
Started Jul 22 07:22:38 PM PDT 24
Finished Jul 22 07:23:08 PM PDT 24
Peak memory 217464 kb
Host smart-412fced1-03c1-4752-871a-3bbcba32208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087258768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2087258768
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.952191692
Short name T443
Test name
Test status
Simulation time 543813025 ps
CPU time 26.82 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:24:19 PM PDT 24
Peak memory 246216 kb
Host smart-f373817f-4d36-4c75-98fd-eeff33952a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952191692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.952191692
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2052164415
Short name T569
Test name
Test status
Simulation time 277622875 ps
CPU time 3.16 seconds
Started Jul 22 07:23:45 PM PDT 24
Finished Jul 22 07:24:12 PM PDT 24
Peak memory 217844 kb
Host smart-a363f6b1-610d-4aae-9318-832714486b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052164415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2052164415
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3247363165
Short name T608
Test name
Test status
Simulation time 23058539691 ps
CPU time 436.16 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:30:39 PM PDT 24
Peak memory 233904 kb
Host smart-81a60bca-60e1-4b5c-80cf-8c511707008f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247363165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3247363165
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2722310047
Short name T366
Test name
Test status
Simulation time 100228273538 ps
CPU time 529.98 seconds
Started Jul 22 07:23:48 PM PDT 24
Finished Jul 22 07:33:04 PM PDT 24
Peak memory 389020 kb
Host smart-d673dec7-b874-4870-aeca-5d93f0ef7d17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2722310047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2722310047
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3466789340
Short name T562
Test name
Test status
Simulation time 15539296 ps
CPU time 0.99 seconds
Started Jul 22 07:22:35 PM PDT 24
Finished Jul 22 07:23:06 PM PDT 24
Peak memory 211420 kb
Host smart-7b7ec7fd-7497-487a-9634-26c7a960d59b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466789340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3466789340
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1663043460
Short name T840
Test name
Test status
Simulation time 26492817 ps
CPU time 1.48 seconds
Started Jul 22 07:22:45 PM PDT 24
Finished Jul 22 07:23:14 PM PDT 24
Peak memory 208496 kb
Host smart-ece9a367-4c09-49ba-8589-ef93f6ab3057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663043460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1663043460
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1528480042
Short name T464
Test name
Test status
Simulation time 2019022151 ps
CPU time 8.05 seconds
Started Jul 22 07:22:45 PM PDT 24
Finished Jul 22 07:23:19 PM PDT 24
Peak memory 217852 kb
Host smart-04ae01c7-fdd8-4ad5-a0de-26a45dee3742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528480042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1528480042
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3601494183
Short name T444
Test name
Test status
Simulation time 39660625 ps
CPU time 1.79 seconds
Started Jul 22 07:22:46 PM PDT 24
Finished Jul 22 07:23:15 PM PDT 24
Peak memory 216648 kb
Host smart-a9cc8ceb-6bcf-4bf0-83e5-21c3ff62ebd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601494183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3601494183
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3148072777
Short name T739
Test name
Test status
Simulation time 12080020295 ps
CPU time 60.11 seconds
Started Jul 22 07:22:46 PM PDT 24
Finished Jul 22 07:24:13 PM PDT 24
Peak memory 218668 kb
Host smart-a1191f7b-de29-4f38-8f95-9d4735630c37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148072777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3148072777
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2552735425
Short name T83
Test name
Test status
Simulation time 1219486946 ps
CPU time 4.06 seconds
Started Jul 22 07:22:45 PM PDT 24
Finished Jul 22 07:23:16 PM PDT 24
Peak memory 222604 kb
Host smart-47a0a3ef-ce7b-4d6e-a1be-d3f15c3176a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552735425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2552735425
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.695691855
Short name T406
Test name
Test status
Simulation time 446234179 ps
CPU time 6.57 seconds
Started Jul 22 07:22:45 PM PDT 24
Finished Jul 22 07:23:18 PM PDT 24
Peak memory 217184 kb
Host smart-2543cb4c-4a8d-433f-a741-a6a51463ef75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695691855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
695691855
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2269734156
Short name T220
Test name
Test status
Simulation time 4412236095 ps
CPU time 57.71 seconds
Started Jul 22 07:22:45 PM PDT 24
Finished Jul 22 07:24:09 PM PDT 24
Peak memory 283336 kb
Host smart-8dc19240-3b8d-4f9f-a773-abc246cd00a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269734156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2269734156
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3226184975
Short name T431
Test name
Test status
Simulation time 2912258638 ps
CPU time 16.3 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:23:39 PM PDT 24
Peak memory 250584 kb
Host smart-5177af92-0a99-4bd2-bb51-b6c82b4a69e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226184975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3226184975
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1705977732
Short name T524
Test name
Test status
Simulation time 20441253 ps
CPU time 1.84 seconds
Started Jul 22 07:22:49 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 217840 kb
Host smart-8bca249b-1cca-48a5-be8e-2b8bf8d0d0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705977732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1705977732
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.264274268
Short name T631
Test name
Test status
Simulation time 2112246283 ps
CPU time 13.33 seconds
Started Jul 22 07:22:49 PM PDT 24
Finished Jul 22 07:23:28 PM PDT 24
Peak memory 225688 kb
Host smart-a281e41a-ac32-4883-b10f-7348a07a2af1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264274268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.264274268
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1461418387
Short name T558
Test name
Test status
Simulation time 4707741653 ps
CPU time 16.01 seconds
Started Jul 22 07:22:45 PM PDT 24
Finished Jul 22 07:23:27 PM PDT 24
Peak memory 225648 kb
Host smart-703d51de-53e3-4f4c-960e-f534e212a55b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461418387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1461418387
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.385619225
Short name T516
Test name
Test status
Simulation time 1294167312 ps
CPU time 11.05 seconds
Started Jul 22 07:22:46 PM PDT 24
Finished Jul 22 07:23:23 PM PDT 24
Peak memory 217816 kb
Host smart-2a63177a-7793-4c13-bfd1-d2c4cf66324d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385619225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.385619225
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1767196155
Short name T49
Test name
Test status
Simulation time 799109818 ps
CPU time 8.79 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:23:31 PM PDT 24
Peak memory 217920 kb
Host smart-0d5312b9-7327-43b0-a874-d3e010239eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767196155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1767196155
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1359815369
Short name T425
Test name
Test status
Simulation time 61340056 ps
CPU time 1.85 seconds
Started Jul 22 07:22:46 PM PDT 24
Finished Jul 22 07:23:15 PM PDT 24
Peak memory 217384 kb
Host smart-b3b99085-97de-4b11-bb0b-a1725b441c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359815369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1359815369
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2767336912
Short name T732
Test name
Test status
Simulation time 1612341157 ps
CPU time 25.74 seconds
Started Jul 22 07:22:49 PM PDT 24
Finished Jul 22 07:23:40 PM PDT 24
Peak memory 250668 kb
Host smart-e0b185c9-6fce-45a1-9a66-5091cda324e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767336912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2767336912
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.92465609
Short name T267
Test name
Test status
Simulation time 464444248 ps
CPU time 4.51 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:18 PM PDT 24
Peak memory 217616 kb
Host smart-10fb8e2f-1fff-41c7-8b32-45375db2d3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92465609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.92465609
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3253473927
Short name T535
Test name
Test status
Simulation time 2774229798 ps
CPU time 92.91 seconds
Started Jul 22 07:22:46 PM PDT 24
Finished Jul 22 07:24:46 PM PDT 24
Peak memory 275284 kb
Host smart-b4b1ea84-9cb9-46ce-bba3-def99ccaa298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253473927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3253473927
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1350417310
Short name T136
Test name
Test status
Simulation time 140135321197 ps
CPU time 767.27 seconds
Started Jul 22 07:22:47 PM PDT 24
Finished Jul 22 07:36:00 PM PDT 24
Peak memory 611092 kb
Host smart-fdc7caa8-c046-415c-b142-b7d948a670e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1350417310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1350417310
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.4076076536
Short name T306
Test name
Test status
Simulation time 19999847 ps
CPU time 1.17 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:15 PM PDT 24
Peak memory 212632 kb
Host smart-e6ba5994-c45d-4160-9c87-fba54d37fcbc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076076536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.4076076536
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2814003287
Short name T756
Test name
Test status
Simulation time 65835574 ps
CPU time 0.89 seconds
Started Jul 22 07:22:59 PM PDT 24
Finished Jul 22 07:23:24 PM PDT 24
Peak memory 208612 kb
Host smart-f11054d7-1751-4e3b-a238-0ee3ef4c67f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814003287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2814003287
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2366838577
Short name T375
Test name
Test status
Simulation time 444563831 ps
CPU time 13.46 seconds
Started Jul 22 07:23:01 PM PDT 24
Finished Jul 22 07:23:39 PM PDT 24
Peak memory 217844 kb
Host smart-bb94580c-92e7-4c79-92b1-fb15ea05d09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366838577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2366838577
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2683966431
Short name T791
Test name
Test status
Simulation time 53192631 ps
CPU time 2.14 seconds
Started Jul 22 07:23:00 PM PDT 24
Finished Jul 22 07:23:26 PM PDT 24
Peak memory 217272 kb
Host smart-4b719348-b898-4bb7-9405-d8adb3a6be7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683966431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2683966431
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3897133204
Short name T814
Test name
Test status
Simulation time 3388289478 ps
CPU time 33.88 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:23:56 PM PDT 24
Peak memory 218272 kb
Host smart-42d3fe2b-2015-446a-b9cd-5c94987a6b74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897133204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3897133204
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2577271203
Short name T862
Test name
Test status
Simulation time 3720959282 ps
CPU time 5.13 seconds
Started Jul 22 07:23:00 PM PDT 24
Finished Jul 22 07:23:30 PM PDT 24
Peak memory 223400 kb
Host smart-5461d792-46e6-471c-a86a-18279ba53c73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577271203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2577271203
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1146485591
Short name T235
Test name
Test status
Simulation time 175529755 ps
CPU time 2.81 seconds
Started Jul 22 07:23:02 PM PDT 24
Finished Jul 22 07:23:30 PM PDT 24
Peak memory 217180 kb
Host smart-d18f2495-2b6f-4a54-8773-51fcde1c60dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146485591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1146485591
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1501343298
Short name T711
Test name
Test status
Simulation time 24903433205 ps
CPU time 46.52 seconds
Started Jul 22 07:23:02 PM PDT 24
Finished Jul 22 07:24:13 PM PDT 24
Peak memory 275228 kb
Host smart-96f8b792-83ae-49a1-9e85-4c7d63a974c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501343298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1501343298
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3436459846
Short name T532
Test name
Test status
Simulation time 6766334815 ps
CPU time 18.52 seconds
Started Jul 22 07:23:03 PM PDT 24
Finished Jul 22 07:23:47 PM PDT 24
Peak memory 249952 kb
Host smart-8598ebdc-15e0-409d-bf33-8aad9aabb9f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436459846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3436459846
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.521898311
Short name T455
Test name
Test status
Simulation time 414132491 ps
CPU time 4.6 seconds
Started Jul 22 07:22:59 PM PDT 24
Finished Jul 22 07:23:28 PM PDT 24
Peak memory 217848 kb
Host smart-ac2ce1eb-6101-42ec-926f-083672c10cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521898311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.521898311
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1051864060
Short name T782
Test name
Test status
Simulation time 2524604371 ps
CPU time 12.61 seconds
Started Jul 22 07:23:01 PM PDT 24
Finished Jul 22 07:23:38 PM PDT 24
Peak memory 225720 kb
Host smart-a83e6ee9-29ac-481a-bb16-3d818c025d5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051864060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1051864060
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.4292855586
Short name T570
Test name
Test status
Simulation time 1043323152 ps
CPU time 9.09 seconds
Started Jul 22 07:23:43 PM PDT 24
Finished Jul 22 07:24:16 PM PDT 24
Peak memory 225588 kb
Host smart-bc63b9ca-ed3b-471f-b60d-5bdce6799793
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292855586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.4292855586
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2447141024
Short name T255
Test name
Test status
Simulation time 218303339 ps
CPU time 9.39 seconds
Started Jul 22 07:22:59 PM PDT 24
Finished Jul 22 07:23:32 PM PDT 24
Peak memory 217800 kb
Host smart-a021346d-c7b9-48d9-b8ab-e5327f1804ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447141024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2447141024
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1695819783
Short name T685
Test name
Test status
Simulation time 503751448 ps
CPU time 7.47 seconds
Started Jul 22 07:22:59 PM PDT 24
Finished Jul 22 07:23:30 PM PDT 24
Peak memory 217852 kb
Host smart-b13f02d1-ccde-4639-a3de-4eb076b4135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695819783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1695819783
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1091280633
Short name T440
Test name
Test status
Simulation time 114930138 ps
CPU time 2.03 seconds
Started Jul 22 07:22:47 PM PDT 24
Finished Jul 22 07:23:15 PM PDT 24
Peak memory 213736 kb
Host smart-907ddca9-9c14-44db-9f3c-cf2e85f3884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091280633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1091280633
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.834867071
Short name T632
Test name
Test status
Simulation time 470046502 ps
CPU time 18.08 seconds
Started Jul 22 07:22:47 PM PDT 24
Finished Jul 22 07:23:31 PM PDT 24
Peak memory 250496 kb
Host smart-c32440ff-0ab2-424d-8988-d767007a8612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834867071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.834867071
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3642730753
Short name T64
Test name
Test status
Simulation time 120124279 ps
CPU time 4.32 seconds
Started Jul 22 07:23:00 PM PDT 24
Finished Jul 22 07:23:28 PM PDT 24
Peak memory 222432 kb
Host smart-a5bdce04-74d6-40d9-bef9-2b5fc41557d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642730753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3642730753
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4174776045
Short name T316
Test name
Test status
Simulation time 7295184304 ps
CPU time 132.36 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:25:35 PM PDT 24
Peak memory 275556 kb
Host smart-a6047899-0e92-46cc-b010-d66c0c7e71f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174776045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4174776045
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2151989112
Short name T90
Test name
Test status
Simulation time 226387957701 ps
CPU time 1723.31 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:52:06 PM PDT 24
Peak memory 512960 kb
Host smart-23286f48-3761-45b6-849e-fd3b5d3205b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2151989112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2151989112
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.725549278
Short name T441
Test name
Test status
Simulation time 13356412 ps
CPU time 1.09 seconds
Started Jul 22 07:22:58 PM PDT 24
Finished Jul 22 07:23:24 PM PDT 24
Peak memory 211420 kb
Host smart-c36a331b-e543-4fbc-914d-e641d6be78b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725549278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.725549278
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.667915570
Short name T212
Test name
Test status
Simulation time 49823354 ps
CPU time 0.82 seconds
Started Jul 22 07:24:30 PM PDT 24
Finished Jul 22 07:25:21 PM PDT 24
Peak memory 208264 kb
Host smart-45e80b2b-3abb-481f-8561-52dd8f88f2b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667915570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.667915570
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2303139244
Short name T507
Test name
Test status
Simulation time 503334229 ps
CPU time 12.92 seconds
Started Jul 22 07:23:11 PM PDT 24
Finished Jul 22 07:23:48 PM PDT 24
Peak memory 217832 kb
Host smart-59fdc091-bd62-432b-a015-04d374cb340e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303139244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2303139244
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2189669769
Short name T30
Test name
Test status
Simulation time 412313660 ps
CPU time 6.05 seconds
Started Jul 22 07:23:09 PM PDT 24
Finished Jul 22 07:23:38 PM PDT 24
Peak memory 217452 kb
Host smart-327a1bfa-228f-402f-a519-9e3eb15f8975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189669769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2189669769
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1998930493
Short name T805
Test name
Test status
Simulation time 6216300941 ps
CPU time 29 seconds
Started Jul 22 07:23:12 PM PDT 24
Finished Jul 22 07:24:04 PM PDT 24
Peak memory 218560 kb
Host smart-a072921f-7e96-4c25-8ab7-e60ca132426e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998930493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1998930493
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1200606
Short name T835
Test name
Test status
Simulation time 2187418339 ps
CPU time 4.07 seconds
Started Jul 22 07:23:10 PM PDT 24
Finished Jul 22 07:23:37 PM PDT 24
Peak memory 222476 kb
Host smart-3f71fc8f-1d7b-4bd3-8179-7a1157c5dbb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_pr
og_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_p
rog_failure.1200606
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2790925856
Short name T617
Test name
Test status
Simulation time 2391139879 ps
CPU time 5.93 seconds
Started Jul 22 07:23:09 PM PDT 24
Finished Jul 22 07:23:39 PM PDT 24
Peak memory 217244 kb
Host smart-a875c655-3643-4001-b2e4-ec16035fbefa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790925856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2790925856
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3632089757
Short name T611
Test name
Test status
Simulation time 6120745233 ps
CPU time 49.22 seconds
Started Jul 22 07:23:09 PM PDT 24
Finished Jul 22 07:24:22 PM PDT 24
Peak memory 266920 kb
Host smart-ec50fa0c-9e66-4d88-a6d0-bfb89af39519
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632089757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3632089757
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2168041752
Short name T720
Test name
Test status
Simulation time 387860915 ps
CPU time 16.09 seconds
Started Jul 22 07:23:07 PM PDT 24
Finished Jul 22 07:23:48 PM PDT 24
Peak memory 247196 kb
Host smart-92cdfd1f-2fe1-446a-89a5-bbebe8e4315b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168041752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2168041752
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1266489013
Short name T779
Test name
Test status
Simulation time 407517708 ps
CPU time 3.13 seconds
Started Jul 22 07:23:07 PM PDT 24
Finished Jul 22 07:23:35 PM PDT 24
Peak memory 217960 kb
Host smart-b9b250c4-af5c-4d83-a2a0-7486f10819be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266489013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1266489013
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1573298250
Short name T388
Test name
Test status
Simulation time 693689479 ps
CPU time 15.63 seconds
Started Jul 22 07:23:07 PM PDT 24
Finished Jul 22 07:23:47 PM PDT 24
Peak memory 217944 kb
Host smart-9881b9ed-9f48-407f-9f56-ff7bbc2de4ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573298250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1573298250
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1848176746
Short name T408
Test name
Test status
Simulation time 439584199 ps
CPU time 11.15 seconds
Started Jul 22 07:23:08 PM PDT 24
Finished Jul 22 07:23:43 PM PDT 24
Peak memory 225580 kb
Host smart-0cf95390-98f3-4d36-9a89-9de21e92743f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848176746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1848176746
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.463084431
Short name T377
Test name
Test status
Simulation time 695774997 ps
CPU time 9.52 seconds
Started Jul 22 07:23:09 PM PDT 24
Finished Jul 22 07:23:42 PM PDT 24
Peak memory 225624 kb
Host smart-4115bb58-7443-4bb9-b67a-cc0b5565cbfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463084431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.463084431
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2178325074
Short name T158
Test name
Test status
Simulation time 1331290026 ps
CPU time 13.63 seconds
Started Jul 22 07:23:36 PM PDT 24
Finished Jul 22 07:24:09 PM PDT 24
Peak memory 217868 kb
Host smart-e5520c1d-8db7-4609-9caf-e32cfd5f8cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178325074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2178325074
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2368099331
Short name T214
Test name
Test status
Simulation time 26782857 ps
CPU time 2.24 seconds
Started Jul 22 07:23:03 PM PDT 24
Finished Jul 22 07:23:31 PM PDT 24
Peak memory 212952 kb
Host smart-c4d54fd4-10aa-46a9-b9a4-215833c980c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368099331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2368099331
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.773464079
Short name T773
Test name
Test status
Simulation time 1285655410 ps
CPU time 25.75 seconds
Started Jul 22 07:23:01 PM PDT 24
Finished Jul 22 07:23:51 PM PDT 24
Peak memory 250684 kb
Host smart-40e20f52-ace7-4ad6-b32c-bacfc75bc59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773464079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.773464079
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.537899585
Short name T820
Test name
Test status
Simulation time 340367669 ps
CPU time 7.58 seconds
Started Jul 22 07:23:10 PM PDT 24
Finished Jul 22 07:23:42 PM PDT 24
Peak memory 250632 kb
Host smart-99e26edb-95f1-4a83-9312-d3a2a64d43f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537899585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.537899585
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.4289254875
Short name T578
Test name
Test status
Simulation time 4591096102 ps
CPU time 119.02 seconds
Started Jul 22 07:23:11 PM PDT 24
Finished Jul 22 07:25:34 PM PDT 24
Peak memory 273940 kb
Host smart-dbdf2c4f-aa74-424b-bb65-e61907f10872
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289254875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.4289254875
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3227712435
Short name T141
Test name
Test status
Simulation time 156062491485 ps
CPU time 169.92 seconds
Started Jul 22 07:23:11 PM PDT 24
Finished Jul 22 07:26:24 PM PDT 24
Peak memory 282724 kb
Host smart-d2e1023f-2a70-4b2d-b877-d7cfcda57e8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3227712435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3227712435
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.696480161
Short name T725
Test name
Test status
Simulation time 31753471 ps
CPU time 0.92 seconds
Started Jul 22 07:23:04 PM PDT 24
Finished Jul 22 07:23:30 PM PDT 24
Peak memory 211524 kb
Host smart-18a8a8da-7248-4629-9f23-ab6a0c845c93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696480161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.696480161
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3700755955
Short name T500
Test name
Test status
Simulation time 82857161 ps
CPU time 1.11 seconds
Started Jul 22 07:23:24 PM PDT 24
Finished Jul 22 07:23:43 PM PDT 24
Peak memory 208716 kb
Host smart-c7a952b4-e983-4c99-a530-3671f3ce9931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700755955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3700755955
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.249874337
Short name T715
Test name
Test status
Simulation time 1902868737 ps
CPU time 12.22 seconds
Started Jul 22 07:23:10 PM PDT 24
Finished Jul 22 07:23:46 PM PDT 24
Peak memory 217804 kb
Host smart-ca0c5ab0-f0b1-4281-a888-c0d44b097077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249874337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.249874337
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.876817913
Short name T376
Test name
Test status
Simulation time 283535338 ps
CPU time 4.82 seconds
Started Jul 22 07:23:17 PM PDT 24
Finished Jul 22 07:23:43 PM PDT 24
Peak memory 217276 kb
Host smart-24375b9d-7a5d-46da-9139-6cbf999b8d0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876817913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.876817913
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.556093232
Short name T430
Test name
Test status
Simulation time 1777872519 ps
CPU time 55.48 seconds
Started Jul 22 07:23:17 PM PDT 24
Finished Jul 22 07:24:34 PM PDT 24
Peak memory 218424 kb
Host smart-43e91bc2-c308-4656-857b-af3d3ecd6a23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556093232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.556093232
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.503110955
Short name T665
Test name
Test status
Simulation time 6781777647 ps
CPU time 8.41 seconds
Started Jul 22 07:23:18 PM PDT 24
Finished Jul 22 07:23:47 PM PDT 24
Peak memory 224416 kb
Host smart-910a99f0-29f4-495b-9808-3191092c50c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503110955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.503110955
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1697563872
Short name T453
Test name
Test status
Simulation time 666044636 ps
CPU time 8.6 seconds
Started Jul 22 07:23:10 PM PDT 24
Finished Jul 22 07:23:43 PM PDT 24
Peak memory 217140 kb
Host smart-310ebc82-4a07-4436-bd4e-a89cd7fbacff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697563872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1697563872
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.567490048
Short name T731
Test name
Test status
Simulation time 7278155739 ps
CPU time 77.9 seconds
Started Jul 22 07:23:09 PM PDT 24
Finished Jul 22 07:24:50 PM PDT 24
Peak memory 281924 kb
Host smart-94247bbe-7ad0-4ab8-8226-f6514a3cd14a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567490048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.567490048
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.886160759
Short name T429
Test name
Test status
Simulation time 1170610152 ps
CPU time 23.22 seconds
Started Jul 22 07:23:24 PM PDT 24
Finished Jul 22 07:24:05 PM PDT 24
Peak memory 250728 kb
Host smart-f8574cf0-d228-46b6-bedf-b0a6ae6ef78d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886160759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.886160759
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3326637667
Short name T2
Test name
Test status
Simulation time 105870982 ps
CPU time 3.04 seconds
Started Jul 22 07:23:08 PM PDT 24
Finished Jul 22 07:23:35 PM PDT 24
Peak memory 217856 kb
Host smart-c598969f-2edd-4dd0-b759-95d9f7b66c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326637667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3326637667
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.172276622
Short name T385
Test name
Test status
Simulation time 406938107 ps
CPU time 19.41 seconds
Started Jul 22 07:23:17 PM PDT 24
Finished Jul 22 07:23:58 PM PDT 24
Peak memory 217872 kb
Host smart-74168c38-12b7-48c8-a7f2-19f9a21b0185
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172276622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.172276622
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2985353465
Short name T628
Test name
Test status
Simulation time 1721636676 ps
CPU time 11.54 seconds
Started Jul 22 07:23:35 PM PDT 24
Finished Jul 22 07:24:05 PM PDT 24
Peak memory 225588 kb
Host smart-20b43f6f-0e37-41b3-b961-f1d82079581b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985353465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2985353465
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3510961600
Short name T221
Test name
Test status
Simulation time 2447829832 ps
CPU time 10.68 seconds
Started Jul 22 07:23:18 PM PDT 24
Finished Jul 22 07:23:49 PM PDT 24
Peak memory 217864 kb
Host smart-a9fb586f-4e8e-4505-b0bd-176ef8745dc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510961600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3510961600
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2779519897
Short name T192
Test name
Test status
Simulation time 405969574 ps
CPU time 16.38 seconds
Started Jul 22 07:23:08 PM PDT 24
Finished Jul 22 07:23:49 PM PDT 24
Peak memory 225616 kb
Host smart-bcda1007-16cf-4d9b-9c50-3a172a26099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779519897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2779519897
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.325890924
Short name T318
Test name
Test status
Simulation time 93496308 ps
CPU time 2.88 seconds
Started Jul 22 07:23:11 PM PDT 24
Finished Jul 22 07:23:37 PM PDT 24
Peak memory 213988 kb
Host smart-52c5c5d1-6587-41e0-8914-7f3a6121c624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325890924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.325890924
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.436816505
Short name T358
Test name
Test status
Simulation time 1419583162 ps
CPU time 30.37 seconds
Started Jul 22 07:23:07 PM PDT 24
Finished Jul 22 07:24:02 PM PDT 24
Peak memory 250672 kb
Host smart-256dfada-9b5b-44c2-9acc-f20302ce6976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436816505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.436816505
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1192014638
Short name T244
Test name
Test status
Simulation time 159986652 ps
CPU time 7.73 seconds
Started Jul 22 07:23:10 PM PDT 24
Finished Jul 22 07:23:41 PM PDT 24
Peak memory 250604 kb
Host smart-55dd5e36-bc2f-4d0a-988e-d44617aa544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192014638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1192014638
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3583155040
Short name T270
Test name
Test status
Simulation time 12211673258 ps
CPU time 198.69 seconds
Started Jul 22 07:23:19 PM PDT 24
Finished Jul 22 07:26:58 PM PDT 24
Peak memory 283348 kb
Host smart-3ddfc35a-ecfb-44ed-a4a7-4ef6e48b98a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583155040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3583155040
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3876635722
Short name T213
Test name
Test status
Simulation time 50617914 ps
CPU time 0.88 seconds
Started Jul 22 07:23:10 PM PDT 24
Finished Jul 22 07:23:35 PM PDT 24
Peak memory 212480 kb
Host smart-c3679fe1-49dd-497c-b37d-6fecc9a34755
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876635722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3876635722
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2132606309
Short name T494
Test name
Test status
Simulation time 30265020 ps
CPU time 0.88 seconds
Started Jul 22 07:23:29 PM PDT 24
Finished Jul 22 07:23:47 PM PDT 24
Peak memory 208444 kb
Host smart-53b18b49-5f01-4f88-97d2-46a2b48ae0d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132606309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2132606309
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2209367380
Short name T389
Test name
Test status
Simulation time 559440703 ps
CPU time 14.1 seconds
Started Jul 22 07:23:17 PM PDT 24
Finished Jul 22 07:23:52 PM PDT 24
Peak memory 217852 kb
Host smart-5a5fa226-d86e-4f45-bee5-53e31a17ab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209367380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2209367380
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3732916805
Short name T784
Test name
Test status
Simulation time 110638171 ps
CPU time 2.25 seconds
Started Jul 22 07:23:30 PM PDT 24
Finished Jul 22 07:23:50 PM PDT 24
Peak memory 217276 kb
Host smart-5888e137-615c-49d0-9245-8122e6b1cad0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732916805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3732916805
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.945133125
Short name T332
Test name
Test status
Simulation time 5275730215 ps
CPU time 140.98 seconds
Started Jul 22 07:23:51 PM PDT 24
Finished Jul 22 07:26:37 PM PDT 24
Peak memory 220660 kb
Host smart-360863e2-ad64-4a9c-b6e1-7374c39874e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945133125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.945133125
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2718767422
Short name T811
Test name
Test status
Simulation time 458441589 ps
CPU time 15.1 seconds
Started Jul 22 07:23:28 PM PDT 24
Finished Jul 22 07:24:01 PM PDT 24
Peak memory 217884 kb
Host smart-fd7812a9-298d-4110-9da2-ed58c0f63d26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718767422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2718767422
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2441347509
Short name T471
Test name
Test status
Simulation time 1552118025 ps
CPU time 12.26 seconds
Started Jul 22 07:23:28 PM PDT 24
Finished Jul 22 07:23:58 PM PDT 24
Peak memory 217192 kb
Host smart-ddd20f78-7459-4eee-ab7f-05b8080a9c32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441347509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2441347509
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1223694598
Short name T271
Test name
Test status
Simulation time 12002631097 ps
CPU time 62.41 seconds
Started Jul 22 07:23:28 PM PDT 24
Finished Jul 22 07:24:48 PM PDT 24
Peak memory 283192 kb
Host smart-a35323cf-31a3-4413-84d2-11dc184a0ace
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223694598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1223694598
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3639914896
Short name T491
Test name
Test status
Simulation time 1305385484 ps
CPU time 19.51 seconds
Started Jul 22 07:23:28 PM PDT 24
Finished Jul 22 07:24:06 PM PDT 24
Peak memory 222608 kb
Host smart-41744c07-397f-4147-9ee2-9f8db8be4034
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639914896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3639914896
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1181390307
Short name T832
Test name
Test status
Simulation time 23549003 ps
CPU time 1.88 seconds
Started Jul 22 07:23:17 PM PDT 24
Finished Jul 22 07:23:40 PM PDT 24
Peak memory 217864 kb
Host smart-45acde57-5911-438a-9116-4a1fe1dae65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181390307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1181390307
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2923928080
Short name T723
Test name
Test status
Simulation time 4968696655 ps
CPU time 16.14 seconds
Started Jul 22 07:23:29 PM PDT 24
Finished Jul 22 07:24:03 PM PDT 24
Peak memory 225736 kb
Host smart-f7493ed5-6eee-453c-98bf-8d1b57b108b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923928080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2923928080
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3336764286
Short name T557
Test name
Test status
Simulation time 1820743516 ps
CPU time 11.92 seconds
Started Jul 22 07:23:29 PM PDT 24
Finished Jul 22 07:23:58 PM PDT 24
Peak memory 225584 kb
Host smart-4b918672-b7fa-497f-bdb5-4b0d513f87c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336764286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3336764286
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.682977962
Short name T527
Test name
Test status
Simulation time 1283284230 ps
CPU time 8.49 seconds
Started Jul 22 07:23:32 PM PDT 24
Finished Jul 22 07:23:59 PM PDT 24
Peak memory 217800 kb
Host smart-e6b62a31-7fcd-48d1-9903-e5f7a5d802b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682977962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.682977962
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.357775056
Short name T656
Test name
Test status
Simulation time 290515051 ps
CPU time 8.38 seconds
Started Jul 22 07:23:28 PM PDT 24
Finished Jul 22 07:23:54 PM PDT 24
Peak memory 224768 kb
Host smart-5e016f85-861b-4100-8f15-6a1c08afbe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357775056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.357775056
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3349537816
Short name T241
Test name
Test status
Simulation time 16048128 ps
CPU time 1.25 seconds
Started Jul 22 07:23:18 PM PDT 24
Finished Jul 22 07:23:40 PM PDT 24
Peak memory 211892 kb
Host smart-74f264fd-9b37-41ac-acd3-c3b30e92cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349537816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3349537816
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1929439781
Short name T621
Test name
Test status
Simulation time 1001000086 ps
CPU time 30.89 seconds
Started Jul 22 07:23:23 PM PDT 24
Finished Jul 22 07:24:13 PM PDT 24
Peak memory 250784 kb
Host smart-cd4b9afe-2beb-4980-b167-a3dd45dfb049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929439781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1929439781
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1931291149
Short name T145
Test name
Test status
Simulation time 232605049 ps
CPU time 7.67 seconds
Started Jul 22 07:24:30 PM PDT 24
Finished Jul 22 07:25:28 PM PDT 24
Peak memory 250592 kb
Host smart-c951e259-eb9e-4b34-a1f2-8c3b52a0afbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931291149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1931291149
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2829987660
Short name T528
Test name
Test status
Simulation time 57820377641 ps
CPU time 245.26 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:28:37 PM PDT 24
Peak memory 225716 kb
Host smart-e36ef57d-1fe3-441e-a681-5d9a4f3e6fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829987660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2829987660
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.398844704
Short name T133
Test name
Test status
Simulation time 6666523281 ps
CPU time 175.9 seconds
Started Jul 22 07:23:29 PM PDT 24
Finished Jul 22 07:26:43 PM PDT 24
Peak memory 268920 kb
Host smart-d88444b9-4832-4e40-b6d5-652926b3314c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=398844704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.398844704
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4274100208
Short name T258
Test name
Test status
Simulation time 21425474 ps
CPU time 1.07 seconds
Started Jul 22 07:23:18 PM PDT 24
Finished Jul 22 07:23:40 PM PDT 24
Peak memory 217268 kb
Host smart-5dc522ba-4207-4666-b6a1-2184a8c4f526
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274100208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4274100208
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.4025631092
Short name T842
Test name
Test status
Simulation time 18560209 ps
CPU time 0.93 seconds
Started Jul 22 07:23:37 PM PDT 24
Finished Jul 22 07:23:59 PM PDT 24
Peak memory 208432 kb
Host smart-8d3796eb-c347-4f05-bbc1-431484d09671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025631092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.4025631092
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3835541998
Short name T802
Test name
Test status
Simulation time 1240506118 ps
CPU time 17.21 seconds
Started Jul 22 07:23:28 PM PDT 24
Finished Jul 22 07:24:03 PM PDT 24
Peak memory 217960 kb
Host smart-5d3746ec-2591-4432-87c0-d2e79ccd18cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835541998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3835541998
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.543206106
Short name T746
Test name
Test status
Simulation time 124348719 ps
CPU time 1.89 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:54 PM PDT 24
Peak memory 216704 kb
Host smart-f280440c-65fe-49d0-ac24-a6bae0cf89b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543206106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.543206106
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.345669243
Short name T851
Test name
Test status
Simulation time 5233521509 ps
CPU time 40.42 seconds
Started Jul 22 07:23:32 PM PDT 24
Finished Jul 22 07:24:31 PM PDT 24
Peak memory 218504 kb
Host smart-864f3f9e-7c2e-48bd-b501-257193cb29b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345669243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.345669243
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.538449792
Short name T785
Test name
Test status
Simulation time 662605959 ps
CPU time 5.49 seconds
Started Jul 22 07:24:06 PM PDT 24
Finished Jul 22 07:24:45 PM PDT 24
Peak memory 217776 kb
Host smart-96eab80d-24f4-411c-b965-c30f1d12ba1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538449792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.538449792
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.138582062
Short name T264
Test name
Test status
Simulation time 602343178 ps
CPU time 3.94 seconds
Started Jul 22 07:23:29 PM PDT 24
Finished Jul 22 07:23:50 PM PDT 24
Peak memory 217260 kb
Host smart-1b31a6e5-9793-4e25-bca4-889a54e40036
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138582062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
138582062
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1110589453
Short name T521
Test name
Test status
Simulation time 9022244216 ps
CPU time 49.57 seconds
Started Jul 22 07:23:30 PM PDT 24
Finished Jul 22 07:24:38 PM PDT 24
Peak memory 267060 kb
Host smart-309e125e-bd96-4cb2-a6f4-34a6ee23c257
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110589453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1110589453
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.4209305119
Short name T635
Test name
Test status
Simulation time 564136953 ps
CPU time 22.02 seconds
Started Jul 22 07:23:29 PM PDT 24
Finished Jul 22 07:24:09 PM PDT 24
Peak memory 250552 kb
Host smart-c0bdd63b-a3fd-4d9d-a6c5-4219adfa593f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209305119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.4209305119
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.202652785
Short name T394
Test name
Test status
Simulation time 78893208 ps
CPU time 3.51 seconds
Started Jul 22 07:23:32 PM PDT 24
Finished Jul 22 07:23:54 PM PDT 24
Peak memory 217824 kb
Host smart-89d95436-4bcb-45ce-81b0-5e2241f11df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202652785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.202652785
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3832880562
Short name T199
Test name
Test status
Simulation time 1721481011 ps
CPU time 11.01 seconds
Started Jul 22 07:23:38 PM PDT 24
Finished Jul 22 07:24:10 PM PDT 24
Peak memory 225584 kb
Host smart-8099b5bf-6880-43eb-bfcf-6ac5ef6ab5ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832880562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3832880562
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.545527758
Short name T261
Test name
Test status
Simulation time 190150546 ps
CPU time 7.07 seconds
Started Jul 22 07:23:41 PM PDT 24
Finished Jul 22 07:24:11 PM PDT 24
Peak memory 217804 kb
Host smart-8dd43806-f05d-4c74-ac1e-0446c8c456e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545527758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.545527758
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1967128490
Short name T367
Test name
Test status
Simulation time 456256347 ps
CPU time 9.64 seconds
Started Jul 22 07:23:29 PM PDT 24
Finished Jul 22 07:23:56 PM PDT 24
Peak memory 217912 kb
Host smart-94077b0f-c27f-4978-85e5-8ec2781de690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967128490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1967128490
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2189152420
Short name T498
Test name
Test status
Simulation time 150443948 ps
CPU time 2.48 seconds
Started Jul 22 07:23:29 PM PDT 24
Finished Jul 22 07:23:49 PM PDT 24
Peak memory 217192 kb
Host smart-af0aa063-a8ec-4f14-a1cf-2db5737c73c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189152420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2189152420
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1946950867
Short name T450
Test name
Test status
Simulation time 711797312 ps
CPU time 32.55 seconds
Started Jul 22 07:23:28 PM PDT 24
Finished Jul 22 07:24:19 PM PDT 24
Peak memory 250612 kb
Host smart-647c5274-c854-4765-b874-841a56af597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946950867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1946950867
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4030722177
Short name T707
Test name
Test status
Simulation time 113146750 ps
CPU time 6.22 seconds
Started Jul 22 07:23:30 PM PDT 24
Finished Jul 22 07:23:54 PM PDT 24
Peak memory 246900 kb
Host smart-64a8a703-f309-4a98-9650-4152a1f27877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030722177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4030722177
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4070299771
Short name T454
Test name
Test status
Simulation time 4164172457 ps
CPU time 97.61 seconds
Started Jul 22 07:23:41 PM PDT 24
Finished Jul 22 07:25:42 PM PDT 24
Peak memory 267112 kb
Host smart-2de264d1-3130-40de-8444-8f49f7657d1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070299771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4070299771
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2651344971
Short name T438
Test name
Test status
Simulation time 18899356006 ps
CPU time 409.61 seconds
Started Jul 22 07:23:44 PM PDT 24
Finished Jul 22 07:30:57 PM PDT 24
Peak memory 283620 kb
Host smart-9a925825-ca3d-4166-bbc5-a90248a31683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2651344971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2651344971
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.399663006
Short name T273
Test name
Test status
Simulation time 40744567 ps
CPU time 0.99 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:53 PM PDT 24
Peak memory 211428 kb
Host smart-fc86cacf-700e-46b0-8834-be77e72097f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399663006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.399663006
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.298278676
Short name T155
Test name
Test status
Simulation time 139999611 ps
CPU time 0.96 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:45 PM PDT 24
Peak memory 208472 kb
Host smart-2d5ec65c-09c3-44a9-8f39-e94d6810a356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298278676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.298278676
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3427476733
Short name T452
Test name
Test status
Simulation time 12747345 ps
CPU time 0.87 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:24:57 PM PDT 24
Peak memory 207560 kb
Host smart-f4e11019-38fc-4394-ba05-2215da2d49e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427476733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3427476733
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1519376974
Short name T489
Test name
Test status
Simulation time 2589656012 ps
CPU time 13.17 seconds
Started Jul 22 07:20:51 PM PDT 24
Finished Jul 22 07:21:29 PM PDT 24
Peak memory 218560 kb
Host smart-4570581a-164b-4b10-9744-d02bcd97564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519376974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1519376974
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2026699866
Short name T555
Test name
Test status
Simulation time 6965035712 ps
CPU time 6.41 seconds
Started Jul 22 07:20:51 PM PDT 24
Finished Jul 22 07:21:21 PM PDT 24
Peak memory 217300 kb
Host smart-4de35636-2f65-424a-86d0-b4f1eeb1fc90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026699866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2026699866
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2590637802
Short name T476
Test name
Test status
Simulation time 1650630160 ps
CPU time 50.43 seconds
Started Jul 22 07:24:44 PM PDT 24
Finished Jul 22 07:26:33 PM PDT 24
Peak memory 217748 kb
Host smart-4109aa05-22d7-4fee-a039-b1464a9ca9c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590637802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2590637802
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.4008659682
Short name T690
Test name
Test status
Simulation time 1587060769 ps
CPU time 4.92 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:47 PM PDT 24
Peak memory 217312 kb
Host smart-a40db409-7c78-4837-81cf-dad60f157b28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008659682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.4
008659682
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1555932087
Short name T625
Test name
Test status
Simulation time 507917283 ps
CPU time 8.62 seconds
Started Jul 22 07:21:03 PM PDT 24
Finished Jul 22 07:21:50 PM PDT 24
Peak memory 217848 kb
Host smart-9885cb22-d675-4569-9699-b92c4de83d3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555932087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1555932087
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2520239721
Short name T218
Test name
Test status
Simulation time 1868530693 ps
CPU time 25.05 seconds
Started Jul 22 07:20:52 PM PDT 24
Finished Jul 22 07:21:41 PM PDT 24
Peak memory 217216 kb
Host smart-54556f02-5c58-48a3-80a3-0b722d1853ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520239721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2520239721
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.969957583
Short name T333
Test name
Test status
Simulation time 5828860595 ps
CPU time 9.78 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:24:02 PM PDT 24
Peak memory 217252 kb
Host smart-74b8eb1d-0176-430d-9d1a-763ea542d570
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969957583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.969957583
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1968996048
Short name T618
Test name
Test status
Simulation time 1214727911 ps
CPU time 60.93 seconds
Started Jul 22 07:20:51 PM PDT 24
Finished Jul 22 07:22:16 PM PDT 24
Peak memory 275176 kb
Host smart-4106e820-673d-41f7-bf53-ea9c22029070
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968996048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1968996048
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.177618485
Short name T293
Test name
Test status
Simulation time 3034085914 ps
CPU time 23.88 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:25:20 PM PDT 24
Peak memory 250604 kb
Host smart-458bdc98-f2d7-4b84-90d3-57160b5685d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177618485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.177618485
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3613976510
Short name T602
Test name
Test status
Simulation time 60327079 ps
CPU time 3.17 seconds
Started Jul 22 07:24:45 PM PDT 24
Finished Jul 22 07:25:48 PM PDT 24
Peak memory 217808 kb
Host smart-071339a5-98cb-4151-8440-02c61bcf9d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613976510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3613976510
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3509094170
Short name T59
Test name
Test status
Simulation time 264528854 ps
CPU time 12.01 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:54 PM PDT 24
Peak memory 217320 kb
Host smart-ab13b4b4-bdee-4446-84b9-4f502b679a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509094170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3509094170
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.4049792839
Short name T75
Test name
Test status
Simulation time 108798274 ps
CPU time 25.83 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:24:18 PM PDT 24
Peak memory 269500 kb
Host smart-85188266-c696-4818-8b54-3acd475dfb22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049792839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.4049792839
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2468592418
Short name T559
Test name
Test status
Simulation time 255308770 ps
CPU time 10.41 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:25:07 PM PDT 24
Peak memory 217904 kb
Host smart-9008f5e7-92bb-4259-8904-95435c155d60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468592418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2468592418
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2772782997
Short name T82
Test name
Test status
Simulation time 713119406 ps
CPU time 13.73 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:56 PM PDT 24
Peak memory 225612 kb
Host smart-79191a81-64db-46d7-ade8-d54bd543ce8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772782997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2772782997
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.602326381
Short name T849
Test name
Test status
Simulation time 205589669 ps
CPU time 6.48 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:58 PM PDT 24
Peak memory 225324 kb
Host smart-5df2340c-943f-49db-bdd7-fcd92bd27344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602326381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.602326381
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3037202130
Short name T473
Test name
Test status
Simulation time 338078123 ps
CPU time 12.18 seconds
Started Jul 22 07:24:45 PM PDT 24
Finished Jul 22 07:25:55 PM PDT 24
Peak memory 217880 kb
Host smart-716a6e78-01a4-4f80-bbbd-59ea1430002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037202130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3037202130
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.517197864
Short name T551
Test name
Test status
Simulation time 67980309 ps
CPU time 2.57 seconds
Started Jul 22 07:24:45 PM PDT 24
Finished Jul 22 07:25:46 PM PDT 24
Peak memory 213868 kb
Host smart-c6c51240-ea4f-4dcd-b127-e0c553b5294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517197864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.517197864
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3384399044
Short name T284
Test name
Test status
Simulation time 217444505 ps
CPU time 20.38 seconds
Started Jul 22 07:20:48 PM PDT 24
Finished Jul 22 07:21:30 PM PDT 24
Peak memory 250556 kb
Host smart-74d58d6a-1908-4b85-9552-b7b37fdcfe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384399044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3384399044
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1687108384
Short name T391
Test name
Test status
Simulation time 356660748 ps
CPU time 6.71 seconds
Started Jul 22 07:24:45 PM PDT 24
Finished Jul 22 07:25:50 PM PDT 24
Peak memory 250112 kb
Host smart-0ebeec08-8086-40db-8e5c-255c48a691e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687108384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1687108384
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3388397354
Short name T24
Test name
Test status
Simulation time 2610451496 ps
CPU time 64.27 seconds
Started Jul 22 07:21:03 PM PDT 24
Finished Jul 22 07:22:44 PM PDT 24
Peak memory 281416 kb
Host smart-13789cc7-13f4-4544-97b2-2e39f5e15ed5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388397354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3388397354
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.4163460223
Short name T96
Test name
Test status
Simulation time 269539947639 ps
CPU time 1172.09 seconds
Started Jul 22 07:21:05 PM PDT 24
Finished Jul 22 07:41:16 PM PDT 24
Peak memory 283548 kb
Host smart-337096db-9089-4103-b9c7-86d1e9c6544b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4163460223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.4163460223
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.689864127
Short name T866
Test name
Test status
Simulation time 43511490 ps
CPU time 0.95 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:53 PM PDT 24
Peak memory 212540 kb
Host smart-07742c02-91bc-40ef-9685-c5c03c6c0ffa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689864127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.689864127
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2019197758
Short name T588
Test name
Test status
Simulation time 16668515 ps
CPU time 0.87 seconds
Started Jul 22 07:23:40 PM PDT 24
Finished Jul 22 07:24:03 PM PDT 24
Peak memory 208392 kb
Host smart-f3a44479-b83f-4357-9370-357fa7f8994d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019197758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2019197758
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3760654533
Short name T544
Test name
Test status
Simulation time 600708133 ps
CPU time 9.72 seconds
Started Jul 22 07:23:40 PM PDT 24
Finished Jul 22 07:24:12 PM PDT 24
Peak memory 225700 kb
Host smart-a333f799-84a6-4fbb-a918-e116c67cc2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760654533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3760654533
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2764550098
Short name T8
Test name
Test status
Simulation time 148136109 ps
CPU time 2.36 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:24:03 PM PDT 24
Peak memory 217236 kb
Host smart-a4013195-f875-4bc8-88b6-28b7631c4cfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764550098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2764550098
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3963683068
Short name T595
Test name
Test status
Simulation time 75185819 ps
CPU time 3.68 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:24:03 PM PDT 24
Peak memory 217852 kb
Host smart-68e73cb8-e233-475f-8528-19faf8800121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963683068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3963683068
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1384896061
Short name T458
Test name
Test status
Simulation time 387836303 ps
CPU time 13.6 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:24:14 PM PDT 24
Peak memory 225652 kb
Host smart-b2824a89-8467-4ead-86cb-a23135c22c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384896061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1384896061
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.541289250
Short name T288
Test name
Test status
Simulation time 1625500150 ps
CPU time 10.93 seconds
Started Jul 22 07:23:43 PM PDT 24
Finished Jul 22 07:24:17 PM PDT 24
Peak memory 225628 kb
Host smart-70c10af7-552b-4b0d-ae8c-204638b8e7ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541289250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.541289250
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3790765058
Short name T262
Test name
Test status
Simulation time 1333572276 ps
CPU time 9.11 seconds
Started Jul 22 07:23:40 PM PDT 24
Finished Jul 22 07:24:12 PM PDT 24
Peak memory 225584 kb
Host smart-ece1bbc0-5bf0-4f57-85ab-f54ec05c4227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790765058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3790765058
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2804685911
Short name T852
Test name
Test status
Simulation time 1054929524 ps
CPU time 8.01 seconds
Started Jul 22 07:23:42 PM PDT 24
Finished Jul 22 07:24:13 PM PDT 24
Peak memory 217848 kb
Host smart-0ae2df25-260a-4e88-9d8b-3f376ec0192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804685911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2804685911
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1741041953
Short name T744
Test name
Test status
Simulation time 343833562 ps
CPU time 2.74 seconds
Started Jul 22 07:23:40 PM PDT 24
Finished Jul 22 07:24:06 PM PDT 24
Peak memory 214384 kb
Host smart-44b6fb0b-bd9a-4d10-86e1-dedeb8c25b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741041953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1741041953
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3722732119
Short name T854
Test name
Test status
Simulation time 1711669677 ps
CPU time 28.33 seconds
Started Jul 22 07:23:37 PM PDT 24
Finished Jul 22 07:24:26 PM PDT 24
Peak memory 250600 kb
Host smart-6f03a22b-5d91-4a95-9fa2-2caa0496713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722732119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3722732119
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2925775001
Short name T691
Test name
Test status
Simulation time 173242821 ps
CPU time 2.98 seconds
Started Jul 22 07:23:38 PM PDT 24
Finished Jul 22 07:24:02 PM PDT 24
Peak memory 226088 kb
Host smart-f6eae787-1a0e-4930-91cd-bc222ee8e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925775001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2925775001
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3241360093
Short name T518
Test name
Test status
Simulation time 4839524065 ps
CPU time 157.86 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:26:38 PM PDT 24
Peak memory 420816 kb
Host smart-2828d231-d7ea-4dd5-b75d-42f018f26c80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241360093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3241360093
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2656787495
Short name T733
Test name
Test status
Simulation time 18912555 ps
CPU time 0.93 seconds
Started Jul 22 07:23:41 PM PDT 24
Finished Jul 22 07:24:06 PM PDT 24
Peak memory 211456 kb
Host smart-9a0fc4ad-e54c-494c-becb-6325c5c623f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656787495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2656787495
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3318102211
Short name T819
Test name
Test status
Simulation time 83617761 ps
CPU time 1.04 seconds
Started Jul 22 07:23:47 PM PDT 24
Finished Jul 22 07:24:13 PM PDT 24
Peak memory 208620 kb
Host smart-b3ef48fe-9a1d-4632-952f-a3cb1480de59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318102211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3318102211
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4272793689
Short name T545
Test name
Test status
Simulation time 1298838332 ps
CPU time 12.06 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:24:12 PM PDT 24
Peak memory 217764 kb
Host smart-247f91c4-9b18-4434-8f8f-31654e885c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272793689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4272793689
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2482291143
Short name T33
Test name
Test status
Simulation time 2739826081 ps
CPU time 3.08 seconds
Started Jul 22 07:23:47 PM PDT 24
Finished Jul 22 07:24:14 PM PDT 24
Peak memory 216848 kb
Host smart-088894c6-1594-4efc-b564-8f9b17cb9f1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482291143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2482291143
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1683348839
Short name T242
Test name
Test status
Simulation time 223011323 ps
CPU time 3.69 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:24:03 PM PDT 24
Peak memory 217972 kb
Host smart-fd29c8d5-f3d2-4639-8571-1db88647034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683348839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1683348839
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.488284910
Short name T224
Test name
Test status
Simulation time 1106395693 ps
CPU time 10.91 seconds
Started Jul 22 07:23:48 PM PDT 24
Finished Jul 22 07:24:25 PM PDT 24
Peak memory 217820 kb
Host smart-6ea519bc-0e51-4b27-9ecf-18311901dd61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488284910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.488284910
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1329409373
Short name T291
Test name
Test status
Simulation time 602694754 ps
CPU time 14.31 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:24:29 PM PDT 24
Peak memory 225544 kb
Host smart-e2237801-04be-437c-97aa-ec711bb6b24f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329409373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1329409373
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3276949562
Short name T826
Test name
Test status
Simulation time 823511365 ps
CPU time 7.42 seconds
Started Jul 22 07:23:48 PM PDT 24
Finished Jul 22 07:24:21 PM PDT 24
Peak memory 217800 kb
Host smart-a35b8e69-aa36-4787-84e1-f0796a5ba878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276949562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3276949562
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3255208440
Short name T694
Test name
Test status
Simulation time 1206675654 ps
CPU time 7.73 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:24:08 PM PDT 24
Peak memory 218024 kb
Host smart-2cce0ab1-c7c0-42b1-b56c-be8cf5f63dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255208440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3255208440
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1040235516
Short name T57
Test name
Test status
Simulation time 40869715 ps
CPU time 2.95 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:24:04 PM PDT 24
Peak memory 214628 kb
Host smart-539a0381-2b71-47d3-a7bd-a4900bf5bcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040235516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1040235516
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2494689898
Short name T48
Test name
Test status
Simulation time 1060751677 ps
CPU time 24.48 seconds
Started Jul 22 07:23:39 PM PDT 24
Finished Jul 22 07:24:24 PM PDT 24
Peak memory 250608 kb
Host smart-06f762ed-d258-4ce4-90ce-b2d06ba0aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494689898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2494689898
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.649238132
Short name T465
Test name
Test status
Simulation time 497534639 ps
CPU time 6.91 seconds
Started Jul 22 07:23:41 PM PDT 24
Finished Jul 22 07:24:10 PM PDT 24
Peak memory 246980 kb
Host smart-7cbefd1c-c207-42fd-924e-eaef04321ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649238132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.649238132
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.959258821
Short name T487
Test name
Test status
Simulation time 3180807867 ps
CPU time 80.7 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:25:36 PM PDT 24
Peak memory 267060 kb
Host smart-b9fb81c0-a4ae-4eea-b4a4-2db36508c478
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959258821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.959258821
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.841014182
Short name T477
Test name
Test status
Simulation time 16414535 ps
CPU time 0.87 seconds
Started Jul 22 07:23:41 PM PDT 24
Finished Jul 22 07:24:06 PM PDT 24
Peak memory 211508 kb
Host smart-2b442217-d2b6-4778-b54e-d956a284d985
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841014182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.841014182
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.85817792
Short name T396
Test name
Test status
Simulation time 17354638 ps
CPU time 0.95 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:36 PM PDT 24
Peak memory 208408 kb
Host smart-6245f7db-31e3-45c1-8377-c46361690337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85817792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.85817792
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1469938481
Short name T405
Test name
Test status
Simulation time 1465400634 ps
CPU time 17.02 seconds
Started Jul 22 07:23:47 PM PDT 24
Finished Jul 22 07:24:28 PM PDT 24
Peak memory 217756 kb
Host smart-a6fd362f-5a3c-43b0-84b6-86d60a230ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469938481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1469938481
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2246379892
Short name T154
Test name
Test status
Simulation time 524745854 ps
CPU time 5.71 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:24:20 PM PDT 24
Peak memory 217264 kb
Host smart-0baf93a7-3b9c-473a-83a4-c08af3281bd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246379892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2246379892
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2947850728
Short name T510
Test name
Test status
Simulation time 90400891 ps
CPU time 2.82 seconds
Started Jul 22 07:23:50 PM PDT 24
Finished Jul 22 07:24:19 PM PDT 24
Peak memory 217856 kb
Host smart-23aba403-8cd0-4d58-85b6-25bd0a08bd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947850728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2947850728
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2941244285
Short name T327
Test name
Test status
Simulation time 1531498908 ps
CPU time 22.04 seconds
Started Jul 22 07:23:48 PM PDT 24
Finished Jul 22 07:24:36 PM PDT 24
Peak memory 218052 kb
Host smart-559cacab-7a26-4f68-a18b-16ebaec8fa7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941244285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2941244285
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.395296285
Short name T646
Test name
Test status
Simulation time 783719719 ps
CPU time 14.85 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:24:29 PM PDT 24
Peak memory 225600 kb
Host smart-e45734ce-3b1b-4143-8cce-d888d8d87fdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395296285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.395296285
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.704809096
Short name T672
Test name
Test status
Simulation time 612055190 ps
CPU time 8.23 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:24:24 PM PDT 24
Peak memory 225700 kb
Host smart-ccc7ad03-119f-4c29-90db-8b3c78fec455
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704809096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.704809096
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1144328827
Short name T727
Test name
Test status
Simulation time 764087289 ps
CPU time 8.92 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:24:24 PM PDT 24
Peak memory 217928 kb
Host smart-b571d7dc-1670-4b03-a2bc-652054e65854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144328827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1144328827
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.175177689
Short name T703
Test name
Test status
Simulation time 169075698 ps
CPU time 8.13 seconds
Started Jul 22 07:23:50 PM PDT 24
Finished Jul 22 07:24:24 PM PDT 24
Peak memory 217248 kb
Host smart-cf84e9ed-01e8-406f-b0e3-6a2c1343e0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175177689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.175177689
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1490626975
Short name T256
Test name
Test status
Simulation time 1500644377 ps
CPU time 18.8 seconds
Started Jul 22 07:23:50 PM PDT 24
Finished Jul 22 07:24:35 PM PDT 24
Peak memory 250608 kb
Host smart-8b64001e-850d-4cc4-8ff8-aa5822444f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490626975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1490626975
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4284700698
Short name T328
Test name
Test status
Simulation time 59888420 ps
CPU time 7.72 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:24:22 PM PDT 24
Peak memory 243580 kb
Host smart-b1f1b8b9-e7d8-4cf4-9efc-c90d8bff0a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284700698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4284700698
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1566488054
Short name T436
Test name
Test status
Simulation time 8872005226 ps
CPU time 115.24 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:26:11 PM PDT 24
Peak memory 267808 kb
Host smart-3c83840c-697d-4a9b-8241-c659ad7b6181
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566488054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1566488054
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2635357800
Short name T486
Test name
Test status
Simulation time 83882775430 ps
CPU time 581.52 seconds
Started Jul 22 07:23:49 PM PDT 24
Finished Jul 22 07:33:56 PM PDT 24
Peak memory 308384 kb
Host smart-e0c5754a-bcbb-4245-9ee6-fce4c0cb1261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2635357800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2635357800
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2723285483
Short name T12
Test name
Test status
Simulation time 22902378 ps
CPU time 0.9 seconds
Started Jul 22 07:23:46 PM PDT 24
Finished Jul 22 07:24:11 PM PDT 24
Peak memory 211564 kb
Host smart-4e279af7-0f7c-479d-a125-b8198eb54180
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723285483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2723285483
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2209325620
Short name T771
Test name
Test status
Simulation time 80227317 ps
CPU time 1.02 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:36 PM PDT 24
Peak memory 208480 kb
Host smart-671cf0ef-1397-4a73-9e48-661081d95729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209325620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2209325620
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2501108352
Short name T257
Test name
Test status
Simulation time 446722888 ps
CPU time 12.73 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:24:45 PM PDT 24
Peak memory 217844 kb
Host smart-ae97fba6-7a78-4f1f-b257-b7e0b9597e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501108352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2501108352
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2862302434
Short name T762
Test name
Test status
Simulation time 5195414128 ps
CPU time 8.94 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:45 PM PDT 24
Peak memory 217356 kb
Host smart-42f087ae-45de-4147-aaac-181d4254aa73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862302434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2862302434
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.854270053
Short name T446
Test name
Test status
Simulation time 291393450 ps
CPU time 2.52 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:24:35 PM PDT 24
Peak memory 222004 kb
Host smart-3f24426b-5f67-4f72-a689-39a89ff9d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854270053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.854270053
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2141465239
Short name T838
Test name
Test status
Simulation time 1347639684 ps
CPU time 13.36 seconds
Started Jul 22 07:25:01 PM PDT 24
Finished Jul 22 07:26:23 PM PDT 24
Peak memory 225600 kb
Host smart-8b95ce91-8620-41ed-a67b-4c13092b8c19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141465239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2141465239
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3410297730
Short name T615
Test name
Test status
Simulation time 581732390 ps
CPU time 12.72 seconds
Started Jul 22 07:24:04 PM PDT 24
Finished Jul 22 07:24:50 PM PDT 24
Peak memory 225760 kb
Host smart-ce40b8ac-cb2a-45d1-85f3-0c1ab0afbb6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410297730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3410297730
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2591133147
Short name T162
Test name
Test status
Simulation time 644964638 ps
CPU time 12.81 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:49 PM PDT 24
Peak memory 217808 kb
Host smart-dadd49b5-9264-458b-9cf1-aa66c0a80dc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591133147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2591133147
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2465292509
Short name T839
Test name
Test status
Simulation time 663891589 ps
CPU time 13.11 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:24:47 PM PDT 24
Peak memory 217956 kb
Host smart-1acf1124-c3ce-4303-988a-bf3ed5be6d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465292509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2465292509
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2139312136
Short name T824
Test name
Test status
Simulation time 29971828 ps
CPU time 1.86 seconds
Started Jul 22 07:24:02 PM PDT 24
Finished Jul 22 07:24:36 PM PDT 24
Peak memory 217268 kb
Host smart-e31beee1-d6f1-4e60-99f7-6cace173b905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139312136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2139312136
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4117395248
Short name T359
Test name
Test status
Simulation time 752472587 ps
CPU time 36.64 seconds
Started Jul 22 07:24:00 PM PDT 24
Finished Jul 22 07:25:08 PM PDT 24
Peak memory 250528 kb
Host smart-182a9434-067c-4f6c-bbe5-090a26552a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117395248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4117395248
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.161694401
Short name T463
Test name
Test status
Simulation time 103946344 ps
CPU time 7 seconds
Started Jul 22 07:24:02 PM PDT 24
Finished Jul 22 07:24:41 PM PDT 24
Peak memory 250536 kb
Host smart-bf8e393f-b0a3-4046-86a5-a95622b12838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161694401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.161694401
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.498247555
Short name T590
Test name
Test status
Simulation time 10439360186 ps
CPU time 85.13 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:25:59 PM PDT 24
Peak memory 262976 kb
Host smart-780980c1-5487-4496-aba4-81cab5077a97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498247555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.498247555
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3025339618
Short name T287
Test name
Test status
Simulation time 106169313 ps
CPU time 1.18 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:24:34 PM PDT 24
Peak memory 212644 kb
Host smart-fcf4a678-d412-4c49-bd0c-03d7b420922a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025339618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3025339618
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3494131780
Short name T567
Test name
Test status
Simulation time 16950571 ps
CPU time 0.98 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:24:33 PM PDT 24
Peak memory 208464 kb
Host smart-9b243407-0bdc-408d-a00a-c6d2e78fe1a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494131780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3494131780
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2697618750
Short name T799
Test name
Test status
Simulation time 1741859075 ps
CPU time 13.88 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:49 PM PDT 24
Peak memory 217940 kb
Host smart-b2e90a96-a3c3-47e3-b1e0-67b2ad470357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697618750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2697618750
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2562416640
Short name T869
Test name
Test status
Simulation time 391425478 ps
CPU time 3.26 seconds
Started Jul 22 07:24:05 PM PDT 24
Finished Jul 22 07:24:41 PM PDT 24
Peak memory 217272 kb
Host smart-ffc0826c-a6d3-429d-882c-9d996ee9b4f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562416640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2562416640
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.628530162
Short name T639
Test name
Test status
Simulation time 60954710 ps
CPU time 2.53 seconds
Started Jul 22 07:25:01 PM PDT 24
Finished Jul 22 07:26:12 PM PDT 24
Peak memory 217868 kb
Host smart-fb5510d5-763b-4b29-928c-3116a853387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628530162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.628530162
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2024333372
Short name T843
Test name
Test status
Simulation time 406117377 ps
CPU time 11.9 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:47 PM PDT 24
Peak memory 218500 kb
Host smart-56f85d03-d57d-466a-9942-c55e1ebe88e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024333372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2024333372
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2334463054
Short name T266
Test name
Test status
Simulation time 2044167976 ps
CPU time 11.95 seconds
Started Jul 22 07:24:02 PM PDT 24
Finished Jul 22 07:24:46 PM PDT 24
Peak memory 225648 kb
Host smart-5507720e-0faa-4904-b13e-435ccf2db625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334463054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2334463054
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1470216310
Short name T39
Test name
Test status
Simulation time 208648873 ps
CPU time 6.61 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:24:40 PM PDT 24
Peak memory 217788 kb
Host smart-3a8fd33a-6f9d-4b63-94a4-4e5ec9886510
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470216310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1470216310
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.621303962
Short name T143
Test name
Test status
Simulation time 357913640 ps
CPU time 9.67 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:24:43 PM PDT 24
Peak memory 217916 kb
Host smart-f71114b9-726d-42dd-9dcf-283bf64d666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621303962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.621303962
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2410672306
Short name T554
Test name
Test status
Simulation time 72824533 ps
CPU time 2.69 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:24:36 PM PDT 24
Peak memory 214124 kb
Host smart-f1992834-0bcc-4766-8b88-612d63015693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410672306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2410672306
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2675295542
Short name T229
Test name
Test status
Simulation time 1003088005 ps
CPU time 17.86 seconds
Started Jul 22 07:24:02 PM PDT 24
Finished Jul 22 07:24:52 PM PDT 24
Peak memory 250584 kb
Host smart-7c927a28-fe78-4904-9244-98fb77929fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675295542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2675295542
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1658680533
Short name T749
Test name
Test status
Simulation time 62107180 ps
CPU time 7.22 seconds
Started Jul 22 07:24:00 PM PDT 24
Finished Jul 22 07:24:38 PM PDT 24
Peak memory 246476 kb
Host smart-0498df10-7796-4123-997a-105acdf193a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658680533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1658680533
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2143606212
Short name T560
Test name
Test status
Simulation time 15844425947 ps
CPU time 115.32 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:26:31 PM PDT 24
Peak memory 228168 kb
Host smart-98ea474b-8af8-4b5f-bd55-4b0ca67df49f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143606212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2143606212
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1404814504
Short name T263
Test name
Test status
Simulation time 22949547596 ps
CPU time 686.11 seconds
Started Jul 22 07:24:01 PM PDT 24
Finished Jul 22 07:35:59 PM PDT 24
Peak memory 283496 kb
Host smart-288dfffb-9c91-475c-8e75-5065d79d91d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1404814504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1404814504
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4047999687
Short name T542
Test name
Test status
Simulation time 21833558 ps
CPU time 0.87 seconds
Started Jul 22 07:24:04 PM PDT 24
Finished Jul 22 07:24:38 PM PDT 24
Peak memory 212528 kb
Host smart-bd6ee49a-e994-45dd-ac47-be2f85eba084
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047999687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.4047999687
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.320711996
Short name T750
Test name
Test status
Simulation time 19905524 ps
CPU time 1.22 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:24:54 PM PDT 24
Peak memory 208604 kb
Host smart-966b4c00-671c-411d-b9b3-aa3c4456018e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320711996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.320711996
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1347314716
Short name T457
Test name
Test status
Simulation time 1181498981 ps
CPU time 14.35 seconds
Started Jul 22 07:24:02 PM PDT 24
Finished Jul 22 07:24:49 PM PDT 24
Peak memory 217852 kb
Host smart-1658b4b6-6a90-4f91-94e2-6653803229cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347314716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1347314716
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2379974998
Short name T597
Test name
Test status
Simulation time 54385572 ps
CPU time 1.49 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:38 PM PDT 24
Peak memory 217276 kb
Host smart-a7015bde-fa36-44d3-96df-53d42fa29fff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379974998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2379974998
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1900914595
Short name T40
Test name
Test status
Simulation time 34442232 ps
CPU time 1.99 seconds
Started Jul 22 07:24:04 PM PDT 24
Finished Jul 22 07:24:40 PM PDT 24
Peak memory 217868 kb
Host smart-cdc08933-c404-4822-8a1f-649f4b4fc3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900914595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1900914595
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2202495722
Short name T753
Test name
Test status
Simulation time 811525715 ps
CPU time 20.22 seconds
Started Jul 22 07:24:00 PM PDT 24
Finished Jul 22 07:24:51 PM PDT 24
Peak memory 225604 kb
Host smart-7c1c0ef4-24a8-4537-ba2a-3e6a86f7fd34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202495722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2202495722
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1911095479
Short name T853
Test name
Test status
Simulation time 955595368 ps
CPU time 13.18 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:25:05 PM PDT 24
Peak memory 225524 kb
Host smart-ee2ed867-030b-4f7f-bea3-c1701d2d4152
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911095479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1911095479
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3512409543
Short name T55
Test name
Test status
Simulation time 365689271 ps
CPU time 8.94 seconds
Started Jul 22 07:24:15 PM PDT 24
Finished Jul 22 07:25:07 PM PDT 24
Peak memory 225584 kb
Host smart-83d40d5e-bc38-4510-800a-e434a060bbad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512409543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3512409543
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4207201378
Short name T606
Test name
Test status
Simulation time 287114935 ps
CPU time 10.44 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:46 PM PDT 24
Peak memory 218104 kb
Host smart-59d44557-f679-41d4-9b24-eaf48b865fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207201378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4207201378
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3982156083
Short name T708
Test name
Test status
Simulation time 158781271 ps
CPU time 2.11 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:38 PM PDT 24
Peak memory 213812 kb
Host smart-fcd62982-b4b1-4560-8fc6-938331da1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982156083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3982156083
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3919223744
Short name T806
Test name
Test status
Simulation time 1877941055 ps
CPU time 33.03 seconds
Started Jul 22 07:24:00 PM PDT 24
Finished Jul 22 07:25:04 PM PDT 24
Peak memory 250608 kb
Host smart-d6588477-2406-4fd9-8dbc-a7ef199a1256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919223744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3919223744
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3633092679
Short name T314
Test name
Test status
Simulation time 88390196 ps
CPU time 8.35 seconds
Started Jul 22 07:24:03 PM PDT 24
Finished Jul 22 07:24:45 PM PDT 24
Peak memory 250600 kb
Host smart-01d6c5c9-3439-448f-a898-eb9fa1533b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633092679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3633092679
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.396105818
Short name T374
Test name
Test status
Simulation time 11829297911 ps
CPU time 83.76 seconds
Started Jul 22 07:24:12 PM PDT 24
Finished Jul 22 07:26:17 PM PDT 24
Peak memory 219408 kb
Host smart-bf647262-94c4-451d-af1a-81f6a09f6792
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396105818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.396105818
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2845441201
Short name T140
Test name
Test status
Simulation time 7163922713 ps
CPU time 166.6 seconds
Started Jul 22 07:24:18 PM PDT 24
Finished Jul 22 07:27:52 PM PDT 24
Peak memory 283184 kb
Host smart-abb0c12b-6602-49a5-b7b8-3c73716304f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2845441201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.2845441201
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1514911810
Short name T776
Test name
Test status
Simulation time 13740609 ps
CPU time 1.08 seconds
Started Jul 22 07:24:16 PM PDT 24
Finished Jul 22 07:25:00 PM PDT 24
Peak memory 211472 kb
Host smart-ef947c33-95e4-45de-913f-ca80bcd2d4fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514911810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1514911810
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1587167267
Short name T319
Test name
Test status
Simulation time 25769063 ps
CPU time 0.94 seconds
Started Jul 22 07:24:12 PM PDT 24
Finished Jul 22 07:24:55 PM PDT 24
Peak memory 208460 kb
Host smart-cd4aebbc-47e8-4d92-9188-84ddba6e2fd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587167267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1587167267
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3347380826
Short name T681
Test name
Test status
Simulation time 268994939 ps
CPU time 9.35 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:25:02 PM PDT 24
Peak memory 217832 kb
Host smart-357528d3-fc03-4f0e-8d62-f56fc6b114ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347380826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3347380826
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1785122028
Short name T783
Test name
Test status
Simulation time 556297059 ps
CPU time 2.52 seconds
Started Jul 22 07:24:15 PM PDT 24
Finished Jul 22 07:25:00 PM PDT 24
Peak memory 217264 kb
Host smart-3609ba56-01b0-432d-8e2f-ed659df4e588
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785122028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1785122028
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1928751002
Short name T576
Test name
Test status
Simulation time 101181453 ps
CPU time 3.32 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:24:56 PM PDT 24
Peak memory 217916 kb
Host smart-1472fea8-9b63-4e1b-b2c9-f10df6f8eb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928751002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1928751002
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3716843976
Short name T768
Test name
Test status
Simulation time 2526945395 ps
CPU time 13.3 seconds
Started Jul 22 07:24:13 PM PDT 24
Finished Jul 22 07:25:09 PM PDT 24
Peak memory 225572 kb
Host smart-b90355d9-3ece-4252-aae6-ab97e21ca476
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716843976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3716843976
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2266408889
Short name T86
Test name
Test status
Simulation time 594468546 ps
CPU time 10.96 seconds
Started Jul 22 07:24:18 PM PDT 24
Finished Jul 22 07:25:16 PM PDT 24
Peak memory 225580 kb
Host smart-82308d3e-4bfd-40ca-84d6-b8f72758cab1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266408889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2266408889
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3862683473
Short name T830
Test name
Test status
Simulation time 1915611058 ps
CPU time 15.33 seconds
Started Jul 22 07:24:10 PM PDT 24
Finished Jul 22 07:25:06 PM PDT 24
Peak memory 225648 kb
Host smart-1aaeb090-573c-4068-9664-f4aca93ff687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862683473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3862683473
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3413368816
Short name T62
Test name
Test status
Simulation time 703430234 ps
CPU time 2.5 seconds
Started Jul 22 07:24:13 PM PDT 24
Finished Jul 22 07:24:57 PM PDT 24
Peak memory 217404 kb
Host smart-de80f9bc-4ec9-4174-97f4-bc10b93f026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413368816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3413368816
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2780221780
Short name T466
Test name
Test status
Simulation time 1180142633 ps
CPU time 25.42 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:25:22 PM PDT 24
Peak memory 250596 kb
Host smart-364e0fd5-2b53-4ed5-96e4-625d1edee8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780221780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2780221780
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3217839483
Short name T548
Test name
Test status
Simulation time 148329880 ps
CPU time 8.61 seconds
Started Jul 22 07:25:14 PM PDT 24
Finished Jul 22 07:26:39 PM PDT 24
Peak memory 250668 kb
Host smart-7e75132c-a784-403e-9e96-6cf33575eca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217839483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3217839483
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3913543895
Short name T205
Test name
Test status
Simulation time 97440576461 ps
CPU time 537.93 seconds
Started Jul 22 07:24:13 PM PDT 24
Finished Jul 22 07:33:53 PM PDT 24
Peak memory 270812 kb
Host smart-7c2a1592-f235-4a00-a734-02c42a789365
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913543895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3913543895
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2544253888
Short name T45
Test name
Test status
Simulation time 17212280498 ps
CPU time 309.53 seconds
Started Jul 22 07:24:12 PM PDT 24
Finished Jul 22 07:30:04 PM PDT 24
Peak memory 283548 kb
Host smart-ef833266-a650-4989-9d53-7a50e26b92d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2544253888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2544253888
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2800581392
Short name T605
Test name
Test status
Simulation time 11766945 ps
CPU time 0.85 seconds
Started Jul 22 07:24:16 PM PDT 24
Finished Jul 22 07:25:00 PM PDT 24
Peak memory 211572 kb
Host smart-da04ad47-6acf-4f04-8528-1a2a69231308
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800581392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2800581392
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3999249224
Short name T702
Test name
Test status
Simulation time 20243212 ps
CPU time 0.78 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:24:52 PM PDT 24
Peak memory 208296 kb
Host smart-76476f31-8f9f-45a0-b7b9-6ceef98693a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999249224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3999249224
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.406871731
Short name T556
Test name
Test status
Simulation time 1170727352 ps
CPU time 12.82 seconds
Started Jul 22 07:24:16 PM PDT 24
Finished Jul 22 07:25:13 PM PDT 24
Peak memory 217908 kb
Host smart-f5a6586c-0a07-4db1-a361-601f4a15fc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406871731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.406871731
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.885078612
Short name T265
Test name
Test status
Simulation time 407050199 ps
CPU time 4.51 seconds
Started Jul 22 07:24:12 PM PDT 24
Finished Jul 22 07:24:59 PM PDT 24
Peak memory 217256 kb
Host smart-ecd33b25-2cb8-467c-8d0d-1f4c23d924d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885078612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.885078612
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1647339192
Short name T308
Test name
Test status
Simulation time 147730490 ps
CPU time 2.15 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:24:55 PM PDT 24
Peak memory 221908 kb
Host smart-cc31d625-20a3-4dbb-a20f-7c2aa477a329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647339192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1647339192
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.4199401870
Short name T714
Test name
Test status
Simulation time 864506443 ps
CPU time 24.05 seconds
Started Jul 22 07:24:13 PM PDT 24
Finished Jul 22 07:25:20 PM PDT 24
Peak memory 225584 kb
Host smart-078419f3-708f-488e-9b5a-1af9739a57a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199401870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.4199401870
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3176683383
Short name T796
Test name
Test status
Simulation time 2688211613 ps
CPU time 9.14 seconds
Started Jul 22 07:24:13 PM PDT 24
Finished Jul 22 07:25:04 PM PDT 24
Peak memory 225616 kb
Host smart-6c47fd39-9447-40ae-97ea-4f62190370b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176683383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3176683383
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1023655378
Short name T766
Test name
Test status
Simulation time 243394236 ps
CPU time 8.22 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:25:01 PM PDT 24
Peak memory 217804 kb
Host smart-66e15bf9-ba7a-4ea2-9624-ebb18c59f7a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023655378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1023655378
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4254090413
Short name T599
Test name
Test status
Simulation time 247392760 ps
CPU time 8.88 seconds
Started Jul 22 07:24:16 PM PDT 24
Finished Jul 22 07:25:08 PM PDT 24
Peak memory 217992 kb
Host smart-eb925c74-c591-4577-8c81-c04da996ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254090413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4254090413
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.542834440
Short name T61
Test name
Test status
Simulation time 98114648 ps
CPU time 2.58 seconds
Started Jul 22 07:24:10 PM PDT 24
Finished Jul 22 07:24:52 PM PDT 24
Peak memory 217256 kb
Host smart-e1754241-9018-47fb-bca6-367b4ff9c0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542834440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.542834440
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2724090524
Short name T268
Test name
Test status
Simulation time 374171837 ps
CPU time 32.92 seconds
Started Jul 22 07:24:16 PM PDT 24
Finished Jul 22 07:25:32 PM PDT 24
Peak memory 250636 kb
Host smart-73da52cb-460d-410d-8479-424cc48a0314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724090524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2724090524
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1982851931
Short name T88
Test name
Test status
Simulation time 51118882 ps
CPU time 3.28 seconds
Started Jul 22 07:24:13 PM PDT 24
Finished Jul 22 07:24:59 PM PDT 24
Peak memory 222432 kb
Host smart-126e1c81-4d75-403a-9bc5-5417f04f6773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982851931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1982851931
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2043817112
Short name T215
Test name
Test status
Simulation time 84471305145 ps
CPU time 338.63 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:30:31 PM PDT 24
Peak memory 267040 kb
Host smart-9eb6a9be-f0bc-4a37-8c6a-1ada1b145806
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043817112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2043817112
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3804422224
Short name T664
Test name
Test status
Simulation time 13731156 ps
CPU time 0.86 seconds
Started Jul 22 07:24:18 PM PDT 24
Finished Jul 22 07:25:05 PM PDT 24
Peak memory 211508 kb
Host smart-6b91db6c-52be-4668-8586-4e44b0f774cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804422224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3804422224
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2806853105
Short name T575
Test name
Test status
Simulation time 126609678 ps
CPU time 1.14 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:13 PM PDT 24
Peak memory 208512 kb
Host smart-884e722c-fcc2-48aa-9b27-ccbc0837953e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806853105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2806853105
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.224031621
Short name T636
Test name
Test status
Simulation time 458862276 ps
CPU time 13.66 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:25:10 PM PDT 24
Peak memory 217860 kb
Host smart-b8634dd0-1801-40b2-b5ca-1d7c0731ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224031621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.224031621
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1935195788
Short name T282
Test name
Test status
Simulation time 424247523 ps
CPU time 4.28 seconds
Started Jul 22 07:24:17 PM PDT 24
Finished Jul 22 07:25:08 PM PDT 24
Peak memory 217316 kb
Host smart-d82c9489-d3ce-4e93-8547-35cae2e38522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935195788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1935195788
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.613312929
Short name T87
Test name
Test status
Simulation time 165600944 ps
CPU time 2 seconds
Started Jul 22 07:24:12 PM PDT 24
Finished Jul 22 07:24:57 PM PDT 24
Peak memory 217832 kb
Host smart-38a2b702-b2fc-461b-bf17-3af1e106a5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613312929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.613312929
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2217041178
Short name T46
Test name
Test status
Simulation time 347014378 ps
CPU time 10.93 seconds
Started Jul 22 07:24:11 PM PDT 24
Finished Jul 22 07:25:03 PM PDT 24
Peak memory 225188 kb
Host smart-ecf43581-5528-4650-ba00-22c592b1b001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217041178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2217041178
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3541136158
Short name T216
Test name
Test status
Simulation time 374228624 ps
CPU time 10.15 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:22 PM PDT 24
Peak memory 225304 kb
Host smart-ad7f0225-9a5a-4037-a24d-0f112524a3c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541136158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3541136158
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.906317240
Short name T206
Test name
Test status
Simulation time 510686578 ps
CPU time 8.59 seconds
Started Jul 22 07:24:40 PM PDT 24
Finished Jul 22 07:25:43 PM PDT 24
Peak memory 217796 kb
Host smart-3e53bf8e-3695-4062-8bb5-17bc45bafd07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906317240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.906317240
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3722462890
Short name T16
Test name
Test status
Simulation time 69213954 ps
CPU time 4.11 seconds
Started Jul 22 07:24:12 PM PDT 24
Finished Jul 22 07:24:57 PM PDT 24
Peak memory 217260 kb
Host smart-a8341aea-dc04-47d9-8331-8d1d8ef0c8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722462890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3722462890
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2559854773
Short name T397
Test name
Test status
Simulation time 3858809027 ps
CPU time 25 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:25:21 PM PDT 24
Peak memory 250612 kb
Host smart-be500070-bb3b-45c9-87f5-24019afc2f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559854773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2559854773
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.653882902
Short name T649
Test name
Test status
Simulation time 219375492 ps
CPU time 2.64 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:24:58 PM PDT 24
Peak memory 226084 kb
Host smart-2f855527-51f1-4af7-93ea-03873b4a281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653882902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.653882902
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1321724154
Short name T231
Test name
Test status
Simulation time 20374654368 ps
CPU time 96.21 seconds
Started Jul 22 07:24:21 PM PDT 24
Finished Jul 22 07:26:46 PM PDT 24
Peak memory 252240 kb
Host smart-e02dc22e-cb35-42d2-a190-da0f7ae748ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321724154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1321724154
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1019537499
Short name T364
Test name
Test status
Simulation time 35456426 ps
CPU time 0.88 seconds
Started Jul 22 07:24:18 PM PDT 24
Finished Jul 22 07:25:06 PM PDT 24
Peak memory 211436 kb
Host smart-8b6bc116-fa37-4707-be0f-768fa42102b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019537499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1019537499
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.539145132
Short name T278
Test name
Test status
Simulation time 62752033 ps
CPU time 1.06 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:14 PM PDT 24
Peak memory 208516 kb
Host smart-020a1fea-6a19-4bba-a0c8-ccf526ef7607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539145132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.539145132
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1804678331
Short name T794
Test name
Test status
Simulation time 984344550 ps
CPU time 14.64 seconds
Started Jul 22 07:24:21 PM PDT 24
Finished Jul 22 07:25:25 PM PDT 24
Peak memory 217788 kb
Host smart-57387baa-c371-473e-9fe9-4d040b5f11f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804678331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1804678331
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3767602441
Short name T493
Test name
Test status
Simulation time 41774750 ps
CPU time 1.81 seconds
Started Jul 22 07:24:22 PM PDT 24
Finished Jul 22 07:25:13 PM PDT 24
Peak memory 216796 kb
Host smart-f0370522-112f-4e6b-a332-fdb48b981e55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767602441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3767602441
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1707678641
Short name T587
Test name
Test status
Simulation time 25136300 ps
CPU time 1.86 seconds
Started Jul 22 07:24:22 PM PDT 24
Finished Jul 22 07:25:14 PM PDT 24
Peak memory 221784 kb
Host smart-218e6371-edfa-4ba6-9ba8-1454a857bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707678641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1707678641
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2401815109
Short name T760
Test name
Test status
Simulation time 895975842 ps
CPU time 13.13 seconds
Started Jul 22 07:25:13 PM PDT 24
Finished Jul 22 07:26:43 PM PDT 24
Peak memory 219556 kb
Host smart-7b9cc7bd-fd59-4ac5-b1c9-e770535764ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401815109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2401815109
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3919125353
Short name T243
Test name
Test status
Simulation time 1447403639 ps
CPU time 16.91 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:29 PM PDT 24
Peak memory 225696 kb
Host smart-0c06456e-c44a-4d00-98f7-e34a8cdc9df9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919125353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3919125353
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.4216047825
Short name T742
Test name
Test status
Simulation time 3203433517 ps
CPU time 14.73 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:28 PM PDT 24
Peak memory 225668 kb
Host smart-f744e50c-ad33-4d68-b52d-4411ae215714
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216047825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
4216047825
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1989667012
Short name T810
Test name
Test status
Simulation time 1422145982 ps
CPU time 13.04 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:25 PM PDT 24
Peak memory 218036 kb
Host smart-aabb2cd9-67cf-4f05-9046-1bb30731e6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989667012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1989667012
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2847491831
Short name T499
Test name
Test status
Simulation time 50395208 ps
CPU time 3.34 seconds
Started Jul 22 07:24:24 PM PDT 24
Finished Jul 22 07:25:17 PM PDT 24
Peak memory 214128 kb
Host smart-b1e6dd04-3d4a-4415-a31a-2cf517c8626b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847491831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2847491831
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1393070464
Short name T433
Test name
Test status
Simulation time 727958717 ps
CPU time 16.2 seconds
Started Jul 22 07:24:21 PM PDT 24
Finished Jul 22 07:25:27 PM PDT 24
Peak memory 250640 kb
Host smart-eaaad4bf-893b-4df9-8d13-af76c5ee24df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393070464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1393070464
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.225664049
Short name T322
Test name
Test status
Simulation time 145550577 ps
CPU time 7.15 seconds
Started Jul 22 07:24:22 PM PDT 24
Finished Jul 22 07:25:19 PM PDT 24
Peak memory 250600 kb
Host smart-05a14977-b256-4c72-b923-df808a4beb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225664049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.225664049
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.209799667
Short name T687
Test name
Test status
Simulation time 2978983636 ps
CPU time 76.66 seconds
Started Jul 22 07:24:24 PM PDT 24
Finished Jul 22 07:26:30 PM PDT 24
Peak memory 281880 kb
Host smart-23ce2fc5-8e87-4918-8abf-f2be1f07ec61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209799667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.209799667
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.561828883
Short name T637
Test name
Test status
Simulation time 44409300 ps
CPU time 0.92 seconds
Started Jul 22 07:24:24 PM PDT 24
Finished Jul 22 07:25:14 PM PDT 24
Peak memory 211484 kb
Host smart-62424e80-b7ba-497e-a78d-1db0761d10d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561828883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.561828883
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.731835417
Short name T726
Test name
Test status
Simulation time 307265151 ps
CPU time 1 seconds
Started Jul 22 07:21:02 PM PDT 24
Finished Jul 22 07:21:39 PM PDT 24
Peak memory 208468 kb
Host smart-c8fc7677-0228-434a-888c-6b2ed49c8052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731835417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.731835417
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.337190718
Short name T846
Test name
Test status
Simulation time 24229499 ps
CPU time 0.8 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:44 PM PDT 24
Peak memory 208204 kb
Host smart-d33ab79e-a8d9-42f4-8e5b-b735208ea0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337190718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.337190718
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.4210162000
Short name T369
Test name
Test status
Simulation time 1201170044 ps
CPU time 13.06 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:55 PM PDT 24
Peak memory 217844 kb
Host smart-942da86f-1ea1-40e4-af6e-7f222f75ae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210162000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.4210162000
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3858933620
Short name T834
Test name
Test status
Simulation time 494311604 ps
CPU time 3.39 seconds
Started Jul 22 07:20:53 PM PDT 24
Finished Jul 22 07:21:22 PM PDT 24
Peak memory 216812 kb
Host smart-1685e325-c8da-4690-8c79-86480b2b05b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858933620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3858933620
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3073875845
Short name T654
Test name
Test status
Simulation time 8228122810 ps
CPU time 30.11 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:44 PM PDT 24
Peak memory 218476 kb
Host smart-a8b52c4d-1590-4d58-8236-b3d1e3a4fc90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073875845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3073875845
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2919321551
Short name T673
Test name
Test status
Simulation time 410958355 ps
CPU time 4.1 seconds
Started Jul 22 07:21:02 PM PDT 24
Finished Jul 22 07:21:42 PM PDT 24
Peak memory 217428 kb
Host smart-20c30cd6-9dd0-4ac1-8f28-aa14a42ba90e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919321551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
919321551
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2907687939
Short name T274
Test name
Test status
Simulation time 353511767 ps
CPU time 6.57 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:20 PM PDT 24
Peak memory 217780 kb
Host smart-14b38b06-7c95-464e-818c-fc958c71e8e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907687939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2907687939
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3565042093
Short name T286
Test name
Test status
Simulation time 985857637 ps
CPU time 26.98 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:41 PM PDT 24
Peak memory 217196 kb
Host smart-6cce6547-89b5-401e-98e6-f4fa3446036d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565042093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3565042093
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.837817590
Short name T751
Test name
Test status
Simulation time 238890485 ps
CPU time 3.84 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:18 PM PDT 24
Peak memory 217184 kb
Host smart-b4086de5-5fd6-437c-939f-df2fb64f36cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837817590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.837817590
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3313342946
Short name T401
Test name
Test status
Simulation time 5509323489 ps
CPU time 34.97 seconds
Started Jul 22 07:20:52 PM PDT 24
Finished Jul 22 07:21:52 PM PDT 24
Peak memory 267240 kb
Host smart-e875d393-3382-493b-b1ca-5b0b016e2f0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313342946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3313342946
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3922006820
Short name T237
Test name
Test status
Simulation time 405728567 ps
CPU time 13.11 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:27 PM PDT 24
Peak memory 222760 kb
Host smart-a0f3df8f-8364-4695-a1cf-adbdf558944c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922006820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3922006820
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.339166133
Short name T354
Test name
Test status
Simulation time 76406644 ps
CPU time 3.88 seconds
Started Jul 22 07:22:47 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 217824 kb
Host smart-1b5d130a-d8a9-4f42-9422-85e27dd5d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339166133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.339166133
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.4195486117
Short name T428
Test name
Test status
Simulation time 1380821559 ps
CPU time 14.2 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:28 PM PDT 24
Peak memory 217244 kb
Host smart-4e0af7c9-560b-468a-acbf-c94fdd7c5015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195486117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.4195486117
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3589029177
Short name T52
Test name
Test status
Simulation time 387180008 ps
CPU time 22.52 seconds
Started Jul 22 07:21:02 PM PDT 24
Finished Jul 22 07:22:00 PM PDT 24
Peak memory 281380 kb
Host smart-0056be45-baa7-42d7-8c5c-4d843b7beda6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589029177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3589029177
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2756860272
Short name T194
Test name
Test status
Simulation time 1282812112 ps
CPU time 10.83 seconds
Started Jul 22 07:22:48 PM PDT 24
Finished Jul 22 07:23:25 PM PDT 24
Peak memory 218476 kb
Host smart-51a78c34-3020-49c6-a728-57caf7de20f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756860272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2756860272
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3643674627
Short name T679
Test name
Test status
Simulation time 297716618 ps
CPU time 12.33 seconds
Started Jul 22 07:21:02 PM PDT 24
Finished Jul 22 07:21:50 PM PDT 24
Peak memory 217740 kb
Host smart-0570e00c-4358-49be-9bd5-20a83d7b5176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643674627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3643674627
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2423245131
Short name T195
Test name
Test status
Simulation time 420221083 ps
CPU time 8.39 seconds
Started Jul 22 07:21:05 PM PDT 24
Finished Jul 22 07:21:52 PM PDT 24
Peak memory 217804 kb
Host smart-723c9a91-1610-4c6d-8bc8-46959c9692b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423245131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
423245131
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2905348743
Short name T281
Test name
Test status
Simulation time 365947490 ps
CPU time 12.97 seconds
Started Jul 22 07:21:05 PM PDT 24
Finished Jul 22 07:21:57 PM PDT 24
Peak memory 217924 kb
Host smart-9d7bccb5-cce3-4dbd-a9c2-db761631ff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905348743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2905348743
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2150699613
Short name T379
Test name
Test status
Simulation time 56185273 ps
CPU time 1.08 seconds
Started Jul 22 07:20:55 PM PDT 24
Finished Jul 22 07:21:25 PM PDT 24
Peak memory 213404 kb
Host smart-76a95607-dff4-489c-90f0-7aa522414f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150699613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2150699613
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1393390204
Short name T626
Test name
Test status
Simulation time 2501470461 ps
CPU time 28.81 seconds
Started Jul 22 07:20:55 PM PDT 24
Finished Jul 22 07:21:52 PM PDT 24
Peak memory 250800 kb
Host smart-db7c5781-49a9-4eba-a9b9-36c51f2d36b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393390204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1393390204
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1374111647
Short name T671
Test name
Test status
Simulation time 57566695 ps
CPU time 3.57 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:46 PM PDT 24
Peak memory 217840 kb
Host smart-05866066-5170-4c63-9335-4b0a86bd5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374111647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1374111647
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1088379885
Short name T777
Test name
Test status
Simulation time 3585810812 ps
CPU time 60.51 seconds
Started Jul 22 07:21:02 PM PDT 24
Finished Jul 22 07:22:38 PM PDT 24
Peak memory 250664 kb
Host smart-b46f9cfe-e179-4783-9427-dd5d4fa484ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088379885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1088379885
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2900860834
Short name T677
Test name
Test status
Simulation time 19216337 ps
CPU time 0.83 seconds
Started Jul 22 07:20:54 PM PDT 24
Finished Jul 22 07:21:24 PM PDT 24
Peak memory 211628 kb
Host smart-ce48fc22-f6ec-46e5-9e54-ac4d43591837
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900860834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2900860834
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1212938808
Short name T399
Test name
Test status
Simulation time 80027056 ps
CPU time 0.88 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:30 PM PDT 24
Peak memory 208436 kb
Host smart-a32bccbe-7879-41f6-8fcf-f95a9d0fcdb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212938808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1212938808
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2509074283
Short name T592
Test name
Test status
Simulation time 243613600 ps
CPU time 11.65 seconds
Started Jul 22 07:24:25 PM PDT 24
Finished Jul 22 07:25:26 PM PDT 24
Peak memory 217852 kb
Host smart-fc7e8fad-0746-4f87-9943-a54fe83d9b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509074283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2509074283
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.974717911
Short name T511
Test name
Test status
Simulation time 828747421 ps
CPU time 4.81 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:35 PM PDT 24
Peak memory 216732 kb
Host smart-3d177eb1-3827-409d-8d84-146fe495a86a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974717911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.974717911
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1542262549
Short name T594
Test name
Test status
Simulation time 30073806 ps
CPU time 2 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:15 PM PDT 24
Peak memory 217880 kb
Host smart-f8ced16e-50e4-425b-b4d1-27a787370b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542262549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1542262549
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3815412119
Short name T553
Test name
Test status
Simulation time 1046338928 ps
CPU time 8.85 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:39 PM PDT 24
Peak memory 225644 kb
Host smart-43add31b-919a-4608-936a-374f011a161b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815412119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3815412119
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4107725268
Short name T531
Test name
Test status
Simulation time 1325704598 ps
CPU time 10.64 seconds
Started Jul 22 07:24:38 PM PDT 24
Finished Jul 22 07:25:44 PM PDT 24
Peak memory 225560 kb
Host smart-d4eafb28-bc59-4ec3-a0d5-7b520e48e8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107725268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4107725268
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3610603276
Short name T228
Test name
Test status
Simulation time 248797512 ps
CPU time 9.56 seconds
Started Jul 22 07:24:37 PM PDT 24
Finished Jul 22 07:25:42 PM PDT 24
Peak memory 225556 kb
Host smart-3ba6741b-8f8f-42f0-9c0b-46c9081fa3b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610603276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3610603276
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.547872923
Short name T310
Test name
Test status
Simulation time 264974834 ps
CPU time 9.48 seconds
Started Jul 22 07:24:35 PM PDT 24
Finished Jul 22 07:25:38 PM PDT 24
Peak memory 217916 kb
Host smart-52dd23dc-1c6b-4b7b-8c1c-aaf6bbe48e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547872923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.547872923
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2536447088
Short name T867
Test name
Test status
Simulation time 83101585 ps
CPU time 2.98 seconds
Started Jul 22 07:24:21 PM PDT 24
Finished Jul 22 07:25:14 PM PDT 24
Peak memory 214072 kb
Host smart-0a480dcb-79d3-469b-8e78-4d8378ba0201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536447088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2536447088
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1831723840
Short name T343
Test name
Test status
Simulation time 834900575 ps
CPU time 24.82 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:37 PM PDT 24
Peak memory 245504 kb
Host smart-655a2b76-c68c-402e-b5fc-a98b4a55ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831723840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1831723840
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.4166258671
Short name T217
Test name
Test status
Simulation time 488754340 ps
CPU time 7.43 seconds
Started Jul 22 07:24:23 PM PDT 24
Finished Jul 22 07:25:19 PM PDT 24
Peak memory 250784 kb
Host smart-9261fbd9-c938-4877-9eea-ac621d3f6479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166258671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.4166258671
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2930287872
Short name T586
Test name
Test status
Simulation time 51736856209 ps
CPU time 111.31 seconds
Started Jul 22 07:24:37 PM PDT 24
Finished Jul 22 07:27:24 PM PDT 24
Peak memory 217452 kb
Host smart-561c839b-89c9-4c9a-a356-c2fa40596174
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930287872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2930287872
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1485525753
Short name T44
Test name
Test status
Simulation time 268750886223 ps
CPU time 330.62 seconds
Started Jul 22 07:24:37 PM PDT 24
Finished Jul 22 07:31:03 PM PDT 24
Peak memory 314128 kb
Host smart-13d7fcef-95dc-42af-b11a-3b30298da619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1485525753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1485525753
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3897194628
Short name T248
Test name
Test status
Simulation time 61502082 ps
CPU time 0.83 seconds
Started Jul 22 07:24:25 PM PDT 24
Finished Jul 22 07:25:15 PM PDT 24
Peak memory 211496 kb
Host smart-0cd36de0-4681-4518-98a1-0810a82137e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897194628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3897194628
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1753948122
Short name T755
Test name
Test status
Simulation time 88412760 ps
CPU time 1.14 seconds
Started Jul 22 07:24:37 PM PDT 24
Finished Jul 22 07:25:32 PM PDT 24
Peak memory 208432 kb
Host smart-ea5a8bc6-dffc-42ec-9e73-1eaf6f438f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753948122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1753948122
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.544196336
Short name T583
Test name
Test status
Simulation time 301992512 ps
CPU time 9.44 seconds
Started Jul 22 07:24:35 PM PDT 24
Finished Jul 22 07:25:37 PM PDT 24
Peak memory 225644 kb
Host smart-80a3467a-1cff-411d-9e3d-087bcf85d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544196336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.544196336
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.19238521
Short name T680
Test name
Test status
Simulation time 2602436506 ps
CPU time 15.03 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:44 PM PDT 24
Peak memory 217332 kb
Host smart-beaecefa-376f-4b54-a78f-d372b2285677
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.19238521
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3087254521
Short name T378
Test name
Test status
Simulation time 61709320 ps
CPU time 3.29 seconds
Started Jul 22 07:24:37 PM PDT 24
Finished Jul 22 07:25:34 PM PDT 24
Peak memory 222280 kb
Host smart-c3824868-6717-490e-b320-1a76fe2b9ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087254521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3087254521
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2894368809
Short name T47
Test name
Test status
Simulation time 485752516 ps
CPU time 15.13 seconds
Started Jul 22 07:24:37 PM PDT 24
Finished Jul 22 07:25:46 PM PDT 24
Peak memory 225656 kb
Host smart-327e477f-dda0-4df9-aebe-803d5143850e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894368809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2894368809
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1565283048
Short name T413
Test name
Test status
Simulation time 563684715 ps
CPU time 8.2 seconds
Started Jul 22 07:24:34 PM PDT 24
Finished Jul 22 07:25:35 PM PDT 24
Peak memory 225640 kb
Host smart-8b3b7149-fcc2-418e-9cf6-09a65d597291
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565283048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1565283048
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2813058079
Short name T623
Test name
Test status
Simulation time 2625082352 ps
CPU time 12.25 seconds
Started Jul 22 07:24:37 PM PDT 24
Finished Jul 22 07:25:44 PM PDT 24
Peak memory 225700 kb
Host smart-8cd164b2-a137-4512-98c4-73444937095b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813058079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2813058079
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3285897861
Short name T290
Test name
Test status
Simulation time 569881623 ps
CPU time 8.5 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:39 PM PDT 24
Peak memory 217920 kb
Host smart-171e91e4-5c96-4308-b7f2-57ab2a13de06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285897861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3285897861
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3771624093
Short name T616
Test name
Test status
Simulation time 34679334 ps
CPU time 2.35 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:32 PM PDT 24
Peak memory 214172 kb
Host smart-aa2bc1b4-0041-4339-8504-356b8928f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771624093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3771624093
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.399683827
Short name T774
Test name
Test status
Simulation time 818554209 ps
CPU time 24.41 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:53 PM PDT 24
Peak memory 250608 kb
Host smart-6e3640f1-4d08-4961-8b6f-78e0ae745c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399683827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.399683827
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1025262316
Short name T787
Test name
Test status
Simulation time 379274515 ps
CPU time 3.34 seconds
Started Jul 22 07:24:35 PM PDT 24
Finished Jul 22 07:25:30 PM PDT 24
Peak memory 226004 kb
Host smart-680dbf29-690a-49aa-8489-6fce78aeb5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025262316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1025262316
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.4042943284
Short name T860
Test name
Test status
Simulation time 25159306346 ps
CPU time 190.33 seconds
Started Jul 22 07:24:38 PM PDT 24
Finished Jul 22 07:28:43 PM PDT 24
Peak memory 283408 kb
Host smart-92a8a2e0-2ced-44cb-8772-01f496fb2638
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042943284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.4042943284
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3079269779
Short name T340
Test name
Test status
Simulation time 14724130 ps
CPU time 1.09 seconds
Started Jul 22 07:24:38 PM PDT 24
Finished Jul 22 07:25:34 PM PDT 24
Peak memory 211568 kb
Host smart-074b27d5-534f-4d78-ad7d-d3aa0422a376
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079269779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3079269779
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1600948036
Short name T514
Test name
Test status
Simulation time 32598881 ps
CPU time 0.93 seconds
Started Jul 22 07:24:46 PM PDT 24
Finished Jul 22 07:25:48 PM PDT 24
Peak memory 208528 kb
Host smart-db9b7aeb-b2c1-4ec2-b148-0b0bad677a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600948036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1600948036
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1980713612
Short name T845
Test name
Test status
Simulation time 484044378 ps
CPU time 8.04 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:38 PM PDT 24
Peak memory 217848 kb
Host smart-5b8158e7-3a85-40e4-9043-571397b25c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980713612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1980713612
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2431614579
Short name T34
Test name
Test status
Simulation time 294627106 ps
CPU time 8.52 seconds
Started Jul 22 07:24:46 PM PDT 24
Finished Jul 22 07:25:56 PM PDT 24
Peak memory 217200 kb
Host smart-29cd5962-107b-4471-9139-ef96534d4a09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431614579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2431614579
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1425460913
Short name T152
Test name
Test status
Simulation time 227621170 ps
CPU time 3.3 seconds
Started Jul 22 07:24:35 PM PDT 24
Finished Jul 22 07:25:30 PM PDT 24
Peak memory 222220 kb
Host smart-2ee0716e-60d2-4f70-a72d-f5d3c609a834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425460913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1425460913
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.858071687
Short name T410
Test name
Test status
Simulation time 794784861 ps
CPU time 18.27 seconds
Started Jul 22 07:24:52 PM PDT 24
Finished Jul 22 07:26:15 PM PDT 24
Peak memory 219548 kb
Host smart-4a1d0e42-0c62-4788-a3a3-8efe802f7a76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858071687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.858071687
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1969569000
Short name T361
Test name
Test status
Simulation time 1666950675 ps
CPU time 15.14 seconds
Started Jul 22 07:24:45 PM PDT 24
Finished Jul 22 07:26:02 PM PDT 24
Peak memory 225524 kb
Host smart-7ea05994-4129-486a-84b1-65f20de2a146
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969569000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1969569000
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3952765894
Short name T35
Test name
Test status
Simulation time 346233714 ps
CPU time 11.23 seconds
Started Jul 22 07:24:52 PM PDT 24
Finished Jul 22 07:26:08 PM PDT 24
Peak memory 225588 kb
Host smart-0f78ff33-a279-47c0-9b81-9f6ca9febc1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952765894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3952765894
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3461781329
Short name T342
Test name
Test status
Simulation time 704092205 ps
CPU time 8.39 seconds
Started Jul 22 07:24:47 PM PDT 24
Finished Jul 22 07:25:58 PM PDT 24
Peak memory 217940 kb
Host smart-d920fcb7-d183-491e-baa5-069d1c2af997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461781329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3461781329
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2516131490
Short name T515
Test name
Test status
Simulation time 514098221 ps
CPU time 2.71 seconds
Started Jul 22 07:24:38 PM PDT 24
Finished Jul 22 07:25:36 PM PDT 24
Peak memory 217344 kb
Host smart-d8eac824-7c27-4c61-b2a4-8bb9f35f0e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516131490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2516131490
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3176542236
Short name T381
Test name
Test status
Simulation time 295280238 ps
CPU time 16.35 seconds
Started Jul 22 07:24:35 PM PDT 24
Finished Jul 22 07:25:45 PM PDT 24
Peak memory 250400 kb
Host smart-8936a2b7-4341-4b2c-9089-449193beb6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176542236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3176542236
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.53351629
Short name T161
Test name
Test status
Simulation time 184589203 ps
CPU time 8.72 seconds
Started Jul 22 07:24:36 PM PDT 24
Finished Jul 22 07:25:39 PM PDT 24
Peak memory 250564 kb
Host smart-b9e4815b-5bb9-46d3-be24-0f9b32d3c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53351629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.53351629
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3732320703
Short name T657
Test name
Test status
Simulation time 7578022587 ps
CPU time 62.88 seconds
Started Jul 22 07:24:48 PM PDT 24
Finished Jul 22 07:26:55 PM PDT 24
Peak memory 252460 kb
Host smart-81e7173d-afdc-45fa-b85e-7ca84efaff88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732320703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3732320703
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2831425252
Short name T149
Test name
Test status
Simulation time 209778927220 ps
CPU time 547.79 seconds
Started Jul 22 07:24:51 PM PDT 24
Finished Jul 22 07:35:04 PM PDT 24
Peak memory 282128 kb
Host smart-e0b433a5-24cb-4df6-a084-256950eb9519
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2831425252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2831425252
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1316179783
Short name T372
Test name
Test status
Simulation time 12675315 ps
CPU time 1.05 seconds
Started Jul 22 07:24:34 PM PDT 24
Finished Jul 22 07:25:28 PM PDT 24
Peak memory 211428 kb
Host smart-e385ef9b-a3e5-4538-824d-61979eaf6fe7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316179783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1316179783
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1911235269
Short name T78
Test name
Test status
Simulation time 97139650 ps
CPU time 0.89 seconds
Started Jul 22 07:24:47 PM PDT 24
Finished Jul 22 07:25:50 PM PDT 24
Peak memory 208628 kb
Host smart-243b2c5d-8537-4ef3-b510-50eb484c4eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911235269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1911235269
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1407266711
Short name T488
Test name
Test status
Simulation time 1761076257 ps
CPU time 20.63 seconds
Started Jul 22 07:24:52 PM PDT 24
Finished Jul 22 07:26:17 PM PDT 24
Peak memory 217856 kb
Host smart-31a2c8fe-51a5-4171-bf46-f1ae843e3d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407266711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1407266711
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3968518005
Short name T276
Test name
Test status
Simulation time 198221928 ps
CPU time 4.36 seconds
Started Jul 22 07:24:49 PM PDT 24
Finished Jul 22 07:25:57 PM PDT 24
Peak memory 217272 kb
Host smart-47d08da2-84c6-41c5-8908-3ee814335b94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968518005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3968518005
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1840917201
Short name T844
Test name
Test status
Simulation time 74656468 ps
CPU time 2 seconds
Started Jul 22 07:24:51 PM PDT 24
Finished Jul 22 07:25:57 PM PDT 24
Peak memory 217848 kb
Host smart-a014982d-5610-42ea-aad4-242f30fdd0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840917201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1840917201
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1063015608
Short name T254
Test name
Test status
Simulation time 285736319 ps
CPU time 9.54 seconds
Started Jul 22 07:24:47 PM PDT 24
Finished Jul 22 07:25:58 PM PDT 24
Peak memory 225664 kb
Host smart-b804b886-f92e-4781-9d79-cb689c2dba58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063015608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1063015608
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.4019693651
Short name T233
Test name
Test status
Simulation time 258640031 ps
CPU time 7.3 seconds
Started Jul 22 07:24:46 PM PDT 24
Finished Jul 22 07:25:55 PM PDT 24
Peak memory 225592 kb
Host smart-0e077a36-96b5-4594-8473-8687d26961a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019693651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
4019693651
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1919200218
Short name T81
Test name
Test status
Simulation time 2614472815 ps
CPU time 11.47 seconds
Started Jul 22 07:24:46 PM PDT 24
Finished Jul 22 07:25:59 PM PDT 24
Peak memory 225516 kb
Host smart-bc10d28b-bf40-49f5-bae0-1d77ab6f24bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919200218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1919200218
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1849975017
Short name T638
Test name
Test status
Simulation time 138577795 ps
CPU time 2.09 seconds
Started Jul 22 07:24:46 PM PDT 24
Finished Jul 22 07:25:49 PM PDT 24
Peak memory 217464 kb
Host smart-4a24531b-9acf-483c-a0b1-28162ee66974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849975017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1849975017
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2861825840
Short name T456
Test name
Test status
Simulation time 759789264 ps
CPU time 21.19 seconds
Started Jul 22 07:24:46 PM PDT 24
Finished Jul 22 07:26:08 PM PDT 24
Peak memory 250508 kb
Host smart-b75361e0-7dfe-41af-a280-ad22932da48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861825840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2861825840
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2341916284
Short name T280
Test name
Test status
Simulation time 72939081 ps
CPU time 8.5 seconds
Started Jul 22 07:24:48 PM PDT 24
Finished Jul 22 07:26:00 PM PDT 24
Peak memory 250716 kb
Host smart-55a29951-dd2b-43f1-b53d-02a1c7bb1a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341916284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2341916284
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.633839184
Short name T43
Test name
Test status
Simulation time 71076098723 ps
CPU time 277.4 seconds
Started Jul 22 07:24:49 PM PDT 24
Finished Jul 22 07:30:30 PM PDT 24
Peak memory 316160 kb
Host smart-ee281e89-85cd-4485-8415-03118d2d6e8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633839184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.633839184
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.408325465
Short name T792
Test name
Test status
Simulation time 35666154803 ps
CPU time 271.6 seconds
Started Jul 22 07:24:47 PM PDT 24
Finished Jul 22 07:30:21 PM PDT 24
Peak memory 275640 kb
Host smart-2076affd-057e-4483-aaa4-417672acf57b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=408325465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.408325465
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3750794881
Short name T728
Test name
Test status
Simulation time 29075909 ps
CPU time 0.94 seconds
Started Jul 22 07:24:51 PM PDT 24
Finished Jul 22 07:25:57 PM PDT 24
Peak memory 212528 kb
Host smart-eeba2df8-b21d-4e26-9a45-d515dbf7957b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750794881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3750794881
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.301357574
Short name T77
Test name
Test status
Simulation time 101852370 ps
CPU time 1.09 seconds
Started Jul 22 07:26:25 PM PDT 24
Finished Jul 22 07:27:45 PM PDT 24
Peak memory 207900 kb
Host smart-e613aed9-362e-4b01-a999-207ac66d0621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301357574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.301357574
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.576760195
Short name T645
Test name
Test status
Simulation time 324295406 ps
CPU time 11.45 seconds
Started Jul 22 07:24:51 PM PDT 24
Finished Jul 22 07:26:07 PM PDT 24
Peak memory 225460 kb
Host smart-02ea2fc6-e548-44b7-845b-31a876714311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576760195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.576760195
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1336463839
Short name T32
Test name
Test status
Simulation time 483619853 ps
CPU time 3.28 seconds
Started Jul 22 07:24:52 PM PDT 24
Finished Jul 22 07:26:00 PM PDT 24
Peak memory 216724 kb
Host smart-4edff5e0-832d-485e-9997-4906b0d8805f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336463839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1336463839
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2718174851
Short name T209
Test name
Test status
Simulation time 73987986 ps
CPU time 3.68 seconds
Started Jul 22 07:24:52 PM PDT 24
Finished Jul 22 07:26:00 PM PDT 24
Peak memory 217856 kb
Host smart-53172080-0fd7-437a-8feb-6a33bcfa8d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718174851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2718174851
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.306295630
Short name T326
Test name
Test status
Simulation time 772614644 ps
CPU time 22.44 seconds
Started Jul 22 07:26:25 PM PDT 24
Finished Jul 22 07:28:07 PM PDT 24
Peak memory 225056 kb
Host smart-dc10f5ae-c956-4a43-a03d-c8fdddddceff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306295630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.306295630
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3904384700
Short name T684
Test name
Test status
Simulation time 1349284311 ps
CPU time 9.9 seconds
Started Jul 22 07:24:47 PM PDT 24
Finished Jul 22 07:25:59 PM PDT 24
Peak memory 225584 kb
Host smart-0d269a2c-556d-4ea9-a0bd-cfd2fd7cd757
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904384700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3904384700
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2146954453
Short name T502
Test name
Test status
Simulation time 203375842 ps
CPU time 8.46 seconds
Started Jul 22 07:24:47 PM PDT 24
Finished Jul 22 07:25:57 PM PDT 24
Peak memory 225584 kb
Host smart-0a21efce-374b-4273-87de-a21fe8d906cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146954453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2146954453
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1789891201
Short name T193
Test name
Test status
Simulation time 549056872 ps
CPU time 20.79 seconds
Started Jul 22 07:24:46 PM PDT 24
Finished Jul 22 07:26:08 PM PDT 24
Peak memory 225616 kb
Host smart-5a61f18a-90fd-49f3-b245-6926234a07ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789891201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1789891201
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2349540385
Short name T68
Test name
Test status
Simulation time 88293219 ps
CPU time 1.92 seconds
Started Jul 22 07:26:25 PM PDT 24
Finished Jul 22 07:27:46 PM PDT 24
Peak memory 216948 kb
Host smart-0a13a26b-420d-4159-a3da-e2f151f88bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349540385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2349540385
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3024558264
Short name T297
Test name
Test status
Simulation time 73297630 ps
CPU time 7.16 seconds
Started Jul 22 07:24:46 PM PDT 24
Finished Jul 22 07:25:54 PM PDT 24
Peak memory 250160 kb
Host smart-6ded7800-e0ec-4c19-bd97-80eafab87ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024558264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3024558264
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3051463219
Short name T523
Test name
Test status
Simulation time 44847117078 ps
CPU time 184.71 seconds
Started Jul 22 07:24:48 PM PDT 24
Finished Jul 22 07:28:55 PM PDT 24
Peak memory 278136 kb
Host smart-a8c09f3b-8f25-41f1-9e60-baa62ec53c06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051463219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3051463219
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3901577327
Short name T139
Test name
Test status
Simulation time 47907276328 ps
CPU time 985.89 seconds
Started Jul 22 07:24:59 PM PDT 24
Finished Jul 22 07:42:33 PM PDT 24
Peak memory 611228 kb
Host smart-a86bc7c6-763f-4df7-872e-5c52770ddbea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3901577327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3901577327
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4123013517
Short name T513
Test name
Test status
Simulation time 23123759 ps
CPU time 1 seconds
Started Jul 22 07:26:25 PM PDT 24
Finished Jul 22 07:27:45 PM PDT 24
Peak memory 217216 kb
Host smart-cc591e32-12f2-4072-95d7-25a34b3984ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123013517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4123013517
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4214567295
Short name T693
Test name
Test status
Simulation time 18898702 ps
CPU time 0.95 seconds
Started Jul 22 07:25:01 PM PDT 24
Finished Jul 22 07:26:11 PM PDT 24
Peak memory 207952 kb
Host smart-c740eeed-a566-4d7d-8fd7-0f81441d3aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214567295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4214567295
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.393858061
Short name T459
Test name
Test status
Simulation time 569451419 ps
CPU time 9.82 seconds
Started Jul 22 07:24:57 PM PDT 24
Finished Jul 22 07:26:13 PM PDT 24
Peak memory 225652 kb
Host smart-bfbc57bc-3cf2-4a1f-acbc-c2cce00758d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393858061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.393858061
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3271327221
Short name T858
Test name
Test status
Simulation time 409650569 ps
CPU time 11.05 seconds
Started Jul 22 07:26:39 PM PDT 24
Finished Jul 22 07:28:09 PM PDT 24
Peak memory 217252 kb
Host smart-09aee816-d22c-41e8-a930-211419b68377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271327221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3271327221
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.128654948
Short name T719
Test name
Test status
Simulation time 449781378 ps
CPU time 3.65 seconds
Started Jul 22 07:25:16 PM PDT 24
Finished Jul 22 07:26:38 PM PDT 24
Peak memory 217796 kb
Host smart-d0f204fe-a571-4a01-b747-cd9b865ebd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128654948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.128654948
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4147886604
Short name T698
Test name
Test status
Simulation time 1365715104 ps
CPU time 13.73 seconds
Started Jul 22 07:26:39 PM PDT 24
Finished Jul 22 07:28:11 PM PDT 24
Peak memory 225636 kb
Host smart-9fdeebf8-a45b-44b8-a20d-bcd0b0a43ba6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147886604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4147886604
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2274117210
Short name T277
Test name
Test status
Simulation time 742788912 ps
CPU time 7.9 seconds
Started Jul 22 07:24:56 PM PDT 24
Finished Jul 22 07:26:11 PM PDT 24
Peak memory 225572 kb
Host smart-7daa6893-ed1b-4ebd-a70c-61136e1bde7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274117210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2274117210
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1978987574
Short name T21
Test name
Test status
Simulation time 754554764 ps
CPU time 6.28 seconds
Started Jul 22 07:24:55 PM PDT 24
Finished Jul 22 07:26:08 PM PDT 24
Peak memory 217780 kb
Host smart-022c4d51-d7ab-479e-81dc-d3e20ef0f15f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978987574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1978987574
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.4029719713
Short name T89
Test name
Test status
Simulation time 323632087 ps
CPU time 11.51 seconds
Started Jul 22 07:24:51 PM PDT 24
Finished Jul 22 07:26:08 PM PDT 24
Peak memory 217960 kb
Host smart-f9f3131f-102d-43e7-ad90-f3cb925d308d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029719713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4029719713
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2829949486
Short name T70
Test name
Test status
Simulation time 55081556 ps
CPU time 1.23 seconds
Started Jul 22 07:24:47 PM PDT 24
Finished Jul 22 07:25:50 PM PDT 24
Peak memory 217452 kb
Host smart-f4311946-7b3a-4e79-bf10-1df6430c8d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829949486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2829949486
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1556488819
Short name T808
Test name
Test status
Simulation time 990508682 ps
CPU time 21.4 seconds
Started Jul 22 07:24:51 PM PDT 24
Finished Jul 22 07:26:18 PM PDT 24
Peak memory 245420 kb
Host smart-d754c305-9f30-43c2-8e12-6d34f776f346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556488819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1556488819
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.290592225
Short name T437
Test name
Test status
Simulation time 175563092 ps
CPU time 6.66 seconds
Started Jul 22 07:24:47 PM PDT 24
Finished Jul 22 07:25:56 PM PDT 24
Peak memory 250076 kb
Host smart-aaae9e82-0da8-4ddb-aa20-134694f49460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290592225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.290592225
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2205525228
Short name T60
Test name
Test status
Simulation time 17282138577 ps
CPU time 117.23 seconds
Started Jul 22 07:24:55 PM PDT 24
Finished Jul 22 07:27:57 PM PDT 24
Peak memory 268616 kb
Host smart-5464fcf9-89dc-4439-8b71-d46bb4f67337
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205525228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2205525228
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1544573540
Short name T186
Test name
Test status
Simulation time 152795706626 ps
CPU time 1287.19 seconds
Started Jul 22 07:26:39 PM PDT 24
Finished Jul 22 07:49:25 PM PDT 24
Peak memory 320744 kb
Host smart-5e1aaf1c-de4a-4dde-b727-c5ea52f7b399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1544573540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1544573540
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1369658911
Short name T574
Test name
Test status
Simulation time 15325077 ps
CPU time 0.93 seconds
Started Jul 22 07:24:50 PM PDT 24
Finished Jul 22 07:25:53 PM PDT 24
Peak memory 211576 kb
Host smart-df55b685-5db8-4767-8716-77ecb788a12c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369658911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1369658911
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.4215962604
Short name T222
Test name
Test status
Simulation time 83323518 ps
CPU time 1 seconds
Started Jul 22 07:24:57 PM PDT 24
Finished Jul 22 07:26:05 PM PDT 24
Peak memory 208516 kb
Host smart-07cb0763-99d7-4de3-8e0c-c20c409cc677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215962604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.4215962604
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2372534158
Short name T661
Test name
Test status
Simulation time 402613421 ps
CPU time 11.2 seconds
Started Jul 22 07:24:56 PM PDT 24
Finished Jul 22 07:26:13 PM PDT 24
Peak memory 217844 kb
Host smart-910195dd-71ec-44dd-a4f8-86854c8fefc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372534158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2372534158
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.456109428
Short name T580
Test name
Test status
Simulation time 301912573 ps
CPU time 4.62 seconds
Started Jul 22 07:25:01 PM PDT 24
Finished Jul 22 07:26:15 PM PDT 24
Peak memory 216656 kb
Host smart-bdd1ceaa-bde3-4433-81b7-02d30d435d9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456109428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.456109428
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3092594956
Short name T403
Test name
Test status
Simulation time 36113539 ps
CPU time 1.96 seconds
Started Jul 22 07:24:57 PM PDT 24
Finished Jul 22 07:26:06 PM PDT 24
Peak memory 217916 kb
Host smart-4f167c14-7685-4e7e-a8eb-af38f876dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092594956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3092594956
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1320303278
Short name T344
Test name
Test status
Simulation time 511474043 ps
CPU time 8.23 seconds
Started Jul 22 07:24:57 PM PDT 24
Finished Jul 22 07:26:11 PM PDT 24
Peak memory 218680 kb
Host smart-37fc7c28-9953-44e7-935b-24246f480176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320303278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1320303278
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1010226717
Short name T341
Test name
Test status
Simulation time 1603560482 ps
CPU time 17.9 seconds
Started Jul 22 07:25:03 PM PDT 24
Finished Jul 22 07:26:32 PM PDT 24
Peak memory 225588 kb
Host smart-1e62ef26-4ad2-48bc-a0e8-4aedec82d88b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010226717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1010226717
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1247854441
Short name T738
Test name
Test status
Simulation time 1227534568 ps
CPU time 10.72 seconds
Started Jul 22 07:24:56 PM PDT 24
Finished Jul 22 07:26:13 PM PDT 24
Peak memory 225652 kb
Host smart-a626e794-ad6d-40c9-82a4-01e405398984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247854441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1247854441
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2312893621
Short name T71
Test name
Test status
Simulation time 52151400 ps
CPU time 3.28 seconds
Started Jul 22 07:24:56 PM PDT 24
Finished Jul 22 07:26:05 PM PDT 24
Peak memory 217304 kb
Host smart-b9dd65d8-b988-473a-b740-454775558365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312893621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2312893621
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1194513602
Short name T786
Test name
Test status
Simulation time 974486165 ps
CPU time 21.47 seconds
Started Jul 22 07:24:57 PM PDT 24
Finished Jul 22 07:26:24 PM PDT 24
Peak memory 250676 kb
Host smart-3a39458a-f887-4f57-931a-5872badb38c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194513602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1194513602
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3743828506
Short name T868
Test name
Test status
Simulation time 402165282 ps
CPU time 9.21 seconds
Started Jul 22 07:26:39 PM PDT 24
Finished Jul 22 07:28:07 PM PDT 24
Peak memory 250584 kb
Host smart-715970a2-9435-41c9-87af-18a66edf8d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743828506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3743828506
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.4195921994
Short name T164
Test name
Test status
Simulation time 7200335211 ps
CPU time 140.2 seconds
Started Jul 22 07:26:39 PM PDT 24
Finished Jul 22 07:30:18 PM PDT 24
Peak memory 272432 kb
Host smart-c3938c4d-15c8-475e-9fb9-f13e98feac60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195921994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.4195921994
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.4159615542
Short name T153
Test name
Test status
Simulation time 37428875828 ps
CPU time 1468.56 seconds
Started Jul 22 07:24:58 PM PDT 24
Finished Jul 22 07:50:33 PM PDT 24
Peak memory 480204 kb
Host smart-aa6bddea-0f6f-48a9-bf82-88ff569ade32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4159615542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.4159615542
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3303665752
Short name T481
Test name
Test status
Simulation time 23381057 ps
CPU time 0.98 seconds
Started Jul 22 07:25:00 PM PDT 24
Finished Jul 22 07:26:08 PM PDT 24
Peak memory 211416 kb
Host smart-f620a546-d5e5-4880-873e-26bdcd586b5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303665752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3303665752
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.4103554816
Short name T506
Test name
Test status
Simulation time 16378034 ps
CPU time 0.92 seconds
Started Jul 22 07:25:09 PM PDT 24
Finished Jul 22 07:26:24 PM PDT 24
Peak memory 208332 kb
Host smart-611769b3-cf0f-4d37-ae08-0c29128408e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103554816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4103554816
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2299020827
Short name T41
Test name
Test status
Simulation time 573893391 ps
CPU time 16.91 seconds
Started Jul 22 07:24:58 PM PDT 24
Finished Jul 22 07:26:21 PM PDT 24
Peak memory 225648 kb
Host smart-26deac95-c1ff-4d8e-936b-c02fb0d3ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299020827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2299020827
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1855465453
Short name T546
Test name
Test status
Simulation time 1385250660 ps
CPU time 4.82 seconds
Started Jul 22 07:24:58 PM PDT 24
Finished Jul 22 07:26:10 PM PDT 24
Peak memory 217276 kb
Host smart-9e5a7e6a-619e-4b8b-a1d8-6a511d48b347
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855465453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1855465453
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2860061413
Short name T330
Test name
Test status
Simulation time 58358526 ps
CPU time 2.37 seconds
Started Jul 22 07:25:01 PM PDT 24
Finished Jul 22 07:26:12 PM PDT 24
Peak memory 217848 kb
Host smart-3ed8a7ac-8108-4733-83dd-465f8f461b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860061413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2860061413
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1608288853
Short name T584
Test name
Test status
Simulation time 2824205541 ps
CPU time 29.94 seconds
Started Jul 22 07:24:58 PM PDT 24
Finished Jul 22 07:26:34 PM PDT 24
Peak memory 219672 kb
Host smart-3f8b8d46-00d4-48eb-b77c-ad5c5a86a57f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608288853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1608288853
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2548825538
Short name T736
Test name
Test status
Simulation time 786929609 ps
CPU time 15.29 seconds
Started Jul 22 07:25:03 PM PDT 24
Finished Jul 22 07:26:30 PM PDT 24
Peak memory 225584 kb
Host smart-4025d806-7695-47ef-bd1c-6db78a325e70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548825538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2548825538
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.329588906
Short name T146
Test name
Test status
Simulation time 353482749 ps
CPU time 5.83 seconds
Started Jul 22 07:25:00 PM PDT 24
Finished Jul 22 07:26:14 PM PDT 24
Peak memory 217800 kb
Host smart-e2735446-8530-4f49-b9be-bff13c0b88f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329588906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.329588906
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.835331075
Short name T700
Test name
Test status
Simulation time 1724519327 ps
CPU time 12.27 seconds
Started Jul 22 07:25:00 PM PDT 24
Finished Jul 22 07:26:22 PM PDT 24
Peak memory 217928 kb
Host smart-46e24687-c219-450c-a5f1-bcb3f12f44cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835331075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.835331075
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.4171184956
Short name T828
Test name
Test status
Simulation time 892560263 ps
CPU time 27.23 seconds
Started Jul 22 07:24:58 PM PDT 24
Finished Jul 22 07:26:32 PM PDT 24
Peak memory 250592 kb
Host smart-48a0de5b-f4e6-461b-a877-c96022e9bea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171184956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.4171184956
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.39239182
Short name T203
Test name
Test status
Simulation time 50349358 ps
CPU time 8.48 seconds
Started Jul 22 07:24:56 PM PDT 24
Finished Jul 22 07:26:10 PM PDT 24
Peak memory 246528 kb
Host smart-d999783e-534a-4a9a-901e-4352bead6c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39239182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.39239182
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3822696799
Short name T710
Test name
Test status
Simulation time 25024096947 ps
CPU time 121.93 seconds
Started Jul 22 07:24:55 PM PDT 24
Finished Jul 22 07:28:02 PM PDT 24
Peak memory 283392 kb
Host smart-48e51020-5fd7-4188-9fac-58bb69a83724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822696799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3822696799
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.299043183
Short name T807
Test name
Test status
Simulation time 13293743 ps
CPU time 1.07 seconds
Started Jul 22 07:24:56 PM PDT 24
Finished Jul 22 07:26:04 PM PDT 24
Peak memory 211536 kb
Host smart-735155be-f416-43fc-b840-ac6efa7acf06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299043183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.299043183
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.227259957
Short name T821
Test name
Test status
Simulation time 17615326 ps
CPU time 1.13 seconds
Started Jul 22 07:25:06 PM PDT 24
Finished Jul 22 07:26:19 PM PDT 24
Peak memory 208560 kb
Host smart-05fae7ac-6947-4234-a2dd-b8f2e2b8b453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227259957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.227259957
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2215935396
Short name T804
Test name
Test status
Simulation time 793686646 ps
CPU time 17.59 seconds
Started Jul 22 07:25:08 PM PDT 24
Finished Jul 22 07:26:38 PM PDT 24
Peak memory 217896 kb
Host smart-b3b141bd-9c05-4fa4-969f-6eb62aeeec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215935396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2215935396
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3859567673
Short name T4
Test name
Test status
Simulation time 2115650314 ps
CPU time 3.65 seconds
Started Jul 22 07:25:07 PM PDT 24
Finished Jul 22 07:26:24 PM PDT 24
Peak memory 217244 kb
Host smart-92032b6e-9379-4f6f-9ebf-1eddcd376100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859567673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3859567673
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.855079891
Short name T37
Test name
Test status
Simulation time 161788661 ps
CPU time 2.88 seconds
Started Jul 22 07:25:09 PM PDT 24
Finished Jul 22 07:26:26 PM PDT 24
Peak memory 217848 kb
Host smart-e44ec92b-ff32-4006-b492-4a97d7e9371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855079891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.855079891
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.480729700
Short name T285
Test name
Test status
Simulation time 1419387539 ps
CPU time 14.57 seconds
Started Jul 22 07:25:07 PM PDT 24
Finished Jul 22 07:26:35 PM PDT 24
Peak memory 218448 kb
Host smart-ed7656ad-eb17-49cb-a26c-e8907dba6a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480729700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.480729700
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1123327575
Short name T351
Test name
Test status
Simulation time 10448724283 ps
CPU time 19.31 seconds
Started Jul 22 07:25:07 PM PDT 24
Finished Jul 22 07:26:40 PM PDT 24
Peak memory 217836 kb
Host smart-1dcdf51d-b65d-4eef-939c-8a1eb6ab95e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123327575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1123327575
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.58466146
Short name T380
Test name
Test status
Simulation time 377201719 ps
CPU time 13.23 seconds
Started Jul 22 07:25:07 PM PDT 24
Finished Jul 22 07:26:33 PM PDT 24
Peak memory 225580 kb
Host smart-c8e2a177-a12c-4cdf-9658-82c378d5efd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58466146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.58466146
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.4208107267
Short name T503
Test name
Test status
Simulation time 218606716 ps
CPU time 8.59 seconds
Started Jul 22 07:25:09 PM PDT 24
Finished Jul 22 07:26:31 PM PDT 24
Peak memory 217948 kb
Host smart-7900086d-46da-4311-aafd-a6d0fd407af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208107267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4208107267
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1998073116
Short name T198
Test name
Test status
Simulation time 72168065 ps
CPU time 1.23 seconds
Started Jul 22 07:26:39 PM PDT 24
Finished Jul 22 07:27:59 PM PDT 24
Peak memory 217084 kb
Host smart-ce795de2-fd50-49ac-b1a8-c45d019e3a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998073116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1998073116
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2727490954
Short name T833
Test name
Test status
Simulation time 975350451 ps
CPU time 30.11 seconds
Started Jul 22 07:25:07 PM PDT 24
Finished Jul 22 07:26:50 PM PDT 24
Peak memory 250556 kb
Host smart-09f070e5-3dc7-4036-80aa-f7d412b833a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727490954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2727490954
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1272971457
Short name T315
Test name
Test status
Simulation time 40619228 ps
CPU time 6.32 seconds
Started Jul 22 07:25:27 PM PDT 24
Finished Jul 22 07:26:54 PM PDT 24
Peak memory 246520 kb
Host smart-e6d83d86-c647-46fa-9f2e-63682d8dea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272971457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1272971457
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1981249378
Short name T165
Test name
Test status
Simulation time 8544465107 ps
CPU time 152.56 seconds
Started Jul 22 07:25:08 PM PDT 24
Finished Jul 22 07:28:55 PM PDT 24
Peak memory 283412 kb
Host smart-b130539e-44cb-4cf7-9ea4-818b751e96c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981249378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1981249378
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2255401187
Short name T745
Test name
Test status
Simulation time 7212359803 ps
CPU time 257.5 seconds
Started Jul 22 07:25:08 PM PDT 24
Finished Jul 22 07:30:38 PM PDT 24
Peak memory 398172 kb
Host smart-1ff7b49c-a55c-4484-a7a1-745d2d62be06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2255401187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2255401187
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.371437351
Short name T234
Test name
Test status
Simulation time 43291271 ps
CPU time 0.82 seconds
Started Jul 22 07:25:06 PM PDT 24
Finished Jul 22 07:26:19 PM PDT 24
Peak memory 211364 kb
Host smart-a6e4fcd2-d975-43f6-8bd9-4d9a1bdf9647
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371437351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.371437351
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.492631102
Short name T442
Test name
Test status
Simulation time 41698730 ps
CPU time 0.95 seconds
Started Jul 22 07:25:21 PM PDT 24
Finished Jul 22 07:26:41 PM PDT 24
Peak memory 208424 kb
Host smart-856afbfd-c805-4f83-805d-f0a88e921cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492631102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.492631102
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3945780800
Short name T80
Test name
Test status
Simulation time 1886873147 ps
CPU time 18.32 seconds
Started Jul 22 07:25:17 PM PDT 24
Finished Jul 22 07:26:57 PM PDT 24
Peak memory 217780 kb
Host smart-cf51762c-2207-458e-95fa-b8689e9dba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945780800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3945780800
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2632390586
Short name T743
Test name
Test status
Simulation time 380099381 ps
CPU time 5.58 seconds
Started Jul 22 07:25:17 PM PDT 24
Finished Jul 22 07:26:44 PM PDT 24
Peak memory 217268 kb
Host smart-29bda0cc-32b5-4614-81c5-20a4e035359b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632390586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2632390586
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.743548849
Short name T311
Test name
Test status
Simulation time 84566872 ps
CPU time 3.91 seconds
Started Jul 22 07:25:18 PM PDT 24
Finished Jul 22 07:26:42 PM PDT 24
Peak memory 217764 kb
Host smart-1ffdbb10-a6b3-464a-8d92-322ec165f7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743548849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.743548849
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2154802792
Short name T227
Test name
Test status
Simulation time 412716145 ps
CPU time 9.81 seconds
Started Jul 22 07:25:19 PM PDT 24
Finished Jul 22 07:26:47 PM PDT 24
Peak memory 225300 kb
Host smart-79a28e57-d371-4d0c-aa45-6f59fd261afb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154802792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2154802792
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3358274142
Short name T419
Test name
Test status
Simulation time 6060594151 ps
CPU time 10.03 seconds
Started Jul 22 07:25:17 PM PDT 24
Finished Jul 22 07:26:45 PM PDT 24
Peak memory 225644 kb
Host smart-3b119ca0-ac97-4a7c-b41a-d3c47e343772
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358274142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3358274142
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3164587305
Short name T689
Test name
Test status
Simulation time 945192521 ps
CPU time 8.75 seconds
Started Jul 22 07:25:18 PM PDT 24
Finished Jul 22 07:26:44 PM PDT 24
Peak memory 217768 kb
Host smart-e9680838-e42c-4f6e-b53b-5abfc08467ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164587305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3164587305
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.938104662
Short name T790
Test name
Test status
Simulation time 139416150 ps
CPU time 2.33 seconds
Started Jul 22 07:25:07 PM PDT 24
Finished Jul 22 07:26:23 PM PDT 24
Peak memory 213768 kb
Host smart-1bdf3175-d85c-41f5-b721-4d55eed2c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938104662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.938104662
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3179938912
Short name T461
Test name
Test status
Simulation time 225103027 ps
CPU time 19.05 seconds
Started Jul 22 07:25:10 PM PDT 24
Finished Jul 22 07:26:43 PM PDT 24
Peak memory 250596 kb
Host smart-bf8e9cd4-414d-459a-be56-053763a7f393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179938912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3179938912
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1201485816
Short name T252
Test name
Test status
Simulation time 109823526 ps
CPU time 3.75 seconds
Started Jul 22 07:25:20 PM PDT 24
Finished Jul 22 07:26:44 PM PDT 24
Peak memory 222444 kb
Host smart-a35fc720-fbc6-4c08-a8f8-c3fa52ccbd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201485816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1201485816
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1242235964
Short name T609
Test name
Test status
Simulation time 23844228221 ps
CPU time 714.04 seconds
Started Jul 22 07:25:17 PM PDT 24
Finished Jul 22 07:38:32 PM PDT 24
Peak memory 253484 kb
Host smart-1eda3abf-5ddc-427f-ab51-70cb305be8a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242235964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1242235964
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3957408515
Short name T305
Test name
Test status
Simulation time 34902883 ps
CPU time 0.92 seconds
Started Jul 22 07:25:10 PM PDT 24
Finished Jul 22 07:26:25 PM PDT 24
Peak memory 211452 kb
Host smart-12f83504-c176-4ca8-9265-242b1a787bc5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957408515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3957408515
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2914697789
Short name T829
Test name
Test status
Simulation time 15671510 ps
CPU time 1.03 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:53 PM PDT 24
Peak memory 208152 kb
Host smart-a35752ef-b343-4e54-84c2-87374a932732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914697789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2914697789
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3321965344
Short name T296
Test name
Test status
Simulation time 13589154 ps
CPU time 0.82 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:24:57 PM PDT 24
Peak memory 207560 kb
Host smart-72175445-2f42-46fa-af72-5a67b2383368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321965344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3321965344
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1635315693
Short name T591
Test name
Test status
Simulation time 343496351 ps
CPU time 11.14 seconds
Started Jul 22 07:21:01 PM PDT 24
Finished Jul 22 07:21:48 PM PDT 24
Peak memory 217864 kb
Host smart-517dfd03-4c35-45a0-a24e-3ca2ca995793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635315693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1635315693
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3799310683
Short name T28
Test name
Test status
Simulation time 724548298 ps
CPU time 7.4 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:50 PM PDT 24
Peak memory 216992 kb
Host smart-481541c8-a3fa-494d-b2ba-e9fca4084118
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799310683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3799310683
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4168583592
Short name T823
Test name
Test status
Simulation time 2338322462 ps
CPU time 34.3 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:24:26 PM PDT 24
Peak memory 218664 kb
Host smart-a6779fc2-3abd-4f28-b9f1-9000bb9348a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168583592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4168583592
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.518278040
Short name T724
Test name
Test status
Simulation time 7819905893 ps
CPU time 18.76 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:22:02 PM PDT 24
Peak memory 217432 kb
Host smart-0023ee8c-868c-412a-ad57-6732e79f1366
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518278040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.518278040
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2247409602
Short name T5
Test name
Test status
Simulation time 3750589987 ps
CPU time 15.39 seconds
Started Jul 22 07:20:54 PM PDT 24
Finished Jul 22 07:21:37 PM PDT 24
Peak memory 225652 kb
Host smart-97eb047c-2db1-42ca-b93c-6dcd67507ca7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247409602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2247409602
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2624501261
Short name T601
Test name
Test status
Simulation time 7811270693 ps
CPU time 25.24 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:22:09 PM PDT 24
Peak memory 217304 kb
Host smart-cb179726-dcea-4dee-bfe5-da606327ff4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624501261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2624501261
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4232047789
Short name T841
Test name
Test status
Simulation time 716194907 ps
CPU time 8.79 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:25:05 PM PDT 24
Peak memory 217060 kb
Host smart-2e87d137-3b18-4d8c-a536-b056806a0ec0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232047789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
4232047789
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1854920126
Short name T856
Test name
Test status
Simulation time 2414060747 ps
CPU time 74.61 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:26:11 PM PDT 24
Peak memory 268788 kb
Host smart-dd985bc3-6906-4356-ae9f-5c63b47e1f1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854920126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1854920126
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1872627821
Short name T84
Test name
Test status
Simulation time 4579761901 ps
CPU time 12.54 seconds
Started Jul 22 07:24:44 PM PDT 24
Finished Jul 22 07:25:56 PM PDT 24
Peak memory 250324 kb
Host smart-69e6e4d4-d93e-44c4-9d78-08d4ddf31a41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872627821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1872627821
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3009742966
Short name T135
Test name
Test status
Simulation time 60710951 ps
CPU time 2.55 seconds
Started Jul 22 07:21:01 PM PDT 24
Finished Jul 22 07:21:40 PM PDT 24
Peak memory 217844 kb
Host smart-4250ecf9-f22d-4dfd-9c55-2e5531c178e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009742966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3009742966
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3412692222
Short name T641
Test name
Test status
Simulation time 1525196483 ps
CPU time 13.9 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:56 PM PDT 24
Peak memory 217304 kb
Host smart-43ac38d4-6e00-4950-9c9f-b62f9a849fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412692222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3412692222
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.79050181
Short name T79
Test name
Test status
Simulation time 229534109 ps
CPU time 24.27 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:24:16 PM PDT 24
Peak memory 282344 kb
Host smart-a916cc4c-eaf1-4a79-839a-38a266b7eca8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79050181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.79050181
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1850316071
Short name T467
Test name
Test status
Simulation time 2195822984 ps
CPU time 14.65 seconds
Started Jul 22 07:20:52 PM PDT 24
Finished Jul 22 07:21:33 PM PDT 24
Peak memory 225596 kb
Host smart-e5bfa670-b040-4bf9-bbf9-89eacb958ae4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850316071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1850316071
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2011904832
Short name T663
Test name
Test status
Simulation time 488553843 ps
CPU time 8.84 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:24:00 PM PDT 24
Peak memory 225516 kb
Host smart-18fb94fd-e1d4-4c25-88b3-fec73361332b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011904832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
011904832
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.854218492
Short name T219
Test name
Test status
Simulation time 1984100106 ps
CPU time 8.95 seconds
Started Jul 22 07:21:02 PM PDT 24
Finished Jul 22 07:21:47 PM PDT 24
Peak memory 225652 kb
Host smart-4e78046e-9967-4453-a854-5bd0eee3be93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854218492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.854218492
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.305650404
Short name T508
Test name
Test status
Simulation time 180425965 ps
CPU time 2.16 seconds
Started Jul 22 07:21:03 PM PDT 24
Finished Jul 22 07:21:42 PM PDT 24
Peak memory 217236 kb
Host smart-140c8a62-4142-4c02-8659-fa5c70f1b99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305650404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.305650404
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.940627396
Short name T788
Test name
Test status
Simulation time 1334151768 ps
CPU time 25.41 seconds
Started Jul 22 07:21:02 PM PDT 24
Finished Jul 22 07:22:03 PM PDT 24
Peak memory 250572 kb
Host smart-2bd0fe21-d5a9-4d21-a505-b4ab4ff9db55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940627396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.940627396
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3954967041
Short name T709
Test name
Test status
Simulation time 44084525 ps
CPU time 2.88 seconds
Started Jul 22 07:21:02 PM PDT 24
Finished Jul 22 07:21:41 PM PDT 24
Peak memory 221948 kb
Host smart-bf1a9fc8-4877-41b9-b80c-29f3247602a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954967041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3954967041
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1587011109
Short name T812
Test name
Test status
Simulation time 21779678179 ps
CPU time 289.28 seconds
Started Jul 22 07:24:14 PM PDT 24
Finished Jul 22 07:29:45 PM PDT 24
Peak memory 223372 kb
Host smart-586812db-42fc-4aba-b808-df24b17da8c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587011109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1587011109
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2602620408
Short name T816
Test name
Test status
Simulation time 26779877 ps
CPU time 0.85 seconds
Started Jul 22 07:20:59 PM PDT 24
Finished Jul 22 07:21:35 PM PDT 24
Peak memory 211472 kb
Host smart-c6c8717d-4eb3-4c9e-abef-842142345465
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602620408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2602620408
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.124566972
Short name T309
Test name
Test status
Simulation time 24859314 ps
CPU time 1.29 seconds
Started Jul 22 07:25:19 PM PDT 24
Finished Jul 22 07:26:38 PM PDT 24
Peak memory 208600 kb
Host smart-01aa560f-796b-403d-98d9-02defb320aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124566972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.124566972
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2772204063
Short name T14
Test name
Test status
Simulation time 920787533 ps
CPU time 8.46 seconds
Started Jul 22 07:25:24 PM PDT 24
Finished Jul 22 07:26:54 PM PDT 24
Peak memory 225624 kb
Host smart-7ebcaa25-7083-4579-8a43-baf1b26cb7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772204063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2772204063
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3412074815
Short name T705
Test name
Test status
Simulation time 1361514935 ps
CPU time 4.82 seconds
Started Jul 22 07:25:25 PM PDT 24
Finished Jul 22 07:26:51 PM PDT 24
Peak memory 216708 kb
Host smart-42839da2-de9d-42db-9a05-207c8c2bdfca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412074815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3412074815
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3218734679
Short name T411
Test name
Test status
Simulation time 117071540 ps
CPU time 2.01 seconds
Started Jul 22 07:25:20 PM PDT 24
Finished Jul 22 07:26:42 PM PDT 24
Peak memory 217812 kb
Host smart-ee5cf89a-23bc-4dc9-b886-fb784d6d074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218734679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3218734679
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1727644859
Short name T634
Test name
Test status
Simulation time 1556744170 ps
CPU time 16.26 seconds
Started Jul 22 07:25:22 PM PDT 24
Finished Jul 22 07:26:59 PM PDT 24
Peak memory 225588 kb
Host smart-97796c0f-daba-4f5b-bb3b-8947d2799fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727644859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1727644859
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3935160424
Short name T579
Test name
Test status
Simulation time 1500861235 ps
CPU time 10.39 seconds
Started Jul 22 07:25:20 PM PDT 24
Finished Jul 22 07:26:49 PM PDT 24
Peak memory 225568 kb
Host smart-d5573b30-f2fe-45e4-bb1c-10f92ad5d652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935160424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3935160424
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1832452129
Short name T505
Test name
Test status
Simulation time 474252760 ps
CPU time 16.64 seconds
Started Jul 22 07:25:25 PM PDT 24
Finished Jul 22 07:27:03 PM PDT 24
Peak memory 217916 kb
Host smart-9f0e9a99-96f2-44f3-8330-4a8935916af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832452129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1832452129
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.762731524
Short name T613
Test name
Test status
Simulation time 31345963 ps
CPU time 2.69 seconds
Started Jul 22 07:25:18 PM PDT 24
Finished Jul 22 07:26:39 PM PDT 24
Peak memory 223384 kb
Host smart-c3a04367-ffb4-4a9f-bc25-44cd99648268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762731524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.762731524
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.930057767
Short name T92
Test name
Test status
Simulation time 1760505229 ps
CPU time 22.02 seconds
Started Jul 22 07:25:22 PM PDT 24
Finished Jul 22 07:27:05 PM PDT 24
Peak memory 250604 kb
Host smart-b11f7292-abf9-4b62-8738-27a1cfe7ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930057767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.930057767
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3839622689
Short name T855
Test name
Test status
Simulation time 254126128 ps
CPU time 6.53 seconds
Started Jul 22 07:25:18 PM PDT 24
Finished Jul 22 07:26:42 PM PDT 24
Peak memory 250052 kb
Host smart-0bb5072a-840e-44c7-b75a-34aa165c4644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839622689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3839622689
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2971462686
Short name T324
Test name
Test status
Simulation time 3648929151 ps
CPU time 50.91 seconds
Started Jul 22 07:26:32 PM PDT 24
Finished Jul 22 07:28:44 PM PDT 24
Peak memory 225312 kb
Host smart-166268e2-db32-4f00-b58c-78eda8e2af7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971462686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2971462686
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.4057641444
Short name T686
Test name
Test status
Simulation time 21185890099 ps
CPU time 439.43 seconds
Started Jul 22 07:25:20 PM PDT 24
Finished Jul 22 07:33:58 PM PDT 24
Peak memory 421732 kb
Host smart-95553aff-717a-40b5-89e2-f1483e6145fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4057641444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.4057641444
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2862106110
Short name T696
Test name
Test status
Simulation time 33603080 ps
CPU time 1.07 seconds
Started Jul 22 07:25:30 PM PDT 24
Finished Jul 22 07:26:50 PM PDT 24
Peak memory 208568 kb
Host smart-c4782217-154f-4ddd-93fe-493020ebdebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862106110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2862106110
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.953406630
Short name T362
Test name
Test status
Simulation time 1195781414 ps
CPU time 14.04 seconds
Started Jul 22 07:25:29 PM PDT 24
Finished Jul 22 07:27:03 PM PDT 24
Peak memory 217860 kb
Host smart-28e9764c-361b-431c-90e4-f1a60d9928aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953406630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.953406630
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.247742179
Short name T848
Test name
Test status
Simulation time 2112282992 ps
CPU time 6.26 seconds
Started Jul 22 07:25:28 PM PDT 24
Finished Jul 22 07:26:55 PM PDT 24
Peak memory 217452 kb
Host smart-02b30a68-a74e-48db-8fc7-1bba93cd2e14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247742179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.247742179
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3459379905
Short name T712
Test name
Test status
Simulation time 588220300 ps
CPU time 4.09 seconds
Started Jul 22 07:25:32 PM PDT 24
Finished Jul 22 07:26:55 PM PDT 24
Peak memory 217844 kb
Host smart-a90792c9-d3c8-4c4b-af9b-b2d50fc914db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459379905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3459379905
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3392399942
Short name T717
Test name
Test status
Simulation time 293250548 ps
CPU time 11.38 seconds
Started Jul 22 07:25:27 PM PDT 24
Finished Jul 22 07:26:59 PM PDT 24
Peak memory 225644 kb
Host smart-70f4c0f7-077f-47a2-863b-43c8d0e61c7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392399942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3392399942
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.298482549
Short name T668
Test name
Test status
Simulation time 1794660249 ps
CPU time 14.01 seconds
Started Jul 22 07:25:28 PM PDT 24
Finished Jul 22 07:27:02 PM PDT 24
Peak memory 225576 kb
Host smart-827d2cf6-615d-4f6e-95b5-8e41749fc3cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298482549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.298482549
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1579209598
Short name T447
Test name
Test status
Simulation time 529482616 ps
CPU time 11.45 seconds
Started Jul 22 07:25:28 PM PDT 24
Finished Jul 22 07:27:00 PM PDT 24
Peak memory 225564 kb
Host smart-b9fd0722-c47e-4c8e-8634-5e1ba6899bff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579209598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1579209598
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.415125132
Short name T517
Test name
Test status
Simulation time 255476301 ps
CPU time 9.57 seconds
Started Jul 22 07:25:28 PM PDT 24
Finished Jul 22 07:26:57 PM PDT 24
Peak memory 217968 kb
Host smart-02aa2f86-d464-4ef4-bea5-3933a271f4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415125132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.415125132
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.754863912
Short name T196
Test name
Test status
Simulation time 22135519 ps
CPU time 1.45 seconds
Started Jul 22 07:26:24 PM PDT 24
Finished Jul 22 07:27:42 PM PDT 24
Peak memory 216304 kb
Host smart-d315de20-d8a5-43fc-a7ea-654b5dc76a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754863912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.754863912
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1486598377
Short name T211
Test name
Test status
Simulation time 460853439 ps
CPU time 26.23 seconds
Started Jul 22 07:25:27 PM PDT 24
Finished Jul 22 07:27:13 PM PDT 24
Peak memory 250344 kb
Host smart-e793617a-3e07-4e57-aee8-69b43c0b46e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486598377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1486598377
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2396444372
Short name T365
Test name
Test status
Simulation time 284569796 ps
CPU time 7.02 seconds
Started Jul 22 07:25:26 PM PDT 24
Finished Jul 22 07:26:54 PM PDT 24
Peak memory 242404 kb
Host smart-10d1d12e-16a5-4944-b9b7-b7f86c6579e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396444372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2396444372
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3656802091
Short name T3
Test name
Test status
Simulation time 2326950021 ps
CPU time 107.95 seconds
Started Jul 22 07:25:29 PM PDT 24
Finished Jul 22 07:28:37 PM PDT 24
Peak memory 245844 kb
Host smart-aebd9ce1-b894-43de-a912-703d0f3fead0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656802091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3656802091
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.4138143496
Short name T462
Test name
Test status
Simulation time 61831860004 ps
CPU time 371.56 seconds
Started Jul 22 07:25:29 PM PDT 24
Finished Jul 22 07:33:00 PM PDT 24
Peak memory 372664 kb
Host smart-baca0cbc-2f48-49f9-8dc2-b019084365cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4138143496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.4138143496
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2388000554
Short name T363
Test name
Test status
Simulation time 13964364 ps
CPU time 0.86 seconds
Started Jul 22 07:25:47 PM PDT 24
Finished Jul 22 07:27:07 PM PDT 24
Peak memory 211408 kb
Host smart-2160c801-2b5e-4db7-8bdf-dbb91bada9a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388000554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2388000554
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2705342608
Short name T643
Test name
Test status
Simulation time 29676599 ps
CPU time 0.87 seconds
Started Jul 22 07:25:37 PM PDT 24
Finished Jul 22 07:26:58 PM PDT 24
Peak memory 208484 kb
Host smart-05309453-ddba-4b3a-b6ee-9abd5b148eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705342608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2705342608
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1252566764
Short name T334
Test name
Test status
Simulation time 299878347 ps
CPU time 12.81 seconds
Started Jul 22 07:25:35 PM PDT 24
Finished Jul 22 07:27:08 PM PDT 24
Peak memory 217844 kb
Host smart-d798a6e3-fce2-4821-8b95-ecca4299e998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252566764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1252566764
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1493939423
Short name T585
Test name
Test status
Simulation time 2175660310 ps
CPU time 8.99 seconds
Started Jul 22 07:25:37 PM PDT 24
Finished Jul 22 07:27:07 PM PDT 24
Peak memory 217332 kb
Host smart-daa44ecb-37fa-4ae0-bbd3-1886483ff14d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493939423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1493939423
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3483647702
Short name T512
Test name
Test status
Simulation time 306314304 ps
CPU time 3.67 seconds
Started Jul 22 07:27:27 PM PDT 24
Finished Jul 22 07:28:41 PM PDT 24
Peak memory 222220 kb
Host smart-a4a3237d-c50c-4811-b1f1-d66db5e6c990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483647702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3483647702
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.741403009
Short name T683
Test name
Test status
Simulation time 439557681 ps
CPU time 14.12 seconds
Started Jul 22 07:25:36 PM PDT 24
Finished Jul 22 07:27:10 PM PDT 24
Peak memory 225572 kb
Host smart-654e5461-3f4e-48c0-b6a2-71a7aaa4126e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741403009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.741403009
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1260297827
Short name T798
Test name
Test status
Simulation time 917605842 ps
CPU time 6.95 seconds
Started Jul 22 07:25:36 PM PDT 24
Finished Jul 22 07:27:03 PM PDT 24
Peak memory 225548 kb
Host smart-3e73c01e-63f6-4693-8e0a-1784e636d090
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260297827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1260297827
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1382057612
Short name T701
Test name
Test status
Simulation time 305994312 ps
CPU time 9.02 seconds
Started Jul 22 07:25:36 PM PDT 24
Finished Jul 22 07:27:05 PM PDT 24
Peak memory 217924 kb
Host smart-a1d92fa5-4ea2-45df-81d4-1ac76d7c88e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382057612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1382057612
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3101631396
Short name T538
Test name
Test status
Simulation time 152649900 ps
CPU time 2.43 seconds
Started Jul 22 07:25:27 PM PDT 24
Finished Jul 22 07:26:50 PM PDT 24
Peak memory 213696 kb
Host smart-18b698d9-f606-4426-8994-79e90806efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101631396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3101631396
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2562933557
Short name T201
Test name
Test status
Simulation time 469644788 ps
CPU time 34.4 seconds
Started Jul 22 07:25:38 PM PDT 24
Finished Jul 22 07:27:33 PM PDT 24
Peak memory 250668 kb
Host smart-a4d4213f-bab9-4e8f-90ba-0a04808df598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562933557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2562933557
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.713373318
Short name T741
Test name
Test status
Simulation time 80693830 ps
CPU time 7.8 seconds
Started Jul 22 07:25:37 PM PDT 24
Finished Jul 22 07:27:05 PM PDT 24
Peak memory 248288 kb
Host smart-0929b58e-981a-40f1-8dc7-9811eb71959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713373318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.713373318
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1754471992
Short name T356
Test name
Test status
Simulation time 11703918757 ps
CPU time 119.52 seconds
Started Jul 22 07:27:27 PM PDT 24
Finished Jul 22 07:30:37 PM PDT 24
Peak memory 283176 kb
Host smart-82133fd5-8ea3-43ca-8f3d-e0f72fc3f571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754471992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1754471992
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.771912480
Short name T25
Test name
Test status
Simulation time 43571474788 ps
CPU time 4020.66 seconds
Started Jul 22 07:25:38 PM PDT 24
Finished Jul 22 08:34:00 PM PDT 24
Peak memory 873396 kb
Host smart-54daef54-22d0-4479-a4aa-55cf0727a5db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=771912480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.771912480
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1136309797
Short name T420
Test name
Test status
Simulation time 15814421 ps
CPU time 0.94 seconds
Started Jul 22 07:25:44 PM PDT 24
Finished Jul 22 07:27:06 PM PDT 24
Peak memory 211484 kb
Host smart-525231e0-a6ce-4251-a1d9-56c2738810b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136309797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1136309797
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3830527433
Short name T772
Test name
Test status
Simulation time 75731567 ps
CPU time 0.84 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:27:08 PM PDT 24
Peak memory 208336 kb
Host smart-a5843f95-0e50-4e38-9ee6-1cd5ca50811c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830527433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3830527433
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1298145650
Short name T240
Test name
Test status
Simulation time 2358065696 ps
CPU time 14.19 seconds
Started Jul 22 07:25:38 PM PDT 24
Finished Jul 22 07:27:13 PM PDT 24
Peak memory 218572 kb
Host smart-80d7a1fc-11bd-4b4e-adf2-dfb3da5009a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298145650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1298145650
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2676544425
Short name T387
Test name
Test status
Simulation time 108069194 ps
CPU time 2.18 seconds
Started Jul 22 07:25:39 PM PDT 24
Finished Jul 22 07:27:01 PM PDT 24
Peak memory 216636 kb
Host smart-7fe71c5c-7db7-4d3a-87f4-3d401b0503d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676544425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2676544425
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.17189694
Short name T630
Test name
Test status
Simulation time 375884148 ps
CPU time 3.22 seconds
Started Jul 22 07:25:36 PM PDT 24
Finished Jul 22 07:26:59 PM PDT 24
Peak memory 221804 kb
Host smart-9bad4387-a9eb-4926-a0f0-23aafc888ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17189694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.17189694
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3267168308
Short name T352
Test name
Test status
Simulation time 6788044780 ps
CPU time 19.83 seconds
Started Jul 22 07:25:36 PM PDT 24
Finished Jul 22 07:27:15 PM PDT 24
Peak memory 219132 kb
Host smart-8802c9a9-f671-4505-b95f-990940934fa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267168308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3267168308
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3684573853
Short name T426
Test name
Test status
Simulation time 318820030 ps
CPU time 12.08 seconds
Started Jul 22 07:27:08 PM PDT 24
Finished Jul 22 07:28:34 PM PDT 24
Peak memory 225584 kb
Host smart-f3d4e698-197e-4ac4-b039-38019a0d2a7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684573853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3684573853
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.282732620
Short name T260
Test name
Test status
Simulation time 198548836 ps
CPU time 8.39 seconds
Started Jul 22 07:25:42 PM PDT 24
Finished Jul 22 07:27:11 PM PDT 24
Peak memory 217792 kb
Host smart-880c67fd-d3f9-43ef-a08b-3610de042d53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282732620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.282732620
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2996995753
Short name T543
Test name
Test status
Simulation time 1488147473 ps
CPU time 9.55 seconds
Started Jul 22 07:25:34 PM PDT 24
Finished Jul 22 07:27:04 PM PDT 24
Peak memory 217800 kb
Host smart-6f694600-1c06-452b-b125-f401492f38d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996995753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2996995753
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3316897268
Short name T692
Test name
Test status
Simulation time 167260255 ps
CPU time 3.58 seconds
Started Jul 22 07:25:44 PM PDT 24
Finished Jul 22 07:27:08 PM PDT 24
Peak memory 214668 kb
Host smart-120de3a3-09fd-4c77-9f4f-ea14b5978ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316897268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3316897268
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2970329587
Short name T368
Test name
Test status
Simulation time 1012768586 ps
CPU time 27.93 seconds
Started Jul 22 07:25:36 PM PDT 24
Finished Jul 22 07:27:24 PM PDT 24
Peak memory 250504 kb
Host smart-ff8ee32a-9eaf-40ad-8111-15b59e863d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970329587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2970329587
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2501946261
Short name T850
Test name
Test status
Simulation time 93413354 ps
CPU time 10.47 seconds
Started Jul 22 07:25:35 PM PDT 24
Finished Jul 22 07:27:06 PM PDT 24
Peak memory 250572 kb
Host smart-4bf00f18-74a5-45ef-b67b-bcb2644dde49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501946261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2501946261
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1524991934
Short name T847
Test name
Test status
Simulation time 19171661015 ps
CPU time 188.96 seconds
Started Jul 22 07:25:47 PM PDT 24
Finished Jul 22 07:30:15 PM PDT 24
Peak memory 272380 kb
Host smart-ba149a34-d19b-4d6d-9772-104342ca47d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524991934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1524991934
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1103306654
Short name T131
Test name
Test status
Simulation time 114473855781 ps
CPU time 539.88 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:36:07 PM PDT 24
Peak memory 421656 kb
Host smart-64a4e81c-5bf6-4c20-ba69-e133d37a01d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1103306654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1103306654
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3094669810
Short name T797
Test name
Test status
Simulation time 18370269 ps
CPU time 0.97 seconds
Started Jul 22 07:25:37 PM PDT 24
Finished Jul 22 07:26:59 PM PDT 24
Peak memory 212516 kb
Host smart-6b0c5897-f4d0-4802-83a9-51adc94d1f31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094669810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3094669810
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3398415943
Short name T156
Test name
Test status
Simulation time 117690670 ps
CPU time 1.39 seconds
Started Jul 22 07:25:46 PM PDT 24
Finished Jul 22 07:27:07 PM PDT 24
Peak memory 208612 kb
Host smart-a66b7d84-488e-4bba-9b74-ec69de9e4d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398415943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3398415943
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.296130571
Short name T347
Test name
Test status
Simulation time 337836816 ps
CPU time 16.31 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:27:23 PM PDT 24
Peak memory 217780 kb
Host smart-e988a1fe-de5b-480a-9590-6be84308d285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296130571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.296130571
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3370236315
Short name T519
Test name
Test status
Simulation time 699884564 ps
CPU time 3.28 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:27:10 PM PDT 24
Peak memory 217224 kb
Host smart-f1853b64-cd12-4640-9bc2-bc483261c660
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370236315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3370236315
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3823880542
Short name T383
Test name
Test status
Simulation time 32904277 ps
CPU time 2.1 seconds
Started Jul 22 07:25:48 PM PDT 24
Finished Jul 22 07:27:09 PM PDT 24
Peak memory 222000 kb
Host smart-a626f6b8-0775-4723-8b82-1366f9106327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823880542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3823880542
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4155199824
Short name T460
Test name
Test status
Simulation time 1833915523 ps
CPU time 12.65 seconds
Started Jul 22 07:26:15 PM PDT 24
Finished Jul 22 07:27:46 PM PDT 24
Peak memory 225612 kb
Host smart-ed506d76-f236-46e1-8497-e9f63ba84e5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155199824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4155199824
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2049488957
Short name T353
Test name
Test status
Simulation time 1889190054 ps
CPU time 12.69 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:27:20 PM PDT 24
Peak memory 225584 kb
Host smart-59750abe-3efd-43b4-9589-b47b92643f2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049488957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2049488957
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1214006190
Short name T612
Test name
Test status
Simulation time 1884194667 ps
CPU time 10.1 seconds
Started Jul 22 07:25:50 PM PDT 24
Finished Jul 22 07:27:18 PM PDT 24
Peak memory 217920 kb
Host smart-e87b75bf-0235-4d5b-8c80-8725e28bb757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214006190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1214006190
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2423457076
Short name T827
Test name
Test status
Simulation time 31321190 ps
CPU time 1.57 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:27:09 PM PDT 24
Peak memory 213384 kb
Host smart-c0115992-4a5d-4723-8586-89f8a352ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423457076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2423457076
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2684292785
Short name T223
Test name
Test status
Simulation time 154624088 ps
CPU time 13.25 seconds
Started Jul 22 07:26:57 PM PDT 24
Finished Jul 22 07:28:30 PM PDT 24
Peak memory 250584 kb
Host smart-01564f2c-1639-4bc8-a56f-0b5552a815ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684292785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2684292785
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3523276536
Short name T775
Test name
Test status
Simulation time 175514893 ps
CPU time 6.73 seconds
Started Jul 22 07:25:48 PM PDT 24
Finished Jul 22 07:27:13 PM PDT 24
Peak memory 246888 kb
Host smart-4736c346-cc4f-4e61-a7b3-b0d4d97c026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523276536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3523276536
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3312418301
Short name T530
Test name
Test status
Simulation time 43409091680 ps
CPU time 320.4 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:32:27 PM PDT 24
Peak memory 269428 kb
Host smart-eb61928c-28fa-4af0-87be-ab711356f19a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312418301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3312418301
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3523604153
Short name T674
Test name
Test status
Simulation time 20655510 ps
CPU time 0.87 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:27:08 PM PDT 24
Peak memory 211444 kb
Host smart-37442974-c6a8-4795-8002-d2f17912ed72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523604153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3523604153
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.736052795
Short name T272
Test name
Test status
Simulation time 20335405 ps
CPU time 1.14 seconds
Started Jul 22 07:25:56 PM PDT 24
Finished Jul 22 07:27:14 PM PDT 24
Peak memory 208480 kb
Host smart-9fc23849-26cd-404a-abf9-04e609bdd300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736052795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.736052795
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2516748744
Short name T468
Test name
Test status
Simulation time 2187144693 ps
CPU time 8.48 seconds
Started Jul 22 07:27:18 PM PDT 24
Finished Jul 22 07:28:39 PM PDT 24
Peak memory 217920 kb
Host smart-45de93a8-098f-4ba1-a9ef-edf529682646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516748744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2516748744
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1467558820
Short name T7
Test name
Test status
Simulation time 111127820 ps
CPU time 3.34 seconds
Started Jul 22 07:25:56 PM PDT 24
Finished Jul 22 07:27:17 PM PDT 24
Peak memory 216740 kb
Host smart-0d96044a-6b0e-4fd4-9e60-3e45dc947a86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467558820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1467558820
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2079811623
Short name T210
Test name
Test status
Simulation time 312293268 ps
CPU time 3.3 seconds
Started Jul 22 07:25:50 PM PDT 24
Finished Jul 22 07:27:11 PM PDT 24
Peak memory 217840 kb
Host smart-1a621ac6-2a72-4b29-834a-298a0961a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079811623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2079811623
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3621639692
Short name T422
Test name
Test status
Simulation time 331493736 ps
CPU time 15.79 seconds
Started Jul 22 07:27:18 PM PDT 24
Finished Jul 22 07:28:47 PM PDT 24
Peak memory 218496 kb
Host smart-840128c5-a4e2-48c4-b81b-d58bb63235cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621639692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3621639692
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.443808223
Short name T747
Test name
Test status
Simulation time 184506909 ps
CPU time 7.34 seconds
Started Jul 22 07:26:06 PM PDT 24
Finished Jul 22 07:27:31 PM PDT 24
Peak memory 225364 kb
Host smart-5205350d-06a3-46de-9d15-b3abefd7448d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443808223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.443808223
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3942693412
Short name T864
Test name
Test status
Simulation time 432915869 ps
CPU time 6.05 seconds
Started Jul 22 07:27:18 PM PDT 24
Finished Jul 22 07:28:37 PM PDT 24
Peak memory 224576 kb
Host smart-cb353904-ed18-42b6-a3f1-96a0809cf9d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942693412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3942693412
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1681397604
Short name T148
Test name
Test status
Simulation time 1211278520 ps
CPU time 8.02 seconds
Started Jul 22 07:27:18 PM PDT 24
Finished Jul 22 07:28:40 PM PDT 24
Peak memory 217920 kb
Host smart-65a1f79c-e2dc-4add-8bd3-14c584cfa7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681397604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1681397604
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.896833991
Short name T312
Test name
Test status
Simulation time 148788887 ps
CPU time 1.88 seconds
Started Jul 22 07:25:47 PM PDT 24
Finished Jul 22 07:27:08 PM PDT 24
Peak memory 213788 kb
Host smart-16f017ab-3f7a-4ae6-bd76-9e0297f79282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896833991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.896833991
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2615809277
Short name T418
Test name
Test status
Simulation time 159291222 ps
CPU time 20.77 seconds
Started Jul 22 07:25:45 PM PDT 24
Finished Jul 22 07:27:27 PM PDT 24
Peak memory 250672 kb
Host smart-66268d81-6294-481d-a97b-61b1e4dd3ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615809277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2615809277
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4240234638
Short name T642
Test name
Test status
Simulation time 334771840 ps
CPU time 8.77 seconds
Started Jul 22 07:25:49 PM PDT 24
Finished Jul 22 07:27:16 PM PDT 24
Peak memory 250524 kb
Host smart-14029416-6596-4f5a-a99d-1255564dc341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240234638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4240234638
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.257001220
Short name T863
Test name
Test status
Simulation time 15444258 ps
CPU time 0.88 seconds
Started Jul 22 07:26:43 PM PDT 24
Finished Jul 22 07:27:59 PM PDT 24
Peak memory 211424 kb
Host smart-e3ee539a-7642-4d42-8fb4-be3ed8396e61
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257001220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.257001220
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3516313889
Short name T404
Test name
Test status
Simulation time 61672395 ps
CPU time 0.94 seconds
Started Jul 22 07:27:49 PM PDT 24
Finished Jul 22 07:28:54 PM PDT 24
Peak memory 208448 kb
Host smart-fb575f60-370a-417f-9e9f-560834d65c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516313889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3516313889
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2615579390
Short name T298
Test name
Test status
Simulation time 572733485 ps
CPU time 11.25 seconds
Started Jul 22 07:25:55 PM PDT 24
Finished Jul 22 07:27:23 PM PDT 24
Peak memory 217992 kb
Host smart-a8427670-f4ad-4bdd-bffc-e117ad145917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615579390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2615579390
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3158085888
Short name T325
Test name
Test status
Simulation time 176033504 ps
CPU time 5.25 seconds
Started Jul 22 07:26:06 PM PDT 24
Finished Jul 22 07:27:29 PM PDT 24
Peak memory 217264 kb
Host smart-1d50dcf5-a277-4f51-a44b-c3697a6725a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158085888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3158085888
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3529458012
Short name T748
Test name
Test status
Simulation time 44105576 ps
CPU time 2.27 seconds
Started Jul 22 07:25:56 PM PDT 24
Finished Jul 22 07:27:15 PM PDT 24
Peak memory 221804 kb
Host smart-aba08120-3073-48cf-bc98-edb168c14f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529458012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3529458012
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3995959923
Short name T619
Test name
Test status
Simulation time 364863263 ps
CPU time 12.61 seconds
Started Jul 22 07:25:57 PM PDT 24
Finished Jul 22 07:27:27 PM PDT 24
Peak memory 225324 kb
Host smart-337fe5e3-50b4-482c-bbe3-8d0c5c6125fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995959923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3995959923
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3101739624
Short name T640
Test name
Test status
Simulation time 3264372578 ps
CPU time 12.12 seconds
Started Jul 22 07:25:56 PM PDT 24
Finished Jul 22 07:27:26 PM PDT 24
Peak memory 225656 kb
Host smart-518f218d-f208-4804-968c-c6ec3fd45477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101739624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3101739624
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2132391400
Short name T817
Test name
Test status
Simulation time 686259133 ps
CPU time 14.22 seconds
Started Jul 22 07:25:55 PM PDT 24
Finished Jul 22 07:27:26 PM PDT 24
Peak memory 225584 kb
Host smart-77831526-6f8f-4db0-8ab1-dc2959b30915
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132391400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2132391400
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4152144898
Short name T490
Test name
Test status
Simulation time 294674218 ps
CPU time 7.85 seconds
Started Jul 22 07:25:56 PM PDT 24
Finished Jul 22 07:27:21 PM PDT 24
Peak memory 217940 kb
Host smart-b0db3376-a987-472d-9989-95d16a470820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152144898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4152144898
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.728076830
Short name T837
Test name
Test status
Simulation time 39405926 ps
CPU time 2.6 seconds
Started Jul 22 07:26:06 PM PDT 24
Finished Jul 22 07:27:26 PM PDT 24
Peak memory 214464 kb
Host smart-f315ea4e-68ed-431d-9e07-f1cf0af91552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728076830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.728076830
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.92632849
Short name T427
Test name
Test status
Simulation time 472478725 ps
CPU time 31.9 seconds
Started Jul 22 07:25:58 PM PDT 24
Finished Jul 22 07:27:47 PM PDT 24
Peak memory 247012 kb
Host smart-bddb01c5-28d4-4636-bd06-8c4afbe911f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92632849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.92632849
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4179946430
Short name T793
Test name
Test status
Simulation time 115846138 ps
CPU time 7.97 seconds
Started Jul 22 07:26:06 PM PDT 24
Finished Jul 22 07:27:31 PM PDT 24
Peak memory 250628 kb
Host smart-3e31c650-ce4a-4983-ac06-97639cddbb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179946430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4179946430
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3680434806
Short name T345
Test name
Test status
Simulation time 9568025004 ps
CPU time 89.16 seconds
Started Jul 22 07:26:09 PM PDT 24
Finished Jul 22 07:28:57 PM PDT 24
Peak memory 250700 kb
Host smart-edbdc7e6-7315-49a8-a8c5-a806a6f40971
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680434806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3680434806
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2272910248
Short name T208
Test name
Test status
Simulation time 13625625 ps
CPU time 1.03 seconds
Started Jul 22 07:25:59 PM PDT 24
Finished Jul 22 07:27:17 PM PDT 24
Peak memory 211512 kb
Host smart-9c30b27e-cd98-472c-b84d-81ac55dc490b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272910248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2272910248
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3517220788
Short name T566
Test name
Test status
Simulation time 26325318 ps
CPU time 1.01 seconds
Started Jul 22 07:26:18 PM PDT 24
Finished Jul 22 07:27:37 PM PDT 24
Peak memory 208556 kb
Host smart-73cf716c-4bc4-4ec1-935b-fbb9a76646b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517220788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3517220788
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.484060830
Short name T780
Test name
Test status
Simulation time 724972265 ps
CPU time 20.93 seconds
Started Jul 22 07:26:09 PM PDT 24
Finished Jul 22 07:27:48 PM PDT 24
Peak memory 225616 kb
Host smart-e522bbc8-55aa-4021-bbf9-8da7bf89d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484060830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.484060830
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.4229906923
Short name T495
Test name
Test status
Simulation time 1249789319 ps
CPU time 9.49 seconds
Started Jul 22 07:26:17 PM PDT 24
Finished Jul 22 07:27:45 PM PDT 24
Peak memory 217292 kb
Host smart-768809a9-d73f-4a98-b0aa-077e06dea7a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229906923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.4229906923
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2561843874
Short name T142
Test name
Test status
Simulation time 189345435 ps
CPU time 3.06 seconds
Started Jul 22 07:26:09 PM PDT 24
Finished Jul 22 07:27:30 PM PDT 24
Peak memory 217856 kb
Host smart-4182e717-128a-41af-9abe-d9ef805fd090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561843874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2561843874
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2969380479
Short name T825
Test name
Test status
Simulation time 289480650 ps
CPU time 9.58 seconds
Started Jul 22 07:26:17 PM PDT 24
Finished Jul 22 07:27:46 PM PDT 24
Peak memory 218588 kb
Host smart-ea061a6d-dba4-4f83-ad50-6cf8dd7bb882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969380479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2969380479
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.905410820
Short name T230
Test name
Test status
Simulation time 8826791673 ps
CPU time 17.39 seconds
Started Jul 22 07:26:32 PM PDT 24
Finished Jul 22 07:28:11 PM PDT 24
Peak memory 225628 kb
Host smart-03855944-e46a-420f-adfa-7a063100f73b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905410820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.905410820
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1173346707
Short name T614
Test name
Test status
Simulation time 2528534397 ps
CPU time 9.41 seconds
Started Jul 22 07:26:11 PM PDT 24
Finished Jul 22 07:27:39 PM PDT 24
Peak memory 225580 kb
Host smart-c23c4e53-daa5-45b9-beee-79ab1d8d3fa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173346707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1173346707
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3614559942
Short name T831
Test name
Test status
Simulation time 413698264 ps
CPU time 8.2 seconds
Started Jul 22 07:26:09 PM PDT 24
Finished Jul 22 07:27:36 PM PDT 24
Peak memory 224812 kb
Host smart-b74966ea-018e-4c90-b1e3-1c11666c8f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614559942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3614559942
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2639266176
Short name T604
Test name
Test status
Simulation time 87051728 ps
CPU time 1.59 seconds
Started Jul 22 07:26:10 PM PDT 24
Finished Jul 22 07:27:30 PM PDT 24
Peak memory 217268 kb
Host smart-19628768-ef61-491c-a2fc-61fd20b60327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639266176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2639266176
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.4127331225
Short name T421
Test name
Test status
Simulation time 483233532 ps
CPU time 32.34 seconds
Started Jul 22 07:26:10 PM PDT 24
Finished Jul 22 07:28:02 PM PDT 24
Peak memory 250604 kb
Host smart-d5c7eb8b-ff98-422b-8bc3-77032973128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127331225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.4127331225
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.4288441846
Short name T15
Test name
Test status
Simulation time 142161182 ps
CPU time 8.91 seconds
Started Jul 22 07:26:17 PM PDT 24
Finished Jul 22 07:27:45 PM PDT 24
Peak memory 245996 kb
Host smart-56ca179d-7ea4-475c-8e6a-d41ba7195f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288441846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4288441846
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.503916744
Short name T307
Test name
Test status
Simulation time 20353830039 ps
CPU time 44.54 seconds
Started Jul 22 07:26:18 PM PDT 24
Finished Jul 22 07:28:21 PM PDT 24
Peak memory 267064 kb
Host smart-54983186-c3bc-4e15-a708-5c1194af2345
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503916744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.503916744
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3088667962
Short name T647
Test name
Test status
Simulation time 19348711 ps
CPU time 0.82 seconds
Started Jul 22 07:26:10 PM PDT 24
Finished Jul 22 07:27:29 PM PDT 24
Peak memory 211540 kb
Host smart-e1077052-88f9-4207-ae0a-c8bd276254ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088667962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3088667962
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1645435541
Short name T652
Test name
Test status
Simulation time 19318919 ps
CPU time 1.11 seconds
Started Jul 22 07:26:22 PM PDT 24
Finished Jul 22 07:27:41 PM PDT 24
Peak memory 208560 kb
Host smart-1798711e-0b35-44e6-bf08-802969f10dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645435541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1645435541
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.4228968250
Short name T246
Test name
Test status
Simulation time 246376612 ps
CPU time 10.63 seconds
Started Jul 22 07:26:21 PM PDT 24
Finished Jul 22 07:27:49 PM PDT 24
Peak memory 225664 kb
Host smart-b91ef179-44c0-428d-a160-39a40c3a1ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228968250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4228968250
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2531511953
Short name T323
Test name
Test status
Simulation time 127580080 ps
CPU time 4.1 seconds
Started Jul 22 07:26:18 PM PDT 24
Finished Jul 22 07:27:40 PM PDT 24
Peak memory 217180 kb
Host smart-1467acbe-29fe-42b8-abef-240c8f7fdf5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531511953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2531511953
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3941079611
Short name T759
Test name
Test status
Simulation time 78288701 ps
CPU time 3.54 seconds
Started Jul 22 07:26:19 PM PDT 24
Finished Jul 22 07:27:42 PM PDT 24
Peak memory 217856 kb
Host smart-a13579ca-d253-470d-a56b-f2232f3c0db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941079611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3941079611
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2768628142
Short name T475
Test name
Test status
Simulation time 383048036 ps
CPU time 11.29 seconds
Started Jul 22 07:26:18 PM PDT 24
Finished Jul 22 07:27:48 PM PDT 24
Peak memory 218520 kb
Host smart-7aff79cc-8f8e-4db8-a26f-7d891fc54cb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768628142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2768628142
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3570404642
Short name T416
Test name
Test status
Simulation time 1938565794 ps
CPU time 19.61 seconds
Started Jul 22 07:26:19 PM PDT 24
Finished Jul 22 07:27:58 PM PDT 24
Peak memory 225576 kb
Host smart-75653818-3318-48ed-a206-e24303a3108f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570404642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3570404642
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2444564782
Short name T204
Test name
Test status
Simulation time 500173316 ps
CPU time 9.66 seconds
Started Jul 22 07:26:20 PM PDT 24
Finished Jul 22 07:27:48 PM PDT 24
Peak memory 225576 kb
Host smart-940094d2-0841-4c64-b8ed-e7b7b5ac7a35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444564782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2444564782
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1794559814
Short name T50
Test name
Test status
Simulation time 1409438742 ps
CPU time 9.35 seconds
Started Jul 22 07:26:22 PM PDT 24
Finished Jul 22 07:27:49 PM PDT 24
Peak memory 217924 kb
Host smart-95d48674-16b5-4ae1-af8c-6293dcf7ecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794559814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1794559814
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.868573507
Short name T335
Test name
Test status
Simulation time 110368693 ps
CPU time 2.42 seconds
Started Jul 22 07:26:20 PM PDT 24
Finished Jul 22 07:27:41 PM PDT 24
Peak memory 214000 kb
Host smart-9bb19569-f6b4-477c-8e52-5f9ab6880da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868573507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.868573507
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3180188096
Short name T299
Test name
Test status
Simulation time 638306897 ps
CPU time 31.44 seconds
Started Jul 22 07:26:19 PM PDT 24
Finished Jul 22 07:28:09 PM PDT 24
Peak memory 250740 kb
Host smart-3633d227-13a1-45db-ada0-c595c48fbab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180188096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3180188096
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2533405026
Short name T589
Test name
Test status
Simulation time 375071315 ps
CPU time 9.15 seconds
Started Jul 22 07:26:18 PM PDT 24
Finished Jul 22 07:27:45 PM PDT 24
Peak memory 250660 kb
Host smart-c09bc924-a7b9-46b4-af4f-5fa2bd182555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533405026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2533405026
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2680971782
Short name T737
Test name
Test status
Simulation time 5968356918 ps
CPU time 182.15 seconds
Started Jul 22 07:26:20 PM PDT 24
Finished Jul 22 07:30:41 PM PDT 24
Peak memory 250796 kb
Host smart-05261558-f526-4837-a8e0-397d3139b0ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680971782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2680971782
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2614273630
Short name T469
Test name
Test status
Simulation time 66513573167 ps
CPU time 461.45 seconds
Started Jul 22 07:26:19 PM PDT 24
Finished Jul 22 07:35:19 PM PDT 24
Peak memory 404484 kb
Host smart-414983d7-43d1-4040-b014-ad1bca6aa491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2614273630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2614273630
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2281469262
Short name T239
Test name
Test status
Simulation time 36996133 ps
CPU time 0.85 seconds
Started Jul 22 07:26:19 PM PDT 24
Finished Jul 22 07:27:38 PM PDT 24
Peak memory 211484 kb
Host smart-3cf9f33d-76fb-48b5-b61a-072609dc9560
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281469262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2281469262
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1928554542
Short name T472
Test name
Test status
Simulation time 166125647 ps
CPU time 1.04 seconds
Started Jul 22 07:26:27 PM PDT 24
Finished Jul 22 07:27:48 PM PDT 24
Peak memory 208496 kb
Host smart-67b703bd-397d-4cd5-9199-a534e65e9974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928554542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1928554542
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1667604956
Short name T729
Test name
Test status
Simulation time 2706648580 ps
CPU time 13.4 seconds
Started Jul 22 07:26:18 PM PDT 24
Finished Jul 22 07:27:50 PM PDT 24
Peak memory 225752 kb
Host smart-df9d53d5-41ab-4ddd-851a-ba86f0139943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667604956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1667604956
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1133295876
Short name T577
Test name
Test status
Simulation time 1401369861 ps
CPU time 5.02 seconds
Started Jul 22 07:26:27 PM PDT 24
Finished Jul 22 07:27:51 PM PDT 24
Peak memory 216876 kb
Host smart-3416f6c3-87df-4972-bb63-9121b9c46334
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133295876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1133295876
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.647338878
Short name T622
Test name
Test status
Simulation time 92200199 ps
CPU time 3 seconds
Started Jul 22 07:26:17 PM PDT 24
Finished Jul 22 07:27:39 PM PDT 24
Peak memory 217824 kb
Host smart-fa8e754b-0481-407d-8769-332ea5ed2571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647338878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.647338878
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1559358799
Short name T704
Test name
Test status
Simulation time 636070287 ps
CPU time 12.72 seconds
Started Jul 22 07:26:29 PM PDT 24
Finished Jul 22 07:28:06 PM PDT 24
Peak memory 225644 kb
Host smart-16b15506-bb35-43e1-9f25-e9cee2adfb7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559358799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1559358799
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3441082999
Short name T470
Test name
Test status
Simulation time 1682240576 ps
CPU time 7.63 seconds
Started Jul 22 07:26:28 PM PDT 24
Finished Jul 22 07:28:01 PM PDT 24
Peak memory 225504 kb
Host smart-3a744d39-143a-4ba9-b6f4-2a451ed6d1ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441082999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3441082999
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2061003976
Short name T251
Test name
Test status
Simulation time 299218187 ps
CPU time 8.1 seconds
Started Jul 22 07:27:02 PM PDT 24
Finished Jul 22 07:28:27 PM PDT 24
Peak memory 225588 kb
Host smart-4ddf25db-e4d7-4b4c-a07f-6095dec904c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061003976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2061003976
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2328870343
Short name T859
Test name
Test status
Simulation time 300383264 ps
CPU time 9.65 seconds
Started Jul 22 07:26:28 PM PDT 24
Finished Jul 22 07:27:59 PM PDT 24
Peak memory 217920 kb
Host smart-df73f74a-a078-47ca-8e67-4f653f2d25c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328870343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2328870343
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2697083219
Short name T525
Test name
Test status
Simulation time 29422437 ps
CPU time 1.44 seconds
Started Jul 22 07:26:20 PM PDT 24
Finished Jul 22 07:27:40 PM PDT 24
Peak memory 213304 kb
Host smart-702c8d0d-a9f4-49c7-a492-71a974694032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697083219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2697083219
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2261118742
Short name T415
Test name
Test status
Simulation time 237735109 ps
CPU time 29.63 seconds
Started Jul 22 07:26:20 PM PDT 24
Finished Jul 22 07:28:08 PM PDT 24
Peak memory 250592 kb
Host smart-137226f1-abce-4abe-9b53-9e8a2a783f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261118742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2261118742
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3117564754
Short name T765
Test name
Test status
Simulation time 258589177 ps
CPU time 4.31 seconds
Started Jul 22 07:26:19 PM PDT 24
Finished Jul 22 07:27:42 PM PDT 24
Peak memory 222116 kb
Host smart-928da95f-2c2e-463d-88c4-27c5aa3fe4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117564754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3117564754
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3170131694
Short name T423
Test name
Test status
Simulation time 645625677 ps
CPU time 14.6 seconds
Started Jul 22 07:27:49 PM PDT 24
Finished Jul 22 07:29:07 PM PDT 24
Peak memory 218396 kb
Host smart-abc0201c-c1ff-4fef-adfa-52aacef54ae9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170131694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3170131694
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2813843846
Short name T670
Test name
Test status
Simulation time 19656056 ps
CPU time 0.98 seconds
Started Jul 22 07:26:21 PM PDT 24
Finished Jul 22 07:27:40 PM PDT 24
Peak memory 211472 kb
Host smart-f77e6f61-3183-404a-be69-2aba1173ca9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813843846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2813843846
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3458343197
Short name T627
Test name
Test status
Simulation time 73971575 ps
CPU time 0.99 seconds
Started Jul 22 07:21:28 PM PDT 24
Finished Jul 22 07:22:09 PM PDT 24
Peak memory 208468 kb
Host smart-fee63123-d4c4-4bac-994b-4e50d2342cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458343197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3458343197
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2980835834
Short name T520
Test name
Test status
Simulation time 24697825 ps
CPU time 0.79 seconds
Started Jul 22 07:21:18 PM PDT 24
Finished Jul 22 07:21:59 PM PDT 24
Peak memory 208244 kb
Host smart-edabc395-4df4-4921-b537-6c0d7c3a87f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980835834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2980835834
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.319422439
Short name T758
Test name
Test status
Simulation time 274515032 ps
CPU time 14.7 seconds
Started Jul 22 07:21:07 PM PDT 24
Finished Jul 22 07:22:01 PM PDT 24
Peak memory 225656 kb
Host smart-dfe9d286-252e-4feb-bb90-95c7deb6d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319422439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.319422439
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.559635542
Short name T409
Test name
Test status
Simulation time 451179728 ps
CPU time 1.55 seconds
Started Jul 22 07:21:08 PM PDT 24
Finished Jul 22 07:21:49 PM PDT 24
Peak memory 217208 kb
Host smart-ce08bc1f-49a7-49aa-bc63-5ffd6202ac9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559635542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.559635542
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3277439109
Short name T289
Test name
Test status
Simulation time 4491633246 ps
CPU time 64.15 seconds
Started Jul 22 07:21:15 PM PDT 24
Finished Jul 22 07:23:01 PM PDT 24
Peak memory 218368 kb
Host smart-86c98f2f-4e80-4783-8449-97b31bd31bb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277439109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3277439109
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3256499612
Short name T269
Test name
Test status
Simulation time 148726450 ps
CPU time 4.73 seconds
Started Jul 22 07:21:10 PM PDT 24
Finished Jul 22 07:21:53 PM PDT 24
Peak memory 217328 kb
Host smart-f37a425b-2671-4a77-9633-a2fb8649fdc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256499612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
256499612
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2607580627
Short name T718
Test name
Test status
Simulation time 229085477 ps
CPU time 7.04 seconds
Started Jul 22 07:21:09 PM PDT 24
Finished Jul 22 07:21:55 PM PDT 24
Peak memory 217808 kb
Host smart-1c636750-68af-473b-8c53-04c36ba84d08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607580627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2607580627
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2634700387
Short name T770
Test name
Test status
Simulation time 735304648 ps
CPU time 9.32 seconds
Started Jul 22 07:21:08 PM PDT 24
Finished Jul 22 07:21:56 PM PDT 24
Peak memory 217148 kb
Host smart-8892d7be-9231-46ba-a8d2-57f5bff0c412
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634700387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2634700387
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.107311744
Short name T392
Test name
Test status
Simulation time 2671037967 ps
CPU time 7.81 seconds
Started Jul 22 07:21:46 PM PDT 24
Finished Jul 22 07:22:31 PM PDT 24
Peak memory 217272 kb
Host smart-baf727ac-4f65-48b3-aea2-60dbe80089a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107311744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.107311744
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3374091193
Short name T607
Test name
Test status
Simulation time 2768614107 ps
CPU time 60.04 seconds
Started Jul 22 07:21:08 PM PDT 24
Finished Jul 22 07:22:47 PM PDT 24
Peak memory 253856 kb
Host smart-9871e8bf-65da-4663-93e1-134aecf48d3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374091193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3374091193
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.889313449
Short name T730
Test name
Test status
Simulation time 394714982 ps
CPU time 8.05 seconds
Started Jul 22 07:21:07 PM PDT 24
Finished Jul 22 07:21:54 PM PDT 24
Peak memory 221584 kb
Host smart-21c020fa-998b-42bb-a078-1b54fead1a24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889313449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.889313449
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2607951600
Short name T552
Test name
Test status
Simulation time 54352286 ps
CPU time 3.08 seconds
Started Jul 22 07:21:32 PM PDT 24
Finished Jul 22 07:22:15 PM PDT 24
Peak memory 217848 kb
Host smart-269d0d40-3f10-4428-9255-7e869adfef12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607951600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2607951600
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.764756176
Short name T66
Test name
Test status
Simulation time 187844504 ps
CPU time 12.06 seconds
Started Jul 22 07:21:08 PM PDT 24
Finished Jul 22 07:21:59 PM PDT 24
Peak memory 214236 kb
Host smart-222becad-aa0e-485e-a046-393afec192a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764756176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.764756176
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2951766634
Short name T857
Test name
Test status
Simulation time 1271884001 ps
CPU time 15.33 seconds
Started Jul 22 07:21:14 PM PDT 24
Finished Jul 22 07:22:11 PM PDT 24
Peak memory 225644 kb
Host smart-8e4d3a0b-26ba-491a-ae19-6c635b52a310
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951766634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2951766634
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.4080390754
Short name T207
Test name
Test status
Simulation time 346893788 ps
CPU time 8.44 seconds
Started Jul 22 07:21:12 PM PDT 24
Finished Jul 22 07:22:01 PM PDT 24
Peak memory 225108 kb
Host smart-56fe0545-64fc-45aa-a51a-1862c8d2436d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080390754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.4080390754
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.4110240768
Short name T713
Test name
Test status
Simulation time 976995585 ps
CPU time 10.93 seconds
Started Jul 22 07:21:08 PM PDT 24
Finished Jul 22 07:21:58 PM PDT 24
Peak memory 225512 kb
Host smart-62e99b23-4007-4835-949d-859c91f52651
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110240768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.4
110240768
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3935855216
Short name T390
Test name
Test status
Simulation time 794396197 ps
CPU time 15.35 seconds
Started Jul 22 07:21:07 PM PDT 24
Finished Jul 22 07:22:02 PM PDT 24
Peak memory 225636 kb
Host smart-72815388-230f-4af2-8143-35e7f40ada8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935855216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3935855216
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1537530796
Short name T571
Test name
Test status
Simulation time 534009096 ps
CPU time 3.22 seconds
Started Jul 22 07:21:04 PM PDT 24
Finished Jul 22 07:21:45 PM PDT 24
Peak memory 217268 kb
Host smart-28274811-44a1-45a1-96b7-43b9782c2e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537530796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1537530796
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.235329813
Short name T483
Test name
Test status
Simulation time 1772929807 ps
CPU time 26.05 seconds
Started Jul 22 07:21:08 PM PDT 24
Finished Jul 22 07:22:13 PM PDT 24
Peak memory 245664 kb
Host smart-d7382afd-6f6f-43d3-a84b-2d8f6b433a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235329813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.235329813
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.428028476
Short name T644
Test name
Test status
Simulation time 78017303 ps
CPU time 9.07 seconds
Started Jul 22 07:21:08 PM PDT 24
Finished Jul 22 07:21:56 PM PDT 24
Peak memory 250600 kb
Host smart-36af0e73-8cb9-4523-982f-7cfc6c19aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428028476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.428028476
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1009573090
Short name T529
Test name
Test status
Simulation time 8631526276 ps
CPU time 157.88 seconds
Started Jul 22 07:21:12 PM PDT 24
Finished Jul 22 07:24:31 PM PDT 24
Peak memory 283208 kb
Host smart-cd3d482e-4253-4e5a-8ac1-4de0d22f4273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009573090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1009573090
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3102463746
Short name T91
Test name
Test status
Simulation time 11555938315 ps
CPU time 322.37 seconds
Started Jul 22 07:21:20 PM PDT 24
Finished Jul 22 07:27:24 PM PDT 24
Peak memory 421824 kb
Host smart-936af939-5f6e-44a3-9156-7b3554250731
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3102463746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3102463746
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.440512013
Short name T676
Test name
Test status
Simulation time 36880080 ps
CPU time 0.84 seconds
Started Jul 22 07:23:33 PM PDT 24
Finished Jul 22 07:23:53 PM PDT 24
Peak memory 211456 kb
Host smart-cd97a8e5-c28a-4d4f-93eb-f00a563af015
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440512013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.440512013
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2984477272
Short name T236
Test name
Test status
Simulation time 87166936 ps
CPU time 1.17 seconds
Started Jul 22 07:22:09 PM PDT 24
Finished Jul 22 07:22:42 PM PDT 24
Peak memory 208704 kb
Host smart-d39f490b-09c5-47f5-b7df-cc37f1d2d4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984477272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2984477272
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2155021873
Short name T662
Test name
Test status
Simulation time 257100184 ps
CPU time 11.13 seconds
Started Jul 22 07:21:22 PM PDT 24
Finished Jul 22 07:22:14 PM PDT 24
Peak memory 217788 kb
Host smart-3cac734d-5858-4e9a-93fd-80d3a5ab2145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155021873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2155021873
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1578957602
Short name T501
Test name
Test status
Simulation time 1254735718 ps
CPU time 7.57 seconds
Started Jul 22 07:22:01 PM PDT 24
Finished Jul 22 07:22:42 PM PDT 24
Peak memory 217280 kb
Host smart-e467ca4f-15c3-4cdb-bf76-e4a8966646b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578957602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1578957602
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1448291075
Short name T666
Test name
Test status
Simulation time 9455727520 ps
CPU time 35.39 seconds
Started Jul 22 07:21:23 PM PDT 24
Finished Jul 22 07:22:40 PM PDT 24
Peak memory 218360 kb
Host smart-a761ab78-621d-4f3a-a8b1-3f610cf2ea9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448291075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1448291075
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.904315114
Short name T815
Test name
Test status
Simulation time 5384494430 ps
CPU time 10.9 seconds
Started Jul 22 07:23:18 PM PDT 24
Finished Jul 22 07:23:50 PM PDT 24
Peak memory 217344 kb
Host smart-63526f7d-587c-4735-8808-21ddb785602e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904315114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.904315114
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1019644889
Short name T522
Test name
Test status
Simulation time 9233652378 ps
CPU time 16.67 seconds
Started Jul 22 07:21:23 PM PDT 24
Finished Jul 22 07:22:21 PM PDT 24
Peak memory 225604 kb
Host smart-e97519eb-b6e1-4d1d-828b-32d03bfcbeb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019644889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1019644889
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2990672611
Short name T65
Test name
Test status
Simulation time 3579875435 ps
CPU time 14.27 seconds
Started Jul 22 07:21:23 PM PDT 24
Finished Jul 22 07:22:19 PM PDT 24
Peak memory 217324 kb
Host smart-fc81e619-5c87-47b3-8cb9-da6743494865
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990672611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2990672611
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2626682162
Short name T482
Test name
Test status
Simulation time 147609492 ps
CPU time 3.08 seconds
Started Jul 22 07:21:21 PM PDT 24
Finished Jul 22 07:22:05 PM PDT 24
Peak memory 217216 kb
Host smart-8aff673b-d45a-4ded-9d8f-f27ff2700a7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626682162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2626682162
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3509668730
Short name T740
Test name
Test status
Simulation time 1299629963 ps
CPU time 54.06 seconds
Started Jul 22 07:23:18 PM PDT 24
Finished Jul 22 07:24:33 PM PDT 24
Peak memory 275084 kb
Host smart-16ce4a5a-b7a7-4753-a356-b7877ee298b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509668730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3509668730
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3828939803
Short name T550
Test name
Test status
Simulation time 2002146691 ps
CPU time 28.05 seconds
Started Jul 22 07:22:09 PM PDT 24
Finished Jul 22 07:23:09 PM PDT 24
Peak memory 226248 kb
Host smart-c36681b4-ba18-4816-b26c-e201d563de0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828939803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3828939803
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3826812004
Short name T581
Test name
Test status
Simulation time 45721253 ps
CPU time 2.23 seconds
Started Jul 22 07:23:18 PM PDT 24
Finished Jul 22 07:23:41 PM PDT 24
Peak memory 221772 kb
Host smart-cf84a865-0fc4-4e57-bdc6-5e4adb0aff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826812004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3826812004
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3438018428
Short name T478
Test name
Test status
Simulation time 263219271 ps
CPU time 6.49 seconds
Started Jul 22 07:21:24 PM PDT 24
Finished Jul 22 07:22:12 PM PDT 24
Peak memory 217052 kb
Host smart-dffe84fd-9954-4b77-9b1b-e074162f9198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438018428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3438018428
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3384422882
Short name T536
Test name
Test status
Simulation time 164421962 ps
CPU time 8.64 seconds
Started Jul 22 07:22:08 PM PDT 24
Finished Jul 22 07:22:49 PM PDT 24
Peak memory 225656 kb
Host smart-796513ed-01f9-4191-959b-38a8107822ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384422882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3384422882
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4203440573
Short name T17
Test name
Test status
Simulation time 1429489543 ps
CPU time 9.72 seconds
Started Jul 22 07:22:10 PM PDT 24
Finished Jul 22 07:22:50 PM PDT 24
Peak memory 225444 kb
Host smart-e1185be2-633b-4711-ba43-02819b0a3905
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203440573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4203440573
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.41785020
Short name T485
Test name
Test status
Simulation time 1688121472 ps
CPU time 12.01 seconds
Started Jul 22 07:21:27 PM PDT 24
Finished Jul 22 07:22:20 PM PDT 24
Peak memory 217920 kb
Host smart-5f2cc94c-5e3b-43cb-bb69-a27648060c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41785020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.41785020
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1522360304
Short name T706
Test name
Test status
Simulation time 52583475 ps
CPU time 3.1 seconds
Started Jul 22 07:21:21 PM PDT 24
Finished Jul 22 07:22:05 PM PDT 24
Peak memory 214476 kb
Host smart-f27795c1-3636-446d-ac88-83197e1e6173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522360304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1522360304
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4245537357
Short name T561
Test name
Test status
Simulation time 315848417 ps
CPU time 28.8 seconds
Started Jul 22 07:21:23 PM PDT 24
Finished Jul 22 07:22:33 PM PDT 24
Peak memory 250600 kb
Host smart-b0ca3c1e-9539-4ec5-af05-c49dd460446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245537357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4245537357
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2888538657
Short name T789
Test name
Test status
Simulation time 252474667 ps
CPU time 6.18 seconds
Started Jul 22 07:21:26 PM PDT 24
Finished Jul 22 07:22:13 PM PDT 24
Peak memory 244992 kb
Host smart-ef92cdd6-f7b3-4d6b-a2d9-930b070f9bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888538657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2888538657
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4267923365
Short name T620
Test name
Test status
Simulation time 6216747219 ps
CPU time 121.21 seconds
Started Jul 22 07:21:28 PM PDT 24
Finished Jul 22 07:24:10 PM PDT 24
Peak memory 283488 kb
Host smart-a261a1d9-e4fc-450c-8b9a-9a0a7c4a6a36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267923365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4267923365
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4078649659
Short name T509
Test name
Test status
Simulation time 31013778 ps
CPU time 0.92 seconds
Started Jul 22 07:21:23 PM PDT 24
Finished Jul 22 07:22:06 PM PDT 24
Peak memory 211332 kb
Host smart-c347c6a1-ff64-4c2c-acc3-1fa1178e1282
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078649659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4078649659
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2934064892
Short name T295
Test name
Test status
Simulation time 14885046 ps
CPU time 0.85 seconds
Started Jul 22 07:21:51 PM PDT 24
Finished Jul 22 07:22:28 PM PDT 24
Peak memory 208184 kb
Host smart-b427dd0d-d486-47f4-9008-698f08c53353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934064892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2934064892
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2122359006
Short name T398
Test name
Test status
Simulation time 10920171 ps
CPU time 0.76 seconds
Started Jul 22 07:21:34 PM PDT 24
Finished Jul 22 07:22:14 PM PDT 24
Peak memory 208612 kb
Host smart-4bea305e-bb6a-41f1-af09-cd2007da5c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122359006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2122359006
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1688719464
Short name T629
Test name
Test status
Simulation time 788927527 ps
CPU time 16.8 seconds
Started Jul 22 07:21:21 PM PDT 24
Finished Jul 22 07:22:19 PM PDT 24
Peak memory 217908 kb
Host smart-b4b21c6d-f2ef-44ba-9263-b629cf7e78d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688719464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1688719464
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3578910790
Short name T402
Test name
Test status
Simulation time 1896666328 ps
CPU time 12.96 seconds
Started Jul 22 07:21:35 PM PDT 24
Finished Jul 22 07:22:27 PM PDT 24
Peak memory 217344 kb
Host smart-f4060fc1-c822-45bf-b4f4-24f5a31f86b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578910790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3578910790
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3083556843
Short name T781
Test name
Test status
Simulation time 7392252436 ps
CPU time 30.45 seconds
Started Jul 22 07:21:34 PM PDT 24
Finished Jul 22 07:22:44 PM PDT 24
Peak memory 218340 kb
Host smart-7b026fe5-73d1-4cc3-af9a-07bc0bdf3569
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083556843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3083556843
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2662345428
Short name T526
Test name
Test status
Simulation time 489255925 ps
CPU time 6.02 seconds
Started Jul 22 07:21:35 PM PDT 24
Finished Jul 22 07:22:20 PM PDT 24
Peak memory 217516 kb
Host smart-7bb0c616-5e80-40ef-b8b7-8070f0caba8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662345428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
662345428
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.482610908
Short name T764
Test name
Test status
Simulation time 579803770 ps
CPU time 4.46 seconds
Started Jul 22 07:21:33 PM PDT 24
Finished Jul 22 07:22:17 PM PDT 24
Peak memory 217780 kb
Host smart-d1822b0c-1a7d-4501-96c8-033f854c0aac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482610908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.482610908
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.751194460
Short name T451
Test name
Test status
Simulation time 806689682 ps
CPU time 11.97 seconds
Started Jul 22 07:21:43 PM PDT 24
Finished Jul 22 07:22:33 PM PDT 24
Peak memory 217172 kb
Host smart-1e973228-b44f-4cf5-bf6f-9e4cc07726fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751194460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.751194460
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3144577794
Short name T564
Test name
Test status
Simulation time 273025205 ps
CPU time 7.56 seconds
Started Jul 22 07:21:43 PM PDT 24
Finished Jul 22 07:22:29 PM PDT 24
Peak memory 217188 kb
Host smart-203b6878-5722-40f0-a77b-a026d629af5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144577794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3144577794
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3928708062
Short name T160
Test name
Test status
Simulation time 3631200779 ps
CPU time 44.08 seconds
Started Jul 22 07:21:43 PM PDT 24
Finished Jul 22 07:23:05 PM PDT 24
Peak memory 250832 kb
Host smart-2369fbec-ed88-41ee-9283-f722f4ec293a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928708062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3928708062
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2454231593
Short name T568
Test name
Test status
Simulation time 4446522322 ps
CPU time 31.55 seconds
Started Jul 22 07:21:36 PM PDT 24
Finished Jul 22 07:22:46 PM PDT 24
Peak memory 226032 kb
Host smart-78ccf7b6-1e39-4b0a-a969-049182623fd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454231593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2454231593
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2309696940
Short name T757
Test name
Test status
Simulation time 84794308 ps
CPU time 3.86 seconds
Started Jul 22 07:21:26 PM PDT 24
Finished Jul 22 07:22:11 PM PDT 24
Peak memory 222372 kb
Host smart-7229692f-e3d2-4c5f-b672-f562316627c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309696940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2309696940
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.486044439
Short name T540
Test name
Test status
Simulation time 772385067 ps
CPU time 12.29 seconds
Started Jul 22 07:21:22 PM PDT 24
Finished Jul 22 07:22:16 PM PDT 24
Peak memory 217388 kb
Host smart-494991e8-9ed7-417a-b790-dcbbb833f26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486044439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.486044439
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2782551473
Short name T598
Test name
Test status
Simulation time 645886318 ps
CPU time 21.51 seconds
Started Jul 22 07:21:43 PM PDT 24
Finished Jul 22 07:22:43 PM PDT 24
Peak memory 225552 kb
Host smart-1bb39ce8-2dac-4a7b-80d3-6e131c492cb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782551473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2782551473
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1707662979
Short name T480
Test name
Test status
Simulation time 730055153 ps
CPU time 14.11 seconds
Started Jul 22 07:21:36 PM PDT 24
Finished Jul 22 07:22:29 PM PDT 24
Peak memory 217796 kb
Host smart-2a679e40-7726-4862-834c-d1d16a9af7d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707662979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
707662979
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.969838992
Short name T541
Test name
Test status
Simulation time 702513586 ps
CPU time 12.54 seconds
Started Jul 22 07:21:23 PM PDT 24
Finished Jul 22 07:22:18 PM PDT 24
Peak memory 217980 kb
Host smart-c22bdee7-c7f4-48f9-8193-a921547df0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969838992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.969838992
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2117584385
Short name T659
Test name
Test status
Simulation time 94261468 ps
CPU time 3.24 seconds
Started Jul 22 07:21:20 PM PDT 24
Finished Jul 22 07:22:05 PM PDT 24
Peak memory 217348 kb
Host smart-d14c8070-b4b5-4cd5-8158-fd8a9f5bcf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117584385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2117584385
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.603019954
Short name T395
Test name
Test status
Simulation time 862654828 ps
CPU time 27.4 seconds
Started Jul 22 07:21:23 PM PDT 24
Finished Jul 22 07:22:32 PM PDT 24
Peak memory 250404 kb
Host smart-03a815e9-f0fb-44af-ad47-0699fbdab5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603019954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.603019954
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2310749784
Short name T303
Test name
Test status
Simulation time 56736499 ps
CPU time 7.87 seconds
Started Jul 22 07:21:26 PM PDT 24
Finished Jul 22 07:22:15 PM PDT 24
Peak memory 250748 kb
Host smart-86ec3e86-b240-4d9e-8f10-61d9ecd7c787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310749784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2310749784
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2255498780
Short name T159
Test name
Test status
Simulation time 5217952874 ps
CPU time 94.25 seconds
Started Jul 22 07:22:00 PM PDT 24
Finished Jul 22 07:24:07 PM PDT 24
Peak memory 272004 kb
Host smart-a12a9fd8-887d-4b42-be00-df4a697cb605
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255498780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2255498780
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1975153043
Short name T582
Test name
Test status
Simulation time 27656364095 ps
CPU time 223.08 seconds
Started Jul 22 07:21:51 PM PDT 24
Finished Jul 22 07:26:11 PM PDT 24
Peak memory 283452 kb
Host smart-5d9f6da9-f8d7-47d4-9b72-f8e1e54b95e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1975153043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1975153043
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3367204203
Short name T349
Test name
Test status
Simulation time 13856056 ps
CPU time 0.87 seconds
Started Jul 22 07:21:21 PM PDT 24
Finished Jul 22 07:22:03 PM PDT 24
Peak memory 211424 kb
Host smart-f61beac1-8487-4a02-9235-b7c67333ba57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367204203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3367204203
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3077561397
Short name T238
Test name
Test status
Simulation time 14704836 ps
CPU time 0.88 seconds
Started Jul 22 07:22:05 PM PDT 24
Finished Jul 22 07:22:38 PM PDT 24
Peak memory 208388 kb
Host smart-2bbb47ce-877f-4c61-9497-e6d63d321fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077561397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3077561397
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3639293624
Short name T188
Test name
Test status
Simulation time 37701506 ps
CPU time 0.8 seconds
Started Jul 22 07:21:51 PM PDT 24
Finished Jul 22 07:22:29 PM PDT 24
Peak memory 208564 kb
Host smart-f325ef4f-eec2-438a-940e-7f5724bc7035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639293624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3639293624
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2644727779
Short name T400
Test name
Test status
Simulation time 1165120552 ps
CPU time 13.36 seconds
Started Jul 22 07:21:49 PM PDT 24
Finished Jul 22 07:22:40 PM PDT 24
Peak memory 225656 kb
Host smart-d38a14f1-7e6e-40ca-ac9b-9078b6646159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644727779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2644727779
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1399163838
Short name T166
Test name
Test status
Simulation time 1139997069 ps
CPU time 7.53 seconds
Started Jul 22 07:22:06 PM PDT 24
Finished Jul 22 07:22:45 PM PDT 24
Peak memory 217208 kb
Host smart-456f12ff-c86d-4663-9ffd-6a633a57af46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399163838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1399163838
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.4021665078
Short name T350
Test name
Test status
Simulation time 5369206512 ps
CPU time 44.27 seconds
Started Jul 22 07:22:00 PM PDT 24
Finished Jul 22 07:23:17 PM PDT 24
Peak memory 218928 kb
Host smart-9e1a9934-6b8e-47d7-a785-c8cdd5bbea32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021665078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.4021665078
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.31113549
Short name T769
Test name
Test status
Simulation time 288622707 ps
CPU time 8.13 seconds
Started Jul 22 07:22:06 PM PDT 24
Finished Jul 22 07:22:46 PM PDT 24
Peak memory 217316 kb
Host smart-e5947a7c-1063-46bc-81dc-00da112842aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31113549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.31113549
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.929642315
Short name T85
Test name
Test status
Simulation time 848073978 ps
CPU time 21.79 seconds
Started Jul 22 07:21:59 PM PDT 24
Finished Jul 22 07:22:54 PM PDT 24
Peak memory 224944 kb
Host smart-c43077aa-3e00-427e-af0f-00b1b5c38538
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929642315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.929642315
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.243000792
Short name T573
Test name
Test status
Simulation time 698962981 ps
CPU time 11.77 seconds
Started Jul 22 07:22:05 PM PDT 24
Finished Jul 22 07:22:48 PM PDT 24
Peak memory 217264 kb
Host smart-ed7cab49-efb9-4a8e-98d7-fd26e2adf66d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243000792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.243000792
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.926489656
Short name T716
Test name
Test status
Simulation time 1474421174 ps
CPU time 2.92 seconds
Started Jul 22 07:21:49 PM PDT 24
Finished Jul 22 07:22:29 PM PDT 24
Peak memory 217192 kb
Host smart-8571c7a2-f322-433f-9bc1-17dea475fe37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926489656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.926489656
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3905323825
Short name T360
Test name
Test status
Simulation time 3656979537 ps
CPU time 34.48 seconds
Started Jul 22 07:22:00 PM PDT 24
Finished Jul 22 07:23:08 PM PDT 24
Peak memory 250612 kb
Host smart-baa7b773-0c55-4d29-8d3c-f55f331a6cfd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905323825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3905323825
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.899858494
Short name T226
Test name
Test status
Simulation time 1151786760 ps
CPU time 14.27 seconds
Started Jul 22 07:22:00 PM PDT 24
Finished Jul 22 07:22:47 PM PDT 24
Peak memory 250328 kb
Host smart-8ed75d19-6cb2-44af-bb30-83ad45984c5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899858494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.899858494
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.225591600
Short name T144
Test name
Test status
Simulation time 65982951 ps
CPU time 1.61 seconds
Started Jul 22 07:21:50 PM PDT 24
Finished Jul 22 07:22:29 PM PDT 24
Peak memory 221364 kb
Host smart-23088fe0-153c-4f16-9ba8-02bb6f7c0213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225591600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.225591600
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3974816180
Short name T321
Test name
Test status
Simulation time 402017053 ps
CPU time 9.71 seconds
Started Jul 22 07:22:01 PM PDT 24
Finished Jul 22 07:22:43 PM PDT 24
Peak memory 217272 kb
Host smart-d17e38fb-e162-48e9-85fd-51d8ba35dc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974816180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3974816180
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1349859795
Short name T245
Test name
Test status
Simulation time 377386078 ps
CPU time 15.24 seconds
Started Jul 22 07:22:05 PM PDT 24
Finished Jul 22 07:22:52 PM PDT 24
Peak memory 225652 kb
Host smart-7579ce39-ed9c-47f4-96d7-9f63538e2627
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349859795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1349859795
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2755164883
Short name T329
Test name
Test status
Simulation time 2466535455 ps
CPU time 9.32 seconds
Started Jul 22 07:22:04 PM PDT 24
Finished Jul 22 07:22:46 PM PDT 24
Peak memory 225612 kb
Host smart-66c31ed0-8578-4757-b94e-f7f69e07a2c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755164883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2755164883
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3599510893
Short name T200
Test name
Test status
Simulation time 365089624 ps
CPU time 11.27 seconds
Started Jul 22 07:22:07 PM PDT 24
Finished Jul 22 07:22:50 PM PDT 24
Peak memory 225588 kb
Host smart-ae4afcc8-01c9-405f-a251-7b339eeb4ee7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599510893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
599510893
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1727687755
Short name T633
Test name
Test status
Simulation time 968216084 ps
CPU time 11.74 seconds
Started Jul 22 07:21:50 PM PDT 24
Finished Jul 22 07:22:39 PM PDT 24
Peak memory 225648 kb
Host smart-eead144d-480e-4aa6-acf8-77608364ceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727687755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1727687755
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2961104194
Short name T393
Test name
Test status
Simulation time 453626100 ps
CPU time 3.98 seconds
Started Jul 22 07:21:49 PM PDT 24
Finished Jul 22 07:22:30 PM PDT 24
Peak memory 217456 kb
Host smart-67534a45-f509-432c-9296-98d802dbfc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961104194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2961104194
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3236873504
Short name T197
Test name
Test status
Simulation time 235012727 ps
CPU time 30.21 seconds
Started Jul 22 07:21:49 PM PDT 24
Finished Jul 22 07:22:56 PM PDT 24
Peak memory 250600 kb
Host smart-7a17d795-a171-4d3f-9bf7-c5700696b2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236873504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3236873504
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2444113962
Short name T371
Test name
Test status
Simulation time 407955653 ps
CPU time 2.99 seconds
Started Jul 22 07:21:49 PM PDT 24
Finished Jul 22 07:22:29 PM PDT 24
Peak memory 217908 kb
Host smart-71b3f505-69e9-445d-8dba-e20b2ac50cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444113962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2444113962
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2484729034
Short name T761
Test name
Test status
Simulation time 3711384310 ps
CPU time 71.01 seconds
Started Jul 22 07:22:07 PM PDT 24
Finished Jul 22 07:23:49 PM PDT 24
Peak memory 250628 kb
Host smart-9eed1b83-a11a-455b-b3d2-c118cc4fa54c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484729034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2484729034
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2568397330
Short name T138
Test name
Test status
Simulation time 43097250683 ps
CPU time 210.68 seconds
Started Jul 22 07:22:07 PM PDT 24
Finished Jul 22 07:26:09 PM PDT 24
Peak memory 283408 kb
Host smart-9411b33e-507c-4ae0-85a9-59fd33014c81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2568397330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2568397330
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.590746775
Short name T232
Test name
Test status
Simulation time 14529166 ps
CPU time 0.86 seconds
Started Jul 22 07:21:51 PM PDT 24
Finished Jul 22 07:22:28 PM PDT 24
Peak memory 211376 kb
Host smart-52334d4a-cbc8-4478-ab92-4ce83c062d41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590746775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.590746775
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2811773550
Short name T813
Test name
Test status
Simulation time 92147236 ps
CPU time 1.22 seconds
Started Jul 22 07:24:57 PM PDT 24
Finished Jul 22 07:26:05 PM PDT 24
Peak memory 208560 kb
Host smart-8940e9a4-db00-4558-86e7-73fc9bdb95ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811773550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2811773550
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1562774817
Short name T669
Test name
Test status
Simulation time 36321694 ps
CPU time 0.89 seconds
Started Jul 22 07:22:10 PM PDT 24
Finished Jul 22 07:22:42 PM PDT 24
Peak memory 208240 kb
Host smart-13ec26f6-b397-4cdf-8402-4e64d1d9416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562774817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1562774817
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1772277605
Short name T763
Test name
Test status
Simulation time 1842291229 ps
CPU time 13.19 seconds
Started Jul 22 07:22:08 PM PDT 24
Finished Jul 22 07:22:53 PM PDT 24
Peak memory 217784 kb
Host smart-abeb9e0c-b180-49cf-9a52-b338fb667b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772277605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1772277605
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1663890178
Short name T29
Test name
Test status
Simulation time 1069455411 ps
CPU time 1.88 seconds
Started Jul 22 07:22:26 PM PDT 24
Finished Jul 22 07:22:58 PM PDT 24
Peak memory 217316 kb
Host smart-f9bf0ea5-44cf-4c3b-8402-39ba80bfa8b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663890178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1663890178
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3266984133
Short name T355
Test name
Test status
Simulation time 6016949914 ps
CPU time 42.04 seconds
Started Jul 22 07:22:27 PM PDT 24
Finished Jul 22 07:23:39 PM PDT 24
Peak memory 218508 kb
Host smart-07fb60a5-45db-4bee-8473-3e796027721f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266984133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3266984133
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.235211862
Short name T449
Test name
Test status
Simulation time 734890052 ps
CPU time 18.45 seconds
Started Jul 22 07:22:24 PM PDT 24
Finished Jul 22 07:23:13 PM PDT 24
Peak memory 217344 kb
Host smart-26f80ae5-5073-4b23-96cd-bd888bd06f76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235211862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.235211862
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2320947414
Short name T479
Test name
Test status
Simulation time 625623227 ps
CPU time 5.78 seconds
Started Jul 22 07:22:27 PM PDT 24
Finished Jul 22 07:23:02 PM PDT 24
Peak memory 223012 kb
Host smart-7cc56d76-965d-4715-a970-88e30a50c142
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320947414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2320947414
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.234426544
Short name T6
Test name
Test status
Simulation time 834669752 ps
CPU time 24.17 seconds
Started Jul 22 07:22:26 PM PDT 24
Finished Jul 22 07:23:20 PM PDT 24
Peak memory 217192 kb
Host smart-010faca3-df89-49f0-bb3a-26454e83cbfd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234426544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.234426544
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2656005851
Short name T69
Test name
Test status
Simulation time 445504494 ps
CPU time 7.58 seconds
Started Jul 22 07:22:07 PM PDT 24
Finished Jul 22 07:22:47 PM PDT 24
Peak memory 217120 kb
Host smart-1f633bd8-6501-4cec-8dfa-8ba151d95273
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656005851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2656005851
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.947470080
Short name T302
Test name
Test status
Simulation time 2075378622 ps
CPU time 50.27 seconds
Started Jul 22 07:22:09 PM PDT 24
Finished Jul 22 07:23:31 PM PDT 24
Peak memory 270960 kb
Host smart-17f3d131-4962-454b-966d-5d7642c46621
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947470080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.947470080
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4047278936
Short name T818
Test name
Test status
Simulation time 1219991859 ps
CPU time 11.58 seconds
Started Jul 22 07:22:07 PM PDT 24
Finished Jul 22 07:22:50 PM PDT 24
Peak memory 250728 kb
Host smart-bc4d5b0e-94ad-4e11-991f-0618b44d8928
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047278936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4047278936
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3681485012
Short name T650
Test name
Test status
Simulation time 70983869 ps
CPU time 2.66 seconds
Started Jul 22 07:22:07 PM PDT 24
Finished Jul 22 07:22:41 PM PDT 24
Peak memory 222148 kb
Host smart-432b04d6-c329-41b9-a85f-e069fd9be976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681485012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3681485012
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.921396731
Short name T185
Test name
Test status
Simulation time 849820121 ps
CPU time 7.59 seconds
Started Jul 22 07:22:07 PM PDT 24
Finished Jul 22 07:22:46 PM PDT 24
Peak memory 217264 kb
Host smart-68ef89f4-8581-4497-a201-3e3156ba8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921396731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.921396731
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3242895342
Short name T424
Test name
Test status
Simulation time 232501489 ps
CPU time 9.09 seconds
Started Jul 22 07:22:25 PM PDT 24
Finished Jul 22 07:23:04 PM PDT 24
Peak memory 225572 kb
Host smart-a1ff3674-7d17-40e7-b94c-627abe086215
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242895342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3242895342
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3715435360
Short name T407
Test name
Test status
Simulation time 340264059 ps
CPU time 6.84 seconds
Started Jul 22 07:22:25 PM PDT 24
Finished Jul 22 07:23:02 PM PDT 24
Peak memory 225584 kb
Host smart-a4642c31-b5a1-4dee-b1ba-210f128d626b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715435360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
715435360
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.523055204
Short name T865
Test name
Test status
Simulation time 1615026360 ps
CPU time 11.11 seconds
Started Jul 22 07:22:10 PM PDT 24
Finished Jul 22 07:22:52 PM PDT 24
Peak memory 217964 kb
Host smart-24930606-7f8d-4b34-9432-d9f90e473bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523055204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.523055204
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.535191281
Short name T279
Test name
Test status
Simulation time 94699156 ps
CPU time 2.42 seconds
Started Jul 22 07:22:05 PM PDT 24
Finished Jul 22 07:22:40 PM PDT 24
Peak memory 214200 kb
Host smart-53a3fa2f-8f39-495b-b12e-03fbcb8da570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535191281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.535191281
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3169732242
Short name T250
Test name
Test status
Simulation time 298044111 ps
CPU time 28.86 seconds
Started Jul 22 07:22:09 PM PDT 24
Finished Jul 22 07:23:09 PM PDT 24
Peak memory 246012 kb
Host smart-ced48c0f-f5fe-4b7f-abfe-2c7ce32410a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169732242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3169732242
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2178143395
Short name T370
Test name
Test status
Simulation time 135819107 ps
CPU time 6.07 seconds
Started Jul 22 07:22:09 PM PDT 24
Finished Jul 22 07:22:47 PM PDT 24
Peak memory 246708 kb
Host smart-c09b3761-e93e-4dce-8602-674656d3fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178143395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2178143395
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.622263006
Short name T484
Test name
Test status
Simulation time 2656750900 ps
CPU time 103.01 seconds
Started Jul 22 07:22:24 PM PDT 24
Finished Jul 22 07:24:36 PM PDT 24
Peak memory 282252 kb
Host smart-9c270532-12fb-4661-8a05-3576afbf1bab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622263006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.622263006
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.594462280
Short name T313
Test name
Test status
Simulation time 233816572365 ps
CPU time 364.69 seconds
Started Jul 22 07:22:28 PM PDT 24
Finished Jul 22 07:29:02 PM PDT 24
Peak memory 299964 kb
Host smart-2766d27f-33e4-4e6a-ae8f-ef8a5afac6be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=594462280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.594462280
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1172172334
Short name T836
Test name
Test status
Simulation time 40860423 ps
CPU time 1.01 seconds
Started Jul 22 07:22:09 PM PDT 24
Finished Jul 22 07:22:41 PM PDT 24
Peak memory 211480 kb
Host smart-f3d4dba3-dca4-439d-8362-6adae536508f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172172334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1172172334
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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