Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121751888

1

T1

24190

T2

30663

T3

30454

auto[1]

1600337

1

T1

990

T4

7290

T5

12504

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121718320

1

T1

23695

T2

30663

T3

30454

auto[1]

1633905

1

T1

1485

T4

6697

T5

14143

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8967630	1			T1	4739		T2	7199		T3	104
auto[IdleSt]	25853381	1			T1	5235		T2	6549		T3	30350
auto[ClkMuxSt]	41429	1			T1	41		T2	73		T4	136
auto[CntIncrSt]	41068	1			T1	41		T2	73		T4	136
auto[CntProgSt]	1364583	1			T1	1362		T2	3098		T4	210
auto[TransCheckSt]	31641	1			T1	27		T2	73		T4	98
auto[TokenHashSt]	47290707	1			T1	517		T2	804		T4	8262
auto[FlashRmaSt]	40926	1			T1	37		T4	50		T5	167
auto[TokenCheck0St]	14719	1			T1	21		T4	36		T5	48
auto[TokenCheck1St]	10934	1			T1	17		T4	23		T5	36
auto[TransProgSt]	291102	1			T1	895		T4	42		T5	72
auto[PostTransSt]	15838645	1			T1	6567		T2	12794		T4	147765
auto[ScrapSt]	281218	1			T8	118		T15	3542		T18	3
auto[EscalateSt]	8349968	1			T1	3520		T4	82120		T5	111416
auto[InvalidSt]	14931852	1			T1	2161		T4	247395		T5	360502

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2422	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14931852	1			T1	2161		T4	247395		T5	360502
EscalateSt	8349968	1			T1	3520		T4	82120		T5	111416
ScrapSt	281218	1			T8	118		T15	3542		T18	3
PostTransSt	15838645	1			T1	6567		T2	12794		T4	147765
TransProgSt	291102	1			T1	895		T4	42		T5	72
TokenCheck1St	10934	1			T1	17		T4	23		T5	36
TokenCheck0St	14719	1			T1	21		T4	36		T5	48
FlashRmaSt	40926	1			T1	37		T4	50		T5	167
TokenHashSt	47290707	1			T1	517		T2	804		T4	8262
TransCheckSt	31641	1			T1	27		T2	73		T4	98
CntProgSt	1364583	1			T1	1362		T2	3098		T4	210
CntIncrSt	41068	1			T1	41		T2	73		T4	136
ClkMuxSt	41429	1			T1	41		T2	73		T4	136
IdleSt	25853381	1			T1	5235		T2	6549		T3	30350
ResetSt	8967630	1			T1	4739		T2	7199		T3	104
arcs[ResetSt=>IdleSt]	64075	1			T1	53		T2	74		T3	1
arcs[IdleSt=>ScrapSt]	347	1			T8	3		T15	3		T18	1
arcs[IdleSt=>ClkMuxSt]	41134	1			T1	41		T2	73		T4	136
arcs[ClkMuxSt=>CntIncrSt]	41068	1			T1	41		T2	73		T4	136
arcs[CntIncrSt=>PostTransSt]	2322	1			T4	24		T5	12		T9	14
arcs[CntIncrSt=>CntProgSt]	38677	1			T1	41		T2	73		T4	112
arcs[CntProgSt=>PostTransSt]	5905	1			T1	14		T4	14		T5	28
arcs[CntProgSt=>TransCheckSt]	31641	1			T1	27		T2	73		T4	98
arcs[TransCheckSt=>PostTransSt]	4280	1			T4	19		T5	7		T9	10
arcs[TransCheckSt=>TokenHashSt]	27248	1			T1	27		T2	73		T4	79
arcs[TokenHashSt=>PostTransSt]	11730	1			T1	6		T2	73		T4	43
arcs[TokenHashSt=>FlashRmaSt]	14803	1			T1	21		T4	36		T5	48
arcs[FlashRmaSt=>TokenCheck0St]	14719	1			T1	21		T4	36		T5	48
arcs[TokenCheck0St=>PostTransSt]	3757	1			T1	4		T4	13		T5	12
arcs[TokenCheck0St=>TokenCheck1St]	10934	1			T1	17		T4	23		T5	36
arcs[TokenCheck1St=>PostTransSt]	706	1			T4	1		T9	1		T15	2
arcs[TransProgSt=>PostTransSt]	9333	1			T1	17		T4	22		T5	36
arcs[IdleSt=>EscalateSt]	149	1			T18	3		T40	3		T42	5
arcs[ClkMuxSt=>EscalateSt]	66	1			T18	1		T40	2		T41	1
arcs[CntIncrSt=>EscalateSt]	69	1			T18	2		T41	2		T42	2
arcs[CntProgSt=>EscalateSt]	1131	1			T18	15		T40	24		T41	8
arcs[TransCheckSt=>EscalateSt]	113	1			T41	7		T47	2		T46	1
arcs[TokenHashSt=>EscalateSt]	715	1			T18	6		T40	5		T41	22
arcs[FlashRmaSt=>EscalateSt]	84	1			T18	2		T40	1		T42	1
arcs[TokenCheck0St=>EscalateSt]	28	1			T41	2		T45	2		T46	1
arcs[TokenCheck1St=>EscalateSt]	149	1			T40	1		T41	1		T42	2
arcs[TransProgSt=>EscalateSt]	746	1			T18	18		T40	22		T41	12
arcs[PostTransSt=>EscalateSt]	6145	1			T1	14		T4	16		T5	28
arcs[InvalidSt=>EscalateSt]	17467	1			T1	11		T4	126		T5	243

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8967458	1			T1	4739		T2	7199		T3	104
auto[0]	auto[IdleSt]	25853281	1			T1	5235		T2	6549		T3	30350
auto[0]	auto[ClkMuxSt]	41385	1			T1	41		T2	73		T4	136
auto[0]	auto[CntIncrSt]	41016	1			T1	41		T2	73		T4	136
auto[0]	auto[CntProgSt]	1363799	1			T1	1362		T2	3098		T4	210
auto[0]	auto[TransCheckSt]	31569	1			T1	27		T2	73		T4	98
auto[0]	auto[TokenHashSt]	47290248	1			T1	517		T2	804		T4	8262
auto[0]	auto[FlashRmaSt]	40876	1			T1	37		T4	50		T5	167
auto[0]	auto[TokenCheck0St]	14705	1			T1	21		T4	36		T5	48
auto[0]	auto[TokenCheck1St]	10832	1			T1	17		T4	23		T5	36
auto[0]	auto[TransProgSt]	290596	1			T1	895		T4	42		T5	72
auto[0]	auto[PostTransSt]	15835615	1			T1	6560		T2	12794		T4	147756
auto[0]	auto[ScrapSt]	281164	1			T8	118		T15	3542		T18	2
auto[0]	auto[EscalateSt]	6763693	1			T1	2540		T4	74904		T5	99039
auto[0]	auto[InvalidSt]	14923229	1			T1	2158		T4	247330		T5	360387
auto[1]	auto[ResetSt]	172	1			T18	3		T40	4		T41	1
auto[1]	auto[IdleSt]	100	1			T18	2		T40	2		T42	4
auto[1]	auto[ClkMuxSt]	44	1			T18	1		T40	1		T41	1
auto[1]	auto[CntIncrSt]	52	1			T18	1		T42	1		T78	1
auto[1]	auto[CntProgSt]	784	1			T18	10		T40	19		T41	5
auto[1]	auto[TransCheckSt]	72	1			T41	2		T47	1		T46	1
auto[1]	auto[TokenHashSt]	459	1			T18	2		T40	3		T41	15
auto[1]	auto[FlashRmaSt]	50	1			T42	1		T78	1		T45	2
auto[1]	auto[TokenCheck0St]	14	1			T41	1		T45	2		T46	1
auto[1]	auto[TokenCheck1St]	102	1			T40	1		T42	2		T78	3
auto[1]	auto[TransProgSt]	506	1			T18	12		T40	19		T41	9
auto[1]	auto[PostTransSt]	3030	1			T1	7		T4	9		T5	12
auto[1]	auto[ScrapSt]	54	1			T18	1		T41	1		T42	1
auto[1]	auto[EscalateSt]	1586275	1			T1	980		T4	7216		T5	12377
auto[1]	auto[InvalidSt]	8623	1			T1	3		T4	65		T5	115

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8967459	1			T1	4739		T2	7199		T3	104
auto[0]	auto[IdleSt]	25853288	1			T1	5235		T2	6549		T3	30350
auto[0]	auto[ClkMuxSt]	41387	1			T1	41		T2	73		T4	136
auto[0]	auto[CntIncrSt]	41027	1			T1	41		T2	73		T4	136
auto[0]	auto[CntProgSt]	1363842	1			T1	1362		T2	3098		T4	210
auto[0]	auto[TransCheckSt]	31559	1			T1	27		T2	73		T4	98
auto[0]	auto[TokenHashSt]	47290212	1			T1	517		T2	804		T4	8262
auto[0]	auto[FlashRmaSt]	40867	1			T1	37		T4	50		T5	167
auto[0]	auto[TokenCheck0St]	14697	1			T1	21		T4	36		T5	48
auto[0]	auto[TokenCheck1St]	10834	1			T1	17		T4	23		T5	36
auto[0]	auto[TransProgSt]	290605	1			T1	895		T4	42		T5	72
auto[0]	auto[PostTransSt]	15835465	1			T1	6560		T2	12794		T4	147758
auto[0]	auto[ScrapSt]	281169	1			T8	118		T15	3542		T18	2
auto[0]	auto[EscalateSt]	6730479	1			T1	2050		T4	75491		T5	97417
auto[0]	auto[InvalidSt]	14923008	1			T1	2153		T4	247334		T5	360374
auto[1]	auto[ResetSt]	171	1			T18	1		T40	6		T41	4
auto[1]	auto[IdleSt]	93	1			T18	2		T40	1		T42	3
auto[1]	auto[ClkMuxSt]	42	1			T40	1		T41	1		T42	1
auto[1]	auto[CntIncrSt]	41	1			T18	1		T41	2		T42	2
auto[1]	auto[CntProgSt]	741	1			T18	10		T40	11		T41	4
auto[1]	auto[TransCheckSt]	82	1			T41	5		T47	2		T46	1
auto[1]	auto[TokenHashSt]	495	1			T18	5		T40	5		T41	15
auto[1]	auto[FlashRmaSt]	59	1			T18	2		T40	1		T78	2
auto[1]	auto[TokenCheck0St]	22	1			T41	2		T45	2		T188	1
auto[1]	auto[TokenCheck1St]	100	1			T41	1		T42	1		T78	1
auto[1]	auto[TransProgSt]	497	1			T18	11		T40	11		T41	4
auto[1]	auto[PostTransSt]	3180	1			T1	7		T4	7		T5	16
auto[1]	auto[ScrapSt]	49	1			T18	1		T41	2		T78	1
auto[1]	auto[EscalateSt]	1619489	1			T1	1470		T4	6629		T5	13999
auto[1]	auto[InvalidSt]	8844	1			T1	8		T4	61		T5	128