Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110980493

1

T1

19883

T2

3083

T3

21845

auto[1]

1533310

1

T1

198

T3

11395

T4

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110983864

1

T1

19586

T2

3083

T3

24574

auto[1]

1529939

1

T1

495

T3

8666

T4

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7872811	1			T1	5496		T2	109		T3	10092
auto[IdleSt]	22873310	1			T1	2018		T2	2974		T3	6775
auto[ClkMuxSt]	38161	1			T1	61		T3	63		T4	58
auto[CntIncrSt]	37860	1			T1	61		T3	61		T4	58
auto[CntProgSt]	1545678	1			T1	107		T3	250		T4	91
auto[TransCheckSt]	29615	1			T1	50		T3	38		T4	42
auto[TokenHashSt]	46268505	1			T1	2586		T3	595		T4	414
auto[FlashRmaSt]	38390	1			T1	41		T3	49		T4	48
auto[TokenCheck0St]	13838	1			T1	19		T3	24		T4	10
auto[TokenCheck1St]	10262	1			T1	12		T3	24		T4	2
auto[TransProgSt]	398546	1			T1	20		T3	46		T4	4
auto[PostTransSt]	13256719	1			T1	8704		T3	6		T4	8124
auto[ScrapSt]	153202	1			T3	6		T11	16710		T19	1032
auto[EscalateSt]	7315953	1			T1	906		T3	15211		T4	866
auto[InvalidSt]	12658644	1			T14	591		T11	335		T17	155944

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2309	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12658644	1			T14	591		T11	335		T17	155944
EscalateSt	7315953	1			T1	906		T3	15211		T4	866
ScrapSt	153202	1			T3	6		T11	16710		T19	1032
PostTransSt	13256719	1			T1	8704		T3	6		T4	8124
TransProgSt	398546	1			T1	20		T3	46		T4	4
TokenCheck1St	10262	1			T1	12		T3	24		T4	2
TokenCheck0St	13838	1			T1	19		T3	24		T4	10
FlashRmaSt	38390	1			T1	41		T3	49		T4	48
TokenHashSt	46268505	1			T1	2586		T3	595		T4	414
TransCheckSt	29615	1			T1	50		T3	38		T4	42
CntProgSt	1545678	1			T1	107		T3	250		T4	91
CntIncrSt	37860	1			T1	61		T3	61		T4	58
ClkMuxSt	38161	1			T1	61		T3	63		T4	58
IdleSt	22873310	1			T1	2018		T2	2974		T3	6775
ResetSt	7872811	1			T1	5496		T2	109		T3	10092
arcs[ResetSt=>IdleSt]	59089	1			T1	62		T2	1		T3	72
arcs[IdleSt=>ScrapSt]	355	1			T3	2		T11	3		T19	2
arcs[IdleSt=>ClkMuxSt]	37921	1			T1	61		T3	63		T4	58
arcs[ClkMuxSt=>CntIncrSt]	37860	1			T1	61		T3	61		T4	58
arcs[CntIncrSt=>PostTransSt]	1968	1			T1	4		T4	9		T5	11
arcs[CntIncrSt=>CntProgSt]	35815	1			T1	57		T3	60		T4	49
arcs[CntProgSt=>PostTransSt]	5096	1			T1	7		T4	7		T5	9
arcs[CntProgSt=>TransCheckSt]	29615	1			T1	50		T3	38		T4	42
arcs[TransCheckSt=>PostTransSt]	3969	1			T1	7		T4	5		T13	50
arcs[TransCheckSt=>TokenHashSt]	25508	1			T1	43		T3	37		T4	37
arcs[TokenHashSt=>PostTransSt]	10862	1			T1	24		T4	27		T12	1
arcs[TokenHashSt=>FlashRmaSt]	13919	1			T1	19		T3	25		T4	10
arcs[FlashRmaSt=>TokenCheck0St]	13838	1			T1	19		T3	24		T4	10
arcs[TokenCheck0St=>PostTransSt]	3548	1			T1	7		T4	8		T13	18
arcs[TokenCheck0St=>TokenCheck1St]	10262	1			T1	12		T3	24		T4	2
arcs[TokenCheck1St=>PostTransSt]	690	1			T1	2		T13	8		T5	2
arcs[TransProgSt=>PostTransSt]	8654	1			T1	10		T3	3		T4	2
arcs[IdleSt=>EscalateSt]	203	1			T3	6		T40	10		T42	8
arcs[ClkMuxSt=>EscalateSt]	61	1			T3	2		T40	2		T41	2
arcs[CntIncrSt=>EscalateSt]	77	1			T3	1		T40	5		T41	1
arcs[CntProgSt=>EscalateSt]	1104	1			T3	22		T40	22		T41	27
arcs[TransCheckSt=>EscalateSt]	138	1			T3	1		T41	1		T42	2
arcs[TokenHashSt=>EscalateSt]	727	1			T3	12		T40	11		T41	13
arcs[FlashRmaSt=>EscalateSt]	81	1			T3	1		T40	1		T41	1
arcs[TokenCheck0St=>EscalateSt]	28	1			T40	1		T46	1		T47	1
arcs[TokenCheck1St=>EscalateSt]	156	1			T3	5		T40	9		T41	4
arcs[TransProgSt=>EscalateSt]	762	1			T3	16		T40	10		T41	21
arcs[PostTransSt=>EscalateSt]	5350	1			T1	7		T3	3		T4	7
arcs[InvalidSt=>EscalateSt]	16103	1			T14	4		T11	4		T17	95

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7872629	1			T1	5496		T2	109		T3	10088
auto[0]	auto[IdleSt]	22873170	1			T1	2018		T2	2974		T3	6771
auto[0]	auto[ClkMuxSt]	38118	1			T1	61		T3	62		T4	58
auto[0]	auto[CntIncrSt]	37809	1			T1	61		T3	60		T4	58
auto[0]	auto[CntProgSt]	1544913	1			T1	107		T3	233		T4	91
auto[0]	auto[TransCheckSt]	29525	1			T1	50		T3	37		T4	42
auto[0]	auto[TokenHashSt]	46268039	1			T1	2586		T3	588		T4	414
auto[0]	auto[FlashRmaSt]	38345	1			T1	41		T3	48		T4	48
auto[0]	auto[TokenCheck0St]	13818	1			T1	19		T3	24		T4	10
auto[0]	auto[TokenCheck1St]	10159	1			T1	12		T3	20		T4	2
auto[0]	auto[TransProgSt]	398041	1			T1	20		T3	35		T4	4
auto[0]	auto[PostTransSt]	13254022	1			T1	8702		T3	4		T4	8121
auto[0]	auto[ScrapSt]	153156	1			T3	4		T11	16710		T19	1032
auto[0]	auto[EscalateSt]	5795845	1			T1	710		T3	3871		T4	572
auto[0]	auto[InvalidSt]	12650595	1			T14	589		T11	334		T17	155902
auto[1]	auto[ResetSt]	182	1			T3	4		T40	2		T41	5
auto[1]	auto[IdleSt]	140	1			T3	4		T40	6		T42	6
auto[1]	auto[ClkMuxSt]	43	1			T3	1		T40	1		T41	2
auto[1]	auto[CntIncrSt]	51	1			T3	1		T40	3		T42	1
auto[1]	auto[CntProgSt]	765	1			T3	17		T40	16		T41	19
auto[1]	auto[TransCheckSt]	90	1			T3	1		T41	1		T46	9
auto[1]	auto[TokenHashSt]	466	1			T3	7		T40	5		T41	7
auto[1]	auto[FlashRmaSt]	45	1			T3	1		T40	1		T41	1
auto[1]	auto[TokenCheck0St]	20	1			T46	1		T190	1		T191	1
auto[1]	auto[TokenCheck1St]	103	1			T3	4		T40	6		T41	1
auto[1]	auto[TransProgSt]	505	1			T3	11		T40	4		T41	14
auto[1]	auto[PostTransSt]	2697	1			T1	2		T3	2		T4	3
auto[1]	auto[ScrapSt]	46	1			T3	2		T41	1		T42	1
auto[1]	auto[EscalateSt]	1520108	1			T1	196		T3	11340		T4	294
auto[1]	auto[InvalidSt]	8049	1			T14	2		T11	1		T17	42

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7872643	1			T1	5496		T2	109		T3	10092
auto[0]	auto[IdleSt]	22873174	1			T1	2018		T2	2974		T3	6773
auto[0]	auto[ClkMuxSt]	38123	1			T1	61		T3	61		T4	58
auto[0]	auto[CntIncrSt]	37808	1			T1	61		T3	60		T4	58
auto[0]	auto[CntProgSt]	1544967	1			T1	107		T3	237		T4	91
auto[0]	auto[TransCheckSt]	29528	1			T1	50		T3	38		T4	42
auto[0]	auto[TokenHashSt]	46268013	1			T1	2586		T3	586		T4	414
auto[0]	auto[FlashRmaSt]	38329	1			T1	41		T3	49		T4	48
auto[0]	auto[TokenCheck0St]	13812	1			T1	19		T3	24		T4	10
auto[0]	auto[TokenCheck1St]	10160	1			T1	12		T3	21		T4	2
auto[0]	auto[TransProgSt]	398031	1			T1	20		T3	34		T4	4
auto[0]	auto[PostTransSt]	13253995	1			T1	8699		T3	4		T4	8120
auto[0]	auto[ScrapSt]	153153	1			T3	5		T11	16710		T19	1032
auto[0]	auto[EscalateSt]	5799229	1			T1	416		T3	6590		T4	474
auto[0]	auto[InvalidSt]	12650590	1			T14	589		T11	332		T17	155891
auto[1]	auto[ResetSt]	168	1			T40	2		T41	4		T192	6
auto[1]	auto[IdleSt]	136	1			T3	2		T40	7		T42	7
auto[1]	auto[ClkMuxSt]	38	1			T3	2		T40	1		T41	1
auto[1]	auto[CntIncrSt]	52	1			T3	1		T40	4		T41	1
auto[1]	auto[CntProgSt]	711	1			T3	13		T40	17		T41	14
auto[1]	auto[TransCheckSt]	87	1			T41	1		T42	2		T46	5
auto[1]	auto[TokenHashSt]	492	1			T3	9		T40	8		T41	10
auto[1]	auto[FlashRmaSt]	61	1			T40	1		T42	2		T46	3
auto[1]	auto[TokenCheck0St]	26	1			T40	1		T46	1		T47	1
auto[1]	auto[TokenCheck1St]	102	1			T3	3		T40	6		T41	4
auto[1]	auto[TransProgSt]	515	1			T3	12		T40	8		T41	14
auto[1]	auto[PostTransSt]	2724	1			T1	5		T3	2		T4	4
auto[1]	auto[ScrapSt]	49	1			T3	1		T41	2		T42	1
auto[1]	auto[EscalateSt]	1516724	1			T1	490		T3	8621		T4	392
auto[1]	auto[InvalidSt]	8054	1			T14	2		T11	3		T17	53