Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54093 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
77 |
auto[1] |
1998 |
1 |
|
|
T5 |
12 |
|
T6 |
7 |
|
T19 |
13 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55387 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
704 |
1 |
|
|
T71 |
8 |
|
T55 |
13 |
|
T72 |
10 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54055 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
2036 |
1 |
|
|
T33 |
6 |
|
T30 |
13 |
|
T90 |
3 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54084 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
2007 |
1 |
|
|
T33 |
3 |
|
T8 |
2 |
|
T30 |
5 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54092 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
1999 |
1 |
|
|
T33 |
11 |
|
T8 |
3 |
|
T30 |
10 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50898 |
1 |
|
|
T3 |
80 |
|
T5 |
89 |
|
T16 |
3 |
no_err_inj |
5193 |
1 |
|
|
T4 |
6 |
|
T14 |
19 |
|
T15 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54200 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
76 |
auto[1] |
1891 |
1 |
|
|
T5 |
13 |
|
T6 |
11 |
|
T19 |
7 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55322 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
769 |
1 |
|
|
T71 |
12 |
|
T55 |
9 |
|
T72 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39338 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
16753 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
42 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54082 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
2009 |
1 |
|
|
T6 |
2 |
|
T33 |
11 |
|
T8 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54067 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
2024 |
1 |
|
|
T6 |
2 |
|
T33 |
12 |
|
T8 |
3 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54043 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
2048 |
1 |
|
|
T6 |
2 |
|
T33 |
5 |
|
T8 |
7 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54116 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
81 |
auto[1] |
1975 |
1 |
|
|
T5 |
8 |
|
T6 |
6 |
|
T19 |
6 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53777 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
2314 |
1 |
|
|
T16 |
3 |
|
T6 |
6 |
|
T20 |
21 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55301 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
790 |
1 |
|
|
T71 |
13 |
|
T55 |
9 |
|
T72 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55299 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
792 |
1 |
|
|
T71 |
17 |
|
T55 |
11 |
|
T72 |
16 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55332 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
759 |
1 |
|
|
T71 |
14 |
|
T55 |
9 |
|
T72 |
15 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53480 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
2611 |
1 |
|
|
T6 |
15 |
|
T8 |
36 |
|
T90 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52349 |
1 |
|
|
T4 |
6 |
|
T5 |
89 |
|
T14 |
19 |
auto[1] |
3742 |
1 |
|
|
T3 |
80 |
|
T17 |
68 |
|
T47 |
91 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54099 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
1992 |
1 |
|
|
T6 |
2 |
|
T33 |
8 |
|
T8 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54028 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
2063 |
1 |
|
|
T33 |
9 |
|
T8 |
3 |
|
T30 |
12 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54117 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
1974 |
1 |
|
|
T33 |
7 |
|
T8 |
1 |
|
T30 |
11 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54158 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
78 |
auto[1] |
1933 |
1 |
|
|
T5 |
11 |
|
T6 |
16 |
|
T19 |
7 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50479 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
77 |
auto[1] |
5612 |
1 |
|
|
T5 |
12 |
|
T27 |
83 |
|
T6 |
6 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52268 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[1] |
3823 |
1 |
|
|
T28 |
88 |
|
T21 |
71 |
|
T60 |
97 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56091 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54233 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
76 |
auto[1] |
1858 |
1 |
|
|
T5 |
13 |
|
T6 |
3 |
|
T19 |
9 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54167 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
79 |
auto[1] |
1924 |
1 |
|
|
T5 |
10 |
|
T6 |
4 |
|
T19 |
12 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54229 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
79 |
auto[1] |
1862 |
1 |
|
|
T5 |
10 |
|
T6 |
7 |
|
T19 |
4 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49597 |
1 |
|
|
T3 |
80 |
|
T5 |
89 |
|
T16 |
3 |
auto[0] |
no_err_inj |
3883 |
1 |
|
|
T4 |
6 |
|
T14 |
19 |
|
T15 |
7 |
auto[1] |
err_inj |
1301 |
1 |
|
|
T6 |
8 |
|
T8 |
21 |
|
T90 |
6 |
auto[1] |
no_err_inj |
1310 |
1 |
|
|
T6 |
7 |
|
T8 |
15 |
|
T90 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51567 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1913 |
1 |
|
|
T33 |
9 |
|
T30 |
12 |
|
T66 |
8 |
auto[1] |
auto[0] |
2461 |
1 |
|
|
T6 |
15 |
|
T8 |
33 |
|
T90 |
11 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T8 |
3 |
|
T22 |
2 |
|
T92 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51595 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1885 |
1 |
|
|
T33 |
12 |
|
T30 |
10 |
|
T66 |
12 |
auto[1] |
auto[0] |
2472 |
1 |
|
|
T6 |
13 |
|
T8 |
33 |
|
T90 |
11 |
auto[1] |
auto[1] |
139 |
1 |
|
|
T6 |
2 |
|
T8 |
3 |
|
T22 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51643 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1837 |
1 |
|
|
T33 |
7 |
|
T30 |
11 |
|
T66 |
12 |
auto[1] |
auto[0] |
2474 |
1 |
|
|
T6 |
15 |
|
T8 |
35 |
|
T90 |
11 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T8 |
1 |
|
T22 |
1 |
|
T198 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51610 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1870 |
1 |
|
|
T33 |
3 |
|
T30 |
5 |
|
T66 |
10 |
auto[1] |
auto[0] |
2474 |
1 |
|
|
T6 |
15 |
|
T8 |
34 |
|
T90 |
10 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T8 |
2 |
|
T90 |
1 |
|
T32 |
3 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51622 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1858 |
1 |
|
|
T33 |
11 |
|
T30 |
10 |
|
T66 |
8 |
auto[1] |
auto[0] |
2470 |
1 |
|
|
T6 |
15 |
|
T8 |
33 |
|
T90 |
11 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T8 |
3 |
|
T92 |
3 |
|
T49 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51605 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1875 |
1 |
|
|
T33 |
6 |
|
T30 |
13 |
|
T66 |
16 |
auto[1] |
auto[0] |
2450 |
1 |
|
|
T6 |
15 |
|
T8 |
36 |
|
T90 |
8 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T90 |
3 |
|
T32 |
1 |
|
T22 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38101 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
77 |
auto[0] |
auto[1] |
1237 |
1 |
|
|
T5 |
12 |
|
T6 |
7 |
|
T19 |
13 |
auto[1] |
auto[0] |
15992 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
42 |
auto[1] |
auto[1] |
761 |
1 |
|
|
T51 |
4 |
|
T93 |
14 |
|
T94 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38198 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
76 |
auto[0] |
auto[1] |
1140 |
1 |
|
|
T5 |
13 |
|
T6 |
11 |
|
T19 |
7 |
auto[1] |
auto[0] |
16002 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
42 |
auto[1] |
auto[1] |
751 |
1 |
|
|
T51 |
6 |
|
T93 |
10 |
|
T94 |
4 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37985 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1353 |
1 |
|
|
T16 |
3 |
|
T20 |
16 |
|
T35 |
13 |
auto[1] |
auto[0] |
15792 |
1 |
|
|
T7 |
8 |
|
T8 |
42 |
|
T20 |
20 |
auto[1] |
auto[1] |
961 |
1 |
|
|
T6 |
6 |
|
T20 |
5 |
|
T29 |
16 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38151 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
81 |
auto[0] |
auto[1] |
1187 |
1 |
|
|
T5 |
8 |
|
T6 |
6 |
|
T19 |
6 |
auto[1] |
auto[0] |
15965 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
42 |
auto[1] |
auto[1] |
788 |
1 |
|
|
T51 |
4 |
|
T93 |
6 |
|
T94 |
13 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34458 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
77 |
auto[0] |
auto[1] |
4880 |
1 |
|
|
T5 |
12 |
|
T27 |
83 |
|
T6 |
6 |
auto[1] |
auto[0] |
16021 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
42 |
auto[1] |
auto[1] |
732 |
1 |
|
|
T51 |
8 |
|
T93 |
13 |
|
T94 |
8 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38144 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1194 |
1 |
|
|
T33 |
9 |
|
T8 |
1 |
|
T66 |
8 |
auto[1] |
auto[0] |
15884 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
40 |
auto[1] |
auto[1] |
869 |
1 |
|
|
T8 |
2 |
|
T30 |
12 |
|
T22 |
8 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38166 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1172 |
1 |
|
|
T6 |
2 |
|
T33 |
8 |
|
T90 |
1 |
auto[1] |
auto[0] |
15933 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
41 |
auto[1] |
auto[1] |
820 |
1 |
|
|
T8 |
1 |
|
T30 |
10 |
|
T32 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38116 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1222 |
1 |
|
|
T6 |
2 |
|
T33 |
12 |
|
T8 |
1 |
auto[1] |
auto[0] |
15951 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
40 |
auto[1] |
auto[1] |
802 |
1 |
|
|
T8 |
2 |
|
T30 |
10 |
|
T22 |
7 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38159 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1179 |
1 |
|
|
T6 |
2 |
|
T33 |
11 |
|
T90 |
1 |
auto[1] |
auto[0] |
15923 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
41 |
auto[1] |
auto[1] |
830 |
1 |
|
|
T8 |
1 |
|
T30 |
8 |
|
T22 |
6 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38142 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T33 |
3 |
|
T8 |
1 |
|
T90 |
1 |
auto[1] |
auto[0] |
15942 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
41 |
auto[1] |
auto[1] |
811 |
1 |
|
|
T8 |
1 |
|
T30 |
5 |
|
T32 |
3 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38147 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T33 |
6 |
|
T90 |
3 |
|
T66 |
16 |
auto[1] |
auto[0] |
15908 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
42 |
auto[1] |
auto[1] |
845 |
1 |
|
|
T30 |
13 |
|
T32 |
1 |
|
T22 |
7 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38168 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
79 |
auto[0] |
auto[1] |
1170 |
1 |
|
|
T5 |
10 |
|
T6 |
7 |
|
T19 |
4 |
auto[1] |
auto[0] |
16061 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
42 |
auto[1] |
auto[1] |
692 |
1 |
|
|
T51 |
12 |
|
T93 |
8 |
|
T94 |
9 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38210 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
79 |
auto[0] |
auto[1] |
1128 |
1 |
|
|
T5 |
10 |
|
T6 |
4 |
|
T19 |
12 |
auto[1] |
auto[0] |
15957 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
42 |
auto[1] |
auto[1] |
796 |
1 |
|
|
T51 |
3 |
|
T93 |
14 |
|
T94 |
14 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37806 |
1 |
|
|
T3 |
80 |
|
T4 |
6 |
|
T5 |
89 |
auto[0] |
auto[1] |
1532 |
1 |
|
|
T6 |
15 |
|
T8 |
14 |
|
T90 |
11 |
auto[1] |
auto[0] |
15674 |
1 |
|
|
T6 |
6 |
|
T7 |
8 |
|
T8 |
20 |
auto[1] |
auto[1] |
1079 |
1 |
|
|
T8 |
22 |
|
T32 |
11 |
|
T92 |
13 |