Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105485816

1

T1

1617

T2

1520

T3

19025

auto[1]

1446338

1

T3

10018

T5

594

T16

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105473790

1

T1

1617

T2

1520

T3

18213

auto[1]

1458364

1

T3

10830

T5

594

T16

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7828780	1			T1	88		T2	86		T3	7007
auto[IdleSt]	22531011	1			T1	1529		T2	75		T3	6008
auto[ClkMuxSt]	36777	1			T2	1		T3	67		T4	9
auto[CntIncrSt]	36505	1			T2	1		T3	65		T4	5
auto[CntProgSt]	1595879	1			T2	176		T3	126		T4	83
auto[TransCheckSt]	28422	1			T2	1		T3	52		T4	5
auto[TokenHashSt]	41630397	1			T2	102		T3	394		T4	18361
auto[FlashRmaSt]	38929	1			T3	100		T4	31		T5	33
auto[TokenCheck0St]	13408	1			T3	27		T4	5		T5	21
auto[TokenCheck1St]	9963	1			T3	27		T4	5		T5	8
auto[TransProgSt]	370628	1			T3	48		T4	71		T5	16
auto[PostTransSt]	13132680	1			T2	1078		T3	41		T4	779
auto[ScrapSt]	183694	1			T3	12		T4	45		T17	8
auto[EscalateSt]	7064727	1			T3	15069		T5	1494		T16	396
auto[InvalidSt]	12428239	1			T6	979		T33	4380		T8	10882

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2115	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12428239	1			T6	979		T33	4380		T8	10882
EscalateSt	7064727	1			T3	15069		T5	1494		T16	396
ScrapSt	183694	1			T3	12		T4	45		T17	8
PostTransSt	13132680	1			T2	1078		T3	41		T4	779
TransProgSt	370628	1			T3	48		T4	71		T5	16
TokenCheck1St	9963	1			T3	27		T4	5		T5	8
TokenCheck0St	13408	1			T3	27		T4	5		T5	21
FlashRmaSt	38929	1			T3	100		T4	31		T5	33
TokenHashSt	41630397	1			T2	102		T3	394		T4	18361
TransCheckSt	28422	1			T2	1		T3	52		T4	5
CntProgSt	1595879	1			T2	176		T3	126		T4	83
CntIncrSt	36505	1			T2	1		T3	65		T4	5
ClkMuxSt	36777	1			T2	1		T3	67		T4	9
IdleSt	22531011	1			T1	1529		T2	75		T3	6008
ResetSt	7828780	1			T1	88		T2	86		T3	7007
arcs[ResetSt=>IdleSt]	56322	1			T1	1		T2	1		T3	75
arcs[IdleSt=>ScrapSt]	318	1			T3	3		T4	1		T17	2
arcs[IdleSt=>ClkMuxSt]	36551	1			T2	1		T3	67		T4	5
arcs[ClkMuxSt=>CntIncrSt]	36505	1			T2	1		T3	65		T4	5
arcs[CntIncrSt=>PostTransSt]	1926	1			T5	10		T6	4		T19	12
arcs[CntIncrSt=>CntProgSt]	34517	1			T2	1		T3	64		T4	5
arcs[CntProgSt=>PostTransSt]	4971	1			T5	12		T16	3		T6	13
arcs[CntProgSt=>TransCheckSt]	28422	1			T2	1		T3	52		T4	5
arcs[TransCheckSt=>PostTransSt]	3776	1			T5	10		T28	39		T6	7
arcs[TransCheckSt=>TokenHashSt]	24552	1			T2	1		T3	50		T4	5
arcs[TokenHashSt=>PostTransSt]	10378	1			T2	1		T5	36		T27	83
arcs[TokenHashSt=>FlashRmaSt]	13454	1			T3	30		T4	5		T5	21
arcs[FlashRmaSt=>TokenCheck0St]	13408	1			T3	27		T4	5		T5	21
arcs[TokenCheck0St=>PostTransSt]	3390	1			T5	13		T28	21		T6	10
arcs[TokenCheck0St=>TokenCheck1St]	9963	1			T3	27		T4	5		T5	8
arcs[TokenCheck1St=>PostTransSt]	695	1			T28	16		T21	8		T22	1
arcs[TransProgSt=>PostTransSt]	8464	1			T3	18		T4	5		T5	8
arcs[IdleSt=>EscalateSt]	191	1			T3	4		T17	12		T47	8
arcs[ClkMuxSt=>EscalateSt]	46	1			T3	2		T17	2		T47	2
arcs[CntIncrSt=>EscalateSt]	62	1			T3	1		T17	1		T47	1
arcs[CntProgSt=>EscalateSt]	1124	1			T3	12		T17	23		T47	26
arcs[TransCheckSt=>EscalateSt]	94	1			T3	2		T17	1		T47	1
arcs[TokenHashSt=>EscalateSt]	720	1			T3	20		T17	5		T47	7
arcs[FlashRmaSt=>EscalateSt]	46	1			T3	3		T47	2		T61	2
arcs[TokenCheck0St=>EscalateSt]	55	1			T17	1		T47	3		T61	1
arcs[TokenCheck1St=>EscalateSt]	32	1			T47	2		T61	1		T65	1
arcs[TransProgSt=>EscalateSt]	772	1			T3	9		T17	17		T47	27
arcs[PostTransSt=>EscalateSt]	5308	1			T3	18		T5	12		T16	3
arcs[InvalidSt=>EscalateSt]	14928	1			T6	6		T33	60		T8	13

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7828619	1			T1	88		T2	86		T3	7003
auto[0]	auto[IdleSt]	22530889	1			T1	1529		T2	75		T3	6007
auto[0]	auto[ClkMuxSt]	36753	1			T2	1		T3	66		T4	9
auto[0]	auto[CntIncrSt]	36467	1			T2	1		T3	64		T4	5
auto[0]	auto[CntProgSt]	1595123	1			T2	176		T3	115		T4	83
auto[0]	auto[TransCheckSt]	28361	1			T2	1		T3	52		T4	5
auto[0]	auto[TokenHashSt]	41629898	1			T2	102		T3	382		T4	18361
auto[0]	auto[FlashRmaSt]	38894	1			T3	97		T4	31		T5	33
auto[0]	auto[TokenCheck0St]	13368	1			T3	27		T4	5		T5	21
auto[0]	auto[TokenCheck1St]	9943	1			T3	27		T4	5		T5	8
auto[0]	auto[TransProgSt]	370094	1			T3	40		T4	71		T5	16
auto[0]	auto[PostTransSt]	13130030	1			T2	1078		T3	31		T4	779
auto[0]	auto[ScrapSt]	183656	1			T3	9		T4	45		T17	7
auto[0]	auto[EscalateSt]	5630799	1			T3	5105		T5	906		T16	298
auto[0]	auto[InvalidSt]	12420807	1			T6	975		T33	4348		T8	10880
auto[1]	auto[ResetSt]	161	1			T3	4		T17	1		T47	5
auto[1]	auto[IdleSt]	122	1			T3	1		T17	8		T47	5
auto[1]	auto[ClkMuxSt]	24	1			T3	1		T17	1		T224	1
auto[1]	auto[CntIncrSt]	38	1			T3	1		T17	1		T110	1
auto[1]	auto[CntProgSt]	756	1			T3	11		T17	16		T47	20
auto[1]	auto[TransCheckSt]	61	1			T17	1		T47	1		T61	1
auto[1]	auto[TokenHashSt]	499	1			T3	12		T17	4		T47	3
auto[1]	auto[FlashRmaSt]	35	1			T3	3		T47	1		T61	1
auto[1]	auto[TokenCheck0St]	40	1			T47	3		T61	1		T109	1
auto[1]	auto[TokenCheck1St]	20	1			T61	1		T65	1		T110	1
auto[1]	auto[TransProgSt]	534	1			T3	8		T17	11		T47	13
auto[1]	auto[PostTransSt]	2650	1			T3	10		T5	6		T16	1
auto[1]	auto[ScrapSt]	38	1			T3	3		T17	1		T61	1
auto[1]	auto[EscalateSt]	1433928	1			T3	9964		T5	588		T16	98
auto[1]	auto[InvalidSt]	7432	1			T6	4		T33	32		T8	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7828595	1			T1	88		T2	86		T3	7002
auto[0]	auto[IdleSt]	22530885	1			T1	1529		T2	75		T3	6004
auto[0]	auto[ClkMuxSt]	36744	1			T2	1		T3	66		T4	9
auto[0]	auto[CntIncrSt]	36462	1			T2	1		T3	65		T4	5
auto[0]	auto[CntProgSt]	1595133	1			T2	176		T3	119		T4	83
auto[0]	auto[TransCheckSt]	28367	1			T2	1		T3	50		T4	5
auto[0]	auto[TokenHashSt]	41629936	1			T2	102		T3	380		T4	18361
auto[0]	auto[FlashRmaSt]	38903	1			T3	98		T4	31		T5	33
auto[0]	auto[TokenCheck0St]	13373	1			T3	27		T4	5		T5	21
auto[0]	auto[TokenCheck1St]	9940	1			T3	27		T4	5		T5	8
auto[0]	auto[TransProgSt]	370114	1			T3	42		T4	71		T5	16
auto[0]	auto[PostTransSt]	13129932	1			T2	1078		T3	27		T4	779
auto[0]	auto[ScrapSt]	183653	1			T3	11		T4	45		T17	7
auto[0]	auto[EscalateSt]	5618895	1			T3	4295		T5	906		T16	200
auto[0]	auto[InvalidSt]	12420743	1			T6	977		T33	4352		T8	10871
auto[1]	auto[ResetSt]	185	1			T3	5		T17	3		T47	3
auto[1]	auto[IdleSt]	126	1			T3	4		T17	7		T47	5
auto[1]	auto[ClkMuxSt]	33	1			T3	1		T17	2		T47	2
auto[1]	auto[CntIncrSt]	43	1			T17	1		T47	1		T110	3
auto[1]	auto[CntProgSt]	746	1			T3	7		T17	13		T47	13
auto[1]	auto[TransCheckSt]	55	1			T3	2		T61	2		T109	4
auto[1]	auto[TokenHashSt]	461	1			T3	14		T17	2		T47	4
auto[1]	auto[FlashRmaSt]	26	1			T3	2		T47	1		T61	2
auto[1]	auto[TokenCheck0St]	35	1			T17	1		T47	2		T61	1
auto[1]	auto[TokenCheck1St]	23	1			T47	2		T61	1		T110	1
auto[1]	auto[TransProgSt]	514	1			T3	6		T17	13		T47	18
auto[1]	auto[PostTransSt]	2748	1			T3	14		T5	6		T16	2
auto[1]	auto[ScrapSt]	41	1			T3	1		T17	1		T61	1
auto[1]	auto[EscalateSt]	1445832	1			T3	10774		T5	588		T16	196
auto[1]	auto[InvalidSt]	7496	1			T6	2		T33	28		T8	11