Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52850 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1829 |
1 |
|
|
T15 |
7 |
|
T16 |
8 |
|
T17 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53930 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
749 |
1 |
|
|
T53 |
20 |
|
T23 |
18 |
|
T54 |
11 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52767 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
12 |
auto[1] |
1912 |
1 |
|
|
T3 |
2 |
|
T36 |
17 |
|
T19 |
36 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52743 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
12 |
auto[1] |
1936 |
1 |
|
|
T3 |
2 |
|
T9 |
4 |
|
T36 |
11 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52843 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
12 |
auto[1] |
1836 |
1 |
|
|
T3 |
2 |
|
T9 |
1 |
|
T36 |
9 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49318 |
1 |
|
|
T3 |
10 |
|
T9 |
7 |
|
T15 |
51 |
no_err_inj |
5361 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
4 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52807 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1872 |
1 |
|
|
T15 |
6 |
|
T16 |
16 |
|
T17 |
12 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53847 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
832 |
1 |
|
|
T53 |
9 |
|
T23 |
24 |
|
T54 |
15 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37647 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[1] |
17032 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
587 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52780 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
13 |
auto[1] |
1899 |
1 |
|
|
T3 |
1 |
|
T36 |
4 |
|
T19 |
35 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52785 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
12 |
auto[1] |
1894 |
1 |
|
|
T3 |
2 |
|
T9 |
1 |
|
T36 |
11 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52790 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1889 |
1 |
|
|
T9 |
1 |
|
T36 |
15 |
|
T19 |
45 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52897 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1782 |
1 |
|
|
T15 |
2 |
|
T16 |
12 |
|
T17 |
11 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52091 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
2588 |
1 |
|
|
T37 |
18 |
|
T19 |
129 |
|
T24 |
15 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53950 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
729 |
1 |
|
|
T53 |
10 |
|
T23 |
10 |
|
T54 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53891 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
788 |
1 |
|
|
T53 |
12 |
|
T23 |
15 |
|
T54 |
10 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53913 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
766 |
1 |
|
|
T53 |
14 |
|
T23 |
12 |
|
T54 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52155 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T10 |
6 |
auto[1] |
2524 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T19 |
62 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51090 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
3589 |
1 |
|
|
T45 |
70 |
|
T20 |
54 |
|
T43 |
66 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52761 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
13 |
auto[1] |
1918 |
1 |
|
|
T3 |
1 |
|
T36 |
13 |
|
T19 |
33 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52810 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1869 |
1 |
|
|
T36 |
11 |
|
T19 |
40 |
|
T75 |
12 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52681 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1998 |
1 |
|
|
T36 |
9 |
|
T19 |
41 |
|
T75 |
17 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52784 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1895 |
1 |
|
|
T15 |
2 |
|
T16 |
10 |
|
T17 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49118 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
5561 |
1 |
|
|
T15 |
8 |
|
T16 |
10 |
|
T17 |
10 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51015 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
3664 |
1 |
|
|
T21 |
90 |
|
T18 |
86 |
|
T52 |
92 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54679 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52868 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1811 |
1 |
|
|
T15 |
12 |
|
T16 |
11 |
|
T17 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52809 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1870 |
1 |
|
|
T15 |
8 |
|
T16 |
16 |
|
T17 |
11 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52837 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T3 |
14 |
auto[1] |
1842 |
1 |
|
|
T15 |
6 |
|
T16 |
10 |
|
T17 |
11 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48029 |
1 |
|
|
T15 |
51 |
|
T21 |
90 |
|
T18 |
86 |
auto[0] |
no_err_inj |
4126 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T10 |
6 |
auto[1] |
err_inj |
1289 |
1 |
|
|
T3 |
10 |
|
T9 |
7 |
|
T19 |
38 |
auto[1] |
no_err_inj |
1235 |
1 |
|
|
T3 |
4 |
|
T9 |
5 |
|
T19 |
24 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50430 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T10 |
6 |
auto[0] |
auto[1] |
1725 |
1 |
|
|
T36 |
11 |
|
T19 |
35 |
|
T75 |
12 |
auto[1] |
auto[0] |
2380 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T19 |
57 |
auto[1] |
auto[1] |
144 |
1 |
|
|
T19 |
5 |
|
T39 |
6 |
|
T40 |
5 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50388 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T10 |
6 |
auto[0] |
auto[1] |
1767 |
1 |
|
|
T36 |
11 |
|
T19 |
37 |
|
T75 |
11 |
auto[1] |
auto[0] |
2397 |
1 |
|
|
T3 |
12 |
|
T9 |
11 |
|
T19 |
61 |
auto[1] |
auto[1] |
127 |
1 |
|
|
T3 |
2 |
|
T9 |
1 |
|
T19 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50308 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T10 |
6 |
auto[0] |
auto[1] |
1847 |
1 |
|
|
T36 |
9 |
|
T19 |
32 |
|
T75 |
17 |
auto[1] |
auto[0] |
2373 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T19 |
53 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T19 |
9 |
|
T22 |
2 |
|
T83 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50358 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T10 |
6 |
auto[0] |
auto[1] |
1797 |
1 |
|
|
T36 |
11 |
|
T19 |
36 |
|
T75 |
8 |
auto[1] |
auto[0] |
2385 |
1 |
|
|
T3 |
12 |
|
T9 |
8 |
|
T19 |
58 |
auto[1] |
auto[1] |
139 |
1 |
|
|
T3 |
2 |
|
T9 |
4 |
|
T19 |
4 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50476 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T10 |
6 |
auto[0] |
auto[1] |
1679 |
1 |
|
|
T36 |
9 |
|
T19 |
30 |
|
T75 |
7 |
auto[1] |
auto[0] |
2367 |
1 |
|
|
T3 |
12 |
|
T9 |
11 |
|
T19 |
56 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T3 |
2 |
|
T9 |
1 |
|
T19 |
6 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50393 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T10 |
6 |
auto[0] |
auto[1] |
1762 |
1 |
|
|
T36 |
17 |
|
T19 |
32 |
|
T75 |
12 |
auto[1] |
auto[0] |
2374 |
1 |
|
|
T3 |
12 |
|
T9 |
12 |
|
T19 |
58 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T3 |
2 |
|
T19 |
4 |
|
T22 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36582 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1065 |
1 |
|
|
T15 |
7 |
|
T16 |
8 |
|
T17 |
9 |
auto[1] |
auto[0] |
16268 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
544 |
auto[1] |
auto[1] |
764 |
1 |
|
|
T19 |
43 |
|
T25 |
4 |
|
T27 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36583 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1064 |
1 |
|
|
T15 |
6 |
|
T16 |
16 |
|
T17 |
12 |
auto[1] |
auto[0] |
16224 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
546 |
auto[1] |
auto[1] |
808 |
1 |
|
|
T19 |
41 |
|
T25 |
12 |
|
T27 |
11 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36175 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1472 |
1 |
|
|
T37 |
18 |
|
T19 |
70 |
|
T24 |
15 |
auto[1] |
auto[0] |
15916 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
528 |
auto[1] |
auto[1] |
1116 |
1 |
|
|
T19 |
59 |
|
T22 |
25 |
|
T39 |
43 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36642 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1005 |
1 |
|
|
T15 |
2 |
|
T16 |
12 |
|
T17 |
11 |
auto[1] |
auto[0] |
16255 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
546 |
auto[1] |
auto[1] |
777 |
1 |
|
|
T19 |
41 |
|
T25 |
6 |
|
T27 |
14 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32874 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
4773 |
1 |
|
|
T15 |
8 |
|
T16 |
10 |
|
T17 |
10 |
auto[1] |
auto[0] |
16244 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
541 |
auto[1] |
auto[1] |
788 |
1 |
|
|
T19 |
46 |
|
T25 |
6 |
|
T27 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36546 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1101 |
1 |
|
|
T36 |
11 |
|
T19 |
28 |
|
T75 |
12 |
auto[1] |
auto[0] |
16264 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
575 |
auto[1] |
auto[1] |
768 |
1 |
|
|
T19 |
12 |
|
T81 |
8 |
|
T39 |
13 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36542 |
1 |
|
|
T3 |
13 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1105 |
1 |
|
|
T3 |
1 |
|
T36 |
13 |
|
T19 |
17 |
auto[1] |
auto[0] |
16219 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
571 |
auto[1] |
auto[1] |
813 |
1 |
|
|
T19 |
16 |
|
T22 |
1 |
|
T81 |
8 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36468 |
1 |
|
|
T3 |
12 |
|
T9 |
11 |
|
T10 |
6 |
auto[0] |
auto[1] |
1179 |
1 |
|
|
T3 |
2 |
|
T9 |
1 |
|
T36 |
11 |
auto[1] |
auto[0] |
16317 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
579 |
auto[1] |
auto[1] |
715 |
1 |
|
|
T19 |
8 |
|
T26 |
2 |
|
T81 |
12 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36534 |
1 |
|
|
T3 |
13 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T3 |
1 |
|
T36 |
4 |
|
T19 |
26 |
auto[1] |
auto[0] |
16246 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
578 |
auto[1] |
auto[1] |
786 |
1 |
|
|
T19 |
9 |
|
T22 |
3 |
|
T26 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36549 |
1 |
|
|
T3 |
12 |
|
T9 |
8 |
|
T10 |
6 |
auto[0] |
auto[1] |
1098 |
1 |
|
|
T3 |
2 |
|
T9 |
4 |
|
T36 |
11 |
auto[1] |
auto[0] |
16194 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
574 |
auto[1] |
auto[1] |
838 |
1 |
|
|
T19 |
13 |
|
T26 |
3 |
|
T81 |
11 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36547 |
1 |
|
|
T3 |
12 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1100 |
1 |
|
|
T3 |
2 |
|
T36 |
17 |
|
T19 |
27 |
auto[1] |
auto[0] |
16220 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
578 |
auto[1] |
auto[1] |
812 |
1 |
|
|
T19 |
9 |
|
T81 |
10 |
|
T39 |
12 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36599 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1048 |
1 |
|
|
T15 |
6 |
|
T16 |
10 |
|
T17 |
11 |
auto[1] |
auto[0] |
16238 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
530 |
auto[1] |
auto[1] |
794 |
1 |
|
|
T19 |
57 |
|
T25 |
6 |
|
T27 |
16 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36577 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T10 |
6 |
auto[0] |
auto[1] |
1070 |
1 |
|
|
T15 |
8 |
|
T16 |
16 |
|
T17 |
11 |
auto[1] |
auto[0] |
16232 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
537 |
auto[1] |
auto[1] |
800 |
1 |
|
|
T19 |
50 |
|
T25 |
9 |
|
T27 |
15 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36254 |
1 |
|
|
T10 |
6 |
|
T13 |
8 |
|
T14 |
10 |
auto[0] |
auto[1] |
1393 |
1 |
|
|
T3 |
14 |
|
T9 |
12 |
|
T22 |
15 |
auto[1] |
auto[0] |
15901 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T19 |
525 |
auto[1] |
auto[1] |
1131 |
1 |
|
|
T19 |
62 |
|
T22 |
15 |
|
T26 |
15 |