Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114201961

1

T1

92330

T2

7267

T3

11638

auto[1]

1379843

1

T3

297

T9

198

T15

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114184961

1

T1

92330

T2

7267

T3

11242

auto[1]

1396843

1

T3

693

T9

396

T15

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7423231	1			T1	654		T2	250		T3	1416
auto[IdleSt]	22394361	1			T1	14183		T2	5877		T3	1712
auto[ClkMuxSt]	36404	1			T1	7		T2	3		T3	4
auto[CntIncrSt]	36202	1			T1	7		T2	3		T3	4
auto[CntProgSt]	1861494	1			T1	14		T2	60		T3	26
auto[TransCheckSt]	28225	1			T1	7		T2	3		T3	4
auto[TokenHashSt]	51502196	1			T1	75011		T2	34		T3	2763
auto[FlashRmaSt]	36300	1			T1	7		T2	3		T3	52
auto[TokenCheck0St]	13215	1			T1	7		T2	3		T3	4
auto[TokenCheck1St]	9868	1			T1	7		T2	3		T3	4
auto[TransProgSt]	528673	1			T1	14		T2	32		T3	41
auto[PostTransSt]	13413464	1			T1	2412		T2	996		T3	1208
auto[ScrapSt]	192579	1			T13	10		T14	1013		T38	38
auto[EscalateSt]	6726130	1			T3	2926		T9	1090		T15	843
auto[InvalidSt]	11377496	1			T3	1769		T9	512		T36	10598

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1966	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11377496	1			T3	1769		T9	512		T36	10598
EscalateSt	6726130	1			T3	2926		T9	1090		T15	843
ScrapSt	192579	1			T13	10		T14	1013		T38	38
PostTransSt	13413464	1			T1	2412		T2	996		T3	1208
TransProgSt	528673	1			T1	14		T2	32		T3	41
TokenCheck1St	9868	1			T1	7		T2	3		T3	4
TokenCheck0St	13215	1			T1	7		T2	3		T3	4
FlashRmaSt	36300	1			T1	7		T2	3		T3	52
TokenHashSt	51502196	1			T1	75011		T2	34		T3	2763
TransCheckSt	28225	1			T1	7		T2	3		T3	4
CntProgSt	1861494	1			T1	14		T2	60		T3	26
CntIncrSt	36202	1			T1	7		T2	3		T3	4
ClkMuxSt	36404	1			T1	7		T2	3		T3	4
IdleSt	22394361	1			T1	14183		T2	5877		T3	1712
ResetSt	7423231	1			T1	654		T2	250		T3	1416
arcs[ResetSt=>IdleSt]	54978	1			T1	7		T2	3		T3	15
arcs[IdleSt=>ScrapSt]	308	1			T13	1		T14	2		T38	1
arcs[IdleSt=>ClkMuxSt]	36247	1			T1	7		T2	3		T3	4
arcs[ClkMuxSt=>CntIncrSt]	36202	1			T1	7		T2	3		T3	4
arcs[CntIncrSt=>PostTransSt]	1872	1			T15	8		T16	16		T17	11
arcs[CntIncrSt=>CntProgSt]	34273	1			T1	7		T2	3		T3	4
arcs[CntProgSt=>PostTransSt]	5116	1			T15	7		T16	8		T17	8
arcs[CntProgSt=>TransCheckSt]	28225	1			T1	7		T2	3		T3	4
arcs[TransCheckSt=>PostTransSt]	3713	1			T15	6		T21	44		T18	48
arcs[TransCheckSt=>TokenHashSt]	24390	1			T1	7		T2	3		T3	4
arcs[TokenHashSt=>PostTransSt]	10316	1			T11	1		T12	1		T15	22
arcs[TokenHashSt=>FlashRmaSt]	13247	1			T1	7		T2	3		T3	4
arcs[FlashRmaSt=>TokenCheck0St]	13215	1			T1	7		T2	3		T3	4
arcs[TokenCheck0St=>PostTransSt]	3295	1			T15	6		T21	22		T18	20
arcs[TokenCheck0St=>TokenCheck1St]	9868	1			T1	7		T2	3		T3	4
arcs[TokenCheck1St=>PostTransSt]	682	1			T21	15		T18	10		T16	1
arcs[TransProgSt=>PostTransSt]	8414	1			T1	7		T2	3		T3	4
arcs[IdleSt=>EscalateSt]	135	1			T20	1		T43	3		T48	6
arcs[ClkMuxSt=>EscalateSt]	45	1			T20	2		T43	2		T44	1
arcs[CntIncrSt=>EscalateSt]	57	1			T45	1		T46	3		T47	1
arcs[CntProgSt=>EscalateSt]	932	1			T45	30		T20	6		T43	26
arcs[TransCheckSt=>EscalateSt]	122	1			T45	1		T20	6		T46	5
arcs[TokenHashSt=>EscalateSt]	827	1			T45	6		T20	20		T43	5
arcs[FlashRmaSt=>EscalateSt]	32	1			T45	1		T43	1		T46	1
arcs[TokenCheck0St=>EscalateSt]	52	1			T43	1		T46	1		T47	1
arcs[TokenCheck1St=>EscalateSt]	28	1			T43	1		T46	1		T48	2
arcs[TransProgSt=>EscalateSt]	744	1			T45	26		T20	7		T43	17
arcs[PostTransSt=>EscalateSt]	5505	1			T15	7		T16	8		T17	9
arcs[InvalidSt=>EscalateSt]	14064	1			T3	10		T9	6		T36	76

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7423080	1			T1	654		T2	250		T3	1416
auto[0]	auto[IdleSt]	22394276	1			T1	14183		T2	5877		T3	1712
auto[0]	auto[ClkMuxSt]	36374	1			T1	7		T2	3		T3	4
auto[0]	auto[CntIncrSt]	36167	1			T1	7		T2	3		T3	4
auto[0]	auto[CntProgSt]	1860869	1			T1	14		T2	60		T3	26
auto[0]	auto[TransCheckSt]	28143	1			T1	7		T2	3		T3	4
auto[0]	auto[TokenHashSt]	51501655	1			T1	75011		T2	34		T3	2763
auto[0]	auto[FlashRmaSt]	36275	1			T1	7		T2	3		T3	52
auto[0]	auto[TokenCheck0St]	13179	1			T1	7		T2	3		T3	4
auto[0]	auto[TokenCheck1St]	9852	1			T1	7		T2	3		T3	4
auto[0]	auto[TransProgSt]	528175	1			T1	14		T2	32		T3	41
auto[0]	auto[PostTransSt]	13410702	1			T1	2412		T2	996		T3	1208
auto[0]	auto[ScrapSt]	192539	1			T13	10		T14	1013		T38	38
auto[0]	auto[EscalateSt]	5358215	1			T3	2632		T9	894		T15	549
auto[0]	auto[InvalidSt]	11370494	1			T3	1766		T9	510		T36	10565
auto[1]	auto[ResetSt]	151	1			T45	3		T20	2		T43	4
auto[1]	auto[IdleSt]	85	1			T20	1		T43	1		T48	3
auto[1]	auto[ClkMuxSt]	30	1			T20	1		T43	1		T189	1
auto[1]	auto[CntIncrSt]	35	1			T45	1		T46	2		T44	1
auto[1]	auto[CntProgSt]	625	1			T45	19		T20	4		T43	19
auto[1]	auto[TransCheckSt]	82	1			T45	1		T20	4		T46	5
auto[1]	auto[TokenHashSt]	541	1			T45	3		T20	14		T43	4
auto[1]	auto[FlashRmaSt]	25	1			T45	1		T43	1		T46	1
auto[1]	auto[TokenCheck0St]	36	1			T46	1		T47	1		T48	1
auto[1]	auto[TokenCheck1St]	16	1			T43	1		T46	1		T48	2
auto[1]	auto[TransProgSt]	498	1			T45	13		T20	3		T43	12
auto[1]	auto[PostTransSt]	2762	1			T15	3		T16	5		T17	3
auto[1]	auto[ScrapSt]	40	1			T43	1		T44	2		T190	3
auto[1]	auto[EscalateSt]	1367915	1			T3	294		T9	196		T15	294
auto[1]	auto[InvalidSt]	7002	1			T3	3		T9	2		T36	33

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7423080	1			T1	654		T2	250		T3	1416
auto[0]	auto[IdleSt]	22394267	1			T1	14183		T2	5877		T3	1712
auto[0]	auto[ClkMuxSt]	36377	1			T1	7		T2	3		T3	4
auto[0]	auto[CntIncrSt]	36164	1			T1	7		T2	3		T3	4
auto[0]	auto[CntProgSt]	1860874	1			T1	14		T2	60		T3	26
auto[0]	auto[TransCheckSt]	28140	1			T1	7		T2	3		T3	4
auto[0]	auto[TokenHashSt]	51501654	1			T1	75011		T2	34		T3	2763
auto[0]	auto[FlashRmaSt]	36282	1			T1	7		T2	3		T3	52
auto[0]	auto[TokenCheck0St]	13184	1			T1	7		T2	3		T3	4
auto[0]	auto[TokenCheck1St]	9847	1			T1	7		T2	3		T3	4
auto[0]	auto[TransProgSt]	528172	1			T1	14		T2	32		T3	41
auto[0]	auto[PostTransSt]	13410596	1			T1	2412		T2	996		T3	1208
auto[0]	auto[ScrapSt]	192547	1			T13	10		T14	1013		T38	38
auto[0]	auto[EscalateSt]	5341377	1			T3	2240		T9	698		T15	451
auto[0]	auto[InvalidSt]	11370434	1			T3	1762		T9	508		T36	10555
auto[1]	auto[ResetSt]	151	1			T45	3		T20	2		T43	5
auto[1]	auto[IdleSt]	94	1			T43	2		T48	5		T44	4
auto[1]	auto[ClkMuxSt]	27	1			T20	1		T43	2		T44	1
auto[1]	auto[CntIncrSt]	38	1			T46	3		T47	1		T190	1
auto[1]	auto[CntProgSt]	620	1			T45	21		T20	5		T43	12
auto[1]	auto[TransCheckSt]	85	1			T45	1		T20	4		T46	2
auto[1]	auto[TokenHashSt]	542	1			T45	4		T20	12		T43	4
auto[1]	auto[FlashRmaSt]	18	1			T191	1		T192	2		T193	1
auto[1]	auto[TokenCheck0St]	31	1			T43	1		T46	1		T48	2
auto[1]	auto[TokenCheck1St]	21	1			T46	1		T190	2		T194	1
auto[1]	auto[TransProgSt]	501	1			T45	21		T20	5		T43	13
auto[1]	auto[PostTransSt]	2868	1			T15	4		T16	3		T17	6
auto[1]	auto[ScrapSt]	32	1			T43	1		T48	1		T49	1
auto[1]	auto[EscalateSt]	1384753	1			T3	686		T9	392		T15	392
auto[1]	auto[InvalidSt]	7062	1			T3	7		T9	4		T36	43