Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57468 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
65 | 
 | 
T3 | 
68 | 
| auto[1] | 
2304 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T9 | 
6 | 
 | 
T10 | 
9 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58997 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
775 | 
1 | 
 | 
 | 
T11 | 
22 | 
 | 
T58 | 
10 | 
 | 
T37 | 
18 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57708 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2064 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T19 | 
8 | 
 | 
T17 | 
1 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57718 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2054 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T19 | 
12 | 
 | 
T17 | 
1 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57664 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2108 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T19 | 
8 | 
 | 
T17 | 
2 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
54239 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| no_err_inj | 
5533 | 
1 | 
 | 
 | 
T18 | 
7 | 
 | 
T17 | 
6 | 
 | 
T21 | 
7 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57519 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
66 | 
 | 
T3 | 
68 | 
| auto[1] | 
2253 | 
1 | 
 | 
 | 
T2 | 
10 | 
 | 
T9 | 
9 | 
 | 
T10 | 
10 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58987 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
785 | 
1 | 
 | 
 | 
T11 | 
11 | 
 | 
T58 | 
21 | 
 | 
T37 | 
23 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39977 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[1] | 
19795 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
59 | 
 | 
T8 | 
13 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57647 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2125 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T19 | 
12 | 
 | 
T43 | 
8 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57691 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2081 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T19 | 
11 | 
 | 
T17 | 
1 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57626 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2146 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T19 | 
9 | 
 | 
T17 | 
1 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57452 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
67 | 
 | 
T3 | 
68 | 
| auto[1] | 
2320 | 
1 | 
 | 
 | 
T2 | 
9 | 
 | 
T9 | 
10 | 
 | 
T10 | 
6 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57592 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2180 | 
1 | 
 | 
 | 
T8 | 
13 | 
 | 
T20 | 
19 | 
 | 
T56 | 
19 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58919 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
853 | 
1 | 
 | 
 | 
T11 | 
21 | 
 | 
T58 | 
21 | 
 | 
T37 | 
19 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
59017 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
755 | 
1 | 
 | 
 | 
T11 | 
15 | 
 | 
T58 | 
19 | 
 | 
T37 | 
17 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58990 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
782 | 
1 | 
 | 
 | 
T11 | 
15 | 
 | 
T58 | 
17 | 
 | 
T37 | 
21 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56812 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2960 | 
1 | 
 | 
 | 
T17 | 
14 | 
 | 
T21 | 
10 | 
 | 
T23 | 
15 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55944 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
3828 | 
1 | 
 | 
 | 
T31 | 
53 | 
 | 
T44 | 
56 | 
 | 
T46 | 
89 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57638 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2134 | 
1 | 
 | 
 | 
T4 | 
10 | 
 | 
T19 | 
9 | 
 | 
T43 | 
7 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57636 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2136 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T19 | 
12 | 
 | 
T17 | 
2 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57693 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[1] | 
2079 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T19 | 
11 | 
 | 
T43 | 
12 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57626 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
67 | 
 | 
T3 | 
68 | 
| auto[1] | 
2146 | 
1 | 
 | 
 | 
T2 | 
9 | 
 | 
T9 | 
12 | 
 | 
T10 | 
7 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53899 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
65 | 
 | 
T4 | 
59 | 
| auto[1] | 
5873 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T3 | 
68 | 
 | 
T9 | 
11 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55942 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
 | 
T4 | 
59 | 
| auto[1] | 
3830 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T16 | 
93 | 
 | 
T57 | 
85 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
59772 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57566 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
68 | 
 | 
T3 | 
68 | 
| auto[1] | 
2206 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T9 | 
11 | 
 | 
T10 | 
10 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57540 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
68 | 
 | 
T3 | 
68 | 
| auto[1] | 
2232 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T9 | 
9 | 
 | 
T10 | 
6 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57582 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
66 | 
 | 
T3 | 
68 | 
| auto[1] | 
2190 | 
1 | 
 | 
 | 
T2 | 
10 | 
 | 
T9 | 
14 | 
 | 
T10 | 
7 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
52743 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[0] | 
no_err_inj | 
4069 | 
1 | 
 | 
 | 
T18 | 
7 | 
 | 
T34 | 
7 | 
 | 
T53 | 
19 | 
| auto[1] | 
err_inj | 
1496 | 
1 | 
 | 
 | 
T17 | 
8 | 
 | 
T21 | 
3 | 
 | 
T23 | 
7 | 
| auto[1] | 
no_err_inj | 
1464 | 
1 | 
 | 
 | 
T17 | 
6 | 
 | 
T21 | 
7 | 
 | 
T23 | 
8 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54826 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[0] | 
auto[1] | 
1986 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T19 | 
12 | 
 | 
T43 | 
15 | 
| auto[1] | 
auto[0] | 
2810 | 
1 | 
 | 
 | 
T17 | 
12 | 
 | 
T21 | 
10 | 
 | 
T23 | 
15 | 
| auto[1] | 
auto[1] | 
150 | 
1 | 
 | 
 | 
T17 | 
2 | 
 | 
T64 | 
1 | 
 | 
T34 | 
1 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54898 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[0] | 
auto[1] | 
1914 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T19 | 
11 | 
 | 
T43 | 
11 | 
| auto[1] | 
auto[0] | 
2793 | 
1 | 
 | 
 | 
T17 | 
13 | 
 | 
T21 | 
9 | 
 | 
T23 | 
15 | 
| auto[1] | 
auto[1] | 
167 | 
1 | 
 | 
 | 
T17 | 
1 | 
 | 
T21 | 
1 | 
 | 
T64 | 
1 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54888 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[0] | 
auto[1] | 
1924 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T19 | 
11 | 
 | 
T43 | 
12 | 
| auto[1] | 
auto[0] | 
2805 | 
1 | 
 | 
 | 
T17 | 
14 | 
 | 
T21 | 
10 | 
 | 
T23 | 
14 | 
| auto[1] | 
auto[1] | 
155 | 
1 | 
 | 
 | 
T23 | 
1 | 
 | 
T64 | 
2 | 
 | 
T88 | 
1 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54907 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[0] | 
auto[1] | 
1905 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T19 | 
12 | 
 | 
T43 | 
7 | 
| auto[1] | 
auto[0] | 
2811 | 
1 | 
 | 
 | 
T17 | 
13 | 
 | 
T21 | 
10 | 
 | 
T23 | 
15 | 
| auto[1] | 
auto[1] | 
149 | 
1 | 
 | 
 | 
T17 | 
1 | 
 | 
T78 | 
1 | 
 | 
T32 | 
1 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54886 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[0] | 
auto[1] | 
1926 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T19 | 
8 | 
 | 
T43 | 
10 | 
| auto[1] | 
auto[0] | 
2778 | 
1 | 
 | 
 | 
T17 | 
12 | 
 | 
T21 | 
9 | 
 | 
T23 | 
14 | 
| auto[1] | 
auto[1] | 
182 | 
1 | 
 | 
 | 
T17 | 
2 | 
 | 
T21 | 
1 | 
 | 
T23 | 
1 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54911 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T2 | 
76 | 
 | 
T3 | 
68 | 
| auto[0] | 
auto[1] | 
1901 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T19 | 
8 | 
 | 
T43 | 
5 | 
| auto[1] | 
auto[0] | 
2797 | 
1 | 
 | 
 | 
T17 | 
13 | 
 | 
T21 | 
9 | 
 | 
T23 | 
13 | 
| auto[1] | 
auto[1] | 
163 | 
1 | 
 | 
 | 
T17 | 
1 | 
 | 
T21 | 
1 | 
 | 
T23 | 
2 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38703 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
76 | 
| auto[0] | 
auto[1] | 
1274 | 
1 | 
 | 
 | 
T9 | 
6 | 
 | 
T10 | 
9 | 
 | 
T15 | 
18 | 
| auto[1] | 
auto[0] | 
18765 | 
1 | 
 | 
 | 
T2 | 
65 | 
 | 
T4 | 
59 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
1030 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T22 | 
16 | 
 | 
T34 | 
14 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38682 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
73 | 
| auto[0] | 
auto[1] | 
1295 | 
1 | 
 | 
 | 
T9 | 
9 | 
 | 
T10 | 
10 | 
 | 
T15 | 
12 | 
| auto[1] | 
auto[0] | 
18837 | 
1 | 
 | 
 | 
T2 | 
66 | 
 | 
T4 | 
59 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
958 | 
1 | 
 | 
 | 
T2 | 
10 | 
 | 
T22 | 
7 | 
 | 
T34 | 
14 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38648 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[0] | 
auto[1] | 
1329 | 
1 | 
 | 
 | 
T56 | 
19 | 
 | 
T205 | 
15 | 
 | 
T32 | 
2 | 
| auto[1] | 
auto[0] | 
18944 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
59 | 
 | 
T17 | 
14 | 
| auto[1] | 
auto[1] | 
851 | 
1 | 
 | 
 | 
T8 | 
13 | 
 | 
T20 | 
19 | 
 | 
T206 | 
18 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38674 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
72 | 
| auto[0] | 
auto[1] | 
1303 | 
1 | 
 | 
 | 
T9 | 
10 | 
 | 
T10 | 
6 | 
 | 
T15 | 
12 | 
| auto[1] | 
auto[0] | 
18778 | 
1 | 
 | 
 | 
T2 | 
67 | 
 | 
T4 | 
59 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
1017 | 
1 | 
 | 
 | 
T2 | 
9 | 
 | 
T22 | 
6 | 
 | 
T34 | 
13 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
35033 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T9 | 
71 | 
 | 
T10 | 
55 | 
| auto[0] | 
auto[1] | 
4944 | 
1 | 
 | 
 | 
T3 | 
68 | 
 | 
T9 | 
11 | 
 | 
T10 | 
11 | 
| auto[1] | 
auto[0] | 
18866 | 
1 | 
 | 
 | 
T2 | 
65 | 
 | 
T4 | 
59 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
929 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T22 | 
10 | 
 | 
T34 | 
10 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38851 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[0] | 
auto[1] | 
1126 | 
1 | 
 | 
 | 
T19 | 
12 | 
 | 
T43 | 
15 | 
 | 
T64 | 
1 | 
| auto[1] | 
auto[0] | 
18785 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
51 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
1010 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T17 | 
2 | 
 | 
T34 | 
1 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38824 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[0] | 
auto[1] | 
1153 | 
1 | 
 | 
 | 
T19 | 
9 | 
 | 
T43 | 
7 | 
 | 
T64 | 
1 | 
| auto[1] | 
auto[0] | 
18814 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
49 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
981 | 
1 | 
 | 
 | 
T4 | 
10 | 
 | 
T23 | 
1 | 
 | 
T84 | 
5 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38852 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[0] | 
auto[1] | 
1125 | 
1 | 
 | 
 | 
T19 | 
11 | 
 | 
T43 | 
11 | 
 | 
T64 | 
1 | 
| auto[1] | 
auto[0] | 
18839 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
55 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
956 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T17 | 
1 | 
 | 
T21 | 
1 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38832 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[0] | 
auto[1] | 
1145 | 
1 | 
 | 
 | 
T19 | 
12 | 
 | 
T43 | 
8 | 
 | 
T76 | 
14 | 
| auto[1] | 
auto[0] | 
18815 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
52 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
980 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T23 | 
1 | 
 | 
T34 | 
1 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38843 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[0] | 
auto[1] | 
1134 | 
1 | 
 | 
 | 
T19 | 
12 | 
 | 
T43 | 
7 | 
 | 
T76 | 
11 | 
| auto[1] | 
auto[0] | 
18875 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
52 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
920 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T17 | 
1 | 
 | 
T32 | 
1 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38855 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[0] | 
auto[1] | 
1122 | 
1 | 
 | 
 | 
T19 | 
8 | 
 | 
T43 | 
5 | 
 | 
T76 | 
8 | 
| auto[1] | 
auto[0] | 
18853 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
55 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
942 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T17 | 
1 | 
 | 
T21 | 
1 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38760 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
68 | 
| auto[0] | 
auto[1] | 
1217 | 
1 | 
 | 
 | 
T9 | 
14 | 
 | 
T10 | 
7 | 
 | 
T15 | 
10 | 
| auto[1] | 
auto[0] | 
18822 | 
1 | 
 | 
 | 
T2 | 
66 | 
 | 
T4 | 
59 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
973 | 
1 | 
 | 
 | 
T2 | 
10 | 
 | 
T22 | 
8 | 
 | 
T34 | 
10 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38689 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
73 | 
| auto[0] | 
auto[1] | 
1288 | 
1 | 
 | 
 | 
T9 | 
9 | 
 | 
T10 | 
6 | 
 | 
T15 | 
12 | 
| auto[1] | 
auto[0] | 
18851 | 
1 | 
 | 
 | 
T2 | 
68 | 
 | 
T4 | 
59 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
944 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T22 | 
9 | 
 | 
T34 | 
15 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38318 | 
1 | 
 | 
 | 
T1 | 
52 | 
 | 
T3 | 
68 | 
 | 
T9 | 
82 | 
| auto[0] | 
auto[1] | 
1659 | 
1 | 
 | 
 | 
T64 | 
11 | 
 | 
T78 | 
10 | 
 | 
T92 | 
12 | 
| auto[1] | 
auto[0] | 
18494 | 
1 | 
 | 
 | 
T2 | 
76 | 
 | 
T4 | 
59 | 
 | 
T8 | 
13 | 
| auto[1] | 
auto[1] | 
1301 | 
1 | 
 | 
 | 
T17 | 
14 | 
 | 
T21 | 
10 | 
 | 
T23 | 
15 |