Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130217281

1

T1

16773

T2

187486

T3

93399

auto[1]

1499932

1

T2

297

T4

2156

T9

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130220771

1

T1

16773

T2

186991

T3

93399

auto[1]

1496442

1

T2

792

T4

2548

T9

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8365248	1			T1	4918		T2	8258		T3	7363
auto[IdleSt]	25668970	1			T1	1986		T2	92465		T3	2183
auto[ClkMuxSt]	39846	1			T1	52		T2	76		T3	68
auto[CntIncrSt]	39533	1			T1	52		T2	76		T3	68
auto[CntProgSt]	1728127	1			T1	1182		T2	3873		T3	36039
auto[TransCheckSt]	30938	1			T1	52		T2	57		T3	68
auto[TokenHashSt]	58056572	1			T1	448		T2	1951		T3	37227
auto[FlashRmaSt]	40503	1			T1	70		T2	47		T9	48
auto[TokenCheck0St]	14607	1			T1	19		T2	19		T9	19
auto[TokenCheck1St]	10781	1			T1	11		T2	11		T9	10
auto[TransProgSt]	494362	1			T2	495		T9	350		T10	12
auto[PostTransSt]	15704168	1			T1	7983		T2	75081		T3	10383
auto[ScrapSt]	119743	1			T31	4		T32	48		T33	28
auto[EscalateSt]	7641770	1			T2	5374		T4	28121		T9	749
auto[InvalidSt]	13759881	1			T4	104048		T11	2665		T19	5488

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2164	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13759881	1			T4	104048		T11	2665		T19	5488
EscalateSt	7641770	1			T2	5374		T4	28121		T9	749
ScrapSt	119743	1			T31	4		T32	48		T33	28
PostTransSt	15704168	1			T1	7983		T2	75081		T3	10383
TransProgSt	494362	1			T2	495		T9	350		T10	12
TokenCheck1St	10781	1			T1	11		T2	11		T9	10
TokenCheck0St	14607	1			T1	19		T2	19		T9	19
FlashRmaSt	40503	1			T1	70		T2	47		T9	48
TokenHashSt	58056572	1			T1	448		T2	1951		T3	37227
TransCheckSt	30938	1			T1	52		T2	57		T3	68
CntProgSt	1728127	1			T1	1182		T2	3873		T3	36039
CntIncrSt	39533	1			T1	52		T2	76		T3	68
ClkMuxSt	39846	1			T1	52		T2	76		T3	68
IdleSt	25668970	1			T1	1986		T2	92465		T3	2183
ResetSt	8365248	1			T1	4918		T2	8258		T3	7363
arcs[ResetSt=>IdleSt]	59936	1			T1	53		T2	77		T3	69
arcs[IdleSt=>ScrapSt]	300	1			T31	1		T32	1		T33	1
arcs[IdleSt=>ClkMuxSt]	39565	1			T1	52		T2	76		T3	68
arcs[ClkMuxSt=>CntIncrSt]	39533	1			T1	52		T2	76		T3	68
arcs[CntIncrSt=>PostTransSt]	2232	1			T2	8		T9	9		T10	6
arcs[CntIncrSt=>CntProgSt]	37241	1			T1	52		T2	68		T3	68
arcs[CntProgSt=>PostTransSt]	5217	1			T2	11		T9	6		T10	9
arcs[CntProgSt=>TransCheckSt]	30938	1			T1	52		T2	57		T3	68
arcs[TransCheckSt=>PostTransSt]	4088	1			T1	31		T2	10		T9	14
arcs[TransCheckSt=>TokenHashSt]	26748	1			T1	21		T2	47		T3	68
arcs[TokenHashSt=>PostTransSt]	11271	1			T1	2		T2	28		T3	68
arcs[TokenHashSt=>FlashRmaSt]	14648	1			T1	19		T2	19		T9	19
arcs[FlashRmaSt=>TokenCheck0St]	14607	1			T1	19		T2	19		T9	19
arcs[TokenCheck0St=>PostTransSt]	3751	1			T1	8		T2	8		T9	9
arcs[TokenCheck0St=>TokenCheck1St]	10781	1			T1	11		T2	11		T9	10
arcs[TokenCheck1St=>PostTransSt]	704	1			T1	11		T2	2		T16	10
arcs[TransProgSt=>PostTransSt]	9212	1			T2	9		T9	10		T10	6
arcs[IdleSt=>EscalateSt]	132	1			T31	5		T44	6		T45	7
arcs[ClkMuxSt=>EscalateSt]	32	1			T31	3		T44	2		T45	1
arcs[CntIncrSt=>EscalateSt]	60	1			T31	1		T44	2		T46	3
arcs[CntProgSt=>EscalateSt]	1086	1			T31	14		T44	16		T46	9
arcs[TransCheckSt=>EscalateSt]	102	1			T31	2		T46	3		T48	4
arcs[TokenHashSt=>EscalateSt]	829	1			T31	7		T44	11		T35	1
arcs[FlashRmaSt=>EscalateSt]	41	1			T44	1		T46	1		T47	1
arcs[TokenCheck0St=>EscalateSt]	75	1			T31	1		T46	1		T45	3
arcs[TokenCheck1St=>EscalateSt]	35	1			T44	1		T46	1		T48	1
arcs[TransProgSt=>EscalateSt]	830	1			T31	15		T44	12		T46	7
arcs[PostTransSt=>EscalateSt]	5555	1			T2	11		T9	6		T10	9
arcs[InvalidSt=>EscalateSt]	15473	1			T4	48		T11	15		T19	72

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8365065	1			T1	4918		T2	8258		T3	7363
auto[0]	auto[IdleSt]	25668881	1			T1	1986		T2	92465		T3	2183
auto[0]	auto[ClkMuxSt]	39827	1			T1	52		T2	76		T3	68
auto[0]	auto[CntIncrSt]	39491	1			T1	52		T2	76		T3	68
auto[0]	auto[CntProgSt]	1727421	1			T1	1182		T2	3873		T3	36039
auto[0]	auto[TransCheckSt]	30877	1			T1	52		T2	57		T3	68
auto[0]	auto[TokenHashSt]	58056028	1			T1	448		T2	1951		T3	37227
auto[0]	auto[FlashRmaSt]	40481	1			T1	70		T2	47		T9	48
auto[0]	auto[TokenCheck0St]	14564	1			T1	19		T2	19		T9	19
auto[0]	auto[TokenCheck1St]	10758	1			T1	11		T2	11		T9	10
auto[0]	auto[TransProgSt]	493790	1			T2	495		T9	350		T10	12
auto[0]	auto[PostTransSt]	15701347	1			T1	7983		T2	75078		T3	10383
auto[0]	auto[ScrapSt]	119707	1			T31	4		T32	48		T33	28
auto[0]	auto[EscalateSt]	6154815	1			T2	5080		T4	25987		T9	553
auto[0]	auto[InvalidSt]	13752065	1			T4	104026		T11	2655		T19	5455
auto[1]	auto[ResetSt]	183	1			T31	3		T44	2		T46	7
auto[1]	auto[IdleSt]	89	1			T31	3		T44	4		T45	6
auto[1]	auto[ClkMuxSt]	19	1			T31	3		T44	1		T45	1
auto[1]	auto[CntIncrSt]	42	1			T31	1		T44	2		T46	3
auto[1]	auto[CntProgSt]	706	1			T31	10		T44	11		T46	6
auto[1]	auto[TransCheckSt]	61	1			T31	1		T48	3		T45	5
auto[1]	auto[TokenHashSt]	544	1			T31	5		T44	8		T46	28
auto[1]	auto[FlashRmaSt]	22	1			T201	1		T202	1		T203	1
auto[1]	auto[TokenCheck0St]	43	1			T46	1		T45	3		T204	1
auto[1]	auto[TokenCheck1St]	23	1			T44	1		T48	1		T45	1
auto[1]	auto[TransProgSt]	572	1			T31	12		T44	10		T46	3
auto[1]	auto[PostTransSt]	2821	1			T2	3		T9	2		T10	7
auto[1]	auto[ScrapSt]	36	1			T46	3		T48	1		T45	2
auto[1]	auto[EscalateSt]	1486955	1			T2	294		T4	2134		T9	196
auto[1]	auto[InvalidSt]	7816	1			T4	22		T11	10		T19	33

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8365058	1			T1	4918		T2	8258		T3	7363
auto[0]	auto[IdleSt]	25668882	1			T1	1986		T2	92465		T3	2183
auto[0]	auto[ClkMuxSt]	39822	1			T1	52		T2	76		T3	68
auto[0]	auto[CntIncrSt]	39499	1			T1	52		T2	76		T3	68
auto[0]	auto[CntProgSt]	1727388	1			T1	1182		T2	3873		T3	36039
auto[0]	auto[TransCheckSt]	30875	1			T1	52		T2	57		T3	68
auto[0]	auto[TokenHashSt]	58056008	1			T1	448		T2	1951		T3	37227
auto[0]	auto[FlashRmaSt]	40474	1			T1	70		T2	47		T9	48
auto[0]	auto[TokenCheck0St]	14558	1			T1	19		T2	19		T9	19
auto[0]	auto[TokenCheck1St]	10753	1			T1	11		T2	11		T9	10
auto[0]	auto[TransProgSt]	493811	1			T2	495		T9	350		T10	12
auto[0]	auto[PostTransSt]	15701332	1			T1	7983		T2	75073		T3	10383
auto[0]	auto[ScrapSt]	119712	1			T31	3		T32	48		T33	28
auto[0]	auto[EscalateSt]	6158211	1			T2	4590		T4	25599		T9	357
auto[0]	auto[InvalidSt]	13752224	1			T4	104022		T11	2660		T19	5449
auto[1]	auto[ResetSt]	190	1			T31	3		T44	2		T46	2
auto[1]	auto[IdleSt]	88	1			T31	3		T44	5		T45	3
auto[1]	auto[ClkMuxSt]	24	1			T31	2		T44	2		T45	1
auto[1]	auto[CntIncrSt]	34	1			T31	1		T44	1		T46	1
auto[1]	auto[CntProgSt]	739	1			T31	7		T44	13		T46	4
auto[1]	auto[TransCheckSt]	63	1			T31	1		T46	3		T48	2
auto[1]	auto[TokenHashSt]	564	1			T31	4		T44	8		T35	1
auto[1]	auto[FlashRmaSt]	29	1			T44	1		T46	1		T47	1
auto[1]	auto[TokenCheck0St]	49	1			T31	1		T46	1		T45	1
auto[1]	auto[TokenCheck1St]	28	1			T46	1		T48	1		T45	1
auto[1]	auto[TransProgSt]	551	1			T31	9		T44	10		T46	5
auto[1]	auto[PostTransSt]	2836	1			T2	8		T9	4		T10	2
auto[1]	auto[ScrapSt]	31	1			T31	1		T46	1		T48	2
auto[1]	auto[EscalateSt]	1483559	1			T2	784		T4	2522		T9	392
auto[1]	auto[InvalidSt]	7657	1			T4	26		T11	5		T19	39