Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.13 97.92 95.66 93.40 100.00 98.52 98.51 95.94


Total test records in report: 1006
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T815 /workspace/coverage/default/4.lc_ctrl_jtag_errors.917805357 Jul 28 05:24:50 PM PDT 24 Jul 28 05:25:40 PM PDT 24 3402336104 ps
T816 /workspace/coverage/default/9.lc_ctrl_security_escalation.1477190665 Jul 28 05:25:29 PM PDT 24 Jul 28 05:25:42 PM PDT 24 1374890217 ps
T817 /workspace/coverage/default/22.lc_ctrl_sec_mubi.3624901355 Jul 28 05:26:12 PM PDT 24 Jul 28 05:26:22 PM PDT 24 1216642884 ps
T818 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2136271281 Jul 28 05:26:45 PM PDT 24 Jul 28 05:27:01 PM PDT 24 396729663 ps
T819 /workspace/coverage/default/3.lc_ctrl_security_escalation.430700072 Jul 28 05:24:40 PM PDT 24 Jul 28 05:24:48 PM PDT 24 1370955347 ps
T820 /workspace/coverage/default/1.lc_ctrl_security_escalation.1369813919 Jul 28 05:24:39 PM PDT 24 Jul 28 05:24:47 PM PDT 24 627139795 ps
T821 /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3853804369 Jul 28 05:26:47 PM PDT 24 Jul 28 05:26:56 PM PDT 24 3986241223 ps
T822 /workspace/coverage/default/40.lc_ctrl_smoke.211746737 Jul 28 05:26:49 PM PDT 24 Jul 28 05:26:52 PM PDT 24 35266250 ps
T823 /workspace/coverage/default/0.lc_ctrl_smoke.4032296859 Jul 28 05:24:26 PM PDT 24 Jul 28 05:24:30 PM PDT 24 416690031 ps
T824 /workspace/coverage/default/18.lc_ctrl_sec_mubi.1650263479 Jul 28 05:25:57 PM PDT 24 Jul 28 05:26:09 PM PDT 24 1183860844 ps
T825 /workspace/coverage/default/37.lc_ctrl_state_failure.3133914850 Jul 28 05:26:50 PM PDT 24 Jul 28 05:27:17 PM PDT 24 381173223 ps
T826 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2143330995 Jul 28 05:26:47 PM PDT 24 Jul 28 05:26:57 PM PDT 24 1045980029 ps
T827 /workspace/coverage/default/40.lc_ctrl_alert_test.2992317324 Jul 28 05:26:58 PM PDT 24 Jul 28 05:27:00 PM PDT 24 37887618 ps
T828 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1176034459 Jul 28 05:24:43 PM PDT 24 Jul 28 05:24:57 PM PDT 24 5955692410 ps
T829 /workspace/coverage/default/29.lc_ctrl_security_escalation.1911582251 Jul 28 05:26:28 PM PDT 24 Jul 28 05:26:39 PM PDT 24 1323008107 ps
T830 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3639142314 Jul 28 05:24:48 PM PDT 24 Jul 28 05:24:51 PM PDT 24 69674266 ps
T831 /workspace/coverage/default/18.lc_ctrl_state_failure.2115960459 Jul 28 05:25:51 PM PDT 24 Jul 28 05:26:14 PM PDT 24 145179176 ps
T832 /workspace/coverage/default/29.lc_ctrl_errors.291363010 Jul 28 05:26:28 PM PDT 24 Jul 28 05:26:41 PM PDT 24 2039115436 ps
T833 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3687200331 Jul 28 05:26:05 PM PDT 24 Jul 28 05:26:13 PM PDT 24 2423228349 ps
T834 /workspace/coverage/default/27.lc_ctrl_security_escalation.2710961650 Jul 28 05:26:18 PM PDT 24 Jul 28 05:26:30 PM PDT 24 1046971484 ps
T95 /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.4087804314 Jul 28 05:26:49 PM PDT 24 Jul 28 05:48:51 PM PDT 24 170874446305 ps
T835 /workspace/coverage/default/28.lc_ctrl_state_post_trans.3596601988 Jul 28 05:26:20 PM PDT 24 Jul 28 05:26:29 PM PDT 24 145423033 ps
T836 /workspace/coverage/default/3.lc_ctrl_alert_test.634358035 Jul 28 05:24:48 PM PDT 24 Jul 28 05:24:49 PM PDT 24 20908033 ps
T837 /workspace/coverage/default/1.lc_ctrl_smoke.3634110768 Jul 28 05:24:38 PM PDT 24 Jul 28 05:24:41 PM PDT 24 109181014 ps
T838 /workspace/coverage/default/11.lc_ctrl_smoke.1172524930 Jul 28 05:25:33 PM PDT 24 Jul 28 05:25:36 PM PDT 24 154536371 ps
T839 /workspace/coverage/default/32.lc_ctrl_sec_mubi.4102545108 Jul 28 05:26:43 PM PDT 24 Jul 28 05:26:56 PM PDT 24 492838259 ps
T840 /workspace/coverage/default/47.lc_ctrl_state_failure.3686789998 Jul 28 05:27:09 PM PDT 24 Jul 28 05:27:37 PM PDT 24 292266003 ps
T841 /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2414442858 Jul 28 05:25:47 PM PDT 24 Jul 28 05:36:49 PM PDT 24 74189888833 ps
T842 /workspace/coverage/default/48.lc_ctrl_stress_all.1774430103 Jul 28 05:27:17 PM PDT 24 Jul 28 05:30:16 PM PDT 24 8670322201 ps
T843 /workspace/coverage/default/30.lc_ctrl_smoke.3495505525 Jul 28 05:26:28 PM PDT 24 Jul 28 05:26:30 PM PDT 24 22459155 ps
T844 /workspace/coverage/default/48.lc_ctrl_errors.3921817660 Jul 28 05:27:15 PM PDT 24 Jul 28 05:27:29 PM PDT 24 458043803 ps
T845 /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2979327485 Jul 28 05:25:45 PM PDT 24 Jul 28 05:31:15 PM PDT 24 182418648592 ps
T846 /workspace/coverage/default/31.lc_ctrl_errors.1803516845 Jul 28 05:26:27 PM PDT 24 Jul 28 05:26:43 PM PDT 24 1005713473 ps
T847 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.365745463 Jul 28 05:25:42 PM PDT 24 Jul 28 05:25:51 PM PDT 24 3785506564 ps
T848 /workspace/coverage/default/36.lc_ctrl_errors.1630736460 Jul 28 05:26:47 PM PDT 24 Jul 28 05:27:02 PM PDT 24 1574316154 ps
T849 /workspace/coverage/default/11.lc_ctrl_state_failure.3185204500 Jul 28 05:25:29 PM PDT 24 Jul 28 05:25:55 PM PDT 24 499002291 ps
T850 /workspace/coverage/default/1.lc_ctrl_stress_all.3682873734 Jul 28 05:24:37 PM PDT 24 Jul 28 05:27:18 PM PDT 24 4551338119 ps
T851 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1128790099 Jul 28 05:24:47 PM PDT 24 Jul 28 05:24:49 PM PDT 24 64496008 ps
T852 /workspace/coverage/default/24.lc_ctrl_sec_mubi.1751578324 Jul 28 05:26:13 PM PDT 24 Jul 28 05:26:27 PM PDT 24 628370683 ps
T853 /workspace/coverage/default/2.lc_ctrl_sec_mubi.3973572646 Jul 28 05:24:48 PM PDT 24 Jul 28 05:25:00 PM PDT 24 763358271 ps
T854 /workspace/coverage/default/30.lc_ctrl_prog_failure.1498252964 Jul 28 05:26:25 PM PDT 24 Jul 28 05:26:28 PM PDT 24 554786731 ps
T855 /workspace/coverage/default/2.lc_ctrl_state_failure.771076326 Jul 28 05:24:43 PM PDT 24 Jul 28 05:25:16 PM PDT 24 235574845 ps
T856 /workspace/coverage/default/15.lc_ctrl_sec_mubi.851192602 Jul 28 05:25:45 PM PDT 24 Jul 28 05:26:06 PM PDT 24 2282466862 ps
T857 /workspace/coverage/default/2.lc_ctrl_state_post_trans.2971138735 Jul 28 05:24:44 PM PDT 24 Jul 28 05:24:47 PM PDT 24 63258949 ps
T858 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1547232465 Jul 28 05:25:48 PM PDT 24 Jul 28 05:25:59 PM PDT 24 264207607 ps
T859 /workspace/coverage/default/44.lc_ctrl_sec_mubi.2009444541 Jul 28 05:27:15 PM PDT 24 Jul 28 05:27:36 PM PDT 24 2294003689 ps
T860 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1863774437 Jul 28 05:26:53 PM PDT 24 Jul 28 05:26:54 PM PDT 24 58359938 ps
T861 /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.1546685289 Jul 28 05:26:19 PM PDT 24 Jul 28 05:32:11 PM PDT 24 9963385293 ps
T862 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3054226770 Jul 28 05:27:05 PM PDT 24 Jul 28 05:27:20 PM PDT 24 2866341962 ps
T863 /workspace/coverage/default/45.lc_ctrl_jtag_access.349688888 Jul 28 05:27:07 PM PDT 24 Jul 28 05:27:13 PM PDT 24 250171553 ps
T864 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.462202288 Jul 28 05:26:27 PM PDT 24 Jul 28 05:26:36 PM PDT 24 359696015 ps
T865 /workspace/coverage/default/39.lc_ctrl_alert_test.2982500655 Jul 28 05:26:48 PM PDT 24 Jul 28 05:26:49 PM PDT 24 79132972 ps
T866 /workspace/coverage/default/19.lc_ctrl_jtag_errors.158119613 Jul 28 05:25:55 PM PDT 24 Jul 28 05:26:16 PM PDT 24 4456644521 ps
T867 /workspace/coverage/default/41.lc_ctrl_alert_test.2649530269 Jul 28 05:26:54 PM PDT 24 Jul 28 05:26:56 PM PDT 24 40239928 ps
T868 /workspace/coverage/default/38.lc_ctrl_sec_mubi.151010367 Jul 28 05:26:51 PM PDT 24 Jul 28 05:27:03 PM PDT 24 641032538 ps
T869 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.280303207 Jul 28 05:27:01 PM PDT 24 Jul 28 05:27:03 PM PDT 24 14604973 ps
T870 /workspace/coverage/default/30.lc_ctrl_state_failure.2994793685 Jul 28 05:26:30 PM PDT 24 Jul 28 05:26:54 PM PDT 24 242422802 ps
T871 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4188145762 Jul 28 05:26:18 PM PDT 24 Jul 28 05:26:30 PM PDT 24 817697908 ps
T872 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3559732609 Jul 28 05:25:16 PM PDT 24 Jul 28 05:25:39 PM PDT 24 856132570 ps
T873 /workspace/coverage/default/10.lc_ctrl_state_failure.1814765110 Jul 28 05:25:29 PM PDT 24 Jul 28 05:25:50 PM PDT 24 3424583617 ps
T874 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.309360009 Jul 28 05:26:34 PM PDT 24 Jul 28 05:26:43 PM PDT 24 928916458 ps
T875 /workspace/coverage/default/10.lc_ctrl_prog_failure.64697832 Jul 28 05:25:33 PM PDT 24 Jul 28 05:25:38 PM PDT 24 129293577 ps
T876 /workspace/coverage/default/13.lc_ctrl_state_post_trans.454294269 Jul 28 05:25:36 PM PDT 24 Jul 28 05:25:43 PM PDT 24 81088903 ps
T877 /workspace/coverage/default/14.lc_ctrl_stress_all.2012076379 Jul 28 05:25:42 PM PDT 24 Jul 28 05:29:48 PM PDT 24 4751388949 ps
T878 /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1143576559 Jul 28 05:26:05 PM PDT 24 Jul 28 05:26:06 PM PDT 24 12694767 ps
T879 /workspace/coverage/default/3.lc_ctrl_errors.2224172807 Jul 28 05:24:40 PM PDT 24 Jul 28 05:24:52 PM PDT 24 995879971 ps
T880 /workspace/coverage/default/46.lc_ctrl_sec_mubi.399048589 Jul 28 05:27:09 PM PDT 24 Jul 28 05:27:24 PM PDT 24 2446004886 ps
T881 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3969570710 Jul 28 05:25:41 PM PDT 24 Jul 28 05:25:46 PM PDT 24 468954192 ps
T882 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1808625749 Jul 28 05:26:26 PM PDT 24 Jul 28 05:26:27 PM PDT 24 14976576 ps
T883 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1084981205 Jul 28 05:25:11 PM PDT 24 Jul 28 05:25:22 PM PDT 24 259749419 ps
T884 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1809368539 Jul 28 05:26:49 PM PDT 24 Jul 28 05:27:01 PM PDT 24 1212199700 ps
T112 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2946531376 Jul 28 05:01:46 PM PDT 24 Jul 28 05:01:47 PM PDT 24 31949313 ps
T101 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4196438330 Jul 28 05:02:10 PM PDT 24 Jul 28 05:02:11 PM PDT 24 99276964 ps
T106 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.516956985 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:03 PM PDT 24 25364300 ps
T96 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.909889530 Jul 28 05:02:08 PM PDT 24 Jul 28 05:02:10 PM PDT 24 23315677 ps
T130 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2567935609 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:55 PM PDT 24 1097005251 ps
T133 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1881753202 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:57 PM PDT 24 841965849 ps
T97 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4267756531 Jul 28 05:02:00 PM PDT 24 Jul 28 05:02:05 PM PDT 24 567657561 ps
T131 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1606464163 Jul 28 05:02:22 PM PDT 24 Jul 28 05:02:27 PM PDT 24 975784630 ps
T107 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3652136294 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:04 PM PDT 24 35021679 ps
T885 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2335633333 Jul 28 05:01:59 PM PDT 24 Jul 28 05:02:00 PM PDT 24 22220067 ps
T149 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.400860013 Jul 28 05:01:53 PM PDT 24 Jul 28 05:01:55 PM PDT 24 26019578 ps
T102 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2674895797 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:04 PM PDT 24 23864553 ps
T108 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1077888106 Jul 28 05:02:19 PM PDT 24 Jul 28 05:02:20 PM PDT 24 97109707 ps
T98 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1088583320 Jul 28 05:01:58 PM PDT 24 Jul 28 05:02:00 PM PDT 24 61166554 ps
T132 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.602999808 Jul 28 05:01:54 PM PDT 24 Jul 28 05:01:55 PM PDT 24 178608305 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1910315613 Jul 28 05:02:12 PM PDT 24 Jul 28 05:02:13 PM PDT 24 14778467 ps
T186 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.439961005 Jul 28 05:02:08 PM PDT 24 Jul 28 05:02:09 PM PDT 24 21223712 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.416412151 Jul 28 05:01:53 PM PDT 24 Jul 28 05:01:54 PM PDT 24 41942225 ps
T150 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3972120350 Jul 28 05:02:00 PM PDT 24 Jul 28 05:02:01 PM PDT 24 25161825 ps
T888 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3955916803 Jul 28 05:02:12 PM PDT 24 Jul 28 05:02:14 PM PDT 24 46513691 ps
T195 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1219798502 Jul 28 05:01:57 PM PDT 24 Jul 28 05:02:20 PM PDT 24 15382172134 ps
T187 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.588818810 Jul 28 05:01:59 PM PDT 24 Jul 28 05:02:01 PM PDT 24 38607262 ps
T153 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3242754519 Jul 28 05:02:09 PM PDT 24 Jul 28 05:02:13 PM PDT 24 104781808 ps
T889 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3315386373 Jul 28 05:02:17 PM PDT 24 Jul 28 05:02:23 PM PDT 24 442336504 ps
T118 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4289707175 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:06 PM PDT 24 220761719 ps
T188 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.608485324 Jul 28 05:02:06 PM PDT 24 Jul 28 05:02:07 PM PDT 24 33184288 ps
T196 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.893945306 Jul 28 05:02:03 PM PDT 24 Jul 28 05:02:12 PM PDT 24 351999157 ps
T890 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4135271048 Jul 28 05:02:08 PM PDT 24 Jul 28 05:02:09 PM PDT 24 26356063 ps
T103 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.163627095 Jul 28 05:02:04 PM PDT 24 Jul 28 05:02:07 PM PDT 24 110748968 ps
T115 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1930312649 Jul 28 05:01:59 PM PDT 24 Jul 28 05:02:04 PM PDT 24 127332446 ps
T170 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2874687186 Jul 28 05:01:56 PM PDT 24 Jul 28 05:01:58 PM PDT 24 56659502 ps
T104 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2885112771 Jul 28 05:02:05 PM PDT 24 Jul 28 05:02:07 PM PDT 24 112965035 ps
T891 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2082432111 Jul 28 05:02:05 PM PDT 24 Jul 28 05:02:08 PM PDT 24 195237372 ps
T892 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1059837541 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:14 PM PDT 24 76583522 ps
T893 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1003245573 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:03 PM PDT 24 16411514 ps
T894 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3845741543 Jul 28 05:02:15 PM PDT 24 Jul 28 05:02:16 PM PDT 24 145673855 ps
T895 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2991141183 Jul 28 05:02:20 PM PDT 24 Jul 28 05:02:23 PM PDT 24 288258187 ps
T189 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1276499635 Jul 28 05:02:07 PM PDT 24 Jul 28 05:02:09 PM PDT 24 115726649 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2620035531 Jul 28 05:02:11 PM PDT 24 Jul 28 05:02:13 PM PDT 24 338597899 ps
T105 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1711872424 Jul 28 05:02:04 PM PDT 24 Jul 28 05:02:07 PM PDT 24 87986202 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2407627326 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:52 PM PDT 24 872772668 ps
T199 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1313075279 Jul 28 05:02:30 PM PDT 24 Jul 28 05:02:33 PM PDT 24 255019093 ps
T898 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3669542685 Jul 28 05:02:16 PM PDT 24 Jul 28 05:02:17 PM PDT 24 104673121 ps
T190 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3376896076 Jul 28 05:02:09 PM PDT 24 Jul 28 05:02:21 PM PDT 24 38763541 ps
T200 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.572309588 Jul 28 05:02:18 PM PDT 24 Jul 28 05:02:21 PM PDT 24 862939129 ps
T127 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.60723085 Jul 28 05:02:01 PM PDT 24 Jul 28 05:02:03 PM PDT 24 200936134 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1626356150 Jul 28 05:01:58 PM PDT 24 Jul 28 05:02:00 PM PDT 24 93708997 ps
T900 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1532829458 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:15 PM PDT 24 87751919 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4021468764 Jul 28 05:01:57 PM PDT 24 Jul 28 05:02:00 PM PDT 24 84356003 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.751441193 Jul 28 05:01:57 PM PDT 24 Jul 28 05:01:58 PM PDT 24 115933095 ps
T120 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2473389031 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:03 PM PDT 24 43953536 ps
T903 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1211541078 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:31 PM PDT 24 72008445 ps
T904 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3708020194 Jul 28 05:01:58 PM PDT 24 Jul 28 05:02:05 PM PDT 24 377780115 ps
T123 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.446844939 Jul 28 05:02:09 PM PDT 24 Jul 28 05:02:12 PM PDT 24 143995076 ps
T113 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2077477085 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:52 PM PDT 24 248653221 ps
T905 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4079999495 Jul 28 05:02:08 PM PDT 24 Jul 28 05:02:09 PM PDT 24 39909021 ps
T191 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4087339294 Jul 28 05:01:53 PM PDT 24 Jul 28 05:01:55 PM PDT 24 71653448 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2198249479 Jul 28 05:01:56 PM PDT 24 Jul 28 05:01:58 PM PDT 24 226869407 ps
T907 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1480862405 Jul 28 05:01:46 PM PDT 24 Jul 28 05:01:47 PM PDT 24 26299258 ps
T192 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3175764847 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:14 PM PDT 24 102376349 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2773486581 Jul 28 05:02:06 PM PDT 24 Jul 28 05:02:26 PM PDT 24 838958691 ps
T909 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2855964918 Jul 28 05:02:09 PM PDT 24 Jul 28 05:02:10 PM PDT 24 213321701 ps
T910 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4085025114 Jul 28 05:01:44 PM PDT 24 Jul 28 05:02:11 PM PDT 24 1108118066 ps
T911 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2852857860 Jul 28 05:01:44 PM PDT 24 Jul 28 05:01:46 PM PDT 24 166642064 ps
T128 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3150842248 Jul 28 05:01:57 PM PDT 24 Jul 28 05:02:00 PM PDT 24 221999826 ps
T912 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3009622106 Jul 28 05:02:10 PM PDT 24 Jul 28 05:02:12 PM PDT 24 36379585 ps
T129 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.237489050 Jul 28 05:01:55 PM PDT 24 Jul 28 05:01:58 PM PDT 24 1061658163 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3052296127 Jul 28 05:02:03 PM PDT 24 Jul 28 05:02:05 PM PDT 24 24538411 ps
T914 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3304139832 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:15 PM PDT 24 17603113 ps
T915 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2874516994 Jul 28 05:02:25 PM PDT 24 Jul 28 05:02:26 PM PDT 24 21797244 ps
T916 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.832726968 Jul 28 05:02:07 PM PDT 24 Jul 28 05:02:08 PM PDT 24 17479064 ps
T917 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3757244061 Jul 28 05:02:03 PM PDT 24 Jul 28 05:02:07 PM PDT 24 191019500 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2416824272 Jul 28 05:02:08 PM PDT 24 Jul 28 05:02:09 PM PDT 24 52685132 ps
T919 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3637480953 Jul 28 05:02:20 PM PDT 24 Jul 28 05:02:23 PM PDT 24 249263327 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.277980258 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:04 PM PDT 24 316928706 ps
T124 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3713282671 Jul 28 05:01:54 PM PDT 24 Jul 28 05:01:56 PM PDT 24 61684842 ps
T114 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3796471421 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:26 PM PDT 24 83868016 ps
T921 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3903161079 Jul 28 05:02:30 PM PDT 24 Jul 28 05:02:32 PM PDT 24 85188353 ps
T922 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2404173486 Jul 28 05:02:00 PM PDT 24 Jul 28 05:02:11 PM PDT 24 954587903 ps
T923 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3767475721 Jul 28 05:02:07 PM PDT 24 Jul 28 05:02:10 PM PDT 24 1642794007 ps
T924 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3781077531 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:25 PM PDT 24 70237505 ps
T925 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1669768901 Jul 28 05:01:59 PM PDT 24 Jul 28 05:02:01 PM PDT 24 21785338 ps
T926 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2446669548 Jul 28 05:02:10 PM PDT 24 Jul 28 05:02:14 PM PDT 24 1212281311 ps
T927 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1531233580 Jul 28 05:02:03 PM PDT 24 Jul 28 05:02:30 PM PDT 24 4952617774 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1704173421 Jul 28 05:01:56 PM PDT 24 Jul 28 05:01:57 PM PDT 24 147444941 ps
T929 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.23328643 Jul 28 05:02:25 PM PDT 24 Jul 28 05:02:26 PM PDT 24 60709382 ps
T121 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1683105419 Jul 28 05:01:54 PM PDT 24 Jul 28 05:01:56 PM PDT 24 166953039 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3873208768 Jul 28 05:01:59 PM PDT 24 Jul 28 05:02:00 PM PDT 24 45478578 ps
T931 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1301589736 Jul 28 05:01:56 PM PDT 24 Jul 28 05:02:06 PM PDT 24 4477762503 ps
T932 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1034784938 Jul 28 05:02:04 PM PDT 24 Jul 28 05:02:10 PM PDT 24 1011774962 ps
T933 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3931395400 Jul 28 05:02:22 PM PDT 24 Jul 28 05:02:23 PM PDT 24 16616157 ps
T934 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.431186189 Jul 28 05:01:57 PM PDT 24 Jul 28 05:01:58 PM PDT 24 73682692 ps
T935 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.717851384 Jul 28 05:01:59 PM PDT 24 Jul 28 05:02:01 PM PDT 24 329648057 ps
T936 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3122639369 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:53 PM PDT 24 211573905 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3996208932 Jul 28 05:01:58 PM PDT 24 Jul 28 05:02:00 PM PDT 24 127418059 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3108766300 Jul 28 05:01:57 PM PDT 24 Jul 28 05:02:00 PM PDT 24 812462181 ps
T109 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2100637442 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:18 PM PDT 24 453218532 ps
T116 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1314701108 Jul 28 05:02:00 PM PDT 24 Jul 28 05:02:03 PM PDT 24 288767722 ps
T182 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3467523572 Jul 28 05:02:06 PM PDT 24 Jul 28 05:02:08 PM PDT 24 20726517 ps
T174 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1691446057 Jul 28 05:02:03 PM PDT 24 Jul 28 05:02:05 PM PDT 24 25332490 ps
T119 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1323530527 Jul 28 05:02:17 PM PDT 24 Jul 28 05:02:19 PM PDT 24 95243305 ps
T939 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2241745998 Jul 28 05:02:23 PM PDT 24 Jul 28 05:02:26 PM PDT 24 118978689 ps
T940 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2755764993 Jul 28 05:02:20 PM PDT 24 Jul 28 05:02:22 PM PDT 24 76139039 ps
T941 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1611751371 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:31 PM PDT 24 43849042 ps
T942 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2054475942 Jul 28 05:01:58 PM PDT 24 Jul 28 05:02:00 PM PDT 24 64507216 ps
T943 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3681468624 Jul 28 05:01:58 PM PDT 24 Jul 28 05:02:10 PM PDT 24 1015971489 ps
T944 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.128290543 Jul 28 05:01:58 PM PDT 24 Jul 28 05:01:59 PM PDT 24 51413530 ps
T175 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1883245410 Jul 28 05:02:26 PM PDT 24 Jul 28 05:02:32 PM PDT 24 118989678 ps
T945 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2400145955 Jul 28 05:01:57 PM PDT 24 Jul 28 05:02:01 PM PDT 24 518234418 ps
T946 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3202141716 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:31 PM PDT 24 49943260 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2883484122 Jul 28 05:02:22 PM PDT 24 Jul 28 05:02:24 PM PDT 24 349394269 ps
T948 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4121692077 Jul 28 05:02:10 PM PDT 24 Jul 28 05:02:12 PM PDT 24 229879340 ps
T949 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2212189350 Jul 28 05:02:14 PM PDT 24 Jul 28 05:02:15 PM PDT 24 33893168 ps
T950 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2097004189 Jul 28 05:02:00 PM PDT 24 Jul 28 05:02:02 PM PDT 24 112768473 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.767305959 Jul 28 05:01:56 PM PDT 24 Jul 28 05:02:09 PM PDT 24 3813040583 ps
T952 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.98063421 Jul 28 05:02:11 PM PDT 24 Jul 28 05:02:14 PM PDT 24 151734364 ps
T953 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1127032061 Jul 28 05:02:10 PM PDT 24 Jul 28 05:02:12 PM PDT 24 80461481 ps
T954 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.538547197 Jul 28 05:01:56 PM PDT 24 Jul 28 05:01:58 PM PDT 24 56040275 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1245688109 Jul 28 05:02:33 PM PDT 24 Jul 28 05:02:34 PM PDT 24 34123255 ps
T110 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2850475629 Jul 28 05:02:22 PM PDT 24 Jul 28 05:02:26 PM PDT 24 157738021 ps
T956 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.370024517 Jul 28 05:01:56 PM PDT 24 Jul 28 05:01:57 PM PDT 24 41504091 ps
T176 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.264773199 Jul 28 05:02:06 PM PDT 24 Jul 28 05:02:07 PM PDT 24 11611123 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.570662165 Jul 28 05:02:08 PM PDT 24 Jul 28 05:02:11 PM PDT 24 384842686 ps
T958 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3402852151 Jul 28 05:02:19 PM PDT 24 Jul 28 05:02:20 PM PDT 24 19082684 ps
T959 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1997229310 Jul 28 05:02:33 PM PDT 24 Jul 28 05:02:34 PM PDT 24 35432165 ps
T960 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.301124928 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:16 PM PDT 24 281454532 ps
T961 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.433859067 Jul 28 05:02:15 PM PDT 24 Jul 28 05:02:16 PM PDT 24 21013652 ps
T111 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.376462381 Jul 28 05:01:56 PM PDT 24 Jul 28 05:02:00 PM PDT 24 454687462 ps
T962 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.266312208 Jul 28 05:02:16 PM PDT 24 Jul 28 05:02:17 PM PDT 24 43756339 ps
T963 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1439192903 Jul 28 05:02:17 PM PDT 24 Jul 28 05:02:18 PM PDT 24 45582228 ps
T964 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2005128473 Jul 28 05:02:23 PM PDT 24 Jul 28 05:02:24 PM PDT 24 52998340 ps
T965 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3564793452 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:52 PM PDT 24 221622986 ps
T966 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2207595516 Jul 28 05:02:09 PM PDT 24 Jul 28 05:02:11 PM PDT 24 111746144 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.369002497 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:25 PM PDT 24 57707503 ps
T968 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.862439453 Jul 28 05:02:10 PM PDT 24 Jul 28 05:02:11 PM PDT 24 17727912 ps
T969 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1454181412 Jul 28 05:02:12 PM PDT 24 Jul 28 05:02:15 PM PDT 24 394288095 ps
T970 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3479549940 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:49 PM PDT 24 117467051 ps
T177 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3902987522 Jul 28 05:01:57 PM PDT 24 Jul 28 05:01:58 PM PDT 24 13235143 ps
T971 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3837027166 Jul 28 05:01:59 PM PDT 24 Jul 28 05:02:00 PM PDT 24 27876084 ps
T122 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1455734950 Jul 28 05:01:55 PM PDT 24 Jul 28 05:01:58 PM PDT 24 98837300 ps
T972 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2544523627 Jul 28 05:02:12 PM PDT 24 Jul 28 05:02:13 PM PDT 24 29069198 ps
T973 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3051921960 Jul 28 05:01:45 PM PDT 24 Jul 28 05:01:46 PM PDT 24 15681829 ps
T178 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2834266342 Jul 28 05:02:12 PM PDT 24 Jul 28 05:02:13 PM PDT 24 48730657 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4241944155 Jul 28 05:01:54 PM PDT 24 Jul 28 05:02:01 PM PDT 24 74642161 ps
T975 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1073881088 Jul 28 05:01:58 PM PDT 24 Jul 28 05:02:03 PM PDT 24 425646690 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3974737444 Jul 28 05:01:52 PM PDT 24 Jul 28 05:01:55 PM PDT 24 377749719 ps
T179 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1489595663 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:03 PM PDT 24 82459216 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1721721728 Jul 28 05:02:06 PM PDT 24 Jul 28 05:02:16 PM PDT 24 1524885846 ps
T180 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1307160018 Jul 28 05:02:11 PM PDT 24 Jul 28 05:02:12 PM PDT 24 23714823 ps
T978 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2381676782 Jul 28 05:02:18 PM PDT 24 Jul 28 05:02:21 PM PDT 24 138268107 ps
T979 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.728463135 Jul 28 05:01:53 PM PDT 24 Jul 28 05:02:05 PM PDT 24 4164128926 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.930203328 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:49 PM PDT 24 17763747 ps
T981 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2513766605 Jul 28 05:01:55 PM PDT 24 Jul 28 05:01:58 PM PDT 24 40216775 ps
T117 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1875896031 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:27 PM PDT 24 104035050 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2838542559 Jul 28 05:02:03 PM PDT 24 Jul 28 05:02:08 PM PDT 24 1058232598 ps
T983 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1020522128 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:14 PM PDT 24 90654120 ps
T181 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2312127316 Jul 28 05:02:08 PM PDT 24 Jul 28 05:02:09 PM PDT 24 54023777 ps
T984 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.470247891 Jul 28 05:02:17 PM PDT 24 Jul 28 05:02:18 PM PDT 24 80248587 ps
T985 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2796848331 Jul 28 05:01:54 PM PDT 24 Jul 28 05:01:55 PM PDT 24 19928013 ps
T986 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.812604576 Jul 28 05:01:47 PM PDT 24 Jul 28 05:01:50 PM PDT 24 56999293 ps
T987 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2185606095 Jul 28 05:01:48 PM PDT 24 Jul 28 05:01:49 PM PDT 24 47995502 ps
T988 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2553405471 Jul 28 05:02:22 PM PDT 24 Jul 28 05:02:23 PM PDT 24 42700823 ps
T989 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3116401045 Jul 28 05:01:48 PM PDT 24 Jul 28 05:02:00 PM PDT 24 1762975561 ps
T990 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3539178233 Jul 28 05:02:11 PM PDT 24 Jul 28 05:02:13 PM PDT 24 92613591 ps
T991 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4211871711 Jul 28 05:02:15 PM PDT 24 Jul 28 05:02:18 PM PDT 24 92893979 ps
T125 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1085806863 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:16 PM PDT 24 45948649 ps
T992 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3252704564 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:04 PM PDT 24 37837176 ps
T183 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.388402613 Jul 28 05:02:10 PM PDT 24 Jul 28 05:02:15 PM PDT 24 16308859 ps
T993 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2073826670 Jul 28 05:02:01 PM PDT 24 Jul 28 05:02:03 PM PDT 24 68999212 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3237607174 Jul 28 05:02:04 PM PDT 24 Jul 28 05:02:05 PM PDT 24 235821236 ps
T995 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.177741569 Jul 28 05:02:00 PM PDT 24 Jul 28 05:02:02 PM PDT 24 34851688 ps
T996 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2092230871 Jul 28 05:02:03 PM PDT 24 Jul 28 05:02:04 PM PDT 24 45001547 ps
T997 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2092343963 Jul 28 05:02:00 PM PDT 24 Jul 28 05:02:03 PM PDT 24 144856246 ps
T998 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4293059588 Jul 28 05:01:51 PM PDT 24 Jul 28 05:01:53 PM PDT 24 47038498 ps
T999 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3925155628 Jul 28 05:02:15 PM PDT 24 Jul 28 05:02:25 PM PDT 24 548929763 ps
T1000 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3559710173 Jul 28 05:02:16 PM PDT 24 Jul 28 05:02:20 PM PDT 24 894419017 ps
T184 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.834267856 Jul 28 05:01:56 PM PDT 24 Jul 28 05:01:57 PM PDT 24 19685006 ps
T1001 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.120197213 Jul 28 05:01:55 PM PDT 24 Jul 28 05:02:41 PM PDT 24 4101146616 ps
T1002 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1296498575 Jul 28 05:02:02 PM PDT 24 Jul 28 05:02:04 PM PDT 24 250115161 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%