Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101802861

1

T1

2202

T2

4678

T3

21473

auto[1]

1449761

1

T3

10709

T11

11457

T13

891

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101762922

1

T1

2202

T2

4678

T3

22870

auto[1]

1489700

1

T3

9312

T11

9883

T13

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7471805	1			T1	120		T2	1492		T3	8736
auto[IdleSt]	22274193	1			T1	2082		T2	1941		T3	6057
auto[ClkMuxSt]	35561	1			T2	17		T3	66		T4	79
auto[CntIncrSt]	35338	1			T2	17		T3	64		T4	79
auto[CntProgSt]	2025248	1			T2	34		T3	128		T4	30514
auto[TransCheckSt]	27573	1			T2	17		T3	58		T4	79
auto[TokenHashSt]	38087203	1			T2	188		T3	1104		T4	446
auto[FlashRmaSt]	36206	1			T2	82		T3	27		T4	109
auto[TokenCheck0St]	12887	1			T2	17		T3	22		T4	29
auto[TokenCheck1St]	9628	1			T2	17		T3	22		T4	12
auto[TransProgSt]	485946	1			T2	34		T3	40		T11	353
auto[PostTransSt]	12856727	1			T2	822		T3	33		T4	12634
auto[ScrapSt]	130479	1			T3	16		T11	8		T44	958
auto[EscalateSt]	7335985	1			T3	15809		T11	16594		T13	1637
auto[InvalidSt]	12425696	1			T25	9994		T45	2570		T44	6186

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2147	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12425696	1			T25	9994		T45	2570		T44	6186
EscalateSt	7335985	1			T3	15809		T11	16594		T13	1637
ScrapSt	130479	1			T3	16		T11	8		T44	958
PostTransSt	12856727	1			T2	822		T3	33		T4	12634
TransProgSt	485946	1			T2	34		T3	40		T11	353
TokenCheck1St	9628	1			T2	17		T3	22		T4	12
TokenCheck0St	12887	1			T2	17		T3	22		T4	29
FlashRmaSt	36206	1			T2	82		T3	27		T4	109
TokenHashSt	38087203	1			T2	188		T3	1104		T4	446
TransCheckSt	27573	1			T2	17		T3	58		T4	79
CntProgSt	2025248	1			T2	34		T3	128		T4	30514
CntIncrSt	35338	1			T2	17		T3	64		T4	79
ClkMuxSt	35561	1			T2	17		T3	66		T4	79
IdleSt	22274193	1			T1	2082		T2	1941		T3	6057
ResetSt	7471805	1			T1	120		T2	1492		T3	8736
arcs[ResetSt=>IdleSt]	55089	1			T1	1		T2	17		T3	77
arcs[IdleSt=>ScrapSt]	322	1			T3	4		T11	2		T44	9
arcs[IdleSt=>ClkMuxSt]	35373	1			T2	17		T3	66		T4	79
arcs[ClkMuxSt=>CntIncrSt]	35338	1			T2	17		T3	64		T4	79
arcs[CntIncrSt=>PostTransSt]	1662	1			T13	6		T16	15		T17	7
arcs[CntIncrSt=>CntProgSt]	33624	1			T2	17		T3	64		T4	79
arcs[CntProgSt=>PostTransSt]	4990	1			T13	10		T6	13		T45	12
arcs[CntProgSt=>TransCheckSt]	27573	1			T2	17		T3	58		T4	79
arcs[TransCheckSt=>PostTransSt]	3693	1			T4	38		T13	11		T26	25
arcs[TransCheckSt=>TokenHashSt]	23777	1			T2	17		T3	52		T4	41
arcs[TokenHashSt=>PostTransSt]	9981	1			T4	12		T12	1		T13	29
arcs[TokenHashSt=>FlashRmaSt]	12925	1			T2	17		T3	23		T4	29
arcs[FlashRmaSt=>TokenCheck0St]	12887	1			T2	17		T3	22		T4	29
arcs[TokenCheck0St=>PostTransSt]	3192	1			T4	17		T13	12		T26	21
arcs[TokenCheck0St=>TokenCheck1St]	9628	1			T2	17		T3	22		T4	12
arcs[TokenCheck1St=>PostTransSt]	652	1			T4	12		T26	8		T23	11
arcs[TransProgSt=>PostTransSt]	8151	1			T2	17		T3	16		T11	1
arcs[IdleSt=>EscalateSt]	177	1			T3	6		T11	5		T55	3
arcs[ClkMuxSt=>EscalateSt]	35	1			T3	2		T11	1		T55	2
arcs[CntIncrSt=>EscalateSt]	52	1			T20	1		T56	2		T57	2
arcs[CntProgSt=>EscalateSt]	1061	1			T3	6		T11	23		T22	8
arcs[TransCheckSt=>EscalateSt]	103	1			T3	6		T22	5		T56	8
arcs[TokenHashSt=>EscalateSt]	871	1			T3	29		T11	9		T22	52
arcs[FlashRmaSt=>EscalateSt]	38	1			T3	1		T11	1		T22	3
arcs[TokenCheck0St=>EscalateSt]	67	1			T11	1		T22	2		T55	4
arcs[TokenCheck1St=>EscalateSt]	22	1			T3	1		T22	1		T55	1
arcs[TransProgSt=>EscalateSt]	803	1			T3	5		T11	22		T22	6
arcs[PostTransSt=>EscalateSt]	5368	1			T3	16		T11	1		T13	12
arcs[InvalidSt=>EscalateSt]	14954	1			T25	55		T45	13		T43	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7471640	1			T1	120		T2	1492		T3	8730
auto[0]	auto[IdleSt]	22274083	1			T1	2082		T2	1941		T3	6054
auto[0]	auto[ClkMuxSt]	35539	1			T2	17		T3	64		T4	79
auto[0]	auto[CntIncrSt]	35301	1			T2	17		T3	64		T4	79
auto[0]	auto[CntProgSt]	2024552	1			T2	34		T3	124		T4	30514
auto[0]	auto[TransCheckSt]	27503	1			T2	17		T3	53		T4	79
auto[0]	auto[TokenHashSt]	38086613	1			T2	188		T3	1085		T4	446
auto[0]	auto[FlashRmaSt]	36186	1			T2	82		T3	26		T4	109
auto[0]	auto[TokenCheck0St]	12841	1			T2	17		T3	22		T4	29
auto[0]	auto[TokenCheck1St]	9611	1			T2	17		T3	21		T4	12
auto[0]	auto[TransProgSt]	485398	1			T2	34		T3	35		T11	337
auto[0]	auto[PostTransSt]	12854027	1			T2	822		T3	26		T4	12634
auto[0]	auto[ScrapSt]	130425	1			T3	12		T11	6		T44	958
auto[0]	auto[EscalateSt]	5898639	1			T3	5157		T11	5189		T13	755
auto[0]	auto[InvalidSt]	12418356	1			T25	9969		T45	2565		T44	6186
auto[1]	auto[ResetSt]	165	1			T3	6		T11	6		T22	4
auto[1]	auto[IdleSt]	110	1			T3	3		T11	3		T56	4
auto[1]	auto[ClkMuxSt]	22	1			T3	2		T11	1		T55	1
auto[1]	auto[CntIncrSt]	37	1			T20	1		T56	2		T205	1
auto[1]	auto[CntProgSt]	696	1			T3	4		T11	16		T22	4
auto[1]	auto[TransCheckSt]	70	1			T3	5		T22	2		T56	5
auto[1]	auto[TokenHashSt]	590	1			T3	19		T11	7		T22	42
auto[1]	auto[FlashRmaSt]	20	1			T3	1		T22	2		T206	1
auto[1]	auto[TokenCheck0St]	46	1			T22	1		T55	3		T20	1
auto[1]	auto[TokenCheck1St]	17	1			T3	1		T22	1		T55	1
auto[1]	auto[TransProgSt]	548	1			T3	5		T11	16		T22	3
auto[1]	auto[PostTransSt]	2700	1			T3	7		T11	1		T13	9
auto[1]	auto[ScrapSt]	54	1			T3	4		T11	2		T55	2
auto[1]	auto[EscalateSt]	1437346	1			T3	10652		T11	11405		T13	882
auto[1]	auto[InvalidSt]	7340	1			T25	25		T45	5		T43	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7471631	1			T1	120		T2	1492		T3	8732
auto[0]	auto[IdleSt]	22274076	1			T1	2082		T2	1941		T3	6052
auto[0]	auto[ClkMuxSt]	35536	1			T2	17		T3	66		T4	79
auto[0]	auto[CntIncrSt]	35307	1			T2	17		T3	64		T4	79
auto[0]	auto[CntProgSt]	2024525	1			T2	34		T3	124		T4	30514
auto[0]	auto[TransCheckSt]	27506	1			T2	17		T3	56		T4	79
auto[0]	auto[TokenHashSt]	38086622	1			T2	188		T3	1089		T4	446
auto[0]	auto[FlashRmaSt]	36174	1			T2	82		T3	26		T4	109
auto[0]	auto[TokenCheck0St]	12846	1			T2	17		T3	22		T4	29
auto[0]	auto[TokenCheck1St]	9613	1			T2	17		T3	21		T4	12
auto[0]	auto[TransProgSt]	485413	1			T2	34		T3	37		T11	340
auto[0]	auto[PostTransSt]	12853948	1			T2	822		T3	22		T4	12634
auto[0]	auto[ScrapSt]	130431	1			T3	15		T11	7		T44	958
auto[0]	auto[EscalateSt]	5859065	1			T3	6544		T11	6754		T13	1343
auto[0]	auto[InvalidSt]	12418082	1			T25	9964		T45	2562		T44	6186
auto[1]	auto[ResetSt]	174	1			T3	4		T11	5		T22	4
auto[1]	auto[IdleSt]	117	1			T3	5		T11	3		T55	3
auto[1]	auto[ClkMuxSt]	25	1			T55	2		T207	1		T208	1
auto[1]	auto[CntIncrSt]	31	1			T57	2		T205	1		T209	1
auto[1]	auto[CntProgSt]	723	1			T3	4		T11	14		T22	7
auto[1]	auto[TransCheckSt]	67	1			T3	2		T22	5		T56	4
auto[1]	auto[TokenHashSt]	581	1			T3	15		T11	4		T22	31
auto[1]	auto[FlashRmaSt]	32	1			T3	1		T11	1		T22	3
auto[1]	auto[TokenCheck0St]	41	1			T11	1		T22	1		T55	1
auto[1]	auto[TokenCheck1St]	15	1			T3	1		T22	1		T206	1
auto[1]	auto[TransProgSt]	533	1			T3	3		T11	13		T22	5
auto[1]	auto[PostTransSt]	2779	1			T3	11		T11	1		T13	3
auto[1]	auto[ScrapSt]	48	1			T3	1		T11	1		T205	1
auto[1]	auto[EscalateSt]	1476920	1			T3	9265		T11	9840		T13	294
auto[1]	auto[InvalidSt]	7614	1			T25	30		T45	8		T43	1