Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105362104

1

T1

37372

T2

36568

T3

425945

auto[1]

1439204

1

T3

592

T5

27127

T10

12126

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105371684

1

T1

37372

T2

36568

T3

426339

auto[1]

1429624

1

T3

198

T5

27092

T10

11893

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7503935	1			T1	5067		T2	107		T3	13183
auto[IdleSt]	20521104	1			T1	7081		T2	36461		T3	191067
auto[ClkMuxSt]	36685	1			T1	57		T3	96		T4	68
auto[CntIncrSt]	36514	1			T1	57		T3	96		T4	68
auto[CntProgSt]	1450668	1			T1	13280		T3	17800		T4	5840
auto[TransCheckSt]	28281	1			T1	57		T3	82		T4	68
auto[TokenHashSt]	46256834	1			T1	610		T3	1451		T4	754
auto[FlashRmaSt]	37167	1			T3	145		T5	762		T8	124
auto[TokenCheck0St]	13074	1			T3	47		T5	283		T8	42
auto[TokenCheck1St]	9586	1			T3	39		T5	205		T8	13
auto[TransProgSt]	369306	1			T3	8542		T5	3174		T10	109
auto[PostTransSt]	12486070	1			T1	11163		T3	168798		T4	12957
auto[ScrapSt]	248332	1			T5	474		T10	4		T11	446
auto[EscalateSt]	6596582	1			T3	11809		T5	169799		T10	17019
auto[InvalidSt]	11205222	1			T3	13381		T5	281670		T11	226197

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1948	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11205222	1			T3	13381		T5	281670		T11	226197
EscalateSt	6596582	1			T3	11809		T5	169799		T10	17019
ScrapSt	248332	1			T5	474		T10	4		T11	446
PostTransSt	12486070	1			T1	11163		T3	168798		T4	12957
TransProgSt	369306	1			T3	8542		T5	3174		T10	109
TokenCheck1St	9586	1			T3	39		T5	205		T8	13
TokenCheck0St	13074	1			T3	47		T5	283		T8	42
FlashRmaSt	37167	1			T3	145		T5	762		T8	124
TokenHashSt	46256834	1			T1	610		T3	1451		T4	754
TransCheckSt	28281	1			T1	57		T3	82		T4	68
CntProgSt	1450668	1			T1	13280		T3	17800		T4	5840
CntIncrSt	36514	1			T1	57		T3	96		T4	68
ClkMuxSt	36685	1			T1	57		T3	96		T4	68
IdleSt	20521104	1			T1	7081		T2	36461		T3	191067
ResetSt	7503935	1			T1	5067		T2	107		T3	13183
arcs[ResetSt=>IdleSt]	55435	1			T1	58		T2	1		T3	104
arcs[IdleSt=>ScrapSt]	280	1			T5	3		T10	1		T11	2
arcs[IdleSt=>ClkMuxSt]	36537	1			T1	57		T3	96		T4	68
arcs[ClkMuxSt=>CntIncrSt]	36514	1			T1	57		T3	96		T4	68
arcs[CntIncrSt=>PostTransSt]	1931	1			T3	8		T5	100		T11	20
arcs[CntIncrSt=>CntProgSt]	34504	1			T1	57		T3	88		T4	68
arcs[CntProgSt=>PostTransSt]	5009	1			T3	6		T5	177		T11	87
arcs[CntProgSt=>TransCheckSt]	28281	1			T1	57		T3	82		T4	68
arcs[TransCheckSt=>PostTransSt]	3841	1			T3	10		T5	78		T8	47
arcs[TransCheckSt=>TokenHashSt]	24366	1			T1	57		T3	72		T4	68
arcs[TokenHashSt=>PostTransSt]	10540	1			T1	57		T3	25		T4	68
arcs[TokenHashSt=>FlashRmaSt]	13111	1			T3	47		T5	283		T8	42
arcs[FlashRmaSt=>TokenCheck0St]	13074	1			T3	47		T5	283		T8	42
arcs[TokenCheck0St=>PostTransSt]	3422	1			T3	8		T5	78		T8	29
arcs[TokenCheck0St=>TokenCheck1St]	9586	1			T3	39		T5	205		T8	13
arcs[TokenCheck1St=>PostTransSt]	655	1			T5	8		T8	13		T11	3
arcs[TransProgSt=>PostTransSt]	8002	1			T3	39		T5	197		T10	1
arcs[IdleSt=>EscalateSt]	175	1			T10	6		T36	4		T35	4
arcs[ClkMuxSt=>EscalateSt]	23	1			T31	3		T32	1		T33	1
arcs[CntIncrSt=>EscalateSt]	79	1			T10	4		T34	3		T35	5
arcs[CntProgSt=>EscalateSt]	1214	1			T10	20		T34	47		T36	8
arcs[TransCheckSt=>EscalateSt]	74	1			T36	6		T35	1		T40	2
arcs[TokenHashSt=>EscalateSt]	715	1			T5	1		T10	12		T34	10
arcs[FlashRmaSt=>EscalateSt]	37	1			T10	1		T32	1		T37	2
arcs[TokenCheck0St=>EscalateSt]	66	1			T10	1		T40	2		T31	2
arcs[TokenCheck1St=>EscalateSt]	37	1			T10	4		T34	2		T36	1
arcs[TransProgSt=>EscalateSt]	892	1			T10	29		T34	23		T36	7
arcs[PostTransSt=>EscalateSt]	5272	1			T3	6		T5	177		T10	1
arcs[InvalidSt=>EscalateSt]	14240	1			T3	2		T5	372		T11	338

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7503762	1			T1	5067		T2	107		T3	13183
auto[0]	auto[IdleSt]	20520984	1			T1	7081		T2	36461		T3	191067
auto[0]	auto[ClkMuxSt]	36671	1			T1	57		T3	96		T4	68
auto[0]	auto[CntIncrSt]	36453	1			T1	57		T3	96		T4	68
auto[0]	auto[CntProgSt]	1449815	1			T1	13280		T3	17800		T4	5840
auto[0]	auto[TransCheckSt]	28235	1			T1	57		T3	82		T4	68
auto[0]	auto[TokenHashSt]	46256372	1			T1	610		T3	1451		T4	754
auto[0]	auto[FlashRmaSt]	37138	1			T3	145		T5	762		T8	124
auto[0]	auto[TokenCheck0St]	13028	1			T3	47		T5	283		T8	42
auto[0]	auto[TokenCheck1St]	9559	1			T3	39		T5	205		T8	13
auto[0]	auto[TransProgSt]	368696	1			T3	8542		T5	3174		T10	87
auto[0]	auto[PostTransSt]	12483429	1			T1	11163		T3	168794		T4	12957
auto[0]	auto[ScrapSt]	248290	1			T5	474		T10	3		T11	446
auto[0]	auto[EscalateSt]	5169611	1			T3	11223		T5	142947		T10	4955
auto[0]	auto[InvalidSt]	11198113	1			T3	13379		T5	281494		T11	226042
auto[1]	auto[ResetSt]	173	1			T10	7		T34	2		T36	4
auto[1]	auto[IdleSt]	120	1			T10	5		T36	3		T35	1
auto[1]	auto[ClkMuxSt]	14	1			T31	2		T32	1		T202	1
auto[1]	auto[CntIncrSt]	61	1			T10	2		T34	3		T35	4
auto[1]	auto[CntProgSt]	853	1			T10	15		T34	32		T36	7
auto[1]	auto[TransCheckSt]	46	1			T36	4		T35	1		T40	1
auto[1]	auto[TokenHashSt]	462	1			T5	1		T10	5		T34	7
auto[1]	auto[FlashRmaSt]	29	1			T10	1		T32	1		T37	2
auto[1]	auto[TokenCheck0St]	46	1			T40	1		T31	2		T37	2
auto[1]	auto[TokenCheck1St]	27	1			T10	3		T34	2		T36	1
auto[1]	auto[TransProgSt]	610	1			T10	22		T34	16		T36	6
auto[1]	auto[PostTransSt]	2641	1			T3	4		T5	98		T10	1
auto[1]	auto[ScrapSt]	42	1			T10	1		T36	1		T35	1
auto[1]	auto[EscalateSt]	1426971	1			T3	586		T5	26852		T10	12064
auto[1]	auto[InvalidSt]	7109	1			T3	2		T5	176		T11	155

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7503745	1			T1	5067		T2	107		T3	13183
auto[0]	auto[IdleSt]	20520991	1			T1	7081		T2	36461		T3	191067
auto[0]	auto[ClkMuxSt]	36667	1			T1	57		T3	96		T4	68
auto[0]	auto[CntIncrSt]	36469	1			T1	57		T3	96		T4	68
auto[0]	auto[CntProgSt]	1449881	1			T1	13280		T3	17800		T4	5840
auto[0]	auto[TransCheckSt]	28233	1			T1	57		T3	82		T4	68
auto[0]	auto[TokenHashSt]	46256356	1			T1	610		T3	1451		T4	754
auto[0]	auto[FlashRmaSt]	37151	1			T3	145		T5	762		T8	124
auto[0]	auto[TokenCheck0St]	13035	1			T3	47		T5	283		T8	42
auto[0]	auto[TokenCheck1St]	9567	1			T3	39		T5	205		T8	13
auto[0]	auto[TransProgSt]	368719	1			T3	8542		T5	3174		T10	89
auto[0]	auto[PostTransSt]	12483373	1			T1	11163		T3	168796		T4	12957
auto[0]	auto[ScrapSt]	248293	1			T5	474		T10	3		T11	446
auto[0]	auto[EscalateSt]	5179165	1			T3	11613		T5	142982		T10	5187
auto[0]	auto[InvalidSt]	11198091	1			T3	13381		T5	281474		T11	226014
auto[1]	auto[ResetSt]	190	1			T10	6		T34	5		T36	4
auto[1]	auto[IdleSt]	113	1			T10	4		T36	2		T35	3
auto[1]	auto[ClkMuxSt]	18	1			T31	2		T32	1		T33	1
auto[1]	auto[CntIncrSt]	45	1			T10	3		T34	1		T35	2
auto[1]	auto[CntProgSt]	787	1			T10	12		T34	39		T36	4
auto[1]	auto[TransCheckSt]	48	1			T36	4		T40	2		T31	4
auto[1]	auto[TokenHashSt]	478	1			T10	12		T34	6		T36	12
auto[1]	auto[FlashRmaSt]	16	1			T32	1		T37	1		T203	1
auto[1]	auto[TokenCheck0St]	39	1			T10	1		T40	1		T32	2
auto[1]	auto[TokenCheck1St]	19	1			T10	2		T34	1		T37	1
auto[1]	auto[TransProgSt]	587	1			T10	20		T34	13		T36	4
auto[1]	auto[PostTransSt]	2697	1			T3	2		T5	79		T11	45
auto[1]	auto[ScrapSt]	39	1			T10	1		T36	2		T35	1
auto[1]	auto[EscalateSt]	1417417	1			T3	196		T5	26817		T10	11832
auto[1]	auto[InvalidSt]	7131	1			T5	196		T11	183		T12	21