Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53323 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
71 | 
| auto[1] | 
1755 | 
1 | 
 | 
 | 
T3 | 
13 | 
 | 
T4 | 
8 | 
 | 
T16 | 
12 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54293 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
785 | 
1 | 
 | 
 | 
T14 | 
16 | 
 | 
T19 | 
14 | 
 | 
T65 | 
11 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53083 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
1995 | 
1 | 
 | 
 | 
T11 | 
2 | 
 | 
T12 | 
10 | 
 | 
T13 | 
5 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53145 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
1933 | 
1 | 
 | 
 | 
T11 | 
1 | 
 | 
T12 | 
2 | 
 | 
T13 | 
9 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53069 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
2009 | 
1 | 
 | 
 | 
T12 | 
11 | 
 | 
T13 | 
6 | 
 | 
T6 | 
8 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
49764 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| no_err_inj | 
5314 | 
1 | 
 | 
 | 
T11 | 
12 | 
 | 
T5 | 
13 | 
 | 
T70 | 
7 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53327 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
71 | 
| auto[1] | 
1751 | 
1 | 
 | 
 | 
T3 | 
13 | 
 | 
T4 | 
7 | 
 | 
T16 | 
10 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54319 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
759 | 
1 | 
 | 
 | 
T14 | 
14 | 
 | 
T19 | 
10 | 
 | 
T65 | 
16 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
38809 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
16269 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53153 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
1925 | 
1 | 
 | 
 | 
T12 | 
11 | 
 | 
T13 | 
3 | 
 | 
T6 | 
13 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53043 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
2035 | 
1 | 
 | 
 | 
T12 | 
9 | 
 | 
T13 | 
6 | 
 | 
T6 | 
10 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53133 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
1945 | 
1 | 
 | 
 | 
T12 | 
9 | 
 | 
T13 | 
8 | 
 | 
T6 | 
12 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53349 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
73 | 
| auto[1] | 
1729 | 
1 | 
 | 
 | 
T3 | 
11 | 
 | 
T4 | 
12 | 
 | 
T16 | 
8 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52576 | 
1 | 
 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
 | 
T11 | 
15 | 
| auto[1] | 
2502 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T27 | 
15 | 
 | 
T64 | 
17 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54317 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
761 | 
1 | 
 | 
 | 
T14 | 
12 | 
 | 
T19 | 
12 | 
 | 
T65 | 
17 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54339 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
739 | 
1 | 
 | 
 | 
T14 | 
22 | 
 | 
T19 | 
9 | 
 | 
T65 | 
11 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54318 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
760 | 
1 | 
 | 
 | 
T14 | 
15 | 
 | 
T19 | 
15 | 
 | 
T65 | 
7 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52310 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
2768 | 
1 | 
 | 
 | 
T11 | 
15 | 
 | 
T23 | 
14 | 
 | 
T18 | 
18 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
51231 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
3847 | 
1 | 
 | 
 | 
T21 | 
75 | 
 | 
T54 | 
58 | 
 | 
T55 | 
96 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53101 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
1977 | 
1 | 
 | 
 | 
T12 | 
7 | 
 | 
T13 | 
8 | 
 | 
T6 | 
11 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53071 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
2007 | 
1 | 
 | 
 | 
T12 | 
10 | 
 | 
T13 | 
3 | 
 | 
T6 | 
12 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53126 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[1] | 
1952 | 
1 | 
 | 
 | 
T12 | 
16 | 
 | 
T13 | 
5 | 
 | 
T6 | 
5 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53176 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
68 | 
| auto[1] | 
1902 | 
1 | 
 | 
 | 
T3 | 
16 | 
 | 
T4 | 
10 | 
 | 
T16 | 
11 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49616 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
80 | 
| auto[1] | 
5462 | 
1 | 
 | 
 | 
T3 | 
4 | 
 | 
T4 | 
5 | 
 | 
T22 | 
70 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
51299 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T3 | 
84 | 
 | 
T11 | 
15 | 
| auto[1] | 
3779 | 
1 | 
 | 
 | 
T2 | 
81 | 
 | 
T17 | 
89 | 
 | 
T50 | 
76 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55078 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53261 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
73 | 
| auto[1] | 
1817 | 
1 | 
 | 
 | 
T3 | 
11 | 
 | 
T4 | 
11 | 
 | 
T16 | 
9 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53246 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
78 | 
| auto[1] | 
1832 | 
1 | 
 | 
 | 
T3 | 
6 | 
 | 
T4 | 
6 | 
 | 
T16 | 
16 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53272 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
74 | 
| auto[1] | 
1806 | 
1 | 
 | 
 | 
T3 | 
10 | 
 | 
T4 | 
8 | 
 | 
T16 | 
10 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
48379 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
no_err_inj | 
3931 | 
1 | 
 | 
 | 
T5 | 
13 | 
 | 
T70 | 
7 | 
 | 
T23 | 
34 | 
| auto[1] | 
err_inj | 
1385 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T23 | 
7 | 
 | 
T18 | 
10 | 
| auto[1] | 
no_err_inj | 
1383 | 
1 | 
 | 
 | 
T11 | 
12 | 
 | 
T23 | 
7 | 
 | 
T18 | 
8 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50453 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1857 | 
1 | 
 | 
 | 
T12 | 
10 | 
 | 
T13 | 
3 | 
 | 
T6 | 
12 | 
| auto[1] | 
auto[0] | 
2618 | 
1 | 
 | 
 | 
T11 | 
15 | 
 | 
T23 | 
13 | 
 | 
T18 | 
17 | 
| auto[1] | 
auto[1] | 
150 | 
1 | 
 | 
 | 
T23 | 
1 | 
 | 
T18 | 
1 | 
 | 
T210 | 
2 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50437 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1873 | 
1 | 
 | 
 | 
T12 | 
9 | 
 | 
T13 | 
6 | 
 | 
T6 | 
10 | 
| auto[1] | 
auto[0] | 
2606 | 
1 | 
 | 
 | 
T11 | 
15 | 
 | 
T23 | 
14 | 
 | 
T18 | 
16 | 
| auto[1] | 
auto[1] | 
162 | 
1 | 
 | 
 | 
T18 | 
2 | 
 | 
T211 | 
2 | 
 | 
T26 | 
1 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50513 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1797 | 
1 | 
 | 
 | 
T12 | 
16 | 
 | 
T13 | 
5 | 
 | 
T6 | 
5 | 
| auto[1] | 
auto[0] | 
2613 | 
1 | 
 | 
 | 
T11 | 
15 | 
 | 
T23 | 
13 | 
 | 
T18 | 
18 | 
| auto[1] | 
auto[1] | 
155 | 
1 | 
 | 
 | 
T23 | 
1 | 
 | 
T26 | 
1 | 
 | 
T210 | 
1 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50521 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1789 | 
1 | 
 | 
 | 
T12 | 
2 | 
 | 
T13 | 
9 | 
 | 
T6 | 
8 | 
| auto[1] | 
auto[0] | 
2624 | 
1 | 
 | 
 | 
T11 | 
14 | 
 | 
T23 | 
12 | 
 | 
T18 | 
17 | 
| auto[1] | 
auto[1] | 
144 | 
1 | 
 | 
 | 
T11 | 
1 | 
 | 
T23 | 
2 | 
 | 
T18 | 
1 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50462 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1848 | 
1 | 
 | 
 | 
T12 | 
11 | 
 | 
T13 | 
6 | 
 | 
T6 | 
8 | 
| auto[1] | 
auto[0] | 
2607 | 
1 | 
 | 
 | 
T11 | 
15 | 
 | 
T23 | 
12 | 
 | 
T18 | 
15 | 
| auto[1] | 
auto[1] | 
161 | 
1 | 
 | 
 | 
T23 | 
2 | 
 | 
T18 | 
3 | 
 | 
T26 | 
1 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50478 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1832 | 
1 | 
 | 
 | 
T12 | 
10 | 
 | 
T13 | 
5 | 
 | 
T6 | 
11 | 
| auto[1] | 
auto[0] | 
2605 | 
1 | 
 | 
 | 
T11 | 
13 | 
 | 
T23 | 
14 | 
 | 
T18 | 
17 | 
| auto[1] | 
auto[1] | 
163 | 
1 | 
 | 
 | 
T11 | 
2 | 
 | 
T18 | 
1 | 
 | 
T211 | 
1 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37810 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
71 | 
| auto[0] | 
auto[1] | 
999 | 
1 | 
 | 
 | 
T3 | 
13 | 
 | 
T16 | 
12 | 
 | 
T45 | 
10 | 
| auto[1] | 
auto[0] | 
15513 | 
1 | 
 | 
 | 
T4 | 
59 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
| auto[1] | 
auto[1] | 
756 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T23 | 
12 | 
 | 
T26 | 
9 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37760 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
71 | 
| auto[0] | 
auto[1] | 
1049 | 
1 | 
 | 
 | 
T3 | 
13 | 
 | 
T16 | 
10 | 
 | 
T45 | 
10 | 
| auto[1] | 
auto[0] | 
15567 | 
1 | 
 | 
 | 
T4 | 
60 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
| auto[1] | 
auto[1] | 
702 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T23 | 
8 | 
 | 
T18 | 
2 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37258 | 
1 | 
 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
 | 
T11 | 
15 | 
| auto[0] | 
auto[1] | 
1551 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T27 | 
15 | 
 | 
T64 | 
17 | 
| auto[1] | 
auto[0] | 
15318 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
| auto[1] | 
auto[1] | 
951 | 
1 | 
 | 
 | 
T18 | 
45 | 
 | 
T24 | 
3 | 
 | 
T26 | 
7 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37754 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
73 | 
| auto[0] | 
auto[1] | 
1055 | 
1 | 
 | 
 | 
T3 | 
11 | 
 | 
T16 | 
8 | 
 | 
T45 | 
10 | 
| auto[1] | 
auto[0] | 
15595 | 
1 | 
 | 
 | 
T4 | 
55 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
| auto[1] | 
auto[1] | 
674 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T23 | 
9 | 
 | 
T18 | 
1 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34080 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
80 | 
| auto[0] | 
auto[1] | 
4729 | 
1 | 
 | 
 | 
T3 | 
4 | 
 | 
T22 | 
70 | 
 | 
T20 | 
58 | 
| auto[1] | 
auto[0] | 
15536 | 
1 | 
 | 
 | 
T4 | 
62 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
| auto[1] | 
auto[1] | 
733 | 
1 | 
 | 
 | 
T4 | 
5 | 
 | 
T23 | 
13 | 
 | 
T18 | 
2 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37598 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1211 | 
1 | 
 | 
 | 
T12 | 
10 | 
 | 
T13 | 
3 | 
 | 
T35 | 
12 | 
| auto[1] | 
auto[0] | 
15473 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
78 | 
| auto[1] | 
auto[1] | 
796 | 
1 | 
 | 
 | 
T6 | 
12 | 
 | 
T23 | 
1 | 
 | 
T18 | 
20 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37575 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1234 | 
1 | 
 | 
 | 
T12 | 
7 | 
 | 
T13 | 
8 | 
 | 
T35 | 
13 | 
| auto[1] | 
auto[0] | 
15526 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
79 | 
| auto[1] | 
auto[1] | 
743 | 
1 | 
 | 
 | 
T6 | 
11 | 
 | 
T18 | 
14 | 
 | 
T69 | 
12 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37577 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1232 | 
1 | 
 | 
 | 
T12 | 
9 | 
 | 
T13 | 
6 | 
 | 
T35 | 
9 | 
| auto[1] | 
auto[0] | 
15466 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
80 | 
| auto[1] | 
auto[1] | 
803 | 
1 | 
 | 
 | 
T6 | 
10 | 
 | 
T18 | 
16 | 
 | 
T69 | 
12 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37662 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1147 | 
1 | 
 | 
 | 
T12 | 
11 | 
 | 
T13 | 
3 | 
 | 
T35 | 
10 | 
| auto[1] | 
auto[0] | 
15491 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
77 | 
| auto[1] | 
auto[1] | 
778 | 
1 | 
 | 
 | 
T6 | 
13 | 
 | 
T23 | 
1 | 
 | 
T18 | 
12 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37630 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1179 | 
1 | 
 | 
 | 
T11 | 
1 | 
 | 
T12 | 
2 | 
 | 
T13 | 
9 | 
| auto[1] | 
auto[0] | 
15515 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
82 | 
| auto[1] | 
auto[1] | 
754 | 
1 | 
 | 
 | 
T6 | 
8 | 
 | 
T23 | 
2 | 
 | 
T18 | 
7 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37576 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1233 | 
1 | 
 | 
 | 
T11 | 
2 | 
 | 
T12 | 
10 | 
 | 
T13 | 
5 | 
| auto[1] | 
auto[0] | 
15507 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
79 | 
| auto[1] | 
auto[1] | 
762 | 
1 | 
 | 
 | 
T6 | 
11 | 
 | 
T18 | 
12 | 
 | 
T69 | 
9 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37733 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
74 | 
| auto[0] | 
auto[1] | 
1076 | 
1 | 
 | 
 | 
T3 | 
10 | 
 | 
T16 | 
10 | 
 | 
T45 | 
12 | 
| auto[1] | 
auto[0] | 
15539 | 
1 | 
 | 
 | 
T4 | 
59 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
| auto[1] | 
auto[1] | 
730 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T23 | 
6 | 
 | 
T18 | 
1 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37730 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
78 | 
| auto[0] | 
auto[1] | 
1079 | 
1 | 
 | 
 | 
T3 | 
6 | 
 | 
T16 | 
16 | 
 | 
T45 | 
11 | 
| auto[1] | 
auto[0] | 
15516 | 
1 | 
 | 
 | 
T4 | 
61 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
| auto[1] | 
auto[1] | 
753 | 
1 | 
 | 
 | 
T4 | 
6 | 
 | 
T23 | 
12 | 
 | 
T18 | 
3 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37349 | 
1 | 
 | 
 | 
T1 | 
16 | 
 | 
T2 | 
81 | 
 | 
T3 | 
84 | 
| auto[0] | 
auto[1] | 
1460 | 
1 | 
 | 
 | 
T11 | 
15 | 
 | 
T18 | 
10 | 
 | 
T211 | 
10 | 
| auto[1] | 
auto[0] | 
14961 | 
1 | 
 | 
 | 
T4 | 
67 | 
 | 
T5 | 
13 | 
 | 
T6 | 
90 | 
| auto[1] | 
auto[1] | 
1308 | 
1 | 
 | 
 | 
T23 | 
14 | 
 | 
T18 | 
8 | 
 | 
T69 | 
36 |