Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106264279

1

T1

5009

T2

30450

T3

47579

auto[1]

1440399

1

T1

792

T3

891

T11

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106262805

1

T1

5009

T2

30450

T3

48074

auto[1]

1441873

1

T1

792

T3

396

T11

99

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7559916	1			T1	1670		T2	7642		T3	11372
auto[IdleSt]	24265168	1			T1	1046		T2	8860		T3	3054
auto[ClkMuxSt]	36180	1			T1	16		T2	81		T3	84
auto[CntIncrSt]	35948	1			T1	16		T2	81		T3	84
auto[CntProgSt]	1821485	1			T1	32		T2	162		T3	17780
auto[TransCheckSt]	28040	1			T2	81		T3	65		T10	1
auto[TokenHashSt]	40635587	1			T2	717		T3	606		T10	10
auto[FlashRmaSt]	36705	1			T2	33		T3	24		T11	29
auto[TokenCheck0St]	13087	1			T2	23		T3	24		T11	12
auto[TokenCheck1St]	9817	1			T2	7		T3	13		T11	12
auto[TransProgSt]	464655	1			T3	2147		T11	1500		T4	25
auto[PostTransSt]	13791898	1			T1	950		T2	12763		T3	11610
auto[ScrapSt]	141898	1			T21	8		T23	657		T18	1063
auto[EscalateSt]	7071356	1			T1	2071		T3	1607		T11	693
auto[InvalidSt]	11790829	1			T11	403		T12	8399		T13	5578

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2109	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11790829	1			T11	403		T12	8399		T13	5578
EscalateSt	7071356	1			T1	2071		T3	1607		T11	693
ScrapSt	141898	1			T21	8		T23	657		T18	1063
PostTransSt	13791898	1			T1	950		T2	12763		T3	11610
TransProgSt	464655	1			T3	2147		T11	1500		T4	25
TokenCheck1St	9817	1			T2	7		T3	13		T11	12
TokenCheck0St	13087	1			T2	23		T3	24		T11	12
FlashRmaSt	36705	1			T2	33		T3	24		T11	29
TokenHashSt	40635587	1			T2	717		T3	606		T10	10
TransCheckSt	28040	1			T2	81		T3	65		T10	1
CntProgSt	1821485	1			T1	32		T2	162		T3	17780
CntIncrSt	35948	1			T1	16		T2	81		T3	84
ClkMuxSt	36180	1			T1	16		T2	81		T3	84
IdleSt	24265168	1			T1	1046		T2	8860		T3	3054
ResetSt	7559916	1			T1	1670		T2	7642		T3	11372
arcs[ResetSt=>IdleSt]	55329	1			T1	17		T2	82		T3	85
arcs[IdleSt=>ScrapSt]	310	1			T21	2		T23	2		T18	4
arcs[IdleSt=>ClkMuxSt]	35972	1			T1	16		T2	81		T3	84
arcs[ClkMuxSt=>CntIncrSt]	35948	1			T1	16		T2	81		T3	84
arcs[CntIncrSt=>PostTransSt]	1834	1			T3	6		T4	6		T16	16
arcs[CntIncrSt=>CntProgSt]	34038	1			T1	16		T2	81		T3	78
arcs[CntProgSt=>PostTransSt]	5017	1			T1	16		T3	13		T4	7
arcs[CntProgSt=>TransCheckSt]	28040	1			T2	81		T3	65		T10	1
arcs[TransCheckSt=>PostTransSt]	3731	1			T2	49		T3	10		T4	8
arcs[TransCheckSt=>TokenHashSt]	24162	1			T2	32		T3	55		T10	1
arcs[TokenHashSt=>PostTransSt]	10157	1			T2	9		T3	31		T10	1
arcs[TokenHashSt=>FlashRmaSt]	13120	1			T2	23		T3	24		T11	12
arcs[FlashRmaSt=>TokenCheck0St]	13087	1			T2	23		T3	24		T11	12
arcs[TokenCheck0St=>PostTransSt]	3204	1			T2	16		T3	11		T4	7
arcs[TokenCheck0St=>TokenCheck1St]	9817	1			T2	7		T3	13		T11	12
arcs[TokenCheck1St=>PostTransSt]	648	1			T2	7		T3	1		T14	3
arcs[TransProgSt=>PostTransSt]	8399	1			T3	12		T11	12		T4	13
arcs[IdleSt=>EscalateSt]	173	1			T21	6		T57	4		T51	5
arcs[ClkMuxSt=>EscalateSt]	24	1			T51	1		T52	2		T53	1
arcs[CntIncrSt=>EscalateSt]	76	1			T21	1		T54	3		T55	6
arcs[CntProgSt=>EscalateSt]	981	1			T21	2		T54	29		T55	14
arcs[TransCheckSt=>EscalateSt]	147	1			T21	4		T55	5		T58	10
arcs[TokenHashSt=>EscalateSt]	885	1			T21	15		T54	5		T55	28
arcs[FlashRmaSt=>EscalateSt]	33	1			T21	1		T54	1		T56	1
arcs[TokenCheck0St=>EscalateSt]	66	1			T21	4		T54	3		T55	2
arcs[TokenCheck1St=>EscalateSt]	35	1			T21	1		T56	2		T58	2
arcs[TransProgSt=>EscalateSt]	735	1			T21	6		T54	15		T55	17
arcs[PostTransSt=>EscalateSt]	5408	1			T1	16		T3	13		T4	8
arcs[InvalidSt=>EscalateSt]	14638	1			T11	3		T12	60		T13	40

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7559746	1			T1	1670		T2	7642		T3	11372
auto[0]	auto[IdleSt]	24265063	1			T1	1046		T2	8860		T3	3054
auto[0]	auto[ClkMuxSt]	36163	1			T1	16		T2	81		T3	84
auto[0]	auto[CntIncrSt]	35895	1			T1	16		T2	81		T3	84
auto[0]	auto[CntProgSt]	1820829	1			T1	32		T2	162		T3	17780
auto[0]	auto[TransCheckSt]	27933	1			T2	81		T3	65		T10	1
auto[0]	auto[TokenHashSt]	40635014	1			T2	717		T3	606		T10	10
auto[0]	auto[FlashRmaSt]	36684	1			T2	33		T3	24		T11	29
auto[0]	auto[TokenCheck0St]	13046	1			T2	23		T3	24		T11	12
auto[0]	auto[TokenCheck1St]	9793	1			T2	7		T3	13		T11	12
auto[0]	auto[TransProgSt]	464150	1			T3	2147		T11	1500		T4	25
auto[0]	auto[PostTransSt]	13789174	1			T1	942		T2	12763		T3	11601
auto[0]	auto[ScrapSt]	141847	1			T21	6		T23	657		T18	1063
auto[0]	auto[EscalateSt]	5643273	1			T1	1287		T3	725		T11	497
auto[0]	auto[InvalidSt]	11783560	1			T11	401		T12	8371		T13	5559
auto[1]	auto[ResetSt]	170	1			T21	8		T55	4		T56	3
auto[1]	auto[IdleSt]	105	1			T21	1		T57	4		T51	2
auto[1]	auto[ClkMuxSt]	17	1			T51	1		T52	1		T208	2
auto[1]	auto[CntIncrSt]	53	1			T54	3		T55	2		T56	2
auto[1]	auto[CntProgSt]	656	1			T54	13		T55	10		T57	18
auto[1]	auto[TransCheckSt]	107	1			T21	2		T55	3		T58	4
auto[1]	auto[TokenHashSt]	573	1			T21	8		T54	3		T55	17
auto[1]	auto[FlashRmaSt]	21	1			T21	1		T54	1		T53	1
auto[1]	auto[TokenCheck0St]	41	1			T21	2		T54	3		T55	2
auto[1]	auto[TokenCheck1St]	24	1			T21	1		T56	2		T58	1
auto[1]	auto[TransProgSt]	505	1			T21	5		T54	10		T55	13
auto[1]	auto[PostTransSt]	2724	1			T1	8		T3	9		T4	5
auto[1]	auto[ScrapSt]	51	1			T21	2		T54	1		T57	3
auto[1]	auto[EscalateSt]	1428083	1			T1	784		T3	882		T11	196
auto[1]	auto[InvalidSt]	7269	1			T11	2		T12	28		T13	19

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7559747	1			T1	1670		T2	7642		T3	11372
auto[0]	auto[IdleSt]	24265047	1			T1	1046		T2	8860		T3	3054
auto[0]	auto[ClkMuxSt]	36164	1			T1	16		T2	81		T3	84
auto[0]	auto[CntIncrSt]	35900	1			T1	16		T2	81		T3	84
auto[0]	auto[CntProgSt]	1820861	1			T1	32		T2	162		T3	17780
auto[0]	auto[TransCheckSt]	27956	1			T2	81		T3	65		T10	1
auto[0]	auto[TokenHashSt]	40635016	1			T2	717		T3	606		T10	10
auto[0]	auto[FlashRmaSt]	36679	1			T2	33		T3	24		T11	29
auto[0]	auto[TokenCheck0St]	13042	1			T2	23		T3	24		T11	12
auto[0]	auto[TokenCheck1St]	9798	1			T2	7		T3	13		T11	12
auto[0]	auto[TransProgSt]	464201	1			T3	2147		T11	1500		T4	25
auto[0]	auto[PostTransSt]	13789088	1			T1	942		T2	12763		T3	11606
auto[0]	auto[ScrapSt]	141856	1			T21	8		T23	657		T18	1063
auto[0]	auto[EscalateSt]	5641881	1			T1	1287		T3	1215		T11	595
auto[0]	auto[InvalidSt]	11783460	1			T11	402		T12	8367		T13	5557
auto[1]	auto[ResetSt]	169	1			T21	7		T55	3		T57	1
auto[1]	auto[IdleSt]	121	1			T21	6		T57	3		T51	4
auto[1]	auto[ClkMuxSt]	16	1			T51	1		T52	2		T53	1
auto[1]	auto[CntIncrSt]	48	1			T21	1		T55	6		T52	2
auto[1]	auto[CntProgSt]	624	1			T21	2		T54	26		T55	10
auto[1]	auto[TransCheckSt]	84	1			T21	2		T55	3		T58	7
auto[1]	auto[TokenHashSt]	571	1			T21	10		T54	5		T55	20
auto[1]	auto[FlashRmaSt]	26	1			T54	1		T56	1		T209	1
auto[1]	auto[TokenCheck0St]	45	1			T21	2		T54	1		T55	1
auto[1]	auto[TokenCheck1St]	19	1			T21	1		T56	1		T58	1
auto[1]	auto[TransProgSt]	454	1			T21	3		T54	9		T55	12
auto[1]	auto[PostTransSt]	2810	1			T1	8		T3	4		T4	3
auto[1]	auto[ScrapSt]	42	1			T55	1		T57	2		T58	2
auto[1]	auto[EscalateSt]	1429475	1			T1	784		T3	392		T11	98
auto[1]	auto[InvalidSt]	7369	1			T11	1		T12	32		T13	21