Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114841356

1

T1

35209

T2

21005

T3

4584

auto[1]

1510183

1

T1

1287

T2

2970

T3

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114842420

1

T1

34813

T2

19817

T3

4584

auto[1]

1509119

1

T1

1683

T2

4158

T3

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8053487	1			T1	8981		T2	8644		T3	990
auto[IdleSt]	23285986	1			T1	7809		T2	1090		T3	1789
auto[ClkMuxSt]	37115	1			T1	70		T3	10		T10	73
auto[CntIncrSt]	36871	1			T1	70		T3	10		T10	73
auto[CntProgSt]	1758698	1			T1	301		T3	20		T10	231
auto[TransCheckSt]	28442	1			T1	55		T10	54		T5	316
auto[TokenHashSt]	46401393	1			T1	608		T10	586		T5	994930
auto[FlashRmaSt]	37331	1			T1	207		T10	89		T5	400
auto[TokenCheck0St]	13058	1			T1	42		T10	44		T5	172
auto[TokenCheck1St]	9624	1			T1	27		T10	29		T5	126
auto[TransProgSt]	418172	1			T1	151		T10	111		T5	241
auto[PostTransSt]	14123960	1			T1	11556		T3	845		T10	11909
auto[ScrapSt]	403010	1			T5	54		T30	4		T9	568
auto[EscalateSt]	7679978	1			T1	4175		T2	8960		T3	1415
auto[InvalidSt]	14062244	1			T1	2444		T2	5274		T10	3085

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2170	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14062244	1			T1	2444		T2	5274		T10	3085
EscalateSt	7679978	1			T1	4175		T2	8960		T3	1415
ScrapSt	403010	1			T5	54		T30	4		T9	568
PostTransSt	14123960	1			T1	11556		T3	845		T10	11909
TransProgSt	418172	1			T1	151		T10	111		T5	241
TokenCheck1St	9624	1			T1	27		T10	29		T5	126
TokenCheck0St	13058	1			T1	42		T10	44		T5	172
FlashRmaSt	37331	1			T1	207		T10	89		T5	400
TokenHashSt	46401393	1			T1	608		T10	586		T5	994930
TransCheckSt	28442	1			T1	55		T10	54		T5	316
CntProgSt	1758698	1			T1	301		T3	20		T10	231
CntIncrSt	36871	1			T1	70		T3	10		T10	73
ClkMuxSt	37115	1			T1	70		T3	10		T10	73
IdleSt	23285986	1			T1	7809		T2	1090		T3	1789
ResetSt	8053487	1			T1	8981		T2	8644		T3	990
arcs[ResetSt=>IdleSt]	57418	1			T1	86		T2	82		T3	11
arcs[IdleSt=>ScrapSt]	286	1			T5	2		T30	1		T9	1
arcs[IdleSt=>ClkMuxSt]	36909	1			T1	70		T3	10		T10	73
arcs[ClkMuxSt=>CntIncrSt]	36871	1			T1	70		T3	10		T10	73
arcs[CntIncrSt=>PostTransSt]	2002	1			T5	28		T15	8		T9	19
arcs[CntIncrSt=>CntProgSt]	34799	1			T1	70		T3	10		T10	73
arcs[CntProgSt=>PostTransSt]	5189	1			T1	15		T3	10		T10	19
arcs[CntProgSt=>TransCheckSt]	28442	1			T1	55		T10	54		T5	316
arcs[TransCheckSt=>PostTransSt]	3855	1			T5	32		T15	8		T9	7
arcs[TransCheckSt=>TokenHashSt]	24502	1			T1	55		T10	54		T5	284
arcs[TokenHashSt=>PostTransSt]	10644	1			T1	13		T10	10		T5	108
arcs[TokenHashSt=>FlashRmaSt]	13098	1			T1	42		T10	44		T5	172
arcs[FlashRmaSt=>TokenCheck0St]	13058	1			T1	42		T10	44		T5	172
arcs[TokenCheck0St=>PostTransSt]	3374	1			T1	15		T10	15		T5	46
arcs[TokenCheck0St=>TokenCheck1St]	9624	1			T1	27		T10	29		T5	126
arcs[TokenCheck1St=>PostTransSt]	613	1			T1	2		T10	1		T5	5
arcs[TransProgSt=>PostTransSt]	8077	1			T1	25		T10	28		T5	121
arcs[IdleSt=>EscalateSt]	201	1			T42	9		T45	5		T39	6
arcs[ClkMuxSt=>EscalateSt]	38	1			T39	3		T40	3		T41	1
arcs[CntIncrSt=>EscalateSt]	70	1			T30	4		T42	2		T43	2
arcs[CntProgSt=>EscalateSt]	1168	1			T30	24		T42	31		T44	10
arcs[TransCheckSt=>EscalateSt]	85	1			T30	1		T42	1		T44	7
arcs[TokenHashSt=>EscalateSt]	760	1			T5	4		T30	5		T42	6
arcs[FlashRmaSt=>EscalateSt]	40	1			T44	2		T39	2		T40	1
arcs[TokenCheck0St=>EscalateSt]	60	1			T30	2		T42	6		T43	2
arcs[TokenCheck1St=>EscalateSt]	46	1			T44	1		T43	2		T45	2
arcs[TransProgSt=>EscalateSt]	888	1			T30	16		T42	20		T44	7
arcs[PostTransSt=>EscalateSt]	5443	1			T1	15		T3	10		T10	19
arcs[InvalidSt=>EscalateSt]	15524	1			T1	15		T2	72		T10	16

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8053304	1			T1	8981		T2	8644		T3	990
auto[0]	auto[IdleSt]	23285858	1			T1	7809		T2	1090		T3	1789
auto[0]	auto[ClkMuxSt]	37093	1			T1	70		T3	10		T10	73
auto[0]	auto[CntIncrSt]	36819	1			T1	70		T3	10		T10	73
auto[0]	auto[CntProgSt]	1757911	1			T1	301		T3	20		T10	231
auto[0]	auto[TransCheckSt]	28390	1			T1	55		T10	54		T5	316
auto[0]	auto[TokenHashSt]	46400897	1			T1	608		T10	586		T5	994929
auto[0]	auto[FlashRmaSt]	37308	1			T1	207		T10	89		T5	400
auto[0]	auto[TokenCheck0St]	13014	1			T1	42		T10	44		T5	172
auto[0]	auto[TokenCheck1St]	9589	1			T1	27		T10	29		T5	126
auto[0]	auto[TransProgSt]	417558	1			T1	151		T10	111		T5	241
auto[0]	auto[PostTransSt]	14121211	1			T1	11550		T3	840		T10	11899
auto[0]	auto[ScrapSt]	402976	1			T5	54		T30	3		T9	568
auto[0]	auto[EscalateSt]	6182776	1			T1	2901		T2	6020		T3	925
auto[0]	auto[InvalidSt]	14054482	1			T1	2437		T2	5244		T10	3077
auto[1]	auto[ResetSt]	183	1			T30	4		T42	3		T44	4
auto[1]	auto[IdleSt]	128	1			T42	7		T45	4		T39	2
auto[1]	auto[ClkMuxSt]	22	1			T39	2		T40	3		T217	1
auto[1]	auto[CntIncrSt]	52	1			T30	2		T42	1		T43	1
auto[1]	auto[CntProgSt]	787	1			T30	15		T42	21		T44	8
auto[1]	auto[TransCheckSt]	52	1			T42	1		T44	2		T43	3
auto[1]	auto[TokenHashSt]	496	1			T5	1		T30	3		T42	3
auto[1]	auto[FlashRmaSt]	23	1			T44	2		T39	2		T40	1
auto[1]	auto[TokenCheck0St]	44	1			T30	1		T42	6		T43	1
auto[1]	auto[TokenCheck1St]	35	1			T44	1		T45	2		T39	1
auto[1]	auto[TransProgSt]	614	1			T30	10		T42	15		T44	6
auto[1]	auto[PostTransSt]	2749	1			T1	6		T3	5		T10	10
auto[1]	auto[ScrapSt]	34	1			T30	1		T42	2		T45	1
auto[1]	auto[EscalateSt]	1497202	1			T1	1274		T2	2940		T3	490
auto[1]	auto[InvalidSt]	7762	1			T1	7		T2	30		T10	8

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8053309	1			T1	8981		T2	8644		T3	990
auto[0]	auto[IdleSt]	23285838	1			T1	7809		T2	1090		T3	1789
auto[0]	auto[ClkMuxSt]	37088	1			T1	70		T3	10		T10	73
auto[0]	auto[CntIncrSt]	36826	1			T1	70		T3	10		T10	73
auto[0]	auto[CntProgSt]	1757935	1			T1	301		T3	20		T10	231
auto[0]	auto[TransCheckSt]	28381	1			T1	55		T10	54		T5	316
auto[0]	auto[TokenHashSt]	46400886	1			T1	608		T10	586		T5	994927
auto[0]	auto[FlashRmaSt]	37300	1			T1	207		T10	89		T5	400
auto[0]	auto[TokenCheck0St]	13020	1			T1	42		T10	44		T5	172
auto[0]	auto[TokenCheck1St]	9594	1			T1	27		T10	29		T5	126
auto[0]	auto[TransProgSt]	417601	1			T1	151		T10	111		T5	241
auto[0]	auto[PostTransSt]	14121184	1			T1	11547		T3	840		T10	11900
auto[0]	auto[ScrapSt]	402970	1			T5	54		T30	4		T9	568
auto[0]	auto[EscalateSt]	6183836	1			T1	2509		T2	4844		T3	925
auto[0]	auto[InvalidSt]	14054482	1			T1	2436		T2	5232		T10	3077
auto[1]	auto[ResetSt]	178	1			T30	1		T42	3		T44	2
auto[1]	auto[IdleSt]	148	1			T42	8		T45	3		T39	6
auto[1]	auto[ClkMuxSt]	27	1			T39	2		T41	1		T217	2
auto[1]	auto[CntIncrSt]	45	1			T30	3		T42	2		T43	1
auto[1]	auto[CntProgSt]	763	1			T30	16		T42	21		T44	6
auto[1]	auto[TransCheckSt]	61	1			T30	1		T44	5		T43	5
auto[1]	auto[TokenHashSt]	507	1			T5	3		T30	3		T42	5
auto[1]	auto[FlashRmaSt]	31	1			T44	1		T39	1		T40	1
auto[1]	auto[TokenCheck0St]	38	1			T30	2		T42	5		T43	2
auto[1]	auto[TokenCheck1St]	30	1			T43	2		T45	2		T39	1
auto[1]	auto[TransProgSt]	571	1			T30	10		T42	14		T44	6
auto[1]	auto[PostTransSt]	2776	1			T1	9		T3	5		T10	9
auto[1]	auto[ScrapSt]	40	1			T44	1		T45	1		T39	2
auto[1]	auto[EscalateSt]	1496142	1			T1	1666		T2	4116		T3	490
auto[1]	auto[InvalidSt]	7762	1			T1	8		T2	42		T10	8