Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56471 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2071 | 
1 | 
 | 
 | 
T8 | 
8 | 
 | 
T13 | 
9 | 
 | 
T14 | 
52 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57800 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
742 | 
1 | 
 | 
 | 
T21 | 
18 | 
 | 
T62 | 
16 | 
 | 
T63 | 
13 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56377 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2165 | 
1 | 
 | 
 | 
T5 | 
10 | 
 | 
T24 | 
6 | 
 | 
T18 | 
1 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56372 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2170 | 
1 | 
 | 
 | 
T5 | 
10 | 
 | 
T24 | 
4 | 
 | 
T26 | 
1 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56279 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2263 | 
1 | 
 | 
 | 
T5 | 
10 | 
 | 
T24 | 
11 | 
 | 
T18 | 
2 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
53329 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T5 | 
91 | 
| no_err_inj | 
5213 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T9 | 
4 | 
 | 
T19 | 
2 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56549 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
1993 | 
1 | 
 | 
 | 
T8 | 
6 | 
 | 
T13 | 
5 | 
 | 
T14 | 
51 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57816 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
726 | 
1 | 
 | 
 | 
T21 | 
7 | 
 | 
T62 | 
14 | 
 | 
T63 | 
20 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
40293 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[1] | 
18249 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
56 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56408 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2134 | 
1 | 
 | 
 | 
T5 | 
9 | 
 | 
T24 | 
7 | 
 | 
T18 | 
1 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56341 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2201 | 
1 | 
 | 
 | 
T5 | 
4 | 
 | 
T24 | 
9 | 
 | 
T18 | 
2 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56349 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2193 | 
1 | 
 | 
 | 
T5 | 
14 | 
 | 
T24 | 
6 | 
 | 
T18 | 
1 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56509 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2033 | 
1 | 
 | 
 | 
T8 | 
6 | 
 | 
T13 | 
10 | 
 | 
T14 | 
49 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55983 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T9 | 
4 | 
| auto[1] | 
2559 | 
1 | 
 | 
 | 
T3 | 
3 | 
 | 
T60 | 
1 | 
 | 
T14 | 
12 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57799 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
743 | 
1 | 
 | 
 | 
T21 | 
6 | 
 | 
T62 | 
10 | 
 | 
T63 | 
16 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57832 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
710 | 
1 | 
 | 
 | 
T21 | 
10 | 
 | 
T62 | 
14 | 
 | 
T63 | 
13 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57752 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
790 | 
1 | 
 | 
 | 
T21 | 
11 | 
 | 
T62 | 
8 | 
 | 
T63 | 
24 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55330 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
3212 | 
1 | 
 | 
 | 
T18 | 
12 | 
 | 
T26 | 
14 | 
 | 
T14 | 
95 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54834 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
3708 | 
1 | 
 | 
 | 
T46 | 
88 | 
 | 
T43 | 
63 | 
 | 
T44 | 
83 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56356 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2186 | 
1 | 
 | 
 | 
T5 | 
14 | 
 | 
T24 | 
8 | 
 | 
T26 | 
3 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56449 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2093 | 
1 | 
 | 
 | 
T5 | 
11 | 
 | 
T24 | 
4 | 
 | 
T14 | 
26 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56420 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2122 | 
1 | 
 | 
 | 
T5 | 
9 | 
 | 
T24 | 
7 | 
 | 
T18 | 
1 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56577 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
1965 | 
1 | 
 | 
 | 
T8 | 
5 | 
 | 
T13 | 
14 | 
 | 
T14 | 
48 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52769 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[1] | 
5773 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T8 | 
7 | 
 | 
T17 | 
51 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54659 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
3883 | 
1 | 
 | 
 | 
T15 | 
84 | 
 | 
T16 | 
84 | 
 | 
T61 | 
91 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58542 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56432 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2110 | 
1 | 
 | 
 | 
T8 | 
7 | 
 | 
T13 | 
16 | 
 | 
T14 | 
51 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56533 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
2009 | 
1 | 
 | 
 | 
T8 | 
7 | 
 | 
T13 | 
9 | 
 | 
T14 | 
50 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56555 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[1] | 
1987 | 
1 | 
 | 
 | 
T8 | 
10 | 
 | 
T13 | 
6 | 
 | 
T14 | 
57 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
51696 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T5 | 
91 | 
| auto[0] | 
no_err_inj | 
3634 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T9 | 
4 | 
 | 
T19 | 
2 | 
| auto[1] | 
err_inj | 
1633 | 
1 | 
 | 
 | 
T18 | 
8 | 
 | 
T26 | 
9 | 
 | 
T14 | 
44 | 
| auto[1] | 
no_err_inj | 
1579 | 
1 | 
 | 
 | 
T18 | 
4 | 
 | 
T26 | 
5 | 
 | 
T14 | 
51 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53411 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[0] | 
auto[1] | 
1919 | 
1 | 
 | 
 | 
T5 | 
11 | 
 | 
T24 | 
4 | 
 | 
T14 | 
21 | 
| auto[1] | 
auto[0] | 
3038 | 
1 | 
 | 
 | 
T18 | 
12 | 
 | 
T26 | 
14 | 
 | 
T14 | 
90 | 
| auto[1] | 
auto[1] | 
174 | 
1 | 
 | 
 | 
T14 | 
5 | 
 | 
T55 | 
7 | 
 | 
T209 | 
1 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53286 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[0] | 
auto[1] | 
2044 | 
1 | 
 | 
 | 
T5 | 
4 | 
 | 
T24 | 
9 | 
 | 
T14 | 
20 | 
| auto[1] | 
auto[0] | 
3055 | 
1 | 
 | 
 | 
T18 | 
10 | 
 | 
T26 | 
12 | 
 | 
T14 | 
92 | 
| auto[1] | 
auto[1] | 
157 | 
1 | 
 | 
 | 
T18 | 
2 | 
 | 
T26 | 
2 | 
 | 
T14 | 
3 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53390 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[0] | 
auto[1] | 
1940 | 
1 | 
 | 
 | 
T5 | 
9 | 
 | 
T24 | 
7 | 
 | 
T14 | 
23 | 
| auto[1] | 
auto[0] | 
3030 | 
1 | 
 | 
 | 
T18 | 
11 | 
 | 
T26 | 
14 | 
 | 
T14 | 
90 | 
| auto[1] | 
auto[1] | 
182 | 
1 | 
 | 
 | 
T18 | 
1 | 
 | 
T14 | 
5 | 
 | 
T27 | 
1 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53335 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[0] | 
auto[1] | 
1995 | 
1 | 
 | 
 | 
T5 | 
10 | 
 | 
T24 | 
4 | 
 | 
T14 | 
23 | 
| auto[1] | 
auto[0] | 
3037 | 
1 | 
 | 
 | 
T18 | 
12 | 
 | 
T26 | 
13 | 
 | 
T14 | 
89 | 
| auto[1] | 
auto[1] | 
175 | 
1 | 
 | 
 | 
T26 | 
1 | 
 | 
T14 | 
6 | 
 | 
T27 | 
1 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53269 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[0] | 
auto[1] | 
2061 | 
1 | 
 | 
 | 
T5 | 
10 | 
 | 
T24 | 
11 | 
 | 
T14 | 
27 | 
| auto[1] | 
auto[0] | 
3010 | 
1 | 
 | 
 | 
T18 | 
10 | 
 | 
T26 | 
14 | 
 | 
T14 | 
88 | 
| auto[1] | 
auto[1] | 
202 | 
1 | 
 | 
 | 
T18 | 
2 | 
 | 
T14 | 
7 | 
 | 
T55 | 
6 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53346 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
| auto[0] | 
auto[1] | 
1984 | 
1 | 
 | 
 | 
T5 | 
10 | 
 | 
T24 | 
6 | 
 | 
T14 | 
28 | 
| auto[1] | 
auto[0] | 
3031 | 
1 | 
 | 
 | 
T18 | 
11 | 
 | 
T26 | 
14 | 
 | 
T14 | 
88 | 
| auto[1] | 
auto[1] | 
181 | 
1 | 
 | 
 | 
T18 | 
1 | 
 | 
T14 | 
7 | 
 | 
T55 | 
5 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39152 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1141 | 
1 | 
 | 
 | 
T13 | 
9 | 
 | 
T14 | 
31 | 
 | 
T35 | 
15 | 
| auto[1] | 
auto[0] | 
17319 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
48 | 
| auto[1] | 
auto[1] | 
930 | 
1 | 
 | 
 | 
T8 | 
8 | 
 | 
T14 | 
21 | 
 | 
T27 | 
14 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39244 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1049 | 
1 | 
 | 
 | 
T13 | 
5 | 
 | 
T14 | 
36 | 
 | 
T35 | 
6 | 
| auto[1] | 
auto[0] | 
17305 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
50 | 
| auto[1] | 
auto[1] | 
944 | 
1 | 
 | 
 | 
T8 | 
6 | 
 | 
T14 | 
15 | 
 | 
T27 | 
15 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38890 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T9 | 
4 | 
 | 
T24 | 
62 | 
| auto[0] | 
auto[1] | 
1403 | 
1 | 
 | 
 | 
T3 | 
3 | 
 | 
T60 | 
1 | 
 | 
T55 | 
17 | 
| auto[1] | 
auto[0] | 
17093 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
56 | 
| auto[1] | 
auto[1] | 
1156 | 
1 | 
 | 
 | 
T14 | 
12 | 
 | 
T27 | 
9 | 
 | 
T55 | 
65 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39187 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1106 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T14 | 
27 | 
 | 
T35 | 
14 | 
| auto[1] | 
auto[0] | 
17322 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
50 | 
| auto[1] | 
auto[1] | 
927 | 
1 | 
 | 
 | 
T8 | 
6 | 
 | 
T14 | 
22 | 
 | 
T27 | 
8 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
35414 | 
1 | 
 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
 | 
T24 | 
62 | 
| auto[0] | 
auto[1] | 
4879 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T17 | 
51 | 
 | 
T13 | 
12 | 
| auto[1] | 
auto[0] | 
17355 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
49 | 
| auto[1] | 
auto[1] | 
894 | 
1 | 
 | 
 | 
T8 | 
7 | 
 | 
T14 | 
17 | 
 | 
T27 | 
9 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38998 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1295 | 
1 | 
 | 
 | 
T24 | 
4 | 
 | 
T14 | 
22 | 
 | 
T87 | 
8 | 
| auto[1] | 
auto[0] | 
17451 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
80 | 
 | 
T8 | 
56 | 
| auto[1] | 
auto[1] | 
798 | 
1 | 
 | 
 | 
T5 | 
11 | 
 | 
T14 | 
4 | 
 | 
T88 | 
17 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38998 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1295 | 
1 | 
 | 
 | 
T24 | 
8 | 
 | 
T14 | 
19 | 
 | 
T87 | 
8 | 
| auto[1] | 
auto[0] | 
17358 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
77 | 
 | 
T8 | 
56 | 
| auto[1] | 
auto[1] | 
891 | 
1 | 
 | 
 | 
T5 | 
14 | 
 | 
T26 | 
3 | 
 | 
T14 | 
10 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38897 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1396 | 
1 | 
 | 
 | 
T24 | 
9 | 
 | 
T18 | 
2 | 
 | 
T14 | 
16 | 
| auto[1] | 
auto[0] | 
17444 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
87 | 
 | 
T8 | 
56 | 
| auto[1] | 
auto[1] | 
805 | 
1 | 
 | 
 | 
T5 | 
4 | 
 | 
T26 | 
2 | 
 | 
T14 | 
7 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38957 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1336 | 
1 | 
 | 
 | 
T24 | 
7 | 
 | 
T18 | 
1 | 
 | 
T14 | 
23 | 
| auto[1] | 
auto[0] | 
17451 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
82 | 
 | 
T8 | 
56 | 
| auto[1] | 
auto[1] | 
798 | 
1 | 
 | 
 | 
T5 | 
9 | 
 | 
T14 | 
7 | 
 | 
T88 | 
9 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38933 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1360 | 
1 | 
 | 
 | 
T24 | 
4 | 
 | 
T14 | 
24 | 
 | 
T87 | 
10 | 
| auto[1] | 
auto[0] | 
17439 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
81 | 
 | 
T8 | 
56 | 
| auto[1] | 
auto[1] | 
810 | 
1 | 
 | 
 | 
T5 | 
10 | 
 | 
T26 | 
1 | 
 | 
T14 | 
5 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38949 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1344 | 
1 | 
 | 
 | 
T24 | 
6 | 
 | 
T18 | 
1 | 
 | 
T14 | 
28 | 
| auto[1] | 
auto[0] | 
17428 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
81 | 
 | 
T8 | 
56 | 
| auto[1] | 
auto[1] | 
821 | 
1 | 
 | 
 | 
T5 | 
10 | 
 | 
T14 | 
7 | 
 | 
T88 | 
9 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39218 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1075 | 
1 | 
 | 
 | 
T13 | 
6 | 
 | 
T14 | 
42 | 
 | 
T35 | 
8 | 
| auto[1] | 
auto[0] | 
17337 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
46 | 
| auto[1] | 
auto[1] | 
912 | 
1 | 
 | 
 | 
T8 | 
10 | 
 | 
T14 | 
15 | 
 | 
T27 | 
9 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39180 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1113 | 
1 | 
 | 
 | 
T13 | 
9 | 
 | 
T14 | 
32 | 
 | 
T35 | 
8 | 
| auto[1] | 
auto[0] | 
17353 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
49 | 
| auto[1] | 
auto[1] | 
896 | 
1 | 
 | 
 | 
T8 | 
7 | 
 | 
T14 | 
18 | 
 | 
T27 | 
10 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38471 | 
1 | 
 | 
 | 
T2 | 
100 | 
 | 
T3 | 
3 | 
 | 
T9 | 
4 | 
| auto[0] | 
auto[1] | 
1822 | 
1 | 
 | 
 | 
T18 | 
12 | 
 | 
T14 | 
85 | 
 | 
T55 | 
58 | 
| auto[1] | 
auto[0] | 
16859 | 
1 | 
 | 
 | 
T1 | 
5 | 
 | 
T5 | 
91 | 
 | 
T8 | 
56 | 
| auto[1] | 
auto[1] | 
1390 | 
1 | 
 | 
 | 
T26 | 
14 | 
 | 
T14 | 
10 | 
 | 
T27 | 
12 |