Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110340128

1

T1

20650

T2

91953

T3

2079

auto[1]

1496080

1

T3

99

T5

3528

T8

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110313159

1

T1

20650

T2

91953

T3

1980

auto[1]

1523049

1

T3

198

T5

3136

T8

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7783987	1			T1	421		T2	9098		T3	401
auto[IdleSt]	23999658	1			T1	13945		T2	3117		T3	1116
auto[ClkMuxSt]	37996	1			T1	4		T2	100		T3	3
auto[CntIncrSt]	37732	1			T1	4		T2	100		T3	3
auto[CntProgSt]	1454189	1			T1	1384		T2	200		T3	58
auto[TransCheckSt]	29431	1			T1	4		T2	100		T9	4
auto[TokenHashSt]	44427384	1			T1	459		T2	63981		T9	110
auto[FlashRmaSt]	38926	1			T1	28		T9	21		T8	35
auto[TokenCheck0St]	13562	1			T1	4		T9	4		T8	12
auto[TokenCheck1St]	9997	1			T1	4		T9	4		T8	7
auto[TransProgSt]	405202	1			T1	1439		T9	43		T8	65
auto[PostTransSt]	14241928	1			T1	2275		T2	15257		T3	223
auto[ScrapSt]	342176	1			T1	679		T20	33		T14	317
auto[EscalateSt]	7220116	1			T3	374		T5	31652		T8	5615
auto[InvalidSt]	11791641	1			T5	103619		T24	3698		T18	861

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2283	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11791641	1			T5	103619		T24	3698		T18	861
EscalateSt	7220116	1			T3	374		T5	31652		T8	5615
ScrapSt	342176	1			T1	679		T20	33		T14	317
PostTransSt	14241928	1			T1	2275		T2	15257		T3	223
TransProgSt	405202	1			T1	1439		T9	43		T8	65
TokenCheck1St	9997	1			T1	4		T9	4		T8	7
TokenCheck0St	13562	1			T1	4		T9	4		T8	12
FlashRmaSt	38926	1			T1	28		T9	21		T8	35
TokenHashSt	44427384	1			T1	459		T2	63981		T9	110
TransCheckSt	29431	1			T1	4		T2	100		T9	4
CntProgSt	1454189	1			T1	1384		T2	200		T3	58
CntIncrSt	37732	1			T1	4		T2	100		T3	3
ClkMuxSt	37996	1			T1	4		T2	100		T3	3
IdleSt	23999658	1			T1	13945		T2	3117		T3	1116
ResetSt	7783987	1			T1	421		T2	9098		T3	401
arcs[ResetSt=>IdleSt]	58673	1			T1	5		T2	101		T3	4
arcs[IdleSt=>ScrapSt]	300	1			T1	1		T20	1		T14	2
arcs[IdleSt=>ClkMuxSt]	37770	1			T1	4		T2	100		T3	3
arcs[ClkMuxSt=>CntIncrSt]	37732	1			T1	4		T2	100		T3	3
arcs[CntIncrSt=>PostTransSt]	2012	1			T8	7		T13	9		T14	50
arcs[CntIncrSt=>CntProgSt]	35641	1			T1	4		T2	100		T3	3
arcs[CntProgSt=>PostTransSt]	5342	1			T3	3		T8	8		T21	18
arcs[CntProgSt=>TransCheckSt]	29431	1			T1	4		T2	100		T9	4
arcs[TransCheckSt=>PostTransSt]	3911	1			T8	10		T13	6		T14	57
arcs[TransCheckSt=>TokenHashSt]	25367	1			T1	4		T2	100		T9	4
arcs[TokenHashSt=>PostTransSt]	10858	1			T2	100		T10	1		T8	19
arcs[TokenHashSt=>FlashRmaSt]	13599	1			T1	4		T9	4		T8	12
arcs[FlashRmaSt=>TokenCheck0St]	13562	1			T1	4		T9	4		T8	12
arcs[TokenCheck0St=>PostTransSt]	3508	1			T8	5		T21	6		T13	5
arcs[TokenCheck0St=>TokenCheck1St]	9997	1			T1	4		T9	4		T8	7
arcs[TokenCheck1St=>PostTransSt]	697	1			T21	1		T14	1		T15	15
arcs[TransProgSt=>PostTransSt]	8575	1			T1	4		T9	4		T8	7
arcs[IdleSt=>EscalateSt]	148	1			T43	2		T44	8		T45	2
arcs[ClkMuxSt=>EscalateSt]	38	1			T43	2		T44	1		T45	2
arcs[CntIncrSt=>EscalateSt]	79	1			T46	2		T44	3		T47	1
arcs[CntProgSt=>EscalateSt]	868	1			T46	4		T43	8		T44	28
arcs[TransCheckSt=>EscalateSt]	153	1			T46	7		T43	7		T44	1
arcs[TokenHashSt=>EscalateSt]	910	1			T55	2		T46	45		T43	23
arcs[FlashRmaSt=>EscalateSt]	37	1			T48	2		T49	1		T50	1
arcs[TokenCheck0St=>EscalateSt]	57	1			T44	1		T47	3		T54	2
arcs[TokenCheck1St=>EscalateSt]	27	1			T44	3		T48	2		T54	1
arcs[TransProgSt=>EscalateSt]	698	1			T46	7		T43	2		T44	21
arcs[PostTransSt=>EscalateSt]	5742	1			T3	3		T8	8		T21	18
arcs[InvalidSt=>EscalateSt]	15938	1			T5	68		T24	49		T18	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7783816	1			T1	421		T2	9098		T3	401
auto[0]	auto[IdleSt]	23999565	1			T1	13945		T2	3117		T3	1116
auto[0]	auto[ClkMuxSt]	37970	1			T1	4		T2	100		T3	3
auto[0]	auto[CntIncrSt]	37673	1			T1	4		T2	100		T3	3
auto[0]	auto[CntProgSt]	1453616	1			T1	1384		T2	200		T3	58
auto[0]	auto[TransCheckSt]	29331	1			T1	4		T2	100		T9	4
auto[0]	auto[TokenHashSt]	44426799	1			T1	459		T2	63981		T9	110
auto[0]	auto[FlashRmaSt]	38904	1			T1	28		T9	21		T8	35
auto[0]	auto[TokenCheck0St]	13521	1			T1	4		T9	4		T8	12
auto[0]	auto[TokenCheck1St]	9981	1			T1	4		T9	4		T8	7
auto[0]	auto[TransProgSt]	404758	1			T1	1439		T9	43		T8	65
auto[0]	auto[PostTransSt]	14238982	1			T1	2275		T2	15257		T3	222
auto[0]	auto[ScrapSt]	342128	1			T1	679		T20	33		T14	317
auto[0]	auto[EscalateSt]	5737090	1			T3	276		T5	28160		T8	5419
auto[0]	auto[InvalidSt]	11783711	1			T5	103583		T24	3673		T18	857
auto[1]	auto[ResetSt]	171	1			T46	2		T43	2		T44	4
auto[1]	auto[IdleSt]	93	1			T43	2		T44	5		T45	1
auto[1]	auto[ClkMuxSt]	26	1			T43	2		T44	1		T45	2
auto[1]	auto[CntIncrSt]	59	1			T46	2		T44	3		T45	1
auto[1]	auto[CntProgSt]	573	1			T46	4		T43	6		T44	21
auto[1]	auto[TransCheckSt]	100	1			T46	3		T43	4		T205	4
auto[1]	auto[TokenHashSt]	585	1			T55	1		T46	26		T43	18
auto[1]	auto[FlashRmaSt]	22	1			T48	1		T50	1		T206	1
auto[1]	auto[TokenCheck0St]	41	1			T44	1		T47	2		T54	2
auto[1]	auto[TokenCheck1St]	16	1			T44	2		T48	1		T54	1
auto[1]	auto[TransProgSt]	444	1			T46	6		T43	1		T44	11
auto[1]	auto[PostTransSt]	2946	1			T3	1		T8	2		T21	8
auto[1]	auto[ScrapSt]	48	1			T46	1		T43	1		T47	4
auto[1]	auto[EscalateSt]	1483026	1			T3	98		T5	3492		T8	196
auto[1]	auto[InvalidSt]	7930	1			T5	36		T24	25		T18	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7783789	1			T1	421		T2	9098		T3	401
auto[0]	auto[IdleSt]	23999554	1			T1	13945		T2	3117		T3	1116
auto[0]	auto[ClkMuxSt]	37973	1			T1	4		T2	100		T3	3
auto[0]	auto[CntIncrSt]	37679	1			T1	4		T2	100		T3	3
auto[0]	auto[CntProgSt]	1453585	1			T1	1384		T2	200		T3	58
auto[0]	auto[TransCheckSt]	29333	1			T1	4		T2	100		T9	4
auto[0]	auto[TokenHashSt]	44426783	1			T1	459		T2	63981		T9	110
auto[0]	auto[FlashRmaSt]	38903	1			T1	28		T9	21		T8	35
auto[0]	auto[TokenCheck0St]	13528	1			T1	4		T9	4		T8	12
auto[0]	auto[TokenCheck1St]	9977	1			T1	4		T9	4		T8	7
auto[0]	auto[TransProgSt]	404726	1			T1	1439		T9	43		T8	65
auto[0]	auto[PostTransSt]	14239002	1			T1	2275		T2	15257		T3	221
auto[0]	auto[ScrapSt]	342135	1			T1	679		T20	33		T14	317
auto[0]	auto[EscalateSt]	5710276	1			T3	178		T5	28548		T8	5027
auto[0]	auto[InvalidSt]	11783633	1			T5	103587		T24	3674		T18	859
auto[1]	auto[ResetSt]	198	1			T46	3		T43	3		T44	8
auto[1]	auto[IdleSt]	104	1			T43	2		T44	4		T45	2
auto[1]	auto[ClkMuxSt]	23	1			T43	2		T45	1		T207	1
auto[1]	auto[CntIncrSt]	53	1			T46	1		T44	2		T47	1
auto[1]	auto[CntProgSt]	604	1			T46	2		T43	6		T44	24
auto[1]	auto[TransCheckSt]	98	1			T46	5		T43	6		T44	1
auto[1]	auto[TokenHashSt]	601	1			T55	1		T46	31		T43	14
auto[1]	auto[FlashRmaSt]	23	1			T48	2		T49	1		T50	1
auto[1]	auto[TokenCheck0St]	34	1			T44	1		T47	2		T208	2
auto[1]	auto[TokenCheck1St]	20	1			T44	2		T48	2		T54	1
auto[1]	auto[TransProgSt]	476	1			T46	4		T43	1		T44	15
auto[1]	auto[PostTransSt]	2926	1			T3	2		T8	6		T21	10
auto[1]	auto[ScrapSt]	41	1			T46	3		T43	1		T47	2
auto[1]	auto[EscalateSt]	1509840	1			T3	196		T5	3104		T8	588
auto[1]	auto[InvalidSt]	8008	1			T5	32		T24	24		T18	2