Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113014110

1

T1

19048

T2

4098

T3

10200

auto[1]

1469231

1

T2

495

T3

297

T4

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113032754

1

T1

19048

T2

4296

T3

10101

auto[1]

1450587

1

T2

297

T3

396

T4

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7765856	1			T1	102		T2	1052		T3	1550
auto[IdleSt]	22514791	1			T1	18946		T2	1656		T3	1567
auto[ClkMuxSt]	35794	1			T2	8		T3	6		T4	8
auto[CntIncrSt]	35601	1			T2	8		T3	6		T4	8
auto[CntProgSt]	1724538	1			T2	177		T3	924		T4	66
auto[TransCheckSt]	27735	1			T3	6		T9	35		T5	53
auto[TokenHashSt]	48197739	1			T3	281		T9	3107		T5	993
auto[FlashRmaSt]	37748	1			T3	40		T9	77		T5	50
auto[TokenCheck0St]	12868	1			T3	6		T9	26		T5	18
auto[TokenCheck1St]	9566	1			T3	6		T9	20		T5	10
auto[TransProgSt]	482967	1			T3	1165		T9	40		T5	524
auto[PostTransSt]	13396664	1			T2	573		T3	1877		T4	634
auto[ScrapSt]	138343	1			T11	8		T38	4		T16	15
auto[EscalateSt]	7297851	1			T2	1119		T3	1808		T4	1190
auto[InvalidSt]	12803128	1			T3	1254		T9	2200		T12	1006

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2152	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12803128	1			T3	1254		T9	2200		T12	1006
EscalateSt	7297851	1			T2	1119		T3	1808		T4	1190
ScrapSt	138343	1			T11	8		T38	4		T16	15
PostTransSt	13396664	1			T2	573		T3	1877		T4	634
TransProgSt	482967	1			T3	1165		T9	40		T5	524
TokenCheck1St	9566	1			T3	6		T9	20		T5	10
TokenCheck0St	12868	1			T3	6		T9	26		T5	18
FlashRmaSt	37748	1			T3	40		T9	77		T5	50
TokenHashSt	48197739	1			T3	281		T9	3107		T5	993
TransCheckSt	27735	1			T3	6		T9	35		T5	53
CntProgSt	1724538	1			T2	177		T3	924		T4	66
CntIncrSt	35601	1			T2	8		T3	6		T4	8
ClkMuxSt	35794	1			T2	8		T3	6		T4	8
IdleSt	22514791	1			T1	18946		T2	1656		T3	1567
ResetSt	7765856	1			T1	102		T2	1052		T3	1550
arcs[ResetSt=>IdleSt]	55617	1			T1	1		T2	9		T3	16
arcs[IdleSt=>ScrapSt]	286	1			T11	2		T38	1		T16	1
arcs[IdleSt=>ClkMuxSt]	35638	1			T2	8		T3	6		T4	8
arcs[ClkMuxSt=>CntIncrSt]	35601	1			T2	8		T3	6		T4	8
arcs[CntIncrSt=>PostTransSt]	1866	1			T5	3		T14	5		T15	13
arcs[CntIncrSt=>CntProgSt]	33674	1			T2	8		T3	6		T4	8
arcs[CntProgSt=>PostTransSt]	4844	1			T2	8		T4	8		T9	11
arcs[CntProgSt=>TransCheckSt]	27735	1			T3	6		T9	35		T5	53
arcs[TransCheckSt=>PostTransSt]	3733	1			T5	8		T22	45		T14	12
arcs[TransCheckSt=>TokenHashSt]	23895	1			T3	6		T9	35		T5	45
arcs[TokenHashSt=>PostTransSt]	10192	1			T9	9		T5	27		T12	7
arcs[TokenHashSt=>FlashRmaSt]	12919	1			T3	6		T9	26		T5	18
arcs[FlashRmaSt=>TokenCheck0St]	12868	1			T3	6		T9	26		T5	18
arcs[TokenCheck0St=>PostTransSt]	3232	1			T9	6		T5	8		T12	6
arcs[TokenCheck0St=>TokenCheck1St]	9566	1			T3	6		T9	20		T5	10
arcs[TokenCheck1St=>PostTransSt]	618	1			T5	1		T12	1		T13	2
arcs[TransProgSt=>PostTransSt]	8136	1			T3	6		T9	20		T5	9
arcs[IdleSt=>EscalateSt]	157	1			T11	4		T38	2		T46	3
arcs[ClkMuxSt=>EscalateSt]	37	1			T11	1		T38	1		T46	1
arcs[CntIncrSt=>EscalateSt]	61	1			T11	2		T47	2		T38	2
arcs[CntProgSt=>EscalateSt]	1095	1			T11	30		T47	7		T38	24
arcs[TransCheckSt=>EscalateSt]	107	1			T11	1		T47	6		T17	10
arcs[TokenHashSt=>EscalateSt]	784	1			T11	10		T47	35		T38	3
arcs[FlashRmaSt=>EscalateSt]	51	1			T11	1		T47	1		T38	2
arcs[TokenCheck0St=>EscalateSt]	70	1			T11	2		T47	2		T49	2
arcs[TokenCheck1St=>EscalateSt]	23	1			T11	1		T49	1		T50	2
arcs[TransProgSt=>EscalateSt]	789	1			T11	21		T47	6		T38	14
arcs[PostTransSt=>EscalateSt]	5175	1			T2	8		T4	8		T9	11
arcs[InvalidSt=>EscalateSt]	15105	1			T3	7		T9	12		T12	13

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7765686	1			T1	102		T2	1052		T3	1550
auto[0]	auto[IdleSt]	22514685	1			T1	18946		T2	1656		T3	1567
auto[0]	auto[ClkMuxSt]	35776	1			T2	8		T3	6		T4	8
auto[0]	auto[CntIncrSt]	35558	1			T2	8		T3	6		T4	8
auto[0]	auto[CntProgSt]	1723819	1			T2	177		T3	924		T4	66
auto[0]	auto[TransCheckSt]	27664	1			T3	6		T9	35		T5	53
auto[0]	auto[TokenHashSt]	48197193	1			T3	281		T9	3107		T5	993
auto[0]	auto[FlashRmaSt]	37717	1			T3	40		T9	77		T5	50
auto[0]	auto[TokenCheck0St]	12824	1			T3	6		T9	26		T5	18
auto[0]	auto[TokenCheck1St]	9550	1			T3	6		T9	20		T5	10
auto[0]	auto[TransProgSt]	482425	1			T3	1165		T9	40		T5	524
auto[0]	auto[PostTransSt]	13393939	1			T2	568		T3	1877		T4	628
auto[0]	auto[ScrapSt]	138302	1			T11	6		T38	3		T16	15
auto[0]	auto[EscalateSt]	5841241	1			T2	629		T3	1514		T4	602
auto[0]	auto[InvalidSt]	12795579	1			T3	1251		T9	2193		T12	996
auto[1]	auto[ResetSt]	170	1			T11	3		T47	3		T38	3
auto[1]	auto[IdleSt]	106	1			T11	2		T38	1		T46	2
auto[1]	auto[ClkMuxSt]	18	1			T38	1		T17	1		T50	2
auto[1]	auto[CntIncrSt]	43	1			T11	1		T47	2		T38	1
auto[1]	auto[CntProgSt]	719	1			T11	22		T47	4		T38	13
auto[1]	auto[TransCheckSt]	71	1			T11	1		T47	4		T17	6
auto[1]	auto[TokenHashSt]	546	1			T11	7		T47	23		T38	3
auto[1]	auto[FlashRmaSt]	31	1			T11	1		T38	1		T49	2
auto[1]	auto[TokenCheck0St]	44	1			T11	2		T47	1		T49	1
auto[1]	auto[TokenCheck1St]	16	1			T49	1		T50	1		T216	2
auto[1]	auto[TransProgSt]	542	1			T11	15		T47	3		T38	9
auto[1]	auto[PostTransSt]	2725	1			T2	5		T4	6		T9	8
auto[1]	auto[ScrapSt]	41	1			T11	2		T38	1		T17	1
auto[1]	auto[EscalateSt]	1456610	1			T2	490		T3	294		T4	588
auto[1]	auto[InvalidSt]	7549	1			T3	3		T9	7		T12	10

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7765684	1			T1	102		T2	1052		T3	1550
auto[0]	auto[IdleSt]	22514685	1			T1	18946		T2	1656		T3	1567
auto[0]	auto[ClkMuxSt]	35762	1			T2	8		T3	6		T4	8
auto[0]	auto[CntIncrSt]	35565	1			T2	8		T3	6		T4	8
auto[0]	auto[CntProgSt]	1723791	1			T2	177		T3	924		T4	66
auto[0]	auto[TransCheckSt]	27658	1			T3	6		T9	35		T5	53
auto[0]	auto[TokenHashSt]	48197236	1			T3	281		T9	3107		T5	993
auto[0]	auto[FlashRmaSt]	37713	1			T3	40		T9	77		T5	50
auto[0]	auto[TokenCheck0St]	12826	1			T3	6		T9	26		T5	18
auto[0]	auto[TokenCheck1St]	9551	1			T3	6		T9	20		T5	10
auto[0]	auto[TransProgSt]	482448	1			T3	1165		T9	40		T5	524
auto[0]	auto[PostTransSt]	13394098	1			T2	570		T3	1877		T4	632
auto[0]	auto[ScrapSt]	138307	1			T11	7		T38	4		T16	15
auto[0]	auto[EscalateSt]	5859706	1			T2	825		T3	1416		T4	994
auto[0]	auto[InvalidSt]	12795572	1			T3	1250		T9	2195		T12	1003
auto[1]	auto[ResetSt]	172	1			T11	4		T47	4		T38	4
auto[1]	auto[IdleSt]	106	1			T11	3		T38	1		T46	2
auto[1]	auto[ClkMuxSt]	32	1			T11	1		T46	1		T50	2
auto[1]	auto[CntIncrSt]	36	1			T11	2		T47	1		T38	1
auto[1]	auto[CntProgSt]	747	1			T11	19		T47	6		T38	16
auto[1]	auto[TransCheckSt]	77	1			T11	1		T47	6		T17	7
auto[1]	auto[TokenHashSt]	503	1			T11	7		T47	22		T38	1
auto[1]	auto[FlashRmaSt]	35	1			T47	1		T38	2		T49	2
auto[1]	auto[TokenCheck0St]	42	1			T11	1		T47	1		T49	1
auto[1]	auto[TokenCheck1St]	15	1			T11	1		T50	1		T216	1
auto[1]	auto[TransProgSt]	519	1			T11	12		T47	5		T38	9
auto[1]	auto[PostTransSt]	2566	1			T2	3		T4	2		T9	3
auto[1]	auto[ScrapSt]	36	1			T11	1		T46	1		T17	1
auto[1]	auto[EscalateSt]	1438145	1			T2	294		T3	392		T4	196
auto[1]	auto[InvalidSt]	7556	1			T3	4		T9	5		T12	3