Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55163 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
1766 |
1 |
|
|
T14 |
7 |
|
T15 |
41 |
|
T17 |
10 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56210 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
719 |
1 |
|
|
T11 |
16 |
|
T53 |
21 |
|
T34 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54661 |
1 |
|
|
T1 |
1 |
|
T2 |
126 |
|
T3 |
78 |
auto[1] |
2268 |
1 |
|
|
T2 |
7 |
|
T4 |
1 |
|
T5 |
8 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54673 |
1 |
|
|
T1 |
1 |
|
T2 |
120 |
|
T3 |
78 |
auto[1] |
2256 |
1 |
|
|
T2 |
13 |
|
T4 |
1 |
|
T5 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54692 |
1 |
|
|
T1 |
1 |
|
T2 |
123 |
|
T3 |
78 |
auto[1] |
2237 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T5 |
6 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
51677 |
1 |
|
|
T2 |
107 |
|
T3 |
78 |
|
T4 |
10 |
no_err_inj |
5252 |
1 |
|
|
T1 |
1 |
|
T2 |
26 |
|
T4 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55170 |
1 |
|
|
T1 |
1 |
|
T2 |
132 |
|
T3 |
78 |
auto[1] |
1759 |
1 |
|
|
T2 |
1 |
|
T14 |
15 |
|
T15 |
42 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56202 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
727 |
1 |
|
|
T11 |
13 |
|
T53 |
22 |
|
T34 |
17 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39913 |
1 |
|
|
T1 |
1 |
|
T2 |
101 |
|
T3 |
78 |
auto[1] |
17016 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
63 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54661 |
1 |
|
|
T1 |
1 |
|
T2 |
108 |
|
T3 |
78 |
auto[1] |
2268 |
1 |
|
|
T2 |
25 |
|
T5 |
4 |
|
T13 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54637 |
1 |
|
|
T1 |
1 |
|
T2 |
129 |
|
T3 |
78 |
auto[1] |
2292 |
1 |
|
|
T2 |
4 |
|
T5 |
9 |
|
T13 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54657 |
1 |
|
|
T1 |
1 |
|
T2 |
122 |
|
T3 |
78 |
auto[1] |
2272 |
1 |
|
|
T2 |
11 |
|
T4 |
1 |
|
T5 |
4 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55163 |
1 |
|
|
T1 |
1 |
|
T2 |
131 |
|
T3 |
78 |
auto[1] |
1766 |
1 |
|
|
T2 |
2 |
|
T14 |
5 |
|
T15 |
38 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54496 |
1 |
|
|
T1 |
1 |
|
T2 |
126 |
|
T3 |
78 |
auto[1] |
2433 |
1 |
|
|
T2 |
7 |
|
T15 |
3 |
|
T51 |
6 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56180 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
749 |
1 |
|
|
T11 |
16 |
|
T53 |
17 |
|
T34 |
17 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56149 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
780 |
1 |
|
|
T11 |
13 |
|
T53 |
10 |
|
T34 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56174 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
755 |
1 |
|
|
T11 |
11 |
|
T53 |
12 |
|
T34 |
28 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54160 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
2769 |
1 |
|
|
T4 |
15 |
|
T13 |
15 |
|
T23 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53156 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
3773 |
1 |
|
|
T10 |
88 |
|
T19 |
70 |
|
T42 |
97 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54743 |
1 |
|
|
T1 |
1 |
|
T2 |
125 |
|
T3 |
78 |
auto[1] |
2186 |
1 |
|
|
T2 |
8 |
|
T4 |
1 |
|
T5 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54813 |
1 |
|
|
T1 |
1 |
|
T2 |
127 |
|
T3 |
78 |
auto[1] |
2116 |
1 |
|
|
T2 |
6 |
|
T4 |
1 |
|
T5 |
8 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54750 |
1 |
|
|
T1 |
1 |
|
T2 |
121 |
|
T3 |
78 |
auto[1] |
2179 |
1 |
|
|
T2 |
12 |
|
T4 |
2 |
|
T5 |
7 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55150 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
1779 |
1 |
|
|
T14 |
8 |
|
T15 |
35 |
|
T17 |
13 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51448 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
5481 |
1 |
|
|
T22 |
60 |
|
T14 |
3 |
|
T15 |
40 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53116 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T4 |
15 |
auto[1] |
3813 |
1 |
|
|
T3 |
78 |
|
T20 |
99 |
|
T52 |
97 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56929 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55094 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
1835 |
1 |
|
|
T14 |
7 |
|
T15 |
48 |
|
T17 |
14 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55170 |
1 |
|
|
T1 |
1 |
|
T2 |
133 |
|
T3 |
78 |
auto[1] |
1759 |
1 |
|
|
T14 |
8 |
|
T15 |
34 |
|
T17 |
12 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55220 |
1 |
|
|
T1 |
1 |
|
T2 |
132 |
|
T3 |
78 |
auto[1] |
1709 |
1 |
|
|
T2 |
1 |
|
T14 |
10 |
|
T15 |
31 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
50295 |
1 |
|
|
T2 |
107 |
|
T3 |
78 |
|
T10 |
88 |
auto[0] |
no_err_inj |
3865 |
1 |
|
|
T1 |
1 |
|
T2 |
26 |
|
T14 |
18 |
auto[1] |
err_inj |
1382 |
1 |
|
|
T4 |
10 |
|
T13 |
7 |
|
T23 |
5 |
auto[1] |
no_err_inj |
1387 |
1 |
|
|
T4 |
5 |
|
T13 |
8 |
|
T23 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52179 |
1 |
|
|
T1 |
1 |
|
T2 |
127 |
|
T3 |
78 |
auto[0] |
auto[1] |
1981 |
1 |
|
|
T2 |
6 |
|
T5 |
8 |
|
T61 |
7 |
auto[1] |
auto[0] |
2634 |
1 |
|
|
T4 |
14 |
|
T13 |
15 |
|
T23 |
12 |
auto[1] |
auto[1] |
135 |
1 |
|
|
T4 |
1 |
|
T14 |
2 |
|
T15 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52020 |
1 |
|
|
T1 |
1 |
|
T2 |
129 |
|
T3 |
78 |
auto[0] |
auto[1] |
2140 |
1 |
|
|
T2 |
4 |
|
T5 |
9 |
|
T61 |
4 |
auto[1] |
auto[0] |
2617 |
1 |
|
|
T4 |
15 |
|
T13 |
14 |
|
T23 |
11 |
auto[1] |
auto[1] |
152 |
1 |
|
|
T13 |
1 |
|
T23 |
1 |
|
T16 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52155 |
1 |
|
|
T1 |
1 |
|
T2 |
121 |
|
T3 |
78 |
auto[0] |
auto[1] |
2005 |
1 |
|
|
T2 |
12 |
|
T5 |
7 |
|
T61 |
4 |
auto[1] |
auto[0] |
2595 |
1 |
|
|
T4 |
13 |
|
T13 |
15 |
|
T23 |
12 |
auto[1] |
auto[1] |
174 |
1 |
|
|
T4 |
2 |
|
T15 |
2 |
|
T24 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52065 |
1 |
|
|
T1 |
1 |
|
T2 |
120 |
|
T3 |
78 |
auto[0] |
auto[1] |
2095 |
1 |
|
|
T2 |
13 |
|
T5 |
8 |
|
T61 |
8 |
auto[1] |
auto[0] |
2608 |
1 |
|
|
T4 |
14 |
|
T13 |
14 |
|
T23 |
11 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T23 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52079 |
1 |
|
|
T1 |
1 |
|
T2 |
123 |
|
T3 |
78 |
auto[0] |
auto[1] |
2081 |
1 |
|
|
T2 |
10 |
|
T5 |
6 |
|
T61 |
6 |
auto[1] |
auto[0] |
2613 |
1 |
|
|
T4 |
12 |
|
T13 |
14 |
|
T23 |
12 |
auto[1] |
auto[1] |
156 |
1 |
|
|
T4 |
3 |
|
T13 |
1 |
|
T16 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52054 |
1 |
|
|
T1 |
1 |
|
T2 |
126 |
|
T3 |
78 |
auto[0] |
auto[1] |
2106 |
1 |
|
|
T2 |
7 |
|
T5 |
8 |
|
T61 |
6 |
auto[1] |
auto[0] |
2607 |
1 |
|
|
T4 |
14 |
|
T13 |
14 |
|
T23 |
12 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38875 |
1 |
|
|
T1 |
1 |
|
T2 |
101 |
|
T3 |
78 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T15 |
29 |
|
T17 |
10 |
|
T18 |
14 |
auto[1] |
auto[0] |
16288 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
63 |
auto[1] |
auto[1] |
728 |
1 |
|
|
T14 |
7 |
|
T15 |
12 |
|
T82 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38860 |
1 |
|
|
T1 |
1 |
|
T2 |
100 |
|
T3 |
78 |
auto[0] |
auto[1] |
1053 |
1 |
|
|
T2 |
1 |
|
T15 |
33 |
|
T17 |
10 |
auto[1] |
auto[0] |
16310 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
63 |
auto[1] |
auto[1] |
706 |
1 |
|
|
T14 |
15 |
|
T15 |
9 |
|
T82 |
17 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38527 |
1 |
|
|
T1 |
1 |
|
T2 |
100 |
|
T3 |
78 |
auto[0] |
auto[1] |
1386 |
1 |
|
|
T2 |
1 |
|
T15 |
3 |
|
T51 |
6 |
auto[1] |
auto[0] |
15969 |
1 |
|
|
T2 |
26 |
|
T4 |
15 |
|
T5 |
63 |
auto[1] |
auto[1] |
1047 |
1 |
|
|
T2 |
6 |
|
T24 |
30 |
|
T199 |
3 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38877 |
1 |
|
|
T1 |
1 |
|
T2 |
99 |
|
T3 |
78 |
auto[0] |
auto[1] |
1036 |
1 |
|
|
T2 |
2 |
|
T15 |
24 |
|
T17 |
14 |
auto[1] |
auto[0] |
16286 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
63 |
auto[1] |
auto[1] |
730 |
1 |
|
|
T14 |
5 |
|
T15 |
14 |
|
T82 |
14 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35143 |
1 |
|
|
T1 |
1 |
|
T2 |
101 |
|
T3 |
78 |
auto[0] |
auto[1] |
4770 |
1 |
|
|
T22 |
60 |
|
T15 |
35 |
|
T17 |
8 |
auto[1] |
auto[0] |
16305 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
63 |
auto[1] |
auto[1] |
711 |
1 |
|
|
T14 |
3 |
|
T15 |
5 |
|
T82 |
14 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38625 |
1 |
|
|
T1 |
1 |
|
T2 |
95 |
|
T3 |
78 |
auto[0] |
auto[1] |
1288 |
1 |
|
|
T2 |
6 |
|
T61 |
7 |
|
T14 |
17 |
auto[1] |
auto[0] |
16188 |
1 |
|
|
T2 |
32 |
|
T4 |
14 |
|
T5 |
55 |
auto[1] |
auto[1] |
828 |
1 |
|
|
T4 |
1 |
|
T5 |
8 |
|
T15 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38588 |
1 |
|
|
T1 |
1 |
|
T2 |
93 |
|
T3 |
78 |
auto[0] |
auto[1] |
1325 |
1 |
|
|
T2 |
8 |
|
T13 |
1 |
|
T16 |
2 |
auto[1] |
auto[0] |
16155 |
1 |
|
|
T2 |
32 |
|
T4 |
14 |
|
T5 |
54 |
auto[1] |
auto[1] |
861 |
1 |
|
|
T4 |
1 |
|
T5 |
9 |
|
T23 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38505 |
1 |
|
|
T1 |
1 |
|
T2 |
97 |
|
T3 |
78 |
auto[0] |
auto[1] |
1408 |
1 |
|
|
T2 |
4 |
|
T13 |
1 |
|
T16 |
1 |
auto[1] |
auto[0] |
16132 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
54 |
auto[1] |
auto[1] |
884 |
1 |
|
|
T5 |
9 |
|
T23 |
1 |
|
T90 |
13 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38542 |
1 |
|
|
T1 |
1 |
|
T2 |
76 |
|
T3 |
78 |
auto[0] |
auto[1] |
1371 |
1 |
|
|
T2 |
25 |
|
T13 |
1 |
|
T61 |
9 |
auto[1] |
auto[0] |
16119 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
59 |
auto[1] |
auto[1] |
897 |
1 |
|
|
T5 |
4 |
|
T23 |
2 |
|
T15 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38530 |
1 |
|
|
T1 |
1 |
|
T2 |
88 |
|
T3 |
78 |
auto[0] |
auto[1] |
1383 |
1 |
|
|
T2 |
13 |
|
T13 |
1 |
|
T16 |
2 |
auto[1] |
auto[0] |
16143 |
1 |
|
|
T2 |
32 |
|
T4 |
14 |
|
T5 |
55 |
auto[1] |
auto[1] |
873 |
1 |
|
|
T4 |
1 |
|
T5 |
8 |
|
T23 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38574 |
1 |
|
|
T1 |
1 |
|
T2 |
94 |
|
T3 |
78 |
auto[0] |
auto[1] |
1339 |
1 |
|
|
T2 |
7 |
|
T13 |
1 |
|
T61 |
6 |
auto[1] |
auto[0] |
16087 |
1 |
|
|
T2 |
32 |
|
T4 |
14 |
|
T5 |
55 |
auto[1] |
auto[1] |
929 |
1 |
|
|
T4 |
1 |
|
T5 |
8 |
|
T15 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38887 |
1 |
|
|
T1 |
1 |
|
T2 |
100 |
|
T3 |
78 |
auto[0] |
auto[1] |
1026 |
1 |
|
|
T2 |
1 |
|
T15 |
25 |
|
T17 |
14 |
auto[1] |
auto[0] |
16333 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
63 |
auto[1] |
auto[1] |
683 |
1 |
|
|
T14 |
10 |
|
T15 |
6 |
|
T82 |
12 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38874 |
1 |
|
|
T1 |
1 |
|
T2 |
101 |
|
T3 |
78 |
auto[0] |
auto[1] |
1039 |
1 |
|
|
T15 |
23 |
|
T17 |
12 |
|
T18 |
18 |
auto[1] |
auto[0] |
16296 |
1 |
|
|
T2 |
32 |
|
T4 |
15 |
|
T5 |
63 |
auto[1] |
auto[1] |
720 |
1 |
|
|
T14 |
8 |
|
T15 |
11 |
|
T82 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38375 |
1 |
|
|
T1 |
1 |
|
T2 |
101 |
|
T3 |
78 |
auto[0] |
auto[1] |
1538 |
1 |
|
|
T13 |
15 |
|
T16 |
14 |
|
T14 |
15 |
auto[1] |
auto[0] |
15785 |
1 |
|
|
T2 |
32 |
|
T5 |
63 |
|
T14 |
71 |
auto[1] |
auto[1] |
1231 |
1 |
|
|
T4 |
15 |
|
T23 |
12 |
|
T15 |
27 |