Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109748647

1

T1

1196

T2

413032

T3

41888

auto[1]

1503150

1

T2

4234

T4

588

T10

12448

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109719772

1

T1

1196

T2

413429

T3

41888

auto[1]

1532025

1

T2

3837

T4

98

T10

12684

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7705089	1			T1	108		T2	13866		T3	6999
auto[IdleSt]	21665189	1			T1	296		T2	52017		T3	6959
auto[ClkMuxSt]	35679	1			T1	1		T2	38		T3	78
auto[CntIncrSt]	35426	1			T1	1		T2	38		T3	78
auto[CntProgSt]	1662732	1			T1	15		T2	1183		T3	156
auto[TransCheckSt]	27706	1			T1	1		T2	29		T3	78
auto[TokenHashSt]	47583527	1			T1	20		T2	308727		T3	15032
auto[FlashRmaSt]	35864	1			T1	1		T2	88		T3	82
auto[TokenCheck0St]	12943	1			T1	1		T2	28		T3	31
auto[TokenCheck1St]	9658	1			T1	1		T2	28		T3	11
auto[TransProgSt]	425344	1			T1	7		T2	703		T4	10
auto[PostTransSt]	12588634	1			T1	744		T2	10620		T3	12384
auto[ScrapSt]	137237	1			T2	3315		T10	4		T19	4
auto[EscalateSt]	7246752	1			T2	13235		T4	7554		T10	17936
auto[InvalidSt]	12077644	1			T2	13347		T4	10379		T5	83688

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2373	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12077644	1			T2	13347		T4	10379		T5	83688
EscalateSt	7246752	1			T2	13235		T4	7554		T10	17936
ScrapSt	137237	1			T2	3315		T10	4		T19	4
PostTransSt	12588634	1			T1	744		T2	10620		T3	12384
TransProgSt	425344	1			T1	7		T2	703		T4	10
TokenCheck1St	9658	1			T1	1		T2	28		T3	11
TokenCheck0St	12943	1			T1	1		T2	28		T3	31
FlashRmaSt	35864	1			T1	1		T2	88		T3	82
TokenHashSt	47583527	1			T1	20		T2	308727		T3	15032
TransCheckSt	27706	1			T1	1		T2	29		T3	78
CntProgSt	1662732	1			T1	15		T2	1183		T3	156
CntIncrSt	35426	1			T1	1		T2	38		T3	78
ClkMuxSt	35679	1			T1	1		T2	38		T3	78
IdleSt	21665189	1			T1	296		T2	52017		T3	6959
ResetSt	7705089	1			T1	108		T2	13866		T3	6999
arcs[ResetSt=>IdleSt]	56942	1			T1	1		T2	134		T3	79
arcs[IdleSt=>ScrapSt]	344	1			T2	2		T10	1		T19	1
arcs[IdleSt=>ClkMuxSt]	35461	1			T1	1		T2	38		T3	78
arcs[ClkMuxSt=>CntIncrSt]	35426	1			T1	1		T2	38		T3	78
arcs[CntIncrSt=>PostTransSt]	1762	1			T14	8		T15	34		T17	12
arcs[CntIncrSt=>CntProgSt]	33600	1			T1	1		T2	38		T3	78
arcs[CntProgSt=>PostTransSt]	4873	1			T2	9		T11	16		T14	7
arcs[CntProgSt=>TransCheckSt]	27706	1			T1	1		T2	29		T3	78
arcs[TransCheckSt=>PostTransSt]	3623	1			T2	1		T3	32		T20	57
arcs[TransCheckSt=>TokenHashSt]	23948	1			T1	1		T2	28		T3	46
arcs[TokenHashSt=>PostTransSt]	10113	1			T3	15		T11	10		T12	1
arcs[TokenHashSt=>FlashRmaSt]	12991	1			T1	1		T2	28		T3	31
arcs[FlashRmaSt=>TokenCheck0St]	12943	1			T1	1		T2	28		T3	31
arcs[TokenCheck0St=>PostTransSt]	3226	1			T3	20		T11	13		T20	22
arcs[TokenCheck0St=>TokenCheck1St]	9658	1			T1	1		T2	28		T3	11
arcs[TokenCheck1St=>PostTransSt]	660	1			T2	1		T3	11		T20	5
arcs[TransProgSt=>PostTransSt]	8236	1			T1	1		T2	27		T4	5
arcs[IdleSt=>EscalateSt]	199	1			T10	2		T19	9		T41	2
arcs[ClkMuxSt=>EscalateSt]	35	1			T10	1		T19	2		T41	1
arcs[CntIncrSt=>EscalateSt]	64	1			T10	4		T19	1		T41	3
arcs[CntProgSt=>EscalateSt]	1021	1			T10	8		T19	30		T42	47
arcs[TransCheckSt=>EscalateSt]	135	1			T10	5		T42	1		T46	2
arcs[TokenHashSt=>EscalateSt]	844	1			T10	25		T19	8		T42	12
arcs[FlashRmaSt=>EscalateSt]	48	1			T10	1		T42	3		T41	1
arcs[TokenCheck0St=>EscalateSt]	59	1			T10	2		T19	1		T42	1
arcs[TokenCheck1St=>EscalateSt]	23	1			T41	2		T46	1		T47	1
arcs[TransProgSt=>EscalateSt]	739	1			T10	8		T19	13		T42	21
arcs[PostTransSt=>EscalateSt]	5219	1			T2	9		T10	24		T11	16
arcs[InvalidSt=>EscalateSt]	16414	1			T2	73		T4	7		T5	52

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7704930	1			T1	108		T2	13866		T3	6999
auto[0]	auto[IdleSt]	21665049	1			T1	296		T2	52017		T3	6959
auto[0]	auto[ClkMuxSt]	35658	1			T1	1		T2	38		T3	78
auto[0]	auto[CntIncrSt]	35388	1			T1	1		T2	38		T3	78
auto[0]	auto[CntProgSt]	1662035	1			T1	15		T2	1183		T3	156
auto[0]	auto[TransCheckSt]	27616	1			T1	1		T2	29		T3	78
auto[0]	auto[TokenHashSt]	47582961	1			T1	20		T2	308727		T3	15032
auto[0]	auto[FlashRmaSt]	35835	1			T1	1		T2	88		T3	82
auto[0]	auto[TokenCheck0St]	12899	1			T1	1		T2	28		T3	31
auto[0]	auto[TokenCheck1St]	9642	1			T1	1		T2	28		T3	11
auto[0]	auto[TransProgSt]	424852	1			T1	7		T2	703		T4	10
auto[0]	auto[PostTransSt]	12586012	1			T1	744		T2	10617		T3	12384
auto[0]	auto[ScrapSt]	137182	1			T2	3315		T10	3		T19	3
auto[0]	auto[EscalateSt]	5756617	1			T2	9044		T4	6972		T10	5550
auto[0]	auto[InvalidSt]	12069598	1			T2	13307		T4	10373		T5	83670
auto[1]	auto[ResetSt]	159	1			T10	4		T19	1		T42	3
auto[1]	auto[IdleSt]	140	1			T10	1		T19	5		T41	1
auto[1]	auto[ClkMuxSt]	21	1			T10	1		T19	1		T197	2
auto[1]	auto[CntIncrSt]	38	1			T10	2		T19	1		T41	1
auto[1]	auto[CntProgSt]	697	1			T10	6		T19	21		T42	28
auto[1]	auto[TransCheckSt]	90	1			T10	4		T42	1		T46	1
auto[1]	auto[TokenHashSt]	566	1			T10	18		T19	3		T42	6
auto[1]	auto[FlashRmaSt]	29	1			T10	1		T42	3		T46	1
auto[1]	auto[TokenCheck0St]	44	1			T10	1		T42	1		T41	2
auto[1]	auto[TokenCheck1St]	16	1			T41	2		T46	1		T197	1
auto[1]	auto[TransProgSt]	492	1			T10	7		T19	8		T42	15
auto[1]	auto[PostTransSt]	2622	1			T2	3		T10	16		T11	8
auto[1]	auto[ScrapSt]	55	1			T10	1		T19	1		T42	1
auto[1]	auto[EscalateSt]	1490135	1			T2	4191		T4	582		T10	12386
auto[1]	auto[InvalidSt]	8046	1			T2	40		T4	6		T5	18

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7704935	1			T1	108		T2	13866		T3	6999
auto[0]	auto[IdleSt]	21665058	1			T1	296		T2	52017		T3	6959
auto[0]	auto[ClkMuxSt]	35654	1			T1	1		T2	38		T3	78
auto[0]	auto[CntIncrSt]	35382	1			T1	1		T2	38		T3	78
auto[0]	auto[CntProgSt]	1662066	1			T1	15		T2	1183		T3	156
auto[0]	auto[TransCheckSt]	27615	1			T1	1		T2	29		T3	78
auto[0]	auto[TokenHashSt]	47582996	1			T1	20		T2	308727		T3	15032
auto[0]	auto[FlashRmaSt]	35826	1			T1	1		T2	88		T3	82
auto[0]	auto[TokenCheck0St]	12911	1			T1	1		T2	28		T3	31
auto[0]	auto[TokenCheck1St]	9641	1			T1	1		T2	28		T3	11
auto[0]	auto[TransProgSt]	424845	1			T1	7		T2	703		T4	10
auto[0]	auto[PostTransSt]	12585938	1			T1	744		T2	10614		T3	12384
auto[0]	auto[ScrapSt]	137184	1			T2	3315		T10	4		T19	3
auto[0]	auto[EscalateSt]	5728072	1			T2	9437		T4	7457		T10	5313
auto[0]	auto[InvalidSt]	12069276	1			T2	13314		T4	10378		T5	83654
auto[1]	auto[ResetSt]	154	1			T10	5		T19	2		T42	4
auto[1]	auto[IdleSt]	131	1			T10	2		T19	8		T41	1
auto[1]	auto[ClkMuxSt]	25	1			T10	1		T19	2		T41	1
auto[1]	auto[CntIncrSt]	44	1			T10	3		T41	2		T46	1
auto[1]	auto[CntProgSt]	666	1			T10	5		T19	19		T42	32
auto[1]	auto[TransCheckSt]	91	1			T10	2		T42	1		T46	2
auto[1]	auto[TokenHashSt]	531	1			T10	15		T19	5		T42	10
auto[1]	auto[FlashRmaSt]	38	1			T10	1		T42	1		T41	1
auto[1]	auto[TokenCheck0St]	32	1			T10	2		T19	1		T41	2
auto[1]	auto[TokenCheck1St]	17	1			T41	2		T47	1		T197	1
auto[1]	auto[TransProgSt]	499	1			T10	6		T19	7		T42	12
auto[1]	auto[PostTransSt]	2696	1			T2	6		T10	19		T11	8
auto[1]	auto[ScrapSt]	53	1			T19	1		T42	3		T198	2
auto[1]	auto[EscalateSt]	1518680	1			T2	3798		T4	97		T10	12623
auto[1]	auto[InvalidSt]	8368	1			T2	33		T4	1		T5	34