Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96683721

1

T1

5814

T2

26772

T3

3149

auto[1]

1375749

1

T1

594

T3

495

T11

2178

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96681974

1

T1

5715

T2

26772

T3

3248

auto[1]

1377496

1

T1

693

T3

396

T11

2277

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7110624	1			T1	1248		T2	9074		T3	810
auto[IdleSt]	22304716	1			T1	1871		T2	2993		T3	969
auto[ClkMuxSt]	35115	1			T1	13		T2	83		T3	9
auto[CntIncrSt]	34908	1			T1	13		T2	83		T3	9
auto[CntProgSt]	1511581	1			T1	600		T2	166		T3	215
auto[TransCheckSt]	27426	1			T2	83		T11	46		T14	59
auto[TokenHashSt]	36534544	1			T2	1717		T11	4306		T14	2177
auto[FlashRmaSt]	34005	1			T11	46		T14	75		T4	46
auto[TokenCheck0St]	12252	1			T11	34		T14	24		T4	12
auto[TokenCheck1St]	8938	1			T11	19		T14	11		T4	9
auto[TransProgSt]	377119	1			T11	585		T4	1676		T5	40
auto[PostTransSt]	12963166	1			T1	917		T2	12573		T3	516
auto[ScrapSt]	96813	1			T15	35		T18	4		T16	4
auto[EscalateSt]	6420261	1			T1	1746		T3	1116		T11	6385
auto[InvalidSt]	10586171	1			T11	3404		T12	4071		T5	6717

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1831	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10586171	1			T11	3404		T12	4071		T5	6717
EscalateSt	6420261	1			T1	1746		T3	1116		T11	6385
ScrapSt	96813	1			T15	35		T18	4		T16	4
PostTransSt	12963166	1			T1	917		T2	12573		T3	516
TransProgSt	377119	1			T11	585		T4	1676		T5	40
TokenCheck1St	8938	1			T11	19		T14	11		T4	9
TokenCheck0St	12252	1			T11	34		T14	24		T4	12
FlashRmaSt	34005	1			T11	46		T14	75		T4	46
TokenHashSt	36534544	1			T2	1717		T11	4306		T14	2177
TransCheckSt	27426	1			T2	83		T11	46		T14	59
CntProgSt	1511581	1			T1	600		T2	166		T3	215
CntIncrSt	34908	1			T1	13		T2	83		T3	9
ClkMuxSt	35115	1			T1	13		T2	83		T3	9
IdleSt	22304716	1			T1	1871		T2	2993		T3	969
ResetSt	7110624	1			T1	1248		T2	9074		T3	810
arcs[ResetSt=>IdleSt]	52585	1			T1	14		T2	84		T3	10
arcs[IdleSt=>ScrapSt]	255	1			T15	1		T18	1		T16	1
arcs[IdleSt=>ClkMuxSt]	34945	1			T1	13		T2	83		T3	9
arcs[ClkMuxSt=>CntIncrSt]	34908	1			T1	13		T2	83		T3	9
arcs[CntIncrSt=>PostTransSt]	1701	1			T4	8		T5	11		T6	12
arcs[CntIncrSt=>CntProgSt]	33138	1			T1	13		T2	83		T3	9
arcs[CntProgSt=>PostTransSt]	4761	1			T1	13		T3	9		T11	28
arcs[CntProgSt=>TransCheckSt]	27426	1			T2	83		T11	46		T14	59
arcs[TransCheckSt=>PostTransSt]	3739	1			T14	24		T4	8		T5	12
arcs[TransCheckSt=>TokenHashSt]	23546	1			T2	83		T11	46		T14	35
arcs[TokenHashSt=>PostTransSt]	10312	1			T2	83		T11	12		T14	11
arcs[TokenHashSt=>FlashRmaSt]	12286	1			T11	34		T14	24		T4	12
arcs[FlashRmaSt=>TokenCheck0St]	12252	1			T11	34		T14	24		T4	12
arcs[TokenCheck0St=>PostTransSt]	3244	1			T11	15		T14	13		T4	3
arcs[TokenCheck0St=>TokenCheck1St]	8938	1			T11	19		T14	11		T4	9
arcs[TokenCheck1St=>PostTransSt]	720	1			T14	11		T4	2		T5	2
arcs[TransProgSt=>PostTransSt]	7411	1			T11	19		T4	7		T5	8
arcs[IdleSt=>EscalateSt]	154	1			T18	6		T56	5		T60	2
arcs[ClkMuxSt=>EscalateSt]	37	1			T56	5		T57	4		T58	1
arcs[CntIncrSt=>EscalateSt]	69	1			T18	1		T16	1		T56	1
arcs[CntProgSt=>EscalateSt]	951	1			T18	24		T28	4		T16	33
arcs[TransCheckSt=>EscalateSt]	141	1			T28	5		T16	1		T57	8
arcs[TokenHashSt=>EscalateSt]	948	1			T18	4		T28	30		T16	12
arcs[FlashRmaSt=>EscalateSt]	34	1			T16	1		T56	2		T59	2
arcs[TokenCheck0St=>EscalateSt]	70	1			T28	1		T16	3		T56	1
arcs[TokenCheck1St=>EscalateSt]	37	1			T18	1		T16	1		T56	1
arcs[TransProgSt=>EscalateSt]	770	1			T18	22		T28	5		T16	28
arcs[PostTransSt=>EscalateSt]	5152	1			T1	13		T3	9		T11	28
arcs[InvalidSt=>EscalateSt]	13215	1			T11	17		T12	55		T5	48

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7110435	1			T1	1248		T2	9074		T3	810
auto[0]	auto[IdleSt]	22304616	1			T1	1871		T2	2993		T3	969
auto[0]	auto[ClkMuxSt]	35089	1			T1	13		T2	83		T3	9
auto[0]	auto[CntIncrSt]	34859	1			T1	13		T2	83		T3	9
auto[0]	auto[CntProgSt]	1510943	1			T1	600		T2	166		T3	215
auto[0]	auto[TransCheckSt]	27329	1			T2	83		T11	46		T14	59
auto[0]	auto[TokenHashSt]	36533914	1			T2	1717		T11	4306		T14	2177
auto[0]	auto[FlashRmaSt]	33982	1			T11	46		T14	75		T4	46
auto[0]	auto[TokenCheck0St]	12212	1			T11	34		T14	24		T4	12
auto[0]	auto[TokenCheck1St]	8910	1			T11	19		T14	11		T4	9
auto[0]	auto[TransProgSt]	376594	1			T11	585		T4	1676		T5	40
auto[0]	auto[PostTransSt]	12960547	1			T1	911		T2	12573		T3	511
auto[0]	auto[ScrapSt]	96772	1			T15	35		T18	3		T16	3
auto[0]	auto[EscalateSt]	5056110	1			T1	1158		T3	626		T11	4229
auto[0]	auto[InvalidSt]	10579578	1			T11	3393		T12	4050		T5	6692
auto[1]	auto[ResetSt]	189	1			T18	3		T28	3		T16	3
auto[1]	auto[IdleSt]	100	1			T18	4		T56	5		T60	2
auto[1]	auto[ClkMuxSt]	26	1			T56	4		T57	2		T58	1
auto[1]	auto[CntIncrSt]	49	1			T18	1		T16	1		T56	1
auto[1]	auto[CntProgSt]	638	1			T18	19		T28	2		T16	26
auto[1]	auto[TransCheckSt]	97	1			T28	4		T16	1		T57	8
auto[1]	auto[TokenHashSt]	630	1			T18	2		T28	20		T16	8
auto[1]	auto[FlashRmaSt]	23	1			T16	1		T56	1		T59	2
auto[1]	auto[TokenCheck0St]	40	1			T28	1		T16	3		T56	1
auto[1]	auto[TokenCheck1St]	28	1			T18	1		T16	1		T56	1
auto[1]	auto[TransProgSt]	525	1			T18	15		T28	1		T16	22
auto[1]	auto[PostTransSt]	2619	1			T1	6		T3	5		T11	11
auto[1]	auto[ScrapSt]	41	1			T18	1		T16	1		T56	1
auto[1]	auto[EscalateSt]	1364151	1			T1	588		T3	490		T11	2156
auto[1]	auto[InvalidSt]	6593	1			T11	11		T12	21		T5	25

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7110426	1			T1	1248		T2	9074		T3	810
auto[0]	auto[IdleSt]	22304608	1			T1	1871		T2	2993		T3	969
auto[0]	auto[ClkMuxSt]	35092	1			T1	13		T2	83		T3	9
auto[0]	auto[CntIncrSt]	34871	1			T1	13		T2	83		T3	9
auto[0]	auto[CntProgSt]	1510955	1			T1	600		T2	166		T3	215
auto[0]	auto[TransCheckSt]	27335	1			T2	83		T11	46		T14	59
auto[0]	auto[TokenHashSt]	36533908	1			T2	1717		T11	4306		T14	2177
auto[0]	auto[FlashRmaSt]	33983	1			T11	46		T14	75		T4	46
auto[0]	auto[TokenCheck0St]	12205	1			T11	34		T14	24		T4	12
auto[0]	auto[TokenCheck1St]	8913	1			T11	19		T14	11		T4	9
auto[0]	auto[TransProgSt]	376620	1			T11	585		T4	1676		T5	40
auto[0]	auto[PostTransSt]	12960514	1			T1	910		T2	12573		T3	512
auto[0]	auto[ScrapSt]	96777	1			T15	35		T18	3		T16	3
auto[0]	auto[EscalateSt]	5054387	1			T1	1060		T3	724		T11	4131
auto[0]	auto[InvalidSt]	10579549	1			T11	3398		T12	4037		T5	6694
auto[1]	auto[ResetSt]	198	1			T18	2		T28	3		T16	5
auto[1]	auto[IdleSt]	108	1			T18	5		T56	2		T60	2
auto[1]	auto[ClkMuxSt]	23	1			T56	3		T57	4		T153	1
auto[1]	auto[CntIncrSt]	37	1			T59	2		T57	2		T166	3
auto[1]	auto[CntProgSt]	626	1			T18	15		T28	4		T16	21
auto[1]	auto[TransCheckSt]	91	1			T28	3		T57	4		T209	3
auto[1]	auto[TokenHashSt]	636	1			T18	3		T28	20		T16	8
auto[1]	auto[FlashRmaSt]	22	1			T16	1		T56	2		T59	2
auto[1]	auto[TokenCheck0St]	47	1			T16	1		T56	1		T59	3
auto[1]	auto[TokenCheck1St]	25	1			T18	1		T60	1		T57	1
auto[1]	auto[TransProgSt]	499	1			T18	19		T28	4		T16	16
auto[1]	auto[PostTransSt]	2652	1			T1	7		T3	4		T11	17
auto[1]	auto[ScrapSt]	36	1			T18	1		T16	1		T56	1
auto[1]	auto[EscalateSt]	1365874	1			T1	686		T3	392		T11	2254
auto[1]	auto[InvalidSt]	6622	1			T11	6		T12	34		T5	23