Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107379672

1

T1

18913

T2

38370

T3

14182

auto[1]

1371598

1

T4

196

T9

1386

T10

3960

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107361575

1

T1

18913

T2

38370

T3

14182

auto[1]

1389695

1

T4

196

T9

1188

T10

4158

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7437648	1			T1	1026		T2	6412		T3	111
auto[IdleSt]	24121582	1			T1	14560		T2	6015		T3	14071
auto[ClkMuxSt]	36843	1			T1	10		T2	73		T4	4
auto[CntIncrSt]	36514	1			T1	10		T2	73		T4	4
auto[CntProgSt]	1506387	1			T1	20		T2	146		T4	100
auto[TransCheckSt]	28724	1			T1	10		T2	73		T9	49
auto[TokenHashSt]	42063657	1			T1	190		T2	14020		T9	536
auto[FlashRmaSt]	36354	1			T1	55		T2	51		T9	146
auto[TokenCheck0St]	13099	1			T1	10		T2	29		T9	42
auto[TokenCheck1St]	9607	1			T1	10		T2	11		T9	28
auto[TransProgSt]	395348	1			T1	20		T9	951		T11	812
auto[PostTransSt]	14615270	1			T1	2612		T2	11467		T4	1930
auto[ScrapSt]	171218	1			T1	380		T33	157		T22	4
auto[EscalateSt]	6857505	1			T4	1685		T9	3280		T10	11824
auto[InvalidSt]	11419532	1			T9	855		T10	14981		T12	90432

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1982	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11419532	1			T9	855		T10	14981		T12	90432
EscalateSt	6857505	1			T4	1685		T9	3280		T10	11824
ScrapSt	171218	1			T1	380		T33	157		T22	4
PostTransSt	14615270	1			T1	2612		T2	11467		T4	1930
TransProgSt	395348	1			T1	20		T9	951		T11	812
TokenCheck1St	9607	1			T1	10		T2	11		T9	28
TokenCheck0St	13099	1			T1	10		T2	29		T9	42
FlashRmaSt	36354	1			T1	55		T2	51		T9	146
TokenHashSt	42063657	1			T1	190		T2	14020		T9	536
TransCheckSt	28724	1			T1	10		T2	73		T9	49
CntProgSt	1506387	1			T1	20		T2	146		T4	100
CntIncrSt	36514	1			T1	10		T2	73		T4	4
ClkMuxSt	36843	1			T1	10		T2	73		T4	4
IdleSt	24121582	1			T1	14560		T2	6015		T3	14071
ResetSt	7437648	1			T1	1026		T2	6412		T3	111
arcs[ResetSt=>IdleSt]	55323	1			T1	11		T2	74		T3	1
arcs[IdleSt=>ScrapSt]	302	1			T1	1		T33	1		T22	1
arcs[IdleSt=>ClkMuxSt]	36542	1			T1	10		T2	73		T4	4
arcs[ClkMuxSt=>CntIncrSt]	36514	1			T1	10		T2	73		T4	4
arcs[CntIncrSt=>PostTransSt]	2024	1			T15	8		T16	20		T17	34
arcs[CntIncrSt=>CntProgSt]	34431	1			T1	10		T2	73		T4	4
arcs[CntProgSt=>PostTransSt]	4776	1			T4	4		T9	15		T21	20
arcs[CntProgSt=>TransCheckSt]	28724	1			T1	10		T2	73		T9	49
arcs[TransCheckSt=>PostTransSt]	3938	1			T2	36		T13	44		T19	37
arcs[TransCheckSt=>TokenHashSt]	24679	1			T1	10		T2	37		T9	49
arcs[TokenHashSt=>PostTransSt]	10617	1			T2	8		T9	7		T13	7
arcs[TokenHashSt=>FlashRmaSt]	13140	1			T1	10		T2	29		T9	42
arcs[FlashRmaSt=>TokenCheck0St]	13099	1			T1	10		T2	29		T9	42
arcs[TokenCheck0St=>PostTransSt]	3431	1			T2	18		T9	14		T13	16
arcs[TokenCheck0St=>TokenCheck1St]	9607	1			T1	10		T2	11		T9	28
arcs[TokenCheck1St=>PostTransSt]	660	1			T2	11		T9	1		T13	9
arcs[TransProgSt=>PostTransSt]	8213	1			T1	10		T9	27		T11	11
arcs[IdleSt=>EscalateSt]	152	1			T22	6		T42	3		T43	10
arcs[ClkMuxSt=>EscalateSt]	28	1			T42	4		T43	3		T44	3
arcs[CntIncrSt=>EscalateSt]	59	1			T42	2		T43	2		T45	1
arcs[CntProgSt=>EscalateSt]	931	1			T22	26		T42	2		T43	36
arcs[TransCheckSt=>EscalateSt]	107	1			T22	1		T42	6		T45	6
arcs[TokenHashSt=>EscalateSt]	922	1			T22	12		T42	31		T17	2
arcs[FlashRmaSt=>EscalateSt]	41	1			T42	1		T43	1		T45	1
arcs[TokenCheck0St=>EscalateSt]	61	1			T42	1		T43	1		T45	3
arcs[TokenCheck1St=>EscalateSt]	28	1			T43	3		T48	1		T49	1
arcs[TransProgSt=>EscalateSt]	706	1			T22	22		T42	8		T43	16
arcs[PostTransSt=>EscalateSt]	5152	1			T4	4		T9	15		T21	20
arcs[InvalidSt=>EscalateSt]	14030	1			T9	11		T10	82		T12	47

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7437490	1			T1	1026		T2	6412		T3	111
auto[0]	auto[IdleSt]	24121482	1			T1	14560		T2	6015		T3	14071
auto[0]	auto[ClkMuxSt]	36822	1			T1	10		T2	73		T4	4
auto[0]	auto[CntIncrSt]	36471	1			T1	10		T2	73		T4	4
auto[0]	auto[CntProgSt]	1505777	1			T1	20		T2	146		T4	100
auto[0]	auto[TransCheckSt]	28653	1			T1	10		T2	73		T9	49
auto[0]	auto[TokenHashSt]	42063068	1			T1	190		T2	14020		T9	536
auto[0]	auto[FlashRmaSt]	36328	1			T1	55		T2	51		T9	146
auto[0]	auto[TokenCheck0St]	13058	1			T1	10		T2	29		T9	42
auto[0]	auto[TokenCheck1St]	9592	1			T1	10		T2	11		T9	28
auto[0]	auto[TransProgSt]	394883	1			T1	20		T9	951		T11	812
auto[0]	auto[PostTransSt]	14612632	1			T1	2612		T2	11467		T4	1928
auto[0]	auto[ScrapSt]	171175	1			T1	380		T33	157		T22	3
auto[0]	auto[EscalateSt]	5497711	1			T4	1491		T9	1908		T10	7904
auto[0]	auto[InvalidSt]	11412548	1			T9	851		T10	14941		T12	90403
auto[1]	auto[ResetSt]	158	1			T22	2		T42	3		T43	6
auto[1]	auto[IdleSt]	100	1			T22	5		T42	3		T43	6
auto[1]	auto[ClkMuxSt]	21	1			T42	3		T43	3		T44	3
auto[1]	auto[CntIncrSt]	43	1			T42	2		T43	2		T45	1
auto[1]	auto[CntProgSt]	610	1			T22	20		T42	1		T43	25
auto[1]	auto[TransCheckSt]	71	1			T22	1		T42	3		T45	4
auto[1]	auto[TokenHashSt]	589	1			T22	6		T42	21		T17	2
auto[1]	auto[FlashRmaSt]	26	1			T42	1		T45	1		T44	3
auto[1]	auto[TokenCheck0St]	41	1			T42	1		T45	1		T44	3
auto[1]	auto[TokenCheck1St]	15	1			T191	1		T192	3		T193	1
auto[1]	auto[TransProgSt]	465	1			T22	14		T42	4		T43	12
auto[1]	auto[PostTransSt]	2638	1			T4	2		T9	10		T21	10
auto[1]	auto[ScrapSt]	43	1			T22	1		T42	2		T43	1
auto[1]	auto[EscalateSt]	1359794	1			T4	194		T9	1372		T10	3920
auto[1]	auto[InvalidSt]	6984	1			T9	4		T10	40		T12	29

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7437486	1			T1	1026		T2	6412		T3	111
auto[0]	auto[IdleSt]	24121482	1			T1	14560		T2	6015		T3	14071
auto[0]	auto[ClkMuxSt]	36828	1			T1	10		T2	73		T4	4
auto[0]	auto[CntIncrSt]	36473	1			T1	10		T2	73		T4	4
auto[0]	auto[CntProgSt]	1505754	1			T1	20		T2	146		T4	100
auto[0]	auto[TransCheckSt]	28648	1			T1	10		T2	73		T9	49
auto[0]	auto[TokenHashSt]	42063024	1			T1	190		T2	14020		T9	536
auto[0]	auto[FlashRmaSt]	36327	1			T1	55		T2	51		T9	146
auto[0]	auto[TokenCheck0St]	13064	1			T1	10		T2	29		T9	42
auto[0]	auto[TokenCheck1St]	9590	1			T1	10		T2	11		T9	28
auto[0]	auto[TransProgSt]	394877	1			T1	20		T9	951		T11	812
auto[0]	auto[PostTransSt]	14612629	1			T1	2612		T2	11467		T4	1928
auto[0]	auto[ScrapSt]	171175	1			T1	380		T33	157		T22	4
auto[0]	auto[EscalateSt]	5479750	1			T4	1491		T9	2104		T10	7708
auto[0]	auto[InvalidSt]	11412486	1			T9	848		T10	14939		T12	90414
auto[1]	auto[ResetSt]	162	1			T22	1		T42	3		T43	6
auto[1]	auto[IdleSt]	100	1			T22	3		T42	1		T43	5
auto[1]	auto[ClkMuxSt]	15	1			T42	1		T43	1		T44	1
auto[1]	auto[CntIncrSt]	41	1			T42	2		T43	1		T45	1
auto[1]	auto[CntProgSt]	633	1			T22	16		T42	2		T43	24
auto[1]	auto[TransCheckSt]	76	1			T42	4		T45	4		T194	4
auto[1]	auto[TokenHashSt]	633	1			T22	9		T42	25		T53	1
auto[1]	auto[FlashRmaSt]	27	1			T43	1		T44	3		T195	1
auto[1]	auto[TokenCheck0St]	35	1			T43	1		T45	3		T44	2
auto[1]	auto[TokenCheck1St]	17	1			T43	3		T48	1		T49	1
auto[1]	auto[TransProgSt]	471	1			T22	16		T42	5		T43	7
auto[1]	auto[PostTransSt]	2641	1			T4	2		T9	5		T21	10
auto[1]	auto[ScrapSt]	43	1			T42	1		T45	1		T44	1
auto[1]	auto[EscalateSt]	1377755	1			T4	194		T9	1176		T10	4116
auto[1]	auto[InvalidSt]	7046	1			T9	7		T10	42		T12	18