Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104100584

1

T1

100345

T2

44302

T3

1919

auto[1]

1387677

1

T1

2061

T4

3267

T5

1188

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104085882

1

T1

100374

T2

44302

T3

1919

auto[1]

1402379

1

T1

1772

T4

2178

T5

1188

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7413882	1			T1	22238		T2	107		T3	85
auto[IdleSt]	22307532	1			T1	77869		T2	44195		T3	1834
auto[ClkMuxSt]	36406	1			T1	182		T5	61		T6	7
auto[CntIncrSt]	36126	1			T1	182		T5	61		T6	7
auto[CntProgSt]	1435139	1			T1	337		T5	904		T6	241
auto[TransCheckSt]	28208	1			T1	136		T5	50		T6	7
auto[TokenHashSt]	41831187	1			T1	852857		T5	1249		T6	693
auto[FlashRmaSt]	38128	1			T1	282		T5	76		T6	31
auto[TokenCheck0St]	13117	1			T1	93		T5	42		T6	7
auto[TokenCheck1St]	9633	1			T1	80		T5	26		T6	7
auto[TransProgSt]	424982	1			T1	158		T5	523		T6	337
auto[PostTransSt]	13467509	1			T1	37023		T5	9532		T6	18436
auto[ScrapSt]	308904	1			T1	979		T12	8		T16	36
auto[EscalateSt]	6728969	1			T1	13100		T4	6957		T5	3280
auto[InvalidSt]	11406631	1			T4	4191		T5	1921		T6	7202

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1908	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11406631	1			T4	4191		T5	1921		T6	7202
EscalateSt	6728969	1			T1	13100		T4	6957		T5	3280
ScrapSt	308904	1			T1	979		T12	8		T16	36
PostTransSt	13467509	1			T1	37023		T5	9532		T6	18436
TransProgSt	424982	1			T1	158		T5	523		T6	337
TokenCheck1St	9633	1			T1	80		T5	26		T6	7
TokenCheck0St	13117	1			T1	93		T5	42		T6	7
FlashRmaSt	38128	1			T1	282		T5	76		T6	31
TokenHashSt	41831187	1			T1	852857		T5	1249		T6	693
TransCheckSt	28208	1			T1	136		T5	50		T6	7
CntProgSt	1435139	1			T1	337		T5	904		T6	241
CntIncrSt	36126	1			T1	182		T5	61		T6	7
ClkMuxSt	36406	1			T1	182		T5	61		T6	7
IdleSt	22307532	1			T1	77869		T2	44195		T3	1834
ResetSt	7413882	1			T1	22238		T2	107		T3	85
arcs[ResetSt=>IdleSt]	54654	1			T1	189		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	313	1			T1	3		T12	2		T16	1
arcs[IdleSt=>ClkMuxSt]	36173	1			T1	182		T5	61		T6	7
arcs[ClkMuxSt=>CntIncrSt]	36126	1			T1	182		T5	61		T6	7
arcs[CntIncrSt=>PostTransSt]	1910	1			T1	9		T13	16		T14	19
arcs[CntIncrSt=>CntProgSt]	34149	1			T1	173		T5	61		T6	7
arcs[CntProgSt=>PostTransSt]	4924	1			T1	37		T5	11		T11	15
arcs[CntProgSt=>TransCheckSt]	28208	1			T1	136		T5	50		T6	7
arcs[TransCheckSt=>PostTransSt]	3754	1			T1	12		T17	38		T13	10
arcs[TransCheckSt=>TokenHashSt]	24353	1			T1	124		T5	50		T6	7
arcs[TokenHashSt=>PostTransSt]	10360	1			T1	29		T5	8		T20	8
arcs[TokenHashSt=>FlashRmaSt]	13164	1			T1	93		T5	42		T6	7
arcs[FlashRmaSt=>TokenCheck0St]	13117	1			T1	93		T5	42		T6	7
arcs[TokenCheck0St=>PostTransSt]	3417	1			T1	13		T5	16		T20	16
arcs[TokenCheck0St=>TokenCheck1St]	9633	1			T1	80		T5	26		T6	7
arcs[TokenCheck1St=>PostTransSt]	675	1			T1	1		T5	1		T20	2
arcs[TransProgSt=>PostTransSt]	8142	1			T1	79		T5	25		T6	7
arcs[IdleSt=>EscalateSt]	186	1			T12	8		T15	8		T39	7
arcs[ClkMuxSt=>EscalateSt]	47	1			T12	1		T39	2		T40	1
arcs[CntIncrSt=>EscalateSt]	67	1			T12	1		T39	3		T41	3
arcs[CntProgSt=>EscalateSt]	1017	1			T12	38		T15	37		T39	9
arcs[TransCheckSt=>EscalateSt]	101	1			T12	1		T15	1		T39	2
arcs[TokenHashSt=>EscalateSt]	828	1			T1	2		T12	14		T15	7
arcs[FlashRmaSt=>EscalateSt]	47	1			T12	1		T15	1		T41	2
arcs[TokenCheck0St=>EscalateSt]	67	1			T15	1		T39	4		T41	2
arcs[TokenCheck1St=>EscalateSt]	28	1			T39	1		T45	1		T46	1
arcs[TransProgSt=>EscalateSt]	788	1			T12	21		T15	22		T39	7
arcs[PostTransSt=>EscalateSt]	5270	1			T1	37		T5	11		T11	15
arcs[InvalidSt=>EscalateSt]	13854	1			T4	55		T5	13		T6	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7413728	1			T1	22238		T2	107		T3	85
auto[0]	auto[IdleSt]	22307419	1			T1	77869		T2	44195		T3	1834
auto[0]	auto[ClkMuxSt]	36373	1			T1	182		T5	61		T6	7
auto[0]	auto[CntIncrSt]	36085	1			T1	182		T5	61		T6	7
auto[0]	auto[CntProgSt]	1434487	1			T1	337		T5	904		T6	241
auto[0]	auto[TransCheckSt]	28147	1			T1	136		T5	50		T6	7
auto[0]	auto[TokenHashSt]	41830638	1			T1	852855		T5	1249		T6	693
auto[0]	auto[FlashRmaSt]	38100	1			T1	282		T5	76		T6	31
auto[0]	auto[TokenCheck0St]	13069	1			T1	93		T5	42		T6	7
auto[0]	auto[TokenCheck1St]	9615	1			T1	80		T5	26		T6	7
auto[0]	auto[TransProgSt]	424455	1			T1	158		T5	523		T6	337
auto[0]	auto[PostTransSt]	13464812	1			T1	37004		T5	9525		T6	18436
auto[0]	auto[ScrapSt]	308853	1			T1	979		T12	7		T16	36
auto[0]	auto[EscalateSt]	5353162	1			T1	11060		T4	3723		T5	2104
auto[0]	auto[InvalidSt]	11399733	1			T4	4158		T5	1916		T6	7201
auto[1]	auto[ResetSt]	154	1			T12	4		T15	2		T41	2
auto[1]	auto[IdleSt]	113	1			T12	5		T15	5		T39	5
auto[1]	auto[ClkMuxSt]	33	1			T12	1		T39	2		T40	1
auto[1]	auto[CntIncrSt]	41	1			T12	1		T39	2		T41	1
auto[1]	auto[CntProgSt]	652	1			T12	24		T15	29		T39	6
auto[1]	auto[TransCheckSt]	61	1			T12	1		T15	1		T39	1
auto[1]	auto[TokenHashSt]	549	1			T1	2		T12	11		T15	5
auto[1]	auto[FlashRmaSt]	28	1			T41	1		T45	1		T177	1
auto[1]	auto[TokenCheck0St]	48	1			T15	1		T39	3		T41	2
auto[1]	auto[TokenCheck1St]	18	1			T39	1		T45	1		T217	1
auto[1]	auto[TransProgSt]	527	1			T12	15		T15	15		T39	5
auto[1]	auto[PostTransSt]	2697	1			T1	19		T5	7		T11	7
auto[1]	auto[ScrapSt]	51	1			T12	1		T15	1		T40	2
auto[1]	auto[EscalateSt]	1375807	1			T1	2040		T4	3234		T5	1176
auto[1]	auto[InvalidSt]	6898	1			T4	33		T5	5		T6	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7413740	1			T1	22238		T2	107		T3	85
auto[0]	auto[IdleSt]	22307409	1			T1	77869		T2	44195		T3	1834
auto[0]	auto[ClkMuxSt]	36377	1			T1	182		T5	61		T6	7
auto[0]	auto[CntIncrSt]	36077	1			T1	182		T5	61		T6	7
auto[0]	auto[CntProgSt]	1434429	1			T1	337		T5	904		T6	241
auto[0]	auto[TransCheckSt]	28141	1			T1	136		T5	50		T6	7
auto[0]	auto[TokenHashSt]	41830632	1			T1	852857		T5	1249		T6	693
auto[0]	auto[FlashRmaSt]	38095	1			T1	282		T5	76		T6	31
auto[0]	auto[TokenCheck0St]	13077	1			T1	93		T5	42		T6	7
auto[0]	auto[TokenCheck1St]	9612	1			T1	80		T5	26		T6	7
auto[0]	auto[TransProgSt]	424463	1			T1	158		T5	523		T6	337
auto[0]	auto[PostTransSt]	13464840	1			T1	37005		T5	9528		T6	18436
auto[0]	auto[ScrapSt]	308854	1			T1	979		T12	6		T16	36
auto[0]	auto[EscalateSt]	5338553	1			T1	11346		T4	4801		T5	2104
auto[0]	auto[InvalidSt]	11399675	1			T4	4169		T5	1913		T6	7199
auto[1]	auto[ResetSt]	142	1			T12	2		T15	3		T41	1
auto[1]	auto[IdleSt]	123	1			T12	6		T15	7		T39	3
auto[1]	auto[ClkMuxSt]	29	1			T40	1		T177	2		T46	1
auto[1]	auto[CntIncrSt]	49	1			T39	3		T41	3		T40	1
auto[1]	auto[CntProgSt]	710	1			T12	27		T15	20		T39	6
auto[1]	auto[TransCheckSt]	67	1			T12	1		T39	1		T177	4
auto[1]	auto[TokenHashSt]	555	1			T12	9		T15	4		T39	21
auto[1]	auto[FlashRmaSt]	33	1			T12	1		T15	1		T41	1
auto[1]	auto[TokenCheck0St]	40	1			T15	1		T39	3		T41	1
auto[1]	auto[TokenCheck1St]	21	1			T45	1		T46	1		T217	1
auto[1]	auto[TransProgSt]	519	1			T12	13		T15	14		T39	4
auto[1]	auto[PostTransSt]	2669	1			T1	18		T5	4		T11	8
auto[1]	auto[ScrapSt]	50	1			T12	2		T40	2		T218	1
auto[1]	auto[EscalateSt]	1390416	1			T1	1754		T4	2156		T5	1176
auto[1]	auto[InvalidSt]	6956	1			T4	22		T5	8		T6	3