Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56968 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2103 |
1 |
|
|
T13 |
7 |
|
T14 |
8 |
|
T15 |
36 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58346 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
725 |
1 |
|
|
T12 |
21 |
|
T18 |
15 |
|
T35 |
19 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56934 |
1 |
|
|
T1 |
13 |
|
T3 |
9 |
|
T4 |
4 |
auto[1] |
2137 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
2 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56912 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2159 |
1 |
|
|
T6 |
1 |
|
T14 |
32 |
|
T21 |
4 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56929 |
1 |
|
|
T1 |
13 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2142 |
1 |
|
|
T1 |
1 |
|
T10 |
1 |
|
T6 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
53582 |
1 |
|
|
T1 |
7 |
|
T3 |
5 |
|
T4 |
4 |
no_err_inj |
5489 |
1 |
|
|
T1 |
7 |
|
T3 |
5 |
|
T10 |
4 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56878 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2193 |
1 |
|
|
T13 |
8 |
|
T14 |
18 |
|
T15 |
40 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58383 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
688 |
1 |
|
|
T12 |
16 |
|
T18 |
7 |
|
T35 |
24 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39584 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[1] |
19487 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T14 |
119 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57028 |
1 |
|
|
T1 |
14 |
|
T3 |
8 |
|
T4 |
4 |
auto[1] |
2043 |
1 |
|
|
T3 |
2 |
|
T10 |
1 |
|
T6 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57002 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2069 |
1 |
|
|
T14 |
54 |
|
T21 |
4 |
|
T15 |
62 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56968 |
1 |
|
|
T1 |
14 |
|
T3 |
9 |
|
T4 |
4 |
auto[1] |
2103 |
1 |
|
|
T3 |
1 |
|
T10 |
2 |
|
T14 |
33 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56952 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2119 |
1 |
|
|
T13 |
9 |
|
T14 |
16 |
|
T15 |
35 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56677 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[1] |
2394 |
1 |
|
|
T4 |
4 |
|
T14 |
28 |
|
T15 |
59 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58371 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
700 |
1 |
|
|
T12 |
20 |
|
T18 |
16 |
|
T35 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58340 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
731 |
1 |
|
|
T12 |
19 |
|
T18 |
14 |
|
T35 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58320 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
751 |
1 |
|
|
T12 |
13 |
|
T18 |
10 |
|
T35 |
22 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56095 |
1 |
|
|
T4 |
4 |
|
T12 |
89 |
|
T17 |
11 |
auto[1] |
2976 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55244 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
3827 |
1 |
|
|
T16 |
89 |
|
T41 |
81 |
|
T44 |
79 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56934 |
1 |
|
|
T1 |
12 |
|
T3 |
9 |
|
T4 |
4 |
auto[1] |
2137 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T6 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57031 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2040 |
1 |
|
|
T1 |
2 |
|
T6 |
2 |
|
T14 |
37 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56961 |
1 |
|
|
T1 |
13 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2110 |
1 |
|
|
T1 |
1 |
|
T10 |
2 |
|
T14 |
35 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56873 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2198 |
1 |
|
|
T13 |
7 |
|
T14 |
18 |
|
T15 |
48 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53026 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
6045 |
1 |
|
|
T13 |
9 |
|
T14 |
20 |
|
T15 |
43 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55324 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
3747 |
1 |
|
|
T19 |
60 |
|
T20 |
75 |
|
T54 |
61 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59071 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56856 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2215 |
1 |
|
|
T13 |
11 |
|
T14 |
12 |
|
T15 |
37 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56956 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2115 |
1 |
|
|
T13 |
7 |
|
T14 |
9 |
|
T15 |
30 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56980 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T4 |
4 |
auto[1] |
2091 |
1 |
|
|
T13 |
7 |
|
T14 |
20 |
|
T15 |
37 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
52143 |
1 |
|
|
T4 |
4 |
|
T12 |
89 |
|
T18 |
62 |
auto[0] |
no_err_inj |
3952 |
1 |
|
|
T17 |
11 |
|
T14 |
39 |
|
T15 |
141 |
auto[1] |
err_inj |
1439 |
1 |
|
|
T1 |
7 |
|
T3 |
5 |
|
T10 |
8 |
auto[1] |
no_err_inj |
1537 |
1 |
|
|
T1 |
7 |
|
T3 |
5 |
|
T10 |
4 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54240 |
1 |
|
|
T4 |
4 |
|
T12 |
89 |
|
T17 |
11 |
auto[0] |
auto[1] |
1855 |
1 |
|
|
T14 |
33 |
|
T21 |
7 |
|
T15 |
58 |
auto[1] |
auto[0] |
2791 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T10 |
12 |
auto[1] |
auto[1] |
185 |
1 |
|
|
T1 |
2 |
|
T6 |
2 |
|
T14 |
4 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54189 |
1 |
|
|
T4 |
4 |
|
T12 |
89 |
|
T17 |
11 |
auto[0] |
auto[1] |
1906 |
1 |
|
|
T14 |
49 |
|
T21 |
4 |
|
T15 |
55 |
auto[1] |
auto[0] |
2813 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T14 |
5 |
|
T15 |
7 |
|
T22 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54143 |
1 |
|
|
T4 |
4 |
|
T12 |
89 |
|
T17 |
11 |
auto[0] |
auto[1] |
1952 |
1 |
|
|
T14 |
33 |
|
T21 |
7 |
|
T15 |
43 |
auto[1] |
auto[0] |
2818 |
1 |
|
|
T1 |
13 |
|
T3 |
10 |
|
T10 |
10 |
auto[1] |
auto[1] |
158 |
1 |
|
|
T1 |
1 |
|
T10 |
2 |
|
T14 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54084 |
1 |
|
|
T4 |
4 |
|
T12 |
89 |
|
T17 |
11 |
auto[0] |
auto[1] |
2011 |
1 |
|
|
T14 |
26 |
|
T21 |
4 |
|
T15 |
52 |
auto[1] |
auto[0] |
2828 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T6 |
1 |
|
T14 |
6 |
|
T15 |
7 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54117 |
1 |
|
|
T4 |
4 |
|
T12 |
89 |
|
T17 |
11 |
auto[0] |
auto[1] |
1978 |
1 |
|
|
T14 |
31 |
|
T21 |
7 |
|
T15 |
60 |
auto[1] |
auto[0] |
2812 |
1 |
|
|
T1 |
13 |
|
T3 |
10 |
|
T10 |
11 |
auto[1] |
auto[1] |
164 |
1 |
|
|
T1 |
1 |
|
T10 |
1 |
|
T6 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54117 |
1 |
|
|
T4 |
4 |
|
T12 |
89 |
|
T17 |
11 |
auto[0] |
auto[1] |
1978 |
1 |
|
|
T14 |
33 |
|
T21 |
6 |
|
T15 |
51 |
auto[1] |
auto[0] |
2817 |
1 |
|
|
T1 |
13 |
|
T3 |
9 |
|
T10 |
10 |
auto[1] |
auto[1] |
159 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38382 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1202 |
1 |
|
|
T13 |
7 |
|
T14 |
4 |
|
T15 |
6 |
auto[1] |
auto[0] |
18586 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T14 |
115 |
auto[1] |
auto[1] |
901 |
1 |
|
|
T14 |
4 |
|
T15 |
30 |
|
T81 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38363 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1221 |
1 |
|
|
T13 |
8 |
|
T14 |
9 |
|
T15 |
20 |
auto[1] |
auto[0] |
18515 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T14 |
110 |
auto[1] |
auto[1] |
972 |
1 |
|
|
T14 |
9 |
|
T15 |
20 |
|
T81 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38192 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1392 |
1 |
|
|
T14 |
21 |
|
T15 |
53 |
|
T212 |
19 |
auto[1] |
auto[0] |
18485 |
1 |
|
|
T6 |
13 |
|
T14 |
112 |
|
T21 |
53 |
auto[1] |
auto[1] |
1002 |
1 |
|
|
T4 |
4 |
|
T14 |
7 |
|
T15 |
6 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38411 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1173 |
1 |
|
|
T13 |
9 |
|
T14 |
10 |
|
T15 |
11 |
auto[1] |
auto[0] |
18541 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T14 |
113 |
auto[1] |
auto[1] |
946 |
1 |
|
|
T14 |
6 |
|
T15 |
24 |
|
T81 |
17 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34524 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
5060 |
1 |
|
|
T13 |
9 |
|
T14 |
9 |
|
T15 |
16 |
auto[1] |
auto[0] |
18502 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T14 |
108 |
auto[1] |
auto[1] |
985 |
1 |
|
|
T14 |
11 |
|
T15 |
27 |
|
T81 |
12 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38455 |
1 |
|
|
T1 |
12 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1129 |
1 |
|
|
T1 |
2 |
|
T14 |
36 |
|
T15 |
23 |
auto[1] |
auto[0] |
18576 |
1 |
|
|
T4 |
4 |
|
T6 |
11 |
|
T14 |
118 |
auto[1] |
auto[1] |
911 |
1 |
|
|
T6 |
2 |
|
T14 |
1 |
|
T21 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38406 |
1 |
|
|
T1 |
12 |
|
T3 |
9 |
|
T10 |
12 |
auto[0] |
auto[1] |
1178 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T14 |
51 |
auto[1] |
auto[0] |
18528 |
1 |
|
|
T4 |
4 |
|
T6 |
12 |
|
T14 |
115 |
auto[1] |
auto[1] |
959 |
1 |
|
|
T6 |
1 |
|
T14 |
4 |
|
T21 |
6 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38393 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T14 |
53 |
|
T15 |
16 |
|
T180 |
1 |
auto[1] |
auto[0] |
18609 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T14 |
118 |
auto[1] |
auto[1] |
878 |
1 |
|
|
T14 |
1 |
|
T21 |
4 |
|
T15 |
46 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38452 |
1 |
|
|
T1 |
14 |
|
T3 |
8 |
|
T10 |
11 |
auto[0] |
auto[1] |
1132 |
1 |
|
|
T3 |
2 |
|
T10 |
1 |
|
T14 |
42 |
auto[1] |
auto[0] |
18576 |
1 |
|
|
T4 |
4 |
|
T6 |
12 |
|
T14 |
116 |
auto[1] |
auto[1] |
911 |
1 |
|
|
T6 |
1 |
|
T14 |
3 |
|
T21 |
3 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38420 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1164 |
1 |
|
|
T14 |
29 |
|
T15 |
16 |
|
T180 |
2 |
auto[1] |
auto[0] |
18492 |
1 |
|
|
T4 |
4 |
|
T6 |
12 |
|
T14 |
116 |
auto[1] |
auto[1] |
995 |
1 |
|
|
T6 |
1 |
|
T14 |
3 |
|
T21 |
4 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38407 |
1 |
|
|
T1 |
13 |
|
T3 |
9 |
|
T10 |
10 |
auto[0] |
auto[1] |
1177 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
2 |
auto[1] |
auto[0] |
18527 |
1 |
|
|
T4 |
4 |
|
T6 |
11 |
|
T14 |
117 |
auto[1] |
auto[1] |
960 |
1 |
|
|
T6 |
2 |
|
T14 |
2 |
|
T21 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38404 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1180 |
1 |
|
|
T13 |
7 |
|
T14 |
8 |
|
T15 |
12 |
auto[1] |
auto[0] |
18576 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T14 |
107 |
auto[1] |
auto[1] |
911 |
1 |
|
|
T14 |
12 |
|
T15 |
25 |
|
T81 |
12 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38364 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[0] |
auto[1] |
1220 |
1 |
|
|
T13 |
7 |
|
T14 |
5 |
|
T15 |
14 |
auto[1] |
auto[0] |
18592 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T14 |
115 |
auto[1] |
auto[1] |
895 |
1 |
|
|
T14 |
4 |
|
T15 |
16 |
|
T81 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37896 |
1 |
|
|
T12 |
89 |
|
T17 |
11 |
|
T18 |
62 |
auto[0] |
auto[1] |
1688 |
1 |
|
|
T1 |
14 |
|
T3 |
10 |
|
T10 |
12 |
auto[1] |
auto[0] |
18199 |
1 |
|
|
T4 |
4 |
|
T14 |
79 |
|
T21 |
53 |
auto[1] |
auto[1] |
1288 |
1 |
|
|
T6 |
13 |
|
T14 |
40 |
|
T15 |
73 |