Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123273212

1

T1

7264

T2

1836

T3

7884

auto[1]

1505793

1

T1

198

T3

198

T4

196

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123298737

1

T1

7066

T2

1836

T3

7884

auto[1]

1480268

1

T1

396

T3

198

T4

196

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7944790	1			T1	1285		T2	104		T3	1094
auto[IdleSt]	24375264	1			T1	994		T2	1732		T3	1543
auto[ClkMuxSt]	39033	1			T1	7		T3	5		T4	4
auto[CntIncrSt]	38757	1			T1	7		T3	5		T4	4
auto[CntProgSt]	1959556	1			T1	348		T3	1056		T4	658
auto[TransCheckSt]	30344	1			T1	7		T3	5		T10	4
auto[TokenHashSt]	54625844	1			T1	1712		T3	233		T10	214
auto[FlashRmaSt]	38832	1			T1	7		T3	13		T10	4
auto[TokenCheck0St]	13848	1			T1	7		T3	5		T10	4
auto[TokenCheck1St]	10261	1			T1	7		T3	5		T10	4
auto[TransProgSt]	527678	1			T1	480		T3	1364		T10	8
auto[PostTransSt]	14911846	1			T1	1193		T3	1229		T4	3127
auto[ScrapSt]	261642	1			T17	209		T31	7		T16	4
auto[EscalateSt]	7323107	1			T1	1016		T3	1011		T4	2379
auto[InvalidSt]	12676073	1			T1	392		T3	514		T10	762

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2130	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12676073	1			T1	392		T3	514		T10	762
EscalateSt	7323107	1			T1	1016		T3	1011		T4	2379
ScrapSt	261642	1			T17	209		T31	7		T16	4
PostTransSt	14911846	1			T1	1193		T3	1229		T4	3127
TransProgSt	527678	1			T1	480		T3	1364		T10	8
TokenCheck1St	10261	1			T1	7		T3	5		T10	4
TokenCheck0St	13848	1			T1	7		T3	5		T10	4
FlashRmaSt	38832	1			T1	7		T3	13		T10	4
TokenHashSt	54625844	1			T1	1712		T3	233		T10	214
TransCheckSt	30344	1			T1	7		T3	5		T10	4
CntProgSt	1959556	1			T1	348		T3	1056		T4	658
CntIncrSt	38757	1			T1	7		T3	5		T4	4
ClkMuxSt	39033	1			T1	7		T3	5		T4	4
IdleSt	24375264	1			T1	994		T2	1732		T3	1543
ResetSt	7944790	1			T1	1285		T2	104		T3	1094
arcs[ResetSt=>IdleSt]	59167	1			T1	15		T2	1		T3	10
arcs[IdleSt=>ScrapSt]	372	1			T17	4		T31	3		T16	1
arcs[IdleSt=>ClkMuxSt]	38782	1			T1	7		T3	5		T4	4
arcs[ClkMuxSt=>CntIncrSt]	38757	1			T1	7		T3	5		T4	4
arcs[CntIncrSt=>PostTransSt]	2119	1			T13	7		T14	9		T15	30
arcs[CntIncrSt=>CntProgSt]	36582	1			T1	7		T3	5		T4	4
arcs[CntProgSt=>PostTransSt]	5194	1			T4	4		T12	21		T18	15
arcs[CntProgSt=>TransCheckSt]	30344	1			T1	7		T3	5		T10	4
arcs[TransCheckSt=>PostTransSt]	3979	1			T19	35		T13	7		T20	41
arcs[TransCheckSt=>TokenHashSt]	26244	1			T1	7		T3	5		T10	4
arcs[TokenHashSt=>PostTransSt]	11467	1			T11	1		T12	3		T18	3
arcs[TokenHashSt=>FlashRmaSt]	13891	1			T1	7		T3	5		T10	4
arcs[FlashRmaSt=>TokenCheck0St]	13848	1			T1	7		T3	5		T10	4
arcs[TokenCheck0St=>PostTransSt]	3530	1			T12	15		T18	7		T19	10
arcs[TokenCheck0St=>TokenCheck1St]	10261	1			T1	7		T3	5		T10	4
arcs[TokenCheck1St=>PostTransSt]	698	1			T19	5		T20	6		T14	1
arcs[TransProgSt=>PostTransSt]	8823	1			T1	7		T3	5		T10	4
arcs[IdleSt=>EscalateSt]	150	1			T41	2		T45	4		T46	6
arcs[ClkMuxSt=>EscalateSt]	25	1			T41	1		T42	2		T43	3
arcs[CntIncrSt=>EscalateSt]	56	1			T16	3		T41	2		T44	1
arcs[CntProgSt=>EscalateSt]	1044	1			T16	44		T41	7		T44	6
arcs[TransCheckSt=>EscalateSt]	121	1			T16	1		T41	5		T44	5
arcs[TokenHashSt=>EscalateSt]	885	1			T16	15		T41	32		T44	35
arcs[FlashRmaSt=>EscalateSt]	43	1			T41	2		T44	1		T45	1
arcs[TokenCheck0St=>EscalateSt]	57	1			T41	1		T44	3		T45	2
arcs[TokenCheck1St=>EscalateSt]	20	1			T44	1		T47	1		T48	2
arcs[TransProgSt=>EscalateSt]	720	1			T16	17		T41	4		T44	5
arcs[PostTransSt=>EscalateSt]	5578	1			T4	4		T12	21		T18	15
arcs[InvalidSt=>EscalateSt]	15473	1			T1	6		T3	4		T10	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7944616	1			T1	1285		T2	104		T3	1094
auto[0]	auto[IdleSt]	24375168	1			T1	994		T2	1732		T3	1543
auto[0]	auto[ClkMuxSt]	39014	1			T1	7		T3	5		T4	4
auto[0]	auto[CntIncrSt]	38720	1			T1	7		T3	5		T4	4
auto[0]	auto[CntProgSt]	1958850	1			T1	348		T3	1056		T4	658
auto[0]	auto[TransCheckSt]	30257	1			T1	7		T3	5		T10	4
auto[0]	auto[TokenHashSt]	54625249	1			T1	1712		T3	233		T10	214
auto[0]	auto[FlashRmaSt]	38801	1			T1	7		T3	13		T10	4
auto[0]	auto[TokenCheck0St]	13807	1			T1	7		T3	5		T10	4
auto[0]	auto[TokenCheck1St]	10246	1			T1	7		T3	5		T10	4
auto[0]	auto[TransProgSt]	527182	1			T1	480		T3	1364		T10	8
auto[0]	auto[PostTransSt]	14909010	1			T1	1193		T3	1229		T4	3125
auto[0]	auto[ScrapSt]	261592	1			T17	209		T31	7		T16	3
auto[0]	auto[EscalateSt]	5830299	1			T1	820		T3	815		T4	2185
auto[0]	auto[InvalidSt]	12668271	1			T1	390		T3	512		T10	760
auto[1]	auto[ResetSt]	174	1			T16	1		T41	3		T44	1
auto[1]	auto[IdleSt]	96	1			T45	1		T46	5		T42	6
auto[1]	auto[ClkMuxSt]	19	1			T41	1		T42	1		T43	3
auto[1]	auto[CntIncrSt]	37	1			T16	1		T41	2		T45	2
auto[1]	auto[CntProgSt]	706	1			T16	25		T41	4		T44	4
auto[1]	auto[TransCheckSt]	87	1			T16	1		T41	4		T44	3
auto[1]	auto[TokenHashSt]	595	1			T16	13		T41	24		T44	20
auto[1]	auto[FlashRmaSt]	31	1			T41	1		T45	1		T47	2
auto[1]	auto[TokenCheck0St]	41	1			T41	1		T44	2		T45	1
auto[1]	auto[TokenCheck1St]	15	1			T44	1		T48	2		T211	1
auto[1]	auto[TransProgSt]	496	1			T16	13		T41	3		T44	3
auto[1]	auto[PostTransSt]	2836	1			T4	2		T12	12		T18	4
auto[1]	auto[ScrapSt]	50	1			T16	1		T41	2		T44	1
auto[1]	auto[EscalateSt]	1492808	1			T1	196		T3	196		T4	194
auto[1]	auto[InvalidSt]	7802	1			T1	2		T3	2		T10	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7944597	1			T1	1285		T2	104		T3	1094
auto[0]	auto[IdleSt]	24375170	1			T1	994		T2	1732		T3	1543
auto[0]	auto[ClkMuxSt]	39021	1			T1	7		T3	5		T4	4
auto[0]	auto[CntIncrSt]	38723	1			T1	7		T3	5		T4	4
auto[0]	auto[CntProgSt]	1958880	1			T1	348		T3	1056		T4	658
auto[0]	auto[TransCheckSt]	30269	1			T1	7		T3	5		T10	4
auto[0]	auto[TokenHashSt]	54625269	1			T1	1712		T3	233		T10	214
auto[0]	auto[FlashRmaSt]	38805	1			T1	7		T3	13		T10	4
auto[0]	auto[TokenCheck0St]	13813	1			T1	7		T3	5		T10	4
auto[0]	auto[TokenCheck1St]	10247	1			T1	7		T3	5		T10	4
auto[0]	auto[TransProgSt]	527193	1			T1	480		T3	1364		T10	8
auto[0]	auto[PostTransSt]	14908983	1			T1	1193		T3	1229		T4	3125
auto[0]	auto[ScrapSt]	261593	1			T17	209		T31	7		T16	4
auto[0]	auto[EscalateSt]	5855642	1			T1	624		T3	815		T4	2185
auto[0]	auto[InvalidSt]	12668402	1			T1	388		T3	512		T10	760
auto[1]	auto[ResetSt]	193	1			T16	5		T41	3		T44	3
auto[1]	auto[IdleSt]	94	1			T41	2		T45	3		T46	2
auto[1]	auto[ClkMuxSt]	12	1			T41	1		T42	1		T43	2
auto[1]	auto[CntIncrSt]	34	1			T16	2		T41	2		T44	1
auto[1]	auto[CntProgSt]	676	1			T16	32		T41	4		T44	5
auto[1]	auto[TransCheckSt]	75	1			T16	1		T41	3		T44	5
auto[1]	auto[TokenHashSt]	575	1			T16	5		T41	19		T44	23
auto[1]	auto[FlashRmaSt]	27	1			T41	1		T44	1		T45	1
auto[1]	auto[TokenCheck0St]	35	1			T44	2		T45	1		T48	1
auto[1]	auto[TokenCheck1St]	14	1			T47	1		T48	1		T161	1
auto[1]	auto[TransProgSt]	485	1			T16	12		T41	3		T44	3
auto[1]	auto[PostTransSt]	2863	1			T4	2		T12	9		T18	11
auto[1]	auto[ScrapSt]	49	1			T41	2		T44	1		T45	1
auto[1]	auto[EscalateSt]	1467465	1			T1	392		T3	196		T4	194
auto[1]	auto[InvalidSt]	7671	1			T1	4		T3	2		T10	2