Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113831134

1

T1

150900

T2

1284

T3

27487

auto[1]

1484205

1

T1

396

T3

1287

T4

3267

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113857618

1

T1

150702

T2

1284

T3

27685

auto[1]

1457721

1

T1

594

T3

1089

T4

2475

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7767708	1			T1	4926		T2	96		T3	5345
auto[IdleSt]	22634483	1			T1	80177		T2	1188		T3	5987
auto[ClkMuxSt]	38094	1			T1	55		T3	47		T5	3
auto[CntIncrSt]	37786	1			T1	55		T3	47		T5	3
auto[CntProgSt]	1761111	1			T1	696		T3	951		T5	6
auto[TransCheckSt]	29260	1			T1	36		T3	35		T5	3
auto[TokenHashSt]	47789737	1			T1	274		T3	1872		T5	63
auto[FlashRmaSt]	37985	1			T1	8		T3	74		T5	3
auto[TokenCheck0St]	13491	1			T1	8		T3	31		T5	3
auto[TokenCheck1St]	9950	1			T1	5		T3	21		T5	3
auto[TransProgSt]	453647	1			T1	79		T3	517		T5	6
auto[PostTransSt]	13576059	1			T1	59396		T3	7903		T5	2179
auto[ScrapSt]	211064	1			T12	378		T18	50		T21	5055
auto[EscalateSt]	7509249	1			T1	5581		T3	3502		T4	7365
auto[InvalidSt]	13443659	1			T3	2442		T4	4488		T10	2569

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2056	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13443659	1			T3	2442		T4	4488		T10	2569
EscalateSt	7509249	1			T1	5581		T3	3502		T4	7365
ScrapSt	211064	1			T12	378		T18	50		T21	5055
PostTransSt	13576059	1			T1	59396		T3	7903		T5	2179
TransProgSt	453647	1			T1	79		T3	517		T5	6
TokenCheck1St	9950	1			T1	5		T3	21		T5	3
TokenCheck0St	13491	1			T1	8		T3	31		T5	3
FlashRmaSt	37985	1			T1	8		T3	74		T5	3
TokenHashSt	47789737	1			T1	274		T3	1872		T5	63
TransCheckSt	29260	1			T1	36		T3	35		T5	3
CntProgSt	1761111	1			T1	696		T3	951		T5	6
CntIncrSt	37786	1			T1	55		T3	47		T5	3
ClkMuxSt	38094	1			T1	55		T3	47		T5	3
IdleSt	22634483	1			T1	80177		T2	1188		T3	5987
ResetSt	7767708	1			T1	4926		T2	96		T3	5345
arcs[ResetSt=>IdleSt]	57333	1			T1	56		T2	1		T3	60
arcs[IdleSt=>ScrapSt]	314	1			T12	2		T18	1		T21	1
arcs[IdleSt=>ClkMuxSt]	37822	1			T1	55		T3	47		T5	3
arcs[ClkMuxSt=>CntIncrSt]	37786	1			T1	55		T3	47		T5	3
arcs[CntIncrSt=>PostTransSt]	1973	1			T1	9		T12	21		T14	7
arcs[CntIncrSt=>CntProgSt]	35745	1			T1	46		T3	47		T5	3
arcs[CntProgSt=>PostTransSt]	5434	1			T1	10		T3	12		T10	24
arcs[CntProgSt=>TransCheckSt]	29260	1			T1	36		T3	35		T5	3
arcs[TransCheckSt=>PostTransSt]	4017	1			T1	11		T12	22		T14	16
arcs[TransCheckSt=>TokenHashSt]	25145	1			T1	25		T3	35		T5	3
arcs[TokenHashSt=>PostTransSt]	10789	1			T1	17		T3	4		T10	12
arcs[TokenHashSt=>FlashRmaSt]	13533	1			T1	8		T3	31		T5	3
arcs[FlashRmaSt=>TokenCheck0St]	13491	1			T1	8		T3	31		T5	3
arcs[TokenCheck0St=>PostTransSt]	3479	1			T1	3		T3	10		T10	10
arcs[TokenCheck0St=>TokenCheck1St]	9950	1			T1	5		T3	21		T5	3
arcs[TokenCheck1St=>PostTransSt]	706	1			T1	1		T3	1		T22	1
arcs[TransProgSt=>PostTransSt]	8454	1			T1	4		T3	20		T5	3
arcs[IdleSt=>EscalateSt]	146	1			T42	4		T43	5		T44	7
arcs[ClkMuxSt=>EscalateSt]	36	1			T42	1		T43	3		T44	1
arcs[CntIncrSt=>EscalateSt]	68	1			T42	2		T43	1		T45	5
arcs[CntProgSt=>EscalateSt]	1051	1			T42	17		T43	6		T45	33
arcs[TransCheckSt=>EscalateSt]	98	1			T43	10		T49	1		T44	4
arcs[TokenHashSt=>EscalateSt]	823	1			T14	2		T42	6		T34	1
arcs[FlashRmaSt=>EscalateSt]	42	1			T42	1		T45	1		T44	2
arcs[TokenCheck0St=>EscalateSt]	62	1			T43	1		T45	1		T49	3
arcs[TokenCheck1St=>EscalateSt]	27	1			T42	1		T50	1		T51	1
arcs[TransProgSt=>EscalateSt]	763	1			T42	20		T43	7		T45	21
arcs[PostTransSt=>EscalateSt]	5797	1			T1	10		T3	12		T10	24
arcs[InvalidSt=>EscalateSt]	14831	1			T3	12		T4	58		T10	17

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7767532	1			T1	4926		T2	96		T3	5345
auto[0]	auto[IdleSt]	22634378	1			T1	80177		T2	1188		T3	5987
auto[0]	auto[ClkMuxSt]	38071	1			T1	55		T3	47		T5	3
auto[0]	auto[CntIncrSt]	37742	1			T1	55		T3	47		T5	3
auto[0]	auto[CntProgSt]	1760407	1			T1	696		T3	951		T5	6
auto[0]	auto[TransCheckSt]	29199	1			T1	36		T3	35		T5	3
auto[0]	auto[TokenHashSt]	47789186	1			T1	274		T3	1872		T5	63
auto[0]	auto[FlashRmaSt]	37963	1			T1	8		T3	74		T5	3
auto[0]	auto[TokenCheck0St]	13453	1			T1	8		T3	31		T5	3
auto[0]	auto[TokenCheck1St]	9932	1			T1	5		T3	21		T5	3
auto[0]	auto[TransProgSt]	453144	1			T1	79		T3	517		T5	6
auto[0]	auto[PostTransSt]	13573037	1			T1	59392		T3	7897		T5	2179
auto[0]	auto[ScrapSt]	211011	1			T12	378		T18	50		T21	5055
auto[0]	auto[EscalateSt]	6037834	1			T1	5189		T3	2228		T4	4131
auto[0]	auto[InvalidSt]	13436189	1			T3	2435		T4	4455		T10	2562
auto[1]	auto[ResetSt]	176	1			T42	2		T43	8		T45	6
auto[1]	auto[IdleSt]	105	1			T42	1		T43	2		T44	6
auto[1]	auto[ClkMuxSt]	23	1			T43	3		T44	1		T50	1
auto[1]	auto[CntIncrSt]	44	1			T42	2		T43	1		T45	2
auto[1]	auto[CntProgSt]	704	1			T42	12		T43	3		T45	18
auto[1]	auto[TransCheckSt]	61	1			T43	5		T44	4		T200	1
auto[1]	auto[TokenHashSt]	551	1			T14	1		T42	4		T43	21
auto[1]	auto[FlashRmaSt]	22	1			T45	1		T44	1		T201	1
auto[1]	auto[TokenCheck0St]	38	1			T43	1		T45	1		T49	2
auto[1]	auto[TokenCheck1St]	18	1			T50	1		T202	1		T203	1
auto[1]	auto[TransProgSt]	503	1			T42	10		T43	7		T45	12
auto[1]	auto[PostTransSt]	3022	1			T1	4		T3	6		T10	11
auto[1]	auto[ScrapSt]	53	1			T42	2		T43	1		T45	1
auto[1]	auto[EscalateSt]	1471415	1			T1	392		T3	1274		T4	3234
auto[1]	auto[InvalidSt]	7470	1			T3	7		T4	33		T10	7

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7767548	1			T1	4926		T2	96		T3	5345
auto[0]	auto[IdleSt]	22634393	1			T1	80177		T2	1188		T3	5987
auto[0]	auto[ClkMuxSt]	38069	1			T1	55		T3	47		T5	3
auto[0]	auto[CntIncrSt]	37742	1			T1	55		T3	47		T5	3
auto[0]	auto[CntProgSt]	1760410	1			T1	696		T3	951		T5	6
auto[0]	auto[TransCheckSt]	29192	1			T1	36		T3	35		T5	3
auto[0]	auto[TokenHashSt]	47789206	1			T1	274		T3	1872		T5	63
auto[0]	auto[FlashRmaSt]	37956	1			T1	8		T3	74		T5	3
auto[0]	auto[TokenCheck0St]	13448	1			T1	8		T3	31		T5	3
auto[0]	auto[TokenCheck1St]	9932	1			T1	5		T3	21		T5	3
auto[0]	auto[TransProgSt]	453122	1			T1	79		T3	517		T5	6
auto[0]	auto[PostTransSt]	13573162	1			T1	59390		T3	7897		T5	2179
auto[0]	auto[ScrapSt]	211021	1			T12	378		T18	50		T21	5055
auto[0]	auto[EscalateSt]	6064063	1			T1	4993		T3	2424		T4	4915
auto[0]	auto[InvalidSt]	13436298	1			T3	2437		T4	4463		T10	2559
auto[1]	auto[ResetSt]	160	1			T42	1		T43	6		T45	4
auto[1]	auto[IdleSt]	90	1			T42	4		T43	4		T44	5
auto[1]	auto[ClkMuxSt]	25	1			T42	1		T43	1		T50	1
auto[1]	auto[CntIncrSt]	44	1			T42	2		T43	1		T45	3
auto[1]	auto[CntProgSt]	701	1			T42	13		T43	4		T45	20
auto[1]	auto[TransCheckSt]	68	1			T43	9		T49	1		T44	2
auto[1]	auto[TokenHashSt]	531	1			T14	1		T42	4		T34	1
auto[1]	auto[FlashRmaSt]	29	1			T42	1		T44	2		T201	1
auto[1]	auto[TokenCheck0St]	43	1			T43	1		T45	1		T49	2
auto[1]	auto[TokenCheck1St]	18	1			T42	1		T51	1		T202	1
auto[1]	auto[TransProgSt]	525	1			T42	13		T43	6		T45	17
auto[1]	auto[PostTransSt]	2897	1			T1	6		T3	6		T10	13
auto[1]	auto[ScrapSt]	43	1			T42	2		T43	2		T45	1
auto[1]	auto[EscalateSt]	1445186	1			T1	588		T3	1078		T4	2450
auto[1]	auto[InvalidSt]	7361	1			T3	5		T4	25		T10	10