Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55329 |
1 |
|
|
T1 |
71 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2013 |
1 |
|
|
T1 |
6 |
|
T4 |
6 |
|
T9 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56581 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
761 |
1 |
|
|
T45 |
14 |
|
T63 |
14 |
|
T64 |
8 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55367 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
1975 |
1 |
|
|
T12 |
4 |
|
T22 |
3 |
|
T32 |
2 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55239 |
1 |
|
|
T1 |
77 |
|
T2 |
12 |
|
T3 |
17 |
auto[1] |
2103 |
1 |
|
|
T2 |
2 |
|
T12 |
6 |
|
T15 |
30 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55273 |
1 |
|
|
T1 |
77 |
|
T2 |
13 |
|
T3 |
17 |
auto[1] |
2069 |
1 |
|
|
T2 |
1 |
|
T12 |
5 |
|
T22 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
52149 |
1 |
|
|
T1 |
77 |
|
T2 |
5 |
|
T4 |
83 |
no_err_inj |
5193 |
1 |
|
|
T2 |
9 |
|
T3 |
17 |
|
T21 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55238 |
1 |
|
|
T1 |
69 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2104 |
1 |
|
|
T1 |
8 |
|
T4 |
21 |
|
T9 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56586 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
756 |
1 |
|
|
T45 |
13 |
|
T63 |
12 |
|
T64 |
18 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39108 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
64 |
auto[1] |
18234 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55290 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2052 |
1 |
|
|
T12 |
4 |
|
T22 |
2 |
|
T15 |
20 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55228 |
1 |
|
|
T1 |
77 |
|
T2 |
13 |
|
T3 |
17 |
auto[1] |
2114 |
1 |
|
|
T2 |
1 |
|
T12 |
13 |
|
T22 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55267 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2075 |
1 |
|
|
T12 |
9 |
|
T32 |
2 |
|
T15 |
30 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55291 |
1 |
|
|
T1 |
65 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2051 |
1 |
|
|
T1 |
12 |
|
T4 |
13 |
|
T9 |
8 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54814 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2528 |
1 |
|
|
T10 |
17 |
|
T59 |
3 |
|
T15 |
106 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56622 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
720 |
1 |
|
|
T45 |
26 |
|
T63 |
8 |
|
T64 |
13 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56606 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
736 |
1 |
|
|
T45 |
13 |
|
T63 |
7 |
|
T64 |
9 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56573 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
769 |
1 |
|
|
T45 |
23 |
|
T63 |
12 |
|
T64 |
10 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54340 |
1 |
|
|
T1 |
77 |
|
T3 |
17 |
|
T4 |
83 |
auto[1] |
3002 |
1 |
|
|
T2 |
14 |
|
T22 |
14 |
|
T32 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53787 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
3555 |
1 |
|
|
T13 |
97 |
|
T14 |
68 |
|
T18 |
94 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55301 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2041 |
1 |
|
|
T12 |
10 |
|
T22 |
1 |
|
T32 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55234 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2108 |
1 |
|
|
T12 |
12 |
|
T15 |
23 |
|
T23 |
5 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55252 |
1 |
|
|
T1 |
77 |
|
T2 |
13 |
|
T3 |
17 |
auto[1] |
2090 |
1 |
|
|
T2 |
1 |
|
T12 |
7 |
|
T32 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55329 |
1 |
|
|
T1 |
64 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2013 |
1 |
|
|
T1 |
13 |
|
T4 |
6 |
|
T9 |
7 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51509 |
1 |
|
|
T1 |
70 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
5833 |
1 |
|
|
T1 |
7 |
|
T4 |
5 |
|
T9 |
8 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53887 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
3455 |
1 |
|
|
T60 |
99 |
|
T61 |
51 |
|
T62 |
51 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57342 |
1 |
|
|
T1 |
77 |
|
T2 |
14 |
|
T3 |
17 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55273 |
1 |
|
|
T1 |
65 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2069 |
1 |
|
|
T1 |
12 |
|
T4 |
11 |
|
T9 |
6 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55317 |
1 |
|
|
T1 |
66 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2025 |
1 |
|
|
T1 |
11 |
|
T4 |
13 |
|
T9 |
9 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55208 |
1 |
|
|
T1 |
69 |
|
T2 |
14 |
|
T3 |
17 |
auto[1] |
2134 |
1 |
|
|
T1 |
8 |
|
T4 |
8 |
|
T9 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
50583 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T9 |
64 |
auto[0] |
no_err_inj |
3757 |
1 |
|
|
T3 |
17 |
|
T21 |
7 |
|
T15 |
69 |
auto[1] |
err_inj |
1566 |
1 |
|
|
T2 |
5 |
|
T22 |
8 |
|
T32 |
7 |
auto[1] |
no_err_inj |
1436 |
1 |
|
|
T2 |
9 |
|
T22 |
6 |
|
T32 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52414 |
1 |
|
|
T1 |
77 |
|
T3 |
17 |
|
T4 |
83 |
auto[0] |
auto[1] |
1926 |
1 |
|
|
T12 |
12 |
|
T15 |
21 |
|
T23 |
5 |
auto[1] |
auto[0] |
2820 |
1 |
|
|
T2 |
14 |
|
T22 |
14 |
|
T32 |
12 |
auto[1] |
auto[1] |
182 |
1 |
|
|
T15 |
2 |
|
T16 |
3 |
|
T232 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52401 |
1 |
|
|
T1 |
77 |
|
T3 |
17 |
|
T4 |
83 |
auto[0] |
auto[1] |
1939 |
1 |
|
|
T12 |
13 |
|
T15 |
20 |
|
T23 |
11 |
auto[1] |
auto[0] |
2827 |
1 |
|
|
T2 |
13 |
|
T22 |
13 |
|
T32 |
12 |
auto[1] |
auto[1] |
175 |
1 |
|
|
T2 |
1 |
|
T22 |
1 |
|
T15 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52412 |
1 |
|
|
T1 |
77 |
|
T3 |
17 |
|
T4 |
83 |
auto[0] |
auto[1] |
1928 |
1 |
|
|
T12 |
7 |
|
T15 |
17 |
|
T23 |
12 |
auto[1] |
auto[0] |
2840 |
1 |
|
|
T2 |
13 |
|
T22 |
14 |
|
T32 |
11 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T2 |
1 |
|
T32 |
1 |
|
T15 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52421 |
1 |
|
|
T1 |
77 |
|
T3 |
17 |
|
T4 |
83 |
auto[0] |
auto[1] |
1919 |
1 |
|
|
T12 |
6 |
|
T15 |
26 |
|
T23 |
12 |
auto[1] |
auto[0] |
2818 |
1 |
|
|
T2 |
12 |
|
T22 |
14 |
|
T32 |
12 |
auto[1] |
auto[1] |
184 |
1 |
|
|
T2 |
2 |
|
T15 |
4 |
|
T16 |
7 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52469 |
1 |
|
|
T1 |
77 |
|
T3 |
17 |
|
T4 |
83 |
auto[0] |
auto[1] |
1871 |
1 |
|
|
T12 |
5 |
|
T15 |
16 |
|
T23 |
6 |
auto[1] |
auto[0] |
2804 |
1 |
|
|
T2 |
13 |
|
T22 |
13 |
|
T32 |
11 |
auto[1] |
auto[1] |
198 |
1 |
|
|
T2 |
1 |
|
T22 |
1 |
|
T32 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52541 |
1 |
|
|
T1 |
77 |
|
T3 |
17 |
|
T4 |
83 |
auto[0] |
auto[1] |
1799 |
1 |
|
|
T12 |
4 |
|
T15 |
19 |
|
T23 |
14 |
auto[1] |
auto[0] |
2826 |
1 |
|
|
T2 |
14 |
|
T22 |
11 |
|
T32 |
10 |
auto[1] |
auto[1] |
176 |
1 |
|
|
T22 |
3 |
|
T32 |
2 |
|
T15 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37920 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
55 |
auto[0] |
auto[1] |
1188 |
1 |
|
|
T9 |
9 |
|
T15 |
10 |
|
T16 |
9 |
auto[1] |
auto[0] |
17409 |
1 |
|
|
T1 |
71 |
|
T4 |
77 |
|
T5 |
81 |
auto[1] |
auto[1] |
825 |
1 |
|
|
T1 |
6 |
|
T4 |
6 |
|
T5 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37892 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
55 |
auto[0] |
auto[1] |
1216 |
1 |
|
|
T9 |
9 |
|
T15 |
20 |
|
T16 |
5 |
auto[1] |
auto[0] |
17346 |
1 |
|
|
T1 |
69 |
|
T4 |
62 |
|
T5 |
81 |
auto[1] |
auto[1] |
888 |
1 |
|
|
T1 |
8 |
|
T4 |
21 |
|
T5 |
10 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37609 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
64 |
auto[0] |
auto[1] |
1499 |
1 |
|
|
T10 |
17 |
|
T59 |
3 |
|
T15 |
63 |
auto[1] |
auto[0] |
17205 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
auto[1] |
auto[1] |
1029 |
1 |
|
|
T15 |
43 |
|
T16 |
15 |
|
T233 |
11 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37898 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
56 |
auto[0] |
auto[1] |
1210 |
1 |
|
|
T9 |
8 |
|
T15 |
16 |
|
T16 |
8 |
auto[1] |
auto[0] |
17393 |
1 |
|
|
T1 |
65 |
|
T4 |
70 |
|
T5 |
83 |
auto[1] |
auto[1] |
841 |
1 |
|
|
T1 |
12 |
|
T4 |
13 |
|
T5 |
8 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34132 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
56 |
auto[0] |
auto[1] |
4976 |
1 |
|
|
T9 |
8 |
|
T11 |
76 |
|
T19 |
70 |
auto[1] |
auto[0] |
17377 |
1 |
|
|
T1 |
70 |
|
T4 |
78 |
|
T5 |
81 |
auto[1] |
auto[1] |
857 |
1 |
|
|
T1 |
7 |
|
T4 |
5 |
|
T5 |
10 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37900 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
64 |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T12 |
12 |
|
T15 |
2 |
|
T16 |
18 |
auto[1] |
auto[0] |
17334 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
auto[1] |
auto[1] |
900 |
1 |
|
|
T15 |
21 |
|
T23 |
5 |
|
T24 |
5 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37955 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
64 |
auto[0] |
auto[1] |
1153 |
1 |
|
|
T12 |
10 |
|
T32 |
1 |
|
T15 |
6 |
auto[1] |
auto[0] |
17346 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
auto[1] |
auto[1] |
888 |
1 |
|
|
T22 |
1 |
|
T15 |
15 |
|
T23 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37958 |
1 |
|
|
T2 |
13 |
|
T3 |
17 |
|
T9 |
64 |
auto[0] |
auto[1] |
1150 |
1 |
|
|
T2 |
1 |
|
T12 |
13 |
|
T15 |
2 |
auto[1] |
auto[0] |
17270 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
auto[1] |
auto[1] |
964 |
1 |
|
|
T22 |
1 |
|
T15 |
20 |
|
T23 |
11 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37975 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
64 |
auto[0] |
auto[1] |
1133 |
1 |
|
|
T12 |
4 |
|
T15 |
3 |
|
T90 |
1 |
auto[1] |
auto[0] |
17315 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
auto[1] |
auto[1] |
919 |
1 |
|
|
T22 |
2 |
|
T15 |
17 |
|
T23 |
14 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37941 |
1 |
|
|
T2 |
12 |
|
T3 |
17 |
|
T9 |
64 |
auto[0] |
auto[1] |
1167 |
1 |
|
|
T2 |
2 |
|
T12 |
6 |
|
T15 |
4 |
auto[1] |
auto[0] |
17298 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
auto[1] |
auto[1] |
936 |
1 |
|
|
T15 |
26 |
|
T23 |
12 |
|
T24 |
10 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37995 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
64 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T12 |
4 |
|
T32 |
2 |
|
T15 |
1 |
auto[1] |
auto[0] |
17372 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
auto[1] |
auto[1] |
862 |
1 |
|
|
T22 |
3 |
|
T15 |
19 |
|
T23 |
14 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37840 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
56 |
auto[0] |
auto[1] |
1268 |
1 |
|
|
T9 |
8 |
|
T15 |
12 |
|
T16 |
7 |
auto[1] |
auto[0] |
17368 |
1 |
|
|
T1 |
69 |
|
T4 |
75 |
|
T5 |
80 |
auto[1] |
auto[1] |
866 |
1 |
|
|
T1 |
8 |
|
T4 |
8 |
|
T5 |
11 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37938 |
1 |
|
|
T2 |
14 |
|
T3 |
17 |
|
T9 |
55 |
auto[0] |
auto[1] |
1170 |
1 |
|
|
T9 |
9 |
|
T15 |
10 |
|
T16 |
3 |
auto[1] |
auto[0] |
17379 |
1 |
|
|
T1 |
66 |
|
T4 |
70 |
|
T5 |
75 |
auto[1] |
auto[1] |
855 |
1 |
|
|
T1 |
11 |
|
T4 |
13 |
|
T5 |
16 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37389 |
1 |
|
|
T3 |
17 |
|
T9 |
64 |
|
T10 |
17 |
auto[0] |
auto[1] |
1719 |
1 |
|
|
T2 |
14 |
|
T32 |
12 |
|
T15 |
76 |
auto[1] |
auto[0] |
16951 |
1 |
|
|
T1 |
77 |
|
T4 |
83 |
|
T5 |
91 |
auto[1] |
auto[1] |
1283 |
1 |
|
|
T22 |
14 |
|
T15 |
1 |
|
T16 |
40 |