Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116583859

1

T1

167107

T2

13157

T3

5331

auto[1]

1475057

1

T1

396

T2

297

T4

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116607500

1

T1

167305

T2

13355

T3

5331

auto[1]

1451416

1

T1

198

T2

99

T4

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7837369	1			T1	6959		T2	1330		T3	1594
auto[IdleSt]	23517372	1			T1	84539		T2	2207		T3	2012
auto[ClkMuxSt]	37740	1			T1	77		T2	9		T3	15
auto[CntIncrSt]	37408	1			T1	77		T2	9		T3	15
auto[CntProgSt]	1694239	1			T1	1065		T2	1535		T3	30
auto[TransCheckSt]	29005	1			T1	60		T2	9		T3	15
auto[TokenHashSt]	49324572	1			T1	572		T2	2370		T3	164
auto[FlashRmaSt]	38120	1			T1	47		T2	9		T3	59
auto[TokenCheck0St]	13407	1			T1	20		T2	9		T3	15
auto[TokenCheck1St]	9847	1			T1	13		T2	9		T3	15
auto[TransProgSt]	425669	1			T1	226		T2	1226		T3	30
auto[PostTransSt]	14143525	1			T1	71136		T2	2764		T3	1301
auto[ScrapSt]	89149	1			T3	66		T13	4		T14	8
auto[EscalateSt]	7500619	1			T1	2712		T2	1211		T4	2817
auto[InvalidSt]	13358681	1			T2	756		T12	10250		T45	2578

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2194	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13358681	1			T2	756		T12	10250		T45	2578
EscalateSt	7500619	1			T1	2712		T2	1211		T4	2817
ScrapSt	89149	1			T3	66		T13	4		T14	8
PostTransSt	14143525	1			T1	71136		T2	2764		T3	1301
TransProgSt	425669	1			T1	226		T2	1226		T3	30
TokenCheck1St	9847	1			T1	13		T2	9		T3	15
TokenCheck0St	13407	1			T1	20		T2	9		T3	15
FlashRmaSt	38120	1			T1	47		T2	9		T3	59
TokenHashSt	49324572	1			T1	572		T2	2370		T3	164
TransCheckSt	29005	1			T1	60		T2	9		T3	15
CntProgSt	1694239	1			T1	1065		T2	1535		T3	30
CntIncrSt	37408	1			T1	77		T2	9		T3	15
ClkMuxSt	37740	1			T1	77		T2	9		T3	15
IdleSt	23517372	1			T1	84539		T2	2207		T3	2012
ResetSt	7837369	1			T1	6959		T2	1330		T3	1594
arcs[ResetSt=>IdleSt]	57535	1			T1	78		T2	15		T3	17
arcs[IdleSt=>ScrapSt]	258	1			T3	2		T13	1		T14	2
arcs[IdleSt=>ClkMuxSt]	37447	1			T1	77		T2	9		T3	15
arcs[ClkMuxSt=>CntIncrSt]	37408	1			T1	77		T2	9		T3	15
arcs[CntIncrSt=>PostTransSt]	2027	1			T1	11		T4	13		T9	9
arcs[CntIncrSt=>CntProgSt]	35322	1			T1	66		T2	9		T3	15
arcs[CntProgSt=>PostTransSt]	5286	1			T1	6		T4	6		T9	9
arcs[CntProgSt=>TransCheckSt]	29005	1			T1	60		T2	9		T3	15
arcs[TransCheckSt=>PostTransSt]	3874	1			T1	8		T4	8		T9	8
arcs[TransCheckSt=>TokenHashSt]	25037	1			T1	52		T2	9		T3	15
arcs[TokenHashSt=>PostTransSt]	10866	1			T1	32		T4	22		T9	21
arcs[TokenHashSt=>FlashRmaSt]	13454	1			T1	20		T2	9		T3	15
arcs[FlashRmaSt=>TokenCheck0St]	13407	1			T1	20		T2	9		T3	15
arcs[TokenCheck0St=>PostTransSt]	3503	1			T1	7		T4	20		T9	9
arcs[TokenCheck0St=>TokenCheck1St]	9847	1			T1	13		T2	9		T3	15
arcs[TokenCheck1St=>PostTransSt]	622	1			T1	1		T4	1		T5	2
arcs[TransProgSt=>PostTransSt]	8451	1			T1	12		T2	9		T3	15
arcs[IdleSt=>EscalateSt]	169	1			T13	10		T18	14		T46	5
arcs[ClkMuxSt=>EscalateSt]	39	1			T13	2		T18	4		T46	2
arcs[CntIncrSt=>EscalateSt]	59	1			T13	3		T47	1		T48	4
arcs[CntProgSt=>EscalateSt]	1031	1			T13	19		T14	27		T18	10
arcs[TransCheckSt=>EscalateSt]	94	1			T13	13		T14	1		T18	5
arcs[TokenHashSt=>EscalateSt]	717	1			T13	16		T14	10		T18	30
arcs[FlashRmaSt=>EscalateSt]	47	1			T13	2		T14	1		T49	1
arcs[TokenCheck0St=>EscalateSt]	57	1			T14	1		T18	2		T47	1
arcs[TokenCheck1St=>EscalateSt]	34	1			T48	1		T53	1		T54	1
arcs[TransProgSt=>EscalateSt]	740	1			T13	17		T14	18		T18	7
arcs[PostTransSt=>EscalateSt]	5588	1			T1	6		T4	6		T9	9
arcs[InvalidSt=>EscalateSt]	15208	1			T2	4		T12	54		T45	13

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7837196	1			T1	6959		T2	1330		T3	1594
auto[0]	auto[IdleSt]	23517266	1			T1	84539		T2	2207		T3	2012
auto[0]	auto[ClkMuxSt]	37714	1			T1	77		T2	9		T3	15
auto[0]	auto[CntIncrSt]	37369	1			T1	77		T2	9		T3	15
auto[0]	auto[CntProgSt]	1693551	1			T1	1065		T2	1535		T3	30
auto[0]	auto[TransCheckSt]	28944	1			T1	60		T2	9		T3	15
auto[0]	auto[TokenHashSt]	49324083	1			T1	572		T2	2370		T3	164
auto[0]	auto[FlashRmaSt]	38092	1			T1	47		T2	9		T3	59
auto[0]	auto[TokenCheck0St]	13364	1			T1	20		T2	9		T3	15
auto[0]	auto[TokenCheck1St]	9828	1			T1	13		T2	9		T3	15
auto[0]	auto[TransProgSt]	425200	1			T1	226		T2	1226		T3	30
auto[0]	auto[PostTransSt]	14140635	1			T1	71132		T2	2764		T3	1301
auto[0]	auto[ScrapSt]	89125	1			T3	66		T13	3		T14	7
auto[0]	auto[EscalateSt]	6038331	1			T1	2320		T2	917		T4	2523
auto[0]	auto[InvalidSt]	13350967	1			T2	753		T12	10223		T45	2567
auto[1]	auto[ResetSt]	173	1			T13	2		T14	6		T18	2
auto[1]	auto[IdleSt]	106	1			T13	7		T18	12		T46	3
auto[1]	auto[ClkMuxSt]	26	1			T13	1		T18	2		T46	2
auto[1]	auto[CntIncrSt]	39	1			T13	2		T47	1		T48	3
auto[1]	auto[CntProgSt]	688	1			T13	14		T14	20		T18	6
auto[1]	auto[TransCheckSt]	61	1			T13	9		T18	4		T47	1
auto[1]	auto[TokenHashSt]	489	1			T13	9		T14	9		T18	18
auto[1]	auto[FlashRmaSt]	28	1			T13	2		T14	1		T49	1
auto[1]	auto[TokenCheck0St]	43	1			T14	1		T18	2		T53	1
auto[1]	auto[TokenCheck1St]	19	1			T48	1		T230	1		T231	1
auto[1]	auto[TransProgSt]	469	1			T13	11		T14	11		T18	2
auto[1]	auto[PostTransSt]	2890	1			T1	4		T4	3		T9	3
auto[1]	auto[ScrapSt]	24	1			T13	1		T14	1		T48	1
auto[1]	auto[EscalateSt]	1462288	1			T1	392		T2	294		T4	294
auto[1]	auto[InvalidSt]	7714	1			T2	3		T12	27		T45	11

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7837202	1			T1	6959		T2	1330		T3	1594
auto[0]	auto[IdleSt]	23517254	1			T1	84539		T2	2207		T3	2012
auto[0]	auto[ClkMuxSt]	37715	1			T1	77		T2	9		T3	15
auto[0]	auto[CntIncrSt]	37369	1			T1	77		T2	9		T3	15
auto[0]	auto[CntProgSt]	1693560	1			T1	1065		T2	1535		T3	30
auto[0]	auto[TransCheckSt]	28943	1			T1	60		T2	9		T3	15
auto[0]	auto[TokenHashSt]	49324096	1			T1	572		T2	2370		T3	164
auto[0]	auto[FlashRmaSt]	38089	1			T1	47		T2	9		T3	59
auto[0]	auto[TokenCheck0St]	13372	1			T1	20		T2	9		T3	15
auto[0]	auto[TokenCheck1St]	9823	1			T1	13		T2	9		T3	15
auto[0]	auto[TransProgSt]	425164	1			T1	226		T2	1226		T3	30
auto[0]	auto[PostTransSt]	14140735	1			T1	71134		T2	2764		T3	1301
auto[0]	auto[ScrapSt]	89115	1			T3	66		T13	4		T14	7
auto[0]	auto[EscalateSt]	6061682	1			T1	2516		T2	1113		T4	2523
auto[0]	auto[InvalidSt]	13351187	1			T2	755		T12	10223		T45	2576
auto[1]	auto[ResetSt]	167	1			T13	3		T14	5		T18	1
auto[1]	auto[IdleSt]	118	1			T13	6		T18	6		T46	3
auto[1]	auto[ClkMuxSt]	25	1			T13	1		T18	2		T46	2
auto[1]	auto[CntIncrSt]	39	1			T13	1		T47	1		T48	1
auto[1]	auto[CntProgSt]	679	1			T13	13		T14	14		T18	7
auto[1]	auto[TransCheckSt]	62	1			T13	7		T14	1		T18	3
auto[1]	auto[TokenHashSt]	476	1			T13	9		T14	7		T18	20
auto[1]	auto[FlashRmaSt]	31	1			T13	2		T14	1		T102	1
auto[1]	auto[TokenCheck0St]	35	1			T18	1		T47	1		T48	1
auto[1]	auto[TokenCheck1St]	24	1			T48	1		T53	1		T54	1
auto[1]	auto[TransProgSt]	505	1			T13	7		T14	13		T18	5
auto[1]	auto[PostTransSt]	2790	1			T1	2		T4	3		T9	6
auto[1]	auto[ScrapSt]	34	1			T14	1		T18	1		T48	3
auto[1]	auto[EscalateSt]	1438937	1			T1	196		T2	98		T4	294
auto[1]	auto[InvalidSt]	7494	1			T2	1		T12	27		T45	2