Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.82	97.92	95.47	93.40	97.62	98.52	98.51	96.29

Total test records in report: 1002

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2364753506			Aug 11 07:18:21 PM PDT 24	Aug 11 07:18:23 PM PDT 24	126665810 ps
T1002	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.171261110			Aug 11 07:18:22 PM PDT 24	Aug 11 07:18:23 PM PDT 24	15214107 ps

Test location	/workspace/coverage/default/22.lc_ctrl_security_escalation.2997578107
Short name	T13
Test name
Test status
Simulation time	908903430 ps
CPU time	9.97 seconds
Started	Aug 11 07:06:42 PM PDT 24
Finished	Aug 11 07:06:53 PM PDT 24
Peak memory	225840 kb
Host	smart-caa3f0df-a96b-44a9-a5db-097f778e5416
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997578107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2997578107
Directory	/workspace/22.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.493605131
Short name	T15
Test name
Test status
Simulation time	17631970041 ps
CPU time	357.4 seconds
Started	Aug 11 07:05:33 PM PDT 24
Finished	Aug 11 07:11:30 PM PDT 24
Peak memory	280592 kb
Host	smart-b92bf248-5ec2-4880-8793-e5fe6cc27d10
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=493605131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.493605131
Directory	/workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_mubi.1481399993
Short name	T45
Test name
Test status
Simulation time	4926881009 ps
CPU time	31.87 seconds
Started	Aug 11 07:06:44 PM PDT 24
Finished	Aug 11 07:07:16 PM PDT 24
Peak memory	226012 kb
Host	smart-97cfd21f-5900-48e4-bf37-1bf80a0e5295
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481399993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1481399993
Directory	/workspace/23.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.624798828
Short name	T111
Test name
Test status
Simulation time	110152601 ps
CPU time	4.34 seconds
Started	Aug 11 07:18:20 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	218176 kb
Host	smart-0837b0d7-8f0d-4974-b9d6-902e61fa08bb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624798828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_ err.624798828
Directory	/workspace/14.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.4029560090
Short name	T95
Test name
Test status
Simulation time	472301832126 ps
CPU time	1370.55 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:30:31 PM PDT 24
Peak memory	709800 kb
Host	smart-b7f78774-3291-49e9-a0ab-9288e5a11949
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4029560090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.4029560090
Directory	/workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_cm.974302548
Short name	T52
Test name
Test status
Simulation time	891165101 ps
CPU time	42.21 seconds
Started	Aug 11 07:05:13 PM PDT 24
Finished	Aug 11 07:05:55 PM PDT 24
Peak memory	270380 kb
Host	smart-d8797f20-8d04-4b1b-8a8e-35a22da22844
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974302548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.974302548
Directory	/workspace/0.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/34.lc_ctrl_security_escalation.154721375
Short name	T48
Test name
Test status
Simulation time	312811935 ps
CPU time	9.21 seconds
Started	Aug 11 07:07:42 PM PDT 24
Finished	Aug 11 07:07:51 PM PDT 24
Peak memory	225864 kb
Host	smart-f6ff4b41-3961-44dc-92e8-e0199ed3901e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154721375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.154721375
Directory	/workspace/34.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/33.lc_ctrl_jtag_access.1524889213
Short name	T7
Test name
Test status
Simulation time	394869908 ps
CPU time	9.67 seconds
Started	Aug 11 07:07:38 PM PDT 24
Finished	Aug 11 07:07:48 PM PDT 24
Peak memory	217072 kb
Host	smart-ceac4743-da62-4c4e-841f-1fd5281bbb33
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524889213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1524889213
Directory	/workspace/33.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.270045388
Short name	T116
Test name
Test status
Simulation time	257240604 ps
CPU time	3.57 seconds
Started	Aug 11 07:18:53 PM PDT 24
Finished	Aug 11 07:18:56 PM PDT 24
Peak memory	218240 kb
Host	smart-ba8e660f-166f-4ba2-be60-d30cc611688c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270045388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.270045388
Directory	/workspace/15.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_alert_test.894047666
Short name	T93
Test name
Test status
Simulation time	76885469 ps
CPU time	1.09 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:21 PM PDT 24
Peak memory	208844 kb
Host	smart-ec7c4b22-9238-43c1-953c-8f2438dded45
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894047666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.894047666
Directory	/workspace/16.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_mux.166001032
Short name	T62
Test name
Test status
Simulation time	278314817 ps
CPU time	7.48 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:06:40 PM PDT 24
Peak memory	218040 kb
Host	smart-d2eb1bc3-aa19-47e1-ab8b-1be0a5147a8b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166001032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.166001032
Directory	/workspace/19.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.914823782
Short name	T205
Test name
Test status
Simulation time	53934655 ps
CPU time	0.9 seconds
Started	Aug 11 07:18:30 PM PDT 24
Finished	Aug 11 07:18:31 PM PDT 24
Peak memory	209832 kb
Host	smart-eb86897b-a8f5-46ab-a1a9-c2b56eee4e19
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914823782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.914823782
Directory	/workspace/19.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1951606260
Short name	T142
Test name
Test status
Simulation time	92484190 ps
CPU time	1.76 seconds
Started	Aug 11 07:18:18 PM PDT 24
Finished	Aug 11 07:18:20 PM PDT 24
Peak memory	211620 kb
Host	smart-ecc88ee1-a7d9-4e78-94ab-2c15bbb337be
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951606260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1951606260
Directory	/workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_post_trans.1117952176
Short name	T2
Test name
Test status
Simulation time	138722158 ps
CPU time	4.22 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:43 PM PDT 24
Peak memory	222668 kb
Host	smart-98b31036-9c33-43f8-8844-fc4cbf62a5f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117952176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1117952176
Directory	/workspace/6.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_stress_all.963001538
Short name	T36
Test name
Test status
Simulation time	879691926 ps
CPU time	45.98 seconds
Started	Aug 11 07:06:11 PM PDT 24
Finished	Aug 11 07:06:57 PM PDT 24
Peak memory	248440 kb
Host	smart-63d4f7e8-325e-4cc4-bf24-86db577236cc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963001538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.963001538
Directory	/workspace/12.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.lc_ctrl_security_escalation.1384724193
Short name	T18
Test name
Test status
Simulation time	2614108860 ps
CPU time	10.39 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:26 PM PDT 24
Peak memory	218260 kb
Host	smart-f023c3d1-5aaa-4ab9-a6cc-0ec02ac937f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384724193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1384724193
Directory	/workspace/14.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2347229435
Short name	T129
Test name
Test status
Simulation time	231266183 ps
CPU time	4.21 seconds
Started	Aug 11 07:18:14 PM PDT 24
Finished	Aug 11 07:18:18 PM PDT 24
Peak memory	218164 kb
Host	smart-33073dcf-8345-4b5c-b543-85fffa017690
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347229435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_ err.2347229435
Directory	/workspace/3.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all.1707229693
Short name	T96
Test name
Test status
Simulation time	7614815604 ps
CPU time	128.26 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:10:06 PM PDT 24
Peak memory	269688 kb
Host	smart-f4b757bd-c595-4a12-b226-a24408019e8f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707229693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.1707229693
Directory	/workspace/42.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1472772399
Short name	T112
Test name
Test status
Simulation time	202172360 ps
CPU time	4.05 seconds
Started	Aug 11 07:18:19 PM PDT 24
Finished	Aug 11 07:18:23 PM PDT 24
Peak memory	218212 kb
Host	smart-e2d332c8-55ca-4e80-aa99-7348e2774d82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472772399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_ err.1472772399
Directory	/workspace/9.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/5.lc_ctrl_regwen_during_op.614694391
Short name	T57
Test name
Test status
Simulation time	1008996422 ps
CPU time	23.27 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:55 PM PDT 24
Peak memory	214696 kb
Host	smart-b7b0bae5-ba9c-4600-a8bf-72c4e23cffc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614694391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.614694391
Directory	/workspace/5.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/13.lc_ctrl_errors.2387187403
Short name	T39
Test name
Test status
Simulation time	426157839 ps
CPU time	20.35 seconds
Started	Aug 11 07:06:08 PM PDT 24
Finished	Aug 11 07:06:29 PM PDT 24
Peak memory	218048 kb
Host	smart-ec599a92-0737-48f4-8b86-6f4bd074d7af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387187403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2387187403
Directory	/workspace/13.lc_ctrl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.25915245
Short name	T214
Test name
Test status
Simulation time	42343627 ps
CPU time	1.34 seconds
Started	Aug 11 07:18:21 PM PDT 24
Finished	Aug 11 07:18:22 PM PDT 24
Peak memory	209796 kb
Host	smart-c6f2a96c-8d7a-479f-aa67-352c33b0d5b5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25915245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_ same_csr_outstanding.25915245
Directory	/workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2476717909
Short name	T17
Test name
Test status
Simulation time	31150926 ps
CPU time	0.89 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:13 PM PDT 24
Peak memory	211684 kb
Host	smart-f0560ef4-30e6-44d8-9572-ad84ca95207c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476717909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c trl_volatile_unlock_smoke.2476717909
Directory	/workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3048552886
Short name	T134
Test name
Test status
Simulation time	318511852 ps
CPU time	2.76 seconds
Started	Aug 11 07:18:45 PM PDT 24
Finished	Aug 11 07:18:48 PM PDT 24
Peak memory	223196 kb
Host	smart-dd4d442f-c8de-4381-8f35-64b6d64fbc11
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048552886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg _err.3048552886
Directory	/workspace/12.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.883338421
Short name	T135
Test name
Test status
Simulation time	252248445 ps
CPU time	1.83 seconds
Started	Aug 11 07:18:40 PM PDT 24
Finished	Aug 11 07:18:42 PM PDT 24
Peak memory	218372 kb
Host	smart-2598adbd-7b7e-44cb-b6d6-bdacaa05f3f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883338421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_ err.883338421
Directory	/workspace/13.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3055666493
Short name	T130
Test name
Test status
Simulation time	353513643 ps
CPU time	2.93 seconds
Started	Aug 11 07:18:44 PM PDT 24
Finished	Aug 11 07:18:47 PM PDT 24
Peak memory	223104 kb
Host	smart-9606189b-08ca-4771-8ee4-59f09bfca3a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055666493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg _err.3055666493
Directory	/workspace/18.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.658813801
Short name	T122
Test name
Test status
Simulation time	59998604 ps
CPU time	2.18 seconds
Started	Aug 11 07:18:37 PM PDT 24
Finished	Aug 11 07:18:40 PM PDT 24
Peak memory	222780 kb
Host	smart-c3fff717-d968-4cc2-b63e-278dbefffc88
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658813801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e rr.658813801
Directory	/workspace/7.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.lc_ctrl_claim_transition_if.2912041756
Short name	T225
Test name
Test status
Simulation time	12683073 ps
CPU time	1 seconds
Started	Aug 11 07:05:13 PM PDT 24
Finished	Aug 11 07:05:15 PM PDT 24
Peak memory	208628 kb
Host	smart-89d02a41-54ac-4df0-92bd-b6b8d0eb5cf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912041756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2912041756
Directory	/workspace/1.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/2.lc_ctrl_claim_transition_if.2254993935
Short name	T224
Test name
Test status
Simulation time	12686172 ps
CPU time	1.02 seconds
Started	Aug 11 07:05:18 PM PDT 24
Finished	Aug 11 07:05:19 PM PDT 24
Peak memory	208568 kb
Host	smart-30937044-ea88-4ee4-aca5-6b475aa2fd9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254993935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2254993935
Directory	/workspace/2.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/4.lc_ctrl_claim_transition_if.3553799483
Short name	T228
Test name
Test status
Simulation time	12057351 ps
CPU time	0.85 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:05:25 PM PDT 24
Peak memory	208548 kb
Host	smart-48391323-e35b-497a-a913-11d29aa4adba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553799483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3553799483
Directory	/workspace/4.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/7.lc_ctrl_claim_transition_if.1191836478
Short name	T226
Test name
Test status
Simulation time	14386740 ps
CPU time	0.84 seconds
Started	Aug 11 07:05:41 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	208508 kb
Host	smart-c7d1c659-2414-484a-865f-53e3ed10bfb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191836478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1191836478
Directory	/workspace/7.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_errors.557496288
Short name	T4
Test name
Test status
Simulation time	3802227322 ps
CPU time	36.59 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:06:15 PM PDT 24
Peak memory	218168 kb
Host	smart-2eb09239-25ac-4948-a745-2622d836c4aa
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557496288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err ors.557496288
Directory	/workspace/6.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.749192708
Short name	T110
Test name
Test status
Simulation time	47378109 ps
CPU time	1.7 seconds
Started	Aug 11 07:18:25 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	219392 kb
Host	smart-ef5d03f6-96dd-4716-a34f-cb60f2f9edf2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749192708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.749192708
Directory	/workspace/11.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.839847495
Short name	T139
Test name
Test status
Simulation time	73397017 ps
CPU time	2.09 seconds
Started	Aug 11 07:18:21 PM PDT 24
Finished	Aug 11 07:18:23 PM PDT 24
Peak memory	222524 kb
Host	smart-1a6631f2-bff8-4447-9294-bcfece85a43c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839847495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_ err.839847495
Directory	/workspace/11.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1860567768
Short name	T128
Test name
Test status
Simulation time	65064422 ps
CPU time	2.53 seconds
Started	Aug 11 07:18:32 PM PDT 24
Finished	Aug 11 07:18:34 PM PDT 24
Peak memory	218348 kb
Host	smart-3c58bef0-762e-4219-8209-4af69b995cea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860567768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg _err.1860567768
Directory	/workspace/15.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4169641977
Short name	T141
Test name
Test status
Simulation time	446392911 ps
CPU time	4.26 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:40 PM PDT 24
Peak memory	218288 kb
Host	smart-c557ce57-eab6-411d-a333-1102a5fd0daa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169641977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_ err.4169641977
Directory	/workspace/8.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_errors.943144718
Short name	T43
Test name
Test status
Simulation time	6318641891 ps
CPU time	40.42 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:56 PM PDT 24
Peak memory	218812 kb
Host	smart-c0c55551-04fc-4364-81fb-f0671414482b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943144718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er rors.943144718
Directory	/workspace/14.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/24.lc_ctrl_prog_failure.361434249
Short name	T59
Test name
Test status
Simulation time	28465765 ps
CPU time	2.04 seconds
Started	Aug 11 07:06:45 PM PDT 24
Finished	Aug 11 07:06:47 PM PDT 24
Peak memory	218048 kb
Host	smart-a03dd3f2-d27e-4aef-851d-3ca8fb9c9e70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361434249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.361434249
Directory	/workspace/24.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3052901993
Short name	T907
Test name
Test status
Simulation time	76993536 ps
CPU time	1.03 seconds
Started	Aug 11 07:18:07 PM PDT 24
Finished	Aug 11 07:18:08 PM PDT 24
Peak memory	210036 kb
Host	smart-772c29c3-f7ed-4a7f-aa40-05b1cc711625
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052901993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin g.3052901993
Directory	/workspace/0.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.681324662
Short name	T979
Test name
Test status
Simulation time	307187962 ps
CPU time	1.94 seconds
Started	Aug 11 07:18:22 PM PDT 24
Finished	Aug 11 07:18:29 PM PDT 24
Peak memory	210032 kb
Host	smart-1a606375-5522-4478-ae3b-0b5049b8eb27
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681324662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash .681324662
Directory	/workspace/0.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4060789742
Short name	T207
Test name
Test status
Simulation time	18013397 ps
CPU time	1.24 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	218892 kb
Host	smart-f1bacb2c-ca39-4549-8644-054651596c61
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060789742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese t.4060789742
Directory	/workspace/0.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.51256669
Short name	T965
Test name
Test status
Simulation time	80927849 ps
CPU time	1.19 seconds
Started	Aug 11 07:18:01 PM PDT 24
Finished	Aug 11 07:18:02 PM PDT 24
Peak memory	218336 kb
Host	smart-788a7c4a-79e5-4807-ad65-02b6392b2c23
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51256669 -assert nopostproc +UVM_TESTNAME=l c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.51256669
Directory	/workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1039543234
Short name	T964
Test name
Test status
Simulation time	27158539 ps
CPU time	0.9 seconds
Started	Aug 11 07:18:02 PM PDT 24
Finished	Aug 11 07:18:03 PM PDT 24
Peak memory	209880 kb
Host	smart-c2799ce4-8296-47e2-9c8a-9cfecda89db5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039543234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1039543234
Directory	/workspace/0.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3644136905
Short name	T884
Test name
Test status
Simulation time	185219425 ps
CPU time	1.15 seconds
Started	Aug 11 07:18:13 PM PDT 24
Finished	Aug 11 07:18:15 PM PDT 24
Peak memory	209964 kb
Host	smart-ef350426-a516-42bb-9d78-075c4f1ae7c7
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644136905 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3644136905
Directory	/workspace/0.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1843416434
Short name	T885
Test name
Test status
Simulation time	5062199554 ps
CPU time	6.45 seconds
Started	Aug 11 07:18:18 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	210028 kb
Host	smart-c5043883-4eff-4b03-b93e-63f324b28e8e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843416434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1843416434
Directory	/workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4224820952
Short name	T933
Test name
Test status
Simulation time	959225890 ps
CPU time	23.62 seconds
Started	Aug 11 07:18:14 PM PDT 24
Finished	Aug 11 07:18:38 PM PDT 24
Peak memory	209900 kb
Host	smart-5e38652d-a6be-479e-9908-9f309691226a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224820952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4224820952
Directory	/workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.423497264
Short name	T939
Test name
Test status
Simulation time	193116450 ps
CPU time	4.84 seconds
Started	Aug 11 07:18:11 PM PDT 24
Finished	Aug 11 07:18:16 PM PDT 24
Peak memory	211672 kb
Host	smart-0f19bea3-c1bf-4c27-aa20-2c8acf3f3e6d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423497264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.423497264
Directory	/workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.9837767
Short name	T911
Test name
Test status
Simulation time	1003436657 ps
CPU time	6.26 seconds
Started	Aug 11 07:18:07 PM PDT 24
Finished	Aug 11 07:18:13 PM PDT 24
Peak memory	218296 kb
Host	smart-aea7cc9d-acc6-4906-a354-c5d0f867d646
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983776 7 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.9837767
Directory	/workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.972350988
Short name	T997
Test name
Test status
Simulation time	152306973 ps
CPU time	1.08 seconds
Started	Aug 11 07:18:05 PM PDT 24
Finished	Aug 11 07:18:07 PM PDT 24
Peak memory	210000 kb
Host	smart-932eb5da-b504-4398-a5c8-45c78ba84656
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972350988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.972350988
Directory	/workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1391738508
Short name	T996
Test name
Test status
Simulation time	27571778 ps
CPU time	1.44 seconds
Started	Aug 11 07:18:07 PM PDT 24
Finished	Aug 11 07:18:08 PM PDT 24
Peak memory	210084 kb
Host	smart-441f518f-4473-40c6-8d23-d960a7a6d3dc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391738508 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1391738508
Directory	/workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1081435515
Short name	T969
Test name
Test status
Simulation time	37365686 ps
CPU time	1.04 seconds
Started	Aug 11 07:18:25 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	209540 kb
Host	smart-d7664e15-f766-4b9c-9a87-a3631cee8a47
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081435515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _same_csr_outstanding.1081435515
Directory	/workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2887020894
Short name	T944
Test name
Test status
Simulation time	356594740 ps
CPU time	4.26 seconds
Started	Aug 11 07:18:02 PM PDT 24
Finished	Aug 11 07:18:07 PM PDT 24
Peak memory	218296 kb
Host	smart-2e680db1-ea4a-4e73-8f7a-b656eda1c5cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887020894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2887020894
Directory	/workspace/0.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2865551524
Short name	T138
Test name
Test status
Simulation time	266834148 ps
CPU time	2.08 seconds
Started	Aug 11 07:18:22 PM PDT 24
Finished	Aug 11 07:18:24 PM PDT 24
Peak memory	218184 kb
Host	smart-c3c3fa6d-b1bc-4dd0-bdf7-ad3695a8a89a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865551524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_ err.2865551524
Directory	/workspace/0.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1306973290
Short name	T1000
Test name
Test status
Simulation time	77608751 ps
CPU time	1.27 seconds
Started	Aug 11 07:18:16 PM PDT 24
Finished	Aug 11 07:18:17 PM PDT 24
Peak memory	210068 kb
Host	smart-b104a069-80c8-47ab-844e-9d35fa673104
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306973290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin g.1306973290
Directory	/workspace/1.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4255507852
Short name	T985
Test name
Test status
Simulation time	69298248 ps
CPU time	1.31 seconds
Started	Aug 11 07:18:15 PM PDT 24
Finished	Aug 11 07:18:17 PM PDT 24
Peak memory	209820 kb
Host	smart-1cba7ab8-e559-4cc6-9b2a-dad9fb71705a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255507852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas h.4255507852
Directory	/workspace/1.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2579260913
Short name	T208
Test name
Test status
Simulation time	70397815 ps
CPU time	1.07 seconds
Started	Aug 11 07:18:07 PM PDT 24
Finished	Aug 11 07:18:08 PM PDT 24
Peak memory	212140 kb
Host	smart-69c85b86-859d-4696-8d17-ead51192042a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579260913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese t.2579260913
Directory	/workspace/1.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2442322820
Short name	T957
Test name
Test status
Simulation time	323912322 ps
CPU time	1.29 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	218364 kb
Host	smart-46a7f329-828b-4647-9be1-9f3c8ae44e6c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442322820 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2442322820
Directory	/workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4230198505
Short name	T951
Test name
Test status
Simulation time	106650698 ps
CPU time	0.87 seconds
Started	Aug 11 07:18:28 PM PDT 24
Finished	Aug 11 07:18:29 PM PDT 24
Peak memory	209928 kb
Host	smart-eaf9f8db-4912-41bc-ba57-fa33c734140d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230198505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.4230198505
Directory	/workspace/1.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1929522078
Short name	T960
Test name
Test status
Simulation time	42741512 ps
CPU time	1.67 seconds
Started	Aug 11 07:18:13 PM PDT 24
Finished	Aug 11 07:18:15 PM PDT 24
Peak memory	208684 kb
Host	smart-564d98b1-ae1f-460f-97c9-abc27bafd9ff
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929522078 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1929522078
Directory	/workspace/1.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2885394184
Short name	T973
Test name
Test status
Simulation time	2415820603 ps
CPU time	16.67 seconds
Started	Aug 11 07:18:31 PM PDT 24
Finished	Aug 11 07:18:48 PM PDT 24
Peak memory	210012 kb
Host	smart-e388d2ab-e033-4261-b471-a02d785ff58d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885394184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2885394184
Directory	/workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1177277411
Short name	T897
Test name
Test status
Simulation time	972273726 ps
CPU time	9.74 seconds
Started	Aug 11 07:18:12 PM PDT 24
Finished	Aug 11 07:18:22 PM PDT 24
Peak memory	209720 kb
Host	smart-0197b7c6-dfab-4e7c-9b10-326ccbdf8a49
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177277411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1177277411
Directory	/workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2604171375
Short name	T901
Test name
Test status
Simulation time	1402948641 ps
CPU time	1.92 seconds
Started	Aug 11 07:18:04 PM PDT 24
Finished	Aug 11 07:18:06 PM PDT 24
Peak memory	211472 kb
Host	smart-329dbb50-6ab3-4b50-af15-f9d466d8b3a4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604171375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2604171375
Directory	/workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3126607493
Short name	T966
Test name
Test status
Simulation time	441452471 ps
CPU time	4.1 seconds
Started	Aug 11 07:18:17 PM PDT 24
Finished	Aug 11 07:18:21 PM PDT 24
Peak memory	225568 kb
Host	smart-1709b25c-45bc-4d8c-a402-4eac23b4c42a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312660 7493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3126607493
Directory	/workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3722422102
Short name	T977
Test name
Test status
Simulation time	197613627 ps
CPU time	1.84 seconds
Started	Aug 11 07:18:22 PM PDT 24
Finished	Aug 11 07:18:24 PM PDT 24
Peak memory	209900 kb
Host	smart-90b397aa-7eaf-43f1-a55c-51be90d7d66a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722422102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.3722422102
Directory	/workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1977964414
Short name	T941
Test name
Test status
Simulation time	88093257 ps
CPU time	1.52 seconds
Started	Aug 11 07:18:16 PM PDT 24
Finished	Aug 11 07:18:17 PM PDT 24
Peak memory	218424 kb
Host	smart-0aafdad5-75c7-45f3-a46d-222c2330a601
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977964414 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1977964414
Directory	/workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3625341072
Short name	T900
Test name
Test status
Simulation time	80887648 ps
CPU time	1.33 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	209976 kb
Host	smart-56cc6a2c-a79a-4c5f-bb37-d331b402301f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625341072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _same_csr_outstanding.3625341072
Directory	/workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1996403972
Short name	T954
Test name
Test status
Simulation time	32697355 ps
CPU time	2.03 seconds
Started	Aug 11 07:18:12 PM PDT 24
Finished	Aug 11 07:18:15 PM PDT 24
Peak memory	218360 kb
Host	smart-04c862b1-f424-47c6-833f-eb9e09ce7a38
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996403972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1996403972
Directory	/workspace/1.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2777607757
Short name	T123
Test name
Test status
Simulation time	86375804 ps
CPU time	2.18 seconds
Started	Aug 11 07:18:19 PM PDT 24
Finished	Aug 11 07:18:21 PM PDT 24
Peak memory	222632 kb
Host	smart-ccac0e62-3731-4039-bd93-2bcbafd7414c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777607757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_ err.2777607757
Directory	/workspace/1.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1370354284
Short name	T953
Test name
Test status
Simulation time	24080292 ps
CPU time	1.63 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	218176 kb
Host	smart-57a41775-47f4-4ee8-8f9c-6c55fe44e783
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370354284 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1370354284
Directory	/workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3588844426
Short name	T209
Test name
Test status
Simulation time	25540883 ps
CPU time	0.87 seconds
Started	Aug 11 07:18:20 PM PDT 24
Finished	Aug 11 07:18:21 PM PDT 24
Peak memory	210032 kb
Host	smart-164eff30-f57c-4e96-b340-3c823cc0e092
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588844426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3588844426
Directory	/workspace/10.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2191580133
Short name	T947
Test name
Test status
Simulation time	380227508 ps
CPU time	2.5 seconds
Started	Aug 11 07:18:18 PM PDT 24
Finished	Aug 11 07:18:21 PM PDT 24
Peak memory	218336 kb
Host	smart-b9e35b83-ba45-4535-b0be-ddfa9251e070
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191580133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2191580133
Directory	/workspace/10.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3375933546
Short name	T119
Test name
Test status
Simulation time	265247683 ps
CPU time	2.13 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:38 PM PDT 24
Peak memory	222824 kb
Host	smart-6755e93b-d941-4353-a173-3674fd5224c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375933546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg _err.3375933546
Directory	/workspace/10.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1129747443
Short name	T127
Test name
Test status
Simulation time	119274348 ps
CPU time	1.11 seconds
Started	Aug 11 07:18:34 PM PDT 24
Finished	Aug 11 07:18:36 PM PDT 24
Peak memory	216880 kb
Host	smart-67910b86-44a1-445b-86a1-2b7231c11339
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129747443 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1129747443
Directory	/workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3125514346
Short name	T158
Test name
Test status
Simulation time	191317276 ps
CPU time	0.78 seconds
Started	Aug 11 07:18:28 PM PDT 24
Finished	Aug 11 07:18:29 PM PDT 24
Peak memory	209904 kb
Host	smart-f4708db1-94b8-48b5-8cba-9dd65748b2d5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125514346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3125514346
Directory	/workspace/11.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2198757504
Short name	T923
Test name
Test status
Simulation time	55973104 ps
CPU time	0.96 seconds
Started	Aug 11 07:18:45 PM PDT 24
Finished	Aug 11 07:18:46 PM PDT 24
Peak memory	210044 kb
Host	smart-00c17996-03b4-452b-8330-4e4232b5015e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198757504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_same_csr_outstanding.2198757504
Directory	/workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.322371404
Short name	T982
Test name
Test status
Simulation time	165261132 ps
CPU time	2.2 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	220548 kb
Host	smart-cf340e1b-a37e-484d-8724-ebebe89f0abe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322371404 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.322371404
Directory	/workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1706042317
Short name	T937
Test name
Test status
Simulation time	49837401 ps
CPU time	1.01 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:24 PM PDT 24
Peak memory	210012 kb
Host	smart-ce17c2e6-35e1-4d82-b47d-b18ec25a21f2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706042317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1706042317
Directory	/workspace/12.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2465449310
Short name	T943
Test name
Test status
Simulation time	67771569 ps
CPU time	1.86 seconds
Started	Aug 11 07:18:37 PM PDT 24
Finished	Aug 11 07:18:39 PM PDT 24
Peak memory	209996 kb
Host	smart-4b87cb7c-8878-40cf-8b94-516bd2b56f00
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465449310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_same_csr_outstanding.2465449310
Directory	/workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2292566289
Short name	T955
Test name
Test status
Simulation time	37612628 ps
CPU time	1.63 seconds
Started	Aug 11 07:18:41 PM PDT 24
Finished	Aug 11 07:18:43 PM PDT 24
Peak memory	218244 kb
Host	smart-654783fe-a81d-463d-85eb-1a2edccf8cdc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292566289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2292566289
Directory	/workspace/12.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3561936696
Short name	T981
Test name
Test status
Simulation time	50658800 ps
CPU time	1.16 seconds
Started	Aug 11 07:18:52 PM PDT 24
Finished	Aug 11 07:18:54 PM PDT 24
Peak memory	218360 kb
Host	smart-828e2ea6-c029-4388-8e3a-5f4cf6f4741e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561936696 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3561936696
Directory	/workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2105179408
Short name	T211
Test name
Test status
Simulation time	32686316 ps
CPU time	0.94 seconds
Started	Aug 11 07:18:48 PM PDT 24
Finished	Aug 11 07:18:49 PM PDT 24
Peak memory	209872 kb
Host	smart-791406c3-a883-4e84-a831-47908057eaf7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105179408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2105179408
Directory	/workspace/13.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2368421839
Short name	T904
Test name
Test status
Simulation time	49771632 ps
CPU time	1.49 seconds
Started	Aug 11 07:18:49 PM PDT 24
Finished	Aug 11 07:18:50 PM PDT 24
Peak memory	212128 kb
Host	smart-82a99147-0436-4bf1-b12d-0b68c53ca715
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368421839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_same_csr_outstanding.2368421839
Directory	/workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.107567039
Short name	T126
Test name
Test status
Simulation time	92738814 ps
CPU time	2.95 seconds
Started	Aug 11 07:18:30 PM PDT 24
Finished	Aug 11 07:18:33 PM PDT 24
Peak memory	216848 kb
Host	smart-c4356c94-be13-498f-8255-e07875b689a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107567039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.107567039
Directory	/workspace/13.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2136787807
Short name	T177
Test name
Test status
Simulation time	83938223 ps
CPU time	1.08 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:36 PM PDT 24
Peak memory	218380 kb
Host	smart-f7db8011-adde-4fa5-b6f7-6c0b1631b3cf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136787807 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2136787807
Directory	/workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.28110918
Short name	T949
Test name
Test status
Simulation time	13060893 ps
CPU time	1.04 seconds
Started	Aug 11 07:18:17 PM PDT 24
Finished	Aug 11 07:18:18 PM PDT 24
Peak memory	210072 kb
Host	smart-38c771b4-7888-4d06-98bd-6aae47296ff6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28110918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.28110918
Directory	/workspace/14.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.591383635
Short name	T956
Test name
Test status
Simulation time	17735992 ps
CPU time	0.97 seconds
Started	Aug 11 07:18:25 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	218280 kb
Host	smart-9895310e-e424-4b30-bc83-1de7ff2cac87
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591383635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _same_csr_outstanding.591383635
Directory	/workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.396301451
Short name	T991
Test name
Test status
Simulation time	2081641179 ps
CPU time	4.43 seconds
Started	Aug 11 07:18:15 PM PDT 24
Finished	Aug 11 07:18:19 PM PDT 24
Peak memory	218240 kb
Host	smart-4e2d76f2-f0f9-4620-9bb7-2cacf10a62df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396301451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.396301451
Directory	/workspace/14.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1469093756
Short name	T912
Test name
Test status
Simulation time	43941607 ps
CPU time	1.86 seconds
Started	Aug 11 07:18:34 PM PDT 24
Finished	Aug 11 07:18:36 PM PDT 24
Peak memory	225560 kb
Host	smart-2e362095-cfca-49ef-a770-c144f2af51c5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469093756 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1469093756
Directory	/workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1744559055
Short name	T199
Test name
Test status
Simulation time	14969205 ps
CPU time	1.09 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	209988 kb
Host	smart-b25c1e56-3fe8-47a3-bcdc-227fb4be00c5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744559055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1744559055
Directory	/workspace/15.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3297493515
Short name	T218
Test name
Test status
Simulation time	15062154 ps
CPU time	0.97 seconds
Started	Aug 11 07:18:25 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	210408 kb
Host	smart-9456bc5c-34ba-4be4-9504-98b826845520
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297493515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr l_same_csr_outstanding.3297493515
Directory	/workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1203264883
Short name	T132
Test name
Test status
Simulation time	78714355 ps
CPU time	1.04 seconds
Started	Aug 11 07:18:27 PM PDT 24
Finished	Aug 11 07:18:28 PM PDT 24
Peak memory	221344 kb
Host	smart-fbcf674c-e911-4b10-9ce2-c2b14b7e485d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203264883 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1203264883
Directory	/workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3846267710
Short name	T200
Test name
Test status
Simulation time	35645838 ps
CPU time	0.85 seconds
Started	Aug 11 07:18:37 PM PDT 24
Finished	Aug 11 07:18:38 PM PDT 24
Peak memory	209908 kb
Host	smart-5aa3c28e-02a3-4c6d-bcbf-92a6663aded4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846267710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3846267710
Directory	/workspace/16.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2302403368
Short name	T948
Test name
Test status
Simulation time	394549608 ps
CPU time	1.08 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:24 PM PDT 24
Peak memory	210004 kb
Host	smart-7b39e88f-5202-4db0-a9f4-bc9d035292bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302403368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.2302403368
Directory	/workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1768142860
Short name	T925
Test name
Test status
Simulation time	127361283 ps
CPU time	3.24 seconds
Started	Aug 11 07:18:27 PM PDT 24
Finished	Aug 11 07:18:31 PM PDT 24
Peak memory	218976 kb
Host	smart-0d0e4271-69fb-437b-8a96-af57bb859943
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768142860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1768142860
Directory	/workspace/16.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2181888422
Short name	T113
Test name
Test status
Simulation time	103074684 ps
CPU time	1.88 seconds
Started	Aug 11 07:18:31 PM PDT 24
Finished	Aug 11 07:18:33 PM PDT 24
Peak memory	222636 kb
Host	smart-dbbf3ba4-daa8-4136-9a76-4ab2d8506471
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181888422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg _err.2181888422
Directory	/workspace/16.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2610739763
Short name	T919
Test name
Test status
Simulation time	369221133 ps
CPU time	1.54 seconds
Started	Aug 11 07:18:32 PM PDT 24
Finished	Aug 11 07:18:34 PM PDT 24
Peak memory	218504 kb
Host	smart-422bb401-e833-43f0-8ea8-c6b085ce1202
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610739763 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2610739763
Directory	/workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2879538130
Short name	T961
Test name
Test status
Simulation time	11446283 ps
CPU time	0.86 seconds
Started	Aug 11 07:18:40 PM PDT 24
Finished	Aug 11 07:18:41 PM PDT 24
Peak memory	209768 kb
Host	smart-1b490f44-e83f-4799-aa2d-95efbed81ffd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879538130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2879538130
Directory	/workspace/17.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.355555658
Short name	T157
Test name
Test status
Simulation time	116605263 ps
CPU time	1.38 seconds
Started	Aug 11 07:18:30 PM PDT 24
Finished	Aug 11 07:18:31 PM PDT 24
Peak memory	209932 kb
Host	smart-0efc794e-f06f-4ccc-b91f-00c1152c934a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355555658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _same_csr_outstanding.355555658
Directory	/workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2958500549
Short name	T986
Test name
Test status
Simulation time	212771733 ps
CPU time	1.71 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:37 PM PDT 24
Peak memory	219220 kb
Host	smart-66b3a01c-5508-4ad8-ad9d-b3cf5e8082fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958500549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2958500549
Directory	/workspace/17.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1933629021
Short name	T136
Test name
Test status
Simulation time	81555296 ps
CPU time	1.83 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	221240 kb
Host	smart-7450f210-c322-4d1d-adcb-05023529ead7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933629021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg _err.1933629021
Directory	/workspace/17.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1413620192
Short name	T115
Test name
Test status
Simulation time	28571688 ps
CPU time	1.38 seconds
Started	Aug 11 07:18:45 PM PDT 24
Finished	Aug 11 07:18:47 PM PDT 24
Peak memory	220044 kb
Host	smart-dfa9c284-2ebd-48fa-b6bf-41e987715bc6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413620192 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1413620192
Directory	/workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2569220893
Short name	T159
Test name
Test status
Simulation time	27379410 ps
CPU time	0.91 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:36 PM PDT 24
Peak memory	209892 kb
Host	smart-22b3d34f-6548-4523-a175-7ce65027beb0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569220893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2569220893
Directory	/workspace/18.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2419217849
Short name	T902
Test name
Test status
Simulation time	30234428 ps
CPU time	1.51 seconds
Started	Aug 11 07:18:45 PM PDT 24
Finished	Aug 11 07:18:46 PM PDT 24
Peak memory	210040 kb
Host	smart-081f0e0c-7217-4f91-8dec-b27ed0ea6e59
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419217849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_same_csr_outstanding.2419217849
Directory	/workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1818151185
Short name	T932
Test name
Test status
Simulation time	67096774 ps
CPU time	1.95 seconds
Started	Aug 11 07:18:37 PM PDT 24
Finished	Aug 11 07:18:39 PM PDT 24
Peak memory	219480 kb
Host	smart-0debc6b2-2fa6-4d8e-8051-9171ac9aeac5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818151185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1818151185
Directory	/workspace/18.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1924260638
Short name	T989
Test name
Test status
Simulation time	24748227 ps
CPU time	1.56 seconds
Started	Aug 11 07:18:44 PM PDT 24
Finished	Aug 11 07:18:46 PM PDT 24
Peak memory	222860 kb
Host	smart-b9f42101-ddb7-4680-b5c4-57770be64d69
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924260638 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1924260638
Directory	/workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2377875030
Short name	T215
Test name
Test status
Simulation time	31565974 ps
CPU time	1.07 seconds
Started	Aug 11 07:18:25 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	209800 kb
Host	smart-52e827ea-9ff0-4bc2-b6ae-4f154f3a837f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377875030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr l_same_csr_outstanding.2377875030
Directory	/workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4165319174
Short name	T976
Test name
Test status
Simulation time	123100932 ps
CPU time	4.69 seconds
Started	Aug 11 07:18:33 PM PDT 24
Finished	Aug 11 07:18:38 PM PDT 24
Peak memory	218272 kb
Host	smart-b5cc1f6b-18c8-4490-b5a1-8ad160f427e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165319174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4165319174
Directory	/workspace/19.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.54920302
Short name	T140
Test name
Test status
Simulation time	196086237 ps
CPU time	2.15 seconds
Started	Aug 11 07:18:27 PM PDT 24
Finished	Aug 11 07:18:29 PM PDT 24
Peak memory	222216 kb
Host	smart-142ad106-8edf-4885-a5ed-6b4d3cc7f21d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54920302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_e rr.54920302
Directory	/workspace/19.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2353487030
Short name	T201
Test name
Test status
Simulation time	26015356 ps
CPU time	1.4 seconds
Started	Aug 11 07:18:25 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	210164 kb
Host	smart-c87a12a8-cef4-456b-a22c-e276e043b8ce
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353487030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin g.2353487030
Directory	/workspace/2.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2540325434
Short name	T924
Test name
Test status
Simulation time	143216683 ps
CPU time	1.72 seconds
Started	Aug 11 07:18:52 PM PDT 24
Finished	Aug 11 07:18:54 PM PDT 24
Peak memory	209856 kb
Host	smart-0bcfa038-fd62-4e6e-824c-2f1af432c1c7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540325434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas h.2540325434
Directory	/workspace/2.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1112045592
Short name	T883
Test name
Test status
Simulation time	42380875 ps
CPU time	0.94 seconds
Started	Aug 11 07:18:39 PM PDT 24
Finished	Aug 11 07:18:40 PM PDT 24
Peak memory	210396 kb
Host	smart-a90be544-a157-4f60-b4ca-d29e961f5dcb
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112045592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese t.1112045592
Directory	/workspace/2.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4093952518
Short name	T114
Test name
Test status
Simulation time	19758101 ps
CPU time	1.37 seconds
Started	Aug 11 07:18:00 PM PDT 24
Finished	Aug 11 07:18:01 PM PDT 24
Peak memory	220488 kb
Host	smart-8d432790-8259-4778-a9b9-fa5f06d8e1f4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093952518 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.4093952518
Directory	/workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1913530050
Short name	T212
Test name
Test status
Simulation time	11629515 ps
CPU time	0.88 seconds
Started	Aug 11 07:18:36 PM PDT 24
Finished	Aug 11 07:18:37 PM PDT 24
Peak memory	210076 kb
Host	smart-3481da24-dc59-4915-922b-9aa0f6b54ed7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913530050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1913530050
Directory	/workspace/2.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3676444323
Short name	T894
Test name
Test status
Simulation time	81059069 ps
CPU time	0.92 seconds
Started	Aug 11 07:18:12 PM PDT 24
Finished	Aug 11 07:18:13 PM PDT 24
Peak memory	209928 kb
Host	smart-d64457b1-f154-4bf5-935e-e94c687cd3e0
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676444323 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3676444323
Directory	/workspace/2.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4124225662
Short name	T992
Test name
Test status
Simulation time	6459456674 ps
CPU time	5.62 seconds
Started	Aug 11 07:18:37 PM PDT 24
Finished	Aug 11 07:18:43 PM PDT 24
Peak memory	209908 kb
Host	smart-26b13562-6839-4eaf-bd75-bdb878231e0f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124225662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4124225662
Directory	/workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.462524068
Short name	T946
Test name
Test status
Simulation time	702253333 ps
CPU time	17.36 seconds
Started	Aug 11 07:18:04 PM PDT 24
Finished	Aug 11 07:18:21 PM PDT 24
Peak memory	209892 kb
Host	smart-10b51977-57cc-4372-9c5e-241970dd61e5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462524068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.462524068
Directory	/workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3575537353
Short name	T950
Test name
Test status
Simulation time	250178494 ps
CPU time	3.62 seconds
Started	Aug 11 07:18:05 PM PDT 24
Finished	Aug 11 07:18:09 PM PDT 24
Peak memory	211520 kb
Host	smart-b2b99337-dce3-4e87-a80b-9abba951d91c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575537353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3575537353
Directory	/workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.945461372
Short name	T974
Test name
Test status
Simulation time	58913538 ps
CPU time	1.79 seconds
Started	Aug 11 07:18:12 PM PDT 24
Finished	Aug 11 07:18:14 PM PDT 24
Peak memory	219636 kb
Host	smart-b1726254-752c-47d8-bfbe-5aba36f1abf1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945461 372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.945461372
Directory	/workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1009874154
Short name	T952
Test name
Test status
Simulation time	92588073 ps
CPU time	1.55 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	209992 kb
Host	smart-fe0ff4be-21cd-4d47-baad-311aa9e707fc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009874154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.1009874154
Directory	/workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4083697152
Short name	T999
Test name
Test status
Simulation time	78765973 ps
CPU time	1.2 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:24 PM PDT 24
Peak memory	210092 kb
Host	smart-4435ec22-307b-4f00-9a3c-2f903a1e07e1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083697152 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4083697152
Directory	/workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3612591733
Short name	T984
Test name
Test status
Simulation time	295669064 ps
CPU time	1.37 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	210048 kb
Host	smart-25e4254c-ef82-494d-8405-d84ae8b01228
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612591733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _same_csr_outstanding.3612591733
Directory	/workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3222596113
Short name	T913
Test name
Test status
Simulation time	147310942 ps
CPU time	2.32 seconds
Started	Aug 11 07:18:21 PM PDT 24
Finished	Aug 11 07:18:24 PM PDT 24
Peak memory	218244 kb
Host	smart-ef23bf20-f09b-42fe-a57c-3fa8fcec49f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222596113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3222596113
Directory	/workspace/2.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2072009877
Short name	T137
Test name
Test status
Simulation time	217809381 ps
CPU time	1.97 seconds
Started	Aug 11 07:18:02 PM PDT 24
Finished	Aug 11 07:18:04 PM PDT 24
Peak memory	222792 kb
Host	smart-c921fb25-e7f4-4781-a6ff-dd01c40da680
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072009877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_ err.2072009877
Directory	/workspace/2.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3899103285
Short name	T204
Test name
Test status
Simulation time	28673048 ps
CPU time	1.09 seconds
Started	Aug 11 07:18:09 PM PDT 24
Finished	Aug 11 07:18:11 PM PDT 24
Peak memory	210044 kb
Host	smart-c0eccd91-9e06-40e4-a639-3c75161b2cf4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899103285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin g.3899103285
Directory	/workspace/3.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.435224774
Short name	T160
Test name
Test status
Simulation time	162608310 ps
CPU time	1.89 seconds
Started	Aug 11 07:18:14 PM PDT 24
Finished	Aug 11 07:18:16 PM PDT 24
Peak memory	209292 kb
Host	smart-afb405a4-ac72-484e-a397-d11f5488e6a8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435224774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash .435224774
Directory	/workspace/3.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2831307278
Short name	T889
Test name
Test status
Simulation time	34699750 ps
CPU time	0.89 seconds
Started	Aug 11 07:18:02 PM PDT 24
Finished	Aug 11 07:18:03 PM PDT 24
Peak memory	210448 kb
Host	smart-5efc5f1e-6e15-4fc1-93d3-8a1277e6190a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831307278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese t.2831307278
Directory	/workspace/3.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.75716472
Short name	T921
Test name
Test status
Simulation time	51666358 ps
CPU time	1.2 seconds
Started	Aug 11 07:18:22 PM PDT 24
Finished	Aug 11 07:18:23 PM PDT 24
Peak memory	218400 kb
Host	smart-daa5dff5-e499-4d76-957f-3703659035e9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75716472 -assert nopostproc +UVM_TESTNAME=l c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.75716472
Directory	/workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1979437387
Short name	T202
Test name
Test status
Simulation time	16467156 ps
CPU time	1.13 seconds
Started	Aug 11 07:18:08 PM PDT 24
Finished	Aug 11 07:18:09 PM PDT 24
Peak memory	210088 kb
Host	smart-553f9863-1681-42bc-84d0-c81edec92f87
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979437387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1979437387
Directory	/workspace/3.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3678192375
Short name	T928
Test name
Test status
Simulation time	91384919 ps
CPU time	1.21 seconds
Started	Aug 11 07:17:58 PM PDT 24
Finished	Aug 11 07:18:00 PM PDT 24
Peak memory	209852 kb
Host	smart-9f6e4888-c038-4693-984b-d1e283a028b1
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678192375 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3678192375
Directory	/workspace/3.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1189345526
Short name	T893
Test name
Test status
Simulation time	927596841 ps
CPU time	2.92 seconds
Started	Aug 11 07:18:10 PM PDT 24
Finished	Aug 11 07:18:13 PM PDT 24
Peak memory	209700 kb
Host	smart-43e45d6c-55a6-4ee8-9dcc-33a37d8faa0e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189345526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1189345526
Directory	/workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3233855968
Short name	T886
Test name
Test status
Simulation time	422431830 ps
CPU time	5.78 seconds
Started	Aug 11 07:18:29 PM PDT 24
Finished	Aug 11 07:18:35 PM PDT 24
Peak memory	209336 kb
Host	smart-64713960-c099-48c6-849c-d75455462510
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233855968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3233855968
Directory	/workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2214252618
Short name	T967
Test name
Test status
Simulation time	227291466 ps
CPU time	1.72 seconds
Started	Aug 11 07:18:21 PM PDT 24
Finished	Aug 11 07:18:23 PM PDT 24
Peak memory	219328 kb
Host	smart-6a202e9e-3aed-48a9-918e-24bf4e222d01
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221425 2618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2214252618
Directory	/workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1840489189
Short name	T888
Test name
Test status
Simulation time	58112141 ps
CPU time	2.11 seconds
Started	Aug 11 07:18:10 PM PDT 24
Finished	Aug 11 07:18:12 PM PDT 24
Peak memory	209220 kb
Host	smart-3d845e2e-db3c-429e-8fc5-a61a5d494a60
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840489189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.1840489189
Directory	/workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2971942210
Short name	T117
Test name
Test status
Simulation time	21610515 ps
CPU time	1.43 seconds
Started	Aug 11 07:18:14 PM PDT 24
Finished	Aug 11 07:18:15 PM PDT 24
Peak memory	212176 kb
Host	smart-16f77a67-587d-41cc-abd8-b985a33d7106
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971942210 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2971942210
Directory	/workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4286765312
Short name	T216
Test name
Test status
Simulation time	51083493 ps
CPU time	1.39 seconds
Started	Aug 11 07:18:07 PM PDT 24
Finished	Aug 11 07:18:08 PM PDT 24
Peak memory	209972 kb
Host	smart-570ca199-23e5-4908-8e26-f68c9f4c9501
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286765312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _same_csr_outstanding.4286765312
Directory	/workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2949989777
Short name	T914
Test name
Test status
Simulation time	49935375 ps
CPU time	3.25 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:27 PM PDT 24
Peak memory	219356 kb
Host	smart-6339d40e-689b-4c4b-971f-62549019b6a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949989777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2949989777
Directory	/workspace/3.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2195706620
Short name	T210
Test name
Test status
Simulation time	189219520 ps
CPU time	1.32 seconds
Started	Aug 11 07:18:12 PM PDT 24
Finished	Aug 11 07:18:13 PM PDT 24
Peak memory	210064 kb
Host	smart-6efdd84f-8c4a-47ad-a4b9-fcdb9d2bdae6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195706620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin g.2195706620
Directory	/workspace/4.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1987674468
Short name	T121
Test name
Test status
Simulation time	181956979 ps
CPU time	1.31 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	209996 kb
Host	smart-853661ba-f082-48ad-9559-8f59631d3eb3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987674468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas h.1987674468
Directory	/workspace/4.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.637023011
Short name	T908
Test name
Test status
Simulation time	15080687 ps
CPU time	0.88 seconds
Started	Aug 11 07:18:19 PM PDT 24
Finished	Aug 11 07:18:20 PM PDT 24
Peak memory	210452 kb
Host	smart-2f5d113f-4afc-4ad7-a5ff-8d6c2a467cf1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637023011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset .637023011
Directory	/workspace/4.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3475821565
Short name	T931
Test name
Test status
Simulation time	75821936 ps
CPU time	1.44 seconds
Started	Aug 11 07:18:21 PM PDT 24
Finished	Aug 11 07:18:23 PM PDT 24
Peak memory	220360 kb
Host	smart-71ef7f16-7bdc-4561-ac09-bea3568b3f25
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475821565 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3475821565
Directory	/workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.598121607
Short name	T903
Test name
Test status
Simulation time	36897181 ps
CPU time	0.83 seconds
Started	Aug 11 07:18:17 PM PDT 24
Finished	Aug 11 07:18:18 PM PDT 24
Peak memory	209884 kb
Host	smart-6bb3ac75-e366-4676-9890-fa7caf799b5d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598121607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.598121607
Directory	/workspace/4.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.657012133
Short name	T926
Test name
Test status
Simulation time	88218371 ps
CPU time	2.1 seconds
Started	Aug 11 07:18:18 PM PDT 24
Finished	Aug 11 07:18:20 PM PDT 24
Peak memory	208652 kb
Host	smart-21af0094-0dee-4320-9b2a-db9ddc84dfb6
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657012133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.lc_ctrl_jtag_alert_test.657012133
Directory	/workspace/4.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1634700598
Short name	T942
Test name
Test status
Simulation time	1390092126 ps
CPU time	8.74 seconds
Started	Aug 11 07:18:30 PM PDT 24
Finished	Aug 11 07:18:39 PM PDT 24
Peak memory	209784 kb
Host	smart-31f98b38-c04e-4724-a24d-127d891f0995
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634700598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1634700598
Directory	/workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2863049330
Short name	T915
Test name
Test status
Simulation time	1937321474 ps
CPU time	9.92 seconds
Started	Aug 11 07:18:17 PM PDT 24
Finished	Aug 11 07:18:27 PM PDT 24
Peak memory	209208 kb
Host	smart-b68de66c-ff46-4b98-acb0-d8d90e35da6b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863049330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2863049330
Directory	/workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1850719250
Short name	T887
Test name
Test status
Simulation time	556462657 ps
CPU time	6.61 seconds
Started	Aug 11 07:18:12 PM PDT 24
Finished	Aug 11 07:18:19 PM PDT 24
Peak memory	211512 kb
Host	smart-0725aa80-9e4e-4bf3-8df0-e06c317832e0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850719250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1850719250
Directory	/workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.40436295
Short name	T899
Test name
Test status
Simulation time	105753617 ps
CPU time	2.18 seconds
Started	Aug 11 07:18:16 PM PDT 24
Finished	Aug 11 07:18:18 PM PDT 24
Peak memory	218328 kb
Host	smart-6fe5220f-23f1-46e7-9a3e-961fdc3c7379
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404362 95 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.40436295
Directory	/workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2333411516
Short name	T927
Test name
Test status
Simulation time	192961068 ps
CPU time	1.18 seconds
Started	Aug 11 07:18:30 PM PDT 24
Finished	Aug 11 07:18:32 PM PDT 24
Peak memory	209896 kb
Host	smart-6e187ad8-389b-4f7d-b29c-7922b99f4181
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333411516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.2333411516
Directory	/workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1006942007
Short name	T962
Test name
Test status
Simulation time	119395265 ps
CPU time	0.96 seconds
Started	Aug 11 07:18:18 PM PDT 24
Finished	Aug 11 07:18:19 PM PDT 24
Peak memory	210008 kb
Host	smart-f9517967-6097-4cf0-a144-26c3a9d0897b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006942007 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1006942007
Directory	/workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1568921477
Short name	T980
Test name
Test status
Simulation time	281134696 ps
CPU time	1.3 seconds
Started	Aug 11 07:18:16 PM PDT 24
Finished	Aug 11 07:18:18 PM PDT 24
Peak memory	210088 kb
Host	smart-34a41155-6f80-4855-8267-6da64346006a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568921477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _same_csr_outstanding.1568921477
Directory	/workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1051738357
Short name	T958
Test name
Test status
Simulation time	121711808 ps
CPU time	1.56 seconds
Started	Aug 11 07:18:13 PM PDT 24
Finished	Aug 11 07:18:15 PM PDT 24
Peak memory	218384 kb
Host	smart-c59f8a47-959f-484b-811f-f87360662abe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051738357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1051738357
Directory	/workspace/4.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.914325186
Short name	T131
Test name
Test status
Simulation time	88806568 ps
CPU time	2.61 seconds
Started	Aug 11 07:18:00 PM PDT 24
Finished	Aug 11 07:18:03 PM PDT 24
Peak memory	218324 kb
Host	smart-d7ba4ba1-9470-4f6f-9700-e67afcda4a44
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914325186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e rr.914325186
Directory	/workspace/4.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1562385217
Short name	T935
Test name
Test status
Simulation time	13486052 ps
CPU time	0.97 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:36 PM PDT 24
Peak memory	218332 kb
Host	smart-aabff9aa-ea31-4e3e-869f-6be5f2d5abf1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562385217 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1562385217
Directory	/workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1464294783
Short name	T203
Test name
Test status
Simulation time	17938563 ps
CPU time	1.09 seconds
Started	Aug 11 07:18:14 PM PDT 24
Finished	Aug 11 07:18:15 PM PDT 24
Peak memory	209724 kb
Host	smart-b5ba1c58-7aa0-483a-8e3f-8f5c1d96ae95
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464294783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1464294783
Directory	/workspace/5.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1833471786
Short name	T892
Test name
Test status
Simulation time	29283242 ps
CPU time	1.34 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	209948 kb
Host	smart-0e4aa398-bbea-47e4-98ea-2f6e19c1f23c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833471786 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1833471786
Directory	/workspace/5.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2827018323
Short name	T909
Test name
Test status
Simulation time	739106508 ps
CPU time	9.87 seconds
Started	Aug 11 07:18:22 PM PDT 24
Finished	Aug 11 07:18:37 PM PDT 24
Peak memory	209796 kb
Host	smart-7e181ab0-b445-414f-ba1f-555e950cf3b8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827018323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2827018323
Directory	/workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1446964998
Short name	T938
Test name
Test status
Simulation time	1461318242 ps
CPU time	4.78 seconds
Started	Aug 11 07:18:15 PM PDT 24
Finished	Aug 11 07:18:20 PM PDT 24
Peak memory	209836 kb
Host	smart-d25788c5-0f8a-4cb4-9714-f6b4061c1905
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446964998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1446964998
Directory	/workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2197098002
Short name	T988
Test name
Test status
Simulation time	187328029 ps
CPU time	1.24 seconds
Started	Aug 11 07:18:13 PM PDT 24
Finished	Aug 11 07:18:14 PM PDT 24
Peak memory	211408 kb
Host	smart-c3d9fa98-2176-4272-82d6-c835d2b3e24a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197098002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2197098002
Directory	/workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1915605086
Short name	T971
Test name
Test status
Simulation time	71973867 ps
CPU time	1.68 seconds
Started	Aug 11 07:18:02 PM PDT 24
Finished	Aug 11 07:18:03 PM PDT 24
Peak memory	218528 kb
Host	smart-b1d7286e-4f9f-4a48-92d6-9d79b44cfcb2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191560 5086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1915605086
Directory	/workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1081035659
Short name	T990
Test name
Test status
Simulation time	67870110 ps
CPU time	1.38 seconds
Started	Aug 11 07:18:20 PM PDT 24
Finished	Aug 11 07:18:21 PM PDT 24
Peak memory	210012 kb
Host	smart-6ca018c1-8524-4efc-91c4-3356b26fbe4e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081035659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.1081035659
Directory	/workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.171261110
Short name	T1002
Test name
Test status
Simulation time	15214107 ps
CPU time	1.17 seconds
Started	Aug 11 07:18:22 PM PDT 24
Finished	Aug 11 07:18:23 PM PDT 24
Peak memory	210072 kb
Host	smart-ec17fb50-848a-4416-8959-517f0c710a84
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171261110 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.171261110
Directory	/workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2664092645
Short name	T995
Test name
Test status
Simulation time	29512474 ps
CPU time	1.54 seconds
Started	Aug 11 07:18:31 PM PDT 24
Finished	Aug 11 07:18:33 PM PDT 24
Peak memory	210028 kb
Host	smart-d2abd4de-ad53-4748-9cc7-1ddee601001b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664092645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _same_csr_outstanding.2664092645
Directory	/workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.664102432
Short name	T936
Test name
Test status
Simulation time	136249263 ps
CPU time	2.1 seconds
Started	Aug 11 07:18:13 PM PDT 24
Finished	Aug 11 07:18:15 PM PDT 24
Peak memory	218252 kb
Host	smart-6cf3b1a3-f7d5-4ded-aad6-0ae760d44ab7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664102432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.664102432
Directory	/workspace/5.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2499963178
Short name	T229
Test name
Test status
Simulation time	61180326 ps
CPU time	2.63 seconds
Started	Aug 11 07:18:29 PM PDT 24
Finished	Aug 11 07:18:31 PM PDT 24
Peak memory	218268 kb
Host	smart-9a2a6190-2fb4-4f11-8d30-3cd1410aaddb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499963178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_ err.2499963178
Directory	/workspace/5.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2878593590
Short name	T972
Test name
Test status
Simulation time	43363956 ps
CPU time	1.1 seconds
Started	Aug 11 07:18:20 PM PDT 24
Finished	Aug 11 07:18:22 PM PDT 24
Peak memory	220124 kb
Host	smart-f842fded-6f43-4929-9e01-87d15a68ca3e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878593590 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2878593590
Directory	/workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1860808133
Short name	T978
Test name
Test status
Simulation time	54590179 ps
CPU time	0.87 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:24 PM PDT 24
Peak memory	210024 kb
Host	smart-2db38df8-54f9-4615-b86c-0466544893bb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860808133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1860808133
Directory	/workspace/6.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1758473838
Short name	T916
Test name
Test status
Simulation time	50995121 ps
CPU time	1.83 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	208660 kb
Host	smart-8111147b-d759-4cd4-acac-3534a3dbc92c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758473838 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1758473838
Directory	/workspace/6.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1769896385
Short name	T993
Test name
Test status
Simulation time	8667697694 ps
CPU time	10.11 seconds
Started	Aug 11 07:18:20 PM PDT 24
Finished	Aug 11 07:18:31 PM PDT 24
Peak memory	210044 kb
Host	smart-3e841f0c-d5f3-400e-af15-a740b2525862
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769896385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1769896385
Directory	/workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1027815692
Short name	T906
Test name
Test status
Simulation time	5861632147 ps
CPU time	7.72 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:30 PM PDT 24
Peak memory	209960 kb
Host	smart-7f592e3d-e419-45b1-a29f-5386942e1f70
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027815692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1027815692
Directory	/workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2860898173
Short name	T896
Test name
Test status
Simulation time	231972710 ps
CPU time	2.6 seconds
Started	Aug 11 07:18:29 PM PDT 24
Finished	Aug 11 07:18:32 PM PDT 24
Peak memory	211716 kb
Host	smart-fe2e442b-9e78-43b7-8fd1-fc995f76e689
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860898173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2860898173
Directory	/workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3448040639
Short name	T998
Test name
Test status
Simulation time	414122046 ps
CPU time	2.11 seconds
Started	Aug 11 07:18:22 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	220572 kb
Host	smart-a980db42-63af-41ea-8e12-0dbb94c695fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344804 0639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3448040639
Directory	/workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.4175595145
Short name	T959
Test name
Test status
Simulation time	316544736 ps
CPU time	2.56 seconds
Started	Aug 11 07:18:36 PM PDT 24
Finished	Aug 11 07:18:38 PM PDT 24
Peak memory	210016 kb
Host	smart-82b59eda-575a-487b-a8b7-c29c7f269926
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175595145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.4175595145
Directory	/workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.32401420
Short name	T905
Test name
Test status
Simulation time	74931349 ps
CPU time	1.74 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:36 PM PDT 24
Peak memory	210048 kb
Host	smart-9c9b52ed-9047-4e54-bcb2-5509b24edfdd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32401420 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.32401420
Directory	/workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.919937598
Short name	T219
Test name
Test status
Simulation time	67701132 ps
CPU time	1.72 seconds
Started	Aug 11 07:18:18 PM PDT 24
Finished	Aug 11 07:18:20 PM PDT 24
Peak memory	210004 kb
Host	smart-e03bffeb-f04d-4062-aa33-f27b96875a77
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919937598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ same_csr_outstanding.919937598
Directory	/workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.768223383
Short name	T983
Test name
Test status
Simulation time	93897633 ps
CPU time	2.67 seconds
Started	Aug 11 07:18:15 PM PDT 24
Finished	Aug 11 07:18:18 PM PDT 24
Peak memory	218284 kb
Host	smart-9689a1dc-ca52-4d46-8816-2c3d70ffae2f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768223383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.768223383
Directory	/workspace/6.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1731768711
Short name	T133
Test name
Test status
Simulation time	232142559 ps
CPU time	2.71 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	222688 kb
Host	smart-3c792cb4-5d17-4fc4-882a-d8002b4e8e6e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731768711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_ err.1731768711
Directory	/workspace/6.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3575407404
Short name	T920
Test name
Test status
Simulation time	86237190 ps
CPU time	1.35 seconds
Started	Aug 11 07:18:20 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	219540 kb
Host	smart-4f5f6401-1100-4035-ab74-b91f41f1f3cf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575407404 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3575407404
Directory	/workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1609469139
Short name	T895
Test name
Test status
Simulation time	42252818 ps
CPU time	1.02 seconds
Started	Aug 11 07:18:15 PM PDT 24
Finished	Aug 11 07:18:17 PM PDT 24
Peak memory	210048 kb
Host	smart-80a46911-3c1f-415b-bb9b-9c53e74d94cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609469139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1609469139
Directory	/workspace/7.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3153588399
Short name	T890
Test name
Test status
Simulation time	152751103 ps
CPU time	1.51 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:25 PM PDT 24
Peak memory	209848 kb
Host	smart-d8c1e275-f41b-40e8-adb7-d75fd13c3f46
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153588399 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3153588399
Directory	/workspace/7.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1284946768
Short name	T145
Test name
Test status
Simulation time	447816391 ps
CPU time	5.92 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:29 PM PDT 24
Peak memory	209840 kb
Host	smart-c53b74cb-2764-472e-a3a2-cb7d2b01968a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284946768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1284946768
Directory	/workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.499351560
Short name	T929
Test name
Test status
Simulation time	2020753430 ps
CPU time	12.59 seconds
Started	Aug 11 07:18:28 PM PDT 24
Finished	Aug 11 07:18:40 PM PDT 24
Peak memory	209864 kb
Host	smart-3c5468a9-300a-44d5-b6c7-6b6e84e78042
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499351560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.499351560
Directory	/workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1647116601
Short name	T144
Test name
Test status
Simulation time	311537139 ps
CPU time	1.43 seconds
Started	Aug 11 07:18:20 PM PDT 24
Finished	Aug 11 07:18:21 PM PDT 24
Peak memory	211284 kb
Host	smart-58d8ff8a-0dbd-4192-b87b-7cbba313b860
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647116601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1647116601
Directory	/workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1763541633
Short name	T930
Test name
Test status
Simulation time	205508020 ps
CPU time	1.43 seconds
Started	Aug 11 07:18:26 PM PDT 24
Finished	Aug 11 07:18:28 PM PDT 24
Peak memory	218272 kb
Host	smart-14400aeb-f733-48ab-81c3-b3e5a1efcabc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176354 1633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1763541633
Directory	/workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2040770467
Short name	T143
Test name
Test status
Simulation time	132613734 ps
CPU time	2.37 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:38 PM PDT 24
Peak memory	209972 kb
Host	smart-496a71a1-72a8-4769-bfc3-6c47a948ed43
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040770467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.2040770467
Directory	/workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2973266436
Short name	T970
Test name
Test status
Simulation time	210851593 ps
CPU time	1.1 seconds
Started	Aug 11 07:18:21 PM PDT 24
Finished	Aug 11 07:18:22 PM PDT 24
Peak memory	210076 kb
Host	smart-bb59c76f-e40c-4e29-85db-824cccad2293
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973266436 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2973266436
Directory	/workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.729525971
Short name	T934
Test name
Test status
Simulation time	32328648 ps
CPU time	1.07 seconds
Started	Aug 11 07:18:19 PM PDT 24
Finished	Aug 11 07:18:20 PM PDT 24
Peak memory	210048 kb
Host	smart-94471e5f-760f-485b-b869-1d7951af643d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729525971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ same_csr_outstanding.729525971
Directory	/workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3370632850
Short name	T124
Test name
Test status
Simulation time	198451358 ps
CPU time	2.23 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:27 PM PDT 24
Peak memory	218272 kb
Host	smart-6120b5cd-3c55-4484-838a-d66999fd6cd5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370632850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3370632850
Directory	/workspace/7.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.351906746
Short name	T125
Test name
Test status
Simulation time	89658212 ps
CPU time	1.77 seconds
Started	Aug 11 07:18:39 PM PDT 24
Finished	Aug 11 07:18:41 PM PDT 24
Peak memory	218256 kb
Host	smart-09c700f1-d95a-4f9c-aa91-d99173cc0283
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351906746 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.351906746
Directory	/workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3804245610
Short name	T155
Test name
Test status
Simulation time	27816363 ps
CPU time	1.03 seconds
Started	Aug 11 07:18:49 PM PDT 24
Finished	Aug 11 07:18:50 PM PDT 24
Peak memory	210024 kb
Host	smart-d4141405-8ed5-4e0d-87bc-20e21b7f12b7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804245610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3804245610
Directory	/workspace/8.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.133583040
Short name	T891
Test name
Test status
Simulation time	36237222 ps
CPU time	1.24 seconds
Started	Aug 11 07:18:31 PM PDT 24
Finished	Aug 11 07:18:33 PM PDT 24
Peak memory	208688 kb
Host	smart-14d7af98-97fa-4166-b68c-ed3325ccdf2a
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133583040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.lc_ctrl_jtag_alert_test.133583040
Directory	/workspace/8.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1965649114
Short name	T963
Test name
Test status
Simulation time	13799982056 ps
CPU time	7.54 seconds
Started	Aug 11 07:18:28 PM PDT 24
Finished	Aug 11 07:18:36 PM PDT 24
Peak memory	210032 kb
Host	smart-8f4118f9-1a12-425e-9bc6-f9b715c24a4b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965649114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1965649114
Directory	/workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1902315268
Short name	T120
Test name
Test status
Simulation time	421098575 ps
CPU time	4.82 seconds
Started	Aug 11 07:18:24 PM PDT 24
Finished	Aug 11 07:18:29 PM PDT 24
Peak memory	208732 kb
Host	smart-e8b046b6-b110-40ed-a01f-cc35f070d198
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902315268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1902315268
Directory	/workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3786457982
Short name	T898
Test name
Test status
Simulation time	84477497 ps
CPU time	2.8 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:26 PM PDT 24
Peak memory	211720 kb
Host	smart-d02cb155-1f15-4346-bec0-6cc3e5a26a60
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786457982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3786457982
Directory	/workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1842292228
Short name	T987
Test name
Test status
Simulation time	105176753 ps
CPU time	3.51 seconds
Started	Aug 11 07:18:31 PM PDT 24
Finished	Aug 11 07:18:34 PM PDT 24
Peak memory	219424 kb
Host	smart-e258cb09-0ffb-4b2d-89f1-adf867eb3400
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184229 2228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1842292228
Directory	/workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2244386316
Short name	T940
Test name
Test status
Simulation time	66068062 ps
CPU time	1.48 seconds
Started	Aug 11 07:18:27 PM PDT 24
Finished	Aug 11 07:18:29 PM PDT 24
Peak memory	209948 kb
Host	smart-f7e8c1aa-a997-48b8-8cf2-c0a9c4e623dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244386316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.2244386316
Directory	/workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2934293463
Short name	T975
Test name
Test status
Simulation time	38187461 ps
CPU time	1.69 seconds
Started	Aug 11 07:18:42 PM PDT 24
Finished	Aug 11 07:18:44 PM PDT 24
Peak memory	218208 kb
Host	smart-107e8b39-a89a-4165-a63b-84c8987ae277
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934293463 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2934293463
Directory	/workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3854680775
Short name	T213
Test name
Test status
Simulation time	68692987 ps
CPU time	1.38 seconds
Started	Aug 11 07:18:48 PM PDT 24
Finished	Aug 11 07:18:50 PM PDT 24
Peak memory	210032 kb
Host	smart-8d0babd0-3f60-4927-9681-b65389d79144
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854680775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _same_csr_outstanding.3854680775
Directory	/workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3578828607
Short name	T917
Test name
Test status
Simulation time	47885469 ps
CPU time	3.46 seconds
Started	Aug 11 07:18:34 PM PDT 24
Finished	Aug 11 07:18:38 PM PDT 24
Peak memory	216812 kb
Host	smart-4cc07395-0e6f-46af-a293-5a1d5d1229d3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578828607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3578828607
Directory	/workspace/8.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.529330185
Short name	T922
Test name
Test status
Simulation time	67813347 ps
CPU time	1.42 seconds
Started	Aug 11 07:18:48 PM PDT 24
Finished	Aug 11 07:18:50 PM PDT 24
Peak memory	219968 kb
Host	smart-89684a6d-2707-421f-a655-864bee8f134d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529330185 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.529330185
Directory	/workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.358777132
Short name	T206
Test name
Test status
Simulation time	45902799 ps
CPU time	0.89 seconds
Started	Aug 11 07:18:22 PM PDT 24
Finished	Aug 11 07:18:23 PM PDT 24
Peak memory	209876 kb
Host	smart-cb999046-ea46-405c-8f1f-452cee2a57d7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358777132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.358777132
Directory	/workspace/9.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3193082802
Short name	T968
Test name
Test status
Simulation time	154714417 ps
CPU time	0.93 seconds
Started	Aug 11 07:18:19 PM PDT 24
Finished	Aug 11 07:18:20 PM PDT 24
Peak memory	208604 kb
Host	smart-6ba564ad-9caa-4aba-bbc8-926f9070f8b4
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193082802 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3193082802
Directory	/workspace/9.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3420579110
Short name	T910
Test name
Test status
Simulation time	5104356412 ps
CPU time	9.53 seconds
Started	Aug 11 07:18:27 PM PDT 24
Finished	Aug 11 07:18:37 PM PDT 24
Peak memory	209344 kb
Host	smart-10e70987-ed8d-4589-a9c6-973ae83843a1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420579110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3420579110
Directory	/workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.591532361
Short name	T945
Test name
Test status
Simulation time	1936542471 ps
CPU time	18.19 seconds
Started	Aug 11 07:18:41 PM PDT 24
Finished	Aug 11 07:18:59 PM PDT 24
Peak memory	209852 kb
Host	smart-a002979b-7d4c-4ac2-bc24-3a1d8bab8b90
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591532361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.591532361
Directory	/workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.725853211
Short name	T918
Test name
Test status
Simulation time	260497201 ps
CPU time	2.08 seconds
Started	Aug 11 07:18:35 PM PDT 24
Finished	Aug 11 07:18:38 PM PDT 24
Peak memory	211652 kb
Host	smart-93b5ba9a-2397-4052-b046-e3fbc771f158
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725853211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.725853211
Directory	/workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2681748056
Short name	T994
Test name
Test status
Simulation time	148047130 ps
CPU time	2.63 seconds
Started	Aug 11 07:18:27 PM PDT 24
Finished	Aug 11 07:18:30 PM PDT 24
Peak memory	218392 kb
Host	smart-7243a330-dfeb-40f8-b0b6-27b675580bf0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268174 8056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2681748056
Directory	/workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2364753506
Short name	T1001
Test name
Test status
Simulation time	126665810 ps
CPU time	2.11 seconds
Started	Aug 11 07:18:21 PM PDT 24
Finished	Aug 11 07:18:23 PM PDT 24
Peak memory	210008 kb
Host	smart-7676e97e-0785-4fc1-90bf-878be174c2b1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364753506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.2364753506
Directory	/workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2543483760
Short name	T217
Test name
Test status
Simulation time	17802078 ps
CPU time	0.94 seconds
Started	Aug 11 07:18:45 PM PDT 24
Finished	Aug 11 07:18:46 PM PDT 24
Peak memory	210036 kb
Host	smart-358a9dfb-6c44-40c7-94c2-f5ad007e98ae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543483760 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2543483760
Directory	/workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.380725268
Short name	T156
Test name
Test status
Simulation time	67479881 ps
CPU time	1.32 seconds
Started	Aug 11 07:18:23 PM PDT 24
Finished	Aug 11 07:18:24 PM PDT 24
Peak memory	211992 kb
Host	smart-f8875b2a-123c-428c-944a-b7cfb6186277
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380725268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ same_csr_outstanding.380725268
Directory	/workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2674302918
Short name	T118
Test name
Test status
Simulation time	48686286 ps
CPU time	1.7 seconds
Started	Aug 11 07:18:52 PM PDT 24
Finished	Aug 11 07:18:53 PM PDT 24
Peak memory	218244 kb
Host	smart-b70e27ef-c744-41c1-aedf-ed35658fa7c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674302918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2674302918
Directory	/workspace/9.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_alert_test.1451551279
Short name	T381
Test name
Test status
Simulation time	15190242 ps
CPU time	0.84 seconds
Started	Aug 11 07:05:14 PM PDT 24
Finished	Aug 11 07:05:15 PM PDT 24
Peak memory	208564 kb
Host	smart-ff9bf901-ceb2-4a27-9b5d-559eec16ee8d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451551279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1451551279
Directory	/workspace/0.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.lc_ctrl_claim_transition_if.1704983065
Short name	T720
Test name
Test status
Simulation time	33819427 ps
CPU time	0.93 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:05:12 PM PDT 24
Peak memory	208632 kb
Host	smart-80bab16b-c9e2-4c8c-9517-2d265fe28909
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704983065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1704983065
Directory	/workspace/0.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/0.lc_ctrl_errors.3744151776
Short name	T104
Test name
Test status
Simulation time	2136346279 ps
CPU time	17.31 seconds
Started	Aug 11 07:05:08 PM PDT 24
Finished	Aug 11 07:05:26 PM PDT 24
Peak memory	225900 kb
Host	smart-da23497f-4665-4799-a741-b3ec5d039e81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744151776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3744151776
Directory	/workspace/0.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_access.3429977646
Short name	T869
Test name
Test status
Simulation time	694792206 ps
CPU time	15.16 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:05:27 PM PDT 24
Peak memory	217284 kb
Host	smart-f33cfe7c-1b62-446f-af39-24cbb3238f18
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429977646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3429977646
Directory	/workspace/0.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_errors.2551810336
Short name	T42
Test name
Test status
Simulation time	2438225425 ps
CPU time	38.07 seconds
Started	Aug 11 07:05:12 PM PDT 24
Finished	Aug 11 07:05:50 PM PDT 24
Peak memory	225948 kb
Host	smart-e0e6aaee-7bf8-451f-b2a4-f06804616bb4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551810336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er rors.2551810336
Directory	/workspace/0.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_priority.2542273548
Short name	T273
Test name
Test status
Simulation time	3980330631 ps
CPU time	14.76 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:05:26 PM PDT 24
Peak memory	217712 kb
Host	smart-63de6758-f654-413b-b57c-76ea3f6c1b75
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542273548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2 542273548
Directory	/workspace/0.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.501386936
Short name	T233
Test name
Test status
Simulation time	422097128 ps
CPU time	12.04 seconds
Started	Aug 11 07:05:14 PM PDT 24
Finished	Aug 11 07:05:26 PM PDT 24
Peak memory	218028 kb
Host	smart-4627bded-6fc8-4341-a1eb-b0d1952485dd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501386936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ prog_failure.501386936
Directory	/workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1504838675
Short name	T66
Test name
Test status
Simulation time	1409848971 ps
CPU time	16.4 seconds
Started	Aug 11 07:05:14 PM PDT 24
Finished	Aug 11 07:05:30 PM PDT 24
Peak memory	217396 kb
Host	smart-db90ac79-2b0e-47e2-a9c9-181872338ebf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504838675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_regwen_during_op.1504838675
Directory	/workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_smoke.3040104657
Short name	T775
Test name
Test status
Simulation time	188052262 ps
CPU time	1.65 seconds
Started	Aug 11 07:05:12 PM PDT 24
Finished	Aug 11 07:05:13 PM PDT 24
Peak memory	217476 kb
Host	smart-48a00e6f-c6f3-44bc-b6ad-23b34b3bf10b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040104657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke. 3040104657
Directory	/workspace/0.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1163395265
Short name	T611
Test name
Test status
Simulation time	14648076536 ps
CPU time	74 seconds
Started	Aug 11 07:05:15 PM PDT 24
Finished	Aug 11 07:06:29 PM PDT 24
Peak memory	283568 kb
Host	smart-1a7cf0e8-18f9-40d6-ae2f-4d3a7bbfadf7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163395265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta g_state_failure.1163395265
Directory	/workspace/0.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1338182777
Short name	T698
Test name
Test status
Simulation time	1083121305 ps
CPU time	9.67 seconds
Started	Aug 11 07:05:14 PM PDT 24
Finished	Aug 11 07:05:24 PM PDT 24
Peak memory	226176 kb
Host	smart-ca2034b4-1d05-4292-8830-ac885ea7c5b7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338182777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_state_post_trans.1338182777
Directory	/workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_prog_failure.1785000239
Short name	T34
Test name
Test status
Simulation time	18959672 ps
CPU time	1.76 seconds
Started	Aug 11 07:05:08 PM PDT 24
Finished	Aug 11 07:05:10 PM PDT 24
Peak memory	218116 kb
Host	smart-05120d61-9a0e-4a83-9a9c-6fa58bdd0a4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785000239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1785000239
Directory	/workspace/0.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_regwen_during_op.3542051546
Short name	T438
Test name
Test status
Simulation time	310742441 ps
CPU time	6.98 seconds
Started	Aug 11 07:05:12 PM PDT 24
Finished	Aug 11 07:05:19 PM PDT 24
Peak memory	217520 kb
Host	smart-441295e0-46c9-4bed-9ce9-04e640af6ed3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542051546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3542051546
Directory	/workspace/0.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_mubi.610666627
Short name	T874
Test name
Test status
Simulation time	1903450778 ps
CPU time	13.65 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:05:25 PM PDT 24
Peak memory	225800 kb
Host	smart-fddf31ae-97d3-483c-bb3d-ff6494d74b85
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610666627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.610666627
Directory	/workspace/0.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_digest.1290268893
Short name	T663
Test name
Test status
Simulation time	406252613 ps
CPU time	15.75 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:05:27 PM PDT 24
Peak memory	225792 kb
Host	smart-4ec82932-12b9-4ae8-a8a7-11e07fa98222
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290268893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di gest.1290268893
Directory	/workspace/0.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_mux.1123698603
Short name	T455
Test name
Test status
Simulation time	535677638 ps
CPU time	6.61 seconds
Started	Aug 11 07:05:12 PM PDT 24
Finished	Aug 11 07:05:19 PM PDT 24
Peak memory	225800 kb
Host	smart-8581d078-a3db-485b-bc84-91337abdbe42
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123698603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1 123698603
Directory	/workspace/0.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/0.lc_ctrl_security_escalation.1696337420
Short name	T389
Test name
Test status
Simulation time	384487578 ps
CPU time	9.73 seconds
Started	Aug 11 07:05:07 PM PDT 24
Finished	Aug 11 07:05:17 PM PDT 24
Peak memory	225384 kb
Host	smart-a793d9c5-3f73-4d5d-8ca8-110ad51011e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696337420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1696337420
Directory	/workspace/0.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_smoke.1219772271
Short name	T842
Test name
Test status
Simulation time	389705802 ps
CPU time	2.78 seconds
Started	Aug 11 07:05:08 PM PDT 24
Finished	Aug 11 07:05:11 PM PDT 24
Peak memory	214588 kb
Host	smart-8460037e-2e74-4a5e-abc9-987dbe6e7572
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1219772271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1219772271
Directory	/workspace/0.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_failure.2297413536
Short name	T491
Test name
Test status
Simulation time	329217898 ps
CPU time	27.75 seconds
Started	Aug 11 07:05:07 PM PDT 24
Finished	Aug 11 07:05:35 PM PDT 24
Peak memory	250792 kb
Host	smart-e4ae0531-a315-45c4-b835-ed6e7a10992e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297413536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2297413536
Directory	/workspace/0.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_post_trans.1462487140
Short name	T282
Test name
Test status
Simulation time	138131477 ps
CPU time	7.88 seconds
Started	Aug 11 07:05:08 PM PDT 24
Finished	Aug 11 07:05:16 PM PDT 24
Peak memory	250780 kb
Host	smart-f8f92893-8dd1-4e49-a8f6-088d314427f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1462487140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1462487140
Directory	/workspace/0.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_stress_all.2849990916
Short name	T368
Test name
Test status
Simulation time	2957116618 ps
CPU time	78.36 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:06:30 PM PDT 24
Peak memory	279240 kb
Host	smart-ffc54f08-785b-47aa-ab5e-7c1f6c51201e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849990916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.2849990916
Directory	/workspace/0.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3900990567
Short name	T650
Test name
Test status
Simulation time	13299304 ps
CPU time	0.86 seconds
Started	Aug 11 07:05:09 PM PDT 24
Finished	Aug 11 07:05:10 PM PDT 24
Peak memory	211792 kb
Host	smart-0cf346f7-0158-4386-91b9-59f135846800
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900990567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct rl_volatile_unlock_smoke.3900990567
Directory	/workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_alert_test.1434062589
Short name	T429
Test name
Test status
Simulation time	16132920 ps
CPU time	1.08 seconds
Started	Aug 11 07:05:18 PM PDT 24
Finished	Aug 11 07:05:19 PM PDT 24
Peak memory	208740 kb
Host	smart-308e2d63-87cc-49c4-9f34-f1e42b416245
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434062589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1434062589
Directory	/workspace/1.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.lc_ctrl_errors.2212029065
Short name	T469
Test name
Test status
Simulation time	301558396 ps
CPU time	13.16 seconds
Started	Aug 11 07:05:12 PM PDT 24
Finished	Aug 11 07:05:25 PM PDT 24
Peak memory	225988 kb
Host	smart-1edbef50-839a-4aee-a61c-144ac6961528
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212029065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2212029065
Directory	/workspace/1.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_access.1477868785
Short name	T500
Test name
Test status
Simulation time	247519298 ps
CPU time	4.12 seconds
Started	Aug 11 07:05:17 PM PDT 24
Finished	Aug 11 07:05:21 PM PDT 24
Peak memory	217156 kb
Host	smart-6ce96d8d-16d3-4396-ab76-fbd770f35f49
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477868785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1477868785
Directory	/workspace/1.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_errors.1741779346
Short name	T251
Test name
Test status
Simulation time	1227260891 ps
CPU time	23.29 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:43 PM PDT 24
Peak memory	218068 kb
Host	smart-331aabde-caa2-4a89-9c9e-4898d0a65d72
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741779346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er rors.1741779346
Directory	/workspace/1.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_priority.867086242
Short name	T186
Test name
Test status
Simulation time	155389380 ps
CPU time	3.61 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:23 PM PDT 24
Peak memory	217580 kb
Host	smart-b311f594-8122-4900-8bd1-738d73e00b9a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867086242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.867086242
Directory	/workspace/1.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1463152899
Short name	T248
Test name
Test status
Simulation time	333276691 ps
CPU time	5.97 seconds
Started	Aug 11 07:05:21 PM PDT 24
Finished	Aug 11 07:05:27 PM PDT 24
Peak memory	222848 kb
Host	smart-e7becefd-8e05-46e7-a7ca-aea4392a073d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463152899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag _prog_failure.1463152899
Directory	/workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2150636365
Short name	T504
Test name
Test status
Simulation time	1408511546 ps
CPU time	10.36 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:30 PM PDT 24
Peak memory	217480 kb
Host	smart-59654b66-2837-4710-b419-7ff31111c624
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150636365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_regwen_during_op.2150636365
Directory	/workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_smoke.4157868296
Short name	T323
Test name
Test status
Simulation time	270234286 ps
CPU time	2.69 seconds
Started	Aug 11 07:05:20 PM PDT 24
Finished	Aug 11 07:05:22 PM PDT 24
Peak memory	217432 kb
Host	smart-9684485b-8293-4958-974c-d162eed946eb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157868296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke. 4157868296
Directory	/workspace/1.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2180688360
Short name	T810
Test name
Test status
Simulation time	4887971115 ps
CPU time	54.98 seconds
Started	Aug 11 07:05:18 PM PDT 24
Finished	Aug 11 07:06:13 PM PDT 24
Peak memory	283632 kb
Host	smart-c223556d-02b4-4ef9-861e-da017c6097c3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180688360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_state_failure.2180688360
Directory	/workspace/1.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3382859080
Short name	T751
Test name
Test status
Simulation time	294248760 ps
CPU time	14.87 seconds
Started	Aug 11 07:05:18 PM PDT 24
Finished	Aug 11 07:05:32 PM PDT 24
Peak memory	250556 kb
Host	smart-e128620a-c7a9-4473-a232-5d4da5780f58
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382859080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_state_post_trans.3382859080
Directory	/workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_prog_failure.1177835715
Short name	T607
Test name
Test status
Simulation time	81648078 ps
CPU time	2.57 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:05:14 PM PDT 24
Peak memory	222368 kb
Host	smart-55a60376-2a4d-4426-a4ff-cc0037f23467
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177835715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1177835715
Directory	/workspace/1.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_regwen_during_op.1619277892
Short name	T695
Test name
Test status
Simulation time	267294865 ps
CPU time	17.66 seconds
Started	Aug 11 07:05:14 PM PDT 24
Finished	Aug 11 07:05:32 PM PDT 24
Peak memory	214516 kb
Host	smart-71519d7d-3b35-429c-a9c5-f87b3baa4f3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619277892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1619277892
Directory	/workspace/1.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_cm.3050694146
Short name	T50
Test name
Test status
Simulation time	625349608 ps
CPU time	34.33 seconds
Started	Aug 11 07:05:29 PM PDT 24
Finished	Aug 11 07:06:04 PM PDT 24
Peak memory	282528 kb
Host	smart-f3280a9a-59f8-4255-922f-8ba4bbc8f060
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050694146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3050694146
Directory	/workspace/1.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_mubi.1238215333
Short name	T866
Test name
Test status
Simulation time	712679093 ps
CPU time	12.32 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:05:36 PM PDT 24
Peak memory	225912 kb
Host	smart-a79831fa-7673-4eee-866c-9cfa0b76db3d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238215333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1238215333
Directory	/workspace/1.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_digest.3278557157
Short name	T815
Test name
Test status
Simulation time	954063336 ps
CPU time	15.48 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:35 PM PDT 24
Peak memory	225700 kb
Host	smart-a7872d3d-5f4e-4d2d-9a88-d6309ce8da97
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278557157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di gest.3278557157
Directory	/workspace/1.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_mux.2614843116
Short name	T358
Test name
Test status
Simulation time	2645090276 ps
CPU time	15.78 seconds
Started	Aug 11 07:05:17 PM PDT 24
Finished	Aug 11 07:05:33 PM PDT 24
Peak memory	218116 kb
Host	smart-21941c88-773e-448e-ac7b-1bc12cc23eb5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614843116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2 614843116
Directory	/workspace/1.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/1.lc_ctrl_security_escalation.3538414896
Short name	T102
Test name
Test status
Simulation time	737327864 ps
CPU time	9.2 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:05:20 PM PDT 24
Peak memory	224744 kb
Host	smart-b468e76a-ff7a-4a81-bc73-14f621b3cfa7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538414896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3538414896
Directory	/workspace/1.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/1.lc_ctrl_smoke.22294121
Short name	T88
Test name
Test status
Simulation time	21027675 ps
CPU time	1.57 seconds
Started	Aug 11 07:05:12 PM PDT 24
Finished	Aug 11 07:05:14 PM PDT 24
Peak memory	213444 kb
Host	smart-82583b9f-1b67-4cc1-89b7-dd7d4bf7ee22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22294121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.22294121
Directory	/workspace/1.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_failure.3843335050
Short name	T161
Test name
Test status
Simulation time	623697950 ps
CPU time	22.29 seconds
Started	Aug 11 07:05:14 PM PDT 24
Finished	Aug 11 07:05:36 PM PDT 24
Peak memory	250720 kb
Host	smart-c3689f82-ced8-47dc-8f27-e043a3cc0308
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843335050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3843335050
Directory	/workspace/1.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_post_trans.120514879
Short name	T639
Test name
Test status
Simulation time	259942671 ps
CPU time	9.23 seconds
Started	Aug 11 07:05:12 PM PDT 24
Finished	Aug 11 07:05:22 PM PDT 24
Peak memory	250784 kb
Host	smart-91704c23-4697-41bf-804f-cab3de415630
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120514879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.120514879
Directory	/workspace/1.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all.1389677467
Short name	T551
Test name
Test status
Simulation time	19164739148 ps
CPU time	97.15 seconds
Started	Aug 11 07:05:29 PM PDT 24
Finished	Aug 11 07:07:07 PM PDT 24
Peak memory	282704 kb
Host	smart-21c437e2-ae61-465c-9e8e-bb41a08c0cef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389677467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.1389677467
Directory	/workspace/1.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1729317254
Short name	T109
Test name
Test status
Simulation time	38471761001 ps
CPU time	719.12 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:17:19 PM PDT 24
Peak memory	513204 kb
Host	smart-a34ac21b-b238-491b-8fd3-a58a3f65ceed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1729317254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1729317254
Directory	/workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1265373544
Short name	T718
Test name
Test status
Simulation time	26714837 ps
CPU time	0.9 seconds
Started	Aug 11 07:05:11 PM PDT 24
Finished	Aug 11 07:05:12 PM PDT 24
Peak memory	211668 kb
Host	smart-b84c8ee8-fb8c-4b68-a3b1-39cc485f4585
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265373544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_volatile_unlock_smoke.1265373544
Directory	/workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_alert_test.443308135
Short name	T74
Test name
Test status
Simulation time	45038783 ps
CPU time	0.96 seconds
Started	Aug 11 07:06:05 PM PDT 24
Finished	Aug 11 07:06:06 PM PDT 24
Peak memory	208720 kb
Host	smart-80257cb4-b7d4-433f-ab03-43f6c954b2d8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443308135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.443308135
Directory	/workspace/10.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.lc_ctrl_errors.55011358
Short name	T657
Test name
Test status
Simulation time	1655069685 ps
CPU time	14.01 seconds
Started	Aug 11 07:05:56 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	218092 kb
Host	smart-b87104ed-5739-4b24-ad85-a082b1ccd035
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55011358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.55011358
Directory	/workspace/10.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_access.931737896
Short name	T198
Test name
Test status
Simulation time	7475417404 ps
CPU time	14.95 seconds
Started	Aug 11 07:05:55 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	217636 kb
Host	smart-21e2a652-ac4b-418d-ae01-354137218668
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931737896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.931737896
Directory	/workspace/10.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_errors.1796851807
Short name	T188
Test name
Test status
Simulation time	9565544021 ps
CPU time	59.11 seconds
Started	Aug 11 07:05:57 PM PDT 24
Finished	Aug 11 07:06:56 PM PDT 24
Peak memory	218748 kb
Host	smart-1358df2c-7105-42d5-a2f3-1e1522a3cabe
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796851807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e rrors.1796851807
Directory	/workspace/10.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3938966923
Short name	T669
Test name
Test status
Simulation time	1455333565 ps
CPU time	11.68 seconds
Started	Aug 11 07:05:57 PM PDT 24
Finished	Aug 11 07:06:09 PM PDT 24
Peak memory	217996 kb
Host	smart-3e4e4e3e-a9f3-4c62-9dc1-ba36df050ac0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938966923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_prog_failure.3938966923
Directory	/workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_smoke.2212062370
Short name	T72
Test name
Test status
Simulation time	525896536 ps
CPU time	4.07 seconds
Started	Aug 11 07:05:58 PM PDT 24
Finished	Aug 11 07:06:02 PM PDT 24
Peak memory	217624 kb
Host	smart-12a6eab3-07f2-4cf6-94ed-c11004c662a3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212062370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke .2212062370
Directory	/workspace/10.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.4280954037
Short name	T844
Test name
Test status
Simulation time	9445511786 ps
CPU time	58.58 seconds
Started	Aug 11 07:05:57 PM PDT 24
Finished	Aug 11 07:06:56 PM PDT 24
Peak memory	267240 kb
Host	smart-ac3a1327-bdcc-4552-b26d-f45291c2b571
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280954037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt ag_state_failure.4280954037
Directory	/workspace/10.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3226729524
Short name	T370
Test name
Test status
Simulation time	292423079 ps
CPU time	10.36 seconds
Started	Aug 11 07:05:54 PM PDT 24
Finished	Aug 11 07:06:05 PM PDT 24
Peak memory	221720 kb
Host	smart-5df76f1d-b663-4659-8e29-55e5a0bfcb7e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226729524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl _jtag_state_post_trans.3226729524
Directory	/workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_prog_failure.1712465514
Short name	T271
Test name
Test status
Simulation time	122494456 ps
CPU time	3.82 seconds
Started	Aug 11 07:05:55 PM PDT 24
Finished	Aug 11 07:05:59 PM PDT 24
Peak memory	222548 kb
Host	smart-06c6e6e1-9bd8-40c1-a2ba-cd85e7778e7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712465514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1712465514
Directory	/workspace/10.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_mubi.2547954161
Short name	T521
Test name
Test status
Simulation time	312205923 ps
CPU time	14.27 seconds
Started	Aug 11 07:05:57 PM PDT 24
Finished	Aug 11 07:06:11 PM PDT 24
Peak memory	225924 kb
Host	smart-bd67e5e7-0d6c-47bc-86ad-9e6f03e45e6d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547954161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2547954161
Directory	/workspace/10.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_digest.241240058
Short name	T413
Test name
Test status
Simulation time	651742658 ps
CPU time	8.88 seconds
Started	Aug 11 07:05:57 PM PDT 24
Finished	Aug 11 07:06:06 PM PDT 24
Peak memory	218056 kb
Host	smart-3bc5a6a7-a6a0-4751-ab66-e45f967f1360
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241240058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di gest.241240058
Directory	/workspace/10.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_mux.222673758
Short name	T609
Test name
Test status
Simulation time	410842627 ps
CPU time	10.25 seconds
Started	Aug 11 07:05:58 PM PDT 24
Finished	Aug 11 07:06:08 PM PDT 24
Peak memory	218204 kb
Host	smart-535a17e9-58ee-43e9-8e2e-cefa63dcaa70
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222673758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.222673758
Directory	/workspace/10.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/10.lc_ctrl_security_escalation.666279247
Short name	T54
Test name
Test status
Simulation time	291977123 ps
CPU time	8.69 seconds
Started	Aug 11 07:05:56 PM PDT 24
Finished	Aug 11 07:06:05 PM PDT 24
Peak memory	218168 kb
Host	smart-2cb35ab5-1489-419f-bafa-29f09a3a065d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666279247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.666279247
Directory	/workspace/10.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/10.lc_ctrl_smoke.2393773123
Short name	T817
Test name
Test status
Simulation time	143377093 ps
CPU time	2.32 seconds
Started	Aug 11 07:05:58 PM PDT 24
Finished	Aug 11 07:06:00 PM PDT 24
Peak memory	214060 kb
Host	smart-303c3217-09b3-4393-ad59-1f50873e0952
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393773123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2393773123
Directory	/workspace/10.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_failure.3932306148
Short name	T407
Test name
Test status
Simulation time	490824897 ps
CPU time	25.88 seconds
Started	Aug 11 07:05:54 PM PDT 24
Finished	Aug 11 07:06:20 PM PDT 24
Peak memory	250784 kb
Host	smart-ec384530-9ffa-471b-b602-5966c702ad9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932306148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3932306148
Directory	/workspace/10.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_post_trans.282690103
Short name	T601
Test name
Test status
Simulation time	90013148 ps
CPU time	6.69 seconds
Started	Aug 11 07:05:57 PM PDT 24
Finished	Aug 11 07:06:04 PM PDT 24
Peak memory	250748 kb
Host	smart-7f110324-ff46-4fc1-a2ac-8b2cd49a82be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282690103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.282690103
Directory	/workspace/10.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all.3095770007
Short name	T807
Test name
Test status
Simulation time	16451573392 ps
CPU time	105.94 seconds
Started	Aug 11 07:06:01 PM PDT 24
Finished	Aug 11 07:07:48 PM PDT 24
Peak memory	275720 kb
Host	smart-7da66886-0b3b-4f8b-8db6-fae12b2f368e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095770007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.3095770007
Directory	/workspace/10.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.189163946
Short name	T697
Test name
Test status
Simulation time	28170490 ps
CPU time	0.85 seconds
Started	Aug 11 07:05:54 PM PDT 24
Finished	Aug 11 07:05:55 PM PDT 24
Peak memory	211724 kb
Host	smart-f0c436fa-cb0a-45bc-8734-043a2b0f381d
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189163946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct rl_volatile_unlock_smoke.189163946
Directory	/workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_alert_test.515316883
Short name	T606
Test name
Test status
Simulation time	62490738 ps
CPU time	1.02 seconds
Started	Aug 11 07:06:03 PM PDT 24
Finished	Aug 11 07:06:04 PM PDT 24
Peak memory	208616 kb
Host	smart-960f19dd-9ad5-487d-a3cc-212008c777aa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515316883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.515316883
Directory	/workspace/11.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.lc_ctrl_errors.66051660
Short name	T508
Test name
Test status
Simulation time	333293507 ps
CPU time	13.3 seconds
Started	Aug 11 07:06:02 PM PDT 24
Finished	Aug 11 07:06:16 PM PDT 24
Peak memory	218212 kb
Host	smart-1c1376c3-e542-4805-a383-5d920f9cac8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66051660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.66051660
Directory	/workspace/11.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_access.91129157
Short name	T196
Test name
Test status
Simulation time	50744448 ps
CPU time	1.26 seconds
Started	Aug 11 07:06:02 PM PDT 24
Finished	Aug 11 07:06:03 PM PDT 24
Peak memory	216976 kb
Host	smart-036c0b8b-157a-40f6-b2e2-7525b7fee261
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91129157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.91129157
Directory	/workspace/11.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_errors.114172676
Short name	T696
Test name
Test status
Simulation time	13884120491 ps
CPU time	72.15 seconds
Started	Aug 11 07:06:03 PM PDT 24
Finished	Aug 11 07:07:15 PM PDT 24
Peak memory	225940 kb
Host	smart-e0850d79-0361-4cf5-a613-ef52a66b27ba
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114172676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er rors.114172676
Directory	/workspace/11.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.261530785
Short name	T522
Test name
Test status
Simulation time	525662048 ps
CPU time	10.52 seconds
Started	Aug 11 07:06:03 PM PDT 24
Finished	Aug 11 07:06:14 PM PDT 24
Peak memory	218024 kb
Host	smart-724c30dc-39b7-4f42-83e0-674b066c1ba0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261530785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag _prog_failure.261530785
Directory	/workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_smoke.4169334827
Short name	T863
Test name
Test status
Simulation time	447376943 ps
CPU time	4.83 seconds
Started	Aug 11 07:06:03 PM PDT 24
Finished	Aug 11 07:06:09 PM PDT 24
Peak memory	217444 kb
Host	smart-2c9c9ff9-a05d-4e49-afa7-97fdafa09cb1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169334827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke .4169334827
Directory	/workspace/11.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3695436407
Short name	T23
Test name
Test status
Simulation time	2498214454 ps
CPU time	56.76 seconds
Started	Aug 11 07:06:02 PM PDT 24
Finished	Aug 11 07:06:59 PM PDT 24
Peak memory	251748 kb
Host	smart-876c4ab3-70f4-4065-ade6-768440c7500d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695436407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt ag_state_failure.3695436407
Directory	/workspace/11.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3570597338
Short name	T641
Test name
Test status
Simulation time	1363165687 ps
CPU time	16.74 seconds
Started	Aug 11 07:06:06 PM PDT 24
Finished	Aug 11 07:06:23 PM PDT 24
Peak memory	250868 kb
Host	smart-fbd37c24-e920-413d-8fde-de122c0672a0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570597338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _jtag_state_post_trans.3570597338
Directory	/workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_prog_failure.2348664505
Short name	T771
Test name
Test status
Simulation time	40608661 ps
CPU time	1.87 seconds
Started	Aug 11 07:06:04 PM PDT 24
Finished	Aug 11 07:06:06 PM PDT 24
Peak memory	218096 kb
Host	smart-fef959aa-507c-4b23-91f8-06311feae0ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348664505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2348664505
Directory	/workspace/11.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_mubi.435505125
Short name	T291
Test name
Test status
Simulation time	921950855 ps
CPU time	12.96 seconds
Started	Aug 11 07:06:01 PM PDT 24
Finished	Aug 11 07:06:14 PM PDT 24
Peak memory	218768 kb
Host	smart-08a57ea1-5778-457c-a85a-b05f8603d908
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435505125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.435505125
Directory	/workspace/11.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_digest.4082426756
Short name	T19
Test name
Test status
Simulation time	5813054142 ps
CPU time	13.35 seconds
Started	Aug 11 07:06:02 PM PDT 24
Finished	Aug 11 07:06:15 PM PDT 24
Peak memory	225964 kb
Host	smart-1a59b8f6-5cc3-45cc-8305-a3ae6803fc6c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082426756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d igest.4082426756
Directory	/workspace/11.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_mux.3075260407
Short name	T801
Test name
Test status
Simulation time	1071529901 ps
CPU time	10.75 seconds
Started	Aug 11 07:06:02 PM PDT 24
Finished	Aug 11 07:06:13 PM PDT 24
Peak memory	217968 kb
Host	smart-4e1c8bc2-7c6d-4175-8be0-8690483b9ca1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075260407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux. 3075260407
Directory	/workspace/11.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/11.lc_ctrl_security_escalation.1066532330
Short name	T685
Test name
Test status
Simulation time	1043867192 ps
CPU time	9.83 seconds
Started	Aug 11 07:06:06 PM PDT 24
Finished	Aug 11 07:06:16 PM PDT 24
Peak memory	225944 kb
Host	smart-49bf741e-beaf-4796-9638-222053367d28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066532330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1066532330
Directory	/workspace/11.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/11.lc_ctrl_smoke.2087812194
Short name	T777
Test name
Test status
Simulation time	12840614 ps
CPU time	1.09 seconds
Started	Aug 11 07:06:02 PM PDT 24
Finished	Aug 11 07:06:03 PM PDT 24
Peak memory	212108 kb
Host	smart-18553128-d9d8-432a-9338-2deca33d2eef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087812194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2087812194
Directory	/workspace/11.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_failure.253043997
Short name	T822
Test name
Test status
Simulation time	494319455 ps
CPU time	21.19 seconds
Started	Aug 11 07:06:05 PM PDT 24
Finished	Aug 11 07:06:27 PM PDT 24
Peak memory	250816 kb
Host	smart-baec1e6a-47fd-4460-9f7c-07dc9cdd3ca1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253043997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.253043997
Directory	/workspace/11.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_post_trans.2347979983
Short name	T574
Test name
Test status
Simulation time	522952485 ps
CPU time	3.01 seconds
Started	Aug 11 07:06:03 PM PDT 24
Finished	Aug 11 07:06:07 PM PDT 24
Peak memory	222012 kb
Host	smart-ef8e0b6b-46a1-4d26-8654-6d0c201c7783
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347979983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2347979983
Directory	/workspace/11.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all.922110580
Short name	T477
Test name
Test status
Simulation time	1635826817 ps
CPU time	71.64 seconds
Started	Aug 11 07:06:01 PM PDT 24
Finished	Aug 11 07:07:13 PM PDT 24
Peak memory	250772 kb
Host	smart-59ebe003-2fb9-4bff-a452-b089683a87a7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922110580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all.922110580
Directory	/workspace/11.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3954775140
Short name	T220
Test name
Test status
Simulation time	53433553 ps
CPU time	0.89 seconds
Started	Aug 11 07:05:59 PM PDT 24
Finished	Aug 11 07:06:00 PM PDT 24
Peak memory	217480 kb
Host	smart-64896f5b-a412-489c-a8dd-66d04fdd4eac
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954775140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c trl_volatile_unlock_smoke.3954775140
Directory	/workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_alert_test.3892445136
Short name	T882
Test name
Test status
Simulation time	19597185 ps
CPU time	0.95 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	208736 kb
Host	smart-f9e162a8-8983-42ce-879a-b2bf7245979c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892445136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3892445136
Directory	/workspace/12.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.lc_ctrl_errors.2064083620
Short name	T660
Test name
Test status
Simulation time	1393831546 ps
CPU time	11.59 seconds
Started	Aug 11 07:06:03 PM PDT 24
Finished	Aug 11 07:06:15 PM PDT 24
Peak memory	225840 kb
Host	smart-b4b06aff-6562-4e63-b4b2-2917cc1127cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2064083620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2064083620
Directory	/workspace/12.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_access.3630561323
Short name	T27
Test name
Test status
Simulation time	10205866517 ps
CPU time	12.54 seconds
Started	Aug 11 07:06:07 PM PDT 24
Finished	Aug 11 07:06:20 PM PDT 24
Peak memory	217644 kb
Host	smart-c9bbfd86-231c-411d-a516-f0b494c8686e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630561323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3630561323
Directory	/workspace/12.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_errors.3321810672
Short name	T5
Test name
Test status
Simulation time	98360980223 ps
CPU time	129.04 seconds
Started	Aug 11 07:06:08 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	219800 kb
Host	smart-3bd03217-6f75-4a03-a79d-6bd09b9d201c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321810672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e rrors.3321810672
Directory	/workspace/12.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.858365706
Short name	T602
Test name
Test status
Simulation time	237889129 ps
CPU time	7.39 seconds
Started	Aug 11 07:06:11 PM PDT 24
Finished	Aug 11 07:06:19 PM PDT 24
Peak memory	218068 kb
Host	smart-c334960d-684e-4ae2-a46c-4a1b142f45e8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858365706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag _prog_failure.858365706
Directory	/workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_smoke.1056817488
Short name	T65
Test name
Test status
Simulation time	6270322872 ps
CPU time	9.71 seconds
Started	Aug 11 07:06:01 PM PDT 24
Finished	Aug 11 07:06:11 PM PDT 24
Peak memory	217584 kb
Host	smart-65c8ef56-7a58-4253-bc96-905c738a1e4c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056817488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke .1056817488
Directory	/workspace/12.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3408501836
Short name	T461
Test name
Test status
Simulation time	9552163483 ps
CPU time	80.86 seconds
Started	Aug 11 07:06:06 PM PDT 24
Finished	Aug 11 07:07:27 PM PDT 24
Peak memory	267292 kb
Host	smart-61073ee8-f095-4746-b6c2-a202e2c66cca
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408501836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt ag_state_failure.3408501836
Directory	/workspace/12.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2904818599
Short name	T805
Test name
Test status
Simulation time	357446350 ps
CPU time	11.68 seconds
Started	Aug 11 07:06:02 PM PDT 24
Finished	Aug 11 07:06:14 PM PDT 24
Peak memory	226168 kb
Host	smart-b79abdcb-51ea-4dc2-8561-c00ad26ecd79
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904818599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_state_post_trans.2904818599
Directory	/workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_prog_failure.3730041768
Short name	T175
Test name
Test status
Simulation time	78452234 ps
CPU time	2.91 seconds
Started	Aug 11 07:06:04 PM PDT 24
Finished	Aug 11 07:06:07 PM PDT 24
Peak memory	222216 kb
Host	smart-3c69ebe8-dbc0-46ff-8362-337279841065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730041768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3730041768
Directory	/workspace/12.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_mubi.1341268950
Short name	T570
Test name
Test status
Simulation time	798650739 ps
CPU time	10.72 seconds
Started	Aug 11 07:06:10 PM PDT 24
Finished	Aug 11 07:06:21 PM PDT 24
Peak memory	225936 kb
Host	smart-4d534cbb-013d-4a84-9e17-98985e51f3d2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341268950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1341268950
Directory	/workspace/12.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_digest.2512424245
Short name	T318
Test name
Test status
Simulation time	1413104763 ps
CPU time	7.49 seconds
Started	Aug 11 07:06:07 PM PDT 24
Finished	Aug 11 07:06:15 PM PDT 24
Peak memory	217988 kb
Host	smart-29b69aa5-64b4-4222-997b-38191868e9e4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512424245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d igest.2512424245
Directory	/workspace/12.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_mux.2240733713
Short name	T428
Test name
Test status
Simulation time	245149126 ps
CPU time	8.67 seconds
Started	Aug 11 07:06:10 PM PDT 24
Finished	Aug 11 07:06:19 PM PDT 24
Peak memory	218000 kb
Host	smart-7bfbcc1f-d8e1-4938-af08-10484a245ab8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240733713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux. 2240733713
Directory	/workspace/12.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/12.lc_ctrl_security_escalation.3785092229
Short name	T528
Test name
Test status
Simulation time	609249485 ps
CPU time	8.61 seconds
Started	Aug 11 07:06:05 PM PDT 24
Finished	Aug 11 07:06:14 PM PDT 24
Peak memory	224816 kb
Host	smart-c0cd7c0f-bb59-433f-997b-8ca67be7c076
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785092229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3785092229
Directory	/workspace/12.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/12.lc_ctrl_smoke.168432915
Short name	T617
Test name
Test status
Simulation time	63717560 ps
CPU time	2.78 seconds
Started	Aug 11 07:06:04 PM PDT 24
Finished	Aug 11 07:06:07 PM PDT 24
Peak memory	217480 kb
Host	smart-44075e64-847b-40b3-b37f-02e0227f29b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168432915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.168432915
Directory	/workspace/12.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_failure.910798006
Short name	T164
Test name
Test status
Simulation time	1198740467 ps
CPU time	23.92 seconds
Started	Aug 11 07:06:04 PM PDT 24
Finished	Aug 11 07:06:28 PM PDT 24
Peak memory	250788 kb
Host	smart-fb33f13b-a13f-4f09-b53c-a1de1f37f371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910798006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.910798006
Directory	/workspace/12.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_post_trans.3350024485
Short name	T610
Test name
Test status
Simulation time	297159153 ps
CPU time	6.42 seconds
Started	Aug 11 07:06:03 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	247716 kb
Host	smart-eb45b227-dd9a-4ddb-941f-8fb5fe76918e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350024485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3350024485
Directory	/workspace/12.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1961607102
Short name	T313
Test name
Test status
Simulation time	58847328 ps
CPU time	0.91 seconds
Started	Aug 11 07:06:03 PM PDT 24
Finished	Aug 11 07:06:05 PM PDT 24
Peak memory	211752 kb
Host	smart-ec6b58ad-789b-4fcb-85b4-a56020fe4832
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961607102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_volatile_unlock_smoke.1961607102
Directory	/workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_alert_test.2154636454
Short name	T832
Test name
Test status
Simulation time	19455963 ps
CPU time	1.04 seconds
Started	Aug 11 07:06:10 PM PDT 24
Finished	Aug 11 07:06:11 PM PDT 24
Peak memory	208692 kb
Host	smart-f2407ae0-aad8-47ba-bcb1-4fd2a967d063
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154636454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2154636454
Directory	/workspace/13.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_access.1323729093
Short name	T479
Test name
Test status
Simulation time	8635482192 ps
CPU time	34.76 seconds
Started	Aug 11 07:06:11 PM PDT 24
Finished	Aug 11 07:06:46 PM PDT 24
Peak memory	217656 kb
Host	smart-39a34f45-9ca9-4eaa-95db-4fb15850c9a6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323729093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1323729093
Directory	/workspace/13.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_errors.242787073
Short name	T721
Test name
Test status
Simulation time	19711848967 ps
CPU time	30.52 seconds
Started	Aug 11 07:06:08 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	218784 kb
Host	smart-af96774a-ae7d-46b2-a9dc-e49e1b2c2070
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242787073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er rors.242787073
Directory	/workspace/13.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1379799942
Short name	T638
Test name
Test status
Simulation time	1683692524 ps
CPU time	6.97 seconds
Started	Aug 11 07:06:08 PM PDT 24
Finished	Aug 11 07:06:15 PM PDT 24
Peak memory	217996 kb
Host	smart-adfd4149-3981-42b4-b326-3ab514a3b382
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379799942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta g_prog_failure.1379799942
Directory	/workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_smoke.2498899581
Short name	T446
Test name
Test status
Simulation time	751949308 ps
CPU time	16.66 seconds
Started	Aug 11 07:06:10 PM PDT 24
Finished	Aug 11 07:06:27 PM PDT 24
Peak memory	217452 kb
Host	smart-92ab576c-b39f-4dfc-8e92-99ff5904a540
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498899581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke .2498899581
Directory	/workspace/13.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1837221275
Short name	T260
Test name
Test status
Simulation time	2688345951 ps
CPU time	49.09 seconds
Started	Aug 11 07:06:11 PM PDT 24
Finished	Aug 11 07:07:00 PM PDT 24
Peak memory	279120 kb
Host	smart-8a6ed057-63ca-4589-a1c0-e299611f01e9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837221275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt ag_state_failure.1837221275
Directory	/workspace/13.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2336918484
Short name	T393
Test name
Test status
Simulation time	2823320301 ps
CPU time	21.92 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:31 PM PDT 24
Peak memory	250684 kb
Host	smart-100cc730-979b-470e-8489-ace83ec4dea2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336918484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _jtag_state_post_trans.2336918484
Directory	/workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_prog_failure.1229945925
Short name	T315
Test name
Test status
Simulation time	132640229 ps
CPU time	3.76 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:13 PM PDT 24
Peak memory	222372 kb
Host	smart-431a23b7-4b53-4bff-815b-23ead9023126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229945925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1229945925
Directory	/workspace/13.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_mubi.2063247014
Short name	T316
Test name
Test status
Simulation time	1722783640 ps
CPU time	15.06 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:24 PM PDT 24
Peak memory	219844 kb
Host	smart-d889758c-c882-496f-a9ff-1e221e9bdfb2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063247014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2063247014
Directory	/workspace/13.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_digest.865111360
Short name	T345
Test name
Test status
Simulation time	372429837 ps
CPU time	10.25 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:20 PM PDT 24
Peak memory	218020 kb
Host	smart-2cc84eec-cb92-4768-ad54-4e5d2eaf86f2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865111360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di gest.865111360
Directory	/workspace/13.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_mux.2249997283
Short name	T400
Test name
Test status
Simulation time	301636383 ps
CPU time	7.85 seconds
Started	Aug 11 07:06:10 PM PDT 24
Finished	Aug 11 07:06:18 PM PDT 24
Peak memory	218000 kb
Host	smart-4f2200b6-0a88-458a-840f-dbc7a258ab3b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249997283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux. 2249997283
Directory	/workspace/13.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/13.lc_ctrl_security_escalation.447276945
Short name	T519
Test name
Test status
Simulation time	360448932 ps
CPU time	8.71 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:18 PM PDT 24
Peak memory	218168 kb
Host	smart-50367c7c-be3a-4310-a87b-746a3cbb8837
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447276945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.447276945
Directory	/workspace/13.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/13.lc_ctrl_smoke.4290250508
Short name	T744
Test name
Test status
Simulation time	40546377 ps
CPU time	1.07 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	217512 kb
Host	smart-ddc8959f-da40-4410-ab05-bb8e3cf41118
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290250508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.4290250508
Directory	/workspace/13.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_failure.1939848359
Short name	T377
Test name
Test status
Simulation time	431258739 ps
CPU time	29.95 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	250740 kb
Host	smart-5c56495e-06b8-4dba-86b6-6fc9366f389a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939848359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1939848359
Directory	/workspace/13.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_post_trans.2935743096
Short name	T825
Test name
Test status
Simulation time	195976713 ps
CPU time	6.11 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:15 PM PDT 24
Peak memory	242608 kb
Host	smart-9a17c0ab-2c2a-4fb4-ad3c-831ba4b2c5ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935743096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2935743096
Directory	/workspace/13.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all.4007615571
Short name	T635
Test name
Test status
Simulation time	3576281492 ps
CPU time	15.84 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:25 PM PDT 24
Peak memory	226060 kb
Host	smart-e1598d97-12fc-4d82-8a98-66b90d1f8039
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007615571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.4007615571
Directory	/workspace/13.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.4269555732
Short name	T868
Test name
Test status
Simulation time	39810088159 ps
CPU time	440.65 seconds
Started	Aug 11 07:06:08 PM PDT 24
Finished	Aug 11 07:13:29 PM PDT 24
Peak memory	283816 kb
Host	smart-80b0528e-1c39-43c0-bf3b-55e78818a4c2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4269555732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.4269555732
Directory	/workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1425107179
Short name	T768
Test name
Test status
Simulation time	33699335 ps
CPU time	0.94 seconds
Started	Aug 11 07:06:08 PM PDT 24
Finished	Aug 11 07:06:09 PM PDT 24
Peak memory	211716 kb
Host	smart-bebc3893-7841-49e8-aada-76770a16efbe
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425107179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c trl_volatile_unlock_smoke.1425107179
Directory	/workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_alert_test.1818227893
Short name	T709
Test name
Test status
Simulation time	16417928 ps
CPU time	1.06 seconds
Started	Aug 11 07:06:21 PM PDT 24
Finished	Aug 11 07:06:22 PM PDT 24
Peak memory	208736 kb
Host	smart-39e613c8-14d0-49f2-a8cc-5dd7a7ef18f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818227893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1818227893
Directory	/workspace/14.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.lc_ctrl_errors.4213105631
Short name	T584
Test name
Test status
Simulation time	1915343563 ps
CPU time	12.42 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:33 PM PDT 24
Peak memory	218056 kb
Host	smart-a1e9ce27-be7d-4c47-a0cf-7f5d1fc5ee9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213105631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.4213105631
Directory	/workspace/14.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_access.2592608665
Short name	T26
Test name
Test status
Simulation time	1022738696 ps
CPU time	4.84 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:20 PM PDT 24
Peak memory	217500 kb
Host	smart-4ef9b71f-29b4-4095-8f02-9290ab6106a9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592608665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2592608665
Directory	/workspace/14.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1161765268
Short name	T290
Test name
Test status
Simulation time	563807816 ps
CPU time	4.33 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:25 PM PDT 24
Peak memory	221564 kb
Host	smart-61e091a4-5f69-4217-93fa-bc9580e31696
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161765268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_prog_failure.1161765268
Directory	/workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_smoke.1935485244
Short name	T21
Test name
Test status
Simulation time	240756174 ps
CPU time	3.56 seconds
Started	Aug 11 07:06:14 PM PDT 24
Finished	Aug 11 07:06:18 PM PDT 24
Peak memory	217432 kb
Host	smart-4fba8a96-7878-44a0-9282-7f9bd7c45c75
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935485244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke .1935485244
Directory	/workspace/14.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_failure.511670554
Short name	T274
Test name
Test status
Simulation time	903484065 ps
CPU time	39.9 seconds
Started	Aug 11 07:06:17 PM PDT 24
Finished	Aug 11 07:06:57 PM PDT 24
Peak memory	250720 kb
Host	smart-ca09e60b-1908-4cbe-9965-e8f26a403c4e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511670554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_state_failure.511670554
Directory	/workspace/14.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.75018967
Short name	T22
Test name
Test status
Simulation time	6329661622 ps
CPU time	26.68 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:42 PM PDT 24
Peak memory	250864 kb
Host	smart-67f9f51d-d530-4786-92ae-6dd249057fba
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75018967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_j tag_state_post_trans.75018967
Directory	/workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_prog_failure.2964764950
Short name	T552
Test name
Test status
Simulation time	44191839 ps
CPU time	3 seconds
Started	Aug 11 07:06:14 PM PDT 24
Finished	Aug 11 07:06:17 PM PDT 24
Peak memory	222252 kb
Host	smart-2c0858bf-c882-4a76-9172-a12faf8a7618
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2964764950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2964764950
Directory	/workspace/14.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_mubi.1448698736
Short name	T285
Test name
Test status
Simulation time	562305732 ps
CPU time	13.85 seconds
Started	Aug 11 07:06:18 PM PDT 24
Finished	Aug 11 07:06:32 PM PDT 24
Peak memory	218080 kb
Host	smart-15e4a09f-edb7-4890-b5d8-a546e2d87681
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448698736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1448698736
Directory	/workspace/14.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_digest.3335567289
Short name	T743
Test name
Test status
Simulation time	461340841 ps
CPU time	11.23 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:27 PM PDT 24
Peak memory	218044 kb
Host	smart-d6ec8d68-7189-44e2-ac46-8e56954aa5b1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335567289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d igest.3335567289
Directory	/workspace/14.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_mux.3766629847
Short name	T357
Test name
Test status
Simulation time	458652075 ps
CPU time	9.08 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:25 PM PDT 24
Peak memory	218032 kb
Host	smart-816b0a2e-9401-4823-9ec4-1786802fa35d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766629847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux. 3766629847
Directory	/workspace/14.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/14.lc_ctrl_smoke.1511637922
Short name	T73
Test name
Test status
Simulation time	290667579 ps
CPU time	3.85 seconds
Started	Aug 11 07:06:10 PM PDT 24
Finished	Aug 11 07:06:14 PM PDT 24
Peak memory	217536 kb
Host	smart-7bb7b200-bb03-4c56-bf96-d68deca3554b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511637922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1511637922
Directory	/workspace/14.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_failure.1249395679
Short name	T808
Test name
Test status
Simulation time	366505678 ps
CPU time	22.51 seconds
Started	Aug 11 07:06:10 PM PDT 24
Finished	Aug 11 07:06:33 PM PDT 24
Peak memory	250852 kb
Host	smart-293ffff2-c602-41c3-9f8d-a72038b6ab9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249395679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1249395679
Directory	/workspace/14.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_post_trans.430808147
Short name	T600
Test name
Test status
Simulation time	97396645 ps
CPU time	7.12 seconds
Started	Aug 11 07:06:15 PM PDT 24
Finished	Aug 11 07:06:23 PM PDT 24
Peak memory	242548 kb
Host	smart-b36a5c9f-f76a-4728-ba43-69b939d33e43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=430808147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.430808147
Directory	/workspace/14.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all.400931152
Short name	T35
Test name
Test status
Simulation time	31948519445 ps
CPU time	156.52 seconds
Started	Aug 11 07:06:17 PM PDT 24
Finished	Aug 11 07:08:53 PM PDT 24
Peak memory	283700 kb
Host	smart-f286edc4-86fc-42e7-8608-d8ef9fde4320
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400931152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.400931152
Directory	/workspace/14.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3439185285
Short name	T154
Test name
Test status
Simulation time	71497157316 ps
CPU time	1770.84 seconds
Started	Aug 11 07:06:15 PM PDT 24
Finished	Aug 11 07:35:46 PM PDT 24
Peak memory	1519744 kb
Host	smart-33be9910-fae3-4eeb-a2a8-dec7f60a466d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3439185285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3439185285
Directory	/workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3002939853
Short name	T337
Test name
Test status
Simulation time	14147579 ps
CPU time	0.91 seconds
Started	Aug 11 07:06:09 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	211736 kb
Host	smart-c54f75d1-8403-441d-8011-74ca3aee7a95
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002939853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_volatile_unlock_smoke.3002939853
Directory	/workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_alert_test.184864480
Short name	T708
Test name
Test status
Simulation time	47192651 ps
CPU time	0.9 seconds
Started	Aug 11 07:06:25 PM PDT 24
Finished	Aug 11 07:06:25 PM PDT 24
Peak memory	208736 kb
Host	smart-7cc8a03d-ac15-4829-bea0-35c7749c48ce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184864480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.184864480
Directory	/workspace/15.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.lc_ctrl_errors.2934603175
Short name	T336
Test name
Test status
Simulation time	425310164 ps
CPU time	13.25 seconds
Started	Aug 11 07:06:14 PM PDT 24
Finished	Aug 11 07:06:27 PM PDT 24
Peak memory	225888 kb
Host	smart-ab03298f-22e9-453b-afa5-8efcbce059ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934603175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2934603175
Directory	/workspace/15.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_access.2191066161
Short name	T851
Test name
Test status
Simulation time	3198031109 ps
CPU time	8.38 seconds
Started	Aug 11 07:06:15 PM PDT 24
Finished	Aug 11 07:06:24 PM PDT 24
Peak memory	217776 kb
Host	smart-4648a1fa-3bbc-4710-b46c-f7ec04ef677f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191066161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2191066161
Directory	/workspace/15.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_errors.4276367899
Short name	T453
Test name
Test status
Simulation time	1849463301 ps
CPU time	25.82 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:42 PM PDT 24
Peak memory	218812 kb
Host	smart-7a7fb5e6-ed4c-48ec-9c99-7be95ae9acc8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276367899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e rrors.4276367899
Directory	/workspace/15.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.489162237
Short name	T756
Test name
Test status
Simulation time	998071318 ps
CPU time	7.35 seconds
Started	Aug 11 07:06:17 PM PDT 24
Finished	Aug 11 07:06:24 PM PDT 24
Peak memory	218008 kb
Host	smart-87ee853f-0ac8-48f7-97b1-13574ca6b0e4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489162237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag _prog_failure.489162237
Directory	/workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_smoke.2769483888
Short name	T719
Test name
Test status
Simulation time	155403941 ps
CPU time	4.61 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:21 PM PDT 24
Peak memory	217444 kb
Host	smart-22e67b6f-6bcc-4a06-b7a4-0039ef22cd74
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769483888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke .2769483888
Directory	/workspace/15.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2924211822
Short name	T682
Test name
Test status
Simulation time	3129303001 ps
CPU time	95.12 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:07:51 PM PDT 24
Peak memory	268288 kb
Host	smart-da8b3d05-473c-4a12-9b47-bae50a2b072e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924211822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_state_failure.2924211822
Directory	/workspace/15.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.823972866
Short name	T369
Test name
Test status
Simulation time	4660406372 ps
CPU time	23.79 seconds
Started	Aug 11 07:06:15 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	250840 kb
Host	smart-48c2c811-be5b-4310-b9d2-0ec3806ce59e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823972866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_ jtag_state_post_trans.823972866
Directory	/workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_prog_failure.2734213284
Short name	T182
Test name
Test status
Simulation time	30051806 ps
CPU time	1.43 seconds
Started	Aug 11 07:06:18 PM PDT 24
Finished	Aug 11 07:06:19 PM PDT 24
Peak memory	218028 kb
Host	smart-87e807f3-54f3-4d73-98b9-7e6a1b908ff2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734213284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2734213284
Directory	/workspace/15.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_mubi.4085159234
Short name	T537
Test name
Test status
Simulation time	402269109 ps
CPU time	10.4 seconds
Started	Aug 11 07:06:14 PM PDT 24
Finished	Aug 11 07:06:24 PM PDT 24
Peak memory	225908 kb
Host	smart-b12c545d-5eaf-440e-9fd7-70c5f4042c5a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085159234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.4085159234
Directory	/workspace/15.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_digest.1641171735
Short name	T692
Test name
Test status
Simulation time	1252485369 ps
CPU time	11.38 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:32 PM PDT 24
Peak memory	218048 kb
Host	smart-913045f7-0d0d-4ce3-98ce-d79a38096e75
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641171735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d igest.1641171735
Directory	/workspace/15.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_mux.100787375
Short name	T416
Test name
Test status
Simulation time	2176902117 ps
CPU time	11.99 seconds
Started	Aug 11 07:06:17 PM PDT 24
Finished	Aug 11 07:06:29 PM PDT 24
Peak memory	218084 kb
Host	smart-d2f989aa-80b7-4020-a498-475acef95f57
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100787375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.100787375
Directory	/workspace/15.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/15.lc_ctrl_security_escalation.3182267335
Short name	T542
Test name
Test status
Simulation time	206899776 ps
CPU time	8.73 seconds
Started	Aug 11 07:06:21 PM PDT 24
Finished	Aug 11 07:06:30 PM PDT 24
Peak memory	225012 kb
Host	smart-652a3da9-e1f7-4815-92f1-4c522d10ca81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3182267335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3182267335
Directory	/workspace/15.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/15.lc_ctrl_smoke.3942518518
Short name	T585
Test name
Test status
Simulation time	118061049 ps
CPU time	1.51 seconds
Started	Aug 11 07:06:15 PM PDT 24
Finished	Aug 11 07:06:16 PM PDT 24
Peak memory	213592 kb
Host	smart-a8cd4ae9-e91f-4457-b0e5-5ed75c8210c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942518518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3942518518
Directory	/workspace/15.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_failure.3004441843
Short name	T680
Test name
Test status
Simulation time	214812070 ps
CPU time	27.92 seconds
Started	Aug 11 07:06:16 PM PDT 24
Finished	Aug 11 07:06:44 PM PDT 24
Peak memory	245836 kb
Host	smart-91c6512d-4ab3-4ce4-a113-90447ead172e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004441843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3004441843
Directory	/workspace/15.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_post_trans.3003142569
Short name	T427
Test name
Test status
Simulation time	1332143164 ps
CPU time	7.85 seconds
Started	Aug 11 07:06:21 PM PDT 24
Finished	Aug 11 07:06:29 PM PDT 24
Peak memory	250628 kb
Host	smart-9774fa68-622f-41b8-984d-657efe53d42a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003142569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3003142569
Directory	/workspace/15.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all.977218490
Short name	T752
Test name
Test status
Simulation time	8330878644 ps
CPU time	61 seconds
Started	Aug 11 07:06:23 PM PDT 24
Finished	Aug 11 07:07:25 PM PDT 24
Peak memory	226036 kb
Host	smart-5d150bb2-1f27-445f-a63f-49afef91e00a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977218490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.977218490
Directory	/workspace/15.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.807545420
Short name	T335
Test name
Test status
Simulation time	20896463 ps
CPU time	1.28 seconds
Started	Aug 11 07:06:15 PM PDT 24
Finished	Aug 11 07:06:17 PM PDT 24
Peak memory	217504 kb
Host	smart-c7143b78-8d94-4d82-8ec7-d7cbf182f950
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807545420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct rl_volatile_unlock_smoke.807545420
Directory	/workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_errors.3908631140
Short name	T517
Test name
Test status
Simulation time	199774604 ps
CPU time	8.26 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:29 PM PDT 24
Peak memory	218112 kb
Host	smart-4f441122-4eb1-4922-97e6-811cd76c8a44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908631140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3908631140
Directory	/workspace/16.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_access.3978807978
Short name	T187
Test name
Test status
Simulation time	3849191341 ps
CPU time	19.15 seconds
Started	Aug 11 07:06:22 PM PDT 24
Finished	Aug 11 07:06:41 PM PDT 24
Peak memory	217656 kb
Host	smart-11041b8c-e98a-4f9f-a694-65628c1fe2fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978807978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3978807978
Directory	/workspace/16.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_errors.1002443684
Short name	T557
Test name
Test status
Simulation time	1185866776 ps
CPU time	36.17 seconds
Started	Aug 11 07:06:21 PM PDT 24
Finished	Aug 11 07:06:57 PM PDT 24
Peak memory	225880 kb
Host	smart-6fd52d37-c085-443a-9fd3-215d3dc0b84f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002443684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e rrors.1002443684
Directory	/workspace/16.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1787216934
Short name	T835
Test name
Test status
Simulation time	2075303728 ps
CPU time	14.57 seconds
Started	Aug 11 07:06:23 PM PDT 24
Finished	Aug 11 07:06:38 PM PDT 24
Peak memory	218048 kb
Host	smart-73494e27-f05c-4154-8685-1bc1deecf386
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787216934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_prog_failure.1787216934
Directory	/workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_smoke.2157402111
Short name	T183
Test name
Test status
Simulation time	1467043500 ps
CPU time	17.82 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:38 PM PDT 24
Peak memory	217456 kb
Host	smart-0f484ea1-72c5-4ba4-8854-078bd1d871a8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157402111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke .2157402111
Directory	/workspace/16.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1622414761
Short name	T431
Test name
Test status
Simulation time	4531774711 ps
CPU time	35.85 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:56 PM PDT 24
Peak memory	275368 kb
Host	smart-5261711f-0987-402a-b9a1-00499dcbd5a6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622414761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt ag_state_failure.1622414761
Directory	/workspace/16.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1391090629
Short name	T732
Test name
Test status
Simulation time	969877292 ps
CPU time	14.55 seconds
Started	Aug 11 07:06:22 PM PDT 24
Finished	Aug 11 07:06:37 PM PDT 24
Peak memory	226192 kb
Host	smart-77135469-c494-49e1-aeba-54543b3d9028
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391090629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_state_post_trans.1391090629
Directory	/workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_prog_failure.1556411644
Short name	T549
Test name
Test status
Simulation time	189869714 ps
CPU time	2.78 seconds
Started	Aug 11 07:06:21 PM PDT 24
Finished	Aug 11 07:06:24 PM PDT 24
Peak memory	218080 kb
Host	smart-a25e7ece-db79-4427-ae72-d87cb2b5ecfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556411644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1556411644
Directory	/workspace/16.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_mubi.2860478888
Short name	T633
Test name
Test status
Simulation time	531955240 ps
CPU time	10.71 seconds
Started	Aug 11 07:06:29 PM PDT 24
Finished	Aug 11 07:06:40 PM PDT 24
Peak memory	218140 kb
Host	smart-f8e122d7-0034-4bf3-887c-c412264dfc11
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860478888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2860478888
Directory	/workspace/16.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_digest.1320921115
Short name	T862
Test name
Test status
Simulation time	412820776 ps
CPU time	15.84 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:36 PM PDT 24
Peak memory	225856 kb
Host	smart-f56b1389-1eab-4d5f-a45d-9b8f23500a1d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320921115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d igest.1320921115
Directory	/workspace/16.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_mux.3014702524
Short name	T586
Test name
Test status
Simulation time	297951665 ps
CPU time	10.12 seconds
Started	Aug 11 07:06:22 PM PDT 24
Finished	Aug 11 07:06:32 PM PDT 24
Peak memory	218016 kb
Host	smart-0d7b4344-feec-49c7-9f75-d70c1c092a8d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014702524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux. 3014702524
Directory	/workspace/16.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/16.lc_ctrl_security_escalation.457538687
Short name	T569
Test name
Test status
Simulation time	373741033 ps
CPU time	9.21 seconds
Started	Aug 11 07:06:22 PM PDT 24
Finished	Aug 11 07:06:31 PM PDT 24
Peak memory	225424 kb
Host	smart-49ad8ba1-d183-4bd4-8c4b-ba24f465e0e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457538687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.457538687
Directory	/workspace/16.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/16.lc_ctrl_smoke.318992528
Short name	T707
Test name
Test status
Simulation time	154606811 ps
CPU time	4.24 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:24 PM PDT 24
Peak memory	217408 kb
Host	smart-82512908-1911-4eb1-90f4-2a15442585c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=318992528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.318992528
Directory	/workspace/16.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_failure.3251194236
Short name	T553
Test name
Test status
Simulation time	1215907727 ps
CPU time	24.17 seconds
Started	Aug 11 07:06:30 PM PDT 24
Finished	Aug 11 07:06:54 PM PDT 24
Peak memory	250824 kb
Host	smart-0bde76cb-fea0-4b8d-b106-98b41e63c44a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251194236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3251194236
Directory	/workspace/16.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_post_trans.3260371739
Short name	T652
Test name
Test status
Simulation time	293606185 ps
CPU time	8.58 seconds
Started	Aug 11 07:06:21 PM PDT 24
Finished	Aug 11 07:06:30 PM PDT 24
Peak memory	250824 kb
Host	smart-4d761303-7a81-4c90-8e3c-a5f59d40303e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260371739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3260371739
Directory	/workspace/16.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all.3350208636
Short name	T366
Test name
Test status
Simulation time	14133030793 ps
CPU time	45.64 seconds
Started	Aug 11 07:06:19 PM PDT 24
Finished	Aug 11 07:07:05 PM PDT 24
Peak memory	250864 kb
Host	smart-137181a5-771b-422a-aeda-12da5e20d787
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350208636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.3350208636
Directory	/workspace/16.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2015335969
Short name	T166
Test name
Test status
Simulation time	395011623927 ps
CPU time	1159.51 seconds
Started	Aug 11 07:06:19 PM PDT 24
Finished	Aug 11 07:25:39 PM PDT 24
Peak memory	513148 kb
Host	smart-378c85fd-c210-45ad-a5d7-bfe2c4241a41
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2015335969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2015335969
Directory	/workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1712319459
Short name	T392
Test name
Test status
Simulation time	44027235 ps
CPU time	1.03 seconds
Started	Aug 11 07:06:23 PM PDT 24
Finished	Aug 11 07:06:24 PM PDT 24
Peak memory	211684 kb
Host	smart-a6ce8266-a3ca-460b-b77b-b9f64ee658f6
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712319459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c trl_volatile_unlock_smoke.1712319459
Directory	/workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_alert_test.2752458382
Short name	T172
Test name
Test status
Simulation time	101430460 ps
CPU time	0.93 seconds
Started	Aug 11 07:06:32 PM PDT 24
Finished	Aug 11 07:06:33 PM PDT 24
Peak memory	208712 kb
Host	smart-e2ff7b84-261c-4add-9b94-8f1b2cc4374e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752458382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2752458382
Directory	/workspace/17.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.lc_ctrl_errors.1931393195
Short name	T731
Test name
Test status
Simulation time	756385250 ps
CPU time	8.33 seconds
Started	Aug 11 07:06:22 PM PDT 24
Finished	Aug 11 07:06:30 PM PDT 24
Peak memory	225928 kb
Host	smart-85facff4-165d-48e9-9ab7-a482de74695f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931393195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1931393195
Directory	/workspace/17.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_access.1626039847
Short name	T30
Test name
Test status
Simulation time	1270342375 ps
CPU time	28.09 seconds
Started	Aug 11 07:06:22 PM PDT 24
Finished	Aug 11 07:06:50 PM PDT 24
Peak memory	217356 kb
Host	smart-a24df2ad-be77-4d65-82f3-7a266e99f16b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626039847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1626039847
Directory	/workspace/17.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_errors.597509109
Short name	T37
Test name
Test status
Simulation time	16480871028 ps
CPU time	129.86 seconds
Started	Aug 11 07:06:19 PM PDT 24
Finished	Aug 11 07:08:28 PM PDT 24
Peak memory	221032 kb
Host	smart-4ac27293-b315-416a-9a19-7a8cf75e1e5f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597509109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er rors.597509109
Directory	/workspace/17.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3682888847
Short name	T458
Test name
Test status
Simulation time	418223854 ps
CPU time	12.62 seconds
Started	Aug 11 07:06:30 PM PDT 24
Finished	Aug 11 07:06:43 PM PDT 24
Peak memory	221872 kb
Host	smart-dbf4079d-17c4-47a0-b70c-45cc51c410c3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682888847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_prog_failure.3682888847
Directory	/workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_smoke.875943705
Short name	T286
Test name
Test status
Simulation time	240407724 ps
CPU time	4.04 seconds
Started	Aug 11 07:06:19 PM PDT 24
Finished	Aug 11 07:06:23 PM PDT 24
Peak memory	217512 kb
Host	smart-55e98eb0-0b93-4240-b873-232eeafe923b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875943705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke. 875943705
Directory	/workspace/17.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2102849902
Short name	T245
Test name
Test status
Simulation time	8499657179 ps
CPU time	128.97 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:08:29 PM PDT 24
Peak memory	283548 kb
Host	smart-f0efb0e6-3374-4e45-8882-1fcd76376628
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102849902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt ag_state_failure.2102849902
Directory	/workspace/17.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2312442060
Short name	T796
Test name
Test status
Simulation time	508715093 ps
CPU time	11.45 seconds
Started	Aug 11 07:06:22 PM PDT 24
Finished	Aug 11 07:06:33 PM PDT 24
Peak memory	250284 kb
Host	smart-c6f0e718-2601-411a-bf3d-4904f85acc58
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312442060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_state_post_trans.2312442060
Directory	/workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_prog_failure.2829682198
Short name	T379
Test name
Test status
Simulation time	19649713 ps
CPU time	1.5 seconds
Started	Aug 11 07:06:21 PM PDT 24
Finished	Aug 11 07:06:22 PM PDT 24
Peak memory	218064 kb
Host	smart-de1c61fb-0980-4415-af96-8828a0b54a01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2829682198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2829682198
Directory	/workspace/17.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_mubi.524679091
Short name	T727
Test name
Test status
Simulation time	6327404636 ps
CPU time	14.53 seconds
Started	Aug 11 07:06:25 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	226024 kb
Host	smart-81976111-8d74-47c6-99c4-330a39b3d902
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524679091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.524679091
Directory	/workspace/17.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_digest.2201829931
Short name	T781
Test name
Test status
Simulation time	837459672 ps
CPU time	17.68 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:38 PM PDT 24
Peak memory	225848 kb
Host	smart-e32c07d8-65eb-40d1-8cc3-ac5c3ee8d405
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201829931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d igest.2201829931
Directory	/workspace/17.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_mux.469672580
Short name	T401
Test name
Test status
Simulation time	289220342 ps
CPU time	9.26 seconds
Started	Aug 11 07:06:22 PM PDT 24
Finished	Aug 11 07:06:31 PM PDT 24
Peak memory	218004 kb
Host	smart-07e7d3c9-321b-40fb-9350-003985126afa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469672580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.469672580
Directory	/workspace/17.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/17.lc_ctrl_security_escalation.2570170888
Short name	T667
Test name
Test status
Simulation time	1589342922 ps
CPU time	6.62 seconds
Started	Aug 11 07:06:30 PM PDT 24
Finished	Aug 11 07:06:37 PM PDT 24
Peak memory	224336 kb
Host	smart-0389824a-a275-4cbc-bef0-39068e715f9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2570170888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2570170888
Directory	/workspace/17.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/17.lc_ctrl_smoke.2049727222
Short name	T782
Test name
Test status
Simulation time	158879302 ps
CPU time	2.6 seconds
Started	Aug 11 07:06:21 PM PDT 24
Finished	Aug 11 07:06:24 PM PDT 24
Peak memory	223392 kb
Host	smart-8570b007-ca87-47d4-8373-9f929d09a9d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049727222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2049727222
Directory	/workspace/17.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_failure.2758394172
Short name	T280
Test name
Test status
Simulation time	1249524281 ps
CPU time	22.22 seconds
Started	Aug 11 07:06:19 PM PDT 24
Finished	Aug 11 07:06:41 PM PDT 24
Peak memory	250720 kb
Host	smart-72556106-81a2-485c-831f-edcc216baeb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758394172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2758394172
Directory	/workspace/17.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_post_trans.1280246149
Short name	T716
Test name
Test status
Simulation time	470617935 ps
CPU time	6.89 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:06:27 PM PDT 24
Peak memory	246884 kb
Host	smart-6dfabf8e-c473-4f49-a7a5-f97ed7a4ef15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280246149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1280246149
Directory	/workspace/17.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all.2230977748
Short name	T643
Test name
Test status
Simulation time	2350003205 ps
CPU time	73.57 seconds
Started	Aug 11 07:06:20 PM PDT 24
Finished	Aug 11 07:07:33 PM PDT 24
Peak memory	250916 kb
Host	smart-45d01c6e-ed1c-4339-9ded-8de48881a770
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230977748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all.2230977748
Directory	/workspace/17.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3243777625
Short name	T575
Test name
Test status
Simulation time	13633622 ps
CPU time	0.94 seconds
Started	Aug 11 07:06:25 PM PDT 24
Finished	Aug 11 07:06:26 PM PDT 24
Peak memory	211832 kb
Host	smart-7c6341a6-713c-40fc-b087-c3d9bc15e661
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243777625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_volatile_unlock_smoke.3243777625
Directory	/workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_alert_test.1573234724
Short name	T800
Test name
Test status
Simulation time	47288894 ps
CPU time	0.85 seconds
Started	Aug 11 07:06:26 PM PDT 24
Finished	Aug 11 07:06:27 PM PDT 24
Peak memory	208544 kb
Host	smart-04905943-717a-4788-a07f-97b26c3b46f9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573234724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1573234724
Directory	/workspace/18.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.lc_ctrl_errors.994991333
Short name	T722
Test name
Test status
Simulation time	1036011768 ps
CPU time	20.23 seconds
Started	Aug 11 07:06:30 PM PDT 24
Finished	Aug 11 07:06:50 PM PDT 24
Peak memory	218096 kb
Host	smart-3712abed-efa8-478c-9bed-f8d877a7a1dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=994991333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.994991333
Directory	/workspace/18.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_access.153999710
Short name	T578
Test name
Test status
Simulation time	3395094085 ps
CPU time	11 seconds
Started	Aug 11 07:06:26 PM PDT 24
Finished	Aug 11 07:06:38 PM PDT 24
Peak memory	217628 kb
Host	smart-ad63b6b3-ee32-404d-9513-4ff336aa106e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153999710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.153999710
Directory	/workspace/18.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_errors.1316549095
Short name	T288
Test name
Test status
Simulation time	1118452650 ps
CPU time	36.01 seconds
Started	Aug 11 07:06:29 PM PDT 24
Finished	Aug 11 07:07:05 PM PDT 24
Peak memory	217996 kb
Host	smart-06a639ec-1273-4a96-8da6-b5923e069d21
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316549095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e rrors.1316549095
Directory	/workspace/18.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3908240974
Short name	T101
Test name
Test status
Simulation time	2465849856 ps
CPU time	7.73 seconds
Started	Aug 11 07:06:26 PM PDT 24
Finished	Aug 11 07:06:34 PM PDT 24
Peak memory	218164 kb
Host	smart-501b0d67-84ec-4b6e-9e6c-9b5e5c06226b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908240974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_prog_failure.3908240974
Directory	/workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_smoke.471307705
Short name	T68
Test name
Test status
Simulation time	2143530431 ps
CPU time	6.55 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:35 PM PDT 24
Peak memory	217444 kb
Host	smart-cf7482a5-4800-4ca5-8f44-a103459e560e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471307705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke. 471307705
Directory	/workspace/18.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.26112117
Short name	T471
Test name
Test status
Simulation time	3668849391 ps
CPU time	68.44 seconds
Started	Aug 11 07:06:27 PM PDT 24
Finished	Aug 11 07:07:36 PM PDT 24
Peak memory	275516 kb
Host	smart-2ba24509-829a-438d-98aa-64bbdd69b92c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag _state_failure.26112117
Directory	/workspace/18.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3744977644
Short name	T628
Test name
Test status
Simulation time	1196054508 ps
CPU time	15.51 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:44 PM PDT 24
Peak memory	250736 kb
Host	smart-930160ee-a806-48bf-91f7-8636e7505774
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744977644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_state_post_trans.3744977644
Directory	/workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_prog_failure.2910096805
Short name	T624
Test name
Test status
Simulation time	120755511 ps
CPU time	3.48 seconds
Started	Aug 11 07:06:27 PM PDT 24
Finished	Aug 11 07:06:30 PM PDT 24
Peak memory	218124 kb
Host	smart-ad9549e0-dd85-4a84-8e06-c4be1c6368ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910096805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2910096805
Directory	/workspace/18.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_mubi.3364766272
Short name	T64
Test name
Test status
Simulation time	259170092 ps
CPU time	12.05 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:40 PM PDT 24
Peak memory	218760 kb
Host	smart-2ae0e78a-d521-4660-a176-38ed895f5736
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364766272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3364766272
Directory	/workspace/18.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_digest.880314637
Short name	T320
Test name
Test status
Simulation time	516624200 ps
CPU time	19.43 seconds
Started	Aug 11 07:06:26 PM PDT 24
Finished	Aug 11 07:06:46 PM PDT 24
Peak memory	218032 kb
Host	smart-6b52e129-f8aa-4239-8b2c-eae96890a455
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880314637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di gest.880314637
Directory	/workspace/18.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_mux.1050824163
Short name	T728
Test name
Test status
Simulation time	877639069 ps
CPU time	8.42 seconds
Started	Aug 11 07:06:30 PM PDT 24
Finished	Aug 11 07:06:38 PM PDT 24
Peak memory	218028 kb
Host	smart-7fd91084-0020-42fc-a30e-3d1f8ceed282
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050824163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux. 1050824163
Directory	/workspace/18.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/18.lc_ctrl_security_escalation.513446376
Short name	T46
Test name
Test status
Simulation time	218050239 ps
CPU time	9.17 seconds
Started	Aug 11 07:06:30 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	225064 kb
Host	smart-5a540898-0d50-4d50-8100-2fc0f87ca1ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513446376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.513446376
Directory	/workspace/18.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/18.lc_ctrl_smoke.1266968896
Short name	T595
Test name
Test status
Simulation time	34076980 ps
CPU time	1.27 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:30 PM PDT 24
Peak memory	221620 kb
Host	smart-ae595d4e-25cc-472c-8085-ea248e9a2fac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266968896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1266968896
Directory	/workspace/18.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_failure.2945567670
Short name	T872
Test name
Test status
Simulation time	642078380 ps
CPU time	27.12 seconds
Started	Aug 11 07:06:27 PM PDT 24
Finished	Aug 11 07:06:55 PM PDT 24
Peak memory	250784 kb
Host	smart-f80dcc1d-6228-474d-9c59-e28cd0618751
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945567670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2945567670
Directory	/workspace/18.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_post_trans.4251578734
Short name	T108
Test name
Test status
Simulation time	258376582 ps
CPU time	7.33 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:36 PM PDT 24
Peak memory	250804 kb
Host	smart-e2d97559-5e2a-4b1b-8b06-380a4e864de3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251578734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.4251578734
Directory	/workspace/18.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all.2398572017
Short name	T656
Test name
Test status
Simulation time	18769777848 ps
CPU time	133.67 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:08:42 PM PDT 24
Peak memory	251792 kb
Host	smart-685bd2d1-5a90-434e-823d-cc1d32bcb502
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398572017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.2398572017
Directory	/workspace/18.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3664886660
Short name	T169
Test name
Test status
Simulation time	84610949476 ps
CPU time	916.07 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:21:45 PM PDT 24
Peak memory	496780 kb
Host	smart-76cbeb97-6406-4b2a-94a1-b793c1cafa7e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3664886660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3664886660
Directory	/workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2046176056
Short name	T372
Test name
Test status
Simulation time	15369235 ps
CPU time	1.11 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:29 PM PDT 24
Peak memory	212816 kb
Host	smart-fc8caa57-f7cc-478f-a2f1-24725bf04f59
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046176056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_volatile_unlock_smoke.2046176056
Directory	/workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_alert_test.243551800
Short name	T473
Test name
Test status
Simulation time	63383245 ps
CPU time	1.2 seconds
Started	Aug 11 07:06:34 PM PDT 24
Finished	Aug 11 07:06:36 PM PDT 24
Peak memory	208768 kb
Host	smart-80c2e650-a887-4783-a7f4-b3d022838578
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243551800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.243551800
Directory	/workspace/19.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.lc_ctrl_errors.24320494
Short name	T772
Test name
Test status
Simulation time	1529572069 ps
CPU time	17.63 seconds
Started	Aug 11 07:06:30 PM PDT 24
Finished	Aug 11 07:06:48 PM PDT 24
Peak memory	218084 kb
Host	smart-05a94b54-c34b-4644-968f-663fef0c4531
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24320494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.24320494
Directory	/workspace/19.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_access.578680598
Short name	T814
Test name
Test status
Simulation time	548208531 ps
CPU time	6.55 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:06:40 PM PDT 24
Peak memory	217244 kb
Host	smart-a67187e5-5108-49b7-8572-90b099a2ad3f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578680598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.578680598
Directory	/workspace/19.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_errors.2024121719
Short name	T485
Test name
Test status
Simulation time	12194965205 ps
CPU time	40.14 seconds
Started	Aug 11 07:06:34 PM PDT 24
Finished	Aug 11 07:07:14 PM PDT 24
Peak memory	226016 kb
Host	smart-4b013e90-4b2e-4c5b-bc90-6c11dcff3338
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024121719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e rrors.2024121719
Directory	/workspace/19.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3556599782
Short name	T558
Test name
Test status
Simulation time	171634852 ps
CPU time	6.24 seconds
Started	Aug 11 07:06:27 PM PDT 24
Finished	Aug 11 07:06:34 PM PDT 24
Peak memory	222812 kb
Host	smart-9acf751f-862f-4e3a-8e44-7ea361aef6ff
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556599782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_prog_failure.3556599782
Directory	/workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_smoke.995153122
Short name	T434
Test name
Test status
Simulation time	94016218 ps
CPU time	3.47 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:31 PM PDT 24
Peak memory	217448 kb
Host	smart-e940c810-0f07-45a4-97f0-20bb171b47b2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995153122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke. 995153122
Directory	/workspace/19.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1199044192
Short name	T24
Test name
Test status
Simulation time	1357319353 ps
CPU time	58.58 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:07:27 PM PDT 24
Peak memory	275340 kb
Host	smart-d872ccc3-a77f-4fad-a0a1-96c18cc95889
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199044192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt ag_state_failure.1199044192
Directory	/workspace/19.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1785788481
Short name	T495
Test name
Test status
Simulation time	861176501 ps
CPU time	9.08 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:37 PM PDT 24
Peak memory	222964 kb
Host	smart-cf1fa05c-be3d-4682-b44b-e7a77c61a30b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785788481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_state_post_trans.1785788481
Directory	/workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_prog_failure.562164657
Short name	T373
Test name
Test status
Simulation time	186513396 ps
CPU time	3.04 seconds
Started	Aug 11 07:06:27 PM PDT 24
Finished	Aug 11 07:06:30 PM PDT 24
Peak memory	218292 kb
Host	smart-13ff237e-d6b1-42cc-ad6d-7fa8a1a8b67a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562164657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.562164657
Directory	/workspace/19.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_mubi.4247720338
Short name	T794
Test name
Test status
Simulation time	349858274 ps
CPU time	12.84 seconds
Started	Aug 11 07:06:32 PM PDT 24
Finished	Aug 11 07:06:45 PM PDT 24
Peak memory	225912 kb
Host	smart-239a213f-f8d8-4282-a707-57602ce84821
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247720338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4247720338
Directory	/workspace/19.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_digest.4167379537
Short name	T677
Test name
Test status
Simulation time	1523501373 ps
CPU time	14.97 seconds
Started	Aug 11 07:06:32 PM PDT 24
Finished	Aug 11 07:06:47 PM PDT 24
Peak memory	217984 kb
Host	smart-0b6716e5-e5f6-49c5-8568-a1a0aa513146
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167379537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d igest.4167379537
Directory	/workspace/19.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/19.lc_ctrl_security_escalation.1488234985
Short name	T380
Test name
Test status
Simulation time	5150361575 ps
CPU time	8.88 seconds
Started	Aug 11 07:06:30 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	218304 kb
Host	smart-b5ad2eeb-3d86-4e51-b0bc-00d1fb480b41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488234985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1488234985
Directory	/workspace/19.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/19.lc_ctrl_smoke.3574424050
Short name	T81
Test name
Test status
Simulation time	126445058 ps
CPU time	6.25 seconds
Started	Aug 11 07:06:26 PM PDT 24
Finished	Aug 11 07:06:33 PM PDT 24
Peak memory	217444 kb
Host	smart-634dc2c1-7703-41de-912b-dd7bc75d78ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574424050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3574424050
Directory	/workspace/19.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_failure.486531828
Short name	T546
Test name
Test status
Simulation time	359661911 ps
CPU time	26.48 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:54 PM PDT 24
Peak memory	250792 kb
Host	smart-1284bd08-177f-48b2-9419-5e4e7bc59266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486531828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.486531828
Directory	/workspace/19.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_post_trans.2411419484
Short name	T406
Test name
Test status
Simulation time	204470521 ps
CPU time	7.06 seconds
Started	Aug 11 07:06:28 PM PDT 24
Finished	Aug 11 07:06:35 PM PDT 24
Peak memory	246148 kb
Host	smart-fdc77c1f-a467-4491-8176-5657c3b7850b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411419484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2411419484
Directory	/workspace/19.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all.760476135
Short name	T501
Test name
Test status
Simulation time	1134389370 ps
CPU time	45.6 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:07:19 PM PDT 24
Peak memory	252652 kb
Host	smart-537ac320-7fc3-4c33-a3d1-447ed52185b6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760476135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.760476135
Directory	/workspace/19.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3682654088
Short name	T785
Test name
Test status
Simulation time	11104878 ps
CPU time	0.88 seconds
Started	Aug 11 07:06:29 PM PDT 24
Finished	Aug 11 07:06:30 PM PDT 24
Peak memory	211696 kb
Host	smart-7c3e7018-c0df-441e-8135-08b5b80d82e7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682654088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c trl_volatile_unlock_smoke.3682654088
Directory	/workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_alert_test.3511220246
Short name	T779
Test name
Test status
Simulation time	44518365 ps
CPU time	1.03 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:05:31 PM PDT 24
Peak memory	208740 kb
Host	smart-2679d496-06d2-464a-9520-d5637e4226fa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511220246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3511220246
Directory	/workspace/2.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.lc_ctrl_errors.3217780721
Short name	T40
Test name
Test status
Simulation time	1307925109 ps
CPU time	11.04 seconds
Started	Aug 11 07:05:29 PM PDT 24
Finished	Aug 11 07:05:40 PM PDT 24
Peak memory	218048 kb
Host	smart-4563f9a5-35ed-41de-922a-947cc36d8f1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217780721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3217780721
Directory	/workspace/2.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_access.3941943890
Short name	T415
Test name
Test status
Simulation time	293835311 ps
CPU time	8.39 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:28 PM PDT 24
Peak memory	217096 kb
Host	smart-da091248-5494-4e3a-a88f-6b36c17f6840
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941943890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3941943890
Directory	/workspace/2.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_errors.4115677083
Short name	T38
Test name
Test status
Simulation time	6410718435 ps
CPU time	47.9 seconds
Started	Aug 11 07:05:29 PM PDT 24
Finished	Aug 11 07:06:17 PM PDT 24
Peak memory	218192 kb
Host	smart-9c5fde28-d04a-4101-91a2-e778ae054eb0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115677083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er rors.4115677083
Directory	/workspace/2.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_priority.2726378430
Short name	T69
Test name
Test status
Simulation time	2343016309 ps
CPU time	5.44 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:25 PM PDT 24
Peak memory	217304 kb
Host	smart-70bbc829-cbf0-4780-8fa7-da99e48e0916
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726378430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2 726378430
Directory	/workspace/2.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.53690463
Short name	T492
Test name
Test status
Simulation time	2722177866 ps
CPU time	5.77 seconds
Started	Aug 11 07:05:18 PM PDT 24
Finished	Aug 11 07:05:24 PM PDT 24
Peak memory	221956 kb
Host	smart-8e5329bf-8783-44cd-b75c-ce337154feff
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53690463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_p rog_failure.53690463
Directory	/workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1611925143
Short name	T674
Test name
Test status
Simulation time	2424791765 ps
CPU time	18.5 seconds
Started	Aug 11 07:05:22 PM PDT 24
Finished	Aug 11 07:05:41 PM PDT 24
Peak memory	217740 kb
Host	smart-89e78501-49fe-4fb8-b669-d6ce46dc1a64
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611925143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_regwen_during_op.1611925143
Directory	/workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_smoke.3375466879
Short name	T303
Test name
Test status
Simulation time	3253950568 ps
CPU time	5.98 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:26 PM PDT 24
Peak memory	217564 kb
Host	smart-102ae86b-ae54-40fb-bebc-9ea20876ba29
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375466879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke. 3375466879
Directory	/workspace/2.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2656564742
Short name	T237
Test name
Test status
Simulation time	10356708752 ps
CPU time	52.51 seconds
Started	Aug 11 07:05:22 PM PDT 24
Finished	Aug 11 07:06:15 PM PDT 24
Peak memory	280600 kb
Host	smart-20a03af8-d37f-40bb-9f26-304db3c0fe2b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656564742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta g_state_failure.2656564742
Directory	/workspace/2.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3863996650
Short name	T675
Test name
Test status
Simulation time	1019584235 ps
CPU time	14 seconds
Started	Aug 11 07:05:18 PM PDT 24
Finished	Aug 11 07:05:33 PM PDT 24
Peak memory	250692 kb
Host	smart-bedaca91-f899-45e8-9b9e-e73c5b392c3b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863996650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_state_post_trans.3863996650
Directory	/workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_prog_failure.3932983369
Short name	T648
Test name
Test status
Simulation time	142582627 ps
CPU time	2.49 seconds
Started	Aug 11 07:05:18 PM PDT 24
Finished	Aug 11 07:05:21 PM PDT 24
Peak memory	222104 kb
Host	smart-9b82cba3-fcac-4330-a628-bc91018c2b2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932983369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3932983369
Directory	/workspace/2.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_regwen_during_op.857836782
Short name	T404
Test name
Test status
Simulation time	988309928 ps
CPU time	15.7 seconds
Started	Aug 11 07:05:29 PM PDT 24
Finished	Aug 11 07:05:45 PM PDT 24
Peak memory	213920 kb
Host	smart-6b8c5b48-3246-4c8b-9340-86aa490d4aab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857836782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.857836782
Directory	/workspace/2.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_cm.442310969
Short name	T91
Test name
Test status
Simulation time	1033011803 ps
CPU time	44.37 seconds
Started	Aug 11 07:05:26 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	269556 kb
Host	smart-b2e91d7c-4e52-4d02-9b9a-d6b5780f75f2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442310969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.442310969
Directory	/workspace/2.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_mubi.148937775
Short name	T308
Test name
Test status
Simulation time	193747761 ps
CPU time	9.92 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:29 PM PDT 24
Peak memory	225844 kb
Host	smart-a8376b03-426f-4183-a651-6b5c22030196
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148937775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.148937775
Directory	/workspace/2.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_digest.1174462708
Short name	T383
Test name
Test status
Simulation time	1073009011 ps
CPU time	9.66 seconds
Started	Aug 11 07:05:27 PM PDT 24
Finished	Aug 11 07:05:37 PM PDT 24
Peak memory	225804 kb
Host	smart-9d8e7d94-b586-4ee2-b4e0-5850d6fb1c91
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174462708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di gest.1174462708
Directory	/workspace/2.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_mux.3571732751
Short name	T703
Test name
Test status
Simulation time	374913299 ps
CPU time	12.33 seconds
Started	Aug 11 07:05:26 PM PDT 24
Finished	Aug 11 07:05:39 PM PDT 24
Peak memory	225820 kb
Host	smart-c4ede442-4227-484a-a191-668f8bab1e27
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571732751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3 571732751
Directory	/workspace/2.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/2.lc_ctrl_security_escalation.3443931627
Short name	T681
Test name
Test status
Simulation time	1282101798 ps
CPU time	8.24 seconds
Started	Aug 11 07:05:18 PM PDT 24
Finished	Aug 11 07:05:26 PM PDT 24
Peak memory	225860 kb
Host	smart-cd58ac66-089b-42a8-8550-7333dad940ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443931627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3443931627
Directory	/workspace/2.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/2.lc_ctrl_smoke.2874591633
Short name	T103
Test name
Test status
Simulation time	146324987 ps
CPU time	2.32 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:21 PM PDT 24
Peak memory	214024 kb
Host	smart-a53796af-e845-418d-9b8b-22740abc0250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874591633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2874591633
Directory	/workspace/2.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_failure.311918039
Short name	T462
Test name
Test status
Simulation time	258816002 ps
CPU time	29.11 seconds
Started	Aug 11 07:05:19 PM PDT 24
Finished	Aug 11 07:05:48 PM PDT 24
Peak memory	250792 kb
Host	smart-74ed28c2-e6d6-417e-856e-00039c36ed90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311918039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.311918039
Directory	/workspace/2.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_post_trans.4268894692
Short name	T90
Test name
Test status
Simulation time	1804658150 ps
CPU time	8.46 seconds
Started	Aug 11 07:05:23 PM PDT 24
Finished	Aug 11 07:05:32 PM PDT 24
Peak memory	250788 kb
Host	smart-9a4abd14-e317-43e0-9583-de9f1faec1bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268894692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.4268894692
Directory	/workspace/2.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_stress_all.3933115745
Short name	T76
Test name
Test status
Simulation time	14283345807 ps
CPU time	154.1 seconds
Started	Aug 11 07:05:28 PM PDT 24
Finished	Aug 11 07:08:02 PM PDT 24
Peak memory	267276 kb
Host	smart-42e6ad0d-a605-4dde-a843-c5ececd9d0e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933115745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.3933115745
Directory	/workspace/2.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4017172872
Short name	T766
Test name
Test status
Simulation time	34284001 ps
CPU time	0.88 seconds
Started	Aug 11 07:05:29 PM PDT 24
Finished	Aug 11 07:05:30 PM PDT 24
Peak memory	211700 kb
Host	smart-32c00295-d29f-4fd0-9f72-9bc685579722
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017172872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct rl_volatile_unlock_smoke.4017172872
Directory	/workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_alert_test.225303890
Short name	T559
Test name
Test status
Simulation time	17706858 ps
CPU time	1.12 seconds
Started	Aug 11 07:06:34 PM PDT 24
Finished	Aug 11 07:06:35 PM PDT 24
Peak memory	208812 kb
Host	smart-427918ed-b8e8-453d-bba0-43c26e3f6286
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225303890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.225303890
Directory	/workspace/20.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.lc_ctrl_errors.2342055438
Short name	T520
Test name
Test status
Simulation time	1302594401 ps
CPU time	20.03 seconds
Started	Aug 11 07:06:34 PM PDT 24
Finished	Aug 11 07:06:54 PM PDT 24
Peak memory	218068 kb
Host	smart-3becd8a5-a390-4f97-8d3e-513a822db3f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342055438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2342055438
Directory	/workspace/20.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/20.lc_ctrl_jtag_access.1392558286
Short name	T417
Test name
Test status
Simulation time	845700560 ps
CPU time	5.61 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	216880 kb
Host	smart-bbd077b7-8a7a-4025-95ff-d3da6c431b76
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392558286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1392558286
Directory	/workspace/20.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/20.lc_ctrl_prog_failure.199163005
Short name	T829
Test name
Test status
Simulation time	73081536 ps
CPU time	1.95 seconds
Started	Aug 11 07:06:34 PM PDT 24
Finished	Aug 11 07:06:36 PM PDT 24
Peak memory	218072 kb
Host	smart-16a594ba-6f9d-44c5-b960-9d66ac6f209a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199163005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.199163005
Directory	/workspace/20.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_mubi.3519397286
Short name	T452
Test name
Test status
Simulation time	617684774 ps
CPU time	24.83 seconds
Started	Aug 11 07:06:32 PM PDT 24
Finished	Aug 11 07:06:57 PM PDT 24
Peak memory	225932 kb
Host	smart-2b0a2654-a009-4904-af94-9f8339ef2c8d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519397286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3519397286
Directory	/workspace/20.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_digest.1769667670
Short name	T730
Test name
Test status
Simulation time	530207133 ps
CPU time	9.67 seconds
Started	Aug 11 07:06:34 PM PDT 24
Finished	Aug 11 07:06:43 PM PDT 24
Peak memory	225652 kb
Host	smart-a9f6ac0e-c42f-466e-98b4-1fe4a456da1c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769667670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d igest.1769667670
Directory	/workspace/20.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_mux.2046754878
Short name	T644
Test name
Test status
Simulation time	478424472 ps
CPU time	8.91 seconds
Started	Aug 11 07:06:31 PM PDT 24
Finished	Aug 11 07:06:40 PM PDT 24
Peak memory	217920 kb
Host	smart-5cefc54d-0dcd-4515-8411-7ed13a37cdf9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046754878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux. 2046754878
Directory	/workspace/20.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/20.lc_ctrl_security_escalation.1704665236
Short name	T776
Test name
Test status
Simulation time	476462018 ps
CPU time	7.26 seconds
Started	Aug 11 07:06:35 PM PDT 24
Finished	Aug 11 07:06:42 PM PDT 24
Peak memory	218156 kb
Host	smart-78432a89-a49f-4341-b9d2-8511edaed8e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704665236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1704665236
Directory	/workspace/20.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/20.lc_ctrl_smoke.67990886
Short name	T3
Test name
Test status
Simulation time	55567815 ps
CPU time	2.96 seconds
Started	Aug 11 07:06:31 PM PDT 24
Finished	Aug 11 07:06:34 PM PDT 24
Peak memory	217488 kb
Host	smart-12174174-6b2a-4c13-94e1-731e0678dd1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67990886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.67990886
Directory	/workspace/20.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_failure.1132423130
Short name	T12
Test name
Test status
Simulation time	282989104 ps
CPU time	21.75 seconds
Started	Aug 11 07:06:32 PM PDT 24
Finished	Aug 11 07:06:54 PM PDT 24
Peak memory	250804 kb
Host	smart-92152a98-2bb3-47bb-9a3a-ab171e071687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132423130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1132423130
Directory	/workspace/20.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_post_trans.2600526820
Short name	T857
Test name
Test status
Simulation time	78246232 ps
CPU time	8.34 seconds
Started	Aug 11 07:06:32 PM PDT 24
Finished	Aug 11 07:06:41 PM PDT 24
Peak memory	250808 kb
Host	smart-767a4ea7-a8b3-4d9f-84bb-ae65949c96da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600526820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2600526820
Directory	/workspace/20.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all.3807875773
Short name	T734
Test name
Test status
Simulation time	26367911983 ps
CPU time	199.78 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:09:53 PM PDT 24
Peak memory	268564 kb
Host	smart-230edbf6-c3f0-4ec5-98b1-38541ba53c86
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807875773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.3807875773
Directory	/workspace/20.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2315312146
Short name	T148
Test name
Test status
Simulation time	34958284738 ps
CPU time	598.87 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:16:32 PM PDT 24
Peak memory	267384 kb
Host	smart-f0c5dd48-ece4-48d7-9827-26f6af58dea6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2315312146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2315312146
Directory	/workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2725505691
Short name	T342
Test name
Test status
Simulation time	36353643 ps
CPU time	0.89 seconds
Started	Aug 11 07:06:31 PM PDT 24
Finished	Aug 11 07:06:32 PM PDT 24
Peak memory	211648 kb
Host	smart-995413d3-eca8-49ed-909d-99ac352863b2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725505691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c trl_volatile_unlock_smoke.2725505691
Directory	/workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_alert_test.2671284975
Short name	T302
Test name
Test status
Simulation time	72938247 ps
CPU time	0.94 seconds
Started	Aug 11 07:06:41 PM PDT 24
Finished	Aug 11 07:06:42 PM PDT 24
Peak memory	208748 kb
Host	smart-698e2349-faf7-4a55-900f-facde56744c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671284975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2671284975
Directory	/workspace/21.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.lc_ctrl_errors.3989082740
Short name	T292
Test name
Test status
Simulation time	1554372428 ps
CPU time	15.78 seconds
Started	Aug 11 07:06:34 PM PDT 24
Finished	Aug 11 07:06:50 PM PDT 24
Peak memory	218128 kb
Host	smart-be7975e7-4fe0-4f7f-a6fc-167886885471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989082740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3989082740
Directory	/workspace/21.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/21.lc_ctrl_jtag_access.4024475455
Short name	T505
Test name
Test status
Simulation time	317204576 ps
CPU time	9.38 seconds
Started	Aug 11 07:06:39 PM PDT 24
Finished	Aug 11 07:06:49 PM PDT 24
Peak memory	217244 kb
Host	smart-8693d737-e9e0-4792-a592-dac8341beb82
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024475455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4024475455
Directory	/workspace/21.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/21.lc_ctrl_prog_failure.3676230940
Short name	T269
Test name
Test status
Simulation time	337606268 ps
CPU time	1.77 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:06:35 PM PDT 24
Peak memory	221944 kb
Host	smart-b75c4365-59db-4bd2-89a7-1d23f1d311ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676230940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3676230940
Directory	/workspace/21.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_mubi.1214511861
Short name	T854
Test name
Test status
Simulation time	2369351097 ps
CPU time	19.41 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:06:58 PM PDT 24
Peak memory	226016 kb
Host	smart-930d189a-bf6b-429c-bbe6-82a2b19752c9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214511861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1214511861
Directory	/workspace/21.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_digest.3126136976
Short name	T11
Test name
Test status
Simulation time	809410579 ps
CPU time	10.89 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:06:49 PM PDT 24
Peak memory	225840 kb
Host	smart-2db81618-54a6-4f6c-af9c-2b01c39b57fa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126136976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d igest.3126136976
Directory	/workspace/21.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_mux.1719617251
Short name	T591
Test name
Test status
Simulation time	3330406341 ps
CPU time	7.69 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:06:46 PM PDT 24
Peak memory	218320 kb
Host	smart-57277158-85a2-402a-935f-024c1f27311f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719617251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux. 1719617251
Directory	/workspace/21.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/21.lc_ctrl_security_escalation.4219977770
Short name	T444
Test name
Test status
Simulation time	230469977 ps
CPU time	7.68 seconds
Started	Aug 11 07:06:36 PM PDT 24
Finished	Aug 11 07:06:44 PM PDT 24
Peak memory	218160 kb
Host	smart-adc86c18-f6a9-4215-8ef9-d7087058dfb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219977770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.4219977770
Directory	/workspace/21.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/21.lc_ctrl_smoke.2587840563
Short name	T539
Test name
Test status
Simulation time	185016900 ps
CPU time	1.72 seconds
Started	Aug 11 07:06:34 PM PDT 24
Finished	Aug 11 07:06:36 PM PDT 24
Peak memory	217508 kb
Host	smart-bf982d80-aae8-4cb2-8797-a6e3dd418a5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587840563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2587840563
Directory	/workspace/21.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_failure.3474671988
Short name	T450
Test name
Test status
Simulation time	6779917882 ps
CPU time	33.65 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:07:07 PM PDT 24
Peak memory	250940 kb
Host	smart-dac549c9-fec7-4d37-bdfc-104d470ae471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474671988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3474671988
Directory	/workspace/21.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_post_trans.1886880406
Short name	T364
Test name
Test status
Simulation time	74802689 ps
CPU time	6.57 seconds
Started	Aug 11 07:06:32 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	242488 kb
Host	smart-98814ff0-8893-47db-bd73-f5c39a924a35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886880406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1886880406
Directory	/workspace/21.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all.1148823997
Short name	T749
Test name
Test status
Simulation time	23201316183 ps
CPU time	207.45 seconds
Started	Aug 11 07:06:39 PM PDT 24
Finished	Aug 11 07:10:06 PM PDT 24
Peak memory	278616 kb
Host	smart-5aae1cf0-9d08-444c-a597-3dfd381a2202
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148823997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.1148823997
Directory	/workspace/21.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1309717557
Short name	T16
Test name
Test status
Simulation time	17044902340 ps
CPU time	628.2 seconds
Started	Aug 11 07:06:42 PM PDT 24
Finished	Aug 11 07:17:10 PM PDT 24
Peak memory	496764 kb
Host	smart-5d6afb76-2463-4193-8985-4ea581674200
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1309717557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1309717557
Directory	/workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1418656276
Short name	T548
Test name
Test status
Simulation time	59616405 ps
CPU time	0.89 seconds
Started	Aug 11 07:06:33 PM PDT 24
Finished	Aug 11 07:06:34 PM PDT 24
Peak memory	211664 kb
Host	smart-f26f7464-1c42-4155-9219-141589d19333
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418656276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c trl_volatile_unlock_smoke.1418656276
Directory	/workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_alert_test.3154524055
Short name	T270
Test name
Test status
Simulation time	60707047 ps
CPU time	1.07 seconds
Started	Aug 11 07:06:37 PM PDT 24
Finished	Aug 11 07:06:38 PM PDT 24
Peak memory	208752 kb
Host	smart-010490e7-a930-4eb5-b791-7d71312d3542
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154524055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3154524055
Directory	/workspace/22.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.lc_ctrl_errors.1824610508
Short name	T497
Test name
Test status
Simulation time	600487443 ps
CPU time	12.45 seconds
Started	Aug 11 07:06:39 PM PDT 24
Finished	Aug 11 07:06:51 PM PDT 24
Peak memory	225892 kb
Host	smart-3009b15f-c983-4110-8d4f-8f511a59f530
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824610508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1824610508
Directory	/workspace/22.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/22.lc_ctrl_jtag_access.1137326266
Short name	T329
Test name
Test status
Simulation time	333352072 ps
CPU time	5.28 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:06:43 PM PDT 24
Peak memory	217228 kb
Host	smart-a02e72a1-f4ea-4197-9c73-7c4b6bbb41fa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137326266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1137326266
Directory	/workspace/22.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/22.lc_ctrl_prog_failure.2383932897
Short name	T390
Test name
Test status
Simulation time	393952226 ps
CPU time	2.23 seconds
Started	Aug 11 07:06:40 PM PDT 24
Finished	Aug 11 07:06:42 PM PDT 24
Peak memory	221732 kb
Host	smart-c4f55e9b-a531-448c-b83d-663c1c43f48c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383932897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2383932897
Directory	/workspace/22.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_mubi.3835035055
Short name	T515
Test name
Test status
Simulation time	462710533 ps
CPU time	13.28 seconds
Started	Aug 11 07:06:42 PM PDT 24
Finished	Aug 11 07:06:55 PM PDT 24
Peak memory	225924 kb
Host	smart-f82f1d7e-5696-4fd1-be55-de30455a7b4f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835035055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3835035055
Directory	/workspace/22.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_digest.1202696156
Short name	T555
Test name
Test status
Simulation time	1671219651 ps
CPU time	12.81 seconds
Started	Aug 11 07:06:42 PM PDT 24
Finished	Aug 11 07:06:55 PM PDT 24
Peak memory	225776 kb
Host	smart-78b3c98d-adb8-44a7-b333-472864c39a5a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202696156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d igest.1202696156
Directory	/workspace/22.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_mux.274042508
Short name	T333
Test name
Test status
Simulation time	1608860883 ps
CPU time	8.59 seconds
Started	Aug 11 07:06:44 PM PDT 24
Finished	Aug 11 07:06:53 PM PDT 24
Peak memory	217980 kb
Host	smart-25e58e15-4b8b-471c-98d5-9f5d72a717c0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274042508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.274042508
Directory	/workspace/22.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/22.lc_ctrl_smoke.39735029
Short name	T257
Test name
Test status
Simulation time	76959275 ps
CPU time	1.27 seconds
Started	Aug 11 07:06:43 PM PDT 24
Finished	Aug 11 07:06:45 PM PDT 24
Peak memory	213420 kb
Host	smart-30334ca4-d966-4caa-b149-72ca462617de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39735029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.39735029
Directory	/workspace/22.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_failure.1538367331
Short name	T788
Test name
Test status
Simulation time	195874548 ps
CPU time	28.2 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:07:06 PM PDT 24
Peak memory	250792 kb
Host	smart-e75e477d-0e8f-4d08-b8b3-421226fd9b26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538367331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1538367331
Directory	/workspace/22.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_post_trans.3691383134
Short name	T327
Test name
Test status
Simulation time	290586654 ps
CPU time	7.75 seconds
Started	Aug 11 07:06:39 PM PDT 24
Finished	Aug 11 07:06:47 PM PDT 24
Peak memory	250792 kb
Host	smart-11c0445a-303a-4ce6-a043-8fe8d402bdf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691383134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3691383134
Directory	/workspace/22.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all.886706489
Short name	T463
Test name
Test status
Simulation time	6131794718 ps
CPU time	116.92 seconds
Started	Aug 11 07:06:42 PM PDT 24
Finished	Aug 11 07:08:39 PM PDT 24
Peak memory	283656 kb
Host	smart-43ac071f-e244-4ec2-8b68-b478dc61b791
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886706489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.886706489
Directory	/workspace/22.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.4234002328
Short name	T56
Test name
Test status
Simulation time	16894125623 ps
CPU time	335.47 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:12:14 PM PDT 24
Peak memory	332952 kb
Host	smart-41573282-35c1-42b0-8715-f148f7a8f544
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4234002328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.4234002328
Directory	/workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.419424306
Short name	T421
Test name
Test status
Simulation time	34630472 ps
CPU time	0.89 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	211928 kb
Host	smart-e2b1f882-1c25-42d9-9781-c1b58bafc114
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419424306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct rl_volatile_unlock_smoke.419424306
Directory	/workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_alert_test.1975527870
Short name	T165
Test name
Test status
Simulation time	167151116 ps
CPU time	1.05 seconds
Started	Aug 11 07:06:45 PM PDT 24
Finished	Aug 11 07:06:46 PM PDT 24
Peak memory	208844 kb
Host	smart-bf5e3f9b-5e90-400e-801d-791f13b6854c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975527870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1975527870
Directory	/workspace/23.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.lc_ctrl_errors.1596749795
Short name	T493
Test name
Test status
Simulation time	359815860 ps
CPU time	11.81 seconds
Started	Aug 11 07:06:43 PM PDT 24
Finished	Aug 11 07:06:55 PM PDT 24
Peak memory	225788 kb
Host	smart-4f7bc501-4fe3-4500-babc-80afb4884f0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596749795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1596749795
Directory	/workspace/23.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/23.lc_ctrl_jtag_access.1772269180
Short name	T295
Test name
Test status
Simulation time	49910453 ps
CPU time	1.36 seconds
Started	Aug 11 07:06:43 PM PDT 24
Finished	Aug 11 07:06:44 PM PDT 24
Peak memory	216816 kb
Host	smart-6af63ffa-1cb3-489e-b458-7cb63d2e0cb5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772269180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1772269180
Directory	/workspace/23.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/23.lc_ctrl_prog_failure.629257556
Short name	T385
Test name
Test status
Simulation time	114082951 ps
CPU time	4.5 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:06:43 PM PDT 24
Peak memory	218064 kb
Host	smart-ce7e12e3-3500-4b96-9678-52175c8f0750
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629257556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.629257556
Directory	/workspace/23.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_digest.1273307772
Short name	T836
Test name
Test status
Simulation time	386466123 ps
CPU time	10.25 seconds
Started	Aug 11 07:06:44 PM PDT 24
Finished	Aug 11 07:06:54 PM PDT 24
Peak memory	225784 kb
Host	smart-d6959299-652a-4ae7-a188-1b8aabdaab65
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273307772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d igest.1273307772
Directory	/workspace/23.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_mux.2311692385
Short name	T100
Test name
Test status
Simulation time	2153700902 ps
CPU time	9.91 seconds
Started	Aug 11 07:06:51 PM PDT 24
Finished	Aug 11 07:07:01 PM PDT 24
Peak memory	218072 kb
Host	smart-28414cf3-972d-4510-9fb1-2beea9d64ccd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311692385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux. 2311692385
Directory	/workspace/23.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/23.lc_ctrl_security_escalation.2867629190
Short name	T374
Test name
Test status
Simulation time	3360601923 ps
CPU time	10.22 seconds
Started	Aug 11 07:06:50 PM PDT 24
Finished	Aug 11 07:07:00 PM PDT 24
Peak memory	226164 kb
Host	smart-a084d98e-340d-44a5-8934-66a928f5cdcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867629190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2867629190
Directory	/workspace/23.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/23.lc_ctrl_smoke.2755425766
Short name	T563
Test name
Test status
Simulation time	604385406 ps
CPU time	2.58 seconds
Started	Aug 11 07:06:37 PM PDT 24
Finished	Aug 11 07:06:40 PM PDT 24
Peak memory	214384 kb
Host	smart-e1e60b1f-bfaf-4162-bbec-ee2b40bea5f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755425766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2755425766
Directory	/workspace/23.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_failure.3429933451
Short name	T192
Test name
Test status
Simulation time	562074209 ps
CPU time	32.45 seconds
Started	Aug 11 07:06:42 PM PDT 24
Finished	Aug 11 07:07:15 PM PDT 24
Peak memory	250804 kb
Host	smart-f2e24701-684c-4b61-872b-148be7c04175
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429933451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3429933451
Directory	/workspace/23.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_post_trans.345863617
Short name	T795
Test name
Test status
Simulation time	638809637 ps
CPU time	2.59 seconds
Started	Aug 11 07:06:42 PM PDT 24
Finished	Aug 11 07:06:45 PM PDT 24
Peak memory	221160 kb
Host	smart-a2a34037-11a7-4513-b717-979396ae026d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345863617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.345863617
Directory	/workspace/23.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all.3379954417
Short name	T714
Test name
Test status
Simulation time	29898394206 ps
CPU time	147.02 seconds
Started	Aug 11 07:06:51 PM PDT 24
Finished	Aug 11 07:09:18 PM PDT 24
Peak memory	275484 kb
Host	smart-3526e218-9afe-49a6-a50c-d7309b3e4f94
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379954417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.3379954417
Directory	/workspace/23.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2233659092
Short name	T509
Test name
Test status
Simulation time	16537437 ps
CPU time	0.96 seconds
Started	Aug 11 07:06:38 PM PDT 24
Finished	Aug 11 07:06:39 PM PDT 24
Peak memory	211672 kb
Host	smart-f4eacd75-8602-4b9f-85ce-f6486d638ca8
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233659092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c trl_volatile_unlock_smoke.2233659092
Directory	/workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_alert_test.879308701
Short name	T254
Test name
Test status
Simulation time	62187183 ps
CPU time	1.06 seconds
Started	Aug 11 07:06:50 PM PDT 24
Finished	Aug 11 07:06:52 PM PDT 24
Peak memory	208732 kb
Host	smart-11598010-723e-4404-a256-cb8e949a739d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879308701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.879308701
Directory	/workspace/24.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.lc_ctrl_errors.1625379876
Short name	T811
Test name
Test status
Simulation time	727007312 ps
CPU time	17.47 seconds
Started	Aug 11 07:06:44 PM PDT 24
Finished	Aug 11 07:07:01 PM PDT 24
Peak memory	218092 kb
Host	smart-c48a9307-a1a5-430d-b0b7-6a4f75a9ba8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625379876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1625379876
Directory	/workspace/24.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/24.lc_ctrl_jtag_access.1868530097
Short name	T616
Test name
Test status
Simulation time	1720664669 ps
CPU time	5.67 seconds
Started	Aug 11 07:06:43 PM PDT 24
Finished	Aug 11 07:06:49 PM PDT 24
Peak memory	216988 kb
Host	smart-46aeb0ad-4d99-456f-8073-3309d8ac7186
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868530097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1868530097
Directory	/workspace/24.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_mubi.864703875
Short name	T818
Test name
Test status
Simulation time	2128577210 ps
CPU time	15.23 seconds
Started	Aug 11 07:06:50 PM PDT 24
Finished	Aug 11 07:07:06 PM PDT 24
Peak memory	225924 kb
Host	smart-69561526-3821-4596-a240-5a0787290e11
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864703875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.864703875
Directory	/workspace/24.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_digest.1584653859
Short name	T20
Test name
Test status
Simulation time	302632581 ps
CPU time	8.31 seconds
Started	Aug 11 07:06:52 PM PDT 24
Finished	Aug 11 07:07:01 PM PDT 24
Peak memory	225844 kb
Host	smart-65058cb1-e5d9-412e-8686-b7e8d1693512
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584653859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d igest.1584653859
Directory	/workspace/24.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_mux.1865894605
Short name	T360
Test name
Test status
Simulation time	688108349 ps
CPU time	12.8 seconds
Started	Aug 11 07:06:51 PM PDT 24
Finished	Aug 11 07:07:04 PM PDT 24
Peak memory	225692 kb
Host	smart-391c3d34-fef8-4529-be9d-994429585d4a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865894605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux. 1865894605
Directory	/workspace/24.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/24.lc_ctrl_security_escalation.817551338
Short name	T325
Test name
Test status
Simulation time	5184704077 ps
CPU time	7.02 seconds
Started	Aug 11 07:06:44 PM PDT 24
Finished	Aug 11 07:06:52 PM PDT 24
Peak memory	225444 kb
Host	smart-b2441931-f076-48cc-8c22-6ed8d89aee4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817551338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.817551338
Directory	/workspace/24.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/24.lc_ctrl_smoke.4146429344
Short name	T724
Test name
Test status
Simulation time	858009362 ps
CPU time	12.44 seconds
Started	Aug 11 07:06:44 PM PDT 24
Finished	Aug 11 07:06:56 PM PDT 24
Peak memory	217576 kb
Host	smart-6741763f-0cd1-4127-b684-a616da02fe6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146429344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.4146429344
Directory	/workspace/24.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_failure.1010605371
Short name	T701
Test name
Test status
Simulation time	156551360 ps
CPU time	20.07 seconds
Started	Aug 11 07:06:50 PM PDT 24
Finished	Aug 11 07:07:11 PM PDT 24
Peak memory	250908 kb
Host	smart-b5249629-192b-4aa0-9056-764b6dc5e7b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010605371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1010605371
Directory	/workspace/24.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_post_trans.4026304995
Short name	T478
Test name
Test status
Simulation time	649716623 ps
CPU time	9.89 seconds
Started	Aug 11 07:06:43 PM PDT 24
Finished	Aug 11 07:06:53 PM PDT 24
Peak memory	250812 kb
Host	smart-dda673a7-8817-47f4-b688-1d685ee97859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026304995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4026304995
Directory	/workspace/24.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all.2426116246
Short name	T405
Test name
Test status
Simulation time	6691362547 ps
CPU time	80.31 seconds
Started	Aug 11 07:06:52 PM PDT 24
Finished	Aug 11 07:08:12 PM PDT 24
Peak memory	272784 kb
Host	smart-e218eccd-f2d0-45a4-a798-1fbee010ac88
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426116246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all.2426116246
Directory	/workspace/24.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1211348747
Short name	T150
Test name
Test status
Simulation time	20709785306 ps
CPU time	332.18 seconds
Started	Aug 11 07:06:52 PM PDT 24
Finished	Aug 11 07:12:24 PM PDT 24
Peak memory	283836 kb
Host	smart-3ab88c21-c18a-44af-a5a6-2261f8dc7330
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1211348747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1211348747
Directory	/workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1728090744
Short name	T626
Test name
Test status
Simulation time	15447372 ps
CPU time	0.91 seconds
Started	Aug 11 07:06:45 PM PDT 24
Finished	Aug 11 07:06:46 PM PDT 24
Peak memory	211636 kb
Host	smart-109ec521-c34d-4d66-8015-fa61642eabdc
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728090744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c trl_volatile_unlock_smoke.1728090744
Directory	/workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_alert_test.2280343093
Short name	T784
Test name
Test status
Simulation time	59787512 ps
CPU time	1.04 seconds
Started	Aug 11 07:07:00 PM PDT 24
Finished	Aug 11 07:07:01 PM PDT 24
Peak memory	208740 kb
Host	smart-a6c95497-932a-455e-bcb4-07ac3e942cba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280343093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2280343093
Directory	/workspace/25.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.lc_ctrl_errors.471269855
Short name	T235
Test name
Test status
Simulation time	1039528634 ps
CPU time	12.3 seconds
Started	Aug 11 07:06:58 PM PDT 24
Finished	Aug 11 07:07:11 PM PDT 24
Peak memory	218080 kb
Host	smart-d7f39553-768b-4871-9b46-f9722f1212c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471269855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.471269855
Directory	/workspace/25.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/25.lc_ctrl_jtag_access.2707279361
Short name	T783
Test name
Test status
Simulation time	2305295746 ps
CPU time	5.36 seconds
Started	Aug 11 07:06:56 PM PDT 24
Finished	Aug 11 07:07:02 PM PDT 24
Peak memory	217276 kb
Host	smart-87b9142e-96e3-4344-9f71-ff47fcdee483
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707279361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2707279361
Directory	/workspace/25.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/25.lc_ctrl_prog_failure.2228188146
Short name	T855
Test name
Test status
Simulation time	40872552 ps
CPU time	2.17 seconds
Started	Aug 11 07:06:58 PM PDT 24
Finished	Aug 11 07:07:00 PM PDT 24
Peak memory	218044 kb
Host	smart-ac7a20c0-6e55-443b-80c7-46060516c732
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228188146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2228188146
Directory	/workspace/25.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_mubi.1679164642
Short name	T561
Test name
Test status
Simulation time	276214751 ps
CPU time	11.48 seconds
Started	Aug 11 07:06:58 PM PDT 24
Finished	Aug 11 07:07:09 PM PDT 24
Peak memory	225908 kb
Host	smart-067decfb-448c-4e87-bcce-fd5dcf06ab5e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679164642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1679164642
Directory	/workspace/25.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_digest.2836176903
Short name	T253
Test name
Test status
Simulation time	2209573347 ps
CPU time	14.51 seconds
Started	Aug 11 07:06:55 PM PDT 24
Finished	Aug 11 07:07:10 PM PDT 24
Peak memory	218084 kb
Host	smart-40b14f30-ce64-4c9c-8df0-ff9b59235506
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836176903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d igest.2836176903
Directory	/workspace/25.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_mux.731998897
Short name	T568
Test name
Test status
Simulation time	349976591 ps
CPU time	8.55 seconds
Started	Aug 11 07:06:57 PM PDT 24
Finished	Aug 11 07:07:06 PM PDT 24
Peak memory	218040 kb
Host	smart-49a87992-119d-4f97-8086-d4d0b23c9bee
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731998897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.731998897
Directory	/workspace/25.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/25.lc_ctrl_security_escalation.104831160
Short name	T702
Test name
Test status
Simulation time	403797479 ps
CPU time	8.73 seconds
Started	Aug 11 07:06:57 PM PDT 24
Finished	Aug 11 07:07:06 PM PDT 24
Peak memory	225192 kb
Host	smart-24e7a138-18ab-4910-82f7-f0cdc20cf6f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104831160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.104831160
Directory	/workspace/25.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/25.lc_ctrl_smoke.2670475143
Short name	T435
Test name
Test status
Simulation time	71505484 ps
CPU time	4.17 seconds
Started	Aug 11 07:06:51 PM PDT 24
Finished	Aug 11 07:06:56 PM PDT 24
Peak memory	217540 kb
Host	smart-0b632999-18b4-4eba-9d70-f38b9fa5bec2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670475143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2670475143
Directory	/workspace/25.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_failure.2367987285
Short name	T279
Test name
Test status
Simulation time	209221316 ps
CPU time	22.96 seconds
Started	Aug 11 07:06:52 PM PDT 24
Finished	Aug 11 07:07:15 PM PDT 24
Peak memory	250756 kb
Host	smart-9cb21c1b-b233-468b-a41a-809593e81f91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367987285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2367987285
Directory	/workspace/25.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_post_trans.2903543995
Short name	T391
Test name
Test status
Simulation time	345470099 ps
CPU time	2.86 seconds
Started	Aug 11 07:06:53 PM PDT 24
Finished	Aug 11 07:06:56 PM PDT 24
Peak memory	218128 kb
Host	smart-95891f3a-bef9-404f-a2a2-d74a28df242a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903543995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2903543995
Directory	/workspace/25.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all.209520127
Short name	T540
Test name
Test status
Simulation time	22019438128 ps
CPU time	189.62 seconds
Started	Aug 11 07:06:58 PM PDT 24
Finished	Aug 11 07:10:07 PM PDT 24
Peak memory	283728 kb
Host	smart-2a2d75b7-0f92-409d-87f1-c6ca8e1483b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209520127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.209520127
Directory	/workspace/25.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2322658631
Short name	T619
Test name
Test status
Simulation time	41427426 ps
CPU time	0.83 seconds
Started	Aug 11 07:06:50 PM PDT 24
Finished	Aug 11 07:06:51 PM PDT 24
Peak memory	211728 kb
Host	smart-2b2c8b71-1687-4715-9472-1f09ef38b523
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322658631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c trl_volatile_unlock_smoke.2322658631
Directory	/workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_alert_test.970400896
Short name	T353
Test name
Test status
Simulation time	49545991 ps
CPU time	1.02 seconds
Started	Aug 11 07:07:03 PM PDT 24
Finished	Aug 11 07:07:04 PM PDT 24
Peak memory	208708 kb
Host	smart-2484f8f1-bdb8-4f97-98e1-cd26b0eb3f43
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970400896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.970400896
Directory	/workspace/26.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.lc_ctrl_errors.1161249303
Short name	T668
Test name
Test status
Simulation time	340239065 ps
CPU time	9.93 seconds
Started	Aug 11 07:07:03 PM PDT 24
Finished	Aug 11 07:07:13 PM PDT 24
Peak memory	225860 kb
Host	smart-73c70d8b-6c60-4027-b9c5-7ca82ea92d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161249303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1161249303
Directory	/workspace/26.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/26.lc_ctrl_jtag_access.2655185323
Short name	T330
Test name
Test status
Simulation time	466976274 ps
CPU time	6.5 seconds
Started	Aug 11 07:07:09 PM PDT 24
Finished	Aug 11 07:07:16 PM PDT 24
Peak memory	217324 kb
Host	smart-c62de3ee-8845-4a9c-bd26-5a1845ef6e4e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655185323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2655185323
Directory	/workspace/26.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/26.lc_ctrl_prog_failure.464251139
Short name	T710
Test name
Test status
Simulation time	20401462 ps
CPU time	1.64 seconds
Started	Aug 11 07:07:03 PM PDT 24
Finished	Aug 11 07:07:05 PM PDT 24
Peak memory	218092 kb
Host	smart-1b8d9619-22c3-41d5-bf06-b717c0175db9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464251139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.464251139
Directory	/workspace/26.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_mubi.3642314257
Short name	T742
Test name
Test status
Simulation time	807401722 ps
CPU time	12.24 seconds
Started	Aug 11 07:07:02 PM PDT 24
Finished	Aug 11 07:07:14 PM PDT 24
Peak memory	218092 kb
Host	smart-e4220ded-a1d4-46ab-ba29-9a47a4ba9fa2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642314257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3642314257
Directory	/workspace/26.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_digest.1561390670
Short name	T847
Test name
Test status
Simulation time	2745188019 ps
CPU time	14.73 seconds
Started	Aug 11 07:07:03 PM PDT 24
Finished	Aug 11 07:07:18 PM PDT 24
Peak memory	225972 kb
Host	smart-8360cb67-b5b9-4cfd-8c3a-a9567ec987d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561390670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d igest.1561390670
Directory	/workspace/26.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_mux.691571912
Short name	T603
Test name
Test status
Simulation time	2860680800 ps
CPU time	7.46 seconds
Started	Aug 11 07:07:02 PM PDT 24
Finished	Aug 11 07:07:09 PM PDT 24
Peak memory	225948 kb
Host	smart-14d278e0-4081-45fd-9b65-2331ed6eafa0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691571912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.691571912
Directory	/workspace/26.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/26.lc_ctrl_security_escalation.1923686221
Short name	T350
Test name
Test status
Simulation time	429760135 ps
CPU time	7.35 seconds
Started	Aug 11 07:07:02 PM PDT 24
Finished	Aug 11 07:07:09 PM PDT 24
Peak memory	224880 kb
Host	smart-573cf746-c65d-4183-b932-aa416cbdee4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923686221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1923686221
Directory	/workspace/26.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/26.lc_ctrl_smoke.747143546
Short name	T819
Test name
Test status
Simulation time	165653890 ps
CPU time	2.6 seconds
Started	Aug 11 07:07:02 PM PDT 24
Finished	Aug 11 07:07:05 PM PDT 24
Peak memory	217512 kb
Host	smart-540ee993-65b6-4b33-90a9-92723415baf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747143546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.747143546
Directory	/workspace/26.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_failure.1274824717
Short name	T439
Test name
Test status
Simulation time	1784902583 ps
CPU time	30.96 seconds
Started	Aug 11 07:07:03 PM PDT 24
Finished	Aug 11 07:07:34 PM PDT 24
Peak memory	250764 kb
Host	smart-f214faeb-cfd1-49de-8558-41b37f15cd9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274824717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1274824717
Directory	/workspace/26.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_post_trans.528286081
Short name	T349
Test name
Test status
Simulation time	205713231 ps
CPU time	6.28 seconds
Started	Aug 11 07:07:02 PM PDT 24
Finished	Aug 11 07:07:08 PM PDT 24
Peak memory	246784 kb
Host	smart-ed8c1491-8154-4702-aa53-dfe967fe1f00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528286081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.528286081
Directory	/workspace/26.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all.3468795844
Short name	T344
Test name
Test status
Simulation time	3571792423 ps
CPU time	35.64 seconds
Started	Aug 11 07:07:01 PM PDT 24
Finished	Aug 11 07:07:37 PM PDT 24
Peak memory	250928 kb
Host	smart-b4e57dc8-997b-4ce4-b7ad-dc5a4a2b24cf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468795844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all.3468795844
Directory	/workspace/26.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4245705212
Short name	T314
Test name
Test status
Simulation time	36021246 ps
CPU time	0.9 seconds
Started	Aug 11 07:07:02 PM PDT 24
Finished	Aug 11 07:07:03 PM PDT 24
Peak memory	211676 kb
Host	smart-266489a0-59ad-4b47-a8aa-f4685e751700
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245705212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c trl_volatile_unlock_smoke.4245705212
Directory	/workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_alert_test.3571764929
Short name	T589
Test name
Test status
Simulation time	59282259 ps
CPU time	0.94 seconds
Started	Aug 11 07:07:19 PM PDT 24
Finished	Aug 11 07:07:20 PM PDT 24
Peak memory	208640 kb
Host	smart-8bfcb443-ceb9-4d89-934c-129766769b82
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571764929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3571764929
Directory	/workspace/27.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.lc_ctrl_errors.2958290787
Short name	T672
Test name
Test status
Simulation time	868919192 ps
CPU time	10.65 seconds
Started	Aug 11 07:07:09 PM PDT 24
Finished	Aug 11 07:07:20 PM PDT 24
Peak memory	218060 kb
Host	smart-7f910d16-c2c7-433e-970f-629de48ce9e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958290787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2958290787
Directory	/workspace/27.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/27.lc_ctrl_jtag_access.225961449
Short name	T605
Test name
Test status
Simulation time	59109928 ps
CPU time	1.51 seconds
Started	Aug 11 07:07:12 PM PDT 24
Finished	Aug 11 07:07:13 PM PDT 24
Peak memory	216852 kb
Host	smart-4d563a59-b264-4600-8fd2-785a07e0faff
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225961449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.225961449
Directory	/workspace/27.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/27.lc_ctrl_prog_failure.2551666223
Short name	T422
Test name
Test status
Simulation time	87907206 ps
CPU time	3.17 seconds
Started	Aug 11 07:07:09 PM PDT 24
Finished	Aug 11 07:07:12 PM PDT 24
Peak memory	218092 kb
Host	smart-b1b96609-6cdb-4ec3-a73e-425a51e33116
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551666223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2551666223
Directory	/workspace/27.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_mubi.2590789250
Short name	T63
Test name
Test status
Simulation time	450665363 ps
CPU time	12.55 seconds
Started	Aug 11 07:07:12 PM PDT 24
Finished	Aug 11 07:07:24 PM PDT 24
Peak memory	225884 kb
Host	smart-aa2ac5c1-5a1f-4370-8d79-f99951faaa4a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590789250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2590789250
Directory	/workspace/27.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_digest.2437878820
Short name	T848
Test name
Test status
Simulation time	982465349 ps
CPU time	7.74 seconds
Started	Aug 11 07:07:10 PM PDT 24
Finished	Aug 11 07:07:17 PM PDT 24
Peak memory	218024 kb
Host	smart-5a751916-e0bf-4ec2-9659-605af040f327
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437878820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d igest.2437878820
Directory	/workspace/27.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_mux.941715001
Short name	T449
Test name
Test status
Simulation time	429010793 ps
CPU time	8.7 seconds
Started	Aug 11 07:07:08 PM PDT 24
Finished	Aug 11 07:07:17 PM PDT 24
Peak memory	218056 kb
Host	smart-05d253d0-1487-4e74-9427-5828085ea41d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941715001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.941715001
Directory	/workspace/27.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/27.lc_ctrl_security_escalation.1271816407
Short name	T631
Test name
Test status
Simulation time	772354604 ps
CPU time	7.07 seconds
Started	Aug 11 07:07:09 PM PDT 24
Finished	Aug 11 07:07:16 PM PDT 24
Peak memory	225936 kb
Host	smart-a5eeebb9-7905-423b-b291-aef39564137e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271816407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1271816407
Directory	/workspace/27.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/27.lc_ctrl_smoke.3005129925
Short name	T71
Test name
Test status
Simulation time	150803598 ps
CPU time	2.16 seconds
Started	Aug 11 07:07:07 PM PDT 24
Finished	Aug 11 07:07:10 PM PDT 24
Peak memory	217544 kb
Host	smart-1bd20b28-7227-4f79-8e78-97f87bf4dbc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005129925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3005129925
Directory	/workspace/27.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_failure.3476450807
Short name	T735
Test name
Test status
Simulation time	1150456027 ps
CPU time	24.45 seconds
Started	Aug 11 07:07:08 PM PDT 24
Finished	Aug 11 07:07:33 PM PDT 24
Peak memory	250892 kb
Host	smart-e48227c8-4173-4944-aebc-52ddbabf9aa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476450807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3476450807
Directory	/workspace/27.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_post_trans.4263125703
Short name	T661
Test name
Test status
Simulation time	136464363 ps
CPU time	7.35 seconds
Started	Aug 11 07:07:10 PM PDT 24
Finished	Aug 11 07:07:18 PM PDT 24
Peak memory	250756 kb
Host	smart-7a9a47c9-742d-4002-827b-86ae9eaca2f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263125703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4263125703
Directory	/workspace/27.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all.3862180931
Short name	T786
Test name
Test status
Simulation time	1265154760 ps
CPU time	50.97 seconds
Started	Aug 11 07:07:10 PM PDT 24
Finished	Aug 11 07:08:01 PM PDT 24
Peak memory	248068 kb
Host	smart-be56d04b-c5e6-4664-b9b5-f8028022d3cf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862180931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all.3862180931
Directory	/workspace/27.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3212401700
Short name	T689
Test name
Test status
Simulation time	209926681758 ps
CPU time	874.59 seconds
Started	Aug 11 07:07:15 PM PDT 24
Finished	Aug 11 07:21:50 PM PDT 24
Peak memory	300132 kb
Host	smart-dff13ae9-14e3-402b-bf89-160fb90cfd2b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3212401700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3212401700
Directory	/workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.307142433
Short name	T683
Test name
Test status
Simulation time	22190511 ps
CPU time	0.91 seconds
Started	Aug 11 07:07:08 PM PDT 24
Finished	Aug 11 07:07:10 PM PDT 24
Peak memory	212724 kb
Host	smart-6e0dfdc2-4c28-456e-b62b-82e17c9c8d2a
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307142433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct rl_volatile_unlock_smoke.307142433
Directory	/workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_alert_test.3607268635
Short name	T761
Test name
Test status
Simulation time	173704987 ps
CPU time	0.86 seconds
Started	Aug 11 07:07:18 PM PDT 24
Finished	Aug 11 07:07:19 PM PDT 24
Peak memory	208572 kb
Host	smart-612550d1-a6c6-4047-8c6a-ba92661cbd19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607268635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3607268635
Directory	/workspace/28.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.lc_ctrl_errors.258655144
Short name	T480
Test name
Test status
Simulation time	559321817 ps
CPU time	8.59 seconds
Started	Aug 11 07:07:14 PM PDT 24
Finished	Aug 11 07:07:23 PM PDT 24
Peak memory	218020 kb
Host	smart-e3791db4-1fdf-490e-a140-038a340f99a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258655144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.258655144
Directory	/workspace/28.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/28.lc_ctrl_jtag_access.3959617603
Short name	T843
Test name
Test status
Simulation time	194128153 ps
CPU time	1.38 seconds
Started	Aug 11 07:07:14 PM PDT 24
Finished	Aug 11 07:07:15 PM PDT 24
Peak memory	217004 kb
Host	smart-8c8195b5-b285-4d97-91a6-a61bc67fdbb6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959617603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3959617603
Directory	/workspace/28.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/28.lc_ctrl_prog_failure.1768859777
Short name	T774
Test name
Test status
Simulation time	47760765 ps
CPU time	2 seconds
Started	Aug 11 07:07:14 PM PDT 24
Finished	Aug 11 07:07:16 PM PDT 24
Peak memory	218072 kb
Host	smart-9a3dbc9d-53fd-4474-b5d1-b93549420f15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768859777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1768859777
Directory	/workspace/28.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_mubi.2288601564
Short name	T760
Test name
Test status
Simulation time	1201609552 ps
CPU time	19.2 seconds
Started	Aug 11 07:07:19 PM PDT 24
Finished	Aug 11 07:07:39 PM PDT 24
Peak memory	218136 kb
Host	smart-664cb988-0838-4a78-a2d4-c952ca07ede2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288601564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2288601564
Directory	/workspace/28.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_digest.4024026115
Short name	T543
Test name
Test status
Simulation time	662663456 ps
CPU time	10.73 seconds
Started	Aug 11 07:07:19 PM PDT 24
Finished	Aug 11 07:07:30 PM PDT 24
Peak memory	218028 kb
Host	smart-9784a653-0455-42e3-8eec-053d208f04ed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024026115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d igest.4024026115
Directory	/workspace/28.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_mux.1707482929
Short name	T852
Test name
Test status
Simulation time	924892032 ps
CPU time	9.12 seconds
Started	Aug 11 07:07:18 PM PDT 24
Finished	Aug 11 07:07:27 PM PDT 24
Peak memory	218064 kb
Host	smart-03b5720d-5932-4c2e-88ec-7b01d07d0497
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707482929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux. 1707482929
Directory	/workspace/28.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/28.lc_ctrl_security_escalation.466808725
Short name	T47
Test name
Test status
Simulation time	361604152 ps
CPU time	6.38 seconds
Started	Aug 11 07:07:16 PM PDT 24
Finished	Aug 11 07:07:22 PM PDT 24
Peak memory	225016 kb
Host	smart-c924dce8-84c2-4526-895d-704730833d41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466808725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.466808725
Directory	/workspace/28.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/28.lc_ctrl_smoke.2501525616
Short name	T623
Test name
Test status
Simulation time	89615054 ps
CPU time	1.52 seconds
Started	Aug 11 07:07:16 PM PDT 24
Finished	Aug 11 07:07:17 PM PDT 24
Peak memory	217524 kb
Host	smart-fa7bd0bf-dac8-41d2-958c-a49ad56812e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501525616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2501525616
Directory	/workspace/28.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_failure.1656394013
Short name	T189
Test name
Test status
Simulation time	3623197292 ps
CPU time	30.28 seconds
Started	Aug 11 07:07:14 PM PDT 24
Finished	Aug 11 07:07:45 PM PDT 24
Peak memory	250784 kb
Host	smart-8449771c-a454-49a5-9e5c-a178cecf8c68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1656394013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1656394013
Directory	/workspace/28.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_post_trans.627966113
Short name	T577
Test name
Test status
Simulation time	177059937 ps
CPU time	6.53 seconds
Started	Aug 11 07:07:18 PM PDT 24
Finished	Aug 11 07:07:25 PM PDT 24
Peak memory	246952 kb
Host	smart-6e362147-95f2-4668-b0d7-ed42b7ea0489
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627966113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.627966113
Directory	/workspace/28.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all.1068450828
Short name	T180
Test name
Test status
Simulation time	21691302352 ps
CPU time	232.89 seconds
Started	Aug 11 07:07:17 PM PDT 24
Finished	Aug 11 07:11:10 PM PDT 24
Peak memory	281044 kb
Host	smart-ef15fe32-f27f-419e-8c79-4212a02b7af6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068450828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.1068450828
Directory	/workspace/28.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.335923088
Short name	T167
Test name
Test status
Simulation time	173987246983 ps
CPU time	1062.69 seconds
Started	Aug 11 07:07:16 PM PDT 24
Finished	Aug 11 07:24:59 PM PDT 24
Peak memory	404808 kb
Host	smart-96e81629-fb0b-45ef-87ca-c5cc7f1eb22b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=335923088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.335923088
Directory	/workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2187275343
Short name	T222
Test name
Test status
Simulation time	12380591 ps
CPU time	0.92 seconds
Started	Aug 11 07:07:15 PM PDT 24
Finished	Aug 11 07:07:16 PM PDT 24
Peak memory	211628 kb
Host	smart-8e6fd32e-eab6-42e5-8a91-8c6e77a56736
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187275343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c trl_volatile_unlock_smoke.2187275343
Directory	/workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_alert_test.2620783083
Short name	T300
Test name
Test status
Simulation time	22674597 ps
CPU time	1.27 seconds
Started	Aug 11 07:07:20 PM PDT 24
Finished	Aug 11 07:07:22 PM PDT 24
Peak memory	208836 kb
Host	smart-301b565c-4c5f-4636-bd56-436f723b30c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620783083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2620783083
Directory	/workspace/29.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.lc_ctrl_errors.1358802533
Short name	T354
Test name
Test status
Simulation time	484691754 ps
CPU time	12.16 seconds
Started	Aug 11 07:07:22 PM PDT 24
Finished	Aug 11 07:07:35 PM PDT 24
Peak memory	225932 kb
Host	smart-d981d2a3-f2f5-4d71-bafd-967eea2ea238
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1358802533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1358802533
Directory	/workspace/29.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/29.lc_ctrl_jtag_access.4277082211
Short name	T8
Test name
Test status
Simulation time	364751265 ps
CPU time	10.32 seconds
Started	Aug 11 07:07:24 PM PDT 24
Finished	Aug 11 07:07:35 PM PDT 24
Peak memory	217060 kb
Host	smart-96dbfdde-3896-4aa3-9f44-767d3f09c7df
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277082211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.4277082211
Directory	/workspace/29.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/29.lc_ctrl_prog_failure.2554296983
Short name	T746
Test name
Test status
Simulation time	45259983 ps
CPU time	2.79 seconds
Started	Aug 11 07:07:21 PM PDT 24
Finished	Aug 11 07:07:24 PM PDT 24
Peak memory	222144 kb
Host	smart-fb225798-622e-461f-847d-bd86e4a8afc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554296983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2554296983
Directory	/workspace/29.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_mubi.2678551962
Short name	T745
Test name
Test status
Simulation time	744097621 ps
CPU time	13.65 seconds
Started	Aug 11 07:07:23 PM PDT 24
Finished	Aug 11 07:07:37 PM PDT 24
Peak memory	225932 kb
Host	smart-c2eb5819-9ad2-4feb-a219-9349df8f9cba
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678551962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2678551962
Directory	/workspace/29.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_digest.3637033559
Short name	T33
Test name
Test status
Simulation time	1908549461 ps
CPU time	11.02 seconds
Started	Aug 11 07:07:24 PM PDT 24
Finished	Aug 11 07:07:35 PM PDT 24
Peak memory	218044 kb
Host	smart-5b6c56c5-e864-480a-8233-f8b0e596cfee
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637033559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d igest.3637033559
Directory	/workspace/29.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_mux.1584993496
Short name	T326
Test name
Test status
Simulation time	1371062757 ps
CPU time	9.97 seconds
Started	Aug 11 07:07:22 PM PDT 24
Finished	Aug 11 07:07:32 PM PDT 24
Peak memory	217980 kb
Host	smart-3ccd58a9-6050-4b6b-991b-32306d896459
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584993496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux. 1584993496
Directory	/workspace/29.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/29.lc_ctrl_security_escalation.3705039037
Short name	T275
Test name
Test status
Simulation time	1153392475 ps
CPU time	9.06 seconds
Started	Aug 11 07:07:20 PM PDT 24
Finished	Aug 11 07:07:29 PM PDT 24
Peak memory	225548 kb
Host	smart-5f86cd56-6bd8-41dd-91fb-d66f40fa518c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705039037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3705039037
Directory	/workspace/29.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/29.lc_ctrl_smoke.3434074515
Short name	T856
Test name
Test status
Simulation time	90676701 ps
CPU time	1.2 seconds
Started	Aug 11 07:07:25 PM PDT 24
Finished	Aug 11 07:07:26 PM PDT 24
Peak memory	217524 kb
Host	smart-4d1830b7-f7dd-457b-aff3-0eb198dc7ab4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3434074515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3434074515
Directory	/workspace/29.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_failure.1885003008
Short name	T384
Test name
Test status
Simulation time	5983365479 ps
CPU time	29.82 seconds
Started	Aug 11 07:07:21 PM PDT 24
Finished	Aug 11 07:07:51 PM PDT 24
Peak memory	250896 kb
Host	smart-3d3baeba-f5f7-4f37-82b6-c5ca0376e293
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885003008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1885003008
Directory	/workspace/29.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_post_trans.1581102578
Short name	T244
Test name
Test status
Simulation time	67370020 ps
CPU time	3.16 seconds
Started	Aug 11 07:07:21 PM PDT 24
Finished	Aug 11 07:07:24 PM PDT 24
Peak memory	226216 kb
Host	smart-8ec54677-f319-41a2-9f5a-787a8e6bd1be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581102578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1581102578
Directory	/workspace/29.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all.1229648922
Short name	T106
Test name
Test status
Simulation time	12856326508 ps
CPU time	382.97 seconds
Started	Aug 11 07:07:22 PM PDT 24
Finished	Aug 11 07:13:45 PM PDT 24
Peak memory	268172 kb
Host	smart-db3e393b-879d-4d03-a5e7-be4176e9d21e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229648922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.1229648922
Directory	/workspace/29.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2972159055
Short name	T221
Test name
Test status
Simulation time	14274970 ps
CPU time	0.88 seconds
Started	Aug 11 07:07:21 PM PDT 24
Finished	Aug 11 07:07:22 PM PDT 24
Peak memory	212720 kb
Host	smart-40a2c1e8-7e81-426d-8936-2333e201e8f4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972159055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c trl_volatile_unlock_smoke.2972159055
Directory	/workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_alert_test.3670968886
Short name	T592
Test name
Test status
Simulation time	23136501 ps
CPU time	0.91 seconds
Started	Aug 11 07:05:27 PM PDT 24
Finished	Aug 11 07:05:28 PM PDT 24
Peak memory	208708 kb
Host	smart-bca8808b-91e5-43b7-97e9-80b46a5df6fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670968886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3670968886
Directory	/workspace/3.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.lc_ctrl_claim_transition_if.3372057739
Short name	T261
Test name
Test status
Simulation time	33479849 ps
CPU time	0.92 seconds
Started	Aug 11 07:05:26 PM PDT 24
Finished	Aug 11 07:05:27 PM PDT 24
Peak memory	208608 kb
Host	smart-2fcbe4aa-03af-4d76-8807-456286e76e57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372057739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3372057739
Directory	/workspace/3.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/3.lc_ctrl_errors.652516692
Short name	T41
Test name
Test status
Simulation time	2303410484 ps
CPU time	15.78 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:05:39 PM PDT 24
Peak memory	218116 kb
Host	smart-30d6d04c-8149-445c-bce5-c6037399667f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652516692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.652516692
Directory	/workspace/3.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_access.3085060930
Short name	T437
Test name
Test status
Simulation time	254270849 ps
CPU time	3.44 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:29 PM PDT 24
Peak memory	217088 kb
Host	smart-163cf31d-4706-4d80-8729-a9344b693520
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085060930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3085060930
Directory	/workspace/3.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_errors.4148621549
Short name	T1
Test name
Test status
Simulation time	1709218762 ps
CPU time	52.38 seconds
Started	Aug 11 07:05:28 PM PDT 24
Finished	Aug 11 07:06:21 PM PDT 24
Peak memory	218636 kb
Host	smart-ae3b0b65-5a51-4762-a50a-e9a981ca5f9c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148621549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er rors.4148621549
Directory	/workspace/3.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_priority.2040669368
Short name	T284
Test name
Test status
Simulation time	2014448927 ps
CPU time	7.08 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:05:32 PM PDT 24
Peak memory	217276 kb
Host	smart-6a645ada-902a-4eb8-af40-c8320aa4f5c4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040669368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2 040669368
Directory	/workspace/3.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.165638382
Short name	T806
Test name
Test status
Simulation time	249771566 ps
CPU time	2.39 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:05:33 PM PDT 24
Peak memory	217988 kb
Host	smart-0373c9c7-4fae-44e5-850e-3987ae57ac27
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165638382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_ prog_failure.165638382
Directory	/workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2748171022
Short name	T845
Test name
Test status
Simulation time	5428565731 ps
CPU time	20.53 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:46 PM PDT 24
Peak memory	217580 kb
Host	smart-30a4d53d-96a2-4e4b-b1de-c0721e3149d0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748171022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_regwen_during_op.2748171022
Directory	/workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_smoke.4188234547
Short name	T502
Test name
Test status
Simulation time	161021671 ps
CPU time	3.55 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:05:27 PM PDT 24
Peak memory	217424 kb
Host	smart-6a37dee1-47d4-4a7b-bd98-23cb8b7a9a79
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188234547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke. 4188234547
Directory	/workspace/3.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2267804816
Short name	T723
Test name
Test status
Simulation time	4375308420 ps
CPU time	42.65 seconds
Started	Aug 11 07:05:27 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	277440 kb
Host	smart-1f9ba1eb-5132-4f07-beb5-6ca1d3d127cb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267804816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_state_failure.2267804816
Directory	/workspace/3.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1698216357
Short name	T278
Test name
Test status
Simulation time	829440077 ps
CPU time	16.53 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	250688 kb
Host	smart-823761f1-1579-4c2f-be7a-cec1f2d1a04c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698216357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_state_post_trans.1698216357
Directory	/workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_prog_failure.4088118799
Short name	T468
Test name
Test status
Simulation time	46650077 ps
CPU time	3.01 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:28 PM PDT 24
Peak memory	218092 kb
Host	smart-f242f8ab-fe5f-49a5-8486-60bc8cbfe31d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4088118799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4088118799
Directory	/workspace/3.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_regwen_during_op.2233023654
Short name	T803
Test name
Test status
Simulation time	1061666795 ps
CPU time	16.06 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:41 PM PDT 24
Peak memory	217520 kb
Host	smart-23d9b08b-f55a-464d-95ba-f8c205d0fae9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233023654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2233023654
Directory	/workspace/3.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_cm.2428674010
Short name	T97
Test name
Test status
Simulation time	1669542709 ps
CPU time	23.22 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:48 PM PDT 24
Peak memory	284524 kb
Host	smart-0bb9ba79-a533-464c-9bd8-7473c6b08dfa
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428674010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2428674010
Directory	/workspace/3.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_mubi.1462582120
Short name	T365
Test name
Test status
Simulation time	604443707 ps
CPU time	9.91 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:05:40 PM PDT 24
Peak memory	218776 kb
Host	smart-a82431a9-b615-40e4-b564-850d05b345fa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462582120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1462582120
Directory	/workspace/3.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_digest.381960289
Short name	T152
Test name
Test status
Simulation time	542659771 ps
CPU time	19.24 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:05:43 PM PDT 24
Peak memory	218152 kb
Host	smart-61d6b3f2-fa7e-4f73-8248-e9e4db227219
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381960289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig est.381960289
Directory	/workspace/3.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_mux.641494498
Short name	T762
Test name
Test status
Simulation time	2060162638 ps
CPU time	16.06 seconds
Started	Aug 11 07:05:28 PM PDT 24
Finished	Aug 11 07:05:44 PM PDT 24
Peak memory	218012 kb
Host	smart-a45525f3-098d-4118-a051-021e00719e71
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641494498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.641494498
Directory	/workspace/3.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/3.lc_ctrl_security_escalation.264466197
Short name	T524
Test name
Test status
Simulation time	327522077 ps
CPU time	10.02 seconds
Started	Aug 11 07:05:28 PM PDT 24
Finished	Aug 11 07:05:39 PM PDT 24
Peak memory	224536 kb
Host	smart-7e6c9b82-e60d-4ba3-aea2-7f2d287a992d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264466197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.264466197
Directory	/workspace/3.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/3.lc_ctrl_smoke.2498166922
Short name	T87
Test name
Test status
Simulation time	69917159 ps
CPU time	1.59 seconds
Started	Aug 11 07:05:26 PM PDT 24
Finished	Aug 11 07:05:27 PM PDT 24
Peak memory	213792 kb
Host	smart-88b7acf1-6f62-4a26-a70f-4de6608a0fe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498166922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2498166922
Directory	/workspace/3.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_failure.43680921
Short name	T658
Test name
Test status
Simulation time	1079128413 ps
CPU time	24.96 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:50 PM PDT 24
Peak memory	247576 kb
Host	smart-b92ca050-9690-4ed2-a45c-1efa999bb789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43680921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.43680921
Directory	/workspace/3.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_post_trans.256240914
Short name	T425
Test name
Test status
Simulation time	97354726 ps
CPU time	9.42 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:05:34 PM PDT 24
Peak memory	250720 kb
Host	smart-d58cb5b6-0022-42fb-8ddf-cde66fefd9b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256240914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.256240914
Directory	/workspace/3.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all.3325908935
Short name	T679
Test name
Test status
Simulation time	140546422550 ps
CPU time	501.43 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:13:46 PM PDT 24
Peak memory	274644 kb
Host	smart-1d47d544-0316-40cf-90e6-7e2efa2a8660
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325908935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.3325908935
Directory	/workspace/3.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2904971216
Short name	T147
Test name
Test status
Simulation time	166657365075 ps
CPU time	933.63 seconds
Started	Aug 11 07:05:27 PM PDT 24
Finished	Aug 11 07:21:01 PM PDT 24
Peak memory	367776 kb
Host	smart-5b47b2fe-7ca4-4016-a8f8-eef52a76c9f3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2904971216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2904971216
Directory	/workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.352125026
Short name	T193
Test name
Test status
Simulation time	11791831 ps
CPU time	0.92 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:26 PM PDT 24
Peak memory	211632 kb
Host	smart-6df13c10-2976-4e56-892a-1163dedc17d1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352125026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr l_volatile_unlock_smoke.352125026
Directory	/workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_alert_test.594152452
Short name	T99
Test name
Test status
Simulation time	30726071 ps
CPU time	1.01 seconds
Started	Aug 11 07:07:27 PM PDT 24
Finished	Aug 11 07:07:28 PM PDT 24
Peak memory	208720 kb
Host	smart-04973c59-0935-4398-bc1c-654910ed7075
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594152452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.594152452
Directory	/workspace/30.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.lc_ctrl_errors.907657292
Short name	T412
Test name
Test status
Simulation time	584768423 ps
CPU time	13.14 seconds
Started	Aug 11 07:07:26 PM PDT 24
Finished	Aug 11 07:07:40 PM PDT 24
Peak memory	218056 kb
Host	smart-87e0f78d-bd5f-4ab8-b17d-ca5a8892f4f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=907657292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.907657292
Directory	/workspace/30.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/30.lc_ctrl_jtag_access.3123733029
Short name	T599
Test name
Test status
Simulation time	2336051111 ps
CPU time	6.46 seconds
Started	Aug 11 07:07:26 PM PDT 24
Finished	Aug 11 07:07:33 PM PDT 24
Peak memory	216968 kb
Host	smart-037ded5f-fefc-46ec-bdba-2be907d9b0ef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123733029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3123733029
Directory	/workspace/30.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/30.lc_ctrl_prog_failure.3709179819
Short name	T423
Test name
Test status
Simulation time	59370389 ps
CPU time	2.88 seconds
Started	Aug 11 07:07:26 PM PDT 24
Finished	Aug 11 07:07:29 PM PDT 24
Peak memory	218084 kb
Host	smart-63451e90-8b11-4ced-9e50-1d499efabf07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3709179819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3709179819
Directory	/workspace/30.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_mubi.857440920
Short name	T321
Test name
Test status
Simulation time	291011398 ps
CPU time	14.11 seconds
Started	Aug 11 07:07:26 PM PDT 24
Finished	Aug 11 07:07:41 PM PDT 24
Peak memory	218756 kb
Host	smart-f23235fb-1888-45c3-8026-710b39208dd3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857440920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.857440920
Directory	/workspace/30.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_digest.1194787753
Short name	T489
Test name
Test status
Simulation time	2775451244 ps
CPU time	15.95 seconds
Started	Aug 11 07:07:28 PM PDT 24
Finished	Aug 11 07:07:44 PM PDT 24
Peak memory	225916 kb
Host	smart-69ce3464-e76d-4588-8ea1-c8cdf4264e60
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194787753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d igest.1194787753
Directory	/workspace/30.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_mux.3411736905
Short name	T879
Test name
Test status
Simulation time	630676895 ps
CPU time	8.59 seconds
Started	Aug 11 07:07:28 PM PDT 24
Finished	Aug 11 07:07:36 PM PDT 24
Peak memory	218064 kb
Host	smart-f1372c01-5d91-4d99-aeed-2650c7754ffe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411736905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux. 3411736905
Directory	/workspace/30.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/30.lc_ctrl_security_escalation.2532357768
Short name	T741
Test name
Test status
Simulation time	1377807702 ps
CPU time	8.51 seconds
Started	Aug 11 07:07:27 PM PDT 24
Finished	Aug 11 07:07:35 PM PDT 24
Peak memory	224660 kb
Host	smart-1446ae4d-065e-4437-96f7-42aacd4a307e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532357768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2532357768
Directory	/workspace/30.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/30.lc_ctrl_smoke.2398335676
Short name	T877
Test name
Test status
Simulation time	65817557 ps
CPU time	2.72 seconds
Started	Aug 11 07:07:25 PM PDT 24
Finished	Aug 11 07:07:28 PM PDT 24
Peak memory	214612 kb
Host	smart-0e516069-2ba1-43a1-82c1-52e754071d4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2398335676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2398335676
Directory	/workspace/30.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_failure.1589048626
Short name	T162
Test name
Test status
Simulation time	858230594 ps
CPU time	21.91 seconds
Started	Aug 11 07:07:28 PM PDT 24
Finished	Aug 11 07:07:50 PM PDT 24
Peak memory	250804 kb
Host	smart-4a2581c0-99ce-46b2-ad18-058a7ce96e47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589048626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1589048626
Directory	/workspace/30.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_post_trans.68728272
Short name	T748
Test name
Test status
Simulation time	209108468 ps
CPU time	9.24 seconds
Started	Aug 11 07:07:27 PM PDT 24
Finished	Aug 11 07:07:37 PM PDT 24
Peak memory	250676 kb
Host	smart-d3f631ce-7675-46d8-aef3-219a17a8f1f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68728272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.68728272
Directory	/workspace/30.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all.3661165200
Short name	T184
Test name
Test status
Simulation time	6170009987 ps
CPU time	35.48 seconds
Started	Aug 11 07:07:27 PM PDT 24
Finished	Aug 11 07:08:03 PM PDT 24
Peak memory	226752 kb
Host	smart-fd5172bd-c1a2-4f73-855a-e753eb88645d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661165200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.3661165200
Directory	/workspace/30.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.79003318
Short name	T687
Test name
Test status
Simulation time	40741946 ps
CPU time	0.86 seconds
Started	Aug 11 07:07:27 PM PDT 24
Finished	Aug 11 07:07:28 PM PDT 24
Peak memory	208032 kb
Host	smart-9ac159a8-54cf-43bf-9727-6ed4a79f1e86
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79003318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctr l_volatile_unlock_smoke.79003318
Directory	/workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_alert_test.1672257198
Short name	T726
Test name
Test status
Simulation time	84600858 ps
CPU time	1.24 seconds
Started	Aug 11 07:07:36 PM PDT 24
Finished	Aug 11 07:07:37 PM PDT 24
Peak memory	208908 kb
Host	smart-82f3877b-b8eb-4cb5-8199-12f52daa406b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672257198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1672257198
Directory	/workspace/31.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.lc_ctrl_errors.1478027333
Short name	T482
Test name
Test status
Simulation time	875110109 ps
CPU time	10.5 seconds
Started	Aug 11 07:07:34 PM PDT 24
Finished	Aug 11 07:07:44 PM PDT 24
Peak memory	225908 kb
Host	smart-9a9aca3f-5d91-4cdf-b7f1-98b93e15610b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478027333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1478027333
Directory	/workspace/31.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/31.lc_ctrl_jtag_access.704883636
Short name	T418
Test name
Test status
Simulation time	154793124 ps
CPU time	2.58 seconds
Started	Aug 11 07:07:34 PM PDT 24
Finished	Aug 11 07:07:37 PM PDT 24
Peak memory	216868 kb
Host	smart-ccb99507-c6f6-4cc0-a24d-d6e09a36eca7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704883636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.704883636
Directory	/workspace/31.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/31.lc_ctrl_prog_failure.1040327984
Short name	T334
Test name
Test status
Simulation time	791201256 ps
CPU time	3.57 seconds
Started	Aug 11 07:07:35 PM PDT 24
Finished	Aug 11 07:07:39 PM PDT 24
Peak memory	222152 kb
Host	smart-5c7960cb-f4f6-46f1-88de-83c0a8c3b5c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040327984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1040327984
Directory	/workspace/31.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_mubi.3024551842
Short name	T234
Test name
Test status
Simulation time	279619955 ps
CPU time	11.88 seconds
Started	Aug 11 07:07:34 PM PDT 24
Finished	Aug 11 07:07:46 PM PDT 24
Peak memory	225876 kb
Host	smart-fda27e42-9bd8-45d6-b924-ffcacaedef00
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024551842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3024551842
Directory	/workspace/31.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_digest.57663824
Short name	T809
Test name
Test status
Simulation time	273177724 ps
CPU time	9.62 seconds
Started	Aug 11 07:07:33 PM PDT 24
Finished	Aug 11 07:07:43 PM PDT 24
Peak memory	218072 kb
Host	smart-44d1c086-8be8-4187-b66a-b37cff9cdf94
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57663824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_dig est.57663824
Directory	/workspace/31.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_mux.286422070
Short name	T317
Test name
Test status
Simulation time	1503222030 ps
CPU time	9.64 seconds
Started	Aug 11 07:07:36 PM PDT 24
Finished	Aug 11 07:07:46 PM PDT 24
Peak memory	225812 kb
Host	smart-76063ff7-688f-4b5d-a030-a24f05e7f5d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286422070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.286422070
Directory	/workspace/31.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/31.lc_ctrl_security_escalation.583001704
Short name	T850
Test name
Test status
Simulation time	198181868 ps
CPU time	7.04 seconds
Started	Aug 11 07:07:33 PM PDT 24
Finished	Aug 11 07:07:40 PM PDT 24
Peak memory	225116 kb
Host	smart-ee67f865-f99b-446f-937b-430599051db3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583001704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.583001704
Directory	/workspace/31.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/31.lc_ctrl_smoke.259214065
Short name	T67
Test name
Test status
Simulation time	409556582 ps
CPU time	6.29 seconds
Started	Aug 11 07:07:28 PM PDT 24
Finished	Aug 11 07:07:34 PM PDT 24
Peak memory	217516 kb
Host	smart-35ce0589-ffc5-4087-8978-141311ca0aea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259214065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.259214065
Directory	/workspace/31.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_failure.3190726594
Short name	T472
Test name
Test status
Simulation time	903857981 ps
CPU time	18.94 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:58 PM PDT 24
Peak memory	250816 kb
Host	smart-a879210e-da2a-491a-a6e1-076c3371eeb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190726594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3190726594
Directory	/workspace/31.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_post_trans.620791937
Short name	T846
Test name
Test status
Simulation time	107329640 ps
CPU time	3.35 seconds
Started	Aug 11 07:07:36 PM PDT 24
Finished	Aug 11 07:07:39 PM PDT 24
Peak memory	222352 kb
Host	smart-507f0f94-279a-4e54-bcb0-0a706e03d813
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620791937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.620791937
Directory	/workspace/31.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all.3914625933
Short name	T853
Test name
Test status
Simulation time	5305861854 ps
CPU time	68.35 seconds
Started	Aug 11 07:07:36 PM PDT 24
Finished	Aug 11 07:08:45 PM PDT 24
Peak memory	252056 kb
Host	smart-9ffd4e86-ef6e-4315-a83f-9e29b3dd20a0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914625933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.3914625933
Directory	/workspace/31.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3471331998
Short name	T168
Test name
Test status
Simulation time	372171526167 ps
CPU time	3049.45 seconds
Started	Aug 11 07:07:35 PM PDT 24
Finished	Aug 11 07:58:25 PM PDT 24
Peak memory	1552776 kb
Host	smart-914f14df-8ef5-41e8-8e53-387e0db8a639
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3471331998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.3471331998
Directory	/workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2535373149
Short name	T496
Test name
Test status
Simulation time	31621114 ps
CPU time	1.04 seconds
Started	Aug 11 07:07:26 PM PDT 24
Finished	Aug 11 07:07:28 PM PDT 24
Peak memory	212900 kb
Host	smart-fefa6cf0-a483-40f5-a7b4-0c8e53357580
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535373149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c trl_volatile_unlock_smoke.2535373149
Directory	/workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_alert_test.2733954306
Short name	T163
Test name
Test status
Simulation time	11566720 ps
CPU time	0.83 seconds
Started	Aug 11 07:07:34 PM PDT 24
Finished	Aug 11 07:07:35 PM PDT 24
Peak memory	208596 kb
Host	smart-4e2263da-b0ee-4194-a39a-ed5e60173216
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733954306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2733954306
Directory	/workspace/32.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.lc_ctrl_errors.2916686970
Short name	T613
Test name
Test status
Simulation time	590670189 ps
CPU time	11.97 seconds
Started	Aug 11 07:07:33 PM PDT 24
Finished	Aug 11 07:07:45 PM PDT 24
Peak memory	225900 kb
Host	smart-1048a76a-14a7-4b39-bd82-25b2e95a6ddd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916686970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2916686970
Directory	/workspace/32.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/32.lc_ctrl_jtag_access.7705685
Short name	T693
Test name
Test status
Simulation time	385062291 ps
CPU time	10.28 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:49 PM PDT 24
Peak memory	217360 kb
Host	smart-6bed27fb-f9b3-47a8-a386-821f8f955dd4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7705685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.7705685
Directory	/workspace/32.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/32.lc_ctrl_prog_failure.912799477
Short name	T620
Test name
Test status
Simulation time	107251867 ps
CPU time	2.8 seconds
Started	Aug 11 07:07:36 PM PDT 24
Finished	Aug 11 07:07:39 PM PDT 24
Peak memory	222172 kb
Host	smart-ea78e4b4-7f90-40dc-8451-cb7ccae2cdfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912799477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.912799477
Directory	/workspace/32.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_mubi.566413983
Short name	T713
Test name
Test status
Simulation time	1731299189 ps
CPU time	13.91 seconds
Started	Aug 11 07:07:38 PM PDT 24
Finished	Aug 11 07:07:52 PM PDT 24
Peak memory	218780 kb
Host	smart-d8966507-5f67-4a64-8022-2c5ba64c03ed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566413983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.566413983
Directory	/workspace/32.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_digest.780344273
Short name	T566
Test name
Test status
Simulation time	953484186 ps
CPU time	19.86 seconds
Started	Aug 11 07:07:34 PM PDT 24
Finished	Aug 11 07:07:54 PM PDT 24
Peak memory	218084 kb
Host	smart-281c5933-3c72-4f52-ad40-0523ce6bf49e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780344273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di gest.780344273
Directory	/workspace/32.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_mux.2575184000
Short name	T277
Test name
Test status
Simulation time	455891271 ps
CPU time	10.36 seconds
Started	Aug 11 07:07:36 PM PDT 24
Finished	Aug 11 07:07:46 PM PDT 24
Peak memory	218016 kb
Host	smart-d0b353a1-513b-467a-a4ab-49cde850c404
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575184000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux. 2575184000
Directory	/workspace/32.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/32.lc_ctrl_security_escalation.1356886087
Short name	T53
Test name
Test status
Simulation time	556575305 ps
CPU time	10.17 seconds
Started	Aug 11 07:07:35 PM PDT 24
Finished	Aug 11 07:07:45 PM PDT 24
Peak memory	218168 kb
Host	smart-56c4e15d-5e4f-4be3-a47b-c72067aac91b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356886087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1356886087
Directory	/workspace/32.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/32.lc_ctrl_smoke.2842187436
Short name	T581
Test name
Test status
Simulation time	36925579 ps
CPU time	2.71 seconds
Started	Aug 11 07:07:33 PM PDT 24
Finished	Aug 11 07:07:36 PM PDT 24
Peak memory	214736 kb
Host	smart-78e1594e-d8b5-42d8-b791-75da3702c4c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842187436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2842187436
Directory	/workspace/32.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_failure.1001463773
Short name	T499
Test name
Test status
Simulation time	2070671692 ps
CPU time	33.61 seconds
Started	Aug 11 07:07:32 PM PDT 24
Finished	Aug 11 07:08:06 PM PDT 24
Peak memory	250744 kb
Host	smart-066a0254-f34d-439c-91c4-94ecc09779fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001463773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1001463773
Directory	/workspace/32.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_post_trans.3378758790
Short name	T32
Test name
Test status
Simulation time	157506676 ps
CPU time	8.84 seconds
Started	Aug 11 07:07:35 PM PDT 24
Finished	Aug 11 07:07:44 PM PDT 24
Peak memory	250796 kb
Host	smart-c2db2a66-dbf0-41f5-b266-bfc29de4e5a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378758790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3378758790
Directory	/workspace/32.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all.2125268041
Short name	T411
Test name
Test status
Simulation time	59987463944 ps
CPU time	551.45 seconds
Started	Aug 11 07:07:35 PM PDT 24
Finished	Aug 11 07:16:47 PM PDT 24
Peak memory	421920 kb
Host	smart-3fbef2ce-3741-4057-86ae-6b9c7b46fd54
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125268041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.2125268041
Directory	/workspace/32.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3388656124
Short name	T523
Test name
Test status
Simulation time	15049204 ps
CPU time	1.08 seconds
Started	Aug 11 07:07:32 PM PDT 24
Finished	Aug 11 07:07:33 PM PDT 24
Peak memory	211688 kb
Host	smart-fb77cc66-4c86-49cb-a25a-62a3feb4291c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388656124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c trl_volatile_unlock_smoke.3388656124
Directory	/workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_alert_test.403885178
Short name	T573
Test name
Test status
Simulation time	64503621 ps
CPU time	1.14 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:40 PM PDT 24
Peak memory	208940 kb
Host	smart-d9632a6d-25e0-4edd-8857-ff401e87275c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403885178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.403885178
Directory	/workspace/33.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.lc_ctrl_errors.45871873
Short name	T837
Test name
Test status
Simulation time	1027666174 ps
CPU time	15.7 seconds
Started	Aug 11 07:07:34 PM PDT 24
Finished	Aug 11 07:07:50 PM PDT 24
Peak memory	218116 kb
Host	smart-3e949574-9b76-4d30-827e-4a6c03e0eef4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45871873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.45871873
Directory	/workspace/33.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/33.lc_ctrl_prog_failure.526773379
Short name	T247
Test name
Test status
Simulation time	67537662 ps
CPU time	2.26 seconds
Started	Aug 11 07:07:32 PM PDT 24
Finished	Aug 11 07:07:35 PM PDT 24
Peak memory	218088 kb
Host	smart-5a97cf25-7d34-48a2-9a83-7a50ce74d779
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526773379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.526773379
Directory	/workspace/33.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_mubi.2806145793
Short name	T185
Test name
Test status
Simulation time	1581108426 ps
CPU time	23.15 seconds
Started	Aug 11 07:07:33 PM PDT 24
Finished	Aug 11 07:07:57 PM PDT 24
Peak memory	218824 kb
Host	smart-2f08785d-b777-43ff-86ab-11756cb1cea8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806145793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2806145793
Directory	/workspace/33.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_digest.1753588966
Short name	T513
Test name
Test status
Simulation time	326257726 ps
CPU time	8.15 seconds
Started	Aug 11 07:07:34 PM PDT 24
Finished	Aug 11 07:07:42 PM PDT 24
Peak memory	218140 kb
Host	smart-fc665cd4-49a1-4eed-b01d-c16a658f23ab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753588966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d igest.1753588966
Directory	/workspace/33.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_mux.2642032896
Short name	T733
Test name
Test status
Simulation time	361594100 ps
CPU time	8.67 seconds
Started	Aug 11 07:07:33 PM PDT 24
Finished	Aug 11 07:07:42 PM PDT 24
Peak memory	218076 kb
Host	smart-90547a6d-4385-4ef1-81fa-d9ca55435887
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642032896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux. 2642032896
Directory	/workspace/33.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/33.lc_ctrl_security_escalation.343818927
Short name	T339
Test name
Test status
Simulation time	1107568225 ps
CPU time	10.81 seconds
Started	Aug 11 07:07:36 PM PDT 24
Finished	Aug 11 07:07:47 PM PDT 24
Peak memory	225060 kb
Host	smart-6e59c343-2b16-4248-84dc-c839a02a2565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343818927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.343818927
Directory	/workspace/33.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/33.lc_ctrl_smoke.1654760261
Short name	T556
Test name
Test status
Simulation time	167692434 ps
CPU time	4.5 seconds
Started	Aug 11 07:07:33 PM PDT 24
Finished	Aug 11 07:07:38 PM PDT 24
Peak memory	217520 kb
Host	smart-46b80bdf-735d-4b7f-b898-524b4170d52d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654760261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1654760261
Directory	/workspace/33.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_failure.2579401973
Short name	T488
Test name
Test status
Simulation time	238706291 ps
CPU time	24.95 seconds
Started	Aug 11 07:07:32 PM PDT 24
Finished	Aug 11 07:07:57 PM PDT 24
Peak memory	250748 kb
Host	smart-5f0638ac-93db-4425-839e-6f5433f84371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579401973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2579401973
Directory	/workspace/33.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_post_trans.631888486
Short name	T511
Test name
Test status
Simulation time	107242121 ps
CPU time	8.05 seconds
Started	Aug 11 07:07:36 PM PDT 24
Finished	Aug 11 07:07:44 PM PDT 24
Peak memory	250728 kb
Host	smart-be731104-7806-458b-9034-a0f6fc810cf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631888486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.631888486
Directory	/workspace/33.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all.2040833713
Short name	T309
Test name
Test status
Simulation time	3868080278 ps
CPU time	102.37 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:09:21 PM PDT 24
Peak memory	250924 kb
Host	smart-d05d56c4-18e8-46b1-a1b4-8f88f323ea6c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040833713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.2040833713
Directory	/workspace/33.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2125163531
Short name	T307
Test name
Test status
Simulation time	14743010 ps
CPU time	0.93 seconds
Started	Aug 11 07:07:35 PM PDT 24
Finished	Aug 11 07:07:36 PM PDT 24
Peak memory	211652 kb
Host	smart-919e479a-a89a-4d5f-b022-6befbb9343e4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125163531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c trl_volatile_unlock_smoke.2125163531
Directory	/workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_alert_test.96154022
Short name	T604
Test name
Test status
Simulation time	16525880 ps
CPU time	1.09 seconds
Started	Aug 11 07:07:41 PM PDT 24
Finished	Aug 11 07:07:42 PM PDT 24
Peak memory	208692 kb
Host	smart-3673c3f4-d477-4b54-b4ca-9b7f68fe00ab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96154022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.96154022
Directory	/workspace/34.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.lc_ctrl_errors.582875002
Short name	T173
Test name
Test status
Simulation time	6375236934 ps
CPU time	11.34 seconds
Started	Aug 11 07:07:42 PM PDT 24
Finished	Aug 11 07:07:53 PM PDT 24
Peak memory	218548 kb
Host	smart-2d5f0fb6-67d0-4991-9442-10c95e3ad224
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582875002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.582875002
Directory	/workspace/34.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/34.lc_ctrl_jtag_access.3135012310
Short name	T580
Test name
Test status
Simulation time	1345477763 ps
CPU time	2.02 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:42 PM PDT 24
Peak memory	216904 kb
Host	smart-127ab3aa-efc8-4bbe-bfbd-aeab4d10f47a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135012310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3135012310
Directory	/workspace/34.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/34.lc_ctrl_prog_failure.141770855
Short name	T153
Test name
Test status
Simulation time	63002259 ps
CPU time	2.71 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:07:43 PM PDT 24
Peak memory	218100 kb
Host	smart-2641a0d4-3c0f-4ad0-8c0a-2c1ab2c0edf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=141770855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.141770855
Directory	/workspace/34.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_mubi.2371260400
Short name	T534
Test name
Test status
Simulation time	471163375 ps
CPU time	15.37 seconds
Started	Aug 11 07:07:41 PM PDT 24
Finished	Aug 11 07:07:57 PM PDT 24
Peak memory	225880 kb
Host	smart-8abf51e6-c75f-4e81-9dba-2a92af493d70
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371260400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2371260400
Directory	/workspace/34.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_digest.1259299314
Short name	T194
Test name
Test status
Simulation time	4994039126 ps
CPU time	10.55 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:07:51 PM PDT 24
Peak memory	218128 kb
Host	smart-6324f52d-b486-4697-af5a-157b54a53e7b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259299314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d igest.1259299314
Directory	/workspace/34.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_mux.3350479310
Short name	T764
Test name
Test status
Simulation time	233789716 ps
CPU time	6.23 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:07:47 PM PDT 24
Peak memory	218016 kb
Host	smart-b7c3a536-621f-40b7-9b52-f682824356e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350479310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux. 3350479310
Directory	/workspace/34.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/34.lc_ctrl_smoke.2220054082
Short name	T780
Test name
Test status
Simulation time	61513747 ps
CPU time	2.14 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:41 PM PDT 24
Peak memory	217508 kb
Host	smart-b9354c6b-b05e-4125-8394-710888a6537c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220054082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2220054082
Directory	/workspace/34.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_failure.403413310
Short name	T506
Test name
Test status
Simulation time	405193708 ps
CPU time	26.81 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:08:07 PM PDT 24
Peak memory	250900 kb
Host	smart-2ff8dfe2-af7b-4b40-adf5-02a3d453f1a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403413310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.403413310
Directory	/workspace/34.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_post_trans.2452356364
Short name	T773
Test name
Test status
Simulation time	294083440 ps
CPU time	6.71 seconds
Started	Aug 11 07:07:42 PM PDT 24
Finished	Aug 11 07:07:49 PM PDT 24
Peak memory	247228 kb
Host	smart-e77849d5-3dea-4430-a578-9027cf139067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452356364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2452356364
Directory	/workspace/34.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all.4269404300
Short name	T171
Test name
Test status
Simulation time	86685515081 ps
CPU time	596.16 seconds
Started	Aug 11 07:07:41 PM PDT 24
Finished	Aug 11 07:17:37 PM PDT 24
Peak memory	284084 kb
Host	smart-bf54956c-ae50-4275-a9aa-a7369a8f2259
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269404300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.4269404300
Directory	/workspace/34.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2920861478
Short name	T151
Test name
Test status
Simulation time	8862290744 ps
CPU time	187.58 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:10:48 PM PDT 24
Peak memory	275620 kb
Host	smart-6d1265bf-53bc-4a4c-9a7e-5c80b3514cae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2920861478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2920861478
Directory	/workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2763791493
Short name	T711
Test name
Test status
Simulation time	15793890 ps
CPU time	0.96 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:07:41 PM PDT 24
Peak memory	211676 kb
Host	smart-783977da-b427-4888-8d06-31e93314068d
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763791493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c trl_volatile_unlock_smoke.2763791493
Directory	/workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_alert_test.2148889460
Short name	T567
Test name
Test status
Simulation time	41532463 ps
CPU time	0.96 seconds
Started	Aug 11 07:07:41 PM PDT 24
Finished	Aug 11 07:07:42 PM PDT 24
Peak memory	208660 kb
Host	smart-5710681d-b028-42ee-b8a8-163dc2ce435e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148889460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2148889460
Directory	/workspace/35.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.lc_ctrl_errors.3192464395
Short name	T322
Test name
Test status
Simulation time	264573323 ps
CPU time	14.49 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:54 PM PDT 24
Peak memory	226064 kb
Host	smart-c6a60844-d713-49ee-8ff5-12ab6d843047
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192464395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3192464395
Directory	/workspace/35.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/35.lc_ctrl_jtag_access.2105095761
Short name	T395
Test name
Test status
Simulation time	779228731 ps
CPU time	5.21 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:07:45 PM PDT 24
Peak memory	216984 kb
Host	smart-701874fd-76cd-4097-8eb3-03900aa24aec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105095761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2105095761
Directory	/workspace/35.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/35.lc_ctrl_prog_failure.2875281769
Short name	T662
Test name
Test status
Simulation time	32138930 ps
CPU time	1.79 seconds
Started	Aug 11 07:07:41 PM PDT 24
Finished	Aug 11 07:07:43 PM PDT 24
Peak memory	221868 kb
Host	smart-c7a3d182-f49f-4826-a0a0-824515ee695f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875281769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2875281769
Directory	/workspace/35.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_mubi.1179816244
Short name	T298
Test name
Test status
Simulation time	2321248052 ps
CPU time	19.41 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:59 PM PDT 24
Peak memory	226124 kb
Host	smart-beaf43e9-591f-4ea9-b77e-82b977ba1ddb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179816244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1179816244
Directory	/workspace/35.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_digest.4133632475
Short name	T816
Test name
Test status
Simulation time	964546233 ps
CPU time	14.32 seconds
Started	Aug 11 07:07:38 PM PDT 24
Finished	Aug 11 07:07:52 PM PDT 24
Peak memory	218020 kb
Host	smart-ebdaa4b3-b4bc-4d91-a42f-2e3f308655df
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133632475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d igest.4133632475
Directory	/workspace/35.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_mux.2826534857
Short name	T830
Test name
Test status
Simulation time	221828651 ps
CPU time	9.34 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:49 PM PDT 24
Peak memory	217996 kb
Host	smart-76fe7e75-3b6d-4d16-b356-2d39326cc59e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826534857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux. 2826534857
Directory	/workspace/35.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/35.lc_ctrl_security_escalation.2953260806
Short name	T649
Test name
Test status
Simulation time	1359512165 ps
CPU time	14.08 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:54 PM PDT 24
Peak memory	218172 kb
Host	smart-e3069033-bd68-438d-bb39-a9c8aec66b42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2953260806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2953260806
Directory	/workspace/35.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/35.lc_ctrl_smoke.470694294
Short name	T75
Test name
Test status
Simulation time	56112306 ps
CPU time	1.95 seconds
Started	Aug 11 07:07:38 PM PDT 24
Finished	Aug 11 07:07:40 PM PDT 24
Peak memory	217464 kb
Host	smart-1426fa81-877d-4806-9bc8-a11d038d1bb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470694294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.470694294
Directory	/workspace/35.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_failure.162732138
Short name	T676
Test name
Test status
Simulation time	245981082 ps
CPU time	19.64 seconds
Started	Aug 11 07:07:41 PM PDT 24
Finished	Aug 11 07:08:01 PM PDT 24
Peak memory	250796 kb
Host	smart-063aac5c-246c-4c19-9a08-af82fd3c9da3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162732138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.162732138
Directory	/workspace/35.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_post_trans.990056216
Short name	T255
Test name
Test status
Simulation time	172344790 ps
CPU time	8.24 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:48 PM PDT 24
Peak memory	250792 kb
Host	smart-b484aa6d-c8ec-4c91-8f30-aa972511b917
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990056216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.990056216
Directory	/workspace/35.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all.2076126801
Short name	T651
Test name
Test status
Simulation time	2547923141 ps
CPU time	57.82 seconds
Started	Aug 11 07:07:42 PM PDT 24
Finished	Aug 11 07:08:40 PM PDT 24
Peak memory	251008 kb
Host	smart-f8e3d033-f6c4-4792-9c94-c0ef776c4a87
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076126801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.2076126801
Directory	/workspace/35.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1816314552
Short name	T621
Test name
Test status
Simulation time	24127364748 ps
CPU time	834.73 seconds
Started	Aug 11 07:07:38 PM PDT 24
Finished	Aug 11 07:21:33 PM PDT 24
Peak memory	332924 kb
Host	smart-5c2b8dd8-4d10-4550-a74e-a28b2be444ab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1816314552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1816314552
Directory	/workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3418385047
Short name	T466
Test name
Test status
Simulation time	12009529 ps
CPU time	1.02 seconds
Started	Aug 11 07:07:39 PM PDT 24
Finished	Aug 11 07:07:40 PM PDT 24
Peak memory	211688 kb
Host	smart-9125a4db-7671-4841-a375-62900c7c028c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418385047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c trl_volatile_unlock_smoke.3418385047
Directory	/workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_alert_test.3257853065
Short name	T170
Test name
Test status
Simulation time	37173275 ps
CPU time	1.1 seconds
Started	Aug 11 07:07:47 PM PDT 24
Finished	Aug 11 07:07:48 PM PDT 24
Peak memory	208728 kb
Host	smart-9a7e23f6-31df-4f20-b6ff-81990cd4207a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257853065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3257853065
Directory	/workspace/36.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.lc_ctrl_errors.3671842664
Short name	T690
Test name
Test status
Simulation time	613129172 ps
CPU time	12.77 seconds
Started	Aug 11 07:07:45 PM PDT 24
Finished	Aug 11 07:07:58 PM PDT 24
Peak memory	218108 kb
Host	smart-efcff837-a352-4c3d-ace8-613d22b8dafe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671842664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3671842664
Directory	/workspace/36.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/36.lc_ctrl_jtag_access.2326440747
Short name	T758
Test name
Test status
Simulation time	51837280 ps
CPU time	1.7 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:48 PM PDT 24
Peak memory	216968 kb
Host	smart-5caeb153-3244-4367-aeee-9b8b55a89543
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326440747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2326440747
Directory	/workspace/36.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/36.lc_ctrl_prog_failure.3804640237
Short name	T378
Test name
Test status
Simulation time	135942795 ps
CPU time	2.47 seconds
Started	Aug 11 07:07:48 PM PDT 24
Finished	Aug 11 07:07:51 PM PDT 24
Peak memory	221960 kb
Host	smart-08aee50b-adf5-49f6-9fa9-e644433a4ac3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804640237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3804640237
Directory	/workspace/36.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_mubi.3955843214
Short name	T789
Test name
Test status
Simulation time	576343093 ps
CPU time	9.06 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:55 PM PDT 24
Peak memory	225920 kb
Host	smart-7e3c65a6-7eb1-4a22-a84d-0f163574892c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955843214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3955843214
Directory	/workspace/36.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_digest.3499670581
Short name	T297
Test name
Test status
Simulation time	2654871616 ps
CPU time	9.3 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:56 PM PDT 24
Peak memory	218152 kb
Host	smart-e6af9984-61d6-439b-a650-8a2611cbbd8a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499670581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d igest.3499670581
Directory	/workspace/36.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_mux.1865031074
Short name	T388
Test name
Test status
Simulation time	1252176031 ps
CPU time	9.1 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:55 PM PDT 24
Peak memory	218052 kb
Host	smart-b3078374-f7e5-4828-be40-c7a794de61bb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865031074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux. 1865031074
Directory	/workspace/36.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/36.lc_ctrl_security_escalation.1651342426
Short name	T596
Test name
Test status
Simulation time	225476362 ps
CPU time	8.5 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:08:00 PM PDT 24
Peak memory	224584 kb
Host	smart-a04e303a-1a8c-4506-ae11-6f86e1019bd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651342426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1651342426
Directory	/workspace/36.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/36.lc_ctrl_smoke.2534891512
Short name	T873
Test name
Test status
Simulation time	518351003 ps
CPU time	4.31 seconds
Started	Aug 11 07:07:40 PM PDT 24
Finished	Aug 11 07:07:44 PM PDT 24
Peak memory	217452 kb
Host	smart-9744a466-48cc-45e4-95d7-8ca791060a84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534891512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2534891512
Directory	/workspace/36.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_failure.1143849448
Short name	T351
Test name
Test status
Simulation time	354525138 ps
CPU time	29.98 seconds
Started	Aug 11 07:07:44 PM PDT 24
Finished	Aug 11 07:08:14 PM PDT 24
Peak memory	250768 kb
Host	smart-aac15e74-2a4a-47ab-bb22-dd99913daf17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143849448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1143849448
Directory	/workspace/36.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_post_trans.2554358719
Short name	T376
Test name
Test status
Simulation time	214906002 ps
CPU time	6.37 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:53 PM PDT 24
Peak memory	250592 kb
Host	smart-12066d4c-e16c-4e9b-8ea2-3434013e8dbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554358719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2554358719
Directory	/workspace/36.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all.4214912643
Short name	T419
Test name
Test status
Simulation time	16254490259 ps
CPU time	231.62 seconds
Started	Aug 11 07:07:47 PM PDT 24
Finished	Aug 11 07:11:38 PM PDT 24
Peak memory	250912 kb
Host	smart-a2170237-61f1-4457-8802-44d3ec561de4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214912643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.4214912643
Directory	/workspace/36.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1437106216
Short name	T699
Test name
Test status
Simulation time	23391996 ps
CPU time	1.05 seconds
Started	Aug 11 07:07:41 PM PDT 24
Finished	Aug 11 07:07:42 PM PDT 24
Peak memory	211684 kb
Host	smart-e1e9d1bd-6872-409a-af26-1bcc2586ff6c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437106216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c trl_volatile_unlock_smoke.1437106216
Directory	/workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_alert_test.856900960
Short name	T92
Test name
Test status
Simulation time	17368153 ps
CPU time	0.92 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:47 PM PDT 24
Peak memory	208604 kb
Host	smart-057f8a66-ff60-430b-9419-65993314174f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856900960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.856900960
Directory	/workspace/37.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.lc_ctrl_errors.2027784289
Short name	T875
Test name
Test status
Simulation time	1214073271 ps
CPU time	13.18 seconds
Started	Aug 11 07:07:49 PM PDT 24
Finished	Aug 11 07:08:02 PM PDT 24
Peak memory	218080 kb
Host	smart-0c5865df-3551-4e08-b4a4-e080c3ce4fbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027784289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2027784289
Directory	/workspace/37.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/37.lc_ctrl_jtag_access.1666422724
Short name	T25
Test name
Test status
Simulation time	1061128374 ps
CPU time	13.17 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:08:05 PM PDT 24
Peak memory	217072 kb
Host	smart-b138b284-0125-4cc1-8fd1-0ecd28047dce
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666422724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1666422724
Directory	/workspace/37.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/37.lc_ctrl_prog_failure.1242259658
Short name	T802
Test name
Test status
Simulation time	142333746 ps
CPU time	2.53 seconds
Started	Aug 11 07:07:47 PM PDT 24
Finished	Aug 11 07:07:50 PM PDT 24
Peak memory	218036 kb
Host	smart-fbbb3a15-7b56-4bc7-8860-1e605f9a4409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242259658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1242259658
Directory	/workspace/37.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_mubi.317111931
Short name	T266
Test name
Test status
Simulation time	273971556 ps
CPU time	9.13 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:55 PM PDT 24
Peak memory	225924 kb
Host	smart-f8ccd719-08a8-489b-9671-528c8b2959c5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317111931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.317111931
Directory	/workspace/37.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_digest.3563651147
Short name	T436
Test name
Test status
Simulation time	3244391202 ps
CPU time	16.72 seconds
Started	Aug 11 07:07:45 PM PDT 24
Finished	Aug 11 07:08:02 PM PDT 24
Peak memory	218144 kb
Host	smart-f9ec8a09-c446-4a3d-b2a5-18a5da5a81ca
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563651147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d igest.3563651147
Directory	/workspace/37.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_mux.2965861641
Short name	T410
Test name
Test status
Simulation time	241255552 ps
CPU time	9.99 seconds
Started	Aug 11 07:07:45 PM PDT 24
Finished	Aug 11 07:07:55 PM PDT 24
Peak memory	218200 kb
Host	smart-e758378c-b344-4483-b56a-767564d5f0ea
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965861641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux. 2965861641
Directory	/workspace/37.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/37.lc_ctrl_security_escalation.362924700
Short name	T231
Test name
Test status
Simulation time	405743002 ps
CPU time	8.2 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:55 PM PDT 24
Peak memory	224996 kb
Host	smart-e550dd58-7fe0-4b70-956d-f814402f96e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362924700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.362924700
Directory	/workspace/37.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/37.lc_ctrl_smoke.2993628327
Short name	T85
Test name
Test status
Simulation time	190909250 ps
CPU time	2.97 seconds
Started	Aug 11 07:07:48 PM PDT 24
Finished	Aug 11 07:07:51 PM PDT 24
Peak memory	217480 kb
Host	smart-fa6e5cda-45b5-4a1d-abfb-2692fd0a3e03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993628327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2993628327
Directory	/workspace/37.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_failure.1225134527
Short name	T362
Test name
Test status
Simulation time	1251707776 ps
CPU time	24.75 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	250704 kb
Host	smart-656dcf31-d86e-4751-88e3-b1a4eef6e8dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225134527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1225134527
Directory	/workspace/37.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_post_trans.2519302608
Short name	T105
Test name
Test status
Simulation time	103857952 ps
CPU time	7.38 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:53 PM PDT 24
Peak memory	250584 kb
Host	smart-59eb6663-ffaf-48de-90fc-e0d08de2c413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519302608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2519302608
Directory	/workspace/37.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all.2410420307
Short name	T191
Test name
Test status
Simulation time	3084495723 ps
CPU time	71.3 seconds
Started	Aug 11 07:07:47 PM PDT 24
Finished	Aug 11 07:08:58 PM PDT 24
Peak memory	275432 kb
Host	smart-0f0bb56f-9e58-435a-8728-5e9c81312287
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410420307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.2410420307
Directory	/workspace/37.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1154155085
Short name	T769
Test name
Test status
Simulation time	206674094 ps
CPU time	0.83 seconds
Started	Aug 11 07:07:48 PM PDT 24
Finished	Aug 11 07:07:49 PM PDT 24
Peak memory	211652 kb
Host	smart-2bd29413-3dc0-4e2c-8f08-a3f23d66dc37
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154155085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c trl_volatile_unlock_smoke.1154155085
Directory	/workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_alert_test.1822930141
Short name	T258
Test name
Test status
Simulation time	75578625 ps
CPU time	1.2 seconds
Started	Aug 11 07:07:51 PM PDT 24
Finished	Aug 11 07:07:52 PM PDT 24
Peak memory	208728 kb
Host	smart-bbfb7d43-6687-40cb-9d67-7ba55749c971
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822930141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1822930141
Directory	/workspace/38.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.lc_ctrl_errors.2671196263
Short name	T9
Test name
Test status
Simulation time	1201186779 ps
CPU time	14.35 seconds
Started	Aug 11 07:07:53 PM PDT 24
Finished	Aug 11 07:08:07 PM PDT 24
Peak memory	218072 kb
Host	smart-a0638964-4f97-40bd-95ea-26ad8a1d265c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671196263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2671196263
Directory	/workspace/38.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/38.lc_ctrl_jtag_access.2620937863
Short name	T174
Test name
Test status
Simulation time	57803668 ps
CPU time	2.27 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:07:59 PM PDT 24
Peak memory	216932 kb
Host	smart-e051424b-b6a2-4351-95f4-5457df4d8152
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620937863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2620937863
Directory	/workspace/38.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/38.lc_ctrl_prog_failure.546482428
Short name	T876
Test name
Test status
Simulation time	180112009 ps
CPU time	2.96 seconds
Started	Aug 11 07:07:45 PM PDT 24
Finished	Aug 11 07:07:48 PM PDT 24
Peak memory	218020 kb
Host	smart-8725476b-8008-4fe4-ba0e-ad06e1f30d31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546482428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.546482428
Directory	/workspace/38.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_mubi.3237399708
Short name	T470
Test name
Test status
Simulation time	354902255 ps
CPU time	10.45 seconds
Started	Aug 11 07:07:54 PM PDT 24
Finished	Aug 11 07:08:04 PM PDT 24
Peak memory	225916 kb
Host	smart-1dff24f9-0438-4c7a-a7dc-d1bbe980cfe5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237399708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3237399708
Directory	/workspace/38.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_digest.1204870788
Short name	T239
Test name
Test status
Simulation time	306670846 ps
CPU time	10.73 seconds
Started	Aug 11 07:07:51 PM PDT 24
Finished	Aug 11 07:08:02 PM PDT 24
Peak memory	218048 kb
Host	smart-110739ab-a907-4fce-beb2-020d7c2336fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204870788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d igest.1204870788
Directory	/workspace/38.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_mux.2528364521
Short name	T359
Test name
Test status
Simulation time	1003238353 ps
CPU time	8.39 seconds
Started	Aug 11 07:07:56 PM PDT 24
Finished	Aug 11 07:08:05 PM PDT 24
Peak memory	225832 kb
Host	smart-41b01865-2c6c-47a7-97bf-47f7c9499428
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528364521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux. 2528364521
Directory	/workspace/38.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/38.lc_ctrl_security_escalation.1220406567
Short name	T230
Test name
Test status
Simulation time	754565868 ps
CPU time	8.03 seconds
Started	Aug 11 07:07:51 PM PDT 24
Finished	Aug 11 07:07:59 PM PDT 24
Peak memory	218180 kb
Host	smart-09611f72-a7e7-4337-814c-fb79e6a57409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220406567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1220406567
Directory	/workspace/38.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/38.lc_ctrl_smoke.1594559918
Short name	T70
Test name
Test status
Simulation time	43715953 ps
CPU time	2.07 seconds
Started	Aug 11 07:07:48 PM PDT 24
Finished	Aug 11 07:07:50 PM PDT 24
Peak memory	214080 kb
Host	smart-5b898263-c96c-4b5f-b690-7b99a807e4cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594559918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1594559918
Directory	/workspace/38.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_failure.3668672451
Short name	T839
Test name
Test status
Simulation time	277147604 ps
CPU time	23.48 seconds
Started	Aug 11 07:07:49 PM PDT 24
Finished	Aug 11 07:08:13 PM PDT 24
Peak memory	250788 kb
Host	smart-3b185327-c405-4577-b1ec-e03076f3992e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3668672451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3668672451
Directory	/workspace/38.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_post_trans.195951692
Short name	T382
Test name
Test status
Simulation time	179146843 ps
CPU time	7.81 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:54 PM PDT 24
Peak memory	242508 kb
Host	smart-89eacef6-8816-481f-a140-6a1f7ff483ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195951692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.195951692
Directory	/workspace/38.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all.3973108241
Short name	T375
Test name
Test status
Simulation time	7918524402 ps
CPU time	175.97 seconds
Started	Aug 11 07:07:53 PM PDT 24
Finished	Aug 11 07:10:49 PM PDT 24
Peak memory	283492 kb
Host	smart-bb1100d4-e1b1-4563-a7ad-6d8bdc3becc1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973108241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.3973108241
Directory	/workspace/38.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3824212853
Short name	T670
Test name
Test status
Simulation time	28283385755 ps
CPU time	368.79 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:14:07 PM PDT 24
Peak memory	283948 kb
Host	smart-01a90fa9-93b5-483d-99f5-2ceeb4ec7476
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3824212853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3824212853
Directory	/workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.225639776
Short name	T849
Test name
Test status
Simulation time	15266021 ps
CPU time	0.91 seconds
Started	Aug 11 07:07:46 PM PDT 24
Finished	Aug 11 07:07:47 PM PDT 24
Peak memory	212736 kb
Host	smart-bd298749-7573-4021-bb52-26ab0e876f44
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225639776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct rl_volatile_unlock_smoke.225639776
Directory	/workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_alert_test.1335335938
Short name	T301
Test name
Test status
Simulation time	26460762 ps
CPU time	1.01 seconds
Started	Aug 11 07:07:51 PM PDT 24
Finished	Aug 11 07:07:52 PM PDT 24
Peak memory	208696 kb
Host	smart-163d53ef-ad18-4a6a-aa0e-0d2edcbaf47d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335335938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1335335938
Directory	/workspace/39.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.lc_ctrl_errors.2696320101
Short name	T454
Test name
Test status
Simulation time	1199715400 ps
CPU time	10.42 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:08:03 PM PDT 24
Peak memory	218072 kb
Host	smart-afee8b24-503a-456f-8887-9512423832c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696320101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2696320101
Directory	/workspace/39.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/39.lc_ctrl_jtag_access.1768082536
Short name	T636
Test name
Test status
Simulation time	88611596 ps
CPU time	1.95 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:07:54 PM PDT 24
Peak memory	216936 kb
Host	smart-0b3fcd49-d070-4c5a-bda5-579b3c9d6d4a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768082536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1768082536
Directory	/workspace/39.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/39.lc_ctrl_prog_failure.3237025775
Short name	T252
Test name
Test status
Simulation time	57580876 ps
CPU time	2.93 seconds
Started	Aug 11 07:07:56 PM PDT 24
Finished	Aug 11 07:07:59 PM PDT 24
Peak memory	218072 kb
Host	smart-2492b24f-d492-4d5a-8f88-11c2dd331f47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237025775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3237025775
Directory	/workspace/39.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_mubi.3406019758
Short name	T767
Test name
Test status
Simulation time	634489938 ps
CPU time	16.22 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:14 PM PDT 24
Peak memory	226080 kb
Host	smart-d581eaac-b89b-4954-ab21-5281e51dbf0e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406019758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3406019758
Directory	/workspace/39.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_digest.2376046237
Short name	T778
Test name
Test status
Simulation time	11431092596 ps
CPU time	25.2 seconds
Started	Aug 11 07:07:53 PM PDT 24
Finished	Aug 11 07:08:18 PM PDT 24
Peak memory	225964 kb
Host	smart-5afbfab3-e6fd-493b-8489-52891684252f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376046237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d igest.2376046237
Directory	/workspace/39.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_mux.3773199884
Short name	T60
Test name
Test status
Simulation time	506213625 ps
CPU time	18.59 seconds
Started	Aug 11 07:07:51 PM PDT 24
Finished	Aug 11 07:08:09 PM PDT 24
Peak memory	218028 kb
Host	smart-a59ab47a-e005-413c-b11c-55f1d0ff9379
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773199884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux. 3773199884
Directory	/workspace/39.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/39.lc_ctrl_security_escalation.1189825729
Short name	T864
Test name
Test status
Simulation time	1341864091 ps
CPU time	8.17 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:08:05 PM PDT 24
Peak memory	225872 kb
Host	smart-733bc152-7635-4de0-b7e1-f7b1e9e7b9a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189825729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1189825729
Directory	/workspace/39.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/39.lc_ctrl_smoke.3584556999
Short name	T547
Test name
Test status
Simulation time	167387488 ps
CPU time	2.47 seconds
Started	Aug 11 07:07:54 PM PDT 24
Finished	Aug 11 07:07:56 PM PDT 24
Peak memory	217536 kb
Host	smart-0f5d6010-34de-4622-8f8d-71f5f1130230
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584556999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3584556999
Directory	/workspace/39.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_failure.422478132
Short name	T545
Test name
Test status
Simulation time	3659811103 ps
CPU time	30.7 seconds
Started	Aug 11 07:07:53 PM PDT 24
Finished	Aug 11 07:08:24 PM PDT 24
Peak memory	250776 kb
Host	smart-f6a575c2-285d-4407-ae61-b6ef4cf84967
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422478132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.422478132
Directory	/workspace/39.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_post_trans.859523077
Short name	T625
Test name
Test status
Simulation time	67048496 ps
CPU time	9.14 seconds
Started	Aug 11 07:07:53 PM PDT 24
Finished	Aug 11 07:08:02 PM PDT 24
Peak memory	244888 kb
Host	smart-542baf13-9032-42dc-8c84-925548097803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859523077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.859523077
Directory	/workspace/39.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all.1059757752
Short name	T841
Test name
Test status
Simulation time	31026821635 ps
CPU time	234.2 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:11:46 PM PDT 24
Peak memory	226044 kb
Host	smart-3752b65d-827d-4727-9702-d88eae5565ad
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059757752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.1059757752
Directory	/workspace/39.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.6717882
Short name	T149
Test name
Test status
Simulation time	135065743068 ps
CPU time	1063.84 seconds
Started	Aug 11 07:07:51 PM PDT 24
Finished	Aug 11 07:25:35 PM PDT 24
Peak memory	372716 kb
Host	smart-ad434c5e-b6e4-430c-8e86-63773cb2a620
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=6717882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.6717882
Directory	/workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3015628919
Short name	T533
Test name
Test status
Simulation time	12042929 ps
CPU time	0.96 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:07:58 PM PDT 24
Peak memory	211672 kb
Host	smart-f40b1b19-d5a7-4ec1-b7ba-cd1b1650722f
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015628919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c trl_volatile_unlock_smoke.3015628919
Directory	/workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_alert_test.2521791539
Short name	T442
Test name
Test status
Simulation time	21453774 ps
CPU time	0.97 seconds
Started	Aug 11 07:05:33 PM PDT 24
Finished	Aug 11 07:05:35 PM PDT 24
Peak memory	208672 kb
Host	smart-e4da6f00-a509-4db8-a1aa-1427e5e58bfe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521791539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2521791539
Directory	/workspace/4.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.lc_ctrl_errors.3846679089
Short name	T306
Test name
Test status
Simulation time	3776587955 ps
CPU time	24 seconds
Started	Aug 11 07:05:26 PM PDT 24
Finished	Aug 11 07:05:50 PM PDT 24
Peak memory	226036 kb
Host	smart-45ecf969-2d0d-46c4-8b96-c5369e1be4cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846679089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3846679089
Directory	/workspace/4.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_access.1263222971
Short name	T409
Test name
Test status
Simulation time	310193524 ps
CPU time	2.31 seconds
Started	Aug 11 07:05:32 PM PDT 24
Finished	Aug 11 07:05:34 PM PDT 24
Peak memory	216952 kb
Host	smart-17260125-f8fb-4395-b605-5f5180b94697
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263222971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1263222971
Directory	/workspace/4.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_errors.4188193401
Short name	T238
Test name
Test status
Simulation time	7484736088 ps
CPU time	35.47 seconds
Started	Aug 11 07:05:28 PM PDT 24
Finished	Aug 11 07:06:04 PM PDT 24
Peak memory	218756 kb
Host	smart-a7ea583c-c543-4cdf-963d-bb494b9eb417
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188193401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er rors.4188193401
Directory	/workspace/4.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_priority.708922712
Short name	T881
Test name
Test status
Simulation time	701182779 ps
CPU time	16.3 seconds
Started	Aug 11 07:05:33 PM PDT 24
Finished	Aug 11 07:05:49 PM PDT 24
Peak memory	217588 kb
Host	smart-c5c998dd-060f-438b-b1a3-66660380f089
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708922712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.708922712
Directory	/workspace/4.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.881394925
Short name	T293
Test name
Test status
Simulation time	1370124153 ps
CPU time	9.92 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:41 PM PDT 24
Peak memory	218044 kb
Host	smart-8c751dba-e987-4b08-b9ff-e3715f0033ce
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881394925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ prog_failure.881394925
Directory	/workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.424752680
Short name	T82
Test name
Test status
Simulation time	2126497543 ps
CPU time	28.2 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:59 PM PDT 24
Peak memory	217460 kb
Host	smart-9cfa866c-1ff4-4029-b527-2a3cd29f38ab
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424752680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j tag_regwen_during_op.424752680
Directory	/workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_smoke.414604802
Short name	T262
Test name
Test status
Simulation time	666806863 ps
CPU time	3.06 seconds
Started	Aug 11 07:05:26 PM PDT 24
Finished	Aug 11 07:05:29 PM PDT 24
Peak memory	217496 kb
Host	smart-c8f53d44-1ad7-4689-906d-a42b9d3c6bb8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414604802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.414604802
Directory	/workspace/4.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3299652539
Short name	T634
Test name
Test status
Simulation time	8453910091 ps
CPU time	76.31 seconds
Started	Aug 11 07:05:27 PM PDT 24
Finished	Aug 11 07:06:44 PM PDT 24
Peak memory	274208 kb
Host	smart-35c6bf16-ee77-4474-869f-2e9dfcd97a0e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299652539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta g_state_failure.3299652539
Directory	/workspace/4.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2769898933
Short name	T494
Test name
Test status
Simulation time	776615764 ps
CPU time	17.8 seconds
Started	Aug 11 07:05:27 PM PDT 24
Finished	Aug 11 07:05:44 PM PDT 24
Peak memory	248952 kb
Host	smart-83bca319-75b8-4e59-860d-491cc84af17d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769898933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_state_post_trans.2769898933
Directory	/workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_prog_failure.1139465745
Short name	T476
Test name
Test status
Simulation time	185748088 ps
CPU time	4.6 seconds
Started	Aug 11 07:05:29 PM PDT 24
Finished	Aug 11 07:05:33 PM PDT 24
Peak memory	218036 kb
Host	smart-19c6f580-c5db-4cc0-b8b1-8c041deb1ca9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139465745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1139465745
Directory	/workspace/4.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_regwen_during_op.1998669463
Short name	T197
Test name
Test status
Simulation time	300774735 ps
CPU time	16.85 seconds
Started	Aug 11 07:05:24 PM PDT 24
Finished	Aug 11 07:05:41 PM PDT 24
Peak memory	217540 kb
Host	smart-359d230d-9235-44d4-bf4f-fbc323342b7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998669463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1998669463
Directory	/workspace/4.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_cm.383469138
Short name	T51
Test name
Test status
Simulation time	514363112 ps
CPU time	22.16 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:05:52 PM PDT 24
Peak memory	282744 kb
Host	smart-693ad806-3aa3-44a1-9665-16e3d3a0c59f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383469138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.383469138
Directory	/workspace/4.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_mubi.290435977
Short name	T797
Test name
Test status
Simulation time	251478940 ps
CPU time	10.89 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	225924 kb
Host	smart-dc1ca920-0ac5-4e57-8d11-5fc53fd9e1ab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290435977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.290435977
Directory	/workspace/4.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_digest.1903046067
Short name	T283
Test name
Test status
Simulation time	900111521 ps
CPU time	10.93 seconds
Started	Aug 11 07:05:33 PM PDT 24
Finished	Aug 11 07:05:44 PM PDT 24
Peak memory	225852 kb
Host	smart-216b4f37-bf5f-410b-a54d-304329929720
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903046067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di gest.1903046067
Directory	/workspace/4.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_mux.2259872104
Short name	T535
Test name
Test status
Simulation time	217327294 ps
CPU time	9.05 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:41 PM PDT 24
Peak memory	218064 kb
Host	smart-3ce7e840-76e4-467e-a6a9-788b0654970b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259872104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2 259872104
Directory	/workspace/4.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/4.lc_ctrl_security_escalation.747659664
Short name	T49
Test name
Test status
Simulation time	347430191 ps
CPU time	8.32 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:33 PM PDT 24
Peak memory	225128 kb
Host	smart-9bc7890a-4356-4773-932a-00f438d15ce1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747659664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.747659664
Directory	/workspace/4.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/4.lc_ctrl_smoke.1347377870
Short name	T80
Test name
Test status
Simulation time	19564192 ps
CPU time	1.77 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:27 PM PDT 24
Peak memory	213704 kb
Host	smart-c4ccda5e-b283-4c7c-a250-616799ab47dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347377870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1347377870
Directory	/workspace/4.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_failure.789194247
Short name	T870
Test name
Test status
Simulation time	1889846562 ps
CPU time	32.01 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:57 PM PDT 24
Peak memory	246056 kb
Host	smart-98c31101-02a6-4802-a041-0610de11ca33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789194247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.789194247
Directory	/workspace/4.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_post_trans.2678587996
Short name	T486
Test name
Test status
Simulation time	441650812 ps
CPU time	6.59 seconds
Started	Aug 11 07:05:25 PM PDT 24
Finished	Aug 11 07:05:31 PM PDT 24
Peak memory	250736 kb
Host	smart-fc9ad727-e209-4769-9c1e-5d8894ade8d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678587996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2678587996
Directory	/workspace/4.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all.2127208334
Short name	T572
Test name
Test status
Simulation time	860569787 ps
CPU time	29.78 seconds
Started	Aug 11 07:05:33 PM PDT 24
Finished	Aug 11 07:06:02 PM PDT 24
Peak memory	228244 kb
Host	smart-a369684d-99bd-423a-86b5-a6a74c7094d8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127208334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.2127208334
Directory	/workspace/4.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.547110593
Short name	T249
Test name
Test status
Simulation time	43347602 ps
CPU time	0.83 seconds
Started	Aug 11 07:05:28 PM PDT 24
Finished	Aug 11 07:05:29 PM PDT 24
Peak memory	211732 kb
Host	smart-8f3168ee-fca3-4cce-86d3-463ed767d6f9
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547110593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr l_volatile_unlock_smoke.547110593
Directory	/workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_alert_test.4088003625
Short name	T190
Test name
Test status
Simulation time	185129945 ps
CPU time	0.95 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:07:53 PM PDT 24
Peak memory	208728 kb
Host	smart-78b447b7-51f3-480a-b063-c168609e3f74
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088003625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.4088003625
Directory	/workspace/40.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.lc_ctrl_errors.366202018
Short name	T242
Test name
Test status
Simulation time	447822984 ps
CPU time	11.45 seconds
Started	Aug 11 07:07:54 PM PDT 24
Finished	Aug 11 07:08:05 PM PDT 24
Peak memory	218100 kb
Host	smart-07e2b769-b8c9-4c3b-b23c-7f9fe97e2b38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366202018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.366202018
Directory	/workspace/40.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/40.lc_ctrl_jtag_access.377942644
Short name	T432
Test name
Test status
Simulation time	561922027 ps
CPU time	13.85 seconds
Started	Aug 11 07:07:56 PM PDT 24
Finished	Aug 11 07:08:09 PM PDT 24
Peak memory	217136 kb
Host	smart-cf9b3607-4584-48f1-8c9c-e636f673cb6e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377942644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.377942644
Directory	/workspace/40.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/40.lc_ctrl_prog_failure.2059215022
Short name	T241
Test name
Test status
Simulation time	45382657 ps
CPU time	1.93 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:07:54 PM PDT 24
Peak memory	218076 kb
Host	smart-6d924135-bbfc-40de-886b-2ab549e4663b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059215022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2059215022
Directory	/workspace/40.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_mubi.3560198322
Short name	T289
Test name
Test status
Simulation time	685209262 ps
CPU time	18.31 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	218908 kb
Host	smart-b3fbd030-af1f-426c-8f1b-0d769293952c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560198322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3560198322
Directory	/workspace/40.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_digest.3288634351
Short name	T178
Test name
Test status
Simulation time	1793896704 ps
CPU time	9.87 seconds
Started	Aug 11 07:07:50 PM PDT 24
Finished	Aug 11 07:08:00 PM PDT 24
Peak memory	217996 kb
Host	smart-7baabbde-91f7-4c8c-a225-a4240c92ff51
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288634351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d igest.3288634351
Directory	/workspace/40.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_mux.217788587
Short name	T179
Test name
Test status
Simulation time	344687677 ps
CPU time	5.27 seconds
Started	Aug 11 07:07:54 PM PDT 24
Finished	Aug 11 07:07:59 PM PDT 24
Peak memory	217996 kb
Host	smart-04e35dce-6d0e-4f29-9dde-e077cd7178c8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217788587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.217788587
Directory	/workspace/40.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/40.lc_ctrl_security_escalation.1820881270
Short name	T397
Test name
Test status
Simulation time	282033419 ps
CPU time	7.24 seconds
Started	Aug 11 07:07:54 PM PDT 24
Finished	Aug 11 07:08:01 PM PDT 24
Peak memory	218160 kb
Host	smart-70d4fddf-4186-4c43-8f3f-80c9718a956b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820881270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1820881270
Directory	/workspace/40.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/40.lc_ctrl_smoke.3217453864
Short name	T665
Test name
Test status
Simulation time	67764786 ps
CPU time	4.77 seconds
Started	Aug 11 07:07:56 PM PDT 24
Finished	Aug 11 07:08:01 PM PDT 24
Peak memory	217512 kb
Host	smart-1b99f167-598b-4303-8a04-af62a01837b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217453864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3217453864
Directory	/workspace/40.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_failure.1694183783
Short name	T324
Test name
Test status
Simulation time	460681709 ps
CPU time	26.94 seconds
Started	Aug 11 07:07:56 PM PDT 24
Finished	Aug 11 07:08:23 PM PDT 24
Peak memory	250784 kb
Host	smart-bb0f0e93-9641-497f-aeff-874a90615650
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694183783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1694183783
Directory	/workspace/40.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_post_trans.1685477441
Short name	T232
Test name
Test status
Simulation time	273641328 ps
CPU time	6.62 seconds
Started	Aug 11 07:07:52 PM PDT 24
Finished	Aug 11 07:07:59 PM PDT 24
Peak memory	247204 kb
Host	smart-d26b612c-d9b8-4401-9bd9-ac8c2a0602e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685477441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1685477441
Directory	/workspace/40.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all.2906527028
Short name	T646
Test name
Test status
Simulation time	5163271618 ps
CPU time	94.86 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:09:32 PM PDT 24
Peak memory	250816 kb
Host	smart-c5dafdf5-00f7-4d18-a9e7-919e4f0816aa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906527028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all.2906527028
Directory	/workspace/40.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1305317994
Short name	T516
Test name
Test status
Simulation time	77287261 ps
CPU time	0.82 seconds
Started	Aug 11 07:07:53 PM PDT 24
Finished	Aug 11 07:07:54 PM PDT 24
Peak memory	211644 kb
Host	smart-27859b2d-9e32-4885-a8bd-f9db162e158b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305317994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c trl_volatile_unlock_smoke.1305317994
Directory	/workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_alert_test.2483487069
Short name	T867
Test name
Test status
Simulation time	16676910 ps
CPU time	0.9 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:07:59 PM PDT 24
Peak memory	208688 kb
Host	smart-bbbf9948-debf-48d5-bc01-61700bfe1225
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483487069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2483487069
Directory	/workspace/41.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.lc_ctrl_errors.2632911107
Short name	T787
Test name
Test status
Simulation time	1502967586 ps
CPU time	15.74 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:08:13 PM PDT 24
Peak memory	218060 kb
Host	smart-93e88393-3994-4640-b91b-e6ae09e35476
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632911107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2632911107
Directory	/workspace/41.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/41.lc_ctrl_jtag_access.33712986
Short name	T457
Test name
Test status
Simulation time	2310138816 ps
CPU time	6.13 seconds
Started	Aug 11 07:07:59 PM PDT 24
Finished	Aug 11 07:08:05 PM PDT 24
Peak memory	216876 kb
Host	smart-3ae906ae-7a17-4eac-b908-05de1d05b779
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33712986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.33712986
Directory	/workspace/41.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/41.lc_ctrl_prog_failure.4138062501
Short name	T518
Test name
Test status
Simulation time	28086654 ps
CPU time	1.81 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:00 PM PDT 24
Peak memory	221880 kb
Host	smart-06df6453-22dc-45b9-aaf5-8c55b1b7661b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138062501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4138062501
Directory	/workspace/41.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_mubi.4152815364
Short name	T861
Test name
Test status
Simulation time	442180263 ps
CPU time	10.45 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:09 PM PDT 24
Peak memory	218108 kb
Host	smart-74211448-255f-45c6-ae9e-5a6c48b2fd9f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152815364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.4152815364
Directory	/workspace/41.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_digest.1386253829
Short name	T490
Test name
Test status
Simulation time	600371884 ps
CPU time	17.65 seconds
Started	Aug 11 07:07:59 PM PDT 24
Finished	Aug 11 07:08:16 PM PDT 24
Peak memory	225844 kb
Host	smart-82d96cc2-1c56-4f4e-9535-d1f02a10b27a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386253829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d igest.1386253829
Directory	/workspace/41.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_mux.3828238686
Short name	T590
Test name
Test status
Simulation time	850031645 ps
CPU time	6.59 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:05 PM PDT 24
Peak memory	225800 kb
Host	smart-4008240a-13d6-41ae-a98e-045ee2ed545c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828238686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux. 3828238686
Directory	/workspace/41.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/41.lc_ctrl_security_escalation.1153195281
Short name	T791
Test name
Test status
Simulation time	4460245949 ps
CPU time	19.11 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	226020 kb
Host	smart-05255e2a-0e02-4333-8ee7-2648eda9affe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153195281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1153195281
Directory	/workspace/41.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/41.lc_ctrl_smoke.2145429860
Short name	T86
Test name
Test status
Simulation time	39472037 ps
CPU time	2.43 seconds
Started	Aug 11 07:07:53 PM PDT 24
Finished	Aug 11 07:07:55 PM PDT 24
Peak memory	223144 kb
Host	smart-1a7db9e1-4ee7-4181-8089-8124cc4beac0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145429860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2145429860
Directory	/workspace/41.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_failure.1007382787
Short name	T483
Test name
Test status
Simulation time	595075870 ps
CPU time	22.13 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:08:19 PM PDT 24
Peak memory	250808 kb
Host	smart-d0c08cbd-8265-45c0-a9b2-e0077d38fe00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1007382787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1007382787
Directory	/workspace/41.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_post_trans.193958353
Short name	T256
Test name
Test status
Simulation time	60173045 ps
CPU time	8.95 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:07 PM PDT 24
Peak memory	250796 kb
Host	smart-38b3c90c-1a96-4090-9bdc-66cc239e3f56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193958353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.193958353
Directory	/workspace/41.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all.454904035
Short name	T531
Test name
Test status
Simulation time	24606504697 ps
CPU time	216.52 seconds
Started	Aug 11 07:07:59 PM PDT 24
Finished	Aug 11 07:11:36 PM PDT 24
Peak memory	277752 kb
Host	smart-c0ff5c12-d5fc-453c-b8d2-cc90b003b8bd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454904035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.454904035
Directory	/workspace/41.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3574612820
Short name	T754
Test name
Test status
Simulation time	364371630586 ps
CPU time	1240.49 seconds
Started	Aug 11 07:07:59 PM PDT 24
Finished	Aug 11 07:28:40 PM PDT 24
Peak memory	529592 kb
Host	smart-fdadb08d-16e6-44a7-8caf-6a9c1c875acb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3574612820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3574612820
Directory	/workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.874902501
Short name	T630
Test name
Test status
Simulation time	22348414 ps
CPU time	1.02 seconds
Started	Aug 11 07:07:53 PM PDT 24
Finished	Aug 11 07:07:54 PM PDT 24
Peak memory	212692 kb
Host	smart-faa49ba9-a70c-4843-8605-0edc50b9f897
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874902501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct rl_volatile_unlock_smoke.874902501
Directory	/workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_alert_test.1088989420
Short name	T98
Test name
Test status
Simulation time	18554333 ps
CPU time	1.1 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:00 PM PDT 24
Peak memory	208792 kb
Host	smart-d0c08a9b-ba1c-4f9d-963f-445a01175c11
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088989420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1088989420
Directory	/workspace/42.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.lc_ctrl_errors.564493561
Short name	T276
Test name
Test status
Simulation time	1791245434 ps
CPU time	16.08 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:08:14 PM PDT 24
Peak memory	218128 kb
Host	smart-299a4798-11b0-4340-8625-7940bc0bff83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=564493561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.564493561
Directory	/workspace/42.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/42.lc_ctrl_jtag_access.2999046824
Short name	T792
Test name
Test status
Simulation time	852312304 ps
CPU time	5.8 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:03 PM PDT 24
Peak memory	217336 kb
Host	smart-7b5bde90-bb5d-4193-befb-f85c8fa3d691
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999046824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2999046824
Directory	/workspace/42.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/42.lc_ctrl_prog_failure.112154304
Short name	T525
Test name
Test status
Simulation time	193070284 ps
CPU time	2.75 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:00 PM PDT 24
Peak memory	218100 kb
Host	smart-b1221ade-a9cb-4fed-bcfe-5b01a5a9a7d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112154304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.112154304
Directory	/workspace/42.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_mubi.370388381
Short name	T352
Test name
Test status
Simulation time	224634559 ps
CPU time	8.85 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:08:06 PM PDT 24
Peak memory	225904 kb
Host	smart-9221b4dc-6ddb-4938-ad24-abe68ae48797
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370388381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.370388381
Directory	/workspace/42.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_digest.1277871939
Short name	T484
Test name
Test status
Simulation time	14674093321 ps
CPU time	19.51 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:08:16 PM PDT 24
Peak memory	218184 kb
Host	smart-4c83fe20-32eb-4682-b1e1-85a5e031025f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277871939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d igest.1277871939
Directory	/workspace/42.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_mux.412695285
Short name	T310
Test name
Test status
Simulation time	489693059 ps
CPU time	8.48 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:07 PM PDT 24
Peak memory	225804 kb
Host	smart-c7a2f599-9d2f-498e-9831-ce257df43f3c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412695285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.412695285
Directory	/workspace/42.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/42.lc_ctrl_security_escalation.743610118
Short name	T588
Test name
Test status
Simulation time	1019111471 ps
CPU time	10.84 seconds
Started	Aug 11 07:08:02 PM PDT 24
Finished	Aug 11 07:08:13 PM PDT 24
Peak memory	225884 kb
Host	smart-095a99aa-8030-4afc-b5f9-c01536c64fa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=743610118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.743610118
Directory	/workspace/42.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/42.lc_ctrl_smoke.505428502
Short name	T790
Test name
Test status
Simulation time	30278922 ps
CPU time	1.06 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:07:59 PM PDT 24
Peak memory	217528 kb
Host	smart-c0087de5-397f-4ca4-90cd-4de18bee31ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505428502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.505428502
Directory	/workspace/42.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_failure.2515519497
Short name	T386
Test name
Test status
Simulation time	945917348 ps
CPU time	14.68 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:08:12 PM PDT 24
Peak memory	250792 kb
Host	smart-578feb04-cbd3-4b34-a124-9dc7b9d3f6a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515519497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2515519497
Directory	/workspace/42.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_post_trans.140232060
Short name	T467
Test name
Test status
Simulation time	307633486 ps
CPU time	8.81 seconds
Started	Aug 11 07:07:59 PM PDT 24
Finished	Aug 11 07:08:08 PM PDT 24
Peak memory	250716 kb
Host	smart-243e856e-157e-45b7-a6dc-b92cfcbc1305
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140232060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.140232060
Directory	/workspace/42.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.224943402
Short name	T827
Test name
Test status
Simulation time	46836394 ps
CPU time	0.99 seconds
Started	Aug 11 07:07:57 PM PDT 24
Finished	Aug 11 07:07:58 PM PDT 24
Peak memory	211728 kb
Host	smart-dbd70e56-8db5-4be6-94b3-4de3cf984ce0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224943402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct rl_volatile_unlock_smoke.224943402
Directory	/workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_alert_test.2375865197
Short name	T426
Test name
Test status
Simulation time	81203188 ps
CPU time	1.15 seconds
Started	Aug 11 07:08:09 PM PDT 24
Finished	Aug 11 07:08:10 PM PDT 24
Peak memory	208700 kb
Host	smart-244fedce-8469-49c5-ae47-408f8fdc4f5e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375865197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2375865197
Directory	/workspace/43.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.lc_ctrl_errors.292824429
Short name	T348
Test name
Test status
Simulation time	267515282 ps
CPU time	12.73 seconds
Started	Aug 11 07:08:05 PM PDT 24
Finished	Aug 11 07:08:18 PM PDT 24
Peak memory	225912 kb
Host	smart-35b939be-3af9-4753-b338-84a2a619d2e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292824429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.292824429
Directory	/workspace/43.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/43.lc_ctrl_jtag_access.2014784387
Short name	T576
Test name
Test status
Simulation time	5145893268 ps
CPU time	12.89 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:20 PM PDT 24
Peak memory	217612 kb
Host	smart-c46dd5a3-310d-47bd-ac8d-030f15163b4a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014784387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2014784387
Directory	/workspace/43.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/43.lc_ctrl_prog_failure.3329867072
Short name	T538
Test name
Test status
Simulation time	71445066 ps
CPU time	2.95 seconds
Started	Aug 11 07:08:08 PM PDT 24
Finished	Aug 11 07:08:11 PM PDT 24
Peak memory	218080 kb
Host	smart-ed7d5196-102e-4f97-aa3e-69baac4824c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329867072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3329867072
Directory	/workspace/43.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_mubi.3445603141
Short name	T328
Test name
Test status
Simulation time	436472406 ps
CPU time	13.49 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:21 PM PDT 24
Peak memory	225880 kb
Host	smart-910c196f-0969-4b03-9ab5-0fa918d15523
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445603141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3445603141
Directory	/workspace/43.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_digest.2479089957
Short name	T560
Test name
Test status
Simulation time	891237087 ps
CPU time	19.09 seconds
Started	Aug 11 07:08:06 PM PDT 24
Finished	Aug 11 07:08:25 PM PDT 24
Peak memory	218016 kb
Host	smart-c7a6eab0-8dbb-4814-b108-03ff52d900c9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479089957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d igest.2479089957
Directory	/workspace/43.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_mux.226007238
Short name	T840
Test name
Test status
Simulation time	916525853 ps
CPU time	9.66 seconds
Started	Aug 11 07:08:09 PM PDT 24
Finished	Aug 11 07:08:19 PM PDT 24
Peak memory	218052 kb
Host	smart-07ba4b1f-8930-48a7-af09-3aaf69e69237
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226007238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.226007238
Directory	/workspace/43.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/43.lc_ctrl_security_escalation.2642533598
Short name	T691
Test name
Test status
Simulation time	1819820923 ps
CPU time	12.11 seconds
Started	Aug 11 07:08:06 PM PDT 24
Finished	Aug 11 07:08:18 PM PDT 24
Peak memory	218184 kb
Host	smart-1dea9b2c-5c02-4f20-bbd3-562281afe782
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642533598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2642533598
Directory	/workspace/43.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/43.lc_ctrl_smoke.131657916
Short name	T793
Test name
Test status
Simulation time	200450408 ps
CPU time	4.77 seconds
Started	Aug 11 07:07:58 PM PDT 24
Finished	Aug 11 07:08:03 PM PDT 24
Peak memory	217520 kb
Host	smart-f08bcb5c-1b03-431a-a710-435004708fdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131657916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.131657916
Directory	/workspace/43.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_failure.213202228
Short name	T684
Test name
Test status
Simulation time	358598420 ps
CPU time	33.67 seconds
Started	Aug 11 07:08:00 PM PDT 24
Finished	Aug 11 07:08:34 PM PDT 24
Peak memory	250776 kb
Host	smart-a777c234-218b-4ee7-8d8f-d20c76091bde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213202228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.213202228
Directory	/workspace/43.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_post_trans.4287603539
Short name	T447
Test name
Test status
Simulation time	110846477 ps
CPU time	7.57 seconds
Started	Aug 11 07:08:08 PM PDT 24
Finished	Aug 11 07:08:16 PM PDT 24
Peak memory	250776 kb
Host	smart-2bbc8fa4-5dcc-4b81-b6a1-bbcb27302099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287603539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.4287603539
Directory	/workspace/43.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all.2577668412
Short name	T739
Test name
Test status
Simulation time	8998795074 ps
CPU time	210.31 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:11:38 PM PDT 24
Peak memory	283684 kb
Host	smart-47ff66fb-eba4-4ffd-9472-dd7c7c59ad7a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577668412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.2577668412
Directory	/workspace/43.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.388635682
Short name	T654
Test name
Test status
Simulation time	12963728 ps
CPU time	1.03 seconds
Started	Aug 11 07:07:59 PM PDT 24
Finished	Aug 11 07:08:00 PM PDT 24
Peak memory	211796 kb
Host	smart-d4eba4a6-ea17-49d9-b834-be8dcb037d3b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388635682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct rl_volatile_unlock_smoke.388635682
Directory	/workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_alert_test.1270337607
Short name	T514
Test name
Test status
Simulation time	24123569 ps
CPU time	0.93 seconds
Started	Aug 11 07:08:08 PM PDT 24
Finished	Aug 11 07:08:09 PM PDT 24
Peak memory	208688 kb
Host	smart-b0ddb579-ca68-4efc-af5b-785f78d93388
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270337607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1270337607
Directory	/workspace/44.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.lc_ctrl_errors.1989445525
Short name	T645
Test name
Test status
Simulation time	320376881 ps
CPU time	10.41 seconds
Started	Aug 11 07:08:06 PM PDT 24
Finished	Aug 11 07:08:16 PM PDT 24
Peak memory	218092 kb
Host	smart-f353ec49-8b40-4621-aee0-6bcac332a7d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989445525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1989445525
Directory	/workspace/44.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/44.lc_ctrl_jtag_access.2195577985
Short name	T664
Test name
Test status
Simulation time	756517386 ps
CPU time	3.38 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:11 PM PDT 24
Peak memory	216892 kb
Host	smart-5e691b44-0d18-4005-8e85-50b90d934515
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195577985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2195577985
Directory	/workspace/44.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/44.lc_ctrl_prog_failure.1115980287
Short name	T312
Test name
Test status
Simulation time	53613376 ps
CPU time	1.45 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:09 PM PDT 24
Peak memory	218092 kb
Host	smart-593313e9-830a-44f2-abb4-ec6b9b4cc0dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115980287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1115980287
Directory	/workspace/44.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_mubi.1800141586
Short name	T612
Test name
Test status
Simulation time	3234413015 ps
CPU time	15.98 seconds
Started	Aug 11 07:08:06 PM PDT 24
Finished	Aug 11 07:08:22 PM PDT 24
Peak memory	225996 kb
Host	smart-fde986b3-1699-41a5-8549-bb1c6defdbaa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800141586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1800141586
Directory	/workspace/44.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_digest.776017089
Short name	T363
Test name
Test status
Simulation time	289750781 ps
CPU time	13.43 seconds
Started	Aug 11 07:08:08 PM PDT 24
Finished	Aug 11 07:08:21 PM PDT 24
Peak memory	225852 kb
Host	smart-3dbacc46-93ea-4ef3-9d91-d83ff6718274
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776017089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di gest.776017089
Directory	/workspace/44.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_mux.1981266213
Short name	T765
Test name
Test status
Simulation time	285328850 ps
CPU time	9.41 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	218012 kb
Host	smart-5bbdf293-a7a2-435d-90a1-7d8df39aafa7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981266213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux. 1981266213
Directory	/workspace/44.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/44.lc_ctrl_security_escalation.1153505260
Short name	T637
Test name
Test status
Simulation time	573824425 ps
CPU time	12.71 seconds
Started	Aug 11 07:08:06 PM PDT 24
Finished	Aug 11 07:08:19 PM PDT 24
Peak memory	218156 kb
Host	smart-72b2733e-a7db-49d5-a2e1-b768fbe9cca5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153505260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1153505260
Directory	/workspace/44.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/44.lc_ctrl_smoke.1080964682
Short name	T736
Test name
Test status
Simulation time	23835154 ps
CPU time	1.84 seconds
Started	Aug 11 07:08:09 PM PDT 24
Finished	Aug 11 07:08:11 PM PDT 24
Peak memory	217360 kb
Host	smart-d1246e52-e633-4461-92aa-9d88180e4101
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080964682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1080964682
Directory	/workspace/44.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_failure.2297725208
Short name	T622
Test name
Test status
Simulation time	331634457 ps
CPU time	26.56 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:34 PM PDT 24
Peak memory	250820 kb
Host	smart-4679a096-46fa-41f4-b0af-1afda35a2aad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297725208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2297725208
Directory	/workspace/44.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_post_trans.1323128711
Short name	T387
Test name
Test status
Simulation time	338848078 ps
CPU time	8.23 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:16 PM PDT 24
Peak memory	250828 kb
Host	smart-8d151290-c54b-4522-9f2c-b18928f0402e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323128711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1323128711
Directory	/workspace/44.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all.504550278
Short name	T396
Test name
Test status
Simulation time	4469158717 ps
CPU time	52.65 seconds
Started	Aug 11 07:08:08 PM PDT 24
Finished	Aug 11 07:09:01 PM PDT 24
Peak memory	250896 kb
Host	smart-13c25eb3-4a60-4a89-9ed9-5492eb08b1e7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504550278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.504550278
Directory	/workspace/44.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3641565229
Short name	T146
Test name
Test status
Simulation time	3737629702 ps
CPU time	160.82 seconds
Started	Aug 11 07:08:06 PM PDT 24
Finished	Aug 11 07:10:47 PM PDT 24
Peak memory	274144 kb
Host	smart-b8e55b24-5b14-4cf1-8fb0-459e4cc513b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3641565229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3641565229
Directory	/workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2412590086
Short name	T750
Test name
Test status
Simulation time	38476391 ps
CPU time	0.89 seconds
Started	Aug 11 07:08:06 PM PDT 24
Finished	Aug 11 07:08:07 PM PDT 24
Peak memory	212736 kb
Host	smart-a595b730-b245-4860-b254-04262a64b276
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412590086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c trl_volatile_unlock_smoke.2412590086
Directory	/workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_alert_test.2251341112
Short name	T597
Test name
Test status
Simulation time	54005870 ps
CPU time	1.83 seconds
Started	Aug 11 07:08:15 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	208832 kb
Host	smart-a7fd2477-1c4e-4e5e-8bfc-107d9d45fd91
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251341112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2251341112
Directory	/workspace/45.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.lc_ctrl_errors.3213577569
Short name	T311
Test name
Test status
Simulation time	395854681 ps
CPU time	11.83 seconds
Started	Aug 11 07:08:08 PM PDT 24
Finished	Aug 11 07:08:20 PM PDT 24
Peak memory	217808 kb
Host	smart-3b2554ed-c50c-41de-aa8c-c35d06389eb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213577569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3213577569
Directory	/workspace/45.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/45.lc_ctrl_jtag_access.3958201463
Short name	T29
Test name
Test status
Simulation time	662829924 ps
CPU time	2.77 seconds
Started	Aug 11 07:08:09 PM PDT 24
Finished	Aug 11 07:08:12 PM PDT 24
Peak memory	217120 kb
Host	smart-1940cfe0-be3d-43d1-8c09-10cc5792c388
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958201463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3958201463
Directory	/workspace/45.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/45.lc_ctrl_prog_failure.706603273
Short name	T871
Test name
Test status
Simulation time	65059596 ps
CPU time	2.81 seconds
Started	Aug 11 07:08:05 PM PDT 24
Finished	Aug 11 07:08:08 PM PDT 24
Peak memory	218096 kb
Host	smart-1254d512-cc00-4ae7-bfb2-1ed89c528722
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706603273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.706603273
Directory	/workspace/45.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_mubi.1996617754
Short name	T510
Test name
Test status
Simulation time	1097805497 ps
CPU time	23.74 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:31 PM PDT 24
Peak memory	225912 kb
Host	smart-c3d20537-e2fd-40d7-8dfa-8b68c95b2d6e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996617754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1996617754
Directory	/workspace/45.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_digest.1853402756
Short name	T420
Test name
Test status
Simulation time	4524982419 ps
CPU time	27.08 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:08:34 PM PDT 24
Peak memory	225956 kb
Host	smart-47948c7c-6422-4fec-b9f3-490572d44846
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853402756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d igest.1853402756
Directory	/workspace/45.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_mux.3975636967
Short name	T61
Test name
Test status
Simulation time	822169880 ps
CPU time	8.34 seconds
Started	Aug 11 07:08:04 PM PDT 24
Finished	Aug 11 07:08:13 PM PDT 24
Peak memory	217996 kb
Host	smart-d9230052-8c3c-47c6-9177-40b3bfe0387d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975636967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux. 3975636967
Directory	/workspace/45.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/45.lc_ctrl_security_escalation.1822540880
Short name	T737
Test name
Test status
Simulation time	1062265054 ps
CPU time	7.52 seconds
Started	Aug 11 07:08:08 PM PDT 24
Finished	Aug 11 07:08:15 PM PDT 24
Peak memory	224876 kb
Host	smart-1e4c014e-923d-4525-ad97-3912ece858fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822540880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1822540880
Directory	/workspace/45.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/45.lc_ctrl_smoke.863002726
Short name	T424
Test name
Test status
Simulation time	33982420 ps
CPU time	2.64 seconds
Started	Aug 11 07:08:06 PM PDT 24
Finished	Aug 11 07:08:09 PM PDT 24
Peak memory	217524 kb
Host	smart-666052da-a504-4a48-9678-1c31dc2872e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863002726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.863002726
Directory	/workspace/45.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_failure.88757948
Short name	T530
Test name
Test status
Simulation time	256051830 ps
CPU time	28.35 seconds
Started	Aug 11 07:08:09 PM PDT 24
Finished	Aug 11 07:08:38 PM PDT 24
Peak memory	250632 kb
Host	smart-84a2b501-948f-4e7d-96df-6ae64f795409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88757948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.88757948
Directory	/workspace/45.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_post_trans.1119833647
Short name	T448
Test name
Test status
Simulation time	152591194 ps
CPU time	6.55 seconds
Started	Aug 11 07:08:08 PM PDT 24
Finished	Aug 11 07:08:15 PM PDT 24
Peak memory	242432 kb
Host	smart-266ffac1-0a51-4200-b7d1-d68246c6beb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119833647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1119833647
Directory	/workspace/45.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all.1849937572
Short name	T464
Test name
Test status
Simulation time	3550046874 ps
CPU time	83.47 seconds
Started	Aug 11 07:08:07 PM PDT 24
Finished	Aug 11 07:09:30 PM PDT 24
Peak memory	226044 kb
Host	smart-1c7785a3-785c-4d61-94f8-ac71226fd476
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849937572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.1849937572
Directory	/workspace/45.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.97351870
Short name	T753
Test name
Test status
Simulation time	28449010158 ps
CPU time	575.72 seconds
Started	Aug 11 07:08:14 PM PDT 24
Finished	Aug 11 07:17:49 PM PDT 24
Peak memory	496820 kb
Host	smart-5233b34b-5fcc-4ad5-9e86-561ae57cd294
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=97351870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.97351870
Directory	/workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1674255311
Short name	T475
Test name
Test status
Simulation time	125642140 ps
CPU time	0.87 seconds
Started	Aug 11 07:08:09 PM PDT 24
Finished	Aug 11 07:08:10 PM PDT 24
Peak memory	211720 kb
Host	smart-0ce568ab-a921-4426-b064-b14f97ba26f3
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674255311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c trl_volatile_unlock_smoke.1674255311
Directory	/workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_alert_test.3559231795
Short name	T618
Test name
Test status
Simulation time	24610604 ps
CPU time	1.22 seconds
Started	Aug 11 07:08:11 PM PDT 24
Finished	Aug 11 07:08:12 PM PDT 24
Peak memory	208752 kb
Host	smart-05d9f06e-9191-4155-8f0d-467965391993
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559231795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3559231795
Directory	/workspace/46.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.lc_ctrl_errors.2053953104
Short name	T823
Test name
Test status
Simulation time	495031173 ps
CPU time	12.65 seconds
Started	Aug 11 07:08:10 PM PDT 24
Finished	Aug 11 07:08:23 PM PDT 24
Peak memory	218108 kb
Host	smart-b4e4d791-43cb-4fb1-ac92-7a909823560b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053953104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2053953104
Directory	/workspace/46.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/46.lc_ctrl_jtag_access.2102444628
Short name	T608
Test name
Test status
Simulation time	942643450 ps
CPU time	21.58 seconds
Started	Aug 11 07:08:13 PM PDT 24
Finished	Aug 11 07:08:35 PM PDT 24
Peak memory	217364 kb
Host	smart-aa3fa372-8ef5-43df-b079-c9995865ae46
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102444628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2102444628
Directory	/workspace/46.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/46.lc_ctrl_prog_failure.1598359287
Short name	T655
Test name
Test status
Simulation time	100855295 ps
CPU time	4.37 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	218056 kb
Host	smart-11ac10a7-7267-4102-8446-50db139cdb4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598359287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1598359287
Directory	/workspace/46.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_mubi.3308421966
Short name	T503
Test name
Test status
Simulation time	2273241192 ps
CPU time	17.06 seconds
Started	Aug 11 07:08:18 PM PDT 24
Finished	Aug 11 07:08:36 PM PDT 24
Peak memory	226116 kb
Host	smart-dc311fa3-589e-45ae-95e8-e9c0b2206837
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308421966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3308421966
Directory	/workspace/46.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_digest.684008355
Short name	T55
Test name
Test status
Simulation time	982218249 ps
CPU time	11.7 seconds
Started	Aug 11 07:08:11 PM PDT 24
Finished	Aug 11 07:08:23 PM PDT 24
Peak memory	218048 kb
Host	smart-b27ea300-c6d7-4d86-9d93-1d3aa04141a4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684008355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di gest.684008355
Directory	/workspace/46.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_mux.1041145803
Short name	T498
Test name
Test status
Simulation time	1773821207 ps
CPU time	10.56 seconds
Started	Aug 11 07:08:13 PM PDT 24
Finished	Aug 11 07:08:24 PM PDT 24
Peak memory	217928 kb
Host	smart-f569ed9d-cf77-400f-a3e6-9a1bc1e1619b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041145803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux. 1041145803
Directory	/workspace/46.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/46.lc_ctrl_security_escalation.3281897919
Short name	T804
Test name
Test status
Simulation time	380537850 ps
CPU time	10.25 seconds
Started	Aug 11 07:08:14 PM PDT 24
Finished	Aug 11 07:08:25 PM PDT 24
Peak memory	225932 kb
Host	smart-e10f2bd5-54fe-480b-a71b-fece1cc9c912
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281897919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3281897919
Directory	/workspace/46.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/46.lc_ctrl_smoke.4153173004
Short name	T246
Test name
Test status
Simulation time	13689672 ps
CPU time	1.22 seconds
Started	Aug 11 07:08:14 PM PDT 24
Finished	Aug 11 07:08:15 PM PDT 24
Peak memory	221756 kb
Host	smart-491ab171-0652-4871-866b-49cfa7452c3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153173004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4153173004
Directory	/workspace/46.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_failure.936594545
Short name	T659
Test name
Test status
Simulation time	377593248 ps
CPU time	23.41 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:36 PM PDT 24
Peak memory	250752 kb
Host	smart-9e8fdcb5-cd28-4444-86bd-fe0eb59f90fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936594545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.936594545
Directory	/workspace/46.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_post_trans.1566449771
Short name	T813
Test name
Test status
Simulation time	337786254 ps
CPU time	9.19 seconds
Started	Aug 11 07:08:17 PM PDT 24
Finished	Aug 11 07:08:27 PM PDT 24
Peak memory	250804 kb
Host	smart-1ff10e35-5ec9-4bcc-8cc6-c85f666f4e3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566449771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1566449771
Directory	/workspace/46.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/46.lc_ctrl_stress_all.551502680
Short name	T582
Test name
Test status
Simulation time	2056306930 ps
CPU time	60.67 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:09:13 PM PDT 24
Peak memory	250856 kb
Host	smart-d3d458bc-2eb2-4f25-ad4b-075cb60776fa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551502680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.551502680
Directory	/workspace/46.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3362053651
Short name	T653
Test name
Test status
Simulation time	11275719 ps
CPU time	0.9 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:13 PM PDT 24
Peak memory	211652 kb
Host	smart-4f7d2d74-d86c-42f8-b1dd-56eaeb373e1e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362053651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c trl_volatile_unlock_smoke.3362053651
Directory	/workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_alert_test.4049202746
Short name	T688
Test name
Test status
Simulation time	19091815 ps
CPU time	0.93 seconds
Started	Aug 11 07:08:18 PM PDT 24
Finished	Aug 11 07:08:19 PM PDT 24
Peak memory	208792 kb
Host	smart-d1da2f8c-dd27-41ae-a9ff-8a7004ed44c1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049202746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.4049202746
Directory	/workspace/47.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.lc_ctrl_errors.3095463737
Short name	T346
Test name
Test status
Simulation time	288809583 ps
CPU time	11.92 seconds
Started	Aug 11 07:08:17 PM PDT 24
Finished	Aug 11 07:08:29 PM PDT 24
Peak memory	218092 kb
Host	smart-60b61d32-a23f-44de-9ec3-1f4a74734c1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095463737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3095463737
Directory	/workspace/47.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/47.lc_ctrl_jtag_access.3102001397
Short name	T31
Test name
Test status
Simulation time	477224642 ps
CPU time	6.51 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:18 PM PDT 24
Peak memory	217092 kb
Host	smart-3a8475a1-cc03-4c97-91c3-8080baecdc1b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102001397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3102001397
Directory	/workspace/47.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/47.lc_ctrl_prog_failure.594996836
Short name	T757
Test name
Test status
Simulation time	109279669 ps
CPU time	3.16 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:15 PM PDT 24
Peak memory	222372 kb
Host	smart-b3a6c6d6-e794-40af-8b8f-f8d4e6d4c0fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594996836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.594996836
Directory	/workspace/47.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_mubi.882123030
Short name	T465
Test name
Test status
Simulation time	4769731285 ps
CPU time	13.29 seconds
Started	Aug 11 07:08:18 PM PDT 24
Finished	Aug 11 07:08:31 PM PDT 24
Peak memory	226176 kb
Host	smart-7d9f8edf-653d-47ba-9fc9-df691db0d009
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882123030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.882123030
Directory	/workspace/47.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_digest.1890733687
Short name	T826
Test name
Test status
Simulation time	941251762 ps
CPU time	11.08 seconds
Started	Aug 11 07:08:16 PM PDT 24
Finished	Aug 11 07:08:27 PM PDT 24
Peak memory	218036 kb
Host	smart-4841de0c-3e3a-4483-956e-3e6b0890c439
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890733687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d igest.1890733687
Directory	/workspace/47.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_mux.848103593
Short name	T532
Test name
Test status
Simulation time	1681765050 ps
CPU time	13.46 seconds
Started	Aug 11 07:08:14 PM PDT 24
Finished	Aug 11 07:08:27 PM PDT 24
Peak memory	218068 kb
Host	smart-f9c6d070-3b77-45d4-92d9-98c5cbaacceb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848103593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.848103593
Directory	/workspace/47.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/47.lc_ctrl_security_escalation.3569799947
Short name	T14
Test name
Test status
Simulation time	482342317 ps
CPU time	7.52 seconds
Started	Aug 11 07:08:11 PM PDT 24
Finished	Aug 11 07:08:19 PM PDT 24
Peak memory	224876 kb
Host	smart-c026494f-6483-4563-a9ea-2dd34477cae1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569799947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3569799947
Directory	/workspace/47.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/47.lc_ctrl_smoke.3418792992
Short name	T529
Test name
Test status
Simulation time	19120361 ps
CPU time	1.64 seconds
Started	Aug 11 07:08:17 PM PDT 24
Finished	Aug 11 07:08:19 PM PDT 24
Peak memory	213624 kb
Host	smart-951070ac-0ee0-4b60-aef6-1306fdbc32e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418792992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3418792992
Directory	/workspace/47.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_failure.2403183720
Short name	T441
Test name
Test status
Simulation time	519367623 ps
CPU time	26.35 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:38 PM PDT 24
Peak memory	250816 kb
Host	smart-d1fbda5c-6c58-4fe8-a13b-4a36c06f4719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403183720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2403183720
Directory	/workspace/47.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_post_trans.28309703
Short name	T598
Test name
Test status
Simulation time	432194957 ps
CPU time	4.25 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	222600 kb
Host	smart-c6b3eb07-2a5e-42ab-afd5-2ae772089ac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28309703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.28309703
Directory	/workspace/47.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/47.lc_ctrl_stress_all.3722397219
Short name	T58
Test name
Test status
Simulation time	76982726664 ps
CPU time	361.71 seconds
Started	Aug 11 07:08:14 PM PDT 24
Finished	Aug 11 07:14:16 PM PDT 24
Peak memory	250808 kb
Host	smart-83975bf4-97d4-47e8-a99b-ee6b2a8f570e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722397219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.3722397219
Directory	/workspace/47.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3680832678
Short name	T331
Test name
Test status
Simulation time	24180260 ps
CPU time	1.07 seconds
Started	Aug 11 07:08:15 PM PDT 24
Finished	Aug 11 07:08:16 PM PDT 24
Peak memory	211656 kb
Host	smart-6ea1204a-2939-4b4d-be67-f0dbb6096365
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680832678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c trl_volatile_unlock_smoke.3680832678
Directory	/workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_alert_test.3019877132
Short name	T579
Test name
Test status
Simulation time	36049677 ps
CPU time	1 seconds
Started	Aug 11 07:08:25 PM PDT 24
Finished	Aug 11 07:08:26 PM PDT 24
Peak memory	208764 kb
Host	smart-4185fc9c-729e-4d75-b1a5-afa3530289be
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019877132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3019877132
Directory	/workspace/48.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.lc_ctrl_errors.3700974433
Short name	T398
Test name
Test status
Simulation time	5004432446 ps
CPU time	12.86 seconds
Started	Aug 11 07:08:17 PM PDT 24
Finished	Aug 11 07:08:30 PM PDT 24
Peak memory	218324 kb
Host	smart-ac0aa3e9-6e7e-4e50-a82c-c98a29897e7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700974433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3700974433
Directory	/workspace/48.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/48.lc_ctrl_jtag_access.1376039908
Short name	T28
Test name
Test status
Simulation time	519709438 ps
CPU time	3.3 seconds
Started	Aug 11 07:08:16 PM PDT 24
Finished	Aug 11 07:08:19 PM PDT 24
Peak memory	216960 kb
Host	smart-f00ca9f1-3a5d-40fc-b8d3-36d6af864211
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376039908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1376039908
Directory	/workspace/48.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/48.lc_ctrl_prog_failure.3483702052
Short name	T880
Test name
Test status
Simulation time	240253766 ps
CPU time	3.11 seconds
Started	Aug 11 07:08:14 PM PDT 24
Finished	Aug 11 07:08:17 PM PDT 24
Peak memory	218008 kb
Host	smart-99090645-8460-4252-81d1-16615b2458ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483702052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3483702052
Directory	/workspace/48.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_mubi.2687543599
Short name	T487
Test name
Test status
Simulation time	2009056949 ps
CPU time	12.14 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:24 PM PDT 24
Peak memory	225840 kb
Host	smart-cd7029be-c47e-4203-b7be-6888a2422d08
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687543599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2687543599
Directory	/workspace/48.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_digest.3916609011
Short name	T481
Test name
Test status
Simulation time	1236940346 ps
CPU time	12.89 seconds
Started	Aug 11 07:08:26 PM PDT 24
Finished	Aug 11 07:08:39 PM PDT 24
Peak memory	225824 kb
Host	smart-6ca87e55-46fc-478f-aa58-8d3cf1d9b5b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916609011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d igest.3916609011
Directory	/workspace/48.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_mux.2546702149
Short name	T265
Test name
Test status
Simulation time	4931762696 ps
CPU time	11.69 seconds
Started	Aug 11 07:08:24 PM PDT 24
Finished	Aug 11 07:08:35 PM PDT 24
Peak memory	218184 kb
Host	smart-6ec16190-f855-458b-96cc-f5723994e398
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546702149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux. 2546702149
Directory	/workspace/48.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/48.lc_ctrl_security_escalation.3730743703
Short name	T430
Test name
Test status
Simulation time	2199105214 ps
CPU time	10.41 seconds
Started	Aug 11 07:08:13 PM PDT 24
Finished	Aug 11 07:08:23 PM PDT 24
Peak memory	224812 kb
Host	smart-d8dcf77a-7a0c-41c3-8e95-588ea2d883b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730743703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3730743703
Directory	/workspace/48.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/48.lc_ctrl_smoke.2868917409
Short name	T367
Test name
Test status
Simulation time	198431668 ps
CPU time	2.9 seconds
Started	Aug 11 07:08:12 PM PDT 24
Finished	Aug 11 07:08:15 PM PDT 24
Peak memory	217592 kb
Host	smart-b0c4e4b3-bc7d-487e-a352-9951abbe4bb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868917409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2868917409
Directory	/workspace/48.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_failure.3464838891
Short name	T332
Test name
Test status
Simulation time	1113650519 ps
CPU time	17.63 seconds
Started	Aug 11 07:08:15 PM PDT 24
Finished	Aug 11 07:08:32 PM PDT 24
Peak memory	250824 kb
Host	smart-46c888b8-2aa0-4e4b-b8e0-1df349226ff0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3464838891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3464838891
Directory	/workspace/48.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_post_trans.805410884
Short name	T294
Test name
Test status
Simulation time	68831756 ps
CPU time	6.52 seconds
Started	Aug 11 07:08:14 PM PDT 24
Finished	Aug 11 07:08:20 PM PDT 24
Peak memory	245852 kb
Host	smart-40bc5ee4-fd5e-46ea-a435-59a43e65d8c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805410884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.805410884
Directory	/workspace/48.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all.1883971447
Short name	T281
Test name
Test status
Simulation time	9221852046 ps
CPU time	203.1 seconds
Started	Aug 11 07:08:24 PM PDT 24
Finished	Aug 11 07:11:47 PM PDT 24
Peak memory	226060 kb
Host	smart-34488477-1257-40a2-8b35-afc097b17dda
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883971447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all.1883971447
Directory	/workspace/48.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.lc_ctrl_alert_test.2956562903
Short name	T640
Test name
Test status
Simulation time	39269337 ps
CPU time	1.02 seconds
Started	Aug 11 07:08:25 PM PDT 24
Finished	Aug 11 07:08:26 PM PDT 24
Peak memory	208764 kb
Host	smart-a307dfd8-4904-47b4-a66f-a62d67bf837f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956562903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2956562903
Directory	/workspace/49.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.lc_ctrl_errors.172344627
Short name	T259
Test name
Test status
Simulation time	522154022 ps
CPU time	7.87 seconds
Started	Aug 11 07:08:27 PM PDT 24
Finished	Aug 11 07:08:35 PM PDT 24
Peak memory	225864 kb
Host	smart-df157fa2-3197-4205-b174-9a040fd83f1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172344627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.172344627
Directory	/workspace/49.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/49.lc_ctrl_jtag_access.3150132983
Short name	T673
Test name
Test status
Simulation time	2485281903 ps
CPU time	3.6 seconds
Started	Aug 11 07:08:27 PM PDT 24
Finished	Aug 11 07:08:31 PM PDT 24
Peak memory	217492 kb
Host	smart-632cc7f0-f0c6-4342-aae5-01ec624ab0c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150132983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3150132983
Directory	/workspace/49.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/49.lc_ctrl_prog_failure.2538319706
Short name	T10
Test name
Test status
Simulation time	76266136 ps
CPU time	2.95 seconds
Started	Aug 11 07:08:25 PM PDT 24
Finished	Aug 11 07:08:29 PM PDT 24
Peak memory	222100 kb
Host	smart-017f957d-3eb7-4843-a0d2-d3942e0c74bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538319706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2538319706
Directory	/workspace/49.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_mubi.4090283875
Short name	T451
Test name
Test status
Simulation time	1516455281 ps
CPU time	13.53 seconds
Started	Aug 11 07:08:29 PM PDT 24
Finished	Aug 11 07:08:43 PM PDT 24
Peak memory	225904 kb
Host	smart-938631bf-f0b1-48f0-a508-b7d8a46e81c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090283875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4090283875
Directory	/workspace/49.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_digest.1970042716
Short name	T267
Test name
Test status
Simulation time	1667333324 ps
CPU time	15.32 seconds
Started	Aug 11 07:08:24 PM PDT 24
Finished	Aug 11 07:08:39 PM PDT 24
Peak memory	218024 kb
Host	smart-da4f3932-d4c7-4e7d-9d14-98dc914306d5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970042716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d igest.1970042716
Directory	/workspace/49.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_mux.3579262078
Short name	T834
Test name
Test status
Simulation time	1156549047 ps
CPU time	10.94 seconds
Started	Aug 11 07:08:25 PM PDT 24
Finished	Aug 11 07:08:36 PM PDT 24
Peak memory	218028 kb
Host	smart-ce22e007-f138-4f40-a22b-b971abb9fdb3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579262078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux. 3579262078
Directory	/workspace/49.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/49.lc_ctrl_security_escalation.3373313508
Short name	T541
Test name
Test status
Simulation time	1460311824 ps
CPU time	15.13 seconds
Started	Aug 11 07:08:27 PM PDT 24
Finished	Aug 11 07:08:42 PM PDT 24
Peak memory	225240 kb
Host	smart-09d9de73-a87d-45b2-abc1-f2aa369cfe5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373313508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3373313508
Directory	/workspace/49.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/49.lc_ctrl_smoke.1348058667
Short name	T717
Test name
Test status
Simulation time	160018541 ps
CPU time	3.45 seconds
Started	Aug 11 07:08:25 PM PDT 24
Finished	Aug 11 07:08:29 PM PDT 24
Peak memory	217520 kb
Host	smart-f654f6c9-76cf-4d9c-823c-39ee2e94c274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348058667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1348058667
Directory	/workspace/49.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_failure.4280991741
Short name	T562
Test name
Test status
Simulation time	1251222398 ps
CPU time	25.58 seconds
Started	Aug 11 07:08:25 PM PDT 24
Finished	Aug 11 07:08:51 PM PDT 24
Peak memory	250532 kb
Host	smart-7a020dc6-a710-4aff-b98e-e302b897764a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280991741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.4280991741
Directory	/workspace/49.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_post_trans.234771707
Short name	T512
Test name
Test status
Simulation time	105896926 ps
CPU time	7.2 seconds
Started	Aug 11 07:08:27 PM PDT 24
Finished	Aug 11 07:08:34 PM PDT 24
Peak memory	250680 kb
Host	smart-881075e8-6fd3-404d-bce8-523411f05c07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234771707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.234771707
Directory	/workspace/49.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all.572746952
Short name	T831
Test name
Test status
Simulation time	911243685 ps
CPU time	6.66 seconds
Started	Aug 11 07:08:26 PM PDT 24
Finished	Aug 11 07:08:33 PM PDT 24
Peak memory	216036 kb
Host	smart-04ea5647-2cd0-4171-a674-e4367345aa98
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572746952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.572746952
Directory	/workspace/49.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3131220036
Short name	T399
Test name
Test status
Simulation time	10856049 ps
CPU time	1 seconds
Started	Aug 11 07:08:24 PM PDT 24
Finished	Aug 11 07:08:26 PM PDT 24
Peak memory	211748 kb
Host	smart-bdde6fc7-b156-4a2c-bdd9-3c5c9571b5a5
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131220036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c trl_volatile_unlock_smoke.3131220036
Directory	/workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_alert_test.1460536158
Short name	T712
Test name
Test status
Simulation time	51579779 ps
CPU time	1.08 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:05:38 PM PDT 24
Peak memory	208876 kb
Host	smart-36e3c0b2-12d9-4048-a5bf-09339334d098
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460536158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1460536158
Directory	/workspace/5.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.lc_ctrl_claim_transition_if.2041569260
Short name	T223
Test name
Test status
Simulation time	18132397 ps
CPU time	0.91 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:32 PM PDT 24
Peak memory	208616 kb
Host	smart-d050ac60-8712-482f-b579-8076cfb96f39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041569260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2041569260
Directory	/workspace/5.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/5.lc_ctrl_errors.3342777216
Short name	T583
Test name
Test status
Simulation time	356121197 ps
CPU time	14.15 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:46 PM PDT 24
Peak memory	218100 kb
Host	smart-ca13a546-4017-4d09-98ba-38b828b13759
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342777216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3342777216
Directory	/workspace/5.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_access.2109336784
Short name	T195
Test name
Test status
Simulation time	2321437848 ps
CPU time	25.3 seconds
Started	Aug 11 07:05:36 PM PDT 24
Finished	Aug 11 07:06:01 PM PDT 24
Peak memory	217248 kb
Host	smart-b1cf8acd-f76d-4630-bbd6-9e9c3561cf54
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109336784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2109336784
Directory	/workspace/5.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_errors.3462901500
Short name	T812
Test name
Test status
Simulation time	4337110549 ps
CPU time	61.35 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:06:33 PM PDT 24
Peak memory	218768 kb
Host	smart-5bc4e650-eac9-4f9d-9f30-731417c5be19
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462901500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er rors.3462901500
Directory	/workspace/5.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_priority.2865792852
Short name	T647
Test name
Test status
Simulation time	579333577 ps
CPU time	3.75 seconds
Started	Aug 11 07:05:36 PM PDT 24
Finished	Aug 11 07:05:40 PM PDT 24
Peak memory	217332 kb
Host	smart-31a3aefe-7e1c-45c8-a6b5-24a841f63ebf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865792852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2 865792852
Directory	/workspace/5.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3058116677
Short name	T747
Test name
Test status
Simulation time	3472679802 ps
CPU time	10.78 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:05:41 PM PDT 24
Peak memory	218192 kb
Host	smart-4da757f2-c438-4061-b7e8-f6ca2ff1845c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058116677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag _prog_failure.3058116677
Directory	/workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1733127558
Short name	T443
Test name
Test status
Simulation time	1176327295 ps
CPU time	14.69 seconds
Started	Aug 11 07:05:33 PM PDT 24
Finished	Aug 11 07:05:47 PM PDT 24
Peak memory	217476 kb
Host	smart-0fe7bceb-e86a-46e5-b404-7675dba54b95
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733127558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_regwen_during_op.1733127558
Directory	/workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_smoke.3788601439
Short name	T338
Test name
Test status
Simulation time	478962440 ps
CPU time	12.34 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:05:43 PM PDT 24
Peak memory	217488 kb
Host	smart-af4663e5-dea2-48aa-9669-7d81d3f5bf92
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788601439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke. 3788601439
Directory	/workspace/5.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2466712391
Short name	T264
Test name
Test status
Simulation time	2092493305 ps
CPU time	82.97 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:06:55 PM PDT 24
Peak memory	279980 kb
Host	smart-79f27b34-cc22-4a26-8a80-f9d6571ff3ca
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466712391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta g_state_failure.2466712391
Directory	/workspace/5.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3642126881
Short name	T642
Test name
Test status
Simulation time	1398447025 ps
CPU time	11.44 seconds
Started	Aug 11 07:05:33 PM PDT 24
Finished	Aug 11 07:05:44 PM PDT 24
Peak memory	250732 kb
Host	smart-1161051f-9d5d-477b-9728-bbb503fb626f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642126881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_state_post_trans.3642126881
Directory	/workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_prog_failure.244023315
Short name	T704
Test name
Test status
Simulation time	61787428 ps
CPU time	2.5 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:05:32 PM PDT 24
Peak memory	222208 kb
Host	smart-558a8f83-62c1-4f0b-af1f-8b6840a942d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244023315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.244023315
Directory	/workspace/5.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_mubi.3345877233
Short name	T671
Test name
Test status
Simulation time	220240182 ps
CPU time	10 seconds
Started	Aug 11 07:05:32 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	218060 kb
Host	smart-92cbfe15-f263-41dc-aa76-a45dd9054986
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345877233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3345877233
Directory	/workspace/5.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_digest.659851701
Short name	T250
Test name
Test status
Simulation time	381875993 ps
CPU time	15.96 seconds
Started	Aug 11 07:05:34 PM PDT 24
Finished	Aug 11 07:05:50 PM PDT 24
Peak memory	218040 kb
Host	smart-eddae88a-4a84-4956-878a-6b486a6ffcd8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659851701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig est.659851701
Directory	/workspace/5.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_mux.1237150870
Short name	T755
Test name
Test status
Simulation time	236377897 ps
CPU time	9.09 seconds
Started	Aug 11 07:05:32 PM PDT 24
Finished	Aug 11 07:05:41 PM PDT 24
Peak memory	225164 kb
Host	smart-0d6d1156-6046-43b7-8c5f-36c991692aa9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237150870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1 237150870
Directory	/workspace/5.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/5.lc_ctrl_security_escalation.3383671308
Short name	T355
Test name
Test status
Simulation time	447920075 ps
CPU time	10.88 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	218236 kb
Host	smart-a848d6e8-17e0-4fc2-a962-c9441578de45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383671308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3383671308
Directory	/workspace/5.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/5.lc_ctrl_smoke.2524185074
Short name	T176
Test name
Test status
Simulation time	54142935 ps
CPU time	2.51 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:34 PM PDT 24
Peak memory	217592 kb
Host	smart-226261e7-61ea-40a7-a437-d2db426725f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524185074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2524185074
Directory	/workspace/5.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_failure.3019674374
Short name	T594
Test name
Test status
Simulation time	281408394 ps
CPU time	36.18 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:06:07 PM PDT 24
Peak memory	250872 kb
Host	smart-6822f550-0233-4148-9ca7-e023330c2d6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3019674374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3019674374
Directory	/workspace/5.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_post_trans.2781747078
Short name	T440
Test name
Test status
Simulation time	500407250 ps
CPU time	6.87 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:05:37 PM PDT 24
Peak memory	250640 kb
Host	smart-cae81569-8e3f-4ebc-b567-428b11c28a69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781747078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2781747078
Directory	/workspace/5.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all.334715964
Short name	T356
Test name
Test status
Simulation time	2145221008 ps
CPU time	87.66 seconds
Started	Aug 11 07:05:30 PM PDT 24
Finished	Aug 11 07:06:58 PM PDT 24
Peak memory	267952 kb
Host	smart-9b7f0b41-e058-461f-a09a-ed1b7c0dbbe1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334715964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.334715964
Directory	/workspace/5.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2569386073
Short name	T460
Test name
Test status
Simulation time	26473553 ps
CPU time	0.87 seconds
Started	Aug 11 07:05:31 PM PDT 24
Finished	Aug 11 07:05:32 PM PDT 24
Peak memory	211648 kb
Host	smart-afe3485e-283e-40cb-96b7-f89b73fa9ddc
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569386073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct rl_volatile_unlock_smoke.2569386073
Directory	/workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_alert_test.2279290937
Short name	T94
Test name
Test status
Simulation time	74730496 ps
CPU time	0.87 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:05:38 PM PDT 24
Peak memory	208696 kb
Host	smart-783cf41b-9b5d-4ebd-94b7-c6ebd94f51da
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279290937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2279290937
Directory	/workspace/6.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.lc_ctrl_claim_transition_if.2349663123
Short name	T227
Test name
Test status
Simulation time	28583195 ps
CPU time	0.79 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:39 PM PDT 24
Peak memory	208864 kb
Host	smart-97294786-c13d-464e-9b85-f4cf072366a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349663123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2349663123
Directory	/workspace/6.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_access.3395176007
Short name	T860
Test name
Test status
Simulation time	612741507 ps
CPU time	1.23 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:40 PM PDT 24
Peak memory	216880 kb
Host	smart-7ea7d663-6ecf-40a6-8701-2e40fa5e8632
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395176007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3395176007
Directory	/workspace/6.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_priority.3105052013
Short name	T361
Test name
Test status
Simulation time	143550871 ps
CPU time	2.71 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:05:40 PM PDT 24
Peak memory	217368 kb
Host	smart-273e7e87-8b7b-4223-9afa-91c9aebbd2db
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105052013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3 105052013
Directory	/workspace/6.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.883107412
Short name	T304
Test name
Test status
Simulation time	1096987280 ps
CPU time	5.85 seconds
Started	Aug 11 07:05:36 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	218004 kb
Host	smart-cc3aa87b-db76-47cc-ac02-a112529cacea
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883107412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ prog_failure.883107412
Directory	/workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.998213499
Short name	T740
Test name
Test status
Simulation time	1851679713 ps
CPU time	15.73 seconds
Started	Aug 11 07:05:36 PM PDT 24
Finished	Aug 11 07:05:52 PM PDT 24
Peak memory	217436 kb
Host	smart-0353720c-a600-433e-91ea-f4a46e9c8870
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998213499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j tag_regwen_during_op.998213499
Directory	/workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_smoke.3211704692
Short name	T89
Test name
Test status
Simulation time	525890707 ps
CPU time	4.64 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:05:41 PM PDT 24
Peak memory	217388 kb
Host	smart-3c712cf2-2ee2-4fdc-a80c-805c8c827a3b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211704692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke. 3211704692
Directory	/workspace/6.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2281742537
Short name	T459
Test name
Test status
Simulation time	6583877195 ps
CPU time	65.42 seconds
Started	Aug 11 07:05:42 PM PDT 24
Finished	Aug 11 07:06:47 PM PDT 24
Peak memory	283564 kb
Host	smart-f2bd1e1b-a7f9-44a4-848e-b7527ff4c1fe
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281742537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta g_state_failure.2281742537
Directory	/workspace/6.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1470956660
Short name	T763
Test name
Test status
Simulation time	1905741347 ps
CPU time	18.41 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:05:56 PM PDT 24
Peak memory	250192 kb
Host	smart-6d28a8f9-59bd-4c15-aec5-4be4b4477c0e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470956660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_state_post_trans.1470956660
Directory	/workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_prog_failure.2384041324
Short name	T243
Test name
Test status
Simulation time	99188290 ps
CPU time	4.34 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:43 PM PDT 24
Peak memory	218100 kb
Host	smart-fbbf1eb4-3d7f-4c1c-aba0-8635f54769d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384041324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2384041324
Directory	/workspace/6.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_regwen_during_op.1740050467
Short name	T820
Test name
Test status
Simulation time	390491946 ps
CPU time	27.11 seconds
Started	Aug 11 07:05:43 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	214640 kb
Host	smart-02546f7a-bb09-4a76-b3ed-41bf807fdb42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740050467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1740050467
Directory	/workspace/6.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_mubi.3600449882
Short name	T694
Test name
Test status
Simulation time	554352948 ps
CPU time	14.34 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:53 PM PDT 24
Peak memory	225920 kb
Host	smart-3be5ec55-e9f4-4d07-bc2d-6332cb1c0dd7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600449882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3600449882
Directory	/workspace/6.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_digest.3022937285
Short name	T632
Test name
Test status
Simulation time	1750325710 ps
CPU time	14.98 seconds
Started	Aug 11 07:05:38 PM PDT 24
Finished	Aug 11 07:05:53 PM PDT 24
Peak memory	218040 kb
Host	smart-1c6d5416-0810-4476-8c42-d382c3acc1dc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022937285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di gest.3022937285
Directory	/workspace/6.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_mux.697332264
Short name	T627
Test name
Test status
Simulation time	393732476 ps
CPU time	13.45 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:52 PM PDT 24
Peak memory	218084 kb
Host	smart-1c5a56fc-efb6-4b98-a2e5-728cf21cdb26
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697332264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.697332264
Directory	/workspace/6.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/6.lc_ctrl_security_escalation.1466487089
Short name	T565
Test name
Test status
Simulation time	1524948177 ps
CPU time	11.44 seconds
Started	Aug 11 07:05:38 PM PDT 24
Finished	Aug 11 07:05:50 PM PDT 24
Peak memory	225920 kb
Host	smart-986fa8ec-b411-4733-bd06-ea6dd201c9e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466487089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1466487089
Directory	/workspace/6.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/6.lc_ctrl_smoke.2561162977
Short name	T544
Test name
Test status
Simulation time	757803417 ps
CPU time	2.6 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:05:40 PM PDT 24
Peak memory	223808 kb
Host	smart-6f8350f9-0587-4446-886e-1591e409c00e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561162977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2561162977
Directory	/workspace/6.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_failure.1784766456
Short name	T236
Test name
Test status
Simulation time	887760251 ps
CPU time	25.36 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:06:02 PM PDT 24
Peak memory	250956 kb
Host	smart-60b51cef-5e25-4cc8-a0be-5a6d2e7502ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784766456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1784766456
Directory	/workspace/6.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all.514995290
Short name	T107
Test name
Test status
Simulation time	18160213825 ps
CPU time	681.94 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:17:01 PM PDT 24
Peak memory	283692 kb
Host	smart-f1c1bb77-1668-4d99-a201-e2ed1a30bd93
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514995290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.514995290
Directory	/workspace/6.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.30024802
Short name	T263
Test name
Test status
Simulation time	12298023 ps
CPU time	1.03 seconds
Started	Aug 11 07:05:36 PM PDT 24
Finished	Aug 11 07:05:37 PM PDT 24
Peak memory	211640 kb
Host	smart-7f5622fa-6026-4f8c-82dc-f1c8e425be73
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30024802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _volatile_unlock_smoke.30024802
Directory	/workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_alert_test.1666985680
Short name	T78
Test name
Test status
Simulation time	47119483 ps
CPU time	1.05 seconds
Started	Aug 11 07:05:43 PM PDT 24
Finished	Aug 11 07:05:45 PM PDT 24
Peak memory	208700 kb
Host	smart-99eb6c98-67fd-42f6-b5b1-c1824e546777
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666985680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1666985680
Directory	/workspace/7.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.lc_ctrl_errors.520613852
Short name	T770
Test name
Test status
Simulation time	2704785010 ps
CPU time	11.11 seconds
Started	Aug 11 07:05:38 PM PDT 24
Finished	Aug 11 07:05:49 PM PDT 24
Peak memory	218880 kb
Host	smart-c26c04ec-0bd1-4d2a-95fc-46effee8e08b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520613852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.520613852
Directory	/workspace/7.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_access.742605509
Short name	T706
Test name
Test status
Simulation time	1802987773 ps
CPU time	5.89 seconds
Started	Aug 11 07:05:40 PM PDT 24
Finished	Aug 11 07:05:46 PM PDT 24
Peak memory	217332 kb
Host	smart-9ffa3a1f-2f8c-4a42-91d6-488426493533
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742605509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.742605509
Directory	/workspace/7.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_errors.3686941086
Short name	T527
Test name
Test status
Simulation time	2845754982 ps
CPU time	75.15 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:06:55 PM PDT 24
Peak memory	225952 kb
Host	smart-3afca8b6-0a61-4eae-84d0-6db8fb73a794
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686941086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er rors.3686941086
Directory	/workspace/7.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_priority.2390067376
Short name	T299
Test name
Test status
Simulation time	170330966 ps
CPU time	2.82 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	217616 kb
Host	smart-d4f0fd0c-4d99-45ab-8567-18aa28fb9484
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390067376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2 390067376
Directory	/workspace/7.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.382669660
Short name	T287
Test name
Test status
Simulation time	346539545 ps
CPU time	6.02 seconds
Started	Aug 11 07:05:40 PM PDT 24
Finished	Aug 11 07:05:46 PM PDT 24
Peak memory	222764 kb
Host	smart-2f484ce3-171a-4ec8-aef1-f7048941af23
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382669660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ prog_failure.382669660
Directory	/workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.17510625
Short name	T84
Test name
Test status
Simulation time	5651291276 ps
CPU time	11.12 seconds
Started	Aug 11 07:05:43 PM PDT 24
Finished	Aug 11 07:05:55 PM PDT 24
Peak memory	217516 kb
Host	smart-e24c4e68-b522-4e9e-a3ad-5e3c7505d35c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17510625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt ag_regwen_during_op.17510625
Directory	/workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_smoke.1507649235
Short name	T77
Test name
Test status
Simulation time	624338000 ps
CPU time	3.18 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	217504 kb
Host	smart-cf5d0013-5588-4f1f-bacf-97230f581b66
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507649235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke. 1507649235
Directory	/workspace/7.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3862469613
Short name	T341
Test name
Test status
Simulation time	1801103411 ps
CPU time	53.42 seconds
Started	Aug 11 07:05:41 PM PDT 24
Finished	Aug 11 07:06:35 PM PDT 24
Peak memory	267068 kb
Host	smart-10872564-1c52-488d-b569-4c5e81f29291
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862469613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta g_state_failure.3862469613
Directory	/workspace/7.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1275549093
Short name	T445
Test name
Test status
Simulation time	3036873035 ps
CPU time	14.82 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:54 PM PDT 24
Peak memory	223544 kb
Host	smart-a7ff7603-e0e5-4f4f-8b8b-29485ef1a539
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275549093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_state_post_trans.1275549093
Directory	/workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_prog_failure.2600461272
Short name	T394
Test name
Test status
Simulation time	54360195 ps
CPU time	3.32 seconds
Started	Aug 11 07:05:39 PM PDT 24
Finished	Aug 11 07:05:42 PM PDT 24
Peak memory	218120 kb
Host	smart-431a0677-cc59-4723-9570-d3d352e96d12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600461272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2600461272
Directory	/workspace/7.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_regwen_during_op.2056631281
Short name	T593
Test name
Test status
Simulation time	915343157 ps
CPU time	14.01 seconds
Started	Aug 11 07:05:36 PM PDT 24
Finished	Aug 11 07:05:51 PM PDT 24
Peak memory	217448 kb
Host	smart-39ad7701-3faa-4ade-a282-7ff69eae9eba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056631281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2056631281
Directory	/workspace/7.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_mubi.3959310367
Short name	T550
Test name
Test status
Simulation time	1618978435 ps
CPU time	12.65 seconds
Started	Aug 11 07:05:45 PM PDT 24
Finished	Aug 11 07:05:58 PM PDT 24
Peak memory	225972 kb
Host	smart-79015423-1b53-4d42-8acd-4fed093d1a91
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959310367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3959310367
Directory	/workspace/7.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_digest.3753941113
Short name	T678
Test name
Test status
Simulation time	2634607881 ps
CPU time	12.33 seconds
Started	Aug 11 07:05:43 PM PDT 24
Finished	Aug 11 07:05:56 PM PDT 24
Peak memory	218832 kb
Host	smart-8713d89a-4098-42e7-9cbb-46f890011c69
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753941113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di gest.3753941113
Directory	/workspace/7.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_mux.3466476905
Short name	T759
Test name
Test status
Simulation time	295545476 ps
CPU time	8.68 seconds
Started	Aug 11 07:05:43 PM PDT 24
Finished	Aug 11 07:05:52 PM PDT 24
Peak memory	218020 kb
Host	smart-b3f39724-fecd-413d-8cc3-837fc8fe1758
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466476905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3 466476905
Directory	/workspace/7.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/7.lc_ctrl_security_escalation.2210040782
Short name	T725
Test name
Test status
Simulation time	245168315 ps
CPU time	10.05 seconds
Started	Aug 11 07:05:42 PM PDT 24
Finished	Aug 11 07:05:52 PM PDT 24
Peak memory	225868 kb
Host	smart-1e7ed103-db0f-43bf-8913-4729e60e5b02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210040782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2210040782
Directory	/workspace/7.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/7.lc_ctrl_smoke.1738959657
Short name	T319
Test name
Test status
Simulation time	103747904 ps
CPU time	2.02 seconds
Started	Aug 11 07:05:38 PM PDT 24
Finished	Aug 11 07:05:40 PM PDT 24
Peak memory	214032 kb
Host	smart-203264d2-36b7-471e-85c4-4feaf22ddba1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738959657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1738959657
Directory	/workspace/7.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_failure.3531387820
Short name	T666
Test name
Test status
Simulation time	200566155 ps
CPU time	18.52 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:05:56 PM PDT 24
Peak memory	250940 kb
Host	smart-ffcf57fa-58b0-484d-bdad-b28a9f80bc92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531387820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3531387820
Directory	/workspace/7.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_post_trans.3502029523
Short name	T305
Test name
Test status
Simulation time	201291710 ps
CPU time	7.21 seconds
Started	Aug 11 07:05:38 PM PDT 24
Finished	Aug 11 07:05:45 PM PDT 24
Peak memory	250772 kb
Host	smart-d7ca6058-2297-463d-aa9d-f5b115f65f6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502029523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3502029523
Directory	/workspace/7.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all.2867595051
Short name	T403
Test name
Test status
Simulation time	27990666731 ps
CPU time	42.7 seconds
Started	Aug 11 07:05:44 PM PDT 24
Finished	Aug 11 07:06:27 PM PDT 24
Peak memory	250736 kb
Host	smart-a9365bdd-eb24-4e76-862b-97409dfb5ea8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867595051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.2867595051
Directory	/workspace/7.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2463942793
Short name	T44
Test name
Test status
Simulation time	22873576371 ps
CPU time	435.21 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:13:04 PM PDT 24
Peak memory	283956 kb
Host	smart-8297625d-7b02-4de6-8b68-2d82c26f736c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2463942793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2463942793
Directory	/workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3733866221
Short name	T729
Test name
Test status
Simulation time	11413231 ps
CPU time	1.02 seconds
Started	Aug 11 07:05:37 PM PDT 24
Finished	Aug 11 07:05:38 PM PDT 24
Peak memory	211572 kb
Host	smart-36877742-c606-43e7-ba97-3aa4dc548953
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733866221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_volatile_unlock_smoke.3733866221
Directory	/workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_alert_test.326988955
Short name	T865
Test name
Test status
Simulation time	52166930 ps
CPU time	0.88 seconds
Started	Aug 11 07:05:46 PM PDT 24
Finished	Aug 11 07:05:48 PM PDT 24
Peak memory	208624 kb
Host	smart-2ad81d12-1757-4eed-b88e-90e0d2aef4ad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326988955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.326988955
Directory	/workspace/8.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.lc_ctrl_claim_transition_if.4101953466
Short name	T272
Test name
Test status
Simulation time	11330735 ps
CPU time	0.78 seconds
Started	Aug 11 07:05:43 PM PDT 24
Finished	Aug 11 07:05:44 PM PDT 24
Peak memory	208880 kb
Host	smart-fc03129d-ec63-408d-b531-e9430691e193
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101953466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4101953466
Directory	/workspace/8.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/8.lc_ctrl_errors.419605921
Short name	T615
Test name
Test status
Simulation time	231526362 ps
CPU time	11.95 seconds
Started	Aug 11 07:05:47 PM PDT 24
Finished	Aug 11 07:05:59 PM PDT 24
Peak memory	218256 kb
Host	smart-7a51cfc9-8083-4ccb-b531-b01dba2cd1c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419605921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.419605921
Directory	/workspace/8.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_access.415584911
Short name	T6
Test name
Test status
Simulation time	417653132 ps
CPU time	2.27 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:05:51 PM PDT 24
Peak memory	216924 kb
Host	smart-3e1ef9bc-5d9e-46a5-b54b-c3b729705936
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415584911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.415584911
Directory	/workspace/8.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_errors.517554888
Short name	T296
Test name
Test status
Simulation time	976360818 ps
CPU time	18.34 seconds
Started	Aug 11 07:05:42 PM PDT 24
Finished	Aug 11 07:06:01 PM PDT 24
Peak memory	218040 kb
Host	smart-36c43625-ba47-415d-8fc7-a4ce8a250c4b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517554888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err ors.517554888
Directory	/workspace/8.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_priority.3403002252
Short name	T347
Test name
Test status
Simulation time	287171221 ps
CPU time	7.39 seconds
Started	Aug 11 07:05:48 PM PDT 24
Finished	Aug 11 07:05:56 PM PDT 24
Peak memory	217576 kb
Host	smart-21171db4-fd4f-472b-b08b-fc7e8f9b0b7c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403002252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3 403002252
Directory	/workspace/8.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3704739053
Short name	T587
Test name
Test status
Simulation time	993078748 ps
CPU time	8.15 seconds
Started	Aug 11 07:05:44 PM PDT 24
Finished	Aug 11 07:05:52 PM PDT 24
Peak memory	221640 kb
Host	smart-d88bd739-78c6-4333-bd78-2ae52e3cc273
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704739053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _prog_failure.3704739053
Directory	/workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1659959927
Short name	T268
Test name
Test status
Simulation time	1273875982 ps
CPU time	26.85 seconds
Started	Aug 11 07:05:45 PM PDT 24
Finished	Aug 11 07:06:12 PM PDT 24
Peak memory	217500 kb
Host	smart-cef92761-0320-4470-b95c-72cc9d682674
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659959927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_regwen_during_op.1659959927
Directory	/workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_smoke.2746942331
Short name	T878
Test name
Test status
Simulation time	71190802 ps
CPU time	2.99 seconds
Started	Aug 11 07:05:45 PM PDT 24
Finished	Aug 11 07:05:48 PM PDT 24
Peak memory	217488 kb
Host	smart-ee1dd841-de6f-40f1-9193-cf0cffd09745
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746942331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke. 2746942331
Directory	/workspace/8.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3801296986
Short name	T536
Test name
Test status
Simulation time	2764175560 ps
CPU time	36.48 seconds
Started	Aug 11 07:05:46 PM PDT 24
Finished	Aug 11 07:06:22 PM PDT 24
Peak memory	250788 kb
Host	smart-fe2ab47a-a217-497a-b296-37a282eee65a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801296986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta g_state_failure.3801296986
Directory	/workspace/8.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1845100042
Short name	T340
Test name
Test status
Simulation time	1007208442 ps
CPU time	19.76 seconds
Started	Aug 11 07:05:47 PM PDT 24
Finished	Aug 11 07:06:07 PM PDT 24
Peak memory	248932 kb
Host	smart-3bead098-969a-4ef8-ad92-b5c34448696f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845100042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_state_post_trans.1845100042
Directory	/workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_prog_failure.1477138227
Short name	T824
Test name
Test status
Simulation time	42990651 ps
CPU time	2.63 seconds
Started	Aug 11 07:05:47 PM PDT 24
Finished	Aug 11 07:05:49 PM PDT 24
Peak memory	218224 kb
Host	smart-10f02ebb-0e78-4988-a880-510f7497619f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1477138227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1477138227
Directory	/workspace/8.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_regwen_during_op.664549544
Short name	T79
Test name
Test status
Simulation time	179678328 ps
CPU time	4.34 seconds
Started	Aug 11 07:05:45 PM PDT 24
Finished	Aug 11 07:05:50 PM PDT 24
Peak memory	217588 kb
Host	smart-f14916d3-9f4e-42a7-817e-d9cc2a8487e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664549544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.664549544
Directory	/workspace/8.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_mubi.4105479477
Short name	T371
Test name
Test status
Simulation time	613013986 ps
CPU time	9.61 seconds
Started	Aug 11 07:05:44 PM PDT 24
Finished	Aug 11 07:05:54 PM PDT 24
Peak memory	225856 kb
Host	smart-e447037a-517b-47d3-9e16-134f1e79cedf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105479477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4105479477
Directory	/workspace/8.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_digest.1682136346
Short name	T571
Test name
Test status
Simulation time	250429432 ps
CPU time	9.64 seconds
Started	Aug 11 07:05:45 PM PDT 24
Finished	Aug 11 07:05:55 PM PDT 24
Peak memory	218008 kb
Host	smart-465c0b63-48f5-4b3b-99bb-b9cffed9c73b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682136346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di gest.1682136346
Directory	/workspace/8.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_mux.2791333187
Short name	T456
Test name
Test status
Simulation time	1790649313 ps
CPU time	11.5 seconds
Started	Aug 11 07:05:45 PM PDT 24
Finished	Aug 11 07:05:57 PM PDT 24
Peak memory	218036 kb
Host	smart-3fffb86b-af7f-4a2f-89c5-7f1d0a339ca4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791333187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2 791333187
Directory	/workspace/8.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/8.lc_ctrl_security_escalation.3821937359
Short name	T433
Test name
Test status
Simulation time	1310837578 ps
CPU time	11.69 seconds
Started	Aug 11 07:05:44 PM PDT 24
Finished	Aug 11 07:05:56 PM PDT 24
Peak memory	218152 kb
Host	smart-0acee491-c048-4f77-a981-509a29696cf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821937359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3821937359
Directory	/workspace/8.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/8.lc_ctrl_smoke.950548162
Short name	T705
Test name
Test status
Simulation time	21134574 ps
CPU time	1.7 seconds
Started	Aug 11 07:05:43 PM PDT 24
Finished	Aug 11 07:05:44 PM PDT 24
Peak memory	222968 kb
Host	smart-89106f5a-50e6-47e7-804e-005715cd34e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950548162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.950548162
Directory	/workspace/8.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_failure.1553473556
Short name	T833
Test name
Test status
Simulation time	210742750 ps
CPU time	29.11 seconds
Started	Aug 11 07:05:46 PM PDT 24
Finished	Aug 11 07:06:15 PM PDT 24
Peak memory	250876 kb
Host	smart-df358ba5-6fcb-4d46-8e4f-11c656cb9ba7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553473556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1553473556
Directory	/workspace/8.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_post_trans.2544550214
Short name	T798
Test name
Test status
Simulation time	52607429 ps
CPU time	7.58 seconds
Started	Aug 11 07:05:48 PM PDT 24
Finished	Aug 11 07:05:56 PM PDT 24
Peak memory	250780 kb
Host	smart-fc5d77dd-9fb8-423e-8240-b09ce67e7078
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544550214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2544550214
Directory	/workspace/8.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_stress_all.421679902
Short name	T629
Test name
Test status
Simulation time	16397439407 ps
CPU time	193.93 seconds
Started	Aug 11 07:05:44 PM PDT 24
Finished	Aug 11 07:08:58 PM PDT 24
Peak memory	280016 kb
Host	smart-11aa92f2-3b7c-4663-8207-16bab9572646
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421679902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all.421679902
Directory	/workspace/8.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.448810043
Short name	T181
Test name
Test status
Simulation time	37376952 ps
CPU time	0.84 seconds
Started	Aug 11 07:05:47 PM PDT 24
Finished	Aug 11 07:05:48 PM PDT 24
Peak memory	211680 kb
Host	smart-150c544e-b5fd-4280-a1ae-38e9c4b0f4bc
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448810043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr l_volatile_unlock_smoke.448810043
Directory	/workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_alert_test.3732727743
Short name	T715
Test name
Test status
Simulation time	38418254 ps
CPU time	0.81 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:05:50 PM PDT 24
Peak memory	208996 kb
Host	smart-90e9465b-7be8-4766-976c-51aed4ec2fa9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732727743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3732727743
Directory	/workspace/9.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.lc_ctrl_claim_transition_if.3364942551
Short name	T614
Test name
Test status
Simulation time	35267040 ps
CPU time	0.8 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:05:50 PM PDT 24
Peak memory	208892 kb
Host	smart-f1ea169d-e87e-4dfb-b743-a590ff4b3c7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3364942551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3364942551
Directory	/workspace/9.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/9.lc_ctrl_errors.3918841815
Short name	T838
Test name
Test status
Simulation time	1677304436 ps
CPU time	14.15 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:06:03 PM PDT 24
Peak memory	218100 kb
Host	smart-dcef8d45-2f85-4576-b70f-c3ada2639a13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918841815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3918841815
Directory	/workspace/9.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_access.1177497522
Short name	T554
Test name
Test status
Simulation time	769818113 ps
CPU time	10.38 seconds
Started	Aug 11 07:05:50 PM PDT 24
Finished	Aug 11 07:06:00 PM PDT 24
Peak memory	217292 kb
Host	smart-878263f3-0e07-4b00-97db-4460ed88e544
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177497522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1177497522
Directory	/workspace/9.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_errors.2540338698
Short name	T408
Test name
Test status
Simulation time	1356944504 ps
CPU time	44.55 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:06:34 PM PDT 24
Peak memory	218680 kb
Host	smart-e5276af9-9ef5-4159-8135-b958c75a47da
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540338698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er rors.2540338698
Directory	/workspace/9.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_priority.324924843
Short name	T738
Test name
Test status
Simulation time	452370922 ps
CPU time	6.46 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:05:56 PM PDT 24
Peak memory	217588 kb
Host	smart-c5b80714-6a6e-49d2-a68c-e2ea76aa76fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324924843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.324924843
Directory	/workspace/9.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1680125717
Short name	T564
Test name
Test status
Simulation time	558771533 ps
CPU time	16.5 seconds
Started	Aug 11 07:05:53 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	218008 kb
Host	smart-8cb30ea7-0b70-4f1f-a209-22b36065a8ec
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680125717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _prog_failure.1680125717
Directory	/workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.684261137
Short name	T526
Test name
Test status
Simulation time	947417502 ps
CPU time	12.37 seconds
Started	Aug 11 07:05:51 PM PDT 24
Finished	Aug 11 07:06:04 PM PDT 24
Peak memory	217424 kb
Host	smart-31cbd7d4-f072-4817-a577-995a1206db6b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684261137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j tag_regwen_during_op.684261137
Directory	/workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_smoke.1701294675
Short name	T83
Test name
Test status
Simulation time	328630404 ps
CPU time	4.23 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:05:54 PM PDT 24
Peak memory	217468 kb
Host	smart-c5e82ba0-7459-4d8f-b10f-89d82b13ff70
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701294675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke. 1701294675
Directory	/workspace/9.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2593226796
Short name	T343
Test name
Test status
Simulation time	15658654397 ps
CPU time	76.19 seconds
Started	Aug 11 07:05:54 PM PDT 24
Finished	Aug 11 07:07:10 PM PDT 24
Peak memory	283684 kb
Host	smart-2130dbdf-bc19-441b-b2f1-4a9b21888faf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593226796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta g_state_failure.2593226796
Directory	/workspace/9.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1474357584
Short name	T828
Test name
Test status
Simulation time	2207077327 ps
CPU time	23.04 seconds
Started	Aug 11 07:05:50 PM PDT 24
Finished	Aug 11 07:06:13 PM PDT 24
Peak memory	250940 kb
Host	smart-72048fe2-0512-4421-96ef-a6fc24a3056c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474357584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_state_post_trans.1474357584
Directory	/workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_prog_failure.3172371283
Short name	T686
Test name
Test status
Simulation time	49950825 ps
CPU time	2.9 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:05:52 PM PDT 24
Peak memory	218064 kb
Host	smart-274ed54b-e5ec-43e9-839d-baa07c4995a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172371283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3172371283
Directory	/workspace/9.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_regwen_during_op.443564454
Short name	T821
Test name
Test status
Simulation time	252870476 ps
CPU time	5.78 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:05:55 PM PDT 24
Peak memory	214376 kb
Host	smart-47aa5cd1-7d7e-4f29-ab06-5cc4aedfb832
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443564454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.443564454
Directory	/workspace/9.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_mubi.762555611
Short name	T700
Test name
Test status
Simulation time	4603577929 ps
CPU time	12.48 seconds
Started	Aug 11 07:05:48 PM PDT 24
Finished	Aug 11 07:06:00 PM PDT 24
Peak memory	218836 kb
Host	smart-3e93c411-831d-4a7d-bb59-fed941722b5d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762555611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.762555611
Directory	/workspace/9.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_digest.2474569182
Short name	T414
Test name
Test status
Simulation time	775792579 ps
CPU time	10.61 seconds
Started	Aug 11 07:05:51 PM PDT 24
Finished	Aug 11 07:06:02 PM PDT 24
Peak memory	217992 kb
Host	smart-bcd6b41d-c252-4767-9122-047d7fe34c23
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474569182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di gest.2474569182
Directory	/workspace/9.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_mux.2776566629
Short name	T858
Test name
Test status
Simulation time	287725216 ps
CPU time	9.86 seconds
Started	Aug 11 07:05:49 PM PDT 24
Finished	Aug 11 07:06:00 PM PDT 24
Peak memory	217976 kb
Host	smart-b443919e-a82e-4e92-82e2-16f6ce8e9893
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776566629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2 776566629
Directory	/workspace/9.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/9.lc_ctrl_security_escalation.2726158784
Short name	T474
Test name
Test status
Simulation time	205356790 ps
CPU time	6.67 seconds
Started	Aug 11 07:05:50 PM PDT 24
Finished	Aug 11 07:05:56 PM PDT 24
Peak memory	225928 kb
Host	smart-f3a5598f-cd25-4b11-9e97-575102b3fab4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726158784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2726158784
Directory	/workspace/9.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/9.lc_ctrl_smoke.879281148
Short name	T402
Test name
Test status
Simulation time	552994155 ps
CPU time	2.89 seconds
Started	Aug 11 07:05:45 PM PDT 24
Finished	Aug 11 07:05:48 PM PDT 24
Peak memory	214444 kb
Host	smart-094e25f2-9294-491d-8929-f1677a1c26c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879281148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.879281148
Directory	/workspace/9.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_failure.4045972963
Short name	T859
Test name
Test status
Simulation time	267038175 ps
CPU time	30.16 seconds
Started	Aug 11 07:05:50 PM PDT 24
Finished	Aug 11 07:06:21 PM PDT 24
Peak memory	250804 kb
Host	smart-207f3e10-0e58-4bf0-8252-a8d5c4993f68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045972963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4045972963
Directory	/workspace/9.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_post_trans.616219498
Short name	T240
Test name
Test status
Simulation time	48149562 ps
CPU time	2.8 seconds
Started	Aug 11 07:05:51 PM PDT 24
Finished	Aug 11 07:05:54 PM PDT 24
Peak memory	226236 kb
Host	smart-688ff491-2cba-45e4-a7b5-0f0b67c1425a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616219498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.616219498
Directory	/workspace/9.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all.3798831517
Short name	T507
Test name
Test status
Simulation time	769064799 ps
CPU time	19.75 seconds
Started	Aug 11 07:05:50 PM PDT 24
Finished	Aug 11 07:06:10 PM PDT 24
Peak memory	250816 kb
Host	smart-27d5706b-7ba0-4f00-bd87-fa113351ef47
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798831517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.3798831517
Directory	/workspace/9.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.563313768
Short name	T799
Test name
Test status
Simulation time	15097313 ps
CPU time	0.87 seconds
Started	Aug 11 07:05:45 PM PDT 24
Finished	Aug 11 07:05:46 PM PDT 24
Peak memory	211772 kb
Host	smart-cb387b69-463f-4287-bd04-ba36c93c7d47
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563313768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr l_volatile_unlock_smoke.563313768
Directory	/workspace/9.lc_ctrl_volatile_unlock_smoke/latest

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